URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

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```
/openrisc/tags/gdb/gdb-6.8/gdb-6.8.openrisc-2.1/sim/iq2000
```
from Rev 24 to Rev 33
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With Path: Rev

Rev 24 → Rev 33

/model.c

0,0 → 1,2569

model.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: ChangeLog =================================================================== --- ChangeLog (nonexistent) +++ ChangeLog (revision 33) @@ -0,0 +1,202 @@ +2006-12-21 Hans-Peter Nilsson + + * acconfig.h: Remove. + * config.in: Regenerate. + +2006-06-13 Richard Earnshaw + + * configure: Regenerated. + +2006-06-05 Daniel Jacobowitz + + * configure: Regenerated. + +2006-05-31 Daniel Jacobowitz + + * configure: Regenerated. + +2005-03-23 Mark Kettenis + + * configure: Regenerate. + +2005-02-21 Corinna Vinschen + + * iq2000.c: Eliminate need to include gdb/sim-iq2000.h. + +2005-02-18 Corinna Vinschen + + * configure.ac: Rename from configure.in and pull up to autoconf 2.59. + * configure: Regenerate. + +2002-03-18 Jeff Johnston + + * sem-switch.c: Regenerated. + * sem.c: Ditto. + +2002-01-28 Jeff Johnston + + * arch.c: Regenerated. + * arch.h: Ditto. + * cpu.c: Ditto. + * cpu.h: Ditto. + * cpuall.h: Ditto. + * decode.c: Ditto. + * decode.h: Ditto. + * model.c: Ditto. + * sem-switch.c: Ditto. + * sem.c: Ditto. + +2001-11-16 Jeff Johnston + + * decode.c: Regenerated after putting orui into machine-specific + files. + * decode.h: Ditto. + * model.c: Ditto. + * sem-switch.c: Ditto. + * sem.c: Ditto. + +2001-11-13 Jeff Johnston + + * cpu.h: Regenerated after changing jump and branch operands + so that no bit masking is performed. + * decode.c: Ditto. + * iq2000.c (get_h_pc): Change to return h_pc directly. + (set_h_pc): Change to always set the insn mask bit. + * sim-if.c (iq2000bf_disassemble_insn): Change to pass the + pc untouched. + (sim_create_inferior): Changed so starting address is taken + directly from link. If not specified, start address is + 0 with insn mask set on. + +2001-11-08 Jeff Johnston + + * cpu.h: Regenerated after making jump operand UINT. + * decode.c: Ditto. + +2001-10-31 Jeff Johnston + + * sem-switch.c: Regenerated after fixing lb, lbu, lh, lw, + sb, sh, and sw insns handling of offset operand. + * sem.c: Ditto. + +2001-10-30 Jeff Johnston + + * cpu.c: Regenerated. + * cpu.h: Ditto. + * decode.c: Ditto. + * sem-switch.c: Ditto. + * sem.c: Ditto. + * iq2000.c (get_h_pc): New routine. + (set_h_pc): Ditto. + (fetch_str): Translate cpu data addresses to data area. + (do_syscall): Ditto. + (iq2000bf_fetch_register): Use get_h_pc. + (iq2000bf_store_register): Use set_h_pc. + * mloop.in: Change all calls to GETIMEMxxx to use CPU2INSN + on the pc value passed first. + * sim-if.c (iq2000bf_disassemble_insn): New function. + (sim_open): Add extra memory region for insn memory vs data memory. + Also change disassembler to be iq2000bf_disassemble_insn. + (sim_create_inferior): Translate start address using INSN2CPU macro. + * sim-main.h (CPU2INSN, CPU2DATA, INSN2CPU, DATA2CPU): New macros + to translate between Harvard and cpu addresses. + +2001-10-26 Jeff Johnston + + * sem-switch.c: Regenerated after reverting addiu + change. + * sem.c: Ditto. + +2001-10-25 Jeff Johnston + + * Makefile.in: Add -UHAVE_CPU_IQ10 for time-being until + iq10 simulator merged here. + * cpu.h: Regenerated after fixing addiu insn. + * cpuall.h: Ditto. + * decode.c: Ditto. + * decode.h: Ditto. + * model.c: Ditto. + * sem-switch.c: Ditto. + * sem.c: Ditto. + +2001-09-12 Stan Cox + + * iq2000/{cpu.c, cpu.h, decode.c, decode.h, model.c, sem-switch.c, + sem.c}: Regen'd. + * iq2000.c (do_syscall): Support system traps. + +2001-07-05 Ben Elliston + + * Makefile.in (stamp-arch): Use $(CGEN_CPU_DIR). + (stamp-cpu): Likewise. + +2001-04-02 Ben Elliston + + * arch.c, arch.h: Regnerate to track recent cgen improvements. + * cpu.c, cpu.h, cpuall.h, decode.c, decode.h: Likewise. + * model.c, sem-switch.c, sem.c: Likewise. + +2001-01-22 Ben Elliston + + * cpu.h, decode.c, decode.h, model.c: Regenerate. + * sem.c, sem-switch.c: Likewise. + + * arch.c, arch.h, cpu.c, cpu.h, cpuall.h: Regenerate. + * decode.c, decode.h, model.c, sem.c, sem-switch.c: Likewise. + +2000-07-05 Ben Elliston + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +2000-07-04 Ben Elliston + + * sem.c, sem-switch.c: Regenerate. + + * iq2000.c (do_break): Use sim_engine_halt (). + * arch.c, decode.c, decode.h, sem.c, sem-switch.c: Regenerate. + +2000-07-03 Ben Elliston + + * iq2000.c (do_syscall): Examine syscall register (nominally %11). + (do_break): Handle breakpoints. + * tconfig.in (SIM_HAVE_BREAKPOINTS): Define. + (SIM_BREAKPOINT, SIM_BREAKPOINT_SIZE): Likewise. + +2000-06-29 Andrew Cagney + + * iq2000.c (iq2000bf_fetch_register): Implement. + (iq2000bf_store_register): Ditto. + +2000-05-17 Ben Elliston + + * mloop.in (extract-simple, extract-scache): Use SEM_SKIP_COMPILE + to set the skip count for the (skip ..) rtx. + (extract-pbb): Likewise. + (extract-pbb): Include the delay slot instruction of all CTI + instructions in the pbb, not just those that may nullify their + delay slot (eg. likely branches). + + * sem.c, sem-switch.c: Regenerate. + +2000-05-16 Ben Elliston + + * arch.c, cpu.c, cpu.h, decode.c, decode.h: Regenerate. + * sem.c, sem-switch.c: Likewise. + * mloop.in (extract-pbb): Prohibit branch instructions in the + delay slot of branch likely instructions. + +2000-05-16 Ben Elliston + + * Makefile.in: New file. + * configure.in: Ditto. + * acconfig.h: Ditto. + * config.in, configure: Generate. + * arch.c, arch.h, cpu.c, cpu.h, cpuall.h: Ditto. + * decode.c, decode.h: Ditto. + * model.c, sem-switch.c, sem.c: Ditto. + * mloop.in: New file. + * iq2000.c: Ditto. + * iq2000-sim.h: Ditto. + * sim-if.c: Ditto. + * sim-main.h: Ditto. + * tconfig.in: Ditto

ChangeLog Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: iq2000-sim.h =================================================================== --- iq2000-sim.h (nonexistent) +++ iq2000-sim.h (revision 33) @@ -0,0 +1,34 @@ +/* collection of junk waiting time to sort out + Copyright (C) 1998, 1999, 2007, 2008 Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + +This file is part of the GNU Simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +#ifndef IQ2000_SIM_H +#define IQ2000_SIM_H + +#define GETTWI GETTSI +#define SETTWI SETTSI + + +/* Hardware/device support. +/* sim_core_attach device argument. */ +extern device iq2000_devices; + +/* FIXME: Temporary, until device support ready. */ +struct _device { int foo; }; + +#endif /* IQ2000_SIM_H */

iq2000-sim.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: mloop.in =================================================================== --- mloop.in (nonexistent) +++ mloop.in (revision 33) @@ -0,0 +1,243 @@ +# Simulator main loop for IQ2000. -*- C -*- +# Copyright (C) 1998, 1999, 2007, 2008 Free Software Foundation, Inc. +# Contributed by Cygnus Solutions. +# +# This file is part of the GNU Simulators. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# Syntax: +# /bin/sh mainloop.in command +# +# Command is one of: +# +# init +# support +# extract-{simple,scache,pbb} +# {full,fast}-exec-{simple,scache,pbb} +# +# A target need only provide a "full" version of one of simple,scache,pbb. +# If the target wants it can also provide a fast version of same. +# It can't provide more than this, however for illustration's sake the IQ2000 +# port provides examples of all. + +# ??? After a few more ports are done, revisit. +# Will eventually need to machine generate a lot of this. + +case "x$1" in + +xsupport) + +cat <argbuf.semantic.sem_fast) (current_cpu, sc); +#else + vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf); +#endif +#else + abort (); +#endif /* WITH_SEM_SWITCH_FAST */ + } + else + { +#if ! WITH_SEM_SWITCH_FULL + ARGBUF *abuf = &sc->argbuf; + const IDESC *idesc = abuf->idesc; +#if WITH_SCACHE_PBB + int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL); +#else + int virtual_p = 0; +#endif + + if (! virtual_p) + { + /* FIXME: call x-before */ + if (ARGBUF_PROFILE_P (abuf)) + PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num); + /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */ + if (PROFILE_MODEL_P (current_cpu) + && ARGBUF_PROFILE_P (abuf)) + @cpu@_model_insn_before (current_cpu, 1 /*first_p*/); + TRACE_INSN_INIT (current_cpu, abuf, 1); + TRACE_INSN (current_cpu, idesc->idata, + (const struct argbuf *) abuf, abuf->addr); + } +#if WITH_SCACHE + vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc); +#else + vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf); +#endif + if (! virtual_p) + { + /* FIXME: call x-after */ + if (PROFILE_MODEL_P (current_cpu) + && ARGBUF_PROFILE_P (abuf)) + { + int cycles; + + cycles = (*idesc->timing->model_fn) (current_cpu, sc); + @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles); + } + TRACE_INSN_FINI (current_cpu, abuf, 1); + } +#else + abort (); +#endif /* WITH_SEM_SWITCH_FULL */ + } + + return vpc; +} + +EOF +;; + +xinit) +;; + +xextract-simple | xextract-scache) + +# Inputs: current_cpu, vpc, sc, FAST_P +# Outputs: sc filled in + +cat < 0) + { + USI insn = GETIMEMUSI (current_cpu, CPU2INSN(pc)); + + idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P); + SEM_SKIP_COMPILE (current_cpu, sc, 1); + ++sc; + --max_insns; + ++icount; + pc += idesc->length; + + if (IDESC_CTI_P (idesc)) + { + /* Likely branches annul their delay slot if the branch is + not taken by using the (skip ..) rtx. We'll rely on + that. */ + likely_cti = (IDESC_SKIP_P (idesc)); + + SET_CTI_VPC (sc - 1); + + if (CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT)) + { + USI insn = GETIMEMUSI (current_cpu, CPU2INSN(pc)); + idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P); + + if (likely_cti && IDESC_CTI_P (idesc)) + { + /* malformed program */ + sim_io_eprintf (CPU_STATE (current_cpu), + "malformed program, \`%s' insn in branch likely delay slot\n", + CGEN_INSN_NAME (idesc->idata)); + } + else + { + ++sc; + --max_insns; + ++icount; + pc += idesc->length; + } + } + break; + } + } + + Finish: + SET_INSN_COUNT (icount); +} +EOF + +;; + +xfull-exec-* | xfast-exec-*) + +# Inputs: current_cpu, sc, FAST_P +# Outputs: vpc +# vpc contains the address of the next insn to execute + +cat <&2 + exit 1 + ;; + +esac Index: iq2000.c =================================================================== --- iq2000.c (nonexistent) +++ iq2000.c (revision 33) @@ -0,0 +1,266 @@ +/* IQ2000 simulator support code + Copyright (C) 2000, 2004, 2007, 2008 Free Software Foundation, Inc. + Contributed by Cygnus Support. + + This file is part of the GNU simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#define WANT_CPU +#define WANT_CPU_IQ2000BF + +#include "sim-main.h" +#include "cgen-mem.h" +#include "cgen-ops.h" + +enum +{ + GPR0_REGNUM = 0, + NR_GPR = 32, + PC_REGNUM = 32 +}; + +enum libgloss_syscall +{ + SYS_exit = 1, + SYS_open = 2, + SYS_close = 3, + SYS_read = 4, + SYS_write = 5, + SYS_lseek = 6, + SYS_unlink = 7, + SYS_getpid = 8, + SYS_kill = 9, + SYS_fstat = 10, + SYS_argvlen = 12, + SYS_argv = 13, + SYS_chdir = 14, + SYS_stat = 15, + SYS_chmod = 16, + SYS_utime = 17, + SYS_time = 18, + SYS_gettimeofday = 19, + SYS_times = 20 +}; + +/* Read a null terminated string from memory, return in a buffer */ +static char * +fetch_str (current_cpu, pc, addr) + SIM_CPU *current_cpu; + PCADDR pc; + DI addr; +{ + char *buf; + int nr = 0; + while (sim_core_read_1 (current_cpu, + pc, read_map, CPU2DATA(addr + nr)) != 0) + nr++; + buf = NZALLOC (char, nr + 1); + sim_read (CPU_STATE (current_cpu), CPU2DATA(addr), buf, nr); + return buf; +} + +void +do_syscall (SIM_CPU *current_cpu, PCADDR pc) +{ +#if 0 + int syscall = H2T_4 (iq2000bf_h_gr_get (current_cpu, 11)); +#endif + int syscall_function = iq2000bf_h_gr_get (current_cpu, 4); + int i; + char *buf; + int PARM1 = iq2000bf_h_gr_get (current_cpu, 5); + int PARM2 = iq2000bf_h_gr_get (current_cpu, 6); + int PARM3 = iq2000bf_h_gr_get (current_cpu, 7); + const int ret_reg = 2; + + switch (syscall_function) + { + case 0: + switch (H2T_4 (iq2000bf_h_gr_get (current_cpu, 11))) + { + case 0: + /* Pass. */ + puts ("pass"); + exit (0); + case 1: + /* Fail. */ + puts ("fail"); + exit (1); + } + + case SYS_write: + buf = zalloc (PARM3); + sim_read (CPU_STATE (current_cpu), CPU2DATA(PARM2), buf, PARM3); + SET_H_GR (ret_reg, + sim_io_write (CPU_STATE (current_cpu), + PARM1, buf, PARM3)); + zfree (buf); + break; + + case SYS_lseek: + SET_H_GR (ret_reg, + sim_io_lseek (CPU_STATE (current_cpu), + PARM1, PARM2, PARM3)); + break; + + case SYS_exit: + sim_engine_halt (CPU_STATE (current_cpu), current_cpu, + NULL, pc, sim_exited, PARM1); + break; + + case SYS_read: + buf = zalloc (PARM3); + SET_H_GR (ret_reg, + sim_io_read (CPU_STATE (current_cpu), + PARM1, buf, PARM3)); + sim_write (CPU_STATE (current_cpu), CPU2DATA(PARM2), buf, PARM3); + zfree (buf); + break; + + case SYS_open: + buf = fetch_str (current_cpu, pc, PARM1); + SET_H_GR (ret_reg, + sim_io_open (CPU_STATE (current_cpu), + buf, PARM2)); + zfree (buf); + break; + + case SYS_close: + SET_H_GR (ret_reg, + sim_io_close (CPU_STATE (current_cpu), PARM1)); + break; + + case SYS_time: + SET_H_GR (ret_reg, time (0)); + break; + + default: + SET_H_GR (ret_reg, -1); + } +} + +void +do_break (SIM_CPU *current_cpu, PCADDR pc) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); +} + +/* The semantic code invokes this for invalid (unrecognized) instructions. */ + +SEM_PC +sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc) +{ + SIM_DESC sd = CPU_STATE (current_cpu); + sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL); + + return vpc; +} + + +/* Process an address exception. */ + +void +iq2000_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia, + unsigned int map, int nr_bytes, address_word addr, + transfer_type transfer, sim_core_signals sig) +{ + sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr, + transfer, sig); +} + + +/* Initialize cycle counting for an insn. + FIRST_P is non-zero if this is the first insn in a set of parallel + insns. */ + +void +iq2000bf_model_insn_before (SIM_CPU *cpu, int first_p) +{ + /* Do nothing. */ +} + + +/* Record the cycles computed for an insn. + LAST_P is non-zero if this is the last insn in a set of parallel insns, + and we update the total cycle count. + CYCLES is the cycle count of the insn. */ + +void +iq2000bf_model_insn_after(SIM_CPU *cpu, int last_p, int cycles) +{ + /* Do nothing. */ +} + + +int +iq2000bf_model_iq2000_u_exec (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + return idesc->timing->units[unit_num].done; +} + +PCADDR +get_h_pc (SIM_CPU *cpu) +{ + return CPU_CGEN_HW(cpu)->h_pc; +} + +void +set_h_pc (SIM_CPU *cpu, PCADDR addr) +{ + CPU_CGEN_HW(cpu)->h_pc = addr | IQ2000_INSN_MASK; +} + +int +iq2000bf_fetch_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len) +{ + if (nr >= GPR0_REGNUM + && nr < (GPR0_REGNUM + NR_GPR) + && len == 4) + { + *((unsigned32*)buf) = + H2T_4 (iq2000bf_h_gr_get (cpu, nr - GPR0_REGNUM)); + return 4; + } + else if (nr == PC_REGNUM + && len == 4) + { + *((unsigned32*)buf) = H2T_4 (get_h_pc (cpu)); + return 4; + } + else + return 0; +} + +int +iq2000bf_store_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len) +{ + if (nr >= GPR0_REGNUM + && nr < (GPR0_REGNUM + NR_GPR) + && len == 4) + { + iq2000bf_h_gr_set (cpu, nr - GPR0_REGNUM, T2H_4 (*((unsigned32*)buf))); + return 4; + } + else if (nr == PC_REGNUM + && len == 4) + { + set_h_pc (cpu, T2H_4 (*((unsigned32*)buf))); + return 4; + } + else + return 0; +}

iq2000.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: tconfig.in =================================================================== --- tconfig.in (nonexistent) +++ tconfig.in (revision 33) @@ -0,0 +1,42 @@ +/* IQ2000 target configuration file. -*- C -*- */ + +/* Define this if the simulator can vary the size of memory. + See the xxx simulator for an example. + This enables the `-m size' option. + The memory size is stored in STATE_MEM_SIZE. */ +/* Not used for IQ2000 since we use the memory module. TODO -- check this */ +/* #define SIM_HAVE_MEM_SIZE */ + +/* See sim-hload.c. We properly handle LMA. -- TODO: check this */ +#define SIM_HANDLES_LMA 1 + +/* For MSPR support. FIXME: revisit. */ +#define WITH_DEVICES 0 + +/* FIXME: Revisit. */ +#ifdef HAVE_DV_SOCKSER +MODULE_INSTALL_FN dv_sockser_install; +#define MODULE_LIST dv_sockser_install, +#endif + +#if 0 +/* Enable watchpoints. */ +#define WITH_WATCHPOINTS 1 +#endif + +/* ??? Temporary hack until model support unified. */ +#define SIM_HAVE_MODEL + +/* Define this to enable the intrinsic breakpoint mechanism. */ +/* FIXME: may be able to remove SIM_HAVE_BREAKPOINTS since it essentially + duplicates ifdef SIM_BREAKPOINT (right?) */ +#if 1 +#define SIM_HAVE_BREAKPOINTS +#define SIM_BREAKPOINT { 0, 0, 0, 0xD } +#define SIM_BREAKPOINT_SIZE 4 +#endif + +/* This is a global setting. Different cpu families can't mix-n-match -scache + and -pbb. However some cpu families may use -simple while others use + one of -scache/-pbb. ???? */ +#define WITH_SCACHE_PBB 1 Index: arch.c =================================================================== --- arch.c (nonexistent) +++ arch.c (revision 33) @@ -0,0 +1,34 @@ +/* Simulator support for iq2000. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +*/ + +#include "sim-main.h" +#include "bfd.h" + +const MACH *sim_machs[] = +{ +#ifdef HAVE_CPU_IQ2000BF + & iq2000_mach, +#endif + 0 +}; +

arch.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: sim-main.h =================================================================== --- sim-main.h (nonexistent) +++ sim-main.h (revision 33) @@ -0,0 +1,84 @@ + +/* Main header for the Vitesse IQ2000. */ + +#ifndef SIM_MAIN_H +#define SIM_MAIN_H + +#define USING_SIM_BASE_H /* FIXME: quick hack */ + +struct _sim_cpu; /* FIXME: should be in sim-basics.h */ +typedef struct _sim_cpu SIM_CPU; + +/* sim-basics.h includes config.h but cgen-types.h must be included before + sim-basics.h and cgen-types.h needs config.h. */ +#include "config.h" + +#include "symcat.h" +#include "sim-basics.h" +#include "cgen-types.h" +#include "iq2000-desc.h" +#include "iq2000-opc.h" +#include "arch.h" + +/* Pull in IQ2000_{DATA,INSN}_{MASK,VALUE}. */ +#include "elf/iq2000.h" + +/* These must be defined before sim-base.h. */ +typedef USI sim_cia; + +#define CIA_GET(cpu) CPU_PC_GET (cpu) +#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val)) + +#include "sim-base.h" +#include "cgen-sim.h" +#include "iq2000-sim.h" + +/* The _sim_cpu struct. */ + +struct _sim_cpu { + /* sim/common cpu base. */ + sim_cpu_base base; + + /* Static parts of cgen. */ + CGEN_CPU cgen_cpu; + + /* CPU specific parts go here. + Note that in files that don't need to access these pieces WANT_CPU_FOO + won't be defined and thus these parts won't appear. This is ok in the + sense that things work. It is a source of bugs though. + One has to of course be careful to not take the size of this + struct and no structure members accessed in non-cpu specific files can + go after here. Oh for a better language. */ +#if defined (WANT_CPU_IQ2000BF) + IQ2000BF_CPU_DATA cpu_data; +#endif +}; + +/* The sim_state struct. */ + +struct sim_state { + sim_cpu *cpu; +#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu) + + CGEN_STATE cgen_state; + + sim_state_base base; +}; + +/* Misc. */ + +/* Catch address exceptions. */ +extern SIM_CORE_SIGNAL_FN iq2000_core_signal; +#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ +iq2000_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \ + (TRANSFER), (ERROR)) + +/* Convert between CPU-internal addresses and sim_core addresses. */ +#define CPU2DATA(addr) (IQ2000_DATA_VALUE + (addr)) +#define DATA2CPU(addr) ((addr) - IQ2000_DATA_VALUE) +#define CPU2INSN(addr) (IQ2000_INSN_VALUE + ((addr) & ~IQ2000_INSN_MASK)) +#define INSN2CPU(addr) ((addr) - IQ2000_INSN_VALUE) +#define IQ2000_INSN_MEM_SIZE (CPU2INSN(0x800000) - CPU2INSN(0x0000)) +#define IQ2000_DATA_MEM_SIZE (CPU2DATA(0x800000) - CPU2DATA(0x0000)) + +#endif /* SIM_MAIN_H */

sim-main.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: arch.h =================================================================== --- arch.h (nonexistent) +++ arch.h (revision 33) @@ -0,0 +1,43 @@ +/* Simulator header for iq2000. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +*/ + +#ifndef IQ2000_ARCH_H +#define IQ2000_ARCH_H + +#define TARGET_BIG_ENDIAN 1 + +/* Enum declaration for model types. */ +typedef enum model_type { + MODEL_IQ2000, MODEL_MAX +} MODEL_TYPE; + +#define MAX_MODELS ((int) MODEL_MAX) + +/* Enum declaration for unit types. */ +typedef enum unit_type { + UNIT_NONE, UNIT_IQ2000_U_EXEC, UNIT_MAX +} UNIT_TYPE; + +#define MAX_UNITS (1) + +#endif /* IQ2000_ARCH_H */

arch.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: configure.ac =================================================================== --- configure.ac (nonexistent) +++ configure.ac (revision 33) @@ -0,0 +1,21 @@ +dnl Process this file with autoconf to produce a configure script. +AC_PREREQ(2.59)dnl +AC_INIT(Makefile.in) +AC_CONFIG_HEADER(config.h:config.in) + +sinclude(../common/aclocal.m4) + +# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around +# it by inlining the macro's contents. +sinclude(../common/common.m4) + +SIM_AC_OPTION_ENDIAN(BIG_ENDIAN) +SIM_AC_OPTION_ALIGNMENT(STRICT_ALIGNMENT) +SIM_AC_OPTION_HOSTENDIAN +SIM_AC_OPTION_SCACHE(16384) +SIM_AC_OPTION_DEFAULT_MODEL(iq2000) +SIM_AC_OPTION_ENVIRONMENT +SIM_AC_OPTION_INLINE() +SIM_AC_OPTION_CGEN_MAINT + +SIM_AC_OUTPUT

configure.ac Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: decode.c =================================================================== --- decode.c (nonexistent) +++ decode.c (revision 33) @@ -0,0 +1,1296 @@ +/* Simulator instruction decoder for iq2000bf. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +*/ + +#define WANT_CPU iq2000bf +#define WANT_CPU_IQ2000BF + +#include "sim-main.h" +#include "sim-assert.h" + +/* The instruction descriptor array. + This is computed at runtime. Space for it is not malloc'd to save a + teensy bit of cpu in the decoder. Moving it to malloc space is trivial + but won't be done until necessary (we don't currently support the runtime + addition of instructions nor an SMP machine with different cpus). */ +static IDESC iq2000bf_insn_data[IQ2000BF_INSN_BMB + 1]; + +/* Commas between elements are contained in the macros. + Some of these are conditionally compiled out. */ + +static const struct insn_sem iq2000bf_insn_sem[] = +{ + { VIRTUAL_INSN_X_INVALID, IQ2000BF_INSN_X_INVALID, IQ2000BF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_AFTER, IQ2000BF_INSN_X_AFTER, IQ2000BF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_BEFORE, IQ2000BF_INSN_X_BEFORE, IQ2000BF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_CTI_CHAIN, IQ2000BF_INSN_X_CTI_CHAIN, IQ2000BF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_CHAIN, IQ2000BF_INSN_X_CHAIN, IQ2000BF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_BEGIN, IQ2000BF_INSN_X_BEGIN, IQ2000BF_SFMT_EMPTY }, + { IQ2000_INSN_ADD, IQ2000BF_INSN_ADD, IQ2000BF_SFMT_ADD }, + { IQ2000_INSN_ADDI, IQ2000BF_INSN_ADDI, IQ2000BF_SFMT_ADDI }, + { IQ2000_INSN_ADDIU, IQ2000BF_INSN_ADDIU, IQ2000BF_SFMT_ADDI }, + { IQ2000_INSN_ADDU, IQ2000BF_INSN_ADDU, IQ2000BF_SFMT_ADD }, + { IQ2000_INSN_ADO16, IQ2000BF_INSN_ADO16, IQ2000BF_SFMT_ADO16 }, + { IQ2000_INSN_AND, IQ2000BF_INSN_AND, IQ2000BF_SFMT_ADD }, + { IQ2000_INSN_ANDI, IQ2000BF_INSN_ANDI, IQ2000BF_SFMT_ADDI }, + { IQ2000_INSN_ANDOI, IQ2000BF_INSN_ANDOI, IQ2000BF_SFMT_ADDI }, + { IQ2000_INSN_NOR, IQ2000BF_INSN_NOR, IQ2000BF_SFMT_ADD }, + { IQ2000_INSN_OR, IQ2000BF_INSN_OR, IQ2000BF_SFMT_ADD }, + { IQ2000_INSN_ORI, IQ2000BF_INSN_ORI, IQ2000BF_SFMT_ADDI }, + { IQ2000_INSN_RAM, IQ2000BF_INSN_RAM, IQ2000BF_SFMT_RAM }, + { IQ2000_INSN_SLL, IQ2000BF_INSN_SLL, IQ2000BF_SFMT_SLL }, + { IQ2000_INSN_SLLV, IQ2000BF_INSN_SLLV, IQ2000BF_SFMT_ADD }, + { IQ2000_INSN_SLMV, IQ2000BF_INSN_SLMV, IQ2000BF_SFMT_SLMV }, + { IQ2000_INSN_SLT, IQ2000BF_INSN_SLT, IQ2000BF_SFMT_SLT }, + { IQ2000_INSN_SLTI, IQ2000BF_INSN_SLTI, IQ2000BF_SFMT_SLTI }, + { IQ2000_INSN_SLTIU, IQ2000BF_INSN_SLTIU, IQ2000BF_SFMT_SLTI }, + { IQ2000_INSN_SLTU, IQ2000BF_INSN_SLTU, IQ2000BF_SFMT_SLT }, + { IQ2000_INSN_SRA, IQ2000BF_INSN_SRA, IQ2000BF_SFMT_SLL }, + { IQ2000_INSN_SRAV, IQ2000BF_INSN_SRAV, IQ2000BF_SFMT_ADD }, + { IQ2000_INSN_SRL, IQ2000BF_INSN_SRL, IQ2000BF_SFMT_SLL }, + { IQ2000_INSN_SRLV, IQ2000BF_INSN_SRLV, IQ2000BF_SFMT_ADD }, + { IQ2000_INSN_SRMV, IQ2000BF_INSN_SRMV, IQ2000BF_SFMT_SLMV }, + { IQ2000_INSN_SUB, IQ2000BF_INSN_SUB, IQ2000BF_SFMT_ADD }, + { IQ2000_INSN_SUBU, IQ2000BF_INSN_SUBU, IQ2000BF_SFMT_ADD }, + { IQ2000_INSN_XOR, IQ2000BF_INSN_XOR, IQ2000BF_SFMT_ADD }, + { IQ2000_INSN_XORI, IQ2000BF_INSN_XORI, IQ2000BF_SFMT_ADDI }, + { IQ2000_INSN_BBI, IQ2000BF_INSN_BBI, IQ2000BF_SFMT_BBI }, + { IQ2000_INSN_BBIN, IQ2000BF_INSN_BBIN, IQ2000BF_SFMT_BBI }, + { IQ2000_INSN_BBV, IQ2000BF_INSN_BBV, IQ2000BF_SFMT_BBV }, + { IQ2000_INSN_BBVN, IQ2000BF_INSN_BBVN, IQ2000BF_SFMT_BBV }, + { IQ2000_INSN_BEQ, IQ2000BF_INSN_BEQ, IQ2000BF_SFMT_BBV }, + { IQ2000_INSN_BEQL, IQ2000BF_INSN_BEQL, IQ2000BF_SFMT_BBV }, + { IQ2000_INSN_BGEZ, IQ2000BF_INSN_BGEZ, IQ2000BF_SFMT_BGEZ }, + { IQ2000_INSN_BGEZAL, IQ2000BF_INSN_BGEZAL, IQ2000BF_SFMT_BGEZAL }, + { IQ2000_INSN_BGEZALL, IQ2000BF_INSN_BGEZALL, IQ2000BF_SFMT_BGEZAL }, + { IQ2000_INSN_BGEZL, IQ2000BF_INSN_BGEZL, IQ2000BF_SFMT_BGEZ }, + { IQ2000_INSN_BLTZ, IQ2000BF_INSN_BLTZ, IQ2000BF_SFMT_BGEZ }, + { IQ2000_INSN_BLTZL, IQ2000BF_INSN_BLTZL, IQ2000BF_SFMT_BGEZ }, + { IQ2000_INSN_BLTZAL, IQ2000BF_INSN_BLTZAL, IQ2000BF_SFMT_BGEZAL }, + { IQ2000_INSN_BLTZALL, IQ2000BF_INSN_BLTZALL, IQ2000BF_SFMT_BGEZAL }, + { IQ2000_INSN_BMB0, IQ2000BF_INSN_BMB0, IQ2000BF_SFMT_BBV }, + { IQ2000_INSN_BMB1, IQ2000BF_INSN_BMB1, IQ2000BF_SFMT_BBV }, + { IQ2000_INSN_BMB2, IQ2000BF_INSN_BMB2, IQ2000BF_SFMT_BBV }, + { IQ2000_INSN_BMB3, IQ2000BF_INSN_BMB3, IQ2000BF_SFMT_BBV }, + { IQ2000_INSN_BNE, IQ2000BF_INSN_BNE, IQ2000BF_SFMT_BBV }, + { IQ2000_INSN_BNEL, IQ2000BF_INSN_BNEL, IQ2000BF_SFMT_BBV }, + { IQ2000_INSN_JALR, IQ2000BF_INSN_JALR, IQ2000BF_SFMT_JALR }, + { IQ2000_INSN_JR, IQ2000BF_INSN_JR, IQ2000BF_SFMT_JR }, + { IQ2000_INSN_LB, IQ2000BF_INSN_LB, IQ2000BF_SFMT_LB }, + { IQ2000_INSN_LBU, IQ2000BF_INSN_LBU, IQ2000BF_SFMT_LB }, + { IQ2000_INSN_LH, IQ2000BF_INSN_LH, IQ2000BF_SFMT_LH }, + { IQ2000_INSN_LHU, IQ2000BF_INSN_LHU, IQ2000BF_SFMT_LH }, + { IQ2000_INSN_LUI, IQ2000BF_INSN_LUI, IQ2000BF_SFMT_LUI }, + { IQ2000_INSN_LW, IQ2000BF_INSN_LW, IQ2000BF_SFMT_LW }, + { IQ2000_INSN_SB, IQ2000BF_INSN_SB, IQ2000BF_SFMT_SB }, + { IQ2000_INSN_SH, IQ2000BF_INSN_SH, IQ2000BF_SFMT_SH }, + { IQ2000_INSN_SW, IQ2000BF_INSN_SW, IQ2000BF_SFMT_SW }, + { IQ2000_INSN_BREAK, IQ2000BF_INSN_BREAK, IQ2000BF_SFMT_BREAK }, + { IQ2000_INSN_SYSCALL, IQ2000BF_INSN_SYSCALL, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_ANDOUI, IQ2000BF_INSN_ANDOUI, IQ2000BF_SFMT_ANDOUI }, + { IQ2000_INSN_ORUI, IQ2000BF_INSN_ORUI, IQ2000BF_SFMT_ANDOUI }, + { IQ2000_INSN_BGTZ, IQ2000BF_INSN_BGTZ, IQ2000BF_SFMT_BGEZ }, + { IQ2000_INSN_BGTZL, IQ2000BF_INSN_BGTZL, IQ2000BF_SFMT_BGEZ }, + { IQ2000_INSN_BLEZ, IQ2000BF_INSN_BLEZ, IQ2000BF_SFMT_BGEZ }, + { IQ2000_INSN_BLEZL, IQ2000BF_INSN_BLEZL, IQ2000BF_SFMT_BGEZ }, + { IQ2000_INSN_MRGB, IQ2000BF_INSN_MRGB, IQ2000BF_SFMT_MRGB }, + { IQ2000_INSN_BCTXT, IQ2000BF_INSN_BCTXT, IQ2000BF_SFMT_BCTXT }, + { IQ2000_INSN_BC0F, IQ2000BF_INSN_BC0F, IQ2000BF_SFMT_BCTXT }, + { IQ2000_INSN_BC0FL, IQ2000BF_INSN_BC0FL, IQ2000BF_SFMT_BCTXT }, + { IQ2000_INSN_BC3F, IQ2000BF_INSN_BC3F, IQ2000BF_SFMT_BCTXT }, + { IQ2000_INSN_BC3FL, IQ2000BF_INSN_BC3FL, IQ2000BF_SFMT_BCTXT }, + { IQ2000_INSN_BC0T, IQ2000BF_INSN_BC0T, IQ2000BF_SFMT_BCTXT }, + { IQ2000_INSN_BC0TL, IQ2000BF_INSN_BC0TL, IQ2000BF_SFMT_BCTXT }, + { IQ2000_INSN_BC3T, IQ2000BF_INSN_BC3T, IQ2000BF_SFMT_BCTXT }, + { IQ2000_INSN_BC3TL, IQ2000BF_INSN_BC3TL, IQ2000BF_SFMT_BCTXT }, + { IQ2000_INSN_CFC0, IQ2000BF_INSN_CFC0, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_CFC1, IQ2000BF_INSN_CFC1, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_CFC2, IQ2000BF_INSN_CFC2, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_CFC3, IQ2000BF_INSN_CFC3, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_CHKHDR, IQ2000BF_INSN_CHKHDR, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_CTC0, IQ2000BF_INSN_CTC0, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_CTC1, IQ2000BF_INSN_CTC1, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_CTC2, IQ2000BF_INSN_CTC2, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_CTC3, IQ2000BF_INSN_CTC3, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_JCR, IQ2000BF_INSN_JCR, IQ2000BF_SFMT_BCTXT }, + { IQ2000_INSN_LUC32, IQ2000BF_INSN_LUC32, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_LUC32L, IQ2000BF_INSN_LUC32L, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_LUC64, IQ2000BF_INSN_LUC64, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_LUC64L, IQ2000BF_INSN_LUC64L, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_LUK, IQ2000BF_INSN_LUK, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_LULCK, IQ2000BF_INSN_LULCK, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_LUM32, IQ2000BF_INSN_LUM32, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_LUM32L, IQ2000BF_INSN_LUM32L, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_LUM64, IQ2000BF_INSN_LUM64, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_LUM64L, IQ2000BF_INSN_LUM64L, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_LUR, IQ2000BF_INSN_LUR, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_LURL, IQ2000BF_INSN_LURL, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_LUULCK, IQ2000BF_INSN_LUULCK, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_MFC0, IQ2000BF_INSN_MFC0, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_MFC1, IQ2000BF_INSN_MFC1, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_MFC2, IQ2000BF_INSN_MFC2, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_MFC3, IQ2000BF_INSN_MFC3, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_MTC0, IQ2000BF_INSN_MTC0, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_MTC1, IQ2000BF_INSN_MTC1, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_MTC2, IQ2000BF_INSN_MTC2, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_MTC3, IQ2000BF_INSN_MTC3, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_PKRL, IQ2000BF_INSN_PKRL, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_PKRLR1, IQ2000BF_INSN_PKRLR1, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_PKRLR30, IQ2000BF_INSN_PKRLR30, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_RB, IQ2000BF_INSN_RB, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_RBR1, IQ2000BF_INSN_RBR1, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_RBR30, IQ2000BF_INSN_RBR30, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_RFE, IQ2000BF_INSN_RFE, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_RX, IQ2000BF_INSN_RX, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_RXR1, IQ2000BF_INSN_RXR1, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_RXR30, IQ2000BF_INSN_RXR30, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_SLEEP, IQ2000BF_INSN_SLEEP, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_SRRD, IQ2000BF_INSN_SRRD, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_SRRDL, IQ2000BF_INSN_SRRDL, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_SRULCK, IQ2000BF_INSN_SRULCK, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_SRWR, IQ2000BF_INSN_SRWR, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_SRWRU, IQ2000BF_INSN_SRWRU, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_TRAPQFL, IQ2000BF_INSN_TRAPQFL, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_TRAPQNE, IQ2000BF_INSN_TRAPQNE, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_TRAPREL, IQ2000BF_INSN_TRAPREL, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_WB, IQ2000BF_INSN_WB, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_WBU, IQ2000BF_INSN_WBU, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_WBR1, IQ2000BF_INSN_WBR1, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_WBR1U, IQ2000BF_INSN_WBR1U, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_WBR30, IQ2000BF_INSN_WBR30, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_WBR30U, IQ2000BF_INSN_WBR30U, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_WX, IQ2000BF_INSN_WX, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_WXU, IQ2000BF_INSN_WXU, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_WXR1, IQ2000BF_INSN_WXR1, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_WXR1U, IQ2000BF_INSN_WXR1U, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_WXR30, IQ2000BF_INSN_WXR30, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_WXR30U, IQ2000BF_INSN_WXR30U, IQ2000BF_SFMT_SYSCALL }, + { IQ2000_INSN_LDW, IQ2000BF_INSN_LDW, IQ2000BF_SFMT_LDW }, + { IQ2000_INSN_SDW, IQ2000BF_INSN_SDW, IQ2000BF_SFMT_SDW }, + { IQ2000_INSN_J, IQ2000BF_INSN_J, IQ2000BF_SFMT_J }, + { IQ2000_INSN_JAL, IQ2000BF_INSN_JAL, IQ2000BF_SFMT_JAL }, + { IQ2000_INSN_BMB, IQ2000BF_INSN_BMB, IQ2000BF_SFMT_BBV }, +}; + +static const struct insn_sem iq2000bf_insn_sem_invalid = { + VIRTUAL_INSN_X_INVALID, IQ2000BF_INSN_X_INVALID, IQ2000BF_SFMT_EMPTY +}; + +/* Initialize an IDESC from the compile-time computable parts. */ + +static INLINE void +init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) +{ + const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; + + id->num = t->index; + id->sfmt = t->sfmt; + if ((int) t->type <= 0) + id->idata = & cgen_virtual_insn_table[- (int) t->type]; + else + id->idata = & insn_table[t->type]; + id->attrs = CGEN_INSN_ATTRS (id->idata); + /* Oh my god, a magic number. */ + id->length = CGEN_INSN_BITSIZE (id->idata) / 8; + +#if WITH_PROFILE_MODEL_P + id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; + { + SIM_DESC sd = CPU_STATE (cpu); + SIM_ASSERT (t->index == id->timing->num); + } +#endif + + /* Semantic pointers are initialized elsewhere. */ +} + +/* Initialize the instruction descriptor table. */ + +void +iq2000bf_init_idesc_table (SIM_CPU *cpu) +{ + IDESC *id,*tabend; + const struct insn_sem *t,*tend; + int tabsize = sizeof (iq2000bf_insn_data) / sizeof (IDESC); + IDESC *table = iq2000bf_insn_data; + + memset (table, 0, tabsize * sizeof (IDESC)); + + /* First set all entries to the `invalid insn'. */ + t = & iq2000bf_insn_sem_invalid; + for (id = table, tabend = table + tabsize; id < tabend; ++id) + init_idesc (cpu, id, t); + + /* Now fill in the values for the chosen cpu. */ + for (t = iq2000bf_insn_sem, tend = t + sizeof (iq2000bf_insn_sem) / sizeof (*t); + t != tend; ++t) + { + init_idesc (cpu, & table[t->index], t); + } + + /* Link the IDESC table into the cpu. */ + CPU_IDESC (cpu) = table; +} + +/* Given an instruction, return a pointer to its IDESC entry. */ + +const IDESC * +iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, + CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, + ARGBUF *abuf) +{ + /* Result of decoder. */ + IQ2000BF_INSN_TYPE itype; + + { + CGEN_INSN_INT insn = base_insn; + + { + unsigned int val = (((insn >> 26) & (63 << 0))); + switch (val) + { + case 0 : + { + unsigned int val = (((insn >> 1) & (1 << 4)) | ((insn >> 0) & (15 << 0))); + switch (val) + { + case 0 : itype = IQ2000BF_INSN_SLL;goto extract_sfmt_sll; + case 1 : itype = IQ2000BF_INSN_SLMV;goto extract_sfmt_slmv; + case 2 : itype = IQ2000BF_INSN_SRL;goto extract_sfmt_sll; + case 3 : itype = IQ2000BF_INSN_SRA;goto extract_sfmt_sll; + case 4 : itype = IQ2000BF_INSN_SLLV;goto extract_sfmt_add; + case 5 : itype = IQ2000BF_INSN_SRMV;goto extract_sfmt_slmv; + case 6 : itype = IQ2000BF_INSN_SRLV;goto extract_sfmt_add; + case 7 : itype = IQ2000BF_INSN_SRAV;goto extract_sfmt_add; + case 8 : itype = IQ2000BF_INSN_JR;goto extract_sfmt_jr; + case 9 : itype = IQ2000BF_INSN_JALR;goto extract_sfmt_jalr; + case 10 : itype = IQ2000BF_INSN_JCR;goto extract_sfmt_bctxt; + case 12 : itype = IQ2000BF_INSN_SYSCALL;goto extract_sfmt_syscall; + case 13 : itype = IQ2000BF_INSN_BREAK;goto extract_sfmt_break; + case 14 : itype = IQ2000BF_INSN_SLEEP;goto extract_sfmt_syscall; + case 16 : itype = IQ2000BF_INSN_ADD;goto extract_sfmt_add; + case 17 : itype = IQ2000BF_INSN_ADDU;goto extract_sfmt_add; + case 18 : itype = IQ2000BF_INSN_SUB;goto extract_sfmt_add; + case 19 : itype = IQ2000BF_INSN_SUBU;goto extract_sfmt_add; + case 20 : itype = IQ2000BF_INSN_AND;goto extract_sfmt_add; + case 21 : itype = IQ2000BF_INSN_OR;goto extract_sfmt_add; + case 22 : itype = IQ2000BF_INSN_XOR;goto extract_sfmt_add; + case 23 : itype = IQ2000BF_INSN_NOR;goto extract_sfmt_add; + case 25 : itype = IQ2000BF_INSN_ADO16;goto extract_sfmt_ado16; + case 26 : itype = IQ2000BF_INSN_SLT;goto extract_sfmt_slt; + case 27 : itype = IQ2000BF_INSN_SLTU;goto extract_sfmt_slt; + case 29 : itype = IQ2000BF_INSN_MRGB;goto extract_sfmt_mrgb; + default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 1 : + { + unsigned int val = (((insn >> 17) & (1 << 3)) | ((insn >> 16) & (7 << 0))); + switch (val) + { + case 0 : itype = IQ2000BF_INSN_BLTZ;goto extract_sfmt_bgez; + case 1 : itype = IQ2000BF_INSN_BGEZ;goto extract_sfmt_bgez; + case 2 : itype = IQ2000BF_INSN_BLTZL;goto extract_sfmt_bgez; + case 3 : itype = IQ2000BF_INSN_BGEZL;goto extract_sfmt_bgez; + case 6 : itype = IQ2000BF_INSN_BCTXT;goto extract_sfmt_bctxt; + case 8 : itype = IQ2000BF_INSN_BLTZAL;goto extract_sfmt_bgezal; + case 9 : itype = IQ2000BF_INSN_BGEZAL;goto extract_sfmt_bgezal; + case 10 : itype = IQ2000BF_INSN_BLTZALL;goto extract_sfmt_bgezal; + case 11 : itype = IQ2000BF_INSN_BGEZALL;goto extract_sfmt_bgezal; + default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 2 : itype = IQ2000BF_INSN_J;goto extract_sfmt_j; + case 3 : itype = IQ2000BF_INSN_JAL;goto extract_sfmt_jal; + case 4 : itype = IQ2000BF_INSN_BEQ;goto extract_sfmt_bbv; + case 5 : itype = IQ2000BF_INSN_BNE;goto extract_sfmt_bbv; + case 6 : itype = IQ2000BF_INSN_BLEZ;goto extract_sfmt_bgez; + case 7 : itype = IQ2000BF_INSN_BGTZ;goto extract_sfmt_bgez; + case 8 : itype = IQ2000BF_INSN_ADDI;goto extract_sfmt_addi; + case 9 : itype = IQ2000BF_INSN_ADDIU;goto extract_sfmt_addi; + case 10 : itype = IQ2000BF_INSN_SLTI;goto extract_sfmt_slti; + case 11 : itype = IQ2000BF_INSN_SLTIU;goto extract_sfmt_slti; + case 12 : itype = IQ2000BF_INSN_ANDI;goto extract_sfmt_addi; + case 13 : itype = IQ2000BF_INSN_ORI;goto extract_sfmt_addi; + case 14 : itype = IQ2000BF_INSN_XORI;goto extract_sfmt_addi; + case 15 : itype = IQ2000BF_INSN_LUI;goto extract_sfmt_lui; + case 16 : + { + unsigned int val = (((insn >> 19) & (15 << 3)) | ((insn >> 15) & (3 << 1)) | ((insn >> 4) & (1 << 0))); + switch (val) + { + case 0 : /* fall through */ + case 2 : /* fall through */ + case 4 : /* fall through */ + case 6 : itype = IQ2000BF_INSN_MFC0;goto extract_sfmt_syscall; + case 8 : /* fall through */ + case 10 : /* fall through */ + case 12 : /* fall through */ + case 14 : itype = IQ2000BF_INSN_CFC0;goto extract_sfmt_syscall; + case 16 : /* fall through */ + case 18 : /* fall through */ + case 20 : /* fall through */ + case 22 : itype = IQ2000BF_INSN_MTC0;goto extract_sfmt_syscall; + case 24 : /* fall through */ + case 26 : /* fall through */ + case 28 : /* fall through */ + case 30 : itype = IQ2000BF_INSN_CTC0;goto extract_sfmt_syscall; + case 32 : /* fall through */ + case 33 : itype = IQ2000BF_INSN_BC0F;goto extract_sfmt_bctxt; + case 34 : /* fall through */ + case 35 : itype = IQ2000BF_INSN_BC0T;goto extract_sfmt_bctxt; + case 36 : /* fall through */ + case 37 : itype = IQ2000BF_INSN_BC0FL;goto extract_sfmt_bctxt; + case 38 : /* fall through */ + case 39 : itype = IQ2000BF_INSN_BC0TL;goto extract_sfmt_bctxt; + case 65 : itype = IQ2000BF_INSN_RFE;goto extract_sfmt_syscall; + default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 17 : + { + unsigned int val = (((insn >> 22) & (3 << 0))); + switch (val) + { + case 0 : itype = IQ2000BF_INSN_MFC1;goto extract_sfmt_syscall; + case 1 : itype = IQ2000BF_INSN_CFC1;goto extract_sfmt_syscall; + case 2 : itype = IQ2000BF_INSN_MTC1;goto extract_sfmt_syscall; + case 3 : itype = IQ2000BF_INSN_CTC1;goto extract_sfmt_syscall; + default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 18 : + { + unsigned int val = (((insn >> 16) & (3 << 5)) | ((insn >> 0) & (31 << 0))); + switch (val) + { + case 0 : + { + unsigned int val = (((insn >> 23) & (1 << 0))); + switch (val) + { + case 0 : itype = IQ2000BF_INSN_MFC2;goto extract_sfmt_syscall; + case 1 : itype = IQ2000BF_INSN_MTC2;goto extract_sfmt_syscall; + default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 32 : itype = IQ2000BF_INSN_LUULCK;goto extract_sfmt_syscall; + case 33 : itype = IQ2000BF_INSN_LUR;goto extract_sfmt_syscall; + case 34 : itype = IQ2000BF_INSN_LUM32;goto extract_sfmt_syscall; + case 35 : itype = IQ2000BF_INSN_LUC32;goto extract_sfmt_syscall; + case 36 : itype = IQ2000BF_INSN_LULCK;goto extract_sfmt_syscall; + case 37 : itype = IQ2000BF_INSN_LURL;goto extract_sfmt_syscall; + case 38 : itype = IQ2000BF_INSN_LUM32L;goto extract_sfmt_syscall; + case 39 : itype = IQ2000BF_INSN_LUC32L;goto extract_sfmt_syscall; + case 40 : itype = IQ2000BF_INSN_LUK;goto extract_sfmt_syscall; + case 42 : itype = IQ2000BF_INSN_LUM64;goto extract_sfmt_syscall; + case 43 : itype = IQ2000BF_INSN_LUC64;goto extract_sfmt_syscall; + case 46 : itype = IQ2000BF_INSN_LUM64L;goto extract_sfmt_syscall; + case 47 : itype = IQ2000BF_INSN_LUC64L;goto extract_sfmt_syscall; + case 48 : itype = IQ2000BF_INSN_SRRD;goto extract_sfmt_syscall; + case 49 : itype = IQ2000BF_INSN_SRWR;goto extract_sfmt_syscall; + case 52 : itype = IQ2000BF_INSN_SRRDL;goto extract_sfmt_syscall; + case 53 : itype = IQ2000BF_INSN_SRWRU;goto extract_sfmt_syscall; + case 54 : itype = IQ2000BF_INSN_SRULCK;goto extract_sfmt_syscall; + case 64 : + { + unsigned int val = (((insn >> 23) & (1 << 0))); + switch (val) + { + case 0 : itype = IQ2000BF_INSN_CFC2;goto extract_sfmt_syscall; + case 1 : itype = IQ2000BF_INSN_CTC2;goto extract_sfmt_syscall; + default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 19 : + { + unsigned int val = (((insn >> 19) & (31 << 2)) | ((insn >> 0) & (3 << 0))); + switch (val) + { + case 0 : itype = IQ2000BF_INSN_MFC3;goto extract_sfmt_syscall; + case 4 : + { + unsigned int val = (((insn >> 2) & (3 << 0))); + switch (val) + { + case 0 : itype = IQ2000BF_INSN_WB;goto extract_sfmt_syscall; + case 1 : itype = IQ2000BF_INSN_RB;goto extract_sfmt_syscall; + case 2 : itype = IQ2000BF_INSN_TRAPQFL;goto extract_sfmt_syscall; + default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 5 : + { + unsigned int val = (((insn >> 3) & (1 << 0))); + switch (val) + { + case 0 : itype = IQ2000BF_INSN_WBU;goto extract_sfmt_syscall; + case 1 : itype = IQ2000BF_INSN_TRAPQNE;goto extract_sfmt_syscall; + default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 6 : + { + unsigned int val = (((insn >> 2) & (3 << 0))); + switch (val) + { + case 0 : itype = IQ2000BF_INSN_WX;goto extract_sfmt_syscall; + case 1 : itype = IQ2000BF_INSN_RX;goto extract_sfmt_syscall; + case 2 : itype = IQ2000BF_INSN_TRAPREL;goto extract_sfmt_syscall; + default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 7 : + { + unsigned int val = (((insn >> 2) & (1 << 0))); + switch (val) + { + case 0 : itype = IQ2000BF_INSN_WXU;goto extract_sfmt_syscall; + case 1 : itype = IQ2000BF_INSN_PKRL;goto extract_sfmt_syscall; + default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 8 : itype = IQ2000BF_INSN_CFC3;goto extract_sfmt_syscall; + case 16 : itype = IQ2000BF_INSN_MTC3;goto extract_sfmt_syscall; + case 24 : itype = IQ2000BF_INSN_CTC3;goto extract_sfmt_syscall; + case 32 : /* fall through */ + case 33 : /* fall through */ + case 34 : /* fall through */ + case 35 : + { + unsigned int val = (((insn >> 16) & (3 << 0))); + switch (val) + { + case 0 : itype = IQ2000BF_INSN_BC3F;goto extract_sfmt_bctxt; + case 1 : itype = IQ2000BF_INSN_BC3T;goto extract_sfmt_bctxt; + case 2 : itype = IQ2000BF_INSN_BC3FL;goto extract_sfmt_bctxt; + case 3 : itype = IQ2000BF_INSN_BC3TL;goto extract_sfmt_bctxt; + default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 36 : itype = IQ2000BF_INSN_CHKHDR;goto extract_sfmt_syscall; + case 64 : /* fall through */ + case 65 : /* fall through */ + case 66 : /* fall through */ + case 67 : itype = IQ2000BF_INSN_WBR1;goto extract_sfmt_syscall; + case 68 : /* fall through */ + case 69 : /* fall through */ + case 70 : /* fall through */ + case 71 : itype = IQ2000BF_INSN_WBR1U;goto extract_sfmt_syscall; + case 72 : /* fall through */ + case 73 : /* fall through */ + case 74 : /* fall through */ + case 75 : itype = IQ2000BF_INSN_WBR30;goto extract_sfmt_syscall; + case 76 : /* fall through */ + case 77 : /* fall through */ + case 78 : /* fall through */ + case 79 : itype = IQ2000BF_INSN_WBR30U;goto extract_sfmt_syscall; + case 80 : /* fall through */ + case 81 : /* fall through */ + case 82 : /* fall through */ + case 83 : itype = IQ2000BF_INSN_WXR1;goto extract_sfmt_syscall; + case 84 : /* fall through */ + case 85 : /* fall through */ + case 86 : /* fall through */ + case 87 : itype = IQ2000BF_INSN_WXR1U;goto extract_sfmt_syscall; + case 88 : /* fall through */ + case 89 : /* fall through */ + case 90 : /* fall through */ + case 91 : itype = IQ2000BF_INSN_WXR30;goto extract_sfmt_syscall; + case 92 : /* fall through */ + case 93 : /* fall through */ + case 94 : /* fall through */ + case 95 : itype = IQ2000BF_INSN_WXR30U;goto extract_sfmt_syscall; + case 96 : /* fall through */ + case 97 : /* fall through */ + case 98 : /* fall through */ + case 99 : itype = IQ2000BF_INSN_RBR1;goto extract_sfmt_syscall; + case 104 : /* fall through */ + case 105 : /* fall through */ + case 106 : /* fall through */ + case 107 : itype = IQ2000BF_INSN_RBR30;goto extract_sfmt_syscall; + case 112 : /* fall through */ + case 113 : /* fall through */ + case 114 : /* fall through */ + case 115 : itype = IQ2000BF_INSN_RXR1;goto extract_sfmt_syscall; + case 116 : /* fall through */ + case 117 : /* fall through */ + case 118 : /* fall through */ + case 119 : itype = IQ2000BF_INSN_PKRLR1;goto extract_sfmt_syscall; + case 120 : /* fall through */ + case 121 : /* fall through */ + case 122 : /* fall through */ + case 123 : itype = IQ2000BF_INSN_RXR30;goto extract_sfmt_syscall; + case 124 : /* fall through */ + case 125 : /* fall through */ + case 126 : /* fall through */ + case 127 : itype = IQ2000BF_INSN_PKRLR30;goto extract_sfmt_syscall; + default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 20 : itype = IQ2000BF_INSN_BEQL;goto extract_sfmt_bbv; + case 21 : itype = IQ2000BF_INSN_BNEL;goto extract_sfmt_bbv; + case 22 : itype = IQ2000BF_INSN_BLEZL;goto extract_sfmt_bgez; + case 23 : itype = IQ2000BF_INSN_BGTZL;goto extract_sfmt_bgez; + case 24 : itype = IQ2000BF_INSN_BMB0;goto extract_sfmt_bbv; + case 25 : itype = IQ2000BF_INSN_BMB1;goto extract_sfmt_bbv; + case 26 : itype = IQ2000BF_INSN_BMB2;goto extract_sfmt_bbv; + case 27 : itype = IQ2000BF_INSN_BMB3;goto extract_sfmt_bbv; + case 28 : itype = IQ2000BF_INSN_BBI;goto extract_sfmt_bbi; + case 29 : itype = IQ2000BF_INSN_BBV;goto extract_sfmt_bbv; + case 30 : itype = IQ2000BF_INSN_BBIN;goto extract_sfmt_bbi; + case 31 : itype = IQ2000BF_INSN_BBVN;goto extract_sfmt_bbv; + case 32 : itype = IQ2000BF_INSN_LB;goto extract_sfmt_lb; + case 33 : itype = IQ2000BF_INSN_LH;goto extract_sfmt_lh; + case 35 : itype = IQ2000BF_INSN_LW;goto extract_sfmt_lw; + case 36 : itype = IQ2000BF_INSN_LBU;goto extract_sfmt_lb; + case 37 : itype = IQ2000BF_INSN_LHU;goto extract_sfmt_lh; + case 39 : itype = IQ2000BF_INSN_RAM;goto extract_sfmt_ram; + case 40 : itype = IQ2000BF_INSN_SB;goto extract_sfmt_sb; + case 41 : itype = IQ2000BF_INSN_SH;goto extract_sfmt_sh; + case 43 : itype = IQ2000BF_INSN_SW;goto extract_sfmt_sw; + case 44 : itype = IQ2000BF_INSN_ANDOI;goto extract_sfmt_addi; + case 45 : itype = IQ2000BF_INSN_BMB;goto extract_sfmt_bbv; + case 47 : itype = IQ2000BF_INSN_ORUI;goto extract_sfmt_andoui; + case 48 : itype = IQ2000BF_INSN_LDW;goto extract_sfmt_ldw; + case 56 : itype = IQ2000BF_INSN_SDW;goto extract_sfmt_sdw; + case 63 : itype = IQ2000BF_INSN_ANDOUI;goto extract_sfmt_andoui; + default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + } + + /* The instruction has been decoded, now extract the fields. */ + + extract_sfmt_empty: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; +#define FLD(f) abuf->fields.fmt_empty.f + + + /* Record the fields for the semantic handler. */ + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_add: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mrgb.f + UINT f_rs; + UINT f_rt; + UINT f_rd; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); + + /* Record the fields for the semantic handler. */ + FLD (f_rs) = f_rs; + FLD (f_rt) = f_rt; + FLD (f_rd) = f_rd; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_rs 0x%x", 'x', f_rs, "f_rt 0x%x", 'x', f_rt, "f_rd 0x%x", 'x', f_rd, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_addi: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addi.f + UINT f_rs; + UINT f_rt; + UINT f_imm; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_imm) = f_imm; + FLD (f_rs) = f_rs; + FLD (f_rt) = f_rt; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_imm 0x%x", 'x', f_imm, "f_rs 0x%x", 'x', f_rs, "f_rt 0x%x", 'x', f_rt, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ado16: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mrgb.f + UINT f_rs; + UINT f_rt; + UINT f_rd; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); + + /* Record the fields for the semantic handler. */ + FLD (f_rs) = f_rs; + FLD (f_rt) = f_rt; + FLD (f_rd) = f_rd; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ado16", "f_rs 0x%x", 'x', f_rs, "f_rt 0x%x", 'x', f_rt, "f_rd 0x%x", 'x', f_rd, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ram: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ram.f + UINT f_rs; + UINT f_rt; + UINT f_rd; + UINT f_shamt; + UINT f_maskl; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); + f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); + f_maskl = EXTRACT_LSB0_UINT (insn, 32, 4, 5); + + /* Record the fields for the semantic handler. */ + FLD (f_maskl) = f_maskl; + FLD (f_rs) = f_rs; + FLD (f_rd) = f_rd; + FLD (f_rt) = f_rt; + FLD (f_shamt) = f_shamt; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ram", "f_maskl 0x%x", 'x', f_maskl, "f_rs 0x%x", 'x', f_rs, "f_rd 0x%x", 'x', f_rd, "f_rt 0x%x", 'x', f_rt, "f_shamt 0x%x", 'x', f_shamt, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_sll: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ram.f + UINT f_rt; + UINT f_rd; + UINT f_shamt; + + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); + f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); + + /* Record the fields for the semantic handler. */ + FLD (f_rt) = f_rt; + FLD (f_shamt) = f_shamt; + FLD (f_rd) = f_rd; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll", "f_rt 0x%x", 'x', f_rt, "f_shamt 0x%x", 'x', f_shamt, "f_rd 0x%x", 'x', f_rd, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_slmv: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_ram.f + UINT f_rs; + UINT f_rt; + UINT f_rd; + UINT f_shamt; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); + f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); + + /* Record the fields for the semantic handler. */ + FLD (f_rs) = f_rs; + FLD (f_rt) = f_rt; + FLD (f_shamt) = f_shamt; + FLD (f_rd) = f_rd; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slmv", "f_rs 0x%x", 'x', f_rs, "f_rt 0x%x", 'x', f_rt, "f_shamt 0x%x", 'x', f_shamt, "f_rd 0x%x", 'x', f_rd, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_slt: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mrgb.f + UINT f_rs; + UINT f_rt; + UINT f_rd; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); + + /* Record the fields for the semantic handler. */ + FLD (f_rs) = f_rs; + FLD (f_rt) = f_rt; + FLD (f_rd) = f_rd; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slt", "f_rs 0x%x", 'x', f_rs, "f_rt 0x%x", 'x', f_rt, "f_rd 0x%x", 'x', f_rd, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_slti: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addi.f + UINT f_rs; + UINT f_rt; + UINT f_imm; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_imm) = f_imm; + FLD (f_rs) = f_rs; + FLD (f_rt) = f_rt; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slti", "f_imm 0x%x", 'x', f_imm, "f_rs 0x%x", 'x', f_rs, "f_rt 0x%x", 'x', f_rt, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_bbi: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bbi.f + UINT f_rs; + UINT f_rt; + SI f_offset; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); + + /* Record the fields for the semantic handler. */ + FLD (f_rt) = f_rt; + FLD (f_rs) = f_rs; + FLD (i_offset) = f_offset; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bbi", "f_rt 0x%x", 'x', f_rt, "f_rs 0x%x", 'x', f_rs, "offset 0x%x", 'x', f_offset, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bbv: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bbi.f + UINT f_rs; + UINT f_rt; + SI f_offset; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); + + /* Record the fields for the semantic handler. */ + FLD (f_rs) = f_rs; + FLD (f_rt) = f_rt; + FLD (i_offset) = f_offset; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bbv", "f_rs 0x%x", 'x', f_rs, "f_rt 0x%x", 'x', f_rt, "offset 0x%x", 'x', f_offset, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bgez: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bbi.f + UINT f_rs; + SI f_offset; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); + + /* Record the fields for the semantic handler. */ + FLD (f_rs) = f_rs; + FLD (i_offset) = f_offset; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bgez", "f_rs 0x%x", 'x', f_rs, "offset 0x%x", 'x', f_offset, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bgezal: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bbi.f + UINT f_rs; + SI f_offset; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); + + /* Record the fields for the semantic handler. */ + FLD (f_rs) = f_rs; + FLD (i_offset) = f_offset; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bgezal", "f_rs 0x%x", 'x', f_rs, "offset 0x%x", 'x', f_offset, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_jalr: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mrgb.f + UINT f_rs; + UINT f_rd; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); + + /* Record the fields for the semantic handler. */ + FLD (f_rs) = f_rs; + FLD (f_rd) = f_rd; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jalr", "f_rs 0x%x", 'x', f_rs, "f_rd 0x%x", 'x', f_rd, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_jr: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bbi.f + UINT f_rs; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + + /* Record the fields for the semantic handler. */ + FLD (f_rs) = f_rs; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jr", "f_rs 0x%x", 'x', f_rs, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_lb: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addi.f + UINT f_rs; + UINT f_rt; + UINT f_imm; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_rs) = f_rs; + FLD (f_imm) = f_imm; + FLD (f_rt) = f_rt; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lb", "f_rs 0x%x", 'x', f_rs, "f_imm 0x%x", 'x', f_imm, "f_rt 0x%x", 'x', f_rt, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_lh: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addi.f + UINT f_rs; + UINT f_rt; + UINT f_imm; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_rs) = f_rs; + FLD (f_imm) = f_imm; + FLD (f_rt) = f_rt; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lh", "f_rs 0x%x", 'x', f_rs, "f_imm 0x%x", 'x', f_imm, "f_rt 0x%x", 'x', f_rt, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_lui: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addi.f + UINT f_rt; + UINT f_imm; + + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_imm) = f_imm; + FLD (f_rt) = f_rt; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lui", "f_imm 0x%x", 'x', f_imm, "f_rt 0x%x", 'x', f_rt, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_lw: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addi.f + UINT f_rs; + UINT f_rt; + UINT f_imm; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_rs) = f_rs; + FLD (f_imm) = f_imm; + FLD (f_rt) = f_rt; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lw", "f_rs 0x%x", 'x', f_rs, "f_imm 0x%x", 'x', f_imm, "f_rt 0x%x", 'x', f_rt, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_sb: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addi.f + UINT f_rs; + UINT f_rt; + UINT f_imm; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_rs) = f_rs; + FLD (f_imm) = f_imm; + FLD (f_rt) = f_rt; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sb", "f_rs 0x%x", 'x', f_rs, "f_imm 0x%x", 'x', f_imm, "f_rt 0x%x", 'x', f_rt, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_sh: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addi.f + UINT f_rs; + UINT f_rt; + UINT f_imm; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_rs) = f_rs; + FLD (f_imm) = f_imm; + FLD (f_rt) = f_rt; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sh", "f_rs 0x%x", 'x', f_rs, "f_imm 0x%x", 'x', f_imm, "f_rt 0x%x", 'x', f_rt, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_sw: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addi.f + UINT f_rs; + UINT f_rt; + UINT f_imm; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_rs) = f_rs; + FLD (f_imm) = f_imm; + FLD (f_rt) = f_rt; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sw", "f_rs 0x%x", 'x', f_rs, "f_imm 0x%x", 'x', f_imm, "f_rt 0x%x", 'x', f_rt, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_break: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; +#define FLD(f) abuf->fields.fmt_empty.f + + + /* Record the fields for the semantic handler. */ + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_break", (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_syscall: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; +#define FLD(f) abuf->fields.fmt_empty.f + + + /* Record the fields for the semantic handler. */ + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_syscall", (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_andoui: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addi.f + UINT f_rs; + UINT f_rt; + UINT f_imm; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_imm) = f_imm; + FLD (f_rs) = f_rs; + FLD (f_rt) = f_rt; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andoui", "f_imm 0x%x", 'x', f_imm, "f_rs 0x%x", 'x', f_rs, "f_rt 0x%x", 'x', f_rt, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_mrgb: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mrgb.f + UINT f_rs; + UINT f_rt; + UINT f_rd; + UINT f_mask; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); + f_mask = EXTRACT_LSB0_UINT (insn, 32, 9, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_mask) = f_mask; + FLD (f_rs) = f_rs; + FLD (f_rt) = f_rt; + FLD (f_rd) = f_rd; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mrgb", "f_mask 0x%x", 'x', f_mask, "f_rs 0x%x", 'x', f_rs, "f_rt 0x%x", 'x', f_rt, "f_rd 0x%x", 'x', f_rd, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_bctxt: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; +#define FLD(f) abuf->fields.fmt_empty.f + + + /* Record the fields for the semantic handler. */ + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bctxt", (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldw: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addi.f + UINT f_rs; + UINT f_rt; + UINT f_imm; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_rs) = f_rs; + FLD (f_rt) = f_rt; + FLD (f_imm) = f_imm; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldw", "f_rs 0x%x", 'x', f_rs, "f_rt 0x%x", 'x', f_rt, "f_imm 0x%x", 'x', f_imm, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_sdw: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_addi.f + UINT f_rs; + UINT f_rt; + UINT f_imm; + + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_rs) = f_rs; + FLD (f_rt) = f_rt; + FLD (f_imm) = f_imm; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sdw", "f_rs 0x%x", 'x', f_rs, "f_rt 0x%x", 'x', f_rt, "f_imm 0x%x", 'x', f_imm, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_j: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_j.f + USI f_jtarg; + + f_jtarg = ((((pc) & (0xf0000000))) | (((EXTRACT_LSB0_UINT (insn, 32, 15, 16)) << (2)))); + + /* Record the fields for the semantic handler. */ + FLD (i_jmptarg) = f_jtarg; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_j", "jmptarg 0x%x", 'x', f_jtarg, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_jal: + { + const IDESC *idesc = &iq2000bf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_j.f + USI f_jtarg; + + f_jtarg = ((((pc) & (0xf0000000))) | (((EXTRACT_LSB0_UINT (insn, 32, 15, 16)) << (2)))); + + /* Record the fields for the semantic handler. */ + FLD (i_jmptarg) = f_jtarg; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jal", "jmptarg 0x%x", 'x', f_jtarg, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + +}

decode.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: sem-switch.c =================================================================== --- sem-switch.c (nonexistent) +++ sem-switch.c (revision 33) @@ -0,0 +1,3265 @@ +/* Simulator instruction semantics for iq2000bf. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +*/ + +#ifdef DEFINE_LABELS + + /* The labels have the case they have because the enum of insn types + is all uppercase and in the non-stdc case the insn symbol is built + into the enum name. */ + + static struct { + int index; + void *label; + } labels[] = { + { IQ2000BF_INSN_X_INVALID, && case_sem_INSN_X_INVALID }, + { IQ2000BF_INSN_X_AFTER, && case_sem_INSN_X_AFTER }, + { IQ2000BF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE }, + { IQ2000BF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN }, + { IQ2000BF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN }, + { IQ2000BF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN }, + { IQ2000BF_INSN_ADD, && case_sem_INSN_ADD }, + { IQ2000BF_INSN_ADDI, && case_sem_INSN_ADDI }, + { IQ2000BF_INSN_ADDIU, && case_sem_INSN_ADDIU }, + { IQ2000BF_INSN_ADDU, && case_sem_INSN_ADDU }, + { IQ2000BF_INSN_ADO16, && case_sem_INSN_ADO16 }, + { IQ2000BF_INSN_AND, && case_sem_INSN_AND }, + { IQ2000BF_INSN_ANDI, && case_sem_INSN_ANDI }, + { IQ2000BF_INSN_ANDOI, && case_sem_INSN_ANDOI }, + { IQ2000BF_INSN_NOR, && case_sem_INSN_NOR }, + { IQ2000BF_INSN_OR, && case_sem_INSN_OR }, + { IQ2000BF_INSN_ORI, && case_sem_INSN_ORI }, + { IQ2000BF_INSN_RAM, && case_sem_INSN_RAM }, + { IQ2000BF_INSN_SLL, && case_sem_INSN_SLL }, + { IQ2000BF_INSN_SLLV, && case_sem_INSN_SLLV }, + { IQ2000BF_INSN_SLMV, && case_sem_INSN_SLMV }, + { IQ2000BF_INSN_SLT, && case_sem_INSN_SLT }, + { IQ2000BF_INSN_SLTI, && case_sem_INSN_SLTI }, + { IQ2000BF_INSN_SLTIU, && case_sem_INSN_SLTIU }, + { IQ2000BF_INSN_SLTU, && case_sem_INSN_SLTU }, + { IQ2000BF_INSN_SRA, && case_sem_INSN_SRA }, + { IQ2000BF_INSN_SRAV, && case_sem_INSN_SRAV }, + { IQ2000BF_INSN_SRL, && case_sem_INSN_SRL }, + { IQ2000BF_INSN_SRLV, && case_sem_INSN_SRLV }, + { IQ2000BF_INSN_SRMV, && case_sem_INSN_SRMV }, + { IQ2000BF_INSN_SUB, && case_sem_INSN_SUB }, + { IQ2000BF_INSN_SUBU, && case_sem_INSN_SUBU }, + { IQ2000BF_INSN_XOR, && case_sem_INSN_XOR }, + { IQ2000BF_INSN_XORI, && case_sem_INSN_XORI }, + { IQ2000BF_INSN_BBI, && case_sem_INSN_BBI }, + { IQ2000BF_INSN_BBIN, && case_sem_INSN_BBIN }, + { IQ2000BF_INSN_BBV, && case_sem_INSN_BBV }, + { IQ2000BF_INSN_BBVN, && case_sem_INSN_BBVN }, + { IQ2000BF_INSN_BEQ, && case_sem_INSN_BEQ }, + { IQ2000BF_INSN_BEQL, && case_sem_INSN_BEQL }, + { IQ2000BF_INSN_BGEZ, && case_sem_INSN_BGEZ }, + { IQ2000BF_INSN_BGEZAL, && case_sem_INSN_BGEZAL }, + { IQ2000BF_INSN_BGEZALL, && case_sem_INSN_BGEZALL }, + { IQ2000BF_INSN_BGEZL, && case_sem_INSN_BGEZL }, + { IQ2000BF_INSN_BLTZ, && case_sem_INSN_BLTZ }, + { IQ2000BF_INSN_BLTZL, && case_sem_INSN_BLTZL }, + { IQ2000BF_INSN_BLTZAL, && case_sem_INSN_BLTZAL }, + { IQ2000BF_INSN_BLTZALL, && case_sem_INSN_BLTZALL }, + { IQ2000BF_INSN_BMB0, && case_sem_INSN_BMB0 }, + { IQ2000BF_INSN_BMB1, && case_sem_INSN_BMB1 }, + { IQ2000BF_INSN_BMB2, && case_sem_INSN_BMB2 }, + { IQ2000BF_INSN_BMB3, && case_sem_INSN_BMB3 }, + { IQ2000BF_INSN_BNE, && case_sem_INSN_BNE }, + { IQ2000BF_INSN_BNEL, && case_sem_INSN_BNEL }, + { IQ2000BF_INSN_JALR, && case_sem_INSN_JALR }, + { IQ2000BF_INSN_JR, && case_sem_INSN_JR }, + { IQ2000BF_INSN_LB, && case_sem_INSN_LB }, + { IQ2000BF_INSN_LBU, && case_sem_INSN_LBU }, + { IQ2000BF_INSN_LH, && case_sem_INSN_LH }, + { IQ2000BF_INSN_LHU, && case_sem_INSN_LHU }, + { IQ2000BF_INSN_LUI, && case_sem_INSN_LUI }, + { IQ2000BF_INSN_LW, && case_sem_INSN_LW }, + { IQ2000BF_INSN_SB, && case_sem_INSN_SB }, + { IQ2000BF_INSN_SH, && case_sem_INSN_SH }, + { IQ2000BF_INSN_SW, && case_sem_INSN_SW }, + { IQ2000BF_INSN_BREAK, && case_sem_INSN_BREAK }, + { IQ2000BF_INSN_SYSCALL, && case_sem_INSN_SYSCALL }, + { IQ2000BF_INSN_ANDOUI, && case_sem_INSN_ANDOUI }, + { IQ2000BF_INSN_ORUI, && case_sem_INSN_ORUI }, + { IQ2000BF_INSN_BGTZ, && case_sem_INSN_BGTZ }, + { IQ2000BF_INSN_BGTZL, && case_sem_INSN_BGTZL }, + { IQ2000BF_INSN_BLEZ, && case_sem_INSN_BLEZ }, + { IQ2000BF_INSN_BLEZL, && case_sem_INSN_BLEZL }, + { IQ2000BF_INSN_MRGB, && case_sem_INSN_MRGB }, + { IQ2000BF_INSN_BCTXT, && case_sem_INSN_BCTXT }, + { IQ2000BF_INSN_BC0F, && case_sem_INSN_BC0F }, + { IQ2000BF_INSN_BC0FL, && case_sem_INSN_BC0FL }, + { IQ2000BF_INSN_BC3F, && case_sem_INSN_BC3F }, + { IQ2000BF_INSN_BC3FL, && case_sem_INSN_BC3FL }, + { IQ2000BF_INSN_BC0T, && case_sem_INSN_BC0T }, + { IQ2000BF_INSN_BC0TL, && case_sem_INSN_BC0TL }, + { IQ2000BF_INSN_BC3T, && case_sem_INSN_BC3T }, + { IQ2000BF_INSN_BC3TL, && case_sem_INSN_BC3TL }, + { IQ2000BF_INSN_CFC0, && case_sem_INSN_CFC0 }, + { IQ2000BF_INSN_CFC1, && case_sem_INSN_CFC1 }, + { IQ2000BF_INSN_CFC2, && case_sem_INSN_CFC2 }, + { IQ2000BF_INSN_CFC3, && case_sem_INSN_CFC3 }, + { IQ2000BF_INSN_CHKHDR, && case_sem_INSN_CHKHDR }, + { IQ2000BF_INSN_CTC0, && case_sem_INSN_CTC0 }, + { IQ2000BF_INSN_CTC1, && case_sem_INSN_CTC1 }, + { IQ2000BF_INSN_CTC2, && case_sem_INSN_CTC2 }, + { IQ2000BF_INSN_CTC3, && case_sem_INSN_CTC3 }, + { IQ2000BF_INSN_JCR, && case_sem_INSN_JCR }, + { IQ2000BF_INSN_LUC32, && case_sem_INSN_LUC32 }, + { IQ2000BF_INSN_LUC32L, && case_sem_INSN_LUC32L }, + { IQ2000BF_INSN_LUC64, && case_sem_INSN_LUC64 }, + { IQ2000BF_INSN_LUC64L, && case_sem_INSN_LUC64L }, + { IQ2000BF_INSN_LUK, && case_sem_INSN_LUK }, + { IQ2000BF_INSN_LULCK, && case_sem_INSN_LULCK }, + { IQ2000BF_INSN_LUM32, && case_sem_INSN_LUM32 }, + { IQ2000BF_INSN_LUM32L, && case_sem_INSN_LUM32L }, + { IQ2000BF_INSN_LUM64, && case_sem_INSN_LUM64 }, + { IQ2000BF_INSN_LUM64L, && case_sem_INSN_LUM64L }, + { IQ2000BF_INSN_LUR, && case_sem_INSN_LUR }, + { IQ2000BF_INSN_LURL, && case_sem_INSN_LURL }, + { IQ2000BF_INSN_LUULCK, && case_sem_INSN_LUULCK }, + { IQ2000BF_INSN_MFC0, && case_sem_INSN_MFC0 }, + { IQ2000BF_INSN_MFC1, && case_sem_INSN_MFC1 }, + { IQ2000BF_INSN_MFC2, && case_sem_INSN_MFC2 }, + { IQ2000BF_INSN_MFC3, && case_sem_INSN_MFC3 }, + { IQ2000BF_INSN_MTC0, && case_sem_INSN_MTC0 }, + { IQ2000BF_INSN_MTC1, && case_sem_INSN_MTC1 }, + { IQ2000BF_INSN_MTC2, && case_sem_INSN_MTC2 }, + { IQ2000BF_INSN_MTC3, && case_sem_INSN_MTC3 }, + { IQ2000BF_INSN_PKRL, && case_sem_INSN_PKRL }, + { IQ2000BF_INSN_PKRLR1, && case_sem_INSN_PKRLR1 }, + { IQ2000BF_INSN_PKRLR30, && case_sem_INSN_PKRLR30 }, + { IQ2000BF_INSN_RB, && case_sem_INSN_RB }, + { IQ2000BF_INSN_RBR1, && case_sem_INSN_RBR1 }, + { IQ2000BF_INSN_RBR30, && case_sem_INSN_RBR30 }, + { IQ2000BF_INSN_RFE, && case_sem_INSN_RFE }, + { IQ2000BF_INSN_RX, && case_sem_INSN_RX }, + { IQ2000BF_INSN_RXR1, && case_sem_INSN_RXR1 }, + { IQ2000BF_INSN_RXR30, && case_sem_INSN_RXR30 }, + { IQ2000BF_INSN_SLEEP, && case_sem_INSN_SLEEP }, + { IQ2000BF_INSN_SRRD, && case_sem_INSN_SRRD }, + { IQ2000BF_INSN_SRRDL, && case_sem_INSN_SRRDL }, + { IQ2000BF_INSN_SRULCK, && case_sem_INSN_SRULCK }, + { IQ2000BF_INSN_SRWR, && case_sem_INSN_SRWR }, + { IQ2000BF_INSN_SRWRU, && case_sem_INSN_SRWRU }, + { IQ2000BF_INSN_TRAPQFL, && case_sem_INSN_TRAPQFL }, + { IQ2000BF_INSN_TRAPQNE, && case_sem_INSN_TRAPQNE }, + { IQ2000BF_INSN_TRAPREL, && case_sem_INSN_TRAPREL }, + { IQ2000BF_INSN_WB, && case_sem_INSN_WB }, + { IQ2000BF_INSN_WBU, && case_sem_INSN_WBU }, + { IQ2000BF_INSN_WBR1, && case_sem_INSN_WBR1 }, + { IQ2000BF_INSN_WBR1U, && case_sem_INSN_WBR1U }, + { IQ2000BF_INSN_WBR30, && case_sem_INSN_WBR30 }, + { IQ2000BF_INSN_WBR30U, && case_sem_INSN_WBR30U }, + { IQ2000BF_INSN_WX, && case_sem_INSN_WX }, + { IQ2000BF_INSN_WXU, && case_sem_INSN_WXU }, + { IQ2000BF_INSN_WXR1, && case_sem_INSN_WXR1 }, + { IQ2000BF_INSN_WXR1U, && case_sem_INSN_WXR1U }, + { IQ2000BF_INSN_WXR30, && case_sem_INSN_WXR30 }, + { IQ2000BF_INSN_WXR30U, && case_sem_INSN_WXR30U }, + { IQ2000BF_INSN_LDW, && case_sem_INSN_LDW }, + { IQ2000BF_INSN_SDW, && case_sem_INSN_SDW }, + { IQ2000BF_INSN_J, && case_sem_INSN_J }, + { IQ2000BF_INSN_JAL, && case_sem_INSN_JAL }, + { IQ2000BF_INSN_BMB, && case_sem_INSN_BMB }, + { 0, 0 } + }; + int i; + + for (i = 0; labels[i].label != 0; ++i) + { +#if FAST_P + CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; +#else + CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label; +#endif + } + +#undef DEFINE_LABELS +#endif /* DEFINE_LABELS */ + +#ifdef DEFINE_SWITCH + +/* If hyper-fast [well not unnecessarily slow] execution is selected, turn + off frills like tracing and profiling. */ +/* FIXME: A better way would be to have TRACE_RESULT check for something + that can cause it to be optimized out. Another way would be to emit + special handlers into the instruction "stream". */ + +#if FAST_P +#undef TRACE_RESULT +#define TRACE_RESULT(cpu, abuf, name, type, val) +#endif + +#undef GET_ATTR +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) +#else +#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr) +#endif + +{ + +#if WITH_SCACHE_PBB + +/* Branch to next handler without going around main loop. */ +#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case +SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) + +#else /* ! WITH_SCACHE_PBB */ + +#define NEXT(vpc) BREAK (sem) +#ifdef __GNUC__ +#if FAST_P + SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab) +#else + SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab) +#endif +#else + SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num) +#endif + +#endif /* ! WITH_SCACHE_PBB */ + + { + + CASE (sem, INSN_X_INVALID) : /* --invalid-- */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { + /* Update the recorded pc in the cpu state struct. + Only necessary for WITH_SCACHE case, but to avoid the + conditional compilation .... */ + SET_H_PC (pc); + /* Virtual insns have zero size. Overwrite vpc with address of next insn + using the default-insn-bitsize spec. When executing insns in parallel + we may want to queue the fault and continue execution. */ + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + vpc = sim_engine_invalid_insn (current_cpu, pc, vpc); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_X_AFTER) : /* --after-- */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_IQ2000BF + iq2000bf_pbb_after (current_cpu, sem_arg); +#endif + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_X_BEFORE) : /* --before-- */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_IQ2000BF + iq2000bf_pbb_before (current_cpu, sem_arg); +#endif + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_IQ2000BF +#ifdef DEFINE_SWITCH + vpc = iq2000bf_pbb_cti_chain (current_cpu, sem_arg, + pbb_br_type, pbb_br_npc); + BREAK (sem); +#else + /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ + vpc = iq2000bf_pbb_cti_chain (current_cpu, sem_arg, + CPU_PBB_BR_TYPE (current_cpu), + CPU_PBB_BR_NPC (current_cpu)); +#endif +#endif + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_X_CHAIN) : /* --chain-- */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_IQ2000BF + vpc = iq2000bf_pbb_chain (current_cpu, sem_arg); +#ifdef DEFINE_SWITCH + BREAK (sem); +#endif +#endif + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_X_BEGIN) : /* --begin-- */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_IQ2000BF +#if defined DEFINE_SWITCH || defined FAST_P + /* In the switch case FAST_P is a constant, allowing several optimizations + in any called inline functions. */ + vpc = iq2000bf_pbb_begin (current_cpu, FAST_P); +#else +#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */ + vpc = iq2000bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); +#else + vpc = iq2000bf_pbb_begin (current_cpu, 0); +#endif +#endif +#endif + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ADD) : /* add $rd,$rs,$rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mrgb.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ADDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ADDI) : /* addi $rt,$rs,$lo16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ADDIU) : /* addiu $rt,$rs,$lo16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ADDU) : /* addu $rd,$rs,$rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mrgb.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ADDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ADO16) : /* ado16 $rd,$rs,$rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mrgb.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + HI tmp_high; + HI tmp_low; + tmp_low = ADDHI (ANDHI (GET_H_GR (FLD (f_rs)), 65535), ANDHI (GET_H_GR (FLD (f_rt)), 65535)); + tmp_high = ADDHI (SRLSI (GET_H_GR (FLD (f_rs)), 16), SRLSI (GET_H_GR (FLD (f_rt)), 16)); + { + SI opval = ORSI (SLLSI (tmp_high, 16), tmp_low); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_AND) : /* and $rd,$rs,$rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mrgb.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ANDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ANDI) : /* andi $rt,$rs,$lo16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ANDSI (GET_H_GR (FLD (f_rs)), ZEXTSISI (FLD (f_imm))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ANDOI) : /* andoi $rt,$rs,$lo16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ANDSI (GET_H_GR (FLD (f_rs)), ORSI (0xffff0000, EXTHISI (TRUNCSIHI (FLD (f_imm))))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_NOR) : /* nor $rd,$rs,$rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mrgb.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = INVSI (ORSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_OR) : /* or $rd,$rs,$rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mrgb.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ORSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ORI) : /* ori $rt,$rs,$lo16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ORSI (GET_H_GR (FLD (f_rs)), ZEXTSISI (FLD (f_imm))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_RAM) : /* ram $rd,$rt,$shamt,$maskl,$maskr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ram.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SI opval = RORSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + SI opval = ANDSI (GET_H_GR (FLD (f_rd)), SRLSI (0xffffffff, FLD (f_maskl))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + SI opval = ANDSI (GET_H_GR (FLD (f_rd)), SLLSI (0xffffffff, FLD (f_rs))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SLL) : /* sll $rd,$rt,$shamt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ram.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SLLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SLLV) : /* sllv $rd,$rt,$rs */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mrgb.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SLLSI (GET_H_GR (FLD (f_rt)), ANDSI (GET_H_GR (FLD (f_rs)), 31)); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SLMV) : /* slmv $rd,$rt,$rs,$shamt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ram.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ANDSI (SLLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)), SRLSI (0xffffffff, GET_H_GR (FLD (f_rs)))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SLT) : /* slt $rd,$rs,$rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mrgb.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LTSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { + { + SI opval = 1; + SET_H_GR (FLD (f_rd), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} else { + { + SI opval = 0; + SET_H_GR (FLD (f_rd), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SLTI) : /* slti $rt,$rs,$imm */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LTSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))))) { + { + SI opval = 1; + SET_H_GR (FLD (f_rt), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} else { + { + SI opval = 0; + SET_H_GR (FLD (f_rt), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SLTIU) : /* sltiu $rt,$rs,$imm */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LTUSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))))) { + { + SI opval = 1; + SET_H_GR (FLD (f_rt), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} else { + { + SI opval = 0; + SET_H_GR (FLD (f_rt), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SLTU) : /* sltu $rd,$rs,$rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mrgb.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LTUSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { + { + SI opval = 1; + SET_H_GR (FLD (f_rd), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} else { + { + SI opval = 0; + SET_H_GR (FLD (f_rd), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SRA) : /* sra $rd,$rt,$shamt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ram.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SRASI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SRAV) : /* srav $rd,$rt,$rs */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mrgb.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SRASI (GET_H_GR (FLD (f_rt)), ANDSI (GET_H_GR (FLD (f_rs)), 31)); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SRL) : /* srl $rd,$rt,$shamt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ram.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SRLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SRLV) : /* srlv $rd,$rt,$rs */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mrgb.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SRLSI (GET_H_GR (FLD (f_rt)), ANDSI (GET_H_GR (FLD (f_rs)), 31)); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SRMV) : /* srmv $rd,$rt,$rs,$shamt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_ram.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ANDSI (SRLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)), SLLSI (0xffffffff, GET_H_GR (FLD (f_rs)))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SUB) : /* sub $rd,$rs,$rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mrgb.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SUBSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SUBU) : /* subu $rd,$rs,$rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mrgb.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SUBSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_XOR) : /* xor $rd,$rs,$rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mrgb.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = XORSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_XORI) : /* xori $rt,$rs,$lo16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = XORSI (GET_H_GR (FLD (f_rs)), ZEXTSISI (FLD (f_imm))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BBI) : /* bbi $rs($bitnum),$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, FLD (f_rt)))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BBIN) : /* bbin $rs($bitnum),$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTSI (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, FLD (f_rt))))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BBV) : /* bbv $rs,$rt,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, ANDSI (GET_H_GR (FLD (f_rt)), 31)))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BBVN) : /* bbvn $rs,$rt,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTSI (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, ANDSI (GET_H_GR (FLD (f_rt)), 31))))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BEQ) : /* beq $rs,$rt,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BEQL) : /* beql $rs,$rt,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (1) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BGEZ) : /* bgez $rs,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (GESI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BGEZAL) : /* bgezal $rs,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (GESI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + SI opval = ADDSI (pc, 8); + SET_H_GR (((UINT) 31), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BGEZALL) : /* bgezall $rs,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (GESI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + SI opval = ADDSI (pc, 8); + SET_H_GR (((UINT) 31), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} else { +if (1) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BGEZL) : /* bgezl $rs,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (GESI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (1) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BLTZ) : /* bltz $rs,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LTSI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BLTZL) : /* bltzl $rs,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LTSI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (1) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BLTZAL) : /* bltzal $rs,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LTSI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + SI opval = ADDSI (pc, 8); + SET_H_GR (((UINT) 31), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BLTZALL) : /* bltzall $rs,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LTSI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + SI opval = ADDSI (pc, 8); + SET_H_GR (((UINT) 31), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} else { +if (1) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BMB0) : /* bmb0 $rs,$rt,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 255), ANDSI (GET_H_GR (FLD (f_rt)), 255))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BMB1) : /* bmb1 $rs,$rt,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 65280), ANDSI (GET_H_GR (FLD (f_rt)), 65280))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BMB2) : /* bmb2 $rs,$rt,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 16711680), ANDSI (GET_H_GR (FLD (f_rt)), 16711680))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BMB3) : /* bmb3 $rs,$rt,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 0xff000000), ANDSI (GET_H_GR (FLD (f_rt)), 0xff000000))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BNE) : /* bne $rs,$rt,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BNEL) : /* bnel $rs,$rt,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (1) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_JALR) : /* jalr $rd,$rs */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mrgb.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +{ + { + SI opval = ADDSI (pc, 8); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = GET_H_GR (FLD (f_rs)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_JR) : /* jr $rs */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + USI opval = GET_H_GR (FLD (f_rs)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LB) : /* lb $rt,$lo16($base) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LBU) : /* lbu $rt,$lo16($base) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LH) : /* lh $rt,$lo16($base) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LHU) : /* lhu $rt,$lo16($base) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LUI) : /* lui $rt,$hi16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SLLSI (FLD (f_imm), 16); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LW) : /* lw $rt,$lo16($base) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SB) : /* sb $rt,$lo16($base) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + QI opval = ANDQI (GET_H_GR (FLD (f_rt)), 255); + SETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SH) : /* sh $rt,$lo16($base) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + HI opval = ANDHI (GET_H_GR (FLD (f_rt)), 65535); + SETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SW) : /* sw $rt,$lo16($base) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = GET_H_GR (FLD (f_rt)); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BREAK) : /* break */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +do_break (current_cpu, pc); + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SYSCALL) : /* syscall */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +do_syscall (current_cpu); + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ANDOUI) : /* andoui $rt,$rs,$hi16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ANDSI (GET_H_GR (FLD (f_rs)), ORSI (SLLSI (FLD (f_imm), 16), 65535)); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ORUI) : /* orui $rt,$rs,$hi16 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ORSI (GET_H_GR (FLD (f_rs)), SLLSI (FLD (f_imm), 16)); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BGTZ) : /* bgtz $rs,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (GTSI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BGTZL) : /* bgtzl $rs,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (GTSI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (1) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BLEZ) : /* blez $rs,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LESI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BLEZL) : /* blezl $rs,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LESI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (1) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MRGB) : /* mrgb $rd,$rs,$rt,$mask */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_mrgb.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_temp; +if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 0)))) { + tmp_temp = ANDSI (GET_H_GR (FLD (f_rs)), 255); +} else { + tmp_temp = ANDSI (GET_H_GR (FLD (f_rt)), 255); +} +if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 1)))) { + tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rs)), 65280)); +} else { + tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rt)), 65280)); +} +if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 2)))) { + tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rs)), 16711680)); +} else { + tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rt)), 16711680)); +} +if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 3)))) { + tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rs)), 0xff000000)); +} else { + tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rt)), 0xff000000)); +} + { + SI opval = tmp_temp; + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BCTXT) : /* bctxt $rs,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BC0F) : /* bc0f $offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BC0FL) : /* bc0fl $offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BC3F) : /* bc3f $offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BC3FL) : /* bc3fl $offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BC0T) : /* bc0t $offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BC0TL) : /* bc0tl $offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BC3T) : /* bc3t $offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BC3TL) : /* bc3tl $offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_CFC0) : /* cfc0 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_CFC1) : /* cfc1 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_CFC2) : /* cfc2 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_CFC3) : /* cfc3 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_CHKHDR) : /* chkhdr $rd,$rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_CTC0) : /* ctc0 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_CTC1) : /* ctc1 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_CTC2) : /* ctc2 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_CTC3) : /* ctc3 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_JCR) : /* jcr $rs */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LUC32) : /* luc32 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LUC32L) : /* luc32l $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LUC64) : /* luc64 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LUC64L) : /* luc64l $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LUK) : /* luk $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LULCK) : /* lulck $rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LUM32) : /* lum32 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LUM32L) : /* lum32l $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LUM64) : /* lum64 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LUM64L) : /* lum64l $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LUR) : /* lur $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LURL) : /* lurl $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LUULCK) : /* luulck $rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MFC0) : /* mfc0 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MFC1) : /* mfc1 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MFC2) : /* mfc2 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MFC3) : /* mfc3 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MTC0) : /* mtc0 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MTC1) : /* mtc1 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MTC2) : /* mtc2 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MTC3) : /* mtc3 $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_PKRL) : /* pkrl $rd,$rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_PKRLR1) : /* pkrlr1 $rt,$index,$count */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_PKRLR30) : /* pkrlr30 $rt,$index,$count */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_RB) : /* rb $rd,$rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_RBR1) : /* rbr1 $rt,$index,$count */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_RBR30) : /* rbr30 $rt,$index,$count */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_RFE) : /* rfe */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_RX) : /* rx $rd,$rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_RXR1) : /* rxr1 $rt,$index,$count */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_RXR30) : /* rxr30 $rt,$index,$count */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SLEEP) : /* sleep */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SRRD) : /* srrd $rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SRRDL) : /* srrdl $rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SRULCK) : /* srulck $rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SRWR) : /* srwr $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SRWRU) : /* srwru $rt,$rd */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_TRAPQFL) : /* trapqfl */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_TRAPQNE) : /* trapqne */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_TRAPREL) : /* traprel $rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_WB) : /* wb $rd,$rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_WBU) : /* wbu $rd,$rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_WBR1) : /* wbr1 $rt,$index,$count */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_WBR1U) : /* wbr1u $rt,$index,$count */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_WBR30) : /* wbr30 $rt,$index,$count */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_WBR30U) : /* wbr30u $rt,$index,$count */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_WX) : /* wx $rd,$rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_WXU) : /* wxu $rd,$rt */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_WXR1) : /* wxr1 $rt,$index,$count */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_WXR1U) : /* wxr1u $rt,$index,$count */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_WXR30) : /* wxr30 $rt,$index,$count */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_WXR30U) : /* wxr30u $rt,$index,$count */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_empty.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LDW) : /* ldw $rt,$lo16($base) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_addr; + tmp_addr = ANDSI (ADDSI (GET_H_GR (FLD (f_rs)), FLD (f_imm)), INVSI (3)); + { + SI opval = GETMEMSI (current_cpu, pc, tmp_addr); + SET_H_GR (ADDSI (FLD (f_rt), 1), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_addr, 4)); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_SDW) : /* sdw $rt,$lo16($base) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_addi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_addr; + tmp_addr = ANDSI (ADDSI (GET_H_GR (FLD (f_rs)), FLD (f_imm)), INVSI (3)); + { + SI opval = GET_H_GR (FLD (f_rt)); + SETMEMSI (current_cpu, pc, ADDSI (tmp_addr, 4), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + { + SI opval = GET_H_GR (ADDSI (FLD (f_rt), 1)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_J) : /* j $jmptarg */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_j.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + USI opval = FLD (i_jmptarg); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_JAL) : /* jal $jmptarg */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_j.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +{ + { + SI opval = ADDSI (pc, 8); + SET_H_GR (((UINT) 31), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = FLD (i_jmptarg); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_BMB) : /* bmb $rs,$rt,$offset */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_bbi.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_branch_; + tmp_branch_ = 0; +if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 255), ANDSI (GET_H_GR (FLD (f_rt)), 255))) { + tmp_branch_ = 1; +} +if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 65280), ANDSI (GET_H_GR (FLD (f_rt)), 65280))) { + tmp_branch_ = 1; +} +if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 16711680), ANDSI (GET_H_GR (FLD (f_rt)), 16711680))) { + tmp_branch_ = 1; +} +if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 0xff000000), ANDSI (GET_H_GR (FLD (f_rt)), 0xff000000))) { + tmp_branch_ = 1; +} +if (tmp_branch_) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); +#undef FLD +} + NEXT (vpc); + + + } + ENDSWITCH (sem) /* End of semantic switch. */ + ; + + /* At this point `vpc' contains the next insn to execute. */ +} + +#undef DEFINE_SWITCH +#endif /* DEFINE_SWITCH */

sem-switch.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: sim-if.c =================================================================== --- sim-if.c (nonexistent) +++ sim-if.c (revision 33) @@ -0,0 +1,202 @@ +/* Main simulator entry points specific to the IQ2000. + Copyright (C) 2000, 2007, 2008 Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +#include "sim-main.h" +#ifdef HAVE_STDLIB_H +#include +#endif +#include "sim-options.h" +#include "libiberty.h" +#include "bfd.h" + +static void free_state (SIM_DESC); + +/* Records simulator descriptor so utilities like iq2000_dump_regs can be + called from gdb. */ +SIM_DESC current_state; + +/* Cover function for sim_cgen_disassemble_insn. */ + +void +iq2000bf_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn, + const ARGBUF *abuf, IADDR pc, char *buf) +{ + sim_cgen_disassemble_insn(cpu, insn, abuf, pc, buf); +} + +/* Cover function of sim_state_free to free the cpu buffers as well. */ + +static void +free_state (SIM_DESC sd) +{ + if (STATE_MODULES (sd) != NULL) + sim_module_uninstall (sd); + sim_cpu_free_all (sd); + sim_state_free (sd); +} + +/* Create an instance of the simulator. */ + +SIM_DESC +sim_open (kind, callback, abfd, argv) + SIM_OPEN_KIND kind; + host_callback *callback; + struct bfd *abfd; + char **argv; +{ + char c; + int i; + SIM_DESC sd = sim_state_alloc (kind, callback); + + /* The cpu data is kept in a separately allocated chunk of memory. */ + if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK) + { + free_state (sd); + return 0; + } + +#if 0 /* FIXME: pc is in mach-specific struct */ + /* FIXME: watchpoints code shouldn't need this */ + { + SIM_CPU *current_cpu = STATE_CPU (sd, 0); + STATE_WATCHPOINTS (sd)->pc = &(PC); + STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); + } +#endif + + if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) + { + free_state (sd); + return 0; + } + +#if 0 /* FIXME: 'twould be nice if we could do this */ + /* These options override any module options. + Obviously ambiguity should be avoided, however the caller may wish to + augment the meaning of an option. */ + if (extra_options != NULL) + sim_add_option_table (sd, extra_options); +#endif + + /* getopt will print the error message so we just have to exit if this fails. + FIXME: Hmmm... in the case of gdb we need getopt to call + print_filtered. */ + if (sim_parse_args (sd, argv) != SIM_RC_OK) + { + free_state (sd); + return 0; + } + + /* Allocate core managed memory. */ + sim_do_commandf (sd, "memory region 0x%lx,0x%lx", IQ2000_INSN_VALUE, IQ2000_INSN_MEM_SIZE); + sim_do_commandf (sd, "memory region 0x%lx,0x%lx", IQ2000_DATA_VALUE, IQ2000_DATA_MEM_SIZE); + + /* check for/establish the reference program image */ + if (sim_analyze_program (sd, + (STATE_PROG_ARGV (sd) != NULL + ? *STATE_PROG_ARGV (sd) + : NULL), + abfd) != SIM_RC_OK) + { + free_state (sd); + return 0; + } + + /* Establish any remaining configuration options. */ + if (sim_config (sd) != SIM_RC_OK) + { + free_state (sd); + return 0; + } + + if (sim_post_argv_init (sd) != SIM_RC_OK) + { + free_state (sd); + return 0; + } + + /* Open a copy of the cpu descriptor table. */ + { + CGEN_CPU_DESC cd = iq2000_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name, + CGEN_ENDIAN_BIG); + + for (i = 0; i < MAX_NR_PROCESSORS; ++i) + { + SIM_CPU *cpu = STATE_CPU (sd, i); + CPU_CPU_DESC (cpu) = cd; + CPU_DISASSEMBLER (cpu) = iq2000bf_disassemble_insn; + } + iq2000_cgen_init_dis (cd); + } + + /* Initialize various cgen things not done by common framework. + Must be done after iq2000_cgen_cpu_open. */ + cgen_init (sd); + + /* Store in a global so things like sparc32_dump_regs can be invoked + from the gdb command line. */ + current_state = sd; + + return sd; +} + +void +sim_close (sd, quitting) + SIM_DESC sd; + int quitting; +{ + iq2000_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0))); + sim_module_uninstall (sd); +} + +SIM_RC +sim_create_inferior (sd, abfd, argv, envp) + SIM_DESC sd; + struct bfd *abfd; + char **argv; + char **envp; +{ + SIM_CPU *current_cpu = STATE_CPU (sd, 0); + SIM_ADDR addr; + + if (abfd != NULL) + addr = bfd_get_start_address (abfd); + else + addr = CPU2INSN(0); + sim_pc_set (current_cpu, addr); + +#if 0 + STATE_ARGV (sd) = sim_copy_argv (argv); + STATE_ENVP (sd) = sim_copy_argv (envp); +#endif + + return SIM_RC_OK; +} + +void +sim_do_command (sd, cmd) + SIM_DESC sd; + char *cmd; +{ + if (sim_args_command (sd, cmd) != SIM_RC_OK) + sim_io_eprintf (sd, "Unknown command `%s'\n", cmd); +} + + +

sim-if.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: sem.c =================================================================== --- sem.c (nonexistent) +++ sem.c (revision 33) @@ -0,0 +1,3543 @@ +/* Simulator instruction semantics for iq2000bf. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +*/ + +#define WANT_CPU iq2000bf +#define WANT_CPU_IQ2000BF + +#include "sim-main.h" +#include "cgen-mem.h" +#include "cgen-ops.h" + +#undef GET_ATTR +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) +#else +#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr) +#endif + +/* This is used so that we can compile two copies of the semantic code, + one with full feature support and one without that runs fast(er). + FAST_P, when desired, is defined on the command line, -DFAST_P=1. */ +#if FAST_P +#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn) +#undef TRACE_RESULT +#define TRACE_RESULT(cpu, abuf, name, type, val) +#else +#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn) +#endif + +/* x-invalid: --invalid-- */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { + /* Update the recorded pc in the cpu state struct. + Only necessary for WITH_SCACHE case, but to avoid the + conditional compilation .... */ + SET_H_PC (pc); + /* Virtual insns have zero size. Overwrite vpc with address of next insn + using the default-insn-bitsize spec. When executing insns in parallel + we may want to queue the fault and continue execution. */ + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + vpc = sim_engine_invalid_insn (current_cpu, pc, vpc); + } + + return vpc; +#undef FLD +} + +/* x-after: --after-- */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_IQ2000BF + iq2000bf_pbb_after (current_cpu, sem_arg); +#endif + } + + return vpc; +#undef FLD +} + +/* x-before: --before-- */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_IQ2000BF + iq2000bf_pbb_before (current_cpu, sem_arg); +#endif + } + + return vpc; +#undef FLD +} + +/* x-cti-chain: --cti-chain-- */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_IQ2000BF +#ifdef DEFINE_SWITCH + vpc = iq2000bf_pbb_cti_chain (current_cpu, sem_arg, + pbb_br_type, pbb_br_npc); + BREAK (sem); +#else + /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ + vpc = iq2000bf_pbb_cti_chain (current_cpu, sem_arg, + CPU_PBB_BR_TYPE (current_cpu), + CPU_PBB_BR_NPC (current_cpu)); +#endif +#endif + } + + return vpc; +#undef FLD +} + +/* x-chain: --chain-- */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_IQ2000BF + vpc = iq2000bf_pbb_chain (current_cpu, sem_arg); +#ifdef DEFINE_SWITCH + BREAK (sem); +#endif +#endif + } + + return vpc; +#undef FLD +} + +/* x-begin: --begin-- */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_IQ2000BF +#if defined DEFINE_SWITCH || defined FAST_P + /* In the switch case FAST_P is a constant, allowing several optimizations + in any called inline functions. */ + vpc = iq2000bf_pbb_begin (current_cpu, FAST_P); +#else +#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */ + vpc = iq2000bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); +#else + vpc = iq2000bf_pbb_begin (current_cpu, 0); +#endif +#endif +#endif + } + + return vpc; +#undef FLD +} + +/* add: add $rd,$rs,$rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrgb.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ADDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* addi: addi $rt,$rs,$lo16 */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* addiu: addiu $rt,$rs,$lo16 */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,addiu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* addu: addu $rd,$rs,$rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,addu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrgb.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ADDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ado16: ado16 $rd,$rs,$rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,ado16) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrgb.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + HI tmp_high; + HI tmp_low; + tmp_low = ADDHI (ANDHI (GET_H_GR (FLD (f_rs)), 65535), ANDHI (GET_H_GR (FLD (f_rt)), 65535)); + tmp_high = ADDHI (SRLSI (GET_H_GR (FLD (f_rs)), 16), SRLSI (GET_H_GR (FLD (f_rt)), 16)); + { + SI opval = ORSI (SLLSI (tmp_high, 16), tmp_low); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* and: and $rd,$rs,$rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrgb.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ANDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* andi: andi $rt,$rs,$lo16 */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,andi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ANDSI (GET_H_GR (FLD (f_rs)), ZEXTSISI (FLD (f_imm))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* andoi: andoi $rt,$rs,$lo16 */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,andoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ANDSI (GET_H_GR (FLD (f_rs)), ORSI (0xffff0000, EXTHISI (TRUNCSIHI (FLD (f_imm))))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* nor: nor $rd,$rs,$rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,nor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrgb.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = INVSI (ORSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* or: or $rd,$rs,$rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrgb.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ORSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ori: ori $rt,$rs,$lo16 */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,ori) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ORSI (GET_H_GR (FLD (f_rs)), ZEXTSISI (FLD (f_imm))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ram: ram $rd,$rt,$shamt,$maskl,$maskr */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,ram) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ram.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + SI opval = RORSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + SI opval = ANDSI (GET_H_GR (FLD (f_rd)), SRLSI (0xffffffff, FLD (f_maskl))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + SI opval = ANDSI (GET_H_GR (FLD (f_rd)), SLLSI (0xffffffff, FLD (f_rs))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* sll: sll $rd,$rt,$shamt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ram.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SLLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* sllv: sllv $rd,$rt,$rs */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,sllv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrgb.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SLLSI (GET_H_GR (FLD (f_rt)), ANDSI (GET_H_GR (FLD (f_rs)), 31)); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* slmv: slmv $rd,$rt,$rs,$shamt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,slmv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ram.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ANDSI (SLLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)), SRLSI (0xffffffff, GET_H_GR (FLD (f_rs)))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* slt: slt $rd,$rs,$rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,slt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrgb.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LTSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { + { + SI opval = 1; + SET_H_GR (FLD (f_rd), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} else { + { + SI opval = 0; + SET_H_GR (FLD (f_rd), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* slti: slti $rt,$rs,$imm */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,slti) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LTSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))))) { + { + SI opval = 1; + SET_H_GR (FLD (f_rt), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} else { + { + SI opval = 0; + SET_H_GR (FLD (f_rt), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* sltiu: sltiu $rt,$rs,$imm */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,sltiu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LTUSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))))) { + { + SI opval = 1; + SET_H_GR (FLD (f_rt), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} else { + { + SI opval = 0; + SET_H_GR (FLD (f_rt), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* sltu: sltu $rd,$rs,$rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,sltu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrgb.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LTUSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { + { + SI opval = 1; + SET_H_GR (FLD (f_rd), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} else { + { + SI opval = 0; + SET_H_GR (FLD (f_rd), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* sra: sra $rd,$rt,$shamt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ram.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SRASI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* srav: srav $rd,$rt,$rs */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,srav) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrgb.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SRASI (GET_H_GR (FLD (f_rt)), ANDSI (GET_H_GR (FLD (f_rs)), 31)); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* srl: srl $rd,$rt,$shamt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ram.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SRLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* srlv: srlv $rd,$rt,$rs */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,srlv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrgb.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SRLSI (GET_H_GR (FLD (f_rt)), ANDSI (GET_H_GR (FLD (f_rs)), 31)); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* srmv: srmv $rd,$rt,$rs,$shamt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,srmv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ram.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ANDSI (SRLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)), SLLSI (0xffffffff, GET_H_GR (FLD (f_rs)))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* sub: sub $rd,$rs,$rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrgb.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SUBSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* subu: subu $rd,$rs,$rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,subu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrgb.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SUBSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* xor: xor $rd,$rs,$rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrgb.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = XORSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* xori: xori $rt,$rs,$lo16 */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,xori) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = XORSI (GET_H_GR (FLD (f_rs)), ZEXTSISI (FLD (f_imm))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* bbi: bbi $rs($bitnum),$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, FLD (f_rt)))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bbin: bbin $rs($bitnum),$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bbin) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTSI (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, FLD (f_rt))))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bbv: bbv $rs,$rt,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bbv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, ANDSI (GET_H_GR (FLD (f_rt)), 31)))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bbvn: bbvn $rs,$rt,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bbvn) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NOTSI (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, ANDSI (GET_H_GR (FLD (f_rt)), 31))))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* beq: beq $rs,$rt,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* beql: beql $rs,$rt,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,beql) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (1) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bgez: bgez $rs,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (GESI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bgezal: bgezal $rs,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bgezal) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (GESI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + SI opval = ADDSI (pc, 8); + SET_H_GR (((UINT) 31), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bgezall: bgezall $rs,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bgezall) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (GESI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + SI opval = ADDSI (pc, 8); + SET_H_GR (((UINT) 31), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} else { +if (1) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bgezl: bgezl $rs,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bgezl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (GESI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (1) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bltz: bltz $rs,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LTSI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bltzl: bltzl $rs,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bltzl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LTSI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (1) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bltzal: bltzal $rs,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bltzal) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LTSI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + SI opval = ADDSI (pc, 8); + SET_H_GR (((UINT) 31), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bltzall: bltzall $rs,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bltzall) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LTSI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + SI opval = ADDSI (pc, 8); + SET_H_GR (((UINT) 31), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} else { +if (1) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bmb0: bmb0 $rs,$rt,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bmb0) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 255), ANDSI (GET_H_GR (FLD (f_rt)), 255))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bmb1: bmb1 $rs,$rt,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bmb1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 65280), ANDSI (GET_H_GR (FLD (f_rt)), 65280))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bmb2: bmb2 $rs,$rt,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bmb2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 16711680), ANDSI (GET_H_GR (FLD (f_rt)), 16711680))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bmb3: bmb3 $rs,$rt,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bmb3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 0xff000000), ANDSI (GET_H_GR (FLD (f_rt)), 0xff000000))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bne: bne $rs,$rt,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bnel: bnel $rs,$rt,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bnel) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (NESI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (1) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jalr: jalr $rd,$rs */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,jalr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrgb.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +{ + { + SI opval = ADDSI (pc, 8); + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = GET_H_GR (FLD (f_rs)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jr: jr $rs */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,jr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + USI opval = GET_H_GR (FLD (f_rs)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* lb: lb $rt,$lo16($base) */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,lb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* lbu: lbu $rt,$lo16($base) */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,lbu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* lh: lh $rt,$lo16($base) */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,lh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* lhu: lhu $rt,$lo16($base) */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,lhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* lui: lui $rt,$hi16 */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,lui) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = SLLSI (FLD (f_imm), 16); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* lw: lw $rt,$lo16($base) */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,lw) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))))); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* sb: sb $rt,$lo16($base) */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,sb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + QI opval = ANDQI (GET_H_GR (FLD (f_rt)), 255); + SETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* sh: sh $rt,$lo16($base) */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,sh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + HI opval = ANDHI (GET_H_GR (FLD (f_rt)), 65535); + SETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* sw: sw $rt,$lo16($base) */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,sw) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = GET_H_GR (FLD (f_rt)); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* break: break */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,break) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +do_break (current_cpu, pc); + + return vpc; +#undef FLD +} + +/* syscall: syscall */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,syscall) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +do_syscall (current_cpu); + + return vpc; +#undef FLD +} + +/* andoui: andoui $rt,$rs,$hi16 */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,andoui) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ANDSI (GET_H_GR (FLD (f_rs)), ORSI (SLLSI (FLD (f_imm), 16), 65535)); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* orui: orui $rt,$rs,$hi16 */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,orui) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ORSI (GET_H_GR (FLD (f_rs)), SLLSI (FLD (f_imm), 16)); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* bgtz: bgtz $rs,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (GTSI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bgtzl: bgtzl $rs,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bgtzl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (GTSI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (1) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* blez: blez $rs,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LESI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* blezl: blezl $rs,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,blezl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (LESI (GET_H_GR (FLD (f_rs)), 0)) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} else { +if (1) + SEM_SKIP_INSN (current_cpu, sem_arg, vpc); +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* mrgb: mrgb $rd,$rs,$rt,$mask */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,mrgb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrgb.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_temp; +if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 0)))) { + tmp_temp = ANDSI (GET_H_GR (FLD (f_rs)), 255); +} else { + tmp_temp = ANDSI (GET_H_GR (FLD (f_rt)), 255); +} +if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 1)))) { + tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rs)), 65280)); +} else { + tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rt)), 65280)); +} +if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 2)))) { + tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rs)), 16711680)); +} else { + tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rt)), 16711680)); +} +if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 3)))) { + tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rs)), 0xff000000)); +} else { + tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rt)), 0xff000000)); +} + { + SI opval = tmp_temp; + SET_H_GR (FLD (f_rd), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* bctxt: bctxt $rs,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bctxt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bc0f: bc0f $offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bc0f) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bc0fl: bc0fl $offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bc0fl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bc3f: bc3f $offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bc3f) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bc3fl: bc3fl $offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bc3fl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bc0t: bc0t $offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bc0t) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bc0tl: bc0tl $offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bc0tl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bc3t: bc3t $offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bc3t) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bc3tl: bc3tl $offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bc3tl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* cfc0: cfc0 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,cfc0) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* cfc1: cfc1 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,cfc1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* cfc2: cfc2 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,cfc2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* cfc3: cfc3 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,cfc3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* chkhdr: chkhdr $rd,$rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,chkhdr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* ctc0: ctc0 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,ctc0) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* ctc1: ctc1 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,ctc1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* ctc2: ctc2 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,ctc2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* ctc3: ctc3 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,ctc3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* jcr: jcr $rs */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,jcr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* luc32: luc32 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,luc32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* luc32l: luc32l $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,luc32l) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* luc64: luc64 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,luc64) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* luc64l: luc64l $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,luc64l) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* luk: luk $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,luk) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* lulck: lulck $rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,lulck) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* lum32: lum32 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,lum32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* lum32l: lum32l $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,lum32l) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* lum64: lum64 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,lum64) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* lum64l: lum64l $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,lum64l) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* lur: lur $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,lur) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* lurl: lurl $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,lurl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* luulck: luulck $rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,luulck) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* mfc0: mfc0 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,mfc0) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* mfc1: mfc1 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,mfc1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* mfc2: mfc2 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,mfc2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* mfc3: mfc3 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,mfc3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* mtc0: mtc0 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,mtc0) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* mtc1: mtc1 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,mtc1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* mtc2: mtc2 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,mtc2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* mtc3: mtc3 $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,mtc3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* pkrl: pkrl $rd,$rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,pkrl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* pkrlr1: pkrlr1 $rt,$index,$count */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,pkrlr1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* pkrlr30: pkrlr30 $rt,$index,$count */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,pkrlr30) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* rb: rb $rd,$rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,rb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* rbr1: rbr1 $rt,$index,$count */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,rbr1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* rbr30: rbr30 $rt,$index,$count */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,rbr30) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* rfe: rfe */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,rfe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* rx: rx $rd,$rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,rx) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* rxr1: rxr1 $rt,$index,$count */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,rxr1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* rxr30: rxr30 $rt,$index,$count */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,rxr30) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* sleep: sleep */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,sleep) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* srrd: srrd $rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,srrd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* srrdl: srrdl $rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,srrdl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* srulck: srulck $rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,srulck) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* srwr: srwr $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,srwr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* srwru: srwru $rt,$rd */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,srwru) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* trapqfl: trapqfl */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,trapqfl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* trapqne: trapqne */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,trapqne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* traprel: traprel $rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,traprel) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* wb: wb $rd,$rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,wb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* wbu: wbu $rd,$rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,wbu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* wbr1: wbr1 $rt,$index,$count */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,wbr1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* wbr1u: wbr1u $rt,$index,$count */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,wbr1u) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* wbr30: wbr30 $rt,$index,$count */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,wbr30) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* wbr30u: wbr30u $rt,$index,$count */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,wbr30u) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* wx: wx $rd,$rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,wx) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* wxu: wxu $rd,$rt */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,wxu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* wxr1: wxr1 $rt,$index,$count */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,wxr1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* wxr1u: wxr1u $rt,$index,$count */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,wxr1u) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* wxr30: wxr30 $rt,$index,$count */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,wxr30) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* wxr30u: wxr30u $rt,$index,$count */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,wxr30u) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* ldw: ldw $rt,$lo16($base) */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,ldw) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_addr; + tmp_addr = ANDSI (ADDSI (GET_H_GR (FLD (f_rs)), FLD (f_imm)), INVSI (3)); + { + SI opval = GETMEMSI (current_cpu, pc, tmp_addr); + SET_H_GR (ADDSI (FLD (f_rt), 1), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_addr, 4)); + SET_H_GR (FLD (f_rt), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* sdw: sdw $rt,$lo16($base) */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,sdw) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + SI tmp_addr; + tmp_addr = ANDSI (ADDSI (GET_H_GR (FLD (f_rs)), FLD (f_imm)), INVSI (3)); + { + SI opval = GET_H_GR (FLD (f_rt)); + SETMEMSI (current_cpu, pc, ADDSI (tmp_addr, 4), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + { + SI opval = GET_H_GR (ADDSI (FLD (f_rt), 1)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* j: j $jmptarg */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,j) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_j.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + { + USI opval = FLD (i_jmptarg); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jal: jal $jmptarg */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,jal) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_j.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +{ + { + SI opval = ADDSI (pc, 8); + SET_H_GR (((UINT) 31), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); + } + { + USI opval = FLD (i_jmptarg); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} + + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* bmb: bmb $rs,$rt,$offset */ + +static SEM_PC +SEM_FN_NAME (iq2000bf,bmb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bbi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + BI tmp_branch_; + tmp_branch_ = 0; +if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 255), ANDSI (GET_H_GR (FLD (f_rt)), 255))) { + tmp_branch_ = 1; +} +if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 65280), ANDSI (GET_H_GR (FLD (f_rt)), 65280))) { + tmp_branch_ = 1; +} +if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 16711680), ANDSI (GET_H_GR (FLD (f_rt)), 16711680))) { + tmp_branch_ = 1; +} +if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 0xff000000), ANDSI (GET_H_GR (FLD (f_rt)), 0xff000000))) { + tmp_branch_ = 1; +} +if (tmp_branch_) { +{ + { + USI opval = FLD (i_offset); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} +} +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* Table of all semantic fns. */ + +static const struct sem_fn_desc sem_fns[] = { + { IQ2000BF_INSN_X_INVALID, SEM_FN_NAME (iq2000bf,x_invalid) }, + { IQ2000BF_INSN_X_AFTER, SEM_FN_NAME (iq2000bf,x_after) }, + { IQ2000BF_INSN_X_BEFORE, SEM_FN_NAME (iq2000bf,x_before) }, + { IQ2000BF_INSN_X_CTI_CHAIN, SEM_FN_NAME (iq2000bf,x_cti_chain) }, + { IQ2000BF_INSN_X_CHAIN, SEM_FN_NAME (iq2000bf,x_chain) }, + { IQ2000BF_INSN_X_BEGIN, SEM_FN_NAME (iq2000bf,x_begin) }, + { IQ2000BF_INSN_ADD, SEM_FN_NAME (iq2000bf,add) }, + { IQ2000BF_INSN_ADDI, SEM_FN_NAME (iq2000bf,addi) }, + { IQ2000BF_INSN_ADDIU, SEM_FN_NAME (iq2000bf,addiu) }, + { IQ2000BF_INSN_ADDU, SEM_FN_NAME (iq2000bf,addu) }, + { IQ2000BF_INSN_ADO16, SEM_FN_NAME (iq2000bf,ado16) }, + { IQ2000BF_INSN_AND, SEM_FN_NAME (iq2000bf,and) }, + { IQ2000BF_INSN_ANDI, SEM_FN_NAME (iq2000bf,andi) }, + { IQ2000BF_INSN_ANDOI, SEM_FN_NAME (iq2000bf,andoi) }, + { IQ2000BF_INSN_NOR, SEM_FN_NAME (iq2000bf,nor) }, + { IQ2000BF_INSN_OR, SEM_FN_NAME (iq2000bf,or) }, + { IQ2000BF_INSN_ORI, SEM_FN_NAME (iq2000bf,ori) }, + { IQ2000BF_INSN_RAM, SEM_FN_NAME (iq2000bf,ram) }, + { IQ2000BF_INSN_SLL, SEM_FN_NAME (iq2000bf,sll) }, + { IQ2000BF_INSN_SLLV, SEM_FN_NAME (iq2000bf,sllv) }, + { IQ2000BF_INSN_SLMV, SEM_FN_NAME (iq2000bf,slmv) }, + { IQ2000BF_INSN_SLT, SEM_FN_NAME (iq2000bf,slt) }, + { IQ2000BF_INSN_SLTI, SEM_FN_NAME (iq2000bf,slti) }, + { IQ2000BF_INSN_SLTIU, SEM_FN_NAME (iq2000bf,sltiu) }, + { IQ2000BF_INSN_SLTU, SEM_FN_NAME (iq2000bf,sltu) }, + { IQ2000BF_INSN_SRA, SEM_FN_NAME (iq2000bf,sra) }, + { IQ2000BF_INSN_SRAV, SEM_FN_NAME (iq2000bf,srav) }, + { IQ2000BF_INSN_SRL, SEM_FN_NAME (iq2000bf,srl) }, + { IQ2000BF_INSN_SRLV, SEM_FN_NAME (iq2000bf,srlv) }, + { IQ2000BF_INSN_SRMV, SEM_FN_NAME (iq2000bf,srmv) }, + { IQ2000BF_INSN_SUB, SEM_FN_NAME (iq2000bf,sub) }, + { IQ2000BF_INSN_SUBU, SEM_FN_NAME (iq2000bf,subu) }, + { IQ2000BF_INSN_XOR, SEM_FN_NAME (iq2000bf,xor) }, + { IQ2000BF_INSN_XORI, SEM_FN_NAME (iq2000bf,xori) }, + { IQ2000BF_INSN_BBI, SEM_FN_NAME (iq2000bf,bbi) }, + { IQ2000BF_INSN_BBIN, SEM_FN_NAME (iq2000bf,bbin) }, + { IQ2000BF_INSN_BBV, SEM_FN_NAME (iq2000bf,bbv) }, + { IQ2000BF_INSN_BBVN, SEM_FN_NAME (iq2000bf,bbvn) }, + { IQ2000BF_INSN_BEQ, SEM_FN_NAME (iq2000bf,beq) }, + { IQ2000BF_INSN_BEQL, SEM_FN_NAME (iq2000bf,beql) }, + { IQ2000BF_INSN_BGEZ, SEM_FN_NAME (iq2000bf,bgez) }, + { IQ2000BF_INSN_BGEZAL, SEM_FN_NAME (iq2000bf,bgezal) }, + { IQ2000BF_INSN_BGEZALL, SEM_FN_NAME (iq2000bf,bgezall) }, + { IQ2000BF_INSN_BGEZL, SEM_FN_NAME (iq2000bf,bgezl) }, + { IQ2000BF_INSN_BLTZ, SEM_FN_NAME (iq2000bf,bltz) }, + { IQ2000BF_INSN_BLTZL, SEM_FN_NAME (iq2000bf,bltzl) }, + { IQ2000BF_INSN_BLTZAL, SEM_FN_NAME (iq2000bf,bltzal) }, + { IQ2000BF_INSN_BLTZALL, SEM_FN_NAME (iq2000bf,bltzall) }, + { IQ2000BF_INSN_BMB0, SEM_FN_NAME (iq2000bf,bmb0) }, + { IQ2000BF_INSN_BMB1, SEM_FN_NAME (iq2000bf,bmb1) }, + { IQ2000BF_INSN_BMB2, SEM_FN_NAME (iq2000bf,bmb2) }, + { IQ2000BF_INSN_BMB3, SEM_FN_NAME (iq2000bf,bmb3) }, + { IQ2000BF_INSN_BNE, SEM_FN_NAME (iq2000bf,bne) }, + { IQ2000BF_INSN_BNEL, SEM_FN_NAME (iq2000bf,bnel) }, + { IQ2000BF_INSN_JALR, SEM_FN_NAME (iq2000bf,jalr) }, + { IQ2000BF_INSN_JR, SEM_FN_NAME (iq2000bf,jr) }, + { IQ2000BF_INSN_LB, SEM_FN_NAME (iq2000bf,lb) }, + { IQ2000BF_INSN_LBU, SEM_FN_NAME (iq2000bf,lbu) }, + { IQ2000BF_INSN_LH, SEM_FN_NAME (iq2000bf,lh) }, + { IQ2000BF_INSN_LHU, SEM_FN_NAME (iq2000bf,lhu) }, + { IQ2000BF_INSN_LUI, SEM_FN_NAME (iq2000bf,lui) }, + { IQ2000BF_INSN_LW, SEM_FN_NAME (iq2000bf,lw) }, + { IQ2000BF_INSN_SB, SEM_FN_NAME (iq2000bf,sb) }, + { IQ2000BF_INSN_SH, SEM_FN_NAME (iq2000bf,sh) }, + { IQ2000BF_INSN_SW, SEM_FN_NAME (iq2000bf,sw) }, + { IQ2000BF_INSN_BREAK, SEM_FN_NAME (iq2000bf,break) }, + { IQ2000BF_INSN_SYSCALL, SEM_FN_NAME (iq2000bf,syscall) }, + { IQ2000BF_INSN_ANDOUI, SEM_FN_NAME (iq2000bf,andoui) }, + { IQ2000BF_INSN_ORUI, SEM_FN_NAME (iq2000bf,orui) }, + { IQ2000BF_INSN_BGTZ, SEM_FN_NAME (iq2000bf,bgtz) }, + { IQ2000BF_INSN_BGTZL, SEM_FN_NAME (iq2000bf,bgtzl) }, + { IQ2000BF_INSN_BLEZ, SEM_FN_NAME (iq2000bf,blez) }, + { IQ2000BF_INSN_BLEZL, SEM_FN_NAME (iq2000bf,blezl) }, + { IQ2000BF_INSN_MRGB, SEM_FN_NAME (iq2000bf,mrgb) }, + { IQ2000BF_INSN_BCTXT, SEM_FN_NAME (iq2000bf,bctxt) }, + { IQ2000BF_INSN_BC0F, SEM_FN_NAME (iq2000bf,bc0f) }, + { IQ2000BF_INSN_BC0FL, SEM_FN_NAME (iq2000bf,bc0fl) }, + { IQ2000BF_INSN_BC3F, SEM_FN_NAME (iq2000bf,bc3f) }, + { IQ2000BF_INSN_BC3FL, SEM_FN_NAME (iq2000bf,bc3fl) }, + { IQ2000BF_INSN_BC0T, SEM_FN_NAME (iq2000bf,bc0t) }, + { IQ2000BF_INSN_BC0TL, SEM_FN_NAME (iq2000bf,bc0tl) }, + { IQ2000BF_INSN_BC3T, SEM_FN_NAME (iq2000bf,bc3t) }, + { IQ2000BF_INSN_BC3TL, SEM_FN_NAME (iq2000bf,bc3tl) }, + { IQ2000BF_INSN_CFC0, SEM_FN_NAME (iq2000bf,cfc0) }, + { IQ2000BF_INSN_CFC1, SEM_FN_NAME (iq2000bf,cfc1) }, + { IQ2000BF_INSN_CFC2, SEM_FN_NAME (iq2000bf,cfc2) }, + { IQ2000BF_INSN_CFC3, SEM_FN_NAME (iq2000bf,cfc3) }, + { IQ2000BF_INSN_CHKHDR, SEM_FN_NAME (iq2000bf,chkhdr) }, + { IQ2000BF_INSN_CTC0, SEM_FN_NAME (iq2000bf,ctc0) }, + { IQ2000BF_INSN_CTC1, SEM_FN_NAME (iq2000bf,ctc1) }, + { IQ2000BF_INSN_CTC2, SEM_FN_NAME (iq2000bf,ctc2) }, + { IQ2000BF_INSN_CTC3, SEM_FN_NAME (iq2000bf,ctc3) }, + { IQ2000BF_INSN_JCR, SEM_FN_NAME (iq2000bf,jcr) }, + { IQ2000BF_INSN_LUC32, SEM_FN_NAME (iq2000bf,luc32) }, + { IQ2000BF_INSN_LUC32L, SEM_FN_NAME (iq2000bf,luc32l) }, + { IQ2000BF_INSN_LUC64, SEM_FN_NAME (iq2000bf,luc64) }, + { IQ2000BF_INSN_LUC64L, SEM_FN_NAME (iq2000bf,luc64l) }, + { IQ2000BF_INSN_LUK, SEM_FN_NAME (iq2000bf,luk) }, + { IQ2000BF_INSN_LULCK, SEM_FN_NAME (iq2000bf,lulck) }, + { IQ2000BF_INSN_LUM32, SEM_FN_NAME (iq2000bf,lum32) }, + { IQ2000BF_INSN_LUM32L, SEM_FN_NAME (iq2000bf,lum32l) }, + { IQ2000BF_INSN_LUM64, SEM_FN_NAME (iq2000bf,lum64) }, + { IQ2000BF_INSN_LUM64L, SEM_FN_NAME (iq2000bf,lum64l) }, + { IQ2000BF_INSN_LUR, SEM_FN_NAME (iq2000bf,lur) }, + { IQ2000BF_INSN_LURL, SEM_FN_NAME (iq2000bf,lurl) }, + { IQ2000BF_INSN_LUULCK, SEM_FN_NAME (iq2000bf,luulck) }, + { IQ2000BF_INSN_MFC0, SEM_FN_NAME (iq2000bf,mfc0) }, + { IQ2000BF_INSN_MFC1, SEM_FN_NAME (iq2000bf,mfc1) }, + { IQ2000BF_INSN_MFC2, SEM_FN_NAME (iq2000bf,mfc2) }, + { IQ2000BF_INSN_MFC3, SEM_FN_NAME (iq2000bf,mfc3) }, + { IQ2000BF_INSN_MTC0, SEM_FN_NAME (iq2000bf,mtc0) }, + { IQ2000BF_INSN_MTC1, SEM_FN_NAME (iq2000bf,mtc1) }, + { IQ2000BF_INSN_MTC2, SEM_FN_NAME (iq2000bf,mtc2) }, + { IQ2000BF_INSN_MTC3, SEM_FN_NAME (iq2000bf,mtc3) }, + { IQ2000BF_INSN_PKRL, SEM_FN_NAME (iq2000bf,pkrl) }, + { IQ2000BF_INSN_PKRLR1, SEM_FN_NAME (iq2000bf,pkrlr1) }, + { IQ2000BF_INSN_PKRLR30, SEM_FN_NAME (iq2000bf,pkrlr30) }, + { IQ2000BF_INSN_RB, SEM_FN_NAME (iq2000bf,rb) }, + { IQ2000BF_INSN_RBR1, SEM_FN_NAME (iq2000bf,rbr1) }, + { IQ2000BF_INSN_RBR30, SEM_FN_NAME (iq2000bf,rbr30) }, + { IQ2000BF_INSN_RFE, SEM_FN_NAME (iq2000bf,rfe) }, + { IQ2000BF_INSN_RX, SEM_FN_NAME (iq2000bf,rx) }, + { IQ2000BF_INSN_RXR1, SEM_FN_NAME (iq2000bf,rxr1) }, + { IQ2000BF_INSN_RXR30, SEM_FN_NAME (iq2000bf,rxr30) }, + { IQ2000BF_INSN_SLEEP, SEM_FN_NAME (iq2000bf,sleep) }, + { IQ2000BF_INSN_SRRD, SEM_FN_NAME (iq2000bf,srrd) }, + { IQ2000BF_INSN_SRRDL, SEM_FN_NAME (iq2000bf,srrdl) }, + { IQ2000BF_INSN_SRULCK, SEM_FN_NAME (iq2000bf,srulck) }, + { IQ2000BF_INSN_SRWR, SEM_FN_NAME (iq2000bf,srwr) }, + { IQ2000BF_INSN_SRWRU, SEM_FN_NAME (iq2000bf,srwru) }, + { IQ2000BF_INSN_TRAPQFL, SEM_FN_NAME (iq2000bf,trapqfl) }, + { IQ2000BF_INSN_TRAPQNE, SEM_FN_NAME (iq2000bf,trapqne) }, + { IQ2000BF_INSN_TRAPREL, SEM_FN_NAME (iq2000bf,traprel) }, + { IQ2000BF_INSN_WB, SEM_FN_NAME (iq2000bf,wb) }, + { IQ2000BF_INSN_WBU, SEM_FN_NAME (iq2000bf,wbu) }, + { IQ2000BF_INSN_WBR1, SEM_FN_NAME (iq2000bf,wbr1) }, + { IQ2000BF_INSN_WBR1U, SEM_FN_NAME (iq2000bf,wbr1u) }, + { IQ2000BF_INSN_WBR30, SEM_FN_NAME (iq2000bf,wbr30) }, + { IQ2000BF_INSN_WBR30U, SEM_FN_NAME (iq2000bf,wbr30u) }, + { IQ2000BF_INSN_WX, SEM_FN_NAME (iq2000bf,wx) }, + { IQ2000BF_INSN_WXU, SEM_FN_NAME (iq2000bf,wxu) }, + { IQ2000BF_INSN_WXR1, SEM_FN_NAME (iq2000bf,wxr1) }, + { IQ2000BF_INSN_WXR1U, SEM_FN_NAME (iq2000bf,wxr1u) }, + { IQ2000BF_INSN_WXR30, SEM_FN_NAME (iq2000bf,wxr30) }, + { IQ2000BF_INSN_WXR30U, SEM_FN_NAME (iq2000bf,wxr30u) }, + { IQ2000BF_INSN_LDW, SEM_FN_NAME (iq2000bf,ldw) }, + { IQ2000BF_INSN_SDW, SEM_FN_NAME (iq2000bf,sdw) }, + { IQ2000BF_INSN_J, SEM_FN_NAME (iq2000bf,j) }, + { IQ2000BF_INSN_JAL, SEM_FN_NAME (iq2000bf,jal) }, + { IQ2000BF_INSN_BMB, SEM_FN_NAME (iq2000bf,bmb) }, + { 0, 0 } +}; + +/* Add the semantic fns to IDESC_TABLE. */ + +void +SEM_FN_NAME (iq2000bf,init_idesc_table) (SIM_CPU *current_cpu) +{ + IDESC *idesc_table = CPU_IDESC (current_cpu); + const struct sem_fn_desc *sf; + int mach_num = MACH_NUM (CPU_MACH (current_cpu)); + + for (sf = &sem_fns[0]; sf->fn != 0; ++sf) + { + const CGEN_INSN *insn = idesc_table[sf->index].idata; + int valid_p = (CGEN_INSN_VIRTUAL_P (insn) + || CGEN_INSN_MACH_HAS_P (insn, mach_num)); +#if FAST_P + if (valid_p) + idesc_table[sf->index].sem_fast = sf->fn; + else + idesc_table[sf->index].sem_fast = SEM_FN_NAME (iq2000bf,x_invalid); +#else + if (valid_p) + idesc_table[sf->index].sem_full = sf->fn; + else + idesc_table[sf->index].sem_full = SEM_FN_NAME (iq2000bf,x_invalid); +#endif + } +} +

sem.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: cpuall.h =================================================================== --- cpuall.h (nonexistent) +++ cpuall.h (revision 33) @@ -0,0 +1,72 @@ +/* Simulator CPU header for iq2000. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +*/ + +#ifndef IQ2000_CPUALL_H +#define IQ2000_CPUALL_H + +/* Include files for each cpu family. */ + +#ifdef WANT_CPU_IQ2000BF +#include "eng.h" +#include "cgen-engine.h" +#include "cpu.h" +#include "decode.h" +#endif + +#ifdef WANT_CPU_IQ10BF +#include "eng.h" +#include "cgen-engine.h" +#include "cpu.h" +#include "decode.h" +#endif + +extern const MACH iq2000_mach; + +#ifndef WANT_CPU +/* The ARGBUF struct. */ +struct argbuf { + /* These are the baseclass definitions. */ + IADDR addr; + const IDESC *idesc; + char trace_p; + char profile_p; + /* ??? Temporary hack for skip insns. */ + char skip_count; + char unused; + /* cpu specific data follows */ +}; +#endif + +#ifndef WANT_CPU +/* A cached insn. + + ??? SCACHE used to contain more than just argbuf. We could delete the + type entirely and always just use ARGBUF, but for future concerns and as + a level of abstraction it is left in. */ + +struct scache { + struct argbuf argbuf; +}; +#endif + +#endif /* IQ2000_CPUALL_H */

cpuall.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: cpu.c =================================================================== --- cpu.c (nonexistent) +++ cpu.c (revision 33) @@ -0,0 +1,68 @@ +/* Misc. support for CPU family iq2000bf. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +*/ + +#define WANT_CPU iq2000bf +#define WANT_CPU_IQ2000BF + +#include "sim-main.h" +#include "cgen-ops.h" + +/* Get the value of h-pc. */ + +USI +iq2000bf_h_pc_get (SIM_CPU *current_cpu) +{ + return GET_H_PC (); +} + +/* Set a value for h-pc. */ + +void +iq2000bf_h_pc_set (SIM_CPU *current_cpu, USI newval) +{ + SET_H_PC (newval); +} + +/* Get the value of h-gr. */ + +SI +iq2000bf_h_gr_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_GR (regno); +} + +/* Set a value for h-gr. */ + +void +iq2000bf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) +{ + SET_H_GR (regno, newval); +} + +/* Record trace results for INSN. */ + +void +iq2000bf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn, + int *indices, TRACE_RECORD *tr) +{ +}

cpu.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: decode.h =================================================================== --- decode.h (nonexistent) +++ decode.h (revision 33) @@ -0,0 +1,97 @@ +/* Decode header for iq2000bf. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +*/ + +#ifndef IQ2000BF_DECODE_H +#define IQ2000BF_DECODE_H + +extern const IDESC *iq2000bf_decode (SIM_CPU *, IADDR, + CGEN_INSN_INT, CGEN_INSN_INT, + ARGBUF *); +extern void iq2000bf_init_idesc_table (SIM_CPU *); +extern void iq2000bf_sem_init_idesc_table (SIM_CPU *); +extern void iq2000bf_semf_init_idesc_table (SIM_CPU *); + +/* Enum declaration for instructions in cpu family iq2000bf. */ +typedef enum iq2000bf_insn_type { + IQ2000BF_INSN_X_INVALID, IQ2000BF_INSN_X_AFTER, IQ2000BF_INSN_X_BEFORE, IQ2000BF_INSN_X_CTI_CHAIN + , IQ2000BF_INSN_X_CHAIN, IQ2000BF_INSN_X_BEGIN, IQ2000BF_INSN_ADD, IQ2000BF_INSN_ADDI + , IQ2000BF_INSN_ADDIU, IQ2000BF_INSN_ADDU, IQ2000BF_INSN_ADO16, IQ2000BF_INSN_AND + , IQ2000BF_INSN_ANDI, IQ2000BF_INSN_ANDOI, IQ2000BF_INSN_NOR, IQ2000BF_INSN_OR + , IQ2000BF_INSN_ORI, IQ2000BF_INSN_RAM, IQ2000BF_INSN_SLL, IQ2000BF_INSN_SLLV + , IQ2000BF_INSN_SLMV, IQ2000BF_INSN_SLT, IQ2000BF_INSN_SLTI, IQ2000BF_INSN_SLTIU + , IQ2000BF_INSN_SLTU, IQ2000BF_INSN_SRA, IQ2000BF_INSN_SRAV, IQ2000BF_INSN_SRL + , IQ2000BF_INSN_SRLV, IQ2000BF_INSN_SRMV, IQ2000BF_INSN_SUB, IQ2000BF_INSN_SUBU + , IQ2000BF_INSN_XOR, IQ2000BF_INSN_XORI, IQ2000BF_INSN_BBI, IQ2000BF_INSN_BBIN + , IQ2000BF_INSN_BBV, IQ2000BF_INSN_BBVN, IQ2000BF_INSN_BEQ, IQ2000BF_INSN_BEQL + , IQ2000BF_INSN_BGEZ, IQ2000BF_INSN_BGEZAL, IQ2000BF_INSN_BGEZALL, IQ2000BF_INSN_BGEZL + , IQ2000BF_INSN_BLTZ, IQ2000BF_INSN_BLTZL, IQ2000BF_INSN_BLTZAL, IQ2000BF_INSN_BLTZALL + , IQ2000BF_INSN_BMB0, IQ2000BF_INSN_BMB1, IQ2000BF_INSN_BMB2, IQ2000BF_INSN_BMB3 + , IQ2000BF_INSN_BNE, IQ2000BF_INSN_BNEL, IQ2000BF_INSN_JALR, IQ2000BF_INSN_JR + , IQ2000BF_INSN_LB, IQ2000BF_INSN_LBU, IQ2000BF_INSN_LH, IQ2000BF_INSN_LHU + , IQ2000BF_INSN_LUI, IQ2000BF_INSN_LW, IQ2000BF_INSN_SB, IQ2000BF_INSN_SH + , IQ2000BF_INSN_SW, IQ2000BF_INSN_BREAK, IQ2000BF_INSN_SYSCALL, IQ2000BF_INSN_ANDOUI + , IQ2000BF_INSN_ORUI, IQ2000BF_INSN_BGTZ, IQ2000BF_INSN_BGTZL, IQ2000BF_INSN_BLEZ + , IQ2000BF_INSN_BLEZL, IQ2000BF_INSN_MRGB, IQ2000BF_INSN_BCTXT, IQ2000BF_INSN_BC0F + , IQ2000BF_INSN_BC0FL, IQ2000BF_INSN_BC3F, IQ2000BF_INSN_BC3FL, IQ2000BF_INSN_BC0T + , IQ2000BF_INSN_BC0TL, IQ2000BF_INSN_BC3T, IQ2000BF_INSN_BC3TL, IQ2000BF_INSN_CFC0 + , IQ2000BF_INSN_CFC1, IQ2000BF_INSN_CFC2, IQ2000BF_INSN_CFC3, IQ2000BF_INSN_CHKHDR + , IQ2000BF_INSN_CTC0, IQ2000BF_INSN_CTC1, IQ2000BF_INSN_CTC2, IQ2000BF_INSN_CTC3 + , IQ2000BF_INSN_JCR, IQ2000BF_INSN_LUC32, IQ2000BF_INSN_LUC32L, IQ2000BF_INSN_LUC64 + , IQ2000BF_INSN_LUC64L, IQ2000BF_INSN_LUK, IQ2000BF_INSN_LULCK, IQ2000BF_INSN_LUM32 + , IQ2000BF_INSN_LUM32L, IQ2000BF_INSN_LUM64, IQ2000BF_INSN_LUM64L, IQ2000BF_INSN_LUR + , IQ2000BF_INSN_LURL, IQ2000BF_INSN_LUULCK, IQ2000BF_INSN_MFC0, IQ2000BF_INSN_MFC1 + , IQ2000BF_INSN_MFC2, IQ2000BF_INSN_MFC3, IQ2000BF_INSN_MTC0, IQ2000BF_INSN_MTC1 + , IQ2000BF_INSN_MTC2, IQ2000BF_INSN_MTC3, IQ2000BF_INSN_PKRL, IQ2000BF_INSN_PKRLR1 + , IQ2000BF_INSN_PKRLR30, IQ2000BF_INSN_RB, IQ2000BF_INSN_RBR1, IQ2000BF_INSN_RBR30 + , IQ2000BF_INSN_RFE, IQ2000BF_INSN_RX, IQ2000BF_INSN_RXR1, IQ2000BF_INSN_RXR30 + , IQ2000BF_INSN_SLEEP, IQ2000BF_INSN_SRRD, IQ2000BF_INSN_SRRDL, IQ2000BF_INSN_SRULCK + , IQ2000BF_INSN_SRWR, IQ2000BF_INSN_SRWRU, IQ2000BF_INSN_TRAPQFL, IQ2000BF_INSN_TRAPQNE + , IQ2000BF_INSN_TRAPREL, IQ2000BF_INSN_WB, IQ2000BF_INSN_WBU, IQ2000BF_INSN_WBR1 + , IQ2000BF_INSN_WBR1U, IQ2000BF_INSN_WBR30, IQ2000BF_INSN_WBR30U, IQ2000BF_INSN_WX + , IQ2000BF_INSN_WXU, IQ2000BF_INSN_WXR1, IQ2000BF_INSN_WXR1U, IQ2000BF_INSN_WXR30 + , IQ2000BF_INSN_WXR30U, IQ2000BF_INSN_LDW, IQ2000BF_INSN_SDW, IQ2000BF_INSN_J + , IQ2000BF_INSN_JAL, IQ2000BF_INSN_BMB, IQ2000BF_INSN_MAX +} IQ2000BF_INSN_TYPE; + +/* Enum declaration for semantic formats in cpu family iq2000bf. */ +typedef enum iq2000bf_sfmt_type { + IQ2000BF_SFMT_EMPTY, IQ2000BF_SFMT_ADD, IQ2000BF_SFMT_ADDI, IQ2000BF_SFMT_ADO16 + , IQ2000BF_SFMT_RAM, IQ2000BF_SFMT_SLL, IQ2000BF_SFMT_SLMV, IQ2000BF_SFMT_SLT + , IQ2000BF_SFMT_SLTI, IQ2000BF_SFMT_BBI, IQ2000BF_SFMT_BBV, IQ2000BF_SFMT_BGEZ + , IQ2000BF_SFMT_BGEZAL, IQ2000BF_SFMT_JALR, IQ2000BF_SFMT_JR, IQ2000BF_SFMT_LB + , IQ2000BF_SFMT_LH, IQ2000BF_SFMT_LUI, IQ2000BF_SFMT_LW, IQ2000BF_SFMT_SB + , IQ2000BF_SFMT_SH, IQ2000BF_SFMT_SW, IQ2000BF_SFMT_BREAK, IQ2000BF_SFMT_SYSCALL + , IQ2000BF_SFMT_ANDOUI, IQ2000BF_SFMT_MRGB, IQ2000BF_SFMT_BCTXT, IQ2000BF_SFMT_LDW + , IQ2000BF_SFMT_SDW, IQ2000BF_SFMT_J, IQ2000BF_SFMT_JAL +} IQ2000BF_SFMT_TYPE; + +/* Function unit handlers (user written). */ + +extern int iq2000bf_model_iq2000_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); + +/* Profiling before/after handlers (user written) */ + +extern void iq2000bf_model_insn_before (SIM_CPU *, int /*first_p*/); +extern void iq2000bf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/); + +#endif /* IQ2000BF_DECODE_H */

decode.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: config.in =================================================================== --- config.in (nonexistent) +++ config.in (revision 33) @@ -0,0 +1,96 @@ +/* config.in. Generated from configure.ac by autoheader. */ + +/* Define to 1 if translation of program messages to the user's native + language is requested. */ +#undef ENABLE_NLS + +/* Define to 1 if you have the header file. */ +#undef HAVE_DLFCN_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_ERRNO_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_FCNTL_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_FPU_CONTROL_H + +/* Define to 1 if you have the `getrusage' function. */ +#undef HAVE_GETRUSAGE + +/* Define to 1 if you have the header file. */ +#undef HAVE_INTTYPES_H + +/* Define to 1 if you have the `nsl' library (-lnsl). */ +#undef HAVE_LIBNSL + +/* Define to 1 if you have the `socket' library (-lsocket). */ +#undef HAVE_LIBSOCKET + +/* Define to 1 if you have the header file. */ +#undef HAVE_MEMORY_H + +/* Define to 1 if you have the `sigaction' function. */ +#undef HAVE_SIGACTION + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDINT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDLIB_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRINGS_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRING_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_RESOURCE_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_STAT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TIME_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TYPES_H + +/* Define to 1 if you have the `time' function. */ +#undef HAVE_TIME + +/* Define to 1 if you have the header file. */ +#undef HAVE_TIME_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_UNISTD_H + +/* Define to 1 if you have the `__setfpucw' function. */ +#undef HAVE___SETFPUCW + +/* Define to the address where bug reports for this package should be sent. */ +#undef PACKAGE_BUGREPORT + +/* Define to the full name of this package. */ +#undef PACKAGE_NAME + +/* Define to the full name and version of this package. */ +#undef PACKAGE_STRING + +/* Define to the one symbol short name of this package. */ +#undef PACKAGE_TARNAME + +/* Define to the version of this package. */ +#undef PACKAGE_VERSION + +/* Define as the return type of signal handlers (`int' or `void'). */ +#undef RETSIGTYPE + +/* Define to 1 if you have the ANSI C header files. */ +#undef STDC_HEADERS + +/* Define to 1 if your processor stores words with the most significant byte + first (like Motorola and SPARC, unlike Intel and VAX). */ +#undef WORDS_BIGENDIAN Index: cpu.h =================================================================== --- cpu.h (nonexistent) +++ cpu.h (revision 33) @@ -0,0 +1,530 @@ +/* CPU family header for iq2000bf. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +*/ + +#ifndef CPU_IQ2000BF_H +#define CPU_IQ2000BF_H + +/* Maximum number of instructions that are fetched at a time. + This is for LIW type instructions sets (e.g. m32r). */ +#define MAX_LIW_INSNS 1 + +/* Maximum number of instructions that can be executed in parallel. */ +#define MAX_PARALLEL_INSNS 1 + +/* CPU state information. */ +typedef struct { + /* Hardware elements. */ + struct { + /* program counter */ + USI h_pc; +#define GET_H_PC() get_h_pc (current_cpu) +#define SET_H_PC(x) \ +do { \ +set_h_pc (current_cpu, (x));\ +;} while (0) + /* General purpose registers */ + SI h_gr[32]; +#define GET_H_GR(index) (((index) == (0))) ? (0) : (CPU (h_gr[index])) +#define SET_H_GR(index, x) \ +do { \ +if ((((index)) == (0))) {\ +((void) 0); /*nop*/\ +}\ + else {\ +CPU (h_gr[(index)]) = (x);\ +}\ +;} while (0) + } hardware; +#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) +} IQ2000BF_CPU_DATA; + +/* Cover fns for register access. */ +USI iq2000bf_h_pc_get (SIM_CPU *); +void iq2000bf_h_pc_set (SIM_CPU *, USI); +SI iq2000bf_h_gr_get (SIM_CPU *, UINT); +void iq2000bf_h_gr_set (SIM_CPU *, UINT, SI); + +/* These must be hand-written. */ +extern CPUREG_FETCH_FN iq2000bf_fetch_register; +extern CPUREG_STORE_FN iq2000bf_store_register; + +typedef struct { + int empty; +} MODEL_IQ2000_DATA; + +/* Instruction argument buffer. */ + +union sem_fields { + struct { /* no operands */ + int empty; + } fmt_empty; + struct { /* */ + IADDR i_jmptarg; + } sfmt_j; + struct { /* */ + IADDR i_offset; + UINT f_rs; + UINT f_rt; + } sfmt_bbi; + struct { /* */ + UINT f_imm; + UINT f_rs; + UINT f_rt; + } sfmt_addi; + struct { /* */ + UINT f_mask; + UINT f_rd; + UINT f_rs; + UINT f_rt; + } sfmt_mrgb; + struct { /* */ + UINT f_maskl; + UINT f_rd; + UINT f_rs; + UINT f_rt; + UINT f_shamt; + } sfmt_ram; +#if WITH_SCACHE_PBB + /* Writeback handler. */ + struct { + /* Pointer to argbuf entry for insn whose results need writing back. */ + const struct argbuf *abuf; + } write; + /* x-before handler */ + struct { + /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/ + int first_p; + } before; + /* x-after handler */ + struct { + int empty; + } after; + /* This entry is used to terminate each pbb. */ + struct { + /* Number of insns in pbb. */ + int insn_count; + /* Next pbb to execute. */ + SCACHE *next; + SCACHE *branch_target; + } chain; +#endif +}; + +/* The ARGBUF struct. */ +struct argbuf { + /* These are the baseclass definitions. */ + IADDR addr; + const IDESC *idesc; + char trace_p; + char profile_p; + /* ??? Temporary hack for skip insns. */ + char skip_count; + char unused; + /* cpu specific data follows */ + union sem semantic; + int written; + union sem_fields fields; +}; + +/* A cached insn. + + ??? SCACHE used to contain more than just argbuf. We could delete the + type entirely and always just use ARGBUF, but for future concerns and as + a level of abstraction it is left in. */ + +struct scache { + struct argbuf argbuf; +}; + +/* Macros to simplify extraction, reading and semantic code. + These define and assign the local vars that contain the insn's fields. */ + +#define EXTRACT_IFMT_EMPTY_VARS \ + unsigned int length; +#define EXTRACT_IFMT_EMPTY_CODE \ + length = 0; \ + +#define EXTRACT_IFMT_ADD_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + UINT f_rd; \ + UINT f_shamt; \ + UINT f_func; \ + unsigned int length; +#define EXTRACT_IFMT_ADD_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ + f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ + f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_ADDI_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + UINT f_imm; \ + unsigned int length; +#define EXTRACT_IFMT_ADDI_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ + +#define EXTRACT_IFMT_RAM_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + UINT f_rd; \ + UINT f_shamt; \ + UINT f_5; \ + UINT f_maskl; \ + unsigned int length; +#define EXTRACT_IFMT_RAM_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ + f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ + f_5 = EXTRACT_LSB0_UINT (insn, 32, 5, 1); \ + f_maskl = EXTRACT_LSB0_UINT (insn, 32, 4, 5); \ + +#define EXTRACT_IFMT_SLL_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + UINT f_rd; \ + UINT f_shamt; \ + UINT f_func; \ + unsigned int length; +#define EXTRACT_IFMT_SLL_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ + f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ + f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_SLMV_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + UINT f_rd; \ + UINT f_shamt; \ + UINT f_func; \ + unsigned int length; +#define EXTRACT_IFMT_SLMV_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ + f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ + f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_SLTI_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + UINT f_imm; \ + unsigned int length; +#define EXTRACT_IFMT_SLTI_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ + +#define EXTRACT_IFMT_BBI_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + SI f_offset; \ + unsigned int length; +#define EXTRACT_IFMT_BBI_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \ + +#define EXTRACT_IFMT_BBV_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + SI f_offset; \ + unsigned int length; +#define EXTRACT_IFMT_BBV_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \ + +#define EXTRACT_IFMT_BGEZ_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + SI f_offset; \ + unsigned int length; +#define EXTRACT_IFMT_BGEZ_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \ + +#define EXTRACT_IFMT_JALR_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + UINT f_rd; \ + UINT f_shamt; \ + UINT f_func; \ + unsigned int length; +#define EXTRACT_IFMT_JALR_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ + f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ + f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_JR_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + UINT f_rd; \ + UINT f_shamt; \ + UINT f_func; \ + unsigned int length; +#define EXTRACT_IFMT_JR_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ + f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ + f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_LB_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + UINT f_imm; \ + unsigned int length; +#define EXTRACT_IFMT_LB_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ + +#define EXTRACT_IFMT_LUI_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + UINT f_imm; \ + unsigned int length; +#define EXTRACT_IFMT_LUI_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ + +#define EXTRACT_IFMT_BREAK_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + UINT f_rd; \ + UINT f_shamt; \ + UINT f_func; \ + unsigned int length; +#define EXTRACT_IFMT_BREAK_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ + f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ + f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_SYSCALL_VARS \ + UINT f_opcode; \ + UINT f_excode; \ + UINT f_func; \ + unsigned int length; +#define EXTRACT_IFMT_SYSCALL_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_excode = EXTRACT_LSB0_UINT (insn, 32, 25, 20); \ + f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_ANDOUI_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + UINT f_imm; \ + unsigned int length; +#define EXTRACT_IFMT_ANDOUI_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \ + +#define EXTRACT_IFMT_MRGB_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + UINT f_rd; \ + UINT f_10; \ + UINT f_mask; \ + UINT f_func; \ + unsigned int length; +#define EXTRACT_IFMT_MRGB_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ + f_10 = EXTRACT_LSB0_UINT (insn, 32, 10, 1); \ + f_mask = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \ + f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_BC0F_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + SI f_offset; \ + unsigned int length; +#define EXTRACT_IFMT_BC0F_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \ + +#define EXTRACT_IFMT_CFC0_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + UINT f_rd; \ + UINT f_10_11; \ + unsigned int length; +#define EXTRACT_IFMT_CFC0_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ + f_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \ + +#define EXTRACT_IFMT_CHKHDR_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + UINT f_rd; \ + UINT f_shamt; \ + UINT f_func; \ + unsigned int length; +#define EXTRACT_IFMT_CHKHDR_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ + f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ + f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_LULCK_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + UINT f_rd; \ + UINT f_shamt; \ + UINT f_func; \ + unsigned int length; +#define EXTRACT_IFMT_LULCK_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ + f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \ + f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_PKRLR1_VARS \ + UINT f_opcode; \ + UINT f_rs; \ + UINT f_rt; \ + UINT f_count; \ + UINT f_index; \ + unsigned int length; +#define EXTRACT_IFMT_PKRLR1_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_count = EXTRACT_LSB0_UINT (insn, 32, 15, 7); \ + f_index = EXTRACT_LSB0_UINT (insn, 32, 8, 9); \ + +#define EXTRACT_IFMT_RFE_VARS \ + UINT f_opcode; \ + UINT f_25; \ + UINT f_24_19; \ + UINT f_func; \ + unsigned int length; +#define EXTRACT_IFMT_RFE_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_25 = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \ + f_24_19 = EXTRACT_LSB0_UINT (insn, 32, 24, 19); \ + f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + +#define EXTRACT_IFMT_J_VARS \ + UINT f_opcode; \ + UINT f_rsrvd; \ + USI f_jtarg; \ + unsigned int length; +#define EXTRACT_IFMT_J_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_rsrvd = EXTRACT_LSB0_UINT (insn, 32, 25, 10); \ + f_jtarg = ((((pc) & (0xf0000000))) | (((EXTRACT_LSB0_UINT (insn, 32, 15, 16)) << (2)))); \ + +/* Collection of various things for the trace handler to use. */ + +typedef struct trace_record { + IADDR pc; + /* FIXME:wip */ +} TRACE_RECORD; + +#endif /* CPU_IQ2000BF_H */

cpu.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property

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