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    /openrisc/tags/gdb/gdb-6.8/gdb-6.8.openrisc-2.1/sim/mips
    from Rev 24 to Rev 33
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  •

Rev 24 → Rev 33

/mips3d.igen
0,0 → 1,176
// -*- C -*-
 
// Simulator definition for the MIPS MIPS-3D ASE.
// Copyright (C) 2002 Free Software Foundation, Inc.
// Contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom
// Corporation (SiByte).
//
// This file is part of GDB, the GNU debugger.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
 
// Reference: MIPS64 Architecture for Programmers Volume IV-c:
// The MIPS-3D Application-Specific Extension to the
// MIPS64 Architecture. (MIPS Document MD00099)
 
 
010001,10,110,5.FT,5.FS,5.FD,011000:COP1:64,f::ADDR.PS
"addr.ps f<FD>, f<FS>, f<FT>"
*mips3d:
{
/* fd.PL = ft.PU + ft.PL; fd.PU = fs.PU + fs.PL; */
check_fpu (SD_);
check_u64 (SD_, instruction_0);
StoreFPR (FD, fmt_ps, AddR (ValueFPR (FS, fmt_ps),
ValueFPR (FT, fmt_ps), fmt_ps));
}
 
 
010001,01001,3.CC,0,1.TF,16.OFFSET:COP1:64,f::BC1ANY2tf
"bc1any2%s<TF> <CC>, %#lx<OFFSET>"
*mips3d:
{
address_word offset;
int cc = CC;
check_fpu (SD_);
check_u64 (SD_, instruction_0);
if ((cc & 0x1) != 0)
Unpredictable ();
if ((GETFCC (cc) == TF) || (GETFCC (cc + 1) == TF))
{
offset = (EXTEND16 (OFFSET) << 2);
DELAY_SLOT (NIA + offset);
}
}
 
 
010001,01010,3.CC,0,1.TF,16.OFFSET:COP1:64,f::BC1ANY4tf
"bc1any4%s<TF> <CC>, %#lx<OFFSET>"
*mips3d:
{
address_word offset;
int cc = CC;
check_fpu (SD_);
check_u64 (SD_, instruction_0);
if ((cc & 0x3) != 0)
Unpredictable ();
if ((GETFCC (cc) == TF)
|| (GETFCC (cc + 1) == TF)
|| (GETFCC (cc + 2) == TF)
|| (GETFCC (cc + 3) == TF))
{
offset = (EXTEND16 (OFFSET) << 2);
DELAY_SLOT (NIA + offset);
}
}
 
 
010001,10,3.FMT,5.FT,5.FS,3.CC,01,11,4.COND:COP1:64,f::CABS.cond.fmt
"cabs.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
*mips3d:
{
int fmt = FMT;
check_fpu (SD_);
check_u64 (SD_, instruction_0);
check_fmt_p (SD_, fmt, instruction_0);
CompareAbs (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
TRACE_ALU_RESULT (ValueFCR (31));
}
 
 
010001,10,110,00000,5.FS,5.FD,100100:COP1:64,f::CVT.PW.PS
"cvt.pw.ps f<FD>, f<FS>"
*mips3d:
{
/* fd.pu = cvt_rnd (fs.pu); fd.pl = cvt_rnd (fs.pl); */
/* fmt_pw is fmt_long for 64 bit transfers, but cvt encoding is fmt_word. */
check_fpu (SD_);
check_u64 (SD_, instruction_0);
StoreFPR (FD, fmt_pw, ConvertPS (GETRM (), ValueFPR (FS, fmt_ps),
fmt_ps, fmt_word));
}
 
 
010001,10,100,00000,5.FS,5.FD,100110:COP1:64,f::CVT.PS.PW
"cvt.ps.pw f<FD>, f<FS>"
*mips3d:
{
/* fd.pl = cvt_rnd (fs.pl); fd.pu = cvt_rnd (fs.pu); */
/* fmt_pw is fmt_long for 64 bit transfers, but cvt encoding is fmt_word. */
check_fpu (SD_);
check_u64 (SD_, instruction_0);
StoreFPR (FD, fmt_ps, ConvertPS (GETRM (), ValueFPR (FS, fmt_pw),
fmt_word, fmt_ps));
}
 
 
010001,10,110,5.FT,5.FS,5.FD,011010:COP1:64,f::MULR.PS
"mulr.ps f<FD>, f<FS>, f<FT>"
*mips3d:
{
/* fd.PL = ft.PU * ft.PL; fd.PU = fs.PU * fs.PL; */
check_fpu (SD_);
check_u64 (SD_, instruction_0);
StoreFPR (FD, fmt_ps, MultiplyR (ValueFPR (FS, fmt_ps),
ValueFPR (FT, fmt_ps), fmt_ps));
}
 
 
010001,10,3.FMT,00000,5.FS,5.FD,011101:COP1:64,f::RECIP1.fmt
"recip1.%s<FMT> f<FD>, f<FS>"
*mips3d:
{
int fmt = FMT;
check_fpu (SD_);
check_u64 (SD_, instruction_0);
check_fmt_p (SD_, fmt, instruction_0);
StoreFPR (FD, fmt, Recip1 (ValueFPR (FS, fmt), fmt));
}
 
 
010001,10,3.FMT,5.FT,5.FS,5.FD,011100:COP1:64,f::RECIP2.fmt
"recip2.%s<FMT> f<FD>, f<FS>, f<FT>"
*mips3d:
{
int fmt = FMT;
check_fpu (SD_);
check_u64 (SD_, instruction_0);
check_fmt_p (SD_, fmt, instruction_0);
StoreFPR (FD, fmt, Recip2 (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
}
 
 
010001,10,3.FMT,00000,5.FS,5.FD,011110:COP1:64,f::RSQRT1.fmt
"rsqrt1.%s<FMT> f<FD>, f<FS>"
*mips3d:
{
int fmt = FMT;
check_fpu (SD_);
check_u64 (SD_, instruction_0);
check_fmt_p (SD_, fmt, instruction_0);
StoreFPR (FD, fmt, RSquareRoot1 (ValueFPR (FS, fmt), fmt));
}
 
 
010001,10,3.FMT,5.FT,5.FS,5.FD,011111:COP1:64,f::RSQRT2.fmt
"rsqrt2.%s<FMT> f<FD>, f<FS>, f<FT>"
*mips3d:
{
int fmt = FMT;
check_fpu (SD_);
check_u64 (SD_, instruction_0);
check_fmt_p (SD_, fmt, instruction_0);
StoreFPR (FD, fmt, RSquareRoot2 (ValueFPR (FS, fmt),
ValueFPR (FT, fmt), fmt));
}
/interp.c
0,0 → 1,2614
/*> interp.c <*/
/* Simulator for the MIPS architecture.
 
This file is part of the MIPS sim
 
THIS SOFTWARE IS NOT COPYRIGHTED
 
Cygnus offers the following for use in the public domain. Cygnus
makes no warranty with regard to the software or it's performance
and the user accepts the software "AS IS" with all faults.
 
CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
NOTEs:
 
The IDT monitor (found on the VR4300 board), seems to lie about
register contents. It seems to treat the registers as sign-extended
32-bit values. This cause *REAL* problems when single-stepping 64-bit
code on the hardware.
 
*/
 
/* The TRACE manifests enable the provision of extra features. If they
are not defined then a simpler (quicker) simulator is constructed
without the required run-time checks, etc. */
#if 1 /* 0 to allow user build selection, 1 to force inclusion */
#define TRACE (1)
#endif
 
#include "bfd.h"
#include "sim-main.h"
#include "sim-utils.h"
#include "sim-options.h"
#include "sim-assert.h"
#include "sim-hw.h"
 
#include "itable.h"
 
 
#include "config.h"
 
#include <stdio.h>
#include <stdarg.h>
#include <ansidecl.h>
#include <ctype.h>
#include <limits.h>
#include <math.h>
#ifdef HAVE_STDLIB_H
#include <stdlib.h>
#endif
#ifdef HAVE_STRING_H
#include <string.h>
#else
#ifdef HAVE_STRINGS_H
#include <strings.h>
#endif
#endif
 
#include "getopt.h"
#include "libiberty.h"
#include "bfd.h"
#include "gdb/callback.h" /* GDB simulator callback interface */
#include "gdb/remote-sim.h" /* GDB simulator interface */
 
#include "sysdep.h"
 
#ifndef PARAMS
#define PARAMS(x)
#endif
 
char* pr_addr PARAMS ((SIM_ADDR addr));
char* pr_uword64 PARAMS ((uword64 addr));
 
 
/* Within interp.c we refer to the sim_state and sim_cpu directly. */
#define CPU cpu
#define SD sd
 
 
/* The following reserved instruction value is used when a simulator
trap is required. NOTE: Care must be taken, since this value may be
used in later revisions of the MIPS ISA. */
 
#define RSVD_INSTRUCTION (0x00000005)
#define RSVD_INSTRUCTION_MASK (0xFC00003F)
 
#define RSVD_INSTRUCTION_ARG_SHIFT 6
#define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
 
 
/* Bits in the Debug register */
#define Debug_DBD 0x80000000 /* Debug Branch Delay */
#define Debug_DM 0x40000000 /* Debug Mode */
#define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
 
/*---------------------------------------------------------------------------*/
/*-- GDB simulator interface ------------------------------------------------*/
/*---------------------------------------------------------------------------*/
 
static void ColdReset PARAMS((SIM_DESC sd));
 
/*---------------------------------------------------------------------------*/
 
 
 
#define DELAYSLOT() {\
if (STATE & simDELAYSLOT)\
sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
STATE |= simDELAYSLOT;\
}
 
#define JALDELAYSLOT() {\
DELAYSLOT ();\
STATE |= simJALDELAYSLOT;\
}
 
#define NULLIFY() {\
STATE &= ~simDELAYSLOT;\
STATE |= simSKIPNEXT;\
}
 
#define CANCELDELAYSLOT() {\
DSSTATE = 0;\
STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
}
 
#define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
#define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
 
/* Note that the monitor code essentially assumes this layout of memory.
If you change these, change the monitor code, too. */
/* FIXME Currently addresses are truncated to 32-bits, see
mips/sim-main.c:address_translation(). If that changes, then these
values will need to be extended, and tested for more carefully. */
#define K0BASE (0x80000000)
#define K0SIZE (0x20000000)
#define K1BASE (0xA0000000)
#define K1SIZE (0x20000000)
 
/* Simple run-time monitor support.
We emulate the monitor by placing magic reserved instructions at
the monitor's entry points; when we hit these instructions, instead
of raising an exception (as we would normally), we look at the
instruction and perform the appropriate monitory operation.
`*_monitor_base' are the physical addresses at which the corresponding
monitor vectors are located. `0' means none. By default,
install all three.
The RSVD_INSTRUCTION... macros specify the magic instructions we
use at the monitor entry points. */
static int firmware_option_p = 0;
static SIM_ADDR idt_monitor_base = 0xBFC00000;
static SIM_ADDR pmon_monitor_base = 0xBFC00500;
static SIM_ADDR lsipmon_monitor_base = 0xBFC00200;
 
static SIM_RC sim_firmware_command (SIM_DESC sd, char* arg);
 
 
#define MEM_SIZE (8 << 20) /* 8 MBytes */
 
 
#if defined(TRACE)
static char *tracefile = "trace.din"; /* default filename for trace log */
FILE *tracefh = NULL;
static void open_trace PARAMS((SIM_DESC sd));
#endif /* TRACE */
 
static const char * get_insn_name (sim_cpu *, int);
 
/* simulation target board. NULL=canonical */
static char* board = NULL;
 
 
static DECLARE_OPTION_HANDLER (mips_option_handler);
 
enum {
OPTION_DINERO_TRACE = OPTION_START,
OPTION_DINERO_FILE,
OPTION_FIRMWARE,
OPTION_INFO_MEMORY,
OPTION_BOARD
};
 
static int display_mem_info = 0;
 
static SIM_RC
mips_option_handler (sd, cpu, opt, arg, is_command)
SIM_DESC sd;
sim_cpu *cpu;
int opt;
char *arg;
int is_command;
{
int cpu_nr;
switch (opt)
{
case OPTION_DINERO_TRACE: /* ??? */
#if defined(TRACE)
/* Eventually the simTRACE flag could be treated as a toggle, to
allow external control of the program points being traced
(i.e. only from main onwards, excluding the run-time setup,
etc.). */
for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
{
sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
if (arg == NULL)
STATE |= simTRACE;
else if (strcmp (arg, "yes") == 0)
STATE |= simTRACE;
else if (strcmp (arg, "no") == 0)
STATE &= ~simTRACE;
else if (strcmp (arg, "on") == 0)
STATE |= simTRACE;
else if (strcmp (arg, "off") == 0)
STATE &= ~simTRACE;
else
{
fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg);
return SIM_RC_FAIL;
}
}
return SIM_RC_OK;
#else /* !TRACE */
fprintf(stderr,"\
Simulator constructed without dinero tracing support (for performance).\n\
Re-compile simulator with \"-DTRACE\" to enable this option.\n");
return SIM_RC_FAIL;
#endif /* !TRACE */
 
case OPTION_DINERO_FILE:
#if defined(TRACE)
if (optarg != NULL) {
char *tmp;
tmp = (char *)malloc(strlen(optarg) + 1);
if (tmp == NULL)
{
sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
return SIM_RC_FAIL;
}
else {
strcpy(tmp,optarg);
tracefile = tmp;
sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
}
}
#endif /* TRACE */
return SIM_RC_OK;
 
case OPTION_FIRMWARE:
return sim_firmware_command (sd, arg);
 
case OPTION_BOARD:
{
if (arg)
{
board = zalloc(strlen(arg) + 1);
strcpy(board, arg);
}
return SIM_RC_OK;
}
 
case OPTION_INFO_MEMORY:
display_mem_info = 1;
break;
}
return SIM_RC_OK;
}
 
 
static const OPTION mips_options[] =
{
{ {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
'\0', "on|off", "Enable dinero tracing",
mips_option_handler },
{ {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
'\0', "FILE", "Write dinero trace to FILE",
mips_option_handler },
{ {"firmware", required_argument, NULL, OPTION_FIRMWARE},
'\0', "[idt|pmon|lsipmon|none][@ADDRESS]", "Emulate ROM monitor",
mips_option_handler },
{ {"board", required_argument, NULL, OPTION_BOARD},
'\0', "none" /* rely on compile-time string concatenation for other options */
 
#define BOARD_JMR3904 "jmr3904"
"|" BOARD_JMR3904
#define BOARD_JMR3904_PAL "jmr3904pal"
"|" BOARD_JMR3904_PAL
#define BOARD_JMR3904_DEBUG "jmr3904debug"
"|" BOARD_JMR3904_DEBUG
#define BOARD_BSP "bsp"
"|" BOARD_BSP
 
, "Customize simulation for a particular board.", mips_option_handler },
 
/* These next two options have the same names as ones found in the
memory_options[] array in common/sim-memopt.c. This is because
the intention is to provide an alternative handler for those two
options. We need an alternative handler because the memory
regions are not set up until after the command line arguments
have been parsed, and so we cannot display the memory info whilst
processing the command line. There is a hack in sim_open to
remove these handlers when we want the real --memory-info option
to work. */
{ { "info-memory", no_argument, NULL, OPTION_INFO_MEMORY },
'\0', NULL, "List configured memory regions", mips_option_handler },
{ { "memory-info", no_argument, NULL, OPTION_INFO_MEMORY },
'\0', NULL, NULL, mips_option_handler },
{ {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
};
 
 
int interrupt_pending;
 
void
interrupt_event (SIM_DESC sd, void *data)
{
sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
address_word cia = CIA_GET (cpu);
if (SR & status_IE)
{
interrupt_pending = 0;
SignalExceptionInterrupt (1); /* interrupt "1" */
}
else if (!interrupt_pending)
sim_events_schedule (sd, 1, interrupt_event, data);
}
 
 
/*---------------------------------------------------------------------------*/
/*-- Device registration hook -----------------------------------------------*/
/*---------------------------------------------------------------------------*/
static void device_init(SIM_DESC sd) {
#ifdef DEVICE_INIT
extern void register_devices(SIM_DESC);
register_devices(sd);
#endif
}
 
/*---------------------------------------------------------------------------*/
/*-- GDB simulator interface ------------------------------------------------*/
/*---------------------------------------------------------------------------*/
 
SIM_DESC
sim_open (kind, cb, abfd, argv)
SIM_OPEN_KIND kind;
host_callback *cb;
struct bfd *abfd;
char **argv;
{
SIM_DESC sd = sim_state_alloc (kind, cb);
sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
 
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
 
/* FIXME: watchpoints code shouldn't need this */
STATE_WATCHPOINTS (sd)->pc = &(PC);
STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
 
/* Initialize the mechanism for doing insn profiling. */
CPU_INSN_NAME (cpu) = get_insn_name;
CPU_MAX_INSNS (cpu) = nr_itable_entries;
 
STATE = 0;
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
return 0;
sim_add_option_table (sd, NULL, mips_options);
 
 
/* getopt will print the error message so we just have to exit if this fails.
FIXME: Hmmm... in the case of gdb we need getopt to call
print_filtered. */
if (sim_parse_args (sd, argv) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
sim_module_uninstall (sd);
return 0;
}
 
/* handle board-specific memory maps */
if (board == NULL)
{
/* Allocate core managed memory */
sim_memopt *entry, *match = NULL;
address_word mem_size = 0;
int mapped = 0;
 
/* For compatibility with the old code - under this (at level one)
are the kernel spaces K0 & K1. Both of these map to a single
smaller sub region */
sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
 
/* Look for largest memory region defined on command-line at
phys address 0. */
#ifdef SIM_HAVE_FLATMEM
mem_size = STATE_MEM_SIZE (sd);
#endif
for (entry = STATE_MEMOPT (sd); entry != NULL; entry = entry->next)
{
/* If we find an entry at address 0, then we will end up
allocating a new buffer in the "memory alias" command
below. The region at address 0 will be deleted. */
address_word size = (entry->modulo != 0
? entry->modulo : entry->nr_bytes);
if (entry->addr == 0
&& (!match || entry->level < match->level))
match = entry;
else if (entry->addr == K0BASE || entry->addr == K1BASE)
mapped = 1;
else
{
sim_memopt *alias;
for (alias = entry->alias; alias != NULL; alias = alias->next)
{
if (alias->addr == 0
&& (!match || entry->level < match->level))
match = entry;
else if (alias->addr == K0BASE || alias->addr == K1BASE)
mapped = 1;
}
}
}
 
if (!mapped)
{
if (match)
{
/* Get existing memory region size. */
mem_size = (match->modulo != 0
? match->modulo : match->nr_bytes);
/* Delete old region. */
sim_do_commandf (sd, "memory delete %d:0x%lx@%d",
match->space, match->addr, match->level);
}
else if (mem_size == 0)
mem_size = MEM_SIZE;
/* Limit to KSEG1 size (512MB) */
if (mem_size > K1SIZE)
mem_size = K1SIZE;
/* memory alias K1BASE@1,K1SIZE%MEMSIZE,K0BASE */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
K1BASE, K1SIZE, (long)mem_size, K0BASE);
}
 
device_init(sd);
}
else if (board != NULL
&& (strcmp(board, BOARD_BSP) == 0))
{
int i;
 
STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
 
/* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
0x9FC00000,
4 * 1024 * 1024, /* 4 MB */
0xBFC00000);
 
/* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
0x80000000,
4 * 1024 * 1024, /* 4 MB */
0xA0000000);
 
/* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
for (i=0; i<8; i++) /* 32 MB total */
{
unsigned size = 4 * 1024 * 1024; /* 4 MB */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
0x88000000 + (i * size),
size,
0xA8000000 + (i * size));
}
}
#if (WITH_HW)
else if (board != NULL
&& (strcmp(board, BOARD_JMR3904) == 0 ||
strcmp(board, BOARD_JMR3904_PAL) == 0 ||
strcmp(board, BOARD_JMR3904_DEBUG) == 0))
{
/* match VIRTUAL memory layout of JMR-TX3904 board */
int i;
 
/* --- disable monitor unless forced on by user --- */
 
if (! firmware_option_p)
{
idt_monitor_base = 0;
pmon_monitor_base = 0;
lsipmon_monitor_base = 0;
}
 
/* --- environment --- */
 
STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
 
/* --- memory --- */
 
/* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
0x9FC00000,
4 * 1024 * 1024, /* 4 MB */
0xBFC00000);
 
/* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
0x80000000,
4 * 1024 * 1024, /* 4 MB */
0xA0000000);
 
/* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
for (i=0; i<8; i++) /* 32 MB total */
{
unsigned size = 4 * 1024 * 1024; /* 4 MB */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
0x88000000 + (i * size),
size,
0xA8000000 + (i * size));
}
 
/* Dummy memory regions for unsimulated devices - sorted by address */
 
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB1000000, 0x400); /* ISA I/O */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2500000, 0x004); /* LED/switch */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2700000, 0x004); /* RTC */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB3C00000, 0x004); /* RTC */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF8000, 0x900); /* DRAMC */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFE000, 0x01c); /* EBIF */
sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
 
 
/* --- simulated devices --- */
sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
sim_hw_parse (sd, "/tx3904cpu");
sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
sim_hw_parse (sd, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
{
/* FIXME: poking at dv-sockser internals, use tcp backend if
--sockser_addr option was given.*/
extern char* sockser_addr;
if(sockser_addr == NULL)
sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend stdio");
else
sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend tcp");
}
sim_hw_parse (sd, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
sim_hw_parse (sd, "/tx3904sio@0xfffff400/backend stdio");
 
/* -- device connections --- */
sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu");
sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
sim_hw_parse (sd, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
sim_hw_parse (sd, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
 
/* add PAL timer & I/O module */
if(! strcmp(board, BOARD_JMR3904_PAL))
{
/* the device */
sim_hw_parse (sd, "/pal@0xffff0000");
sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64");
 
/* wire up interrupt ports to irc */
sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc");
sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
}
 
if(! strcmp(board, BOARD_JMR3904_DEBUG))
{
/* -- DEBUG: glue interrupt generators --- */
sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
}
 
device_init(sd);
}
#endif
 
if (display_mem_info)
{
struct option_list * ol;
struct option_list * prev;
 
/* This is a hack. We want to execute the real --memory-info command
line switch which is handled in common/sim-memopts.c, not the
override we have defined in this file. So we remove the
mips_options array from the state options list. This is safe
because we have now processed all of the command line. */
for (ol = STATE_OPTIONS (sd), prev = NULL;
ol != NULL;
prev = ol, ol = ol->next)
if (ol->options == mips_options)
break;
 
SIM_ASSERT (ol != NULL);
 
if (prev == NULL)
STATE_OPTIONS (sd) = ol->next;
else
prev->next = ol->next;
 
sim_do_commandf (sd, "memory-info");
}
 
/* check for/establish the a reference program image */
if (sim_analyze_program (sd,
(STATE_PROG_ARGV (sd) != NULL
? *STATE_PROG_ARGV (sd)
: NULL),
abfd) != SIM_RC_OK)
{
sim_module_uninstall (sd);
return 0;
}
 
/* Configure/verify the target byte order and other runtime
configuration options */
if (sim_config (sd) != SIM_RC_OK)
{
sim_module_uninstall (sd);
return 0;
}
 
if (sim_post_argv_init (sd) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
sim_module_uninstall (sd);
return 0;
}
 
/* verify assumptions the simulator made about the host type system.
This macro does not return if there is a problem */
SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
 
/* This is NASTY, in that we are assuming the size of specific
registers: */
{
int rn;
for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
{
if (rn < 32)
cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
else if ((rn >= FGR_BASE) && (rn < (FGR_BASE + NR_FGR)))
cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
else if ((rn >= 33) && (rn <= 37))
cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
else if ((rn == SRIDX)
|| (rn == FCR0IDX)
|| (rn == FCR31IDX)
|| ((rn >= 72) && (rn <= 89)))
cpu->register_widths[rn] = 32;
else
cpu->register_widths[rn] = 0;
}
 
 
}
 
#if defined(TRACE)
if (STATE & simTRACE)
open_trace(sd);
#endif /* TRACE */
 
/*
sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n",
idt_monitor_base,
pmon_monitor_base,
lsipmon_monitor_base);
*/
 
/* Write the monitor trap address handlers into the monitor (eeprom)
address space. This can only be done once the target endianness
has been determined. */
if (idt_monitor_base != 0)
{
unsigned loop;
unsigned idt_monitor_size = 1 << 11;
 
/* the default monitor region */
sim_do_commandf (sd, "memory region 0x%x,0x%x",
idt_monitor_base, idt_monitor_size);
 
/* Entry into the IDT monitor is via fixed address vectors, and
not using machine instructions. To avoid clashing with use of
the MIPS TRAP system, we place our own (simulator specific)
"undefined" instructions into the relevant vector slots. */
for (loop = 0; (loop < idt_monitor_size); loop += 4)
{
address_word vaddr = (idt_monitor_base + loop);
unsigned32 insn = (RSVD_INSTRUCTION |
(((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK)
<< RSVD_INSTRUCTION_ARG_SHIFT));
H2T (insn);
sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
}
}
 
if ((pmon_monitor_base != 0) || (lsipmon_monitor_base != 0))
{
/* The PMON monitor uses the same address space, but rather than
branching into it the address of a routine is loaded. We can
cheat for the moment, and direct the PMON routine to IDT style
instructions within the monitor space. This relies on the IDT
monitor not using the locations from 0xBFC00500 onwards as its
entry points.*/
unsigned loop;
for (loop = 0; (loop < 24); loop++)
{
unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
switch (loop)
{
case 0: /* read */
value = 7;
break;
case 1: /* write */
value = 8;
break;
case 2: /* open */
value = 6;
break;
case 3: /* close */
value = 10;
break;
case 5: /* printf */
value = ((0x500 - 16) / 8); /* not an IDT reason code */
break;
case 8: /* cliexit */
value = 17;
break;
case 11: /* flush_cache */
value = 28;
break;
}
 
SIM_ASSERT (idt_monitor_base != 0);
value = ((unsigned int) idt_monitor_base + (value * 8));
H2T (value);
 
if (pmon_monitor_base != 0)
{
address_word vaddr = (pmon_monitor_base + (loop * 4));
sim_write (sd, vaddr, (char *)&value, sizeof (value));
}
 
if (lsipmon_monitor_base != 0)
{
address_word vaddr = (lsipmon_monitor_base + (loop * 4));
sim_write (sd, vaddr, (char *)&value, sizeof (value));
}
}
 
/* Write an abort sequence into the TRAP (common) exception vector
addresses. This is to catch code executing a TRAP (et.al.)
instruction without installing a trap handler. */
if ((idt_monitor_base != 0) ||
(pmon_monitor_base != 0) ||
(lsipmon_monitor_base != 0))
{
unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
HALT_INSTRUCTION /* BREAK */ };
H2T (halt[0]);
H2T (halt[1]);
sim_write (sd, 0x80000000, (char *) halt, sizeof (halt));
sim_write (sd, 0x80000180, (char *) halt, sizeof (halt));
sim_write (sd, 0x80000200, (char *) halt, sizeof (halt));
/* XXX: Write here unconditionally? */
sim_write (sd, 0xBFC00200, (char *) halt, sizeof (halt));
sim_write (sd, 0xBFC00380, (char *) halt, sizeof (halt));
sim_write (sd, 0xBFC00400, (char *) halt, sizeof (halt));
}
}
 
 
 
return sd;
}
 
#if defined(TRACE)
static void
open_trace(sd)
SIM_DESC sd;
{
tracefh = fopen(tracefile,"wb+");
if (tracefh == NULL)
{
sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
tracefh = stderr;
}
}
#endif /* TRACE */
 
/* Return name of an insn, used by insn profiling. */
static const char *
get_insn_name (sim_cpu *cpu, int i)
{
return itable[i].name;
}
 
void
sim_close (sd, quitting)
SIM_DESC sd;
int quitting;
{
#ifdef DEBUG
printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
#endif
 
 
/* "quitting" is non-zero if we cannot hang on errors */
 
/* shut down modules */
sim_module_uninstall (sd);
 
/* Ensure that any resources allocated through the callback
mechanism are released: */
sim_io_shutdown (sd);
 
#if defined(TRACE)
if (tracefh != NULL && tracefh != stderr)
fclose(tracefh);
tracefh = NULL;
#endif /* TRACE */
 
/* FIXME - free SD */
 
return;
}
 
 
int
sim_write (sd,addr,buffer,size)
SIM_DESC sd;
SIM_ADDR addr;
unsigned char *buffer;
int size;
{
int index;
sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
 
/* Return the number of bytes written, or zero if error. */
#ifdef DEBUG
sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
#endif
 
/* We use raw read and write routines, since we do not want to count
the GDB memory accesses in our statistics gathering. */
 
for (index = 0; index < size; index++)
{
address_word vaddr = (address_word)addr + index;
address_word paddr;
int cca;
if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
break;
if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
break;
}
 
return(index);
}
 
int
sim_read (sd,addr,buffer,size)
SIM_DESC sd;
SIM_ADDR addr;
unsigned char *buffer;
int size;
{
int index;
sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
 
/* Return the number of bytes read, or zero if error. */
#ifdef DEBUG
sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
#endif /* DEBUG */
 
for (index = 0; (index < size); index++)
{
address_word vaddr = (address_word)addr + index;
address_word paddr;
int cca;
if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
break;
if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
break;
}
 
return(index);
}
 
int
sim_store_register (sd,rn,memory,length)
SIM_DESC sd;
int rn;
unsigned char *memory;
int length;
{
sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
/* NOTE: gdb (the client) stores registers in target byte order
while the simulator uses host byte order */
#ifdef DEBUG
sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
#endif /* DEBUG */
 
/* Unfortunately this suffers from the same problem as the register
numbering one. We need to know what the width of each logical
register number is for the architecture being simulated. */
 
if (cpu->register_widths[rn] == 0)
{
sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
return 0;
}
 
 
 
if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
{
cpu->fpr_state[rn - FGR_BASE] = fmt_uninterpreted;
if (cpu->register_widths[rn] == 32)
{
if (length == 8)
{
cpu->fgr[rn - FGR_BASE] =
(unsigned32) T2H_8 (*(unsigned64*)memory);
return 8;
}
else
{
cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
return 4;
}
}
else
{
if (length == 8)
{
cpu->fgr[rn - FGR_BASE] = T2H_8 (*(unsigned64*)memory);
return 8;
}
else
{
cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
return 4;
}
}
}
 
if (cpu->register_widths[rn] == 32)
{
if (length == 8)
{
cpu->registers[rn] =
(unsigned32) T2H_8 (*(unsigned64*)memory);
return 8;
}
else
{
cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
return 4;
}
}
else
{
if (length == 8)
{
cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
return 8;
}
else
{
cpu->registers[rn] = (signed32) T2H_4(*(unsigned32*)memory);
return 4;
}
}
 
return 0;
}
 
int
sim_fetch_register (sd,rn,memory,length)
SIM_DESC sd;
int rn;
unsigned char *memory;
int length;
{
sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
/* NOTE: gdb (the client) stores registers in target byte order
while the simulator uses host byte order */
#ifdef DEBUG
#if 0 /* FIXME: doesn't compile */
sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
#endif
#endif /* DEBUG */
 
if (cpu->register_widths[rn] == 0)
{
sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn);
return 0;
}
 
 
 
/* Any floating point register */
if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
{
if (cpu->register_widths[rn] == 32)
{
if (length == 8)
{
*(unsigned64*)memory =
H2T_8 ((unsigned32) (cpu->fgr[rn - FGR_BASE]));
return 8;
}
else
{
*(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]);
return 4;
}
}
else
{
if (length == 8)
{
*(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]);
return 8;
}
else
{
*(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->fgr[rn - FGR_BASE]));
return 4;
}
}
}
 
if (cpu->register_widths[rn] == 32)
{
if (length == 8)
{
*(unsigned64*)memory =
H2T_8 ((unsigned32) (cpu->registers[rn]));
return 8;
}
else
{
*(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
return 4;
}
}
else
{
if (length == 8)
{
*(unsigned64*)memory =
H2T_8 ((unsigned64) (cpu->registers[rn]));
return 8;
}
else
{
*(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
return 4;
}
}
 
return 0;
}
 
 
SIM_RC
sim_create_inferior (sd, abfd, argv,env)
SIM_DESC sd;
struct bfd *abfd;
char **argv;
char **env;
{
 
#ifdef DEBUG
#if 0 /* FIXME: doesn't compile */
printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
pr_addr(PC));
#endif
#endif /* DEBUG */
 
ColdReset(sd);
 
if (abfd != NULL)
{
/* override PC value set by ColdReset () */
int cpu_nr;
for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
{
sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
}
}
 
#if 0 /* def DEBUG */
if (argv || env)
{
/* We should really place the argv slot values into the argument
registers, and onto the stack as required. However, this
assumes that we have a stack defined, which is not
necessarily true at the moment. */
char **cptr;
sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
for (cptr = argv; (cptr && *cptr); cptr++)
printf("DBG: arg \"%s\"\n",*cptr);
}
#endif /* DEBUG */
 
return SIM_RC_OK;
}
 
void
sim_do_command (sd,cmd)
SIM_DESC sd;
char *cmd;
{
if (sim_args_command (sd, cmd) != SIM_RC_OK)
sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
cmd);
}
 
/*---------------------------------------------------------------------------*/
/*-- Private simulator support interface ------------------------------------*/
/*---------------------------------------------------------------------------*/
 
/* Read a null terminated string from memory, return in a buffer */
static char *
fetch_str (SIM_DESC sd,
address_word addr)
{
char *buf;
int nr = 0;
char null;
while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
nr++;
buf = NZALLOC (char, nr + 1);
sim_read (sd, addr, buf, nr);
return buf;
}
 
 
/* Implements the "sim firmware" command:
sim firmware NAME[@ADDRESS] --- emulate ROM monitor named NAME.
NAME can be idt, pmon, or lsipmon. If omitted, ADDRESS
defaults to the normal address for that monitor.
sim firmware none --- don't emulate any ROM monitor. Useful
if you need a clean address space. */
static SIM_RC
sim_firmware_command (SIM_DESC sd, char *arg)
{
int address_present = 0;
SIM_ADDR address;
 
/* Signal occurrence of this option. */
firmware_option_p = 1;
 
/* Parse out the address, if present. */
{
char *p = strchr (arg, '@');
if (p)
{
char *q;
address_present = 1;
p ++; /* skip over @ */
 
address = strtoul (p, &q, 0);
if (*q != '\0')
{
sim_io_printf (sd, "Invalid address given to the"
"`sim firmware NAME@ADDRESS' command: %s\n",
p);
return SIM_RC_FAIL;
}
}
else
{
address_present = 0;
address = -1; /* Dummy value. */
}
}
 
if (! strncmp (arg, "idt", 3))
{
idt_monitor_base = address_present ? address : 0xBFC00000;
pmon_monitor_base = 0;
lsipmon_monitor_base = 0;
}
else if (! strncmp (arg, "pmon", 4))
{
/* pmon uses indirect calls. Hook into implied idt. */
pmon_monitor_base = address_present ? address : 0xBFC00500;
idt_monitor_base = pmon_monitor_base - 0x500;
lsipmon_monitor_base = 0;
}
else if (! strncmp (arg, "lsipmon", 7))
{
/* lsipmon uses indirect calls. Hook into implied idt. */
pmon_monitor_base = 0;
lsipmon_monitor_base = address_present ? address : 0xBFC00200;
idt_monitor_base = lsipmon_monitor_base - 0x200;
}
else if (! strncmp (arg, "none", 4))
{
if (address_present)
{
sim_io_printf (sd,
"The `sim firmware none' command does "
"not take an `ADDRESS' argument.\n");
return SIM_RC_FAIL;
}
idt_monitor_base = 0;
pmon_monitor_base = 0;
lsipmon_monitor_base = 0;
}
else
{
sim_io_printf (sd, "\
Unrecognized name given to the `sim firmware NAME' command: %s\n\
Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.\n",
arg);
return SIM_RC_FAIL;
}
return SIM_RC_OK;
}
 
 
 
/* Simple monitor interface (currently setup for the IDT and PMON monitors) */
int
sim_monitor (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
unsigned int reason)
{
#ifdef DEBUG
printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
#endif /* DEBUG */
 
/* The IDT monitor actually allows two instructions per vector
slot. However, the simulator currently causes a trap on each
individual instruction. We cheat, and lose the bottom bit. */
reason >>= 1;
 
/* The following callback functions are available, however the
monitor we are simulating does not make use of them: get_errno,
isatty, lseek, rename, system, time and unlink */
switch (reason)
{
 
case 6: /* int open(char *path,int flags) */
{
char *path = fetch_str (sd, A0);
V0 = sim_io_open (sd, path, (int)A1);
zfree (path);
break;
}
 
case 7: /* int read(int file,char *ptr,int len) */
{
int fd = A0;
int nr = A2;
char *buf = zalloc (nr);
V0 = sim_io_read (sd, fd, buf, nr);
sim_write (sd, A1, buf, nr);
zfree (buf);
}
break;
 
case 8: /* int write(int file,char *ptr,int len) */
{
int fd = A0;
int nr = A2;
char *buf = zalloc (nr);
sim_read (sd, A1, buf, nr);
V0 = sim_io_write (sd, fd, buf, nr);
if (fd == 1)
sim_io_flush_stdout (sd);
else if (fd == 2)
sim_io_flush_stderr (sd);
zfree (buf);
break;
}
 
case 10: /* int close(int file) */
{
V0 = sim_io_close (sd, (int)A0);
break;
}
 
case 2: /* Densan monitor: char inbyte(int waitflag) */
{
if (A0 == 0) /* waitflag == NOWAIT */
V0 = (unsigned_word)-1;
}
/* Drop through to case 11 */
 
case 11: /* char inbyte(void) */
{
char tmp;
/* ensure that all output has gone... */
sim_io_flush_stdout (sd);
if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
{
sim_io_error(sd,"Invalid return from character read");
V0 = (unsigned_word)-1;
}
else
V0 = (unsigned_word)tmp;
break;
}
 
case 3: /* Densan monitor: void co(char chr) */
case 12: /* void outbyte(char chr) : write a byte to "stdout" */
{
char tmp = (char)(A0 & 0xFF);
sim_io_write_stdout (sd, &tmp, sizeof(char));
break;
}
 
case 17: /* void _exit() */
{
sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
(unsigned int)(A0 & 0xFFFFFFFF));
break;
}
 
case 28: /* PMON flush_cache */
break;
 
case 55: /* void get_mem_info(unsigned int *ptr) */
/* in: A0 = pointer to three word memory location */
/* out: [A0 + 0] = size */
/* [A0 + 4] = instruction cache size */
/* [A0 + 8] = data cache size */
{
unsigned_4 value;
unsigned_4 zero = 0;
address_word mem_size;
sim_memopt *entry, *match = NULL;
 
/* Search for memory region mapped to KSEG0 or KSEG1. */
for (entry = STATE_MEMOPT (sd);
entry != NULL;
entry = entry->next)
{
if ((entry->addr == K0BASE || entry->addr == K1BASE)
&& (!match || entry->level < match->level))
match = entry;
else
{
sim_memopt *alias;
for (alias = entry->alias;
alias != NULL;
alias = alias->next)
if ((alias->addr == K0BASE || alias->addr == K1BASE)
&& (!match || entry->level < match->level))
match = entry;
}
}
 
/* Get region size, limit to KSEG1 size (512MB). */
SIM_ASSERT (match != NULL);
mem_size = (match->modulo != 0
? match->modulo : match->nr_bytes);
if (mem_size > K1SIZE)
mem_size = K1SIZE;
 
value = mem_size;
H2T (value);
sim_write (sd, A0 + 0, (char *)&value, 4);
sim_write (sd, A0 + 4, (char *)&zero, 4);
sim_write (sd, A0 + 8, (char *)&zero, 4);
/* sim_io_eprintf (sd, "sim: get_mem_info() deprecated\n"); */
break;
}
case 158: /* PMON printf */
/* in: A0 = pointer to format string */
/* A1 = optional argument 1 */
/* A2 = optional argument 2 */
/* A3 = optional argument 3 */
/* out: void */
/* The following is based on the PMON printf source */
{
address_word s = A0;
char c;
signed_word *ap = &A1; /* 1st argument */
/* This isn't the quickest way, since we call the host print
routine for every character almost. But it does avoid
having to allocate and manage a temporary string buffer. */
/* TODO: Include check that we only use three arguments (A1,
A2 and A3) */
while (sim_read (sd, s++, &c, 1) && c != '\0')
{
if (c == '%')
{
char tmp[40];
enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
int width = 0, trunc = 0, haddot = 0, longlong = 0;
while (sim_read (sd, s++, &c, 1) && c != '\0')
{
if (strchr ("dobxXulscefg%", c))
break;
else if (c == '-')
fmt = FMT_LJUST;
else if (c == '0')
fmt = FMT_RJUST0;
else if (c == '~')
fmt = FMT_CENTER;
else if (c == '*')
{
if (haddot)
trunc = (int)*ap++;
else
width = (int)*ap++;
}
else if (c >= '1' && c <= '9')
{
address_word t = s;
unsigned int n;
while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
tmp[s - t] = c;
tmp[s - t] = '\0';
n = (unsigned int)strtol(tmp,NULL,10);
if (haddot)
trunc = n;
else
width = n;
s--;
}
else if (c == '.')
haddot = 1;
}
switch (c)
{
case '%':
sim_io_printf (sd, "%%");
break;
case 's':
if ((int)*ap != 0)
{
address_word p = *ap++;
char ch;
while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
sim_io_printf(sd, "%c", ch);
}
else
sim_io_printf(sd,"(null)");
break;
case 'c':
sim_io_printf (sd, "%c", (int)*ap++);
break;
default:
if (c == 'l')
{
sim_read (sd, s++, &c, 1);
if (c == 'l')
{
longlong = 1;
sim_read (sd, s++, &c, 1);
}
}
if (strchr ("dobxXu", c))
{
word64 lv = (word64) *ap++;
if (c == 'b')
sim_io_printf(sd,"<binary not supported>");
else
{
sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
if (longlong)
sim_io_printf(sd, tmp, lv);
else
sim_io_printf(sd, tmp, (int)lv);
}
}
else if (strchr ("eEfgG", c))
{
double dbl = *(double*)(ap++);
sprintf (tmp, "%%%d.%d%c", width, trunc, c);
sim_io_printf (sd, tmp, dbl);
trunc = 0;
}
}
}
else
sim_io_printf(sd, "%c", c);
}
break;
}
 
default:
/* Unknown reason. */
return 0;
}
return 1;
}
 
/* Store a word into memory. */
 
static void
store_word (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
uword64 vaddr,
signed_word val)
{
address_word paddr;
int uncached;
 
if ((vaddr & 3) != 0)
SignalExceptionAddressStore ();
else
{
if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
isTARGET, isREAL))
{
const uword64 mask = 7;
uword64 memval;
unsigned int byte;
 
paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
byte = (vaddr & mask) ^ (BigEndianCPU << 2);
memval = ((uword64) val) << (8 * byte);
StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
isREAL);
}
}
}
 
/* Load a word from memory. */
 
static signed_word
load_word (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
uword64 vaddr)
{
if ((vaddr & 3) != 0)
{
SIM_CORE_SIGNAL (SD, cpu, cia, read_map, AccessLength_WORD+1, vaddr, read_transfer, sim_core_unaligned_signal);
}
else
{
address_word paddr;
int uncached;
 
if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
isTARGET, isREAL))
{
const uword64 mask = 0x7;
const unsigned int reverse = ReverseEndian ? 1 : 0;
const unsigned int bigend = BigEndianCPU ? 1 : 0;
uword64 memval;
unsigned int byte;
 
paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
isDATA, isREAL);
byte = (vaddr & mask) ^ (bigend << 2);
return EXTEND32 (memval >> (8 * byte));
}
}
 
return 0;
}
 
/* Simulate the mips16 entry and exit pseudo-instructions. These
would normally be handled by the reserved instruction exception
code, but for ease of simulation we just handle them directly. */
 
static void
mips16_entry (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
unsigned int insn)
{
int aregs, sregs, rreg;
 
#ifdef DEBUG
printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
#endif /* DEBUG */
 
aregs = (insn & 0x700) >> 8;
sregs = (insn & 0x0c0) >> 6;
rreg = (insn & 0x020) >> 5;
 
/* This should be checked by the caller. */
if (sregs == 3)
abort ();
 
if (aregs < 5)
{
int i;
signed_word tsp;
 
/* This is the entry pseudo-instruction. */
 
for (i = 0; i < aregs; i++)
store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
 
tsp = SP;
SP -= 32;
 
if (rreg)
{
tsp -= 4;
store_word (SD, CPU, cia, (uword64) tsp, RA);
}
 
for (i = 0; i < sregs; i++)
{
tsp -= 4;
store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
}
}
else
{
int i;
signed_word tsp;
 
/* This is the exit pseudo-instruction. */
 
tsp = SP + 32;
 
if (rreg)
{
tsp -= 4;
RA = load_word (SD, CPU, cia, (uword64) tsp);
}
 
for (i = 0; i < sregs; i++)
{
tsp -= 4;
GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
}
 
SP += 32;
 
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
{
if (aregs == 5)
{
FGR[0] = WORD64LO (GPR[4]);
FPR_STATE[0] = fmt_uninterpreted;
}
else if (aregs == 6)
{
FGR[0] = WORD64LO (GPR[5]);
FGR[1] = WORD64LO (GPR[4]);
FPR_STATE[0] = fmt_uninterpreted;
FPR_STATE[1] = fmt_uninterpreted;
}
}
 
PC = RA;
}
}
 
/*-- trace support ----------------------------------------------------------*/
 
/* The TRACE support is provided (if required) in the memory accessing
routines. Since we are also providing the architecture specific
features, the architecture simulation code can also deal with
notifying the TRACE world of cache flushes, etc. Similarly we do
not need to provide profiling support in the simulator engine,
since we can sample in the instruction fetch control loop. By
defining the TRACE manifest, we add tracing as a run-time
option. */
 
#if defined(TRACE)
/* Tracing by default produces "din" format (as required by
dineroIII). Each line of such a trace file *MUST* have a din label
and address field. The rest of the line is ignored, so comments can
be included if desired. The first field is the label which must be
one of the following values:
 
0 read data
1 write data
2 instruction fetch
3 escape record (treated as unknown access type)
4 escape record (causes cache flush)
 
The address field is a 32bit (lower-case) hexadecimal address
value. The address should *NOT* be preceded by "0x".
 
The size of the memory transfer is not important when dealing with
cache lines (as long as no more than a cache line can be
transferred in a single operation :-), however more information
could be given following the dineroIII requirement to allow more
complete memory and cache simulators to provide better
results. i.e. the University of Pisa has a cache simulator that can
also take bus size and speed as (variable) inputs to calculate
complete system performance (a much more useful ability when trying
to construct an end product, rather than a processor). They
currently have an ARM version of their tool called ChARM. */
 
 
void
dotrace (SIM_DESC sd,
sim_cpu *cpu,
FILE *tracefh,
int type,
SIM_ADDR address,
int width,
char *comment,...)
{
if (STATE & simTRACE) {
va_list ap;
fprintf(tracefh,"%d %s ; width %d ; ",
type,
pr_addr(address),
width);
va_start(ap,comment);
vfprintf(tracefh,comment,ap);
va_end(ap);
fprintf(tracefh,"\n");
}
/* NOTE: Since the "din" format will only accept 32bit addresses, and
we may be generating 64bit ones, we should put the hi-32bits of the
address into the comment field. */
 
/* TODO: Provide a buffer for the trace lines. We can then avoid
performing writes until the buffer is filled, or the file is
being closed. */
 
/* NOTE: We could consider adding a comment field to the "din" file
produced using type 3 markers (unknown access). This would then
allow information about the program that the "din" is for, and
the MIPs world that was being simulated, to be placed into the
trace file. */
 
return;
}
#endif /* TRACE */
 
/*---------------------------------------------------------------------------*/
/*-- simulator engine -------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
 
static void
ColdReset (SIM_DESC sd)
{
int cpu_nr;
for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
{
sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
/* RESET: Fixed PC address: */
PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000);
/* The reset vector address is in the unmapped, uncached memory space. */
SR &= ~(status_SR | status_TS | status_RP);
SR |= (status_ERL | status_BEV);
/* Cheat and allow access to the complete register set immediately */
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
&& WITH_TARGET_WORD_BITSIZE == 64)
SR |= status_FR; /* 64bit registers */
/* Ensure that any instructions with pending register updates are
cleared: */
PENDING_INVALIDATE();
/* Initialise the FPU registers to the unknown state */
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
{
int rn;
for (rn = 0; (rn < 32); rn++)
FPR_STATE[rn] = fmt_uninterpreted;
}
/* Initialise the Config0 register. */
C0_CONFIG = 0x80000000 /* Config1 present */
| 2; /* KSEG0 uncached */
if (WITH_TARGET_WORD_BITSIZE == 64)
{
/* FIXME Currently mips/sim-main.c:address_translation()
truncates all addresses to 32-bits. */
if (0 && WITH_TARGET_ADDRESS_BITSIZE == 64)
C0_CONFIG |= (2 << 13); /* MIPS64, 64-bit addresses */
else
C0_CONFIG |= (1 << 13); /* MIPS64, 32-bit addresses */
}
if (BigEndianMem)
C0_CONFIG |= 0x00008000; /* Big Endian */
}
}
 
 
 
 
/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
/* Signal an exception condition. This will result in an exception
that aborts the instruction. The instruction operation pseudocode
will never see a return from this function call. */
 
void
signal_exception (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
int exception,...)
{
/* int vector; */
 
#ifdef DEBUG
sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
#endif /* DEBUG */
 
/* Ensure that any active atomic read/modify/write operation will fail: */
LLBIT = 0;
 
/* Save registers before interrupt dispatching */
#ifdef SIM_CPU_EXCEPTION_TRIGGER
SIM_CPU_EXCEPTION_TRIGGER(sd, cpu, cia);
#endif
 
switch (exception) {
 
case DebugBreakPoint:
if (! (Debug & Debug_DM))
{
if (INDELAYSLOT())
{
CANCELDELAYSLOT();
Debug |= Debug_DBD; /* signaled from within in delay slot */
DEPC = cia - 4; /* reference the branch instruction */
}
else
{
Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
DEPC = cia;
}
Debug |= Debug_DM; /* in debugging mode */
Debug |= Debug_DBp; /* raising a DBp exception */
PC = 0xBFC00200;
sim_engine_restart (SD, CPU, NULL, NULL_CIA);
}
break;
 
case ReservedInstruction:
{
va_list ap;
unsigned int instruction;
va_start(ap,exception);
instruction = va_arg(ap,unsigned int);
va_end(ap);
/* Provide simple monitor support using ReservedInstruction
exceptions. The following code simulates the fixed vector
entry points into the IDT monitor by causing a simulator
trap, performing the monitor operation, and returning to
the address held in the $ra register (standard PCS return
address). This means we only need to pre-load the vector
space with suitable instruction values. For systems were
actual trap instructions are used, we would not need to
perform this magic. */
if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
{
int reason = (instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK;
if (!sim_monitor (SD, CPU, cia, reason))
sim_io_error (sd, "sim_monitor: unhandled reason = %d, pc = 0x%s\n", reason, pr_addr (cia));
 
/* NOTE: This assumes that a branch-and-link style
instruction was used to enter the vector (which is the
case with the current IDT monitor). */
sim_engine_restart (SD, CPU, NULL, RA);
}
/* Look for the mips16 entry and exit instructions, and
simulate a handler for them. */
else if ((cia & 1) != 0
&& (instruction & 0xf81f) == 0xe809
&& (instruction & 0x0c0) != 0x0c0)
{
mips16_entry (SD, CPU, cia, instruction);
sim_engine_restart (sd, NULL, NULL, NULL_CIA);
}
/* else fall through to normal exception processing */
sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
}
 
default:
/* Store exception code into current exception id variable (used
by exit code): */
 
/* TODO: If not simulating exceptions then stop the simulator
execution. At the moment we always stop the simulation. */
 
#ifdef SUBTARGET_R3900
/* update interrupt-related registers */
 
/* insert exception code in bits 6:2 */
CAUSE = LSMASKED32(CAUSE, 31, 7) | LSINSERTED32(exception, 6, 2);
/* shift IE/KU history bits left */
SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 3, 0), 5, 2);
 
if (STATE & simDELAYSLOT)
{
STATE &= ~simDELAYSLOT;
CAUSE |= cause_BD;
EPC = (cia - 4); /* reference the branch instruction */
}
else
EPC = cia;
 
if (SR & status_BEV)
PC = (signed)0xBFC00000 + 0x180;
else
PC = (signed)0x80000000 + 0x080;
#else
/* See figure 5-17 for an outline of the code below */
if (! (SR & status_EXL))
{
CAUSE = (exception << 2);
if (STATE & simDELAYSLOT)
{
STATE &= ~simDELAYSLOT;
CAUSE |= cause_BD;
EPC = (cia - 4); /* reference the branch instruction */
}
else
EPC = cia;
/* FIXME: TLB et.al. */
/* vector = 0x180; */
}
else
{
CAUSE = (exception << 2);
/* vector = 0x180; */
}
SR |= status_EXL;
/* Store exception code into current exception id variable (used
by exit code): */
 
if (SR & status_BEV)
PC = (signed)0xBFC00200 + 0x180;
else
PC = (signed)0x80000000 + 0x180;
#endif
 
switch ((CAUSE >> 2) & 0x1F)
{
case Interrupt:
/* Interrupts arrive during event processing, no need to
restart */
return;
 
case NMIReset:
/* Ditto */
#ifdef SUBTARGET_3900
/* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
PC = (signed)0xBFC00000;
#endif /* SUBTARGET_3900 */
return;
 
case TLBModification:
case TLBLoad:
case TLBStore:
case AddressLoad:
case AddressStore:
case InstructionFetch:
case DataReference:
/* The following is so that the simulator will continue from the
exception handler address. */
sim_engine_halt (SD, CPU, NULL, PC,
sim_stopped, SIM_SIGBUS);
 
case ReservedInstruction:
case CoProcessorUnusable:
PC = EPC;
sim_engine_halt (SD, CPU, NULL, PC,
sim_stopped, SIM_SIGILL);
 
case IntegerOverflow:
case FPE:
sim_engine_halt (SD, CPU, NULL, PC,
sim_stopped, SIM_SIGFPE);
case BreakPoint:
sim_engine_halt (SD, CPU, NULL, PC, sim_stopped, SIM_SIGTRAP);
break;
 
case SystemCall:
case Trap:
sim_engine_restart (SD, CPU, NULL, PC);
break;
 
case Watch:
PC = EPC;
sim_engine_halt (SD, CPU, NULL, PC,
sim_stopped, SIM_SIGTRAP);
 
default: /* Unknown internal exception */
PC = EPC;
sim_engine_halt (SD, CPU, NULL, PC,
sim_stopped, SIM_SIGABRT);
 
}
 
case SimulatorFault:
{
va_list ap;
char *msg;
va_start(ap,exception);
msg = va_arg(ap,char *);
va_end(ap);
sim_engine_abort (SD, CPU, NULL_CIA,
"FATAL: Simulator error \"%s\"\n",msg);
}
}
 
return;
}
 
 
 
/* This function implements what the MIPS32 and MIPS64 ISAs define as
"UNPREDICTABLE" behaviour.
 
About UNPREDICTABLE behaviour they say: "UNPREDICTABLE results
may vary from processor implementation to processor implementation,
instruction to instruction, or as a function of time on the same
implementation or instruction. Software can never depend on results
that are UNPREDICTABLE. ..." (MIPS64 Architecture for Programmers
Volume II, The MIPS64 Instruction Set. MIPS Document MD00087 revision
0.95, page 2.)
For UNPREDICTABLE behaviour, we print a message, if possible print
the offending instructions mips.igen instruction name (provided by
the caller), and stop the simulator.
 
XXX FIXME: eventually, stopping the simulator should be made conditional
on a command-line option. */
void
unpredictable_action(sim_cpu *cpu, address_word cia)
{
SIM_DESC sd = CPU_STATE(cpu);
 
sim_io_eprintf(sd, "UNPREDICTABLE: PC = 0x%s\n", pr_addr (cia));
sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGABRT);
}
 
 
/*-- co-processor support routines ------------------------------------------*/
 
static int UNUSED
CoProcPresent(unsigned int coproc_number)
{
/* Return TRUE if simulator provides a model for the given co-processor number */
return(0);
}
 
void
cop_lw (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
int coproc_num,
int coproc_reg,
unsigned int memword)
{
switch (coproc_num)
{
case 1:
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
{
#ifdef DEBUG
printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
#endif
StoreFPR(coproc_reg,fmt_uninterpreted_32,(uword64)memword);
break;
}
 
default:
#if 0 /* this should be controlled by a configuration option */
sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
#endif
break;
}
 
return;
}
 
void
cop_ld (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
int coproc_num,
int coproc_reg,
uword64 memword)
{
 
#ifdef DEBUG
printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num, coproc_reg, pr_uword64(memword), pr_addr(cia) );
#endif
 
switch (coproc_num) {
case 1:
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
{
StoreFPR(coproc_reg,fmt_uninterpreted_64,memword);
break;
}
 
default:
#if 0 /* this message should be controlled by a configuration option */
sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
#endif
break;
}
 
return;
}
 
 
 
 
unsigned int
cop_sw (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
int coproc_num,
int coproc_reg)
{
unsigned int value = 0;
 
switch (coproc_num)
{
case 1:
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
{
value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted_32);
break;
}
 
default:
#if 0 /* should be controlled by configuration option */
sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
#endif
break;
}
 
return(value);
}
 
uword64
cop_sd (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
int coproc_num,
int coproc_reg)
{
uword64 value = 0;
switch (coproc_num)
{
case 1:
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
{
value = ValueFPR(coproc_reg,fmt_uninterpreted_64);
break;
}
 
default:
#if 0 /* should be controlled by configuration option */
sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
#endif
break;
}
 
return(value);
}
 
 
 
 
void
decode_coproc (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
unsigned int instruction)
{
int coprocnum = ((instruction >> 26) & 3);
 
switch (coprocnum)
{
case 0: /* standard CPU control and cache registers */
{
int code = ((instruction >> 21) & 0x1F);
int rt = ((instruction >> 16) & 0x1F);
int rd = ((instruction >> 11) & 0x1F);
int tail = instruction & 0x3ff;
/* R4000 Users Manual (second edition) lists the following CP0
instructions:
CODE><-RT><RD-><--TAIL--->
DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
ERET Exception return (VR4100 = 01000010000000000000000000011000)
*/
if (((code == 0x00) || (code == 0x04) /* MFC0 / MTC0 */
|| (code == 0x01) || (code == 0x05)) /* DMFC0 / DMTC0 */
&& tail == 0)
{
/* Clear double/single coprocessor move bit. */
code &= ~1;
 
/* M[TF]C0 (32 bits) | DM[TF]C0 (64 bits) */
switch (rd) /* NOTEs: Standard CP0 registers */
{
/* 0 = Index R4000 VR4100 VR4300 */
/* 1 = Random R4000 VR4100 VR4300 */
/* 2 = EntryLo0 R4000 VR4100 VR4300 */
/* 3 = EntryLo1 R4000 VR4100 VR4300 */
/* 4 = Context R4000 VR4100 VR4300 */
/* 5 = PageMask R4000 VR4100 VR4300 */
/* 6 = Wired R4000 VR4100 VR4300 */
/* 8 = BadVAddr R4000 VR4100 VR4300 */
/* 9 = Count R4000 VR4100 VR4300 */
/* 10 = EntryHi R4000 VR4100 VR4300 */
/* 11 = Compare R4000 VR4100 VR4300 */
/* 12 = SR R4000 VR4100 VR4300 */
#ifdef SUBTARGET_R3900
case 3:
/* 3 = Config R3900 */
case 7:
/* 7 = Cache R3900 */
case 15:
/* 15 = PRID R3900 */
 
/* ignore */
break;
 
case 8:
/* 8 = BadVAddr R4000 VR4100 VR4300 */
if (code == 0x00)
GPR[rt] = (signed_word) (signed_address) COP0_BADVADDR;
else
COP0_BADVADDR = GPR[rt];
break;
 
#endif /* SUBTARGET_R3900 */
case 12:
if (code == 0x00)
GPR[rt] = SR;
else
SR = GPR[rt];
break;
/* 13 = Cause R4000 VR4100 VR4300 */
case 13:
if (code == 0x00)
GPR[rt] = CAUSE;
else
CAUSE = GPR[rt];
break;
/* 14 = EPC R4000 VR4100 VR4300 */
case 14:
if (code == 0x00)
GPR[rt] = (signed_word) (signed_address) EPC;
else
EPC = GPR[rt];
break;
/* 15 = PRId R4000 VR4100 VR4300 */
#ifdef SUBTARGET_R3900
/* 16 = Debug */
case 16:
if (code == 0x00)
GPR[rt] = Debug;
else
Debug = GPR[rt];
break;
#else
/* 16 = Config R4000 VR4100 VR4300 */
case 16:
if (code == 0x00)
GPR[rt] = C0_CONFIG;
else
/* only bottom three bits are writable */
C0_CONFIG = (C0_CONFIG & ~0x7) | (GPR[rt] & 0x7);
break;
#endif
#ifdef SUBTARGET_R3900
/* 17 = Debug */
case 17:
if (code == 0x00)
GPR[rt] = DEPC;
else
DEPC = GPR[rt];
break;
#else
/* 17 = LLAddr R4000 VR4100 VR4300 */
#endif
/* 18 = WatchLo R4000 VR4100 VR4300 */
/* 19 = WatchHi R4000 VR4100 VR4300 */
/* 20 = XContext R4000 VR4100 VR4300 */
/* 26 = PErr or ECC R4000 VR4100 VR4300 */
/* 27 = CacheErr R4000 VR4100 */
/* 28 = TagLo R4000 VR4100 VR4300 */
/* 29 = TagHi R4000 VR4100 VR4300 */
/* 30 = ErrorEPC R4000 VR4100 VR4300 */
if (STATE_VERBOSE_P(SD))
sim_io_eprintf (SD,
"Warning: PC 0x%lx:interp.c decode_coproc DEADC0DE\n",
(unsigned long)cia);
GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
/* CPR[0,rd] = GPR[rt]; */
default:
if (code == 0x00)
GPR[rt] = (signed_word) (signed32) COP0_GPR[rd];
else
COP0_GPR[rd] = GPR[rt];
#if 0
if (code == 0x00)
sim_io_printf(sd,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
else
sim_io_printf(sd,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
#endif
}
}
else if ((code == 0x00 || code == 0x01)
&& rd == 16)
{
/* [D]MFC0 RT,C0_CONFIG,SEL */
signed32 cfg = 0;
switch (tail & 0x07)
{
case 0:
cfg = C0_CONFIG;
break;
case 1:
/* MIPS32 r/o Config1:
Config2 present */
cfg = 0x80000000;
/* MIPS16 implemented.
XXX How to check configuration? */
cfg |= 0x0000004;
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
/* MDMX & FPU implemented */
cfg |= 0x00000021;
break;
case 2:
/* MIPS32 r/o Config2:
Config3 present. */
cfg = 0x80000000;
break;
case 3:
/* MIPS32 r/o Config3:
SmartMIPS implemented. */
cfg = 0x00000002;
break;
}
GPR[rt] = cfg;
}
else if (code == 0x10 && (tail & 0x3f) == 0x18)
{
/* ERET */
if (SR & status_ERL)
{
/* Oops, not yet available */
sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
PC = EPC;
SR &= ~status_ERL;
}
else
{
PC = EPC;
SR &= ~status_EXL;
}
}
else if (code == 0x10 && (tail & 0x3f) == 0x10)
{
/* RFE */
#ifdef SUBTARGET_R3900
/* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
 
/* shift IE/KU history bits right */
SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2), 3, 0);
 
/* TODO: CACHE register */
#endif /* SUBTARGET_R3900 */
}
else if (code == 0x10 && (tail & 0x3f) == 0x1F)
{
/* DERET */
Debug &= ~Debug_DM;
DELAYSLOT();
DSPC = DEPC;
}
else
sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
/* TODO: When executing an ERET or RFE instruction we should
clear LLBIT, to ensure that any out-standing atomic
read/modify/write sequence fails. */
}
break;
case 2: /* co-processor 2 */
{
int handle = 0;
 
 
if(! handle)
{
sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
instruction,pr_addr(cia));
}
}
break;
case 1: /* should not occur (FPU co-processor) */
case 3: /* should not occur (FPU co-processor) */
SignalException(ReservedInstruction,instruction);
break;
}
return;
}
 
 
/* This code copied from gdb's utils.c. Would like to share this code,
but don't know of a common place where both could get to it. */
 
/* Temporary storage using circular buffer */
#define NUMCELLS 16
#define CELLSIZE 32
static char*
get_cell (void)
{
static char buf[NUMCELLS][CELLSIZE];
static int cell=0;
if (++cell>=NUMCELLS) cell=0;
return buf[cell];
}
 
/* Print routines to handle variable size regs, etc */
 
/* Eliminate warning from compiler on 32-bit systems */
static int thirty_two = 32;
 
char*
pr_addr(addr)
SIM_ADDR addr;
{
char *paddr_str=get_cell();
switch (sizeof(addr))
{
case 8:
sprintf(paddr_str,"%08lx%08lx",
(unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
break;
case 4:
sprintf(paddr_str,"%08lx",(unsigned long)addr);
break;
case 2:
sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
break;
default:
sprintf(paddr_str,"%x",addr);
}
return paddr_str;
}
 
char*
pr_uword64(addr)
uword64 addr;
{
char *paddr_str=get_cell();
sprintf(paddr_str,"%08lx%08lx",
(unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
return paddr_str;
}
 
 
void
mips_core_signal (SIM_DESC sd,
sim_cpu *cpu,
sim_cia cia,
unsigned map,
int nr_bytes,
address_word addr,
transfer_type transfer,
sim_core_signals sig)
{
const char *copy = (transfer == read_transfer ? "read" : "write");
address_word ip = CIA_ADDR (cia);
 
switch (sig)
{
case sim_core_unmapped_signal:
sim_io_eprintf (sd, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
nr_bytes, copy,
(unsigned long) addr, (unsigned long) ip);
COP0_BADVADDR = addr;
SignalExceptionDataReference();
break;
 
case sim_core_unaligned_signal:
sim_io_eprintf (sd, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
nr_bytes, copy,
(unsigned long) addr, (unsigned long) ip);
COP0_BADVADDR = addr;
if(transfer == read_transfer)
SignalExceptionAddressLoad();
else
SignalExceptionAddressStore();
break;
 
default:
sim_engine_abort (sd, cpu, cia,
"mips_core_signal - internal error - bad switch");
}
}
 
 
void
mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia)
{
ASSERT(cpu != NULL);
 
if(cpu->exc_suspended > 0)
sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", cpu->exc_suspended);
 
PC = cia;
memcpy(cpu->exc_trigger_registers, cpu->registers, sizeof(cpu->exc_trigger_registers));
cpu->exc_suspended = 0;
}
 
void
mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception)
{
ASSERT(cpu != NULL);
 
if(cpu->exc_suspended > 0)
sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n",
cpu->exc_suspended, exception);
 
memcpy(cpu->exc_suspend_registers, cpu->registers, sizeof(cpu->exc_suspend_registers));
memcpy(cpu->registers, cpu->exc_trigger_registers, sizeof(cpu->registers));
cpu->exc_suspended = exception;
}
 
void
mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception)
{
ASSERT(cpu != NULL);
 
if(exception == 0 && cpu->exc_suspended > 0)
{
/* warn not for breakpoints */
if(cpu->exc_suspended != sim_signal_to_host(sd, SIM_SIGTRAP))
sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n",
cpu->exc_suspended);
}
else if(exception != 0 && cpu->exc_suspended > 0)
{
if(exception != cpu->exc_suspended)
sim_io_eprintf(sd, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
cpu->exc_suspended, exception);
memcpy(cpu->registers, cpu->exc_suspend_registers, sizeof(cpu->registers));
}
else if(exception != 0 && cpu->exc_suspended == 0)
{
sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
}
cpu->exc_suspended = 0;
}
 
 
/*---------------------------------------------------------------------------*/
/*> EOF interp.c <*/
interp.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: m16.igen =================================================================== --- m16.igen (nonexistent) +++ m16.igen (revision 33) @@ -0,0 +1,1236 @@ +// -*- C -*- +// +// +// MIPS Architecture: +// +// CPU Instruction Set (mips16) +// + +// The instructions in this section are ordered according +// to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf. + + +// The MIPS16 codes registers in a special way, map from one to the other. +// ::::::: +:compute:::int:TRX:RX:((RX < 2) ? (16 + RX) \: RX) +:compute:::int:TRY:RY:((RY < 2) ? (16 + RY) \: RY) +:compute:::int:TRZ:RZ:((RZ < 2) ? (16 + RZ) \: RZ) +:compute:::int:SHIFT:SHAMT:((SHAMT == 0) ? 8 \: SHAMT) + +:compute:::int:SHAMT:SHAMT_4_0,S5:(LSINSERTED (S5, 5, 5) | SHAMT_4_0) + +:compute:::address_word:IMMEDIATE:IMM_25_21,IMM_20_16,IMMED_15_0:(LSINSERTED (IMM_25_21, 25, 21) | LSINSERTED (IMM_20_16, 20, 16) | LSINSERTED (IMMED_15_0, 15, 0)) +:compute:::int:R32:R32L,R32H:((R32H << 3) | R32L) + +:compute:::address_word:IMMEDIATE:IMM_10_5,IMM_15_11,IMM_4_0:(LSINSERTED (IMM_10_5, 10, 5) | LSINSERTED (IMM_15_11, 15, 11) | LSINSERTED (IMM_4_0, 4, 0)) + +:compute:::address_word:IMMEDIATE:IMM_10_4,IMM_14_11,IMM_3_0:(LSINSERTED (IMM_10_4, 10, 4) | LSINSERTED (IMM_14_11, 14, 11) | LSINSERTED (IMM_3_0, 3, 0)) + + +// Load and Store Instructions + + +10000,3.RX,3.RY,5.IMMED:RRI:16::LB +"lb r, (r)" +*mips16: +*vr4100: +{ + GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED)); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 10000,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LB +"lb r, (r)" +*mips16: +*vr4100: +{ + GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE))); +} + + + +10100,3.RX,3.RY,5.IMMED:RRI:16::LBU +"lbu r, (r)" +*mips16: +*vr4100: +{ + GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 10100,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LBU +"lbu r, (r)" +*mips16: +*vr4100: +{ + GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE)); +} + + + +10001,3.RX,3.RY,5.IMMED:RRI:16::LH +"lh r, (r)" +*mips16: +*vr4100: +{ + GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1)); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 10001,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LH +"lh r, (r)" +*mips16: +*vr4100: +{ + GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE))); +} + + + +10101,3.RX,3.RY,5.IMMED:RRI:16::LHU +"lhu r, (r)" +*mips16: +*vr4100: +{ + GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 10101,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LHU +"lhu r, (r)" +*mips16: +*vr4100: +{ + GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE)); +} + + + +10011,3.RX,3.RY,5.IMMED:RRI:16::LW +"lw r, (r)" +*mips16: +*vr4100: +{ + GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2)); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 10011,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LW +"lw r, (r)" +*mips16: +*vr4100: +{ + GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE))); +} + + + +10110,3.RX,8.IMMED:RI:16::LWPC +"lw r, (PC)" +*mips16: +*vr4100: +{ + GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, + basepc (SD_) & ~3, IMMED << 2)); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 10110,3.RX,000,5.IMM_4_0:EXT-RI:16::LWPC +"lw r, (PC)" +*mips16: +*vr4100: +{ + GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, basepc (SD_) & ~3, EXTEND16 (IMMEDIATE))); +} + + + +10010,3.RX,8.IMMED:RI:16::LWSP +"lw r, (SP)" +*mips16: +*vr4100: +{ + GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMMED << 2)); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 10010,3.RX,000,5.IMM_4_0:EXT-RI:16::LWSP +"lw r, (SP)" +*mips16: +*vr4100: +{ + GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE))); +} + + + +10111,3.RX,3.RY,5.IMMED:RRI:16::LWU +"lwu r, (r)" +*mips16: +*vr4100: +{ + GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 10111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LWU +"lwu r, (r)" +*mips16: +*vr4100: +{ + GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE)); +} + + + +00111,3.RX,3.RY,5.IMMED:RRI:16::LD +"ld r, (r)" +*mips16: +*vr4100: +{ + GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 00111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LD +"ld r, (r)" +*mips16: +*vr4100: +{ + GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], EXTEND16 (IMMEDIATE)); +} + + + +11111,100,3.RY,5.IMMED:RI64:16::LDPC +"ld r, (PC)" +*mips16: +*vr4100: +{ + GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, + basepc (SD_) & ~7, IMMED << 3); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 11111,100,3.RY,5.IMM_4_0:EXT-RI64:16::LDPC +"ld r, (PC)" +*mips16: +*vr4100: +{ + GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, basepc (SD_) & ~7, EXTEND16 (IMMEDIATE)); +} + + + +11111,000,3.RY,5.IMMED:RI64:16::LDSP +"ld r, (SP)" +*mips16: +*vr4100: +{ + GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 11111,000,3.RY,5.IMM_4_0:EXT-RI64:16::LDSP +"ld r, (SP)" +*mips16: +*vr4100: +{ + GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE)); +} + + + +11000,3.RX,3.RY,5.IMMED:RRI:16::SB +"sb r, (r)" +*mips16: +*vr4100: +{ + do_store (SD_, AccessLength_BYTE, GPR[TRX], IMMED, GPR[TRY]); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 11000,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SB +"sb r, (r)" +*mips16: +*vr4100: +{ + do_store (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]); +} + + + +11001,3.RX,3.RY,5.IMMED:RRI:16::SH +"sh r, (r)" +*mips16: +*vr4100: +{ + do_store (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1, GPR[TRY]); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 11001,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SH +"sh r, (r)" +*mips16: +*vr4100: +{ + do_store (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]); +} + + + +11011,3.RX,3.RY,5.IMMED:RRI:16::SW +"sw r, (r)" +*mips16: +*vr4100: +{ + do_store (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2, GPR[TRY]); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 11011,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SW +"sw r, (r)" +*mips16: +*vr4100: +{ + do_store (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]); +} + + + +11010,3.RX,8.IMMED:RI:16::SWSP +"sw r, (SP)" +*mips16: +*vr4100: +{ + do_store (SD_, AccessLength_WORD, SP, IMMED << 2, GPR[TRX]); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 11010,3.RX,000,5.IMM_4_0:EXT-RI:16::SWSP +"sw r, (SP)" +*mips16: +*vr4100: +{ + do_store (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE), GPR[TRX]); +} + + + +01100,010,8.IMMED:I8:16::SWRASP +"sw r, (SP)" +*mips16: +*vr4100: +{ + do_store (SD_, AccessLength_WORD, SP, IMMED << 2, RA); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 01100,010,000,5.IMM_4_0:EXT-I8:16::SWRASP +"sw r, (SP)" +*mips16: +*vr4100: +{ + do_store (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE), RA); +} + + + +01111,3.RX,3.RY,5.IMMED:RRI:16::SD +"sd r, (r)" +*mips16: +*vr4100: +{ + do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3, GPR[TRY]); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 01111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SD +"sd r, (r)" +*mips16: +*vr4100: +{ + do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]); +} + + + +11111,001,3.RY,5.IMMED:RI64:16::SDSP +"sd r, (SP)" +*mips16: +*vr4100: +{ + do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, GPR[TRY]); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 11111,001,3.RY,5.IMM_4_0:EXT-RI64:16::SDSP +"sd r, (SP)" +*mips16: +*vr4100: +{ + do_store (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE), GPR[TRY]); +} + + + +11111,010,8.IMMED:I64:16::SDRASP +"sd r, (SP)" +*mips16: +*vr4100: +{ + do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, RA); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 11111,010,000,5.IMM_4_0:EXT-I64:16::SDRASP +"sd r, (SP)" +*mips16: +*vr4100: +{ + do_store (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE), RA); +} + + + +// ALU Immediate Instructions + + +01101,3.RX,8.IMMED:RI:16::LI +"li r, " +*mips16: +*vr4100: +{ + do_ori (SD_, 0, TRX, IMMED); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 01101,3.RX,000,5.IMM_4_0:EXT-RI:16::LI +"li r, " +*mips16: +*vr4100: +{ + do_ori (SD_, 0, TRX, IMMEDIATE); +} + + + +01000,3.RX,3.RY,0,4.IMMED:RRI-A:16::ADDIU +"addiu r, r, " +*mips16: +*vr4100: +{ + do_addiu (SD_, TRX, TRY, EXTEND4 (IMMED)); +} + +11110,7.IMM_10_4,4.IMM_14_11 + 01000,3.RX,3.RY,0,4.IMM_3_0:EXT-RRI-A:16::ADDIU +"addiu r, r, " +*mips16: +*vr4100: +{ + do_addiu (SD_, TRX, TRY, EXTEND15 (IMMEDIATE)); +} + + + +01001,3.RX,8.IMMED:RI:16::ADDIU8 +"addiu r, " +*mips16: +*vr4100: +{ + do_addiu (SD_, TRX, TRX, EXTEND8 (IMMED)); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 01001,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIU8 +"addiu r, " +*mips16: +*vr4100: +{ + do_addiu (SD_, TRX, TRX, EXTEND16 (IMMEDIATE)); +} + + + +01100,011,8.IMMED:I8:16::ADJSP +"addiu SP, " +*mips16: +*vr4100: +{ + do_addiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 01100,011,000,5.IMM_4_0:EXT-I8:16::ADJSP +"addiu SP, " +*mips16: +*vr4100: +{ + do_addiu (SD_, SPIDX, SPIDX, EXTEND16 (IMMEDIATE)); +} + + + +00001,3.RX,8.IMMED:RI:16::ADDIUPC +"addiu r, PC, " +*mips16: +*vr4100: +{ + unsigned32 temp = (basepc (SD_) & ~3) + (IMMED << 2); + GPR[TRX] = EXTEND32 (temp); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 00001,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIUPC +"addiu r, PC, " +*mips16: +*vr4100: +{ + unsigned32 temp = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE); + GPR[TRX] = EXTEND32 (temp); +} + + + +00000,3.RX,8.IMMED:RI:16::ADDIUSP +"addiu r, SP, " +*mips16: +*vr4100: +{ + do_addiu (SD_, SPIDX, TRX, IMMED << 2); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 00000,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIUSP +"addiu r, SP, " +*mips16: +*vr4100: +{ + do_addiu (SD_, SPIDX, TRX, EXTEND16 (IMMEDIATE)); +} + + + +01000,3.RX,3.RY,1,4.IMMED:RRI-A:16::DADDIU +"daddiu r, r, " +*mips16: +*vr4100: +{ + do_daddiu (SD_, TRX, TRY, EXTEND4 (IMMED)); +} + +11110,7.IMM_10_4,4.IMM_14_11 + 01000,3.RX,3.RY,1,4.IMM_3_0:EXT-RRI-A:16::DADDIU +"daddiu r, r, " +*mips16: +*vr4100: +{ + do_daddiu (SD_, TRX, TRY, EXTEND15 (IMMEDIATE)); +} + + + +11111,101,3.RY,5.IMMED:RI64:16::DADDIU5 +"daddiu r, " +*mips16: +*vr4100: +{ + do_daddiu (SD_, TRY, TRY, EXTEND5 (IMMED)); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 11111,101,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIU5 +"daddiu r, " +*mips16: +*vr4100: +{ + do_daddiu (SD_, TRY, TRY, EXTEND16 (IMMEDIATE)); +} + + + +11111,011,8.IMMED:I64:16::DADJSP +"daddiu SP, " +*mips16: +*vr4100: +{ + do_daddiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 11111,011,000,5.IMM_4_0:EXT-I64:16::DADJSP +"daddiu SP, " +*mips16: +*vr4100: +{ + do_daddiu (SD_, SPIDX, SPIDX, EXTEND16 (IMMEDIATE)); +} + + + +11111,110,3.RY,5.IMMED:RI64:16::DADDIUPC +"daddiu r, PC, " +*mips16: +*vr4100: +{ + GPR[TRY] = (basepc (SD_) & ~3) + (IMMED << 2); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 11111,110,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIUPC +"daddiu r, PC, " +*mips16: +*vr4100: +{ + GPR[TRY] = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE); +} + + + +11111,111,3.RY,5.IMMED:RI64:16::DADDIUSP +"daddiu r, SP, " +*mips16: +*vr4100: +{ + do_daddiu (SD_, SPIDX, TRY, IMMED << 2); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 11111,111,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIUSP +"daddiu r, SP, " +*mips16: +*vr4100: +{ + do_daddiu (SD_, SPIDX, TRY, EXTEND16 (IMMEDIATE)); +} + + + +01010,3.RX,8.IMMED:RI:16::SLTI +"slti r, " +*mips16: +*vr4100: +{ + do_slti (SD_, TRX, T8IDX, IMMED); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 01010,3.RX,000,5.IMM_4_0:EXT-RI:16::SLTI +"slti r, " +*mips16: +*vr4100: +{ + do_slti (SD_, TRX, T8IDX, IMMEDIATE); +} + + + +01011,3.RX,8.IMMED:RI:16::SLTIU +"sltiu r, " +*mips16: +*vr4100: +{ + do_sltiu (SD_, TRX, T8IDX, IMMED); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 01011,3.RX,000,5.IMM_4_0:EXT-RI:16::SLTIU +"sltiu r, " +*mips16: +*vr4100: +{ + do_sltiu (SD_, TRX, T8IDX, IMMEDIATE); +} + + + +11101,3.RX,3.RY,01010:RR:16::CMP +"cmp r, r" +*mips16: +*vr4100: +{ + do_xor (SD_, TRX, TRY, T8IDX); +} + + +01110,3.RX,8.IMMED:RI:16::CMPI +"cmpi r, " +*mips16: +*vr4100: +{ + do_xori (SD_, TRX, T8IDX, IMMED); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 01110,3.RX,000,5.IMM_4_0:EXT-RI:16::CMPI +"sltiu r, " +*mips16: +*vr4100: +{ + do_xori (SD_, TRX, T8IDX, IMMEDIATE); +} + + + +// Two/Three Operand, Register-Type + + + +11100,3.RX,3.RY,3.RZ,01:RRR:16::ADDU +"addu r, r, r" +*mips16: +*vr4100: +{ + do_addu (SD_, TRX, TRY, TRZ); +} + + + +11100,3.RX,3.RY,3.RZ,11:RRR:16::SUBU +"subu r, r, r" +*mips16: +*vr4100: +{ + do_subu (SD_, TRX, TRY, TRZ); +} + +11100,3.RX,3.RY,3.RZ,00:RRR:16::DADDU +"daddu r, r, r" +*mips16: +*vr4100: +{ + do_daddu (SD_, TRX, TRY, TRZ); +} + + + +11100,3.RX,3.RY,3.RZ,10:RRR:16::DSUBU +"dsubu r, r, r" +*mips16: +*vr4100: +{ + do_dsubu (SD_, TRX, TRY, TRZ); +} + + + +11101,3.RX,3.RY,00010:RR:16::SLT +"slt r, r" +*mips16: +*vr4100: +{ + do_slt (SD_, TRX, TRY, T8IDX); +} + + + +11101,3.RX,3.RY,00011:RR:16::SLTU +"sltu r, r" +*mips16: +*vr4100: +{ + do_sltu (SD_, TRX, TRY, T8IDX); +} + + + +11101,3.RX,3.RY,01011:RR:16::NEG +"neg r, r" +*mips16: +*vr4100: +{ + do_subu (SD_, 0, TRY, TRX); +} + + + +11101,3.RX,3.RY,01100:RR:16::AND +"and r, r" +*mips16: +*vr4100: +{ + do_and (SD_, TRX, TRY, TRX); +} + + + +11101,3.RX,3.RY,01101:RR:16::OR +"or r, r" +*mips16: +*vr4100: +{ + do_or (SD_, TRX, TRY, TRX); +} + + + +11101,3.RX,3.RY,01110:RR:16::XOR +"xor r, r" +*mips16: +*vr4100: +{ + do_xor (SD_, TRX, TRY, TRX); +} + + + +11101,3.RX,3.RY,01111:RR:16::NOT +"not r, r" +*mips16: +*vr4100: +{ + do_nor (SD_, 0, TRY, TRX); +} + + + +01100,111,3.RY,5.R32:I8_MOVR32:16::MOVR32 +"move r, r" +*mips16: +*vr4100: +{ + do_or (SD_, R32, 0, TRY); +} + + + +01100,101,3.R32L,2.R32H,3.RZ:I8_MOV32R:16::MOV32R +"move r, r" +*mips16: +*vr4100: +{ + do_or (SD_, TRZ, 0, R32); +} + + + +00110,3.RX,3.RY,3.SHAMT,00:SHIFT:16::SLL +"sll r, r, " +*mips16: +*vr4100: +{ + do_sll (SD_, TRY, TRX, SHIFT); +} + +11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,00:EXT-SHIFT:16::SLL +"sll r, r, " +*mips16: +*vr4100: +{ + do_sll (SD_, TRY, TRX, SHAMT); +} + + + +00110,3.RX,3.RY,3.SHAMT,10:SHIFT:16::SRL +"srl r, r, " +*mips16: +*vr4100: +{ + do_srl (SD_, TRY, TRX, SHIFT); +} + +11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,10:EXT-SHIFT:16::SRL +"srl r, r, " +*mips16: +*vr4100: +{ + do_srl (SD_, TRY, TRX, SHAMT); +} + + + +00110,3.RX,3.RY,3.SHAMT,11:SHIFT:16::SRA +"sra r, r, " +*mips16: +*vr4100: +{ + do_sra (SD_, TRY, TRX, SHIFT); +} + +11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,11:EXT-SHIFT:16::SRA +"sra r, r, " +*mips16: +*vr4100: +{ + do_sra (SD_, TRY, TRX, SHAMT); +} + + + +11101,3.RX,3.RY,00100:RR:16::SLLV +"sllv r, r" +*mips16: +*vr4100: +{ + do_sllv (SD_, TRX, TRY, TRY); +} + + +11101,3.RX,3.RY,00110:RR:16::SRLV +"srlv r, r" +*mips16: +*vr4100: +{ + do_srlv (SD_, TRX, TRY, TRY); +} + + +11101,3.RX,3.RY,00111:RR:16::SRAV +"srav r, r" +*mips16: +*vr4100: +{ + do_srav (SD_, TRX, TRY, TRY); +} + + +00110,3.RX,3.RY,3.SHAMT,01:SHIFT:16::DSLL +"dsll r, r, " +*mips16: +*vr4100: +{ + do_dsll (SD_, TRY, TRX, SHIFT); +} + +11110,5.SHAMT_4_0,1.S5,00000 + 00110,3.RX,3.RY,000,01:EXT-SHIFT:16::DSLL +"dsll r, r, " +*mips16: +*vr4100: +{ + do_dsll (SD_, TRY, TRX, SHAMT); +} + + + +11101,3.SHAMT,3.RY,01000:SHIFT64:16::DSRL +"dsrl r, " +*mips16: +*vr4100: +{ + do_dsrl (SD_, TRY, TRY, SHIFT); +} + +11110,5.SHAMT_4_0,1.S5,00000 + 11101,000,3.RY,01000:EXT-SHIFT64:16::DSRL +"dsrl r, " +*mips16: +*vr4100: +{ + do_dsrl (SD_, TRY, TRY, SHAMT); +} + + + +11101,3.SHAMT,3.RY,10011:SHIFT64:16::DSRA +"dsra r, " +*mips16: +*vr4100: +{ + do_dsra (SD_, TRY, TRY, SHIFT); +} + +11110,5.SHAMT_4_0,1.S5,00000 + 11101,000,3.RY,10011:EXT-SHIFT64:16::DSRA +"dsra r, " +*mips16: +*vr4100: +{ + do_dsra (SD_, TRY, TRY, SHAMT); +} + + + +11101,3.RX,3.RY,10100:RR:16::DSLLV +"dsllv r, r" +*mips16: +*vr4100: +{ + do_dsllv (SD_, TRX, TRY, TRY); +} + + +11101,3.RX,3.RY,10110:RR:16::DSRLV +"dsrlv r, r" +*mips16: +*vr4100: +{ + do_dsrlv (SD_, TRX, TRY, TRY); +} + + +11101,3.RX,3.RY,10111:RR:16::DSRAV +"dsrav r, r" +*mips16: +*vr4100: +{ + do_dsrav (SD_, TRX, TRY, TRY); +} + + +// Multiply /Divide Instructions + + +11101,3.RX,3.RY,11000:RR:16::MULT +"mult r, r" +*mips16: +*vr4100: +{ + do_mult (SD_, TRX, TRY, 0); +} + + +11101,3.RX,3.RY,11001:RR:16::MULTU +"multu r, r" +*mips16: +*vr4100: +{ + do_multu (SD_, TRX, TRY, 0); +} + + +11101,3.RX,3.RY,11010:RR:16::DIV +"div r, r" +*mips16: +*vr4100: +{ + do_div (SD_, TRX, TRY); +} + + +11101,3.RX,3.RY,11011:RR:16::DIVU +"divu r, r" +*mips16: +*vr4100: +{ + do_divu (SD_, TRX, TRY); +} + + +11101,3.RX,000,10000:RR:16::MFHI +"mfhi r" +*mips16: +*vr4100: +{ + do_mfhi (SD_, TRX); +} + + +11101,3.RX,000,10010:RR:16::MFLO +"mflo r" +*mips16: +*vr4100: +{ + do_mflo (SD_, TRX); +} + + +11101,3.RX,3.RY,11100:RR:16::DMULT +"dmult r, r" +*mips16: +*vr4100: +{ + do_dmult (SD_, TRX, TRY, 0); +} + + +11101,3.RX,3.RY,11101:RR:16::DMULTU +"dmultu r, r" +*mips16: +*vr4100: +{ + do_dmultu (SD_, TRX, TRY, 0); +} + + +11101,3.RX,3.RY,11110:RR:16::DDIV +"ddiv r, r" +*mips16: +*vr4100: +{ + do_ddiv (SD_, TRX, TRY); +} + + +11101,3.RX,3.RY,11111:RR:16::DDIVU +"ddivu r, r" +*mips16: +*vr4100: +{ + do_ddivu (SD_, TRX, TRY); +} + + +// Jump and Branch Instructions + + + +// Issue instruction in delay slot of branch +:function:::address_word:delayslot16:address_word nia, address_word target +{ + instruction_word delay_insn; + sim_events_slip (SD, 1); + DSPC = CIA; /* save current PC somewhere */ + STATE |= simDELAYSLOT; + delay_insn = IMEM16 (nia); /* NOTE: mips16 */ + idecode_issue (CPU_, delay_insn, (nia)); + STATE &= ~simDELAYSLOT; + return target; +} + +// compute basepc dependant on us being in a delay slot +:function:::address_word:basepc: +{ + if (STATE & simDELAYSLOT) + { + return DSPC; /* return saved address of preceeding jmp */ + } + else + { + return CIA; + } +} + + +// JAL +00011,0,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:JAL:16::JAL +"jal " +*mips16: +*vr4100: +{ + address_word region = (NIA & MASK (63, 28)); + RA = NIA + 2; /* skip 16 bit delayslot insn */ + NIA = delayslot16 (SD_, NIA, (region | (IMMEDIATE << 2))) | 1; +} + + + +// JALX - 32 and 16 bit versions. + +011101,26.IMMED:JALX:32::JALX32 +"jalx " +*mips16: +*vr4100: +{ + address_word region = (NIA & MASK (63, 28)); + RA = NIA + 4; /* skip 32 bit delayslot insn */ + NIA = delayslot32 (SD_, (region | (IMMED << 2)) | 1); +} + +00011,1,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:JALX:16::JALX16 +"jalx " +*mips16: +*vr4100: +{ + address_word region = (NIA & MASK (63, 28)); + RA = NIA + 2; /* 16 bit INSN */ + NIA = delayslot16 (SD_, NIA, (region | (IMMEDIATE << 2)) & ~1); +} + + + +11101,3.RX,000,00000:RR:16::JR +"jr r" +*mips16: +*vr4100: +{ + NIA = delayslot16 (SD_, NIA, GPR[TRX]); +} + + +11101,000,001,00000:RR:16::JRRA +"jrra" +*mips16: +*vr4100: +{ + NIA = delayslot16 (SD_, NIA, RA); +} + + + +11101,3.RX,010,00000:RR:16::JALR +"jalr r" +*mips16: +*vr4100: +{ + RA = NIA + 2; + NIA = delayslot16 (SD_, NIA, GPR[TRX]); +} + + + +00100,3.RX,8.IMMED:RI:16::BEQZ +"beqz r, " +*mips16: +*vr4100: +{ + if (GPR[TRX] == 0) + NIA = (NIA + (EXTEND8 (IMMED) << 1)); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 00100,3.RX,000,5.IMM_4_0:EXT-RI:16::BEQZ +"beqz r, " +*mips16: +*vr4100: +{ + if (GPR[TRX] == 0) + NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1)); +} + + + +00101,3.RX,8.IMMED:RI:16::BNEZ +"bnez r, " +*mips16: +*vr4100: +{ + if (GPR[TRX] != 0) + NIA = (NIA + (EXTEND8 (IMMED) << 1)); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 00101,3.RX,000,5.IMM_4_0:EXT-RI:16::BNEZ +"bnez r, " +*mips16: +*vr4100: +{ + if (GPR[TRX] != 0) + NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1)); +} + + + +01100,000,8.IMMED:I8:16::BTEQZ +"bteqz " +*mips16: +*vr4100: +{ + if (T8 == 0) + NIA = (NIA + (EXTEND8 (IMMED) << 1)); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 01100,000,000,5.IMM_4_0:EXT-I8:16::BTEQZ +"bteqz " +*mips16: +*vr4100: +{ + if (T8 == 0) + NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1)); +} + + + +01100,001,8.IMMED:I8:16::BTNEZ +"btnez " +*mips16: +*vr4100: +{ + if (T8 != 0) + NIA = (NIA + (EXTEND8 (IMMED) << 1)); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 01100,001,000,5.IMM_4_0:EXT-I8:16::BTNEZ +"btnez " +*mips16: +*vr4100: +{ + if (T8 != 0) + NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1)); +} + + + +00010,11.IMMED:I:16::B +"b " +*mips16: +*vr4100: +{ + NIA = (NIA + (EXTEND11 (IMMED) << 1)); +} + +11110,6.IMM_10_5,5.IMM_15_11 + 00010,6.0,5.IMM_4_0:EXT-I:16::B +"b " +*mips16: +*vr4100: +{ + NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1)); +} + + + +11101,3.RX,3.RY,00101:RR:16::BREAK +"break" +*mips16: +*vr4100: +{ + if (STATE & simDELAYSLOT) + PC = cia - 2; /* reference the branch instruction */ + else + PC = cia; + SignalException (BreakPoint, instruction_0); +} Index: dv-tx3904tmr.c =================================================================== --- dv-tx3904tmr.c (nonexistent) +++ dv-tx3904tmr.c (revision 33) @@ -0,0 +1,698 @@ +/* This file is part of the program GDB, the GNU debugger. + + Copyright (C) 1998, 2007, 2008 Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + */ + + +#include "sim-main.h" +#include "hw-main.h" + + +/* DEVICE + + + tx3904tmr - tx3904 timer + + + DESCRIPTION + + + Implements one tx3904 timer/counter described in the tx3904 + user guide. Three instances are required for TMR0, TMR1, and + TMR3 within the tx3904, at different base addresses. + + Both internal and system clocks are synthesized as divided versions + of the simulator clock. + + There is no support for: + - edge sensitivity of external clock + - different mode restrictions for TMR0..2 + - level interrupts (interrupts are treated as events that occur at edges) + + + + PROPERTIES + + + reg + + Base of TMR control register bank. must equal 0x100. + Register offsets: 0: TCR: timer control register + 4: TISR: timer interrupt status register + 8: CPRA: compare register A + 12: CPRB: compare register B + 16: ITMR: interval timer mode register + 32: CCDR: divider register + 48: PMGR: pulse generator mode register + 64: WTMR: watchdog timer mode register + 240: TRR: timer read register + + + clock + + Rate of timer clock signal. This number is the number of simulator + ticks per clock signal tick. Default 1. + + + ext + + Rate of "external input clock signal", the other clock input of the + timer. It uses the same scale as above. Default 100. + + + + PORTS + + + int (output) + + Interrupt port. An event is generated when a timer interrupt + occurs. + + + ff (output) + + Flip-flop output, corresponds to the TMFFOUT port. An event is + generated when flip-flop changes value. The integer associated + with the event is 1/0 according to flip-flop value. + + + reset (input) + + Reset port. + + */ + + + +/* static functions */ + +static void deliver_tx3904tmr_tick (struct hw *me, void *data); + + +/* register numbers; each is one word long */ +enum +{ + TCR_REG = 0, + TISR_REG = 1, + CPRA_REG = 2, + CPRB_REG = 3, + ITMR_REG = 4, + CCDR_REG = 8, + PMGR_REG = 12, + WTMR_REG = 16, + TRR_REG = 60 +}; + + + +/* port ID's */ + +enum + { + RESET_PORT, + INT_PORT, + FF_PORT +}; + + +static const struct hw_port_descriptor tx3904tmr_ports[] = +{ + { "int", INT_PORT, 0, output_port, }, + { "ff", FF_PORT, 0, output_port, }, + { "reset", RESET_PORT, 0, input_port, }, + { NULL, }, +}; + + + +/* The timer/counter register internal state. Note that we store + state using the control register images, in host endian order. */ + +struct tx3904tmr { + address_word base_address; /* control register base */ + unsigned_4 clock_ticks, ext_ticks; /* clock frequencies */ + signed_8 last_ticks; /* time at last deliver_*_tick call */ + signed_8 roundoff_ticks; /* sim ticks unprocessed during last tick call */ + int ff; /* pulse generator flip-flop value: 1/0 */ + struct hw_event* event; /* last scheduled event */ + + unsigned_4 tcr; +#define GET_TCR_TCE(c) (((c)->tcr & 0x80) >> 7) +#define GET_TCR_CCDE(c) (((c)->tcr & 0x40) >> 6) +#define GET_TCR_CRE(c) (((c)->tcr & 0x20) >> 5) +#define GET_TCR_CCS(c) (((c)->tcr & 0x04) >> 2) +#define GET_TCR_TMODE(c) (((c)->tcr & 0x03) >> 0) + unsigned_4 tisr; +#define SET_TISR_TWIS(c) ((c)->tisr |= 0x08) +#define SET_TISR_TPIBS(c) ((c)->tisr |= 0x04) +#define SET_TISR_TPIAS(c) ((c)->tisr |= 0x02) +#define SET_TISR_TIIS(c) ((c)->tisr |= 0x01) + unsigned_4 cpra; + unsigned_4 cprb; + unsigned_4 itmr; +#define GET_ITMR_TIIE(c) (((c)->itmr & 0x8000) >> 15) +#define SET_ITMR_TIIE(c,v) BLIT32((c)->itmr, 15, (v) ? 1 : 0) +#define GET_ITMR_TZCE(c) (((c)->itmr & 0x0001) >> 0) +#define SET_ITMR_TZCE(c,v) BLIT32((c)->itmr, 0, (v) ? 1 : 0) + unsigned_4 ccdr; +#define GET_CCDR_CDR(c) (((c)->ccdr & 0x07) >> 0) + unsigned_4 pmgr; +#define GET_PMGR_TPIBE(c) (((c)->pmgr & 0x8000) >> 15) +#define SET_PMGR_TPIBE(c,v) BLIT32((c)->pmgr, 15, (v) ? 1 : 0) +#define GET_PMGR_TPIAE(c) (((c)->pmgr & 0x4000) >> 14) +#define SET_PMGR_TPIAE(c,v) BLIT32((c)->pmgr, 14, (v) ? 1 : 0) +#define GET_PMGR_FFI(c) (((c)->pmgr & 0x0001) >> 0) +#define SET_PMGR_FFI(c,v) BLIT32((c)->pmgr, 0, (v) ? 1 : 0) + unsigned_4 wtmr; +#define GET_WTMR_TWIE(c) (((c)->wtmr & 0x8000) >> 15) +#define SET_WTMR_TWIE(c,v) BLIT32((c)->wtmr, 15, (v) ? 1 : 0) +#define GET_WTMR_WDIS(c) (((c)->wtmr & 0x0080) >> 7) +#define SET_WTMR_WDIS(c,v) BLIT32((c)->wtmr, 7, (v) ? 1 : 0) +#define GET_WTMR_TWC(c) (((c)->wtmr & 0x0001) >> 0) +#define SET_WTMR_TWC(c,v) BLIT32((c)->wtmr, 0, (v) ? 1 : 0) + unsigned_4 trr; +}; + + + +/* Finish off the partially created hw device. Attach our local + callbacks. Wire up our port names etc */ + +static hw_io_read_buffer_method tx3904tmr_io_read_buffer; +static hw_io_write_buffer_method tx3904tmr_io_write_buffer; +static hw_port_event_method tx3904tmr_port_event; + +static void +attach_tx3904tmr_regs (struct hw *me, + struct tx3904tmr *controller) +{ + unsigned_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain one addr/size entry"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, + &attach_address, + me); + hw_unit_size_to_attach_size (hw_parent (me), + ®.size, + &attach_size, me); + + hw_attach_address (hw_parent (me), 0, + attach_space, attach_address, attach_size, + me); + + if(hw_find_property(me, "clock") != NULL) + controller->clock_ticks = (unsigned_4) hw_find_integer_property(me, "clock"); + + if(hw_find_property(me, "ext") != NULL) + controller->ext_ticks = (unsigned_4) hw_find_integer_property(me, "ext"); + + controller->base_address = attach_address; +} + + +static void +tx3904tmr_finish (struct hw *me) +{ + struct tx3904tmr *controller; + + controller = HW_ZALLOC (me, struct tx3904tmr); + set_hw_data (me, controller); + set_hw_io_read_buffer (me, tx3904tmr_io_read_buffer); + set_hw_io_write_buffer (me, tx3904tmr_io_write_buffer); + set_hw_ports (me, tx3904tmr_ports); + set_hw_port_event (me, tx3904tmr_port_event); + + /* Preset clock dividers */ + controller->clock_ticks = 1; + controller->ext_ticks = 100; + + /* Attach ourself to our parent bus */ + attach_tx3904tmr_regs (me, controller); + + /* Initialize to reset state */ + controller->tcr = + controller->itmr = + controller->ccdr = + controller->pmgr = + controller->wtmr = + controller->tisr = + controller->trr = 0; + controller->cpra = controller->cprb = 0x00FFFFFF; + controller->ff = 0; + controller->last_ticks = controller->roundoff_ticks = 0; + controller->event = NULL; +} + + + +/* An event arrives on an interrupt port */ + +static void +tx3904tmr_port_event (struct hw *me, + int my_port, + struct hw *source, + int source_port, + int level) +{ + struct tx3904tmr *controller = hw_data (me); + + switch (my_port) + { + case RESET_PORT: + { + HW_TRACE ((me, "reset")); + + /* preset flip-flop to FFI value */ + controller->ff = GET_PMGR_FFI(controller); + + controller->tcr = + controller->itmr = + controller->ccdr = + controller->pmgr = + controller->wtmr = + controller->tisr = + controller->trr = 0; + controller->cpra = controller->cprb = 0x00FFFFFF; + controller->last_ticks = controller->roundoff_ticks = 0; + if(controller->event != NULL) + hw_event_queue_deschedule(me, controller->event); + controller->event = NULL; + break; + } + + default: + hw_abort (me, "Event on unknown port %d", my_port); + break; + } +} + + +/* generic read/write */ + +static unsigned +tx3904tmr_io_read_buffer (struct hw *me, + void *dest, + int space, + unsigned_word base, + unsigned nr_bytes) +{ + struct tx3904tmr *controller = hw_data (me); + unsigned byte; + + HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes)); + for (byte = 0; byte < nr_bytes; byte++) + { + address_word address = base + byte; + int reg_number = (address - controller->base_address) / 4; + int reg_offset = 3 - (address - controller->base_address) % 4; + unsigned_4 register_value; /* in target byte order */ + + /* fill in entire register_value word */ + switch (reg_number) + { + case TCR_REG: register_value = controller->tcr; break; + case TISR_REG: register_value = controller->tisr; break; + case CPRA_REG: register_value = controller->cpra; break; + case CPRB_REG: register_value = controller->cprb; break; + case ITMR_REG: register_value = controller->itmr; break; + case CCDR_REG: register_value = controller->ccdr; break; + case PMGR_REG: register_value = controller->pmgr; break; + case WTMR_REG: register_value = controller->wtmr; break; + case TRR_REG: register_value = controller->trr; break; + default: register_value = 0; + } + + /* write requested byte out */ + memcpy ((char*) dest + byte, ((char*)& register_value)+reg_offset, 1); + } + + return nr_bytes; +} + + + +static unsigned +tx3904tmr_io_write_buffer (struct hw *me, + const void *source, + int space, + unsigned_word base, + unsigned nr_bytes) +{ + struct tx3904tmr *controller = hw_data (me); + unsigned byte; + + HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes)); + for (byte = 0; byte < nr_bytes; byte++) + { + address_word address = base + byte; + unsigned_1 write_byte = ((const char*) source)[byte]; + int reg_number = (address - controller->base_address) / 4; + int reg_offset = 3 - (address - controller->base_address) % 4; + + /* fill in entire register_value word */ + switch (reg_number) + { + case TCR_REG: + if(reg_offset == 0) /* first byte */ + { + /* update register, but mask out NOP bits */ + controller->tcr = (unsigned_4) (write_byte & 0xef); + + /* Reset counter value if timer suspended and CRE is set. */ + if(GET_TCR_TCE(controller) == 0 && + GET_TCR_CRE(controller) == 1) + controller->trr = 0; + } + /* HW_TRACE ((me, "tcr: %08lx", (long) controller->tcr)); */ + break; + + case ITMR_REG: + if(reg_offset == 1) /* second byte */ + { + SET_ITMR_TIIE(controller, write_byte & 0x80); + } + else if(reg_offset == 0) /* first byte */ + { + SET_ITMR_TZCE(controller, write_byte & 0x01); + } + /* HW_TRACE ((me, "itmr: %08lx", (long) controller->itmr)); */ + break; + + case CCDR_REG: + if(reg_offset == 0) /* first byte */ + { + controller->ccdr = write_byte & 0x07; + } + /* HW_TRACE ((me, "ccdr: %08lx", (long) controller->ccdr)); */ + break; + + case PMGR_REG: + if(reg_offset == 1) /* second byte */ + { + SET_PMGR_TPIBE(controller, write_byte & 0x80); + SET_PMGR_TPIAE(controller, write_byte & 0x40); + } + else if(reg_offset == 0) /* first byte */ + { + SET_PMGR_FFI(controller, write_byte & 0x01); + } + /* HW_TRACE ((me, "pmgr: %08lx", (long) controller->pmgr)); */ + break; + + case WTMR_REG: + if(reg_offset == 1) /* second byte */ + { + SET_WTMR_TWIE(controller, write_byte & 0x80); + } + else if(reg_offset == 0) /* first byte */ + { + SET_WTMR_WDIS(controller, write_byte & 0x80); + SET_WTMR_TWC(controller, write_byte & 0x01); + } + /* HW_TRACE ((me, "wtmr: %08lx", (long) controller->wtmr)); */ + break; + + case TISR_REG: + if(reg_offset == 0) /* first byte */ + { + /* All bits must be zero in given byte, according to + spec. */ + + /* Send an "interrupt off" event on the interrupt port */ + if(controller->tisr != 0) /* any interrupts active? */ + { + hw_port_event(me, INT_PORT, 0); + } + + /* clear interrupt status register */ + controller->tisr = 0; + } + /* HW_TRACE ((me, "tisr: %08lx", (long) controller->tisr)); */ + break; + + case CPRA_REG: + if(reg_offset < 3) /* first, second, or third byte */ + { + MBLIT32(controller->cpra, (reg_offset*8)+7, (reg_offset*8), write_byte); + } + /* HW_TRACE ((me, "cpra: %08lx", (long) controller->cpra)); */ + break; + + case CPRB_REG: + if(reg_offset < 3) /* first, second, or third byte */ + { + MBLIT32(controller->cprb, (reg_offset*8)+7, (reg_offset*8), write_byte); + } + /* HW_TRACE ((me, "cprb: %08lx", (long) controller->cprb)); */ + break; + + default: + HW_TRACE ((me, "write to illegal register %d", reg_number)); + } + } /* loop over bytes */ + + /* Schedule a timer event in near future, so we can increment or + stop the counter, to respond to register updates. */ + hw_event_queue_schedule(me, 1, deliver_tx3904tmr_tick, NULL); + + return nr_bytes; +} + + + +/* Deliver a clock tick to the counter. */ +static void +deliver_tx3904tmr_tick (struct hw *me, + void *data) +{ + struct tx3904tmr *controller = hw_data (me); + SIM_DESC sd = hw_system (me); + signed_8 this_ticks = sim_events_time(sd); + + signed_8 warp; + signed_8 divisor; + signed_8 quotient, remainder; + + /* compute simulation ticks between last tick and this tick */ + if(controller->last_ticks != 0) + warp = this_ticks - controller->last_ticks + controller->roundoff_ticks; + else + { + controller->last_ticks = this_ticks; /* initialize */ + warp = controller->roundoff_ticks; + } + + if(controller->event != NULL) + hw_event_queue_deschedule(me, controller->event); + controller->event = NULL; + + /* Check whether the timer ticking is enabled at this moment. This + largely a function of the TCE bit, but is also slightly + mode-dependent. */ + switch((int) GET_TCR_TMODE(controller)) + { + case 0: /* interval */ + /* do not advance counter if TCE = 0 or if holding at count = CPRA */ + if(GET_TCR_TCE(controller) == 0 || + controller->trr == controller->cpra) + return; + break; + + case 1: /* pulse generator */ + /* do not advance counter if TCE = 0 */ + if(GET_TCR_TCE(controller) == 0) + return; + break; + + case 2: /* watchdog */ + /* do not advance counter if TCE = 0 and WDIS = 1 */ + if(GET_TCR_TCE(controller) == 0 && + GET_WTMR_WDIS(controller) == 1) + return; + break; + + case 3: /* disabled */ + /* regardless of TCE, do not advance counter */ + return; + } + + /* In any of the above cases that return, a subsequent register + write will be needed to restart the timer. A tick event is + scheduled by any register write, so it is more efficient not to + reschedule dummy events here. */ + + + /* find appropriate divisor etc. */ + if(GET_TCR_CCS(controller) == 0) /* internal system clock */ + { + /* apply internal clock divider */ + if(GET_TCR_CCDE(controller)) /* divisor circuit enabled? */ + divisor = controller->clock_ticks * (1 << (1 + GET_CCDR_CDR(controller))); + else + divisor = controller->clock_ticks; + } + else + { + divisor = controller->ext_ticks; + } + + /* how many times to increase counter? */ + quotient = warp / divisor; + remainder = warp % divisor; + + /* NOTE: If the event rescheduling code works properly, the quotient + should never be larger than 1. That is, we should receive events + here at least as frequently as the simulated counter is supposed + to decrement. So the remainder (-> roundoff_ticks) will slowly + accumulate, with the quotient == 0. Once in a while, quotient + will equal 1. */ + + controller->roundoff_ticks = remainder; + controller->last_ticks = this_ticks; + while(quotient > 0) /* Is it time to increment counter? */ + { + /* next 24-bit counter value */ + unsigned_4 next_trr = (controller->trr + 1) % (1 << 24); + quotient --; + + switch((int) GET_TCR_TMODE(controller)) + { + case 0: /* interval timer mode */ + { + /* Current or next counter value matches CPRA value? The + first case covers counter holding at maximum before + reset. The second case covers normal counting + behavior. */ + if(controller->trr == controller->cpra || + next_trr == controller->cpra) + { + /* likely hold CPRA value */ + if(controller->trr == controller->cpra) + next_trr = controller->cpra; + + SET_TISR_TIIS(controller); + + /* Signal an interrupt if it is enabled with TIIE, + and if we just arrived at CPRA. Don't repeatedly + interrupt if holding due to TZCE=0 */ + if(GET_ITMR_TIIE(controller) && + next_trr != controller->trr) + { + hw_port_event(me, INT_PORT, 1); + } + + /* Reset counter? */ + if(GET_ITMR_TZCE(controller)) + { + next_trr = 0; + } + } + } + break; + + case 1: /* pulse generator mode */ + { + /* first trip point */ + if(next_trr == controller->cpra) + { + /* flip flip-flop & report */ + controller->ff ^= 1; + hw_port_event(me, FF_PORT, controller->ff); + SET_TISR_TPIAS(controller); + + /* signal interrupt */ + if(GET_PMGR_TPIAE(controller)) + { + hw_port_event(me, INT_PORT, 1); + } + + } + /* second trip point */ + else if(next_trr == controller->cprb) + { + /* flip flip-flop & report */ + controller->ff ^= 1; + hw_port_event(me, FF_PORT, controller->ff); + SET_TISR_TPIBS(controller); + + /* signal interrupt */ + if(GET_PMGR_TPIBE(controller)) + { + hw_port_event(me, INT_PORT, 1); + } + + /* clear counter */ + next_trr = 0; + } + } + break; + + case 2: /* watchdog timer mode */ + { + /* watchdog timer expiry */ + if(next_trr == controller->cpra) + { + SET_TISR_TWIS(controller); + + /* signal interrupt */ + if(GET_WTMR_TWIE(controller)) + { + hw_port_event(me, INT_PORT, 1); + } + + /* clear counter */ + next_trr = 0; + } + } + break; + + case 3: /* disabled */ + default: + break; + } + + /* update counter and report */ + controller->trr = next_trr; + /* HW_TRACE ((me, "counter trr %ld tisr %lx", + (long) controller->trr, (long) controller->tisr)); */ + } /* end quotient loop */ + + /* Reschedule a timer event in near future, so we can increment the + counter again. Set the event about 75% of divisor time away, so + we will experience roughly 1.3 events per counter increment. */ + controller->event = hw_event_queue_schedule(me, divisor*3/4, deliver_tx3904tmr_tick, NULL); +} + + + + +const struct hw_descriptor dv_tx3904tmr_descriptor[] = { + { "tx3904tmr", tx3904tmr_finish, }, + { NULL }, +};
dv-tx3904tmr.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: mdmx.igen =================================================================== --- mdmx.igen (nonexistent) +++ mdmx.igen (revision 33) @@ -0,0 +1,592 @@ +// -*- C -*- + +// Simulator definition for the MIPS MDMX ASE. +// Copyright (C) 2002 Free Software Foundation, Inc. +// Contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom +// Corporation (SiByte). +// +// This file is part of GDB, the GNU debugger. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// Reference: MIPS64 Architecture Volume IV-b: +// The MDMX Application-Specific Extension + +// Notes on "format selectors" (FMTSEL): +// +// A selector with final bit 0 indicates OB format. +// A selector with final bits 01 indicates QH format. +// A selector with final bits 11 has UNPREDICTABLE result per the spec. +// +// Similarly, for the single-bit fields which differentiate between +// formats (FMTOP), 0 is OB format and 1 is QH format. + +// If you change this file to add instructions, please make sure that model +// "sb1" configurations still build, and that you've added no new +// instructions to the "sb1" model. + + +// Helper: +// +// Check whether MDMX is usable, and if not signal an appropriate exception. +// + +:function:::void:check_mdmx:instruction_word insn +*mdmx: +{ + if (! COP_Usable (1)) + SignalExceptionCoProcessorUnusable (1); + if ((SR & (status_MX|status_FR)) != (status_MX|status_FR)) + SignalExceptionMDMX (); + check_u64 (SD_, insn); +} + + +// Helper: +// +// Check whether a given MDMX format selector indicates a valid and usable +// format, and if not signal an appropriate exception. +// + +:function:::int:check_mdmx_fmtsel:instruction_word insn, int fmtsel +*mdmx: +{ + switch (fmtsel & 0x03) + { + case 0x00: /* ob */ + case 0x02: + case 0x01: /* qh */ + return 1; + case 0x03: /* UNPREDICTABLE */ + SignalException (ReservedInstruction, insn); + return 0; + } + return 0; +} + + +// Helper: +// +// Check whether a given MDMX format bit indicates a valid and usable +// format, and if not signal an appropriate exception. +// + +:function:::int:check_mdmx_fmtop:instruction_word insn, int fmtop +*mdmx: +{ + switch (fmtop & 0x01) + { + case 0x00: /* ob */ + case 0x01: /* qh */ + return 1; + } + return 0; +} + + +:%s::::FMTSEL:int fmtsel +*mdmx: +*sb1: +{ + if ((fmtsel & 0x1) == 0) + return "ob"; + else if ((fmtsel & 0x3) == 1) + return "qh"; + else + return "?"; +} + + +:%s::::FMTOP:int fmtop +*mdmx: +*sb1: +{ + switch (fmtop) + { + case 0: return "ob"; + case 1: return "qh"; + default: return "?"; + } +} + + +:%s::::SHOP:int shop +*mdmx: +*sb1: +{ + if ((shop & 0x11) == 0x00) + switch ((shop >> 1) & 0x07) + { + case 3: return "upsl.ob"; + case 4: return "pach.ob"; + case 6: return "mixh.ob"; + case 7: return "mixl.ob"; + default: return "?"; + } + else if ((shop & 0x03) == 0x01) + switch ((shop >> 2) & 0x07) + { + case 0: return "mixh.qh"; + case 1: return "mixl.qh"; + case 2: return "pach.qh"; + case 4: return "bfla.qh"; + case 6: return "repa.qh"; + case 7: return "repb.qh"; + default: return "?"; + } + else + return "?"; +} + + +011110,5.FMTSEL,5.VT,5.VS,5.VD,001011:MDMX:64::ADD.fmt +"add.%s v, v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + StoreFPR(VD,fmt_mdmx,MX_Add(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); +} + + +011110,5.FMTSEL,5.VT,5.VS,0,0000,110111:MDMX:64::ADDA.fmt +"adda.%s v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + MX_AddA(ValueFPR(VS,fmt_mdmx),VT,FMTSEL); +} + + +011110,5.FMTSEL,5.VT,5.VS,1,0000,110111:MDMX:64::ADDL.fmt +"addl.%s v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + MX_AddL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL); +} + + +011110,00,3.IMM,5.VT,5.VS,5.VD,0110,1.FMTOP,0:MDMX:64::ALNI.fmt +"alni.%s v, v, v, " +*mdmx: +*sb1: +{ + unsigned64 result; + int s; + check_mdmx (SD_, instruction_0); + check_mdmx_fmtop (SD_, instruction_0, FMTOP); + s = (IMM << 3); + result = ValueFPR(VS,fmt_mdmx) << s; + if (s != 0) // x86 gcc treats >> 64 as >> 0 + result |= ValueFPR(VT,fmt_mdmx) >> (64 - s); + StoreFPR(VD,fmt_mdmx,result); +} + + +011110,5.RS,5.VT,5.VS,5.VD,0110,1.FMTOP,1:MDMX:64::ALNV.fmt +"alnv.%s v, v, v, r" +*mdmx: +*sb1: +{ + unsigned64 result; + int s; + check_mdmx (SD_, instruction_0); + check_mdmx_fmtop (SD_, instruction_0, FMTOP); + s = ((GPR[RS] & 0x7) << 3); + result = ValueFPR(VS,fmt_mdmx) << s; + if (s != 0) // x86 gcc treats >> 64 as >> 0 + result |= ValueFPR(VT,fmt_mdmx) >> (64 - s); + StoreFPR(VD,fmt_mdmx,result); +} + + +011110,5.FMTSEL,5.VT,5.VS,5.VD,001100:MDMX:64::AND.fmt +"and.%s v, v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + StoreFPR(VD,fmt_mdmx,MX_And(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); +} + + +011110,5.FMTSEL,5.VT,5.VS,00000,000001:MDMX:64::C.EQ.fmt +"c.eq.%s v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + MX_Comp(ValueFPR(VS,fmt_mdmx),MX_C_EQ,VT,FMTSEL); +} + + +011110,5.FMTSEL,5.VT,5.VS,00000,000101:MDMX:64::C.LE.fmt +"c.le.%s v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + MX_Comp(ValueFPR(VS,fmt_mdmx),MX_C_LT|MX_C_EQ,VT,FMTSEL); +} + + +011110,5.FMTSEL,5.VT,5.VS,00000,000100:MDMX:64::C.LT.fmt +"c.lt.%s v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + MX_Comp(ValueFPR(VS,fmt_mdmx),MX_C_LT,VT,FMTSEL); +} + + +011110,5.FMTSEL,5.VT,5.VS,5.VD,000111:MDMX:64::MAX.fmt +"max.%s v, v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + StoreFPR(VD,fmt_mdmx,MX_Max(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); +} + + +011110,5.FMTSEL,5.VT,5.VS,5.VD,000110:MDMX:64::MIN.fmt +"min.%s v, v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + StoreFPR(VD,fmt_mdmx,MX_Min(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); +} + + +011110,3.SEL,01,5.VT,5.VS,5.VD,000000:MDMX:64::MSGN.QH +"msgn.qh v, v, v" +*mdmx: +{ + check_mdmx (SD_, instruction_0); + StoreFPR(VD,fmt_mdmx,MX_Msgn(ValueFPR(VS,fmt_mdmx),VT,qh_fmtsel(SEL))); +} + + +011110,5.FMTSEL,5.VT,5.VS,5.VD,110000:MDMX:64::MUL.fmt +"mul.%s v, v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + StoreFPR(VD,fmt_mdmx,MX_Mul(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); +} + + +011110,5.FMTSEL,5.VT,5.VS,0,0000,110011:MDMX:64::MULA.fmt +"mula.%s v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + MX_MulA(ValueFPR(VS,fmt_mdmx),VT,FMTSEL); +} + + +011110,5.FMTSEL,5.VT,5.VS,1,0000,110011:MDMX:64::MULL.fmt +"mull.%s v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + MX_MulL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL); +} + + +011110,5.FMTSEL,5.VT,5.VS,0,0000,110010:MDMX:64::MULS.fmt +"muls.%s v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + MX_MulS(ValueFPR(VS,fmt_mdmx),VT,FMTSEL); +} + + +011110,5.FMTSEL,5.VT,5.VS,1,0000,110010:MDMX:64::MULSL.fmt +"mulsl.%s v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + MX_MulSL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL); +} + + +011110,5.FMTSEL,5.VT,5.VS,5.VD,001111:MDMX:64::NOR.fmt +"nor.%s v, v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + StoreFPR(VD,fmt_mdmx,MX_Nor(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); +} + + +011110,5.FMTSEL,5.VT,5.VS,5.VD,001110:MDMX:64::OR.fmt +"or.%s v, v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + StoreFPR(VD,fmt_mdmx,MX_Or(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); +} + + +011110,5.FMTSEL,5.VT,5.VS,5.VD,000010:MDMX:64::PICKF.fmt +"pickf.%s v, v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + StoreFPR(VD,fmt_mdmx,MX_Pick(0,ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); +} + + +011110,5.FMTSEL,5.VT,5.VS,5.VD,000011:MDMX:64::PICKT.fmt +"pickt.%s v, v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + StoreFPR(VD,fmt_mdmx,MX_Pick(1,ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); +} + + +011110,1000,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACH.fmt +"rach.%s v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + check_mdmx_fmtop (SD_, instruction_0, FMTOP); + StoreFPR(VD,fmt_mdmx,MX_RAC(MX_RAC_H,FMTOP)); +} + + +011110,0000,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACL.fmt +"racl.%s v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + check_mdmx_fmtop (SD_, instruction_0, FMTOP); + StoreFPR(VD,fmt_mdmx,MX_RAC(MX_RAC_L,FMTOP)); +} + + +011110,0100,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACM.fmt +"racm.%s v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + check_mdmx_fmtop (SD_, instruction_0, FMTOP); + StoreFPR(VD,fmt_mdmx,MX_RAC(MX_RAC_M,FMTOP)); +} + + +011110,3.SEL,01,5.VT,00000,5.VD,100101:MDMX:64::RNAS.QH +"rnas.qh v, v" +*mdmx: +{ + check_mdmx (SD_, instruction_0); + StoreFPR(VD,fmt_mdmx,MX_RNAS(VT,qh_fmtsel(SEL))); +} + + +011110,5.FMTSEL,5.VT,00000,5.VD,100001:MDMX:64::RNAU.fmt +"rnau.%s v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + StoreFPR(VD,fmt_mdmx,MX_RNAU(VT,FMTSEL)); +} + + +011110,3.SEL,01,5.VT,00000,5.VD,100110:MDMX:64::RNES.QH +"rnes.qh v, v" +*mdmx: +{ + check_mdmx (SD_, instruction_0); + StoreFPR(VD,fmt_mdmx,MX_RNES(VT,qh_fmtsel(SEL))); +} + + +011110,5.FMTSEL,5.VT,00000,5.VD,100010:MDMX:64::RNEU.fmt +"rneu.%s v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + StoreFPR(VD,fmt_mdmx,MX_RNEU(VT,FMTSEL)); +} + + +011110,3.SEL,01,5.VT,00000,5.VD,100100:MDMX:64::RZS.QH +"rzs.qh v, v" +*mdmx: +{ + check_mdmx (SD_, instruction_0); + StoreFPR(VD,fmt_mdmx,MX_RZS(VT,qh_fmtsel(SEL))); +} + + +011110,5.FMTSEL,5.VT,00000,5.VD,100000:MDMX:64::RZU.fmt +"rzu.%s v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + StoreFPR(VD,fmt_mdmx,MX_RZU(VT,FMTSEL)); +} + + +011110,5.SHOP,5.VT,5.VS,5.VD,011111:MDMX:64::SHFL.op.fmt +"shfl.%s v, v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, SHOP)) + StoreFPR(VD,fmt_mdmx,MX_SHFL(SHOP,ValueFPR(VS,fmt_mdmx),ValueFPR(VT,fmt_mdmx))); +} + + +011110,5.FMTSEL,5.VT,5.VS,5.VD,010000:MDMX:64::SLL.fmt +"sll.%s v, v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + StoreFPR(VD,fmt_mdmx,MX_ShiftLeftLogical(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); +} + + +011110,3.SEL,01,5.VT,5.VS,5.VD,010011:MDMX:64::SRA.QH +"sra.qh v, v, v" +*mdmx: +{ + check_mdmx (SD_, instruction_0); + StoreFPR(VD,fmt_mdmx,MX_ShiftRightArith(ValueFPR(VS,fmt_mdmx),VT,qh_fmtsel(SEL))); +} + + +011110,5.FMTSEL,5.VT,5.VS,5.VD,010010:MDMX:64::SRL.fmt +"srl.%s v, v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + StoreFPR(VD,fmt_mdmx,MX_ShiftRightLogical(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); +} + + +011110,5.FMTSEL,5.VT,5.VS,5.VD,001010:MDMX:64::SUB.fmt +"sub.%s v, v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + StoreFPR(VD,fmt_mdmx,MX_Sub(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); +} + + +011110,5.FMTSEL,5.VT,5.VS,0,0000,110110:MDMX:64::SUBA.fmt +"suba.%s v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + MX_SubA(ValueFPR(VS,fmt_mdmx),VT,FMTSEL); +} + + +011110,5.FMTSEL,5.VT,5.VS,1,0000,110110:MDMX:64::SUBL.fmt +"subl.%s v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + MX_SubL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL); +} + + +011110,1000,1.FMTOP,00000,5.VS,00000,111110:MDMX:64::WACH.fmt +"wach.%s v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + check_mdmx_fmtop (SD_, instruction_0, FMTOP); + MX_WACH(FMTOP,ValueFPR(VS,fmt_mdmx)); +} + + +011110,0000,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WACL.fmt +"wacl.%s v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + check_mdmx_fmtop (SD_, instruction_0, FMTOP); + MX_WACL(FMTOP,ValueFPR(VS,fmt_mdmx),ValueFPR(VT,fmt_mdmx)); +} + + +011110,5.FMTSEL,5.VT,5.VS,5.VD,001101:MDMX:64::XOR.fmt +"xor.%s v, v, v" +*mdmx: +*sb1: +{ + check_mdmx (SD_, instruction_0); + if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL)) + StoreFPR(VD,fmt_mdmx,MX_Xor(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); +} Index: mdmx.c =================================================================== --- mdmx.c (nonexistent) +++ mdmx.c (revision 33) @@ -0,0 +1,1476 @@ +/* Simulation code for the MIPS MDMX ASE. + Copyright (C) 2002, 2007, 2008 Free Software Foundation, Inc. + Contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom + Corporation (SiByte). + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +#include + +#include "sim-main.h" + +/* Within mdmx.c we refer to the sim_cpu directly. */ +#define CPU cpu +#define SD (CPU_STATE(CPU)) + +/* XXX FIXME: temporary hack while the impact of making unpredictable() + a "normal" (non-igen) function is evaluated. */ +#undef Unpredictable +#define Unpredictable() unpredictable_action (cpu, cia) + +/* MDMX Representations + + An 8-bit packed byte element (OB) is always unsigned. + The 24-bit accumulators are signed and are represented as 32-bit + signed values, which are reduced to 24-bit signed values prior to + Round and Clamp operations. + + A 16-bit packed halfword element (QH) is always signed. + The 48-bit accumulators are signed and are represented as 64-bit + signed values, which are reduced to 48-bit signed values prior to + Round and Clamp operations. + + The code below assumes a 2's-complement representation of signed + quantities. Care is required to clear extended sign bits when + repacking fields. + + The code (and the code for arithmetic shifts in mips.igen) also makes + the (not guaranteed portable) assumption that right shifts of signed + quantities in C do sign extension. */ + +typedef unsigned64 unsigned48; +#define MASK48 (UNSIGNED64 (0xffffffffffff)) + +typedef unsigned32 unsigned24; +#define MASK24 (UNSIGNED32 (0xffffff)) + +typedef enum { + mdmx_ob, /* OB (octal byte) */ + mdmx_qh /* QH (quad half-word) */ +} MX_fmt; + +typedef enum { + sel_elem, /* element select */ + sel_vect, /* vector select */ + sel_imm /* immediate select */ +} VT_select; + +#define OB_MAX ((unsigned8)0xFF) +#define QH_MIN ((signed16)0x8000) +#define QH_MAX ((signed16)0x7FFF) + +#define OB_CLAMP(x) ((unsigned8)((x) > OB_MAX ? OB_MAX : (x))) +#define QH_CLAMP(x) ((signed16)((x) < QH_MIN ? QH_MIN : \ + ((x) > QH_MAX ? QH_MAX : (x)))) + +#define MX_FMT(fmtsel) (((fmtsel) & 0x1) == 0 ? mdmx_ob : mdmx_qh) +#define MX_VT(fmtsel) (((fmtsel) & 0x10) == 0 ? sel_elem : \ + (((fmtsel) & 0x18) == 0x10 ? sel_vect : sel_imm)) + +#define QH_ELEM(v,fmtsel) \ + ((signed16)(((v) >> (((fmtsel) & 0xC) << 2)) & 0xFFFF)) +#define OB_ELEM(v,fmtsel) \ + ((unsigned8)(((v) >> (((fmtsel) & 0xE) << 2)) & 0xFF)) + + +typedef signed16 (*QH_FUNC)(signed16, signed16); +typedef unsigned8 (*OB_FUNC)(unsigned8, unsigned8); + +/* vectorized logical operators */ + +static signed16 +AndQH(signed16 ts, signed16 tt) +{ + return (signed16)((unsigned16)ts & (unsigned16)tt); +} + +static unsigned8 +AndOB(unsigned8 ts, unsigned8 tt) +{ + return ts & tt; +} + +static signed16 +NorQH(signed16 ts, signed16 tt) +{ + return (signed16)(((unsigned16)ts | (unsigned16)tt) ^ 0xFFFF); +} + +static unsigned8 +NorOB(unsigned8 ts, unsigned8 tt) +{ + return (ts | tt) ^ 0xFF; +} + +static signed16 +OrQH(signed16 ts, signed16 tt) +{ + return (signed16)((unsigned16)ts | (unsigned16)tt); +} + +static unsigned8 +OrOB(unsigned8 ts, unsigned8 tt) +{ + return ts | tt; +} + +static signed16 +XorQH(signed16 ts, signed16 tt) +{ + return (signed16)((unsigned16)ts ^ (unsigned16)tt); +} + +static unsigned8 +XorOB(unsigned8 ts, unsigned8 tt) +{ + return ts ^ tt; +} + +static signed16 +SLLQH(signed16 ts, signed16 tt) +{ + unsigned32 s = (unsigned32)tt & 0xF; + return (signed16)(((unsigned32)ts << s) & 0xFFFF); +} + +static unsigned8 +SLLOB(unsigned8 ts, unsigned8 tt) +{ + unsigned32 s = tt & 0x7; + return (ts << s) & 0xFF; +} + +static signed16 +SRLQH(signed16 ts, signed16 tt) +{ + unsigned32 s = (unsigned32)tt & 0xF; + return (signed16)((unsigned16)ts >> s); +} + +static unsigned8 +SRLOB(unsigned8 ts, unsigned8 tt) +{ + unsigned32 s = tt & 0x7; + return ts >> s; +} + + +/* Vectorized arithmetic operators. */ + +static signed16 +AddQH(signed16 ts, signed16 tt) +{ + signed32 t = (signed32)ts + (signed32)tt; + return QH_CLAMP(t); +} + +static unsigned8 +AddOB(unsigned8 ts, unsigned8 tt) +{ + unsigned32 t = (unsigned32)ts + (unsigned32)tt; + return OB_CLAMP(t); +} + +static signed16 +SubQH(signed16 ts, signed16 tt) +{ + signed32 t = (signed32)ts - (signed32)tt; + return QH_CLAMP(t); +} + +static unsigned8 +SubOB(unsigned8 ts, unsigned8 tt) +{ + signed32 t; + t = (signed32)ts - (signed32)tt; + if (t < 0) + t = 0; + return (unsigned8)t; +} + +static signed16 +MinQH(signed16 ts, signed16 tt) +{ + return (ts < tt ? ts : tt); +} + +static unsigned8 +MinOB(unsigned8 ts, unsigned8 tt) +{ + return (ts < tt ? ts : tt); +} + +static signed16 +MaxQH(signed16 ts, signed16 tt) +{ + return (ts > tt ? ts : tt); +} + +static unsigned8 +MaxOB(unsigned8 ts, unsigned8 tt) +{ + return (ts > tt ? ts : tt); +} + +static signed16 +MulQH(signed16 ts, signed16 tt) +{ + signed32 t = (signed32)ts * (signed32)tt; + return QH_CLAMP(t); +} + +static unsigned8 +MulOB(unsigned8 ts, unsigned8 tt) +{ + unsigned32 t = (unsigned32)ts * (unsigned32)tt; + return OB_CLAMP(t); +} + +/* "msgn" and "sra" are defined only for QH format. */ + +static signed16 +MsgnQH(signed16 ts, signed16 tt) +{ + signed16 t; + if (ts < 0) + t = (tt == QH_MIN ? QH_MAX : -tt); + else if (ts == 0) + t = 0; + else + t = tt; + return t; +} + +static signed16 +SRAQH(signed16 ts, signed16 tt) +{ + unsigned32 s = (unsigned32)tt & 0xF; + return (signed16)((signed32)ts >> s); +} + + +/* "pabsdiff" and "pavg" are defined only for OB format. */ + +static unsigned8 +AbsDiffOB(unsigned8 ts, unsigned8 tt) +{ + return (ts >= tt ? ts - tt : tt - ts); +} + +static unsigned8 +AvgOB(unsigned8 ts, unsigned8 tt) +{ + return ((unsigned32)ts + (unsigned32)tt + 1) >> 1; +} + + +/* Dispatch tables for operations that update a CPR. */ + +static const QH_FUNC qh_func[] = { + AndQH, NorQH, OrQH, XorQH, SLLQH, SRLQH, + AddQH, SubQH, MinQH, MaxQH, + MulQH, MsgnQH, SRAQH, NULL, NULL +}; + +static const OB_FUNC ob_func[] = { + AndOB, NorOB, OrOB, XorOB, SLLOB, SRLOB, + AddOB, SubOB, MinOB, MaxOB, + MulOB, NULL, NULL, AbsDiffOB, AvgOB +}; + +/* Auxiliary functions for CPR updates. */ + +/* Vector mapping for QH format. */ +static unsigned64 +qh_vector_op(unsigned64 v1, unsigned64 v2, QH_FUNC func) +{ + unsigned64 result = 0; + int i; + signed16 h, h1, h2; + + for (i = 0; i < 64; i += 16) + { + h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16; + h2 = (signed16)(v2 & 0xFFFF); v2 >>= 16; + h = (*func)(h1, h2); + result |= ((unsigned64)((unsigned16)h) << i); + } + return result; +} + +static unsigned64 +qh_map_op(unsigned64 v1, signed16 h2, QH_FUNC func) +{ + unsigned64 result = 0; + int i; + signed16 h, h1; + + for (i = 0; i < 64; i += 16) + { + h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16; + h = (*func)(h1, h2); + result |= ((unsigned64)((unsigned16)h) << i); + } + return result; +} + + +/* Vector operations for OB format. */ + +static unsigned64 +ob_vector_op(unsigned64 v1, unsigned64 v2, OB_FUNC func) +{ + unsigned64 result = 0; + int i; + unsigned8 b, b1, b2; + + for (i = 0; i < 64; i += 8) + { + b1 = v1 & 0xFF; v1 >>= 8; + b2 = v2 & 0xFF; v2 >>= 8; + b = (*func)(b1, b2); + result |= ((unsigned64)b << i); + } + return result; +} + +static unsigned64 +ob_map_op(unsigned64 v1, unsigned8 b2, OB_FUNC func) +{ + unsigned64 result = 0; + int i; + unsigned8 b, b1; + + for (i = 0; i < 64; i += 8) + { + b1 = v1 & 0xFF; v1 >>= 8; + b = (*func)(b1, b2); + result |= ((unsigned64)b << i); + } + return result; +} + + +/* Primary entry for operations that update CPRs. */ +unsigned64 +mdmx_cpr_op(sim_cpu *cpu, + address_word cia, + int op, + unsigned64 op1, + int vt, + MX_fmtsel fmtsel) +{ + unsigned64 op2; + unsigned64 result = 0; + + switch (MX_FMT (fmtsel)) + { + case mdmx_qh: + switch (MX_VT (fmtsel)) + { + case sel_elem: + op2 = ValueFPR(vt, fmt_mdmx); + result = qh_map_op(op1, QH_ELEM(op2, fmtsel), qh_func[op]); + break; + case sel_vect: + result = qh_vector_op(op1, ValueFPR(vt, fmt_mdmx), qh_func[op]); + break; + case sel_imm: + result = qh_map_op(op1, vt, qh_func[op]); + break; + } + break; + case mdmx_ob: + switch (MX_VT (fmtsel)) + { + case sel_elem: + op2 = ValueFPR(vt, fmt_mdmx); + result = ob_map_op(op1, OB_ELEM(op2, fmtsel), ob_func[op]); + break; + case sel_vect: + result = ob_vector_op(op1, ValueFPR(vt, fmt_mdmx), ob_func[op]); + break; + case sel_imm: + result = ob_map_op(op1, vt, ob_func[op]); + break; + } + break; + default: + Unpredictable (); + } + + return result; +} + + +/* Operations that update CCs */ + +static void +qh_vector_test(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int cond) +{ + int i; + signed16 h1, h2; + int boolean; + + for (i = 0; i < 4; i++) + { + h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16; + h2 = (signed16)(v2 & 0xFFFF); v2 >>= 16; + boolean = ((cond & MX_C_EQ) && (h1 == h2)) || + ((cond & MX_C_LT) && (h1 < h2)); + SETFCC(i, boolean); + } +} + +static void +qh_map_test(sim_cpu *cpu, unsigned64 v1, signed16 h2, int cond) +{ + int i; + signed16 h1; + int boolean; + + for (i = 0; i < 4; i++) + { + h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16; + boolean = ((cond & MX_C_EQ) && (h1 == h2)) || + ((cond & MX_C_LT) && (h1 < h2)); + SETFCC(i, boolean); + } +} + +static void +ob_vector_test(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int cond) +{ + int i; + unsigned8 b1, b2; + int boolean; + + for (i = 0; i < 8; i++) + { + b1 = v1 & 0xFF; v1 >>= 8; + b2 = v2 & 0xFF; v2 >>= 8; + boolean = ((cond & MX_C_EQ) && (b1 == b2)) || + ((cond & MX_C_LT) && (b1 < b2)); + SETFCC(i, boolean); + } +} + +static void +ob_map_test(sim_cpu *cpu, unsigned64 v1, unsigned8 b2, int cond) +{ + int i; + unsigned8 b1; + int boolean; + + for (i = 0; i < 8; i++) + { + b1 = (unsigned8)(v1 & 0xFF); v1 >>= 8; + boolean = ((cond & MX_C_EQ) && (b1 == b2)) || + ((cond & MX_C_LT) && (b1 < b2)); + SETFCC(i, boolean); + } +} + + +void +mdmx_cc_op(sim_cpu *cpu, + address_word cia, + int cond, + unsigned64 v1, + int vt, + MX_fmtsel fmtsel) +{ + unsigned64 op2; + + switch (MX_FMT (fmtsel)) + { + case mdmx_qh: + switch (MX_VT (fmtsel)) + { + case sel_elem: + op2 = ValueFPR(vt, fmt_mdmx); + qh_map_test(cpu, v1, QH_ELEM(op2, fmtsel), cond); + break; + case sel_vect: + qh_vector_test(cpu, v1, ValueFPR(vt, fmt_mdmx), cond); + break; + case sel_imm: + qh_map_test(cpu, v1, vt, cond); + break; + } + break; + case mdmx_ob: + switch (MX_VT (fmtsel)) + { + case sel_elem: + op2 = ValueFPR(vt, fmt_mdmx); + ob_map_test(cpu, v1, OB_ELEM(op2, fmtsel), cond); + break; + case sel_vect: + ob_vector_test(cpu, v1, ValueFPR(vt, fmt_mdmx), cond); + break; + case sel_imm: + ob_map_test(cpu, v1, vt, cond); + break; + } + break; + default: + Unpredictable (); + } +} + + +/* Pick operations. */ + +static unsigned64 +qh_vector_pick(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int tf) +{ + unsigned64 result = 0; + int i, s; + unsigned16 h; + + s = 0; + for (i = 0; i < 4; i++) + { + h = ((GETFCC(i) == tf) ? (v1 & 0xFFFF) : (v2 & 0xFFFF)); + v1 >>= 16; v2 >>= 16; + result |= ((unsigned64)h << s); + s += 16; + } + return result; +} + +static unsigned64 +qh_map_pick(sim_cpu *cpu, unsigned64 v1, signed16 h2, int tf) +{ + unsigned64 result = 0; + int i, s; + unsigned16 h; + + s = 0; + for (i = 0; i < 4; i++) + { + h = (GETFCC(i) == tf) ? (v1 & 0xFFFF) : (unsigned16)h2; + v1 >>= 16; + result |= ((unsigned64)h << s); + s += 16; + } + return result; +} + +static unsigned64 +ob_vector_pick(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int tf) +{ + unsigned64 result = 0; + int i, s; + unsigned8 b; + + s = 0; + for (i = 0; i < 8; i++) + { + b = (GETFCC(i) == tf) ? (v1 & 0xFF) : (v2 & 0xFF); + v1 >>= 8; v2 >>= 8; + result |= ((unsigned64)b << s); + s += 8; + } + return result; +} + +static unsigned64 +ob_map_pick(sim_cpu *cpu, unsigned64 v1, unsigned8 b2, int tf) +{ + unsigned64 result = 0; + int i, s; + unsigned8 b; + + s = 0; + for (i = 0; i < 8; i++) + { + b = (GETFCC(i) == tf) ? (v1 & 0xFF) : b2; + v1 >>= 8; + result |= ((unsigned64)b << s); + s += 8; + } + return result; +} + + +unsigned64 +mdmx_pick_op(sim_cpu *cpu, + address_word cia, + int tf, + unsigned64 v1, + int vt, + MX_fmtsel fmtsel) +{ + unsigned64 result = 0; + unsigned64 op2; + + switch (MX_FMT (fmtsel)) + { + case mdmx_qh: + switch (MX_VT (fmtsel)) + { + case sel_elem: + op2 = ValueFPR(vt, fmt_mdmx); + result = qh_map_pick(cpu, v1, QH_ELEM(op2, fmtsel), tf); + break; + case sel_vect: + result = qh_vector_pick(cpu, v1, ValueFPR(vt, fmt_mdmx), tf); + break; + case sel_imm: + result = qh_map_pick(cpu, v1, vt, tf); + break; + } + break; + case mdmx_ob: + switch (MX_VT (fmtsel)) + { + case sel_elem: + op2 = ValueFPR(vt, fmt_mdmx); + result = ob_map_pick(cpu, v1, OB_ELEM(op2, fmtsel), tf); + break; + case sel_vect: + result = ob_vector_pick(cpu, v1, ValueFPR(vt, fmt_mdmx), tf); + break; + case sel_imm: + result = ob_map_pick(cpu, v1, vt, tf); + break; + } + break; + default: + Unpredictable (); + } + return result; +} + + +/* Accumulators. */ + +typedef void (*QH_ACC)(signed48 *a, signed16 ts, signed16 tt); + +static void +AccAddAQH(signed48 *a, signed16 ts, signed16 tt) +{ + *a += (signed48)ts + (signed48)tt; +} + +static void +AccAddLQH(signed48 *a, signed16 ts, signed16 tt) +{ + *a = (signed48)ts + (signed48)tt; +} + +static void +AccMulAQH(signed48 *a, signed16 ts, signed16 tt) +{ + *a += (signed48)ts * (signed48)tt; +} + +static void +AccMulLQH(signed48 *a, signed16 ts, signed16 tt) +{ + *a = (signed48)ts * (signed48)tt; +} + +static void +SubMulAQH(signed48 *a, signed16 ts, signed16 tt) +{ + *a -= (signed48)ts * (signed48)tt; +} + +static void +SubMulLQH(signed48 *a, signed16 ts, signed16 tt) +{ + *a = -((signed48)ts * (signed48)tt); +} + +static void +AccSubAQH(signed48 *a, signed16 ts, signed16 tt) +{ + *a += (signed48)ts - (signed48)tt; +} + +static void +AccSubLQH(signed48 *a, signed16 ts, signed16 tt) +{ + *a = (signed48)ts - (signed48)tt; +} + + +typedef void (*OB_ACC)(signed24 *acc, unsigned8 ts, unsigned8 tt); + +static void +AccAddAOB(signed24 *a, unsigned8 ts, unsigned8 tt) +{ + *a += (signed24)ts + (signed24)tt; +} + +static void +AccAddLOB(signed24 *a, unsigned8 ts, unsigned8 tt) +{ + *a = (signed24)ts + (signed24)tt; +} + +static void +AccMulAOB(signed24 *a, unsigned8 ts, unsigned8 tt) +{ + *a += (signed24)ts * (signed24)tt; +} + +static void +AccMulLOB(signed24 *a, unsigned8 ts, unsigned8 tt) +{ + *a = (signed24)ts * (signed24)tt; +} + +static void +SubMulAOB(signed24 *a, unsigned8 ts, unsigned8 tt) +{ + *a -= (signed24)ts * (signed24)tt; +} + +static void +SubMulLOB(signed24 *a, unsigned8 ts, unsigned8 tt) +{ + *a = -((signed24)ts * (signed24)tt); +} + +static void +AccSubAOB(signed24 *a, unsigned8 ts, unsigned8 tt) +{ + *a += (signed24)ts - (signed24)tt; +} + +static void +AccSubLOB(signed24 *a, unsigned8 ts, unsigned8 tt) +{ + *a = (signed24)ts - (signed24)tt; +} + +static void +AccAbsDiffOB(signed24 *a, unsigned8 ts, unsigned8 tt) +{ + unsigned8 t = (ts >= tt ? ts - tt : tt - ts); + *a += (signed24)t; +} + + +/* Dispatch tables for operations that update a CPR. */ + +static const QH_ACC qh_acc[] = { + AccAddAQH, AccAddAQH, AccMulAQH, AccMulLQH, + SubMulAQH, SubMulLQH, AccSubAQH, AccSubLQH, + NULL +}; + +static const OB_ACC ob_acc[] = { + AccAddAOB, AccAddLOB, AccMulAOB, AccMulLOB, + SubMulAOB, SubMulLOB, AccSubAOB, AccSubLOB, + AccAbsDiffOB +}; + + +static void +qh_vector_acc(signed48 a[], unsigned64 v1, unsigned64 v2, QH_ACC acc) +{ + int i; + signed16 h1, h2; + + for (i = 0; i < 4; i++) + { + h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16; + h2 = (signed16)(v2 & 0xFFFF); v2 >>= 16; + (*acc)(&a[i], h1, h2); + } +} + +static void +qh_map_acc(signed48 a[], unsigned64 v1, signed16 h2, QH_ACC acc) +{ + int i; + signed16 h1; + + for (i = 0; i < 4; i++) + { + h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16; + (*acc)(&a[i], h1, h2); + } +} + +static void +ob_vector_acc(signed24 a[], unsigned64 v1, unsigned64 v2, OB_ACC acc) +{ + int i; + unsigned8 b1, b2; + + for (i = 0; i < 8; i++) + { + b1 = v1 & 0xFF; v1 >>= 8; + b2 = v2 & 0xFF; v2 >>= 8; + (*acc)(&a[i], b1, b2); + } +} + +static void +ob_map_acc(signed24 a[], unsigned64 v1, unsigned8 b2, OB_ACC acc) +{ + int i; + unsigned8 b1; + + for (i = 0; i < 8; i++) + { + b1 = v1 & 0xFF; v1 >>= 8; + (*acc)(&a[i], b1, b2); + } +} + + +/* Primary entry for operations that accumulate */ +void +mdmx_acc_op(sim_cpu *cpu, + address_word cia, + int op, + unsigned64 op1, + int vt, + MX_fmtsel fmtsel) +{ + unsigned64 op2; + + switch (MX_FMT (fmtsel)) + { + case mdmx_qh: + switch (MX_VT (fmtsel)) + { + case sel_elem: + op2 = ValueFPR(vt, fmt_mdmx); + qh_map_acc(ACC.qh, op1, QH_ELEM(op2, fmtsel), qh_acc[op]); + break; + case sel_vect: + qh_vector_acc(ACC.qh, op1, ValueFPR(vt, fmt_mdmx), qh_acc[op]); + break; + case sel_imm: + qh_map_acc(ACC.qh, op1, vt, qh_acc[op]); + break; + } + break; + case mdmx_ob: + switch (MX_VT (fmtsel)) + { + case sel_elem: + op2 = ValueFPR(vt, fmt_mdmx); + ob_map_acc(ACC.ob, op1, OB_ELEM(op2, fmtsel), ob_acc[op]); + break; + case sel_vect: + ob_vector_acc(ACC.ob, op1, ValueFPR(vt, fmt_mdmx), ob_acc[op]); + break; + case sel_imm: + ob_map_acc(ACC.ob, op1, vt, ob_acc[op]); + break; + } + break; + default: + Unpredictable (); + } +} + + +/* Reading and writing accumulator (no conversion). */ + +unsigned64 +mdmx_rac_op(sim_cpu *cpu, + address_word cia, + int op, + int fmt) +{ + unsigned64 result; + unsigned int shift; + int i; + + shift = op; /* L = 00, M = 01, H = 10. */ + result = 0; + + switch (fmt) + { + case MX_FMT_QH: + shift <<= 4; /* 16 bits per element. */ + for (i = 3; i >= 0; --i) + { + result <<= 16; + result |= ((ACC.qh[i] >> shift) & 0xFFFF); + } + break; + case MX_FMT_OB: + shift <<= 3; /* 8 bits per element. */ + for (i = 7; i >= 0; --i) + { + result <<= 8; + result |= ((ACC.ob[i] >> shift) & 0xFF); + } + break; + default: + Unpredictable (); + } + return result; +} + +void +mdmx_wacl(sim_cpu *cpu, + address_word cia, + int fmt, + unsigned64 vs, + unsigned64 vt) +{ + int i; + + switch (fmt) + { + case MX_FMT_QH: + for (i = 0; i < 4; i++) + { + signed32 s = (signed16)(vs & 0xFFFF); + ACC.qh[i] = ((signed48)s << 16) | (vt & 0xFFFF); + vs >>= 16; vt >>= 16; + } + break; + case MX_FMT_OB: + for (i = 0; i < 8; i++) + { + signed16 s = (signed8)(vs & 0xFF); + ACC.ob[i] = ((signed24)s << 8) | (vt & 0xFF); + vs >>= 8; vt >>= 8; + } + break; + default: + Unpredictable (); + } +} + +void +mdmx_wach(sim_cpu *cpu, + address_word cia, + int fmt, + unsigned64 vs) +{ + int i; + + switch (fmt) + { + case MX_FMT_QH: + for (i = 0; i < 4; i++) + { + signed32 s = (signed16)(vs & 0xFFFF); + ACC.qh[i] &= ~((signed48)0xFFFF << 32); + ACC.qh[i] |= ((signed48)s << 32); + vs >>= 16; + } + break; + case MX_FMT_OB: + for (i = 0; i < 8; i++) + { + ACC.ob[i] &= ~((signed24)0xFF << 16); + ACC.ob[i] |= ((signed24)(vs & 0xFF) << 16); + vs >>= 8; + } + break; + default: + Unpredictable (); + } +} + + +/* Reading and writing accumulator (rounding conversions). + Enumerating function guarantees s >= 0 for QH ops. */ + +typedef signed16 (*QH_ROUND)(signed48 a, signed16 s); + +#define QH_BIT(n) ((unsigned48)1 << (n)) +#define QH_ONES(n) (((unsigned48)1 << (n))-1) + +static signed16 +RNASQH(signed48 a, signed16 s) +{ + signed48 t; + signed16 result = 0; + + if (s > 48) + result = 0; + else + { + t = (a >> s); + if ((a & QH_BIT(47)) == 0) + { + if (s > 0 && ((a >> (s-1)) & 1) == 1) + t++; + if (t > QH_MAX) + t = QH_MAX; + } + else + { + if (s > 0 && ((a >> (s-1)) & 1) == 1) + { + if (s > 1 && ((unsigned48)a & QH_ONES(s-1)) != 0) + t++; + } + if (t < QH_MIN) + t = QH_MIN; + } + result = (signed16)t; + } + return result; +} + +static signed16 +RNAUQH(signed48 a, signed16 s) +{ + unsigned48 t; + signed16 result; + + if (s > 48) + result = 0; + else if (s == 48) + result = ((unsigned48)a & MASK48) >> 47; + else + { + t = ((unsigned48)a & MASK48) >> s; + if (s > 0 && ((a >> (s-1)) & 1) == 1) + t++; + if (t > 0xFFFF) + t = 0xFFFF; + result = (signed16)t; + } + return result; +} + +static signed16 +RNESQH(signed48 a, signed16 s) +{ + signed48 t; + signed16 result = 0; + + if (s > 47) + result = 0; + else + { + t = (a >> s); + if (s > 0 && ((a >> (s-1)) & 1) == 1) + { + if (s == 1 || (a & QH_ONES(s-1)) == 0) + t += t & 1; + else + t += 1; + } + if ((a & QH_BIT(47)) == 0) + { + if (t > QH_MAX) + t = QH_MAX; + } + else + { + if (t < QH_MIN) + t = QH_MIN; + } + result = (signed16)t; + } + return result; +} + +static signed16 +RNEUQH(signed48 a, signed16 s) +{ + unsigned48 t; + signed16 result; + + if (s > 48) + result = 0; + else if (s == 48) + result = ((unsigned48)a > QH_BIT(47) ? 1 : 0); + else + { + t = ((unsigned48)a & MASK48) >> s; + if (s > 0 && ((a >> (s-1)) & 1) == 1) + { + if (s > 1 && (a & QH_ONES(s-1)) != 0) + t++; + else + t += t & 1; + } + if (t > 0xFFFF) + t = 0xFFFF; + result = (signed16)t; + } + return result; +} + +static signed16 +RZSQH(signed48 a, signed16 s) +{ + signed48 t; + signed16 result = 0; + + if (s > 47) + result = 0; + else + { + t = (a >> s); + if ((a & QH_BIT(47)) == 0) + { + if (t > QH_MAX) + t = QH_MAX; + } + else + { + if (t < QH_MIN) + t = QH_MIN; + } + result = (signed16)t; + } + return result; +} + +static signed16 +RZUQH(signed48 a, signed16 s) +{ + unsigned48 t; + signed16 result = 0; + + if (s > 48) + result = 0; + else if (s == 48) + result = ((unsigned48)a > QH_BIT(47) ? 1 : 0); + else + { + t = ((unsigned48)a & MASK48) >> s; + if (t > 0xFFFF) + t = 0xFFFF; + result = (signed16)t; + } + return result; +} + + +typedef unsigned8 (*OB_ROUND)(signed24 a, unsigned8 s); + +#define OB_BIT(n) ((unsigned24)1 << (n)) +#define OB_ONES(n) (((unsigned24)1 << (n))-1) + +static unsigned8 +RNAUOB(signed24 a, unsigned8 s) +{ + unsigned8 result; + unsigned24 t; + + if (s > 24) + result = 0; + else if (s == 24) + result = ((unsigned24)a & MASK24) >> 23; + else + { + t = ((unsigned24)a & MASK24) >> s; + if (s > 0 && ((a >> (s-1)) & 1) == 1) + t ++; + result = OB_CLAMP(t); + } + return result; +} + +static unsigned8 +RNEUOB(signed24 a, unsigned8 s) +{ + unsigned8 result; + unsigned24 t; + + if (s > 24) + result = 0; + else if (s == 24) + result = (((unsigned24)a & MASK24) > OB_BIT(23) ? 1 : 0); + else + { + t = ((unsigned24)a & MASK24) >> s; + if (s > 0 && ((a >> (s-1)) & 1) == 1) + { + if (s > 1 && (a & OB_ONES(s-1)) != 0) + t++; + else + t += t & 1; + } + result = OB_CLAMP(t); + } + return result; +} + +static unsigned8 +RZUOB(signed24 a, unsigned8 s) +{ + unsigned8 result; + unsigned24 t; + + if (s >= 24) + result = 0; + else + { + t = ((unsigned24)a & MASK24) >> s; + result = OB_CLAMP(t); + } + return result; +} + + +static const QH_ROUND qh_round[] = { + RNASQH, RNAUQH, RNESQH, RNEUQH, RZSQH, RZUQH +}; + +static const OB_ROUND ob_round[] = { + NULL, RNAUOB, NULL, RNEUOB, NULL, RZUOB +}; + + +static unsigned64 +qh_vector_round(sim_cpu *cpu, address_word cia, unsigned64 v2, QH_ROUND round) +{ + unsigned64 result = 0; + int i, s; + signed16 h, h2; + + s = 0; + for (i = 0; i < 4; i++) + { + h2 = (signed16)(v2 & 0xFFFF); + if (h2 >= 0) + h = (*round)(ACC.qh[i], h2); + else + { + UnpredictableResult (); + h = 0xdead; + } + v2 >>= 16; + result |= ((unsigned64)((unsigned16)h) << s); + s += 16; + } + return result; +} + +static unsigned64 +qh_map_round(sim_cpu *cpu, address_word cia, signed16 h2, QH_ROUND round) +{ + unsigned64 result = 0; + int i, s; + signed16 h; + + s = 0; + for (i = 0; i < 4; i++) + { + if (h2 >= 0) + h = (*round)(ACC.qh[i], h2); + else + { + UnpredictableResult (); + h = 0xdead; + } + result |= ((unsigned64)((unsigned16)h) << s); + s += 16; + } + return result; +} + +static unsigned64 +ob_vector_round(sim_cpu *cpu, address_word cia, unsigned64 v2, OB_ROUND round) +{ + unsigned64 result = 0; + int i, s; + unsigned8 b, b2; + + s = 0; + for (i = 0; i < 8; i++) + { + b2 = v2 & 0xFF; v2 >>= 8; + b = (*round)(ACC.ob[i], b2); + result |= ((unsigned64)b << s); + s += 8; + } + return result; +} + +static unsigned64 +ob_map_round(sim_cpu *cpu, address_word cia, unsigned8 b2, OB_ROUND round) +{ + unsigned64 result = 0; + int i, s; + unsigned8 b; + + s = 0; + for (i = 0; i < 8; i++) + { + b = (*round)(ACC.ob[i], b2); + result |= ((unsigned64)b << s); + s += 8; + } + return result; +} + + +unsigned64 +mdmx_round_op(sim_cpu *cpu, + address_word cia, + int rm, + int vt, + MX_fmtsel fmtsel) +{ + unsigned64 op2; + unsigned64 result = 0; + + switch (MX_FMT (fmtsel)) + { + case mdmx_qh: + switch (MX_VT (fmtsel)) + { + case sel_elem: + op2 = ValueFPR(vt, fmt_mdmx); + result = qh_map_round(cpu, cia, QH_ELEM(op2, fmtsel), qh_round[rm]); + break; + case sel_vect: + op2 = ValueFPR(vt, fmt_mdmx); + result = qh_vector_round(cpu, cia, op2, qh_round[rm]); + break; + case sel_imm: + result = qh_map_round(cpu, cia, vt, qh_round[rm]); + break; + } + break; + case mdmx_ob: + switch (MX_VT (fmtsel)) + { + case sel_elem: + op2 = ValueFPR(vt, fmt_mdmx); + result = ob_map_round(cpu, cia, OB_ELEM(op2, fmtsel), ob_round[rm]); + break; + case sel_vect: + op2 = ValueFPR(vt, fmt_mdmx); + result = ob_vector_round(cpu, cia, op2, ob_round[rm]); + break; + case sel_imm: + result = ob_map_round(cpu, cia, vt, ob_round[rm]); + break; + } + break; + default: + Unpredictable (); + } + + return result; +} + + +/* Shuffle operation. */ + +typedef struct { + enum {vs, ss, vt} source; + unsigned int index; +} sh_map; + +static const sh_map ob_shuffle[][8] = { + /* MDMX 2.0 encodings (3-4, 6-7). */ + /* vr5400 encoding (5), otherwise. */ + { }, /* RSVD */ + {{vt,4}, {vs,4}, {vt,5}, {vs,5}, {vt,6}, {vs,6}, {vt,7}, {vs,7}}, /* RSVD */ + {{vt,0}, {vs,0}, {vt,1}, {vs,1}, {vt,2}, {vs,2}, {vt,3}, {vs,3}}, /* RSVD */ + {{vs,0}, {ss,0}, {vs,1}, {ss,1}, {vs,2}, {ss,2}, {vs,3}, {ss,3}}, /* upsl */ + {{vt,1}, {vt,3}, {vt,5}, {vt,7}, {vs,1}, {vs,3}, {vs,5}, {vs,7}}, /* pach */ + {{vt,0}, {vt,2}, {vt,4}, {vt,6}, {vs,0}, {vs,2}, {vs,4}, {vs,6}}, /* pacl */ + {{vt,4}, {vs,4}, {vt,5}, {vs,5}, {vt,6}, {vs,6}, {vt,7}, {vs,7}}, /* mixh */ + {{vt,0}, {vs,0}, {vt,1}, {vs,1}, {vt,2}, {vs,2}, {vt,3}, {vs,3}} /* mixl */ +}; + +static const sh_map qh_shuffle[][4] = { + {{vt,2}, {vs,2}, {vt,3}, {vs,3}}, /* mixh */ + {{vt,0}, {vs,0}, {vt,1}, {vs,1}}, /* mixl */ + {{vt,1}, {vt,3}, {vs,1}, {vs,3}}, /* pach */ + { }, /* RSVD */ + {{vt,1}, {vs,0}, {vt,3}, {vs,2}}, /* bfla */ + { }, /* RSVD */ + {{vt,2}, {vt,3}, {vs,2}, {vs,3}}, /* repa */ + {{vt,0}, {vt,1}, {vs,0}, {vs,1}} /* repb */ +}; + + +unsigned64 +mdmx_shuffle(sim_cpu *cpu, + address_word cia, + int shop, + unsigned64 op1, + unsigned64 op2) +{ + unsigned64 result = 0; + int i, s; + int op; + + if ((shop & 0x3) == 0x1) /* QH format. */ + { + op = shop >> 2; + s = 0; + for (i = 0; i < 4; i++) + { + unsigned64 v; + + switch (qh_shuffle[op][i].source) + { + case vs: + v = op1; + break; + case vt: + v = op2; + break; + default: + Unpredictable (); + v = 0; + } + result |= (((v >> 16*qh_shuffle[op][i].index) & 0xFFFF) << s); + s += 16; + } + } + else if ((shop & 0x1) == 0x0) /* OB format. */ + { + op = shop >> 1; + s = 0; + for (i = 0; i < 8; i++) + { + unsigned8 b; + unsigned int ishift = 8*ob_shuffle[op][i].index; + + switch (ob_shuffle[op][i].source) + { + case vs: + b = (op1 >> ishift) & 0xFF; + break; + case ss: + b = ((op1 >> ishift) & 0x80) ? 0xFF : 0; + break; + case vt: + b = (op2 >> ishift) & 0xFF; + break; + default: + Unpredictable (); + b = 0; + } + result |= ((unsigned64)b << s); + s += 8; + } + } + else + Unpredictable (); + + return result; +}
mdmx.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: ChangeLog =================================================================== --- ChangeLog (nonexistent) +++ ChangeLog (revision 33) @@ -0,0 +1,3242 @@ +2007-10-22 Richard Sandiford + + * mips.igen (check_fmt_p): Provide a separate mips32r2 definition + that unconditionally allows fmt_ps. + (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU) + (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt) + (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change + filter from 64,f to 32,f. + (PREFX): Change filter from 64 to 32. + (LDXC1, LUXC1): Provide separate mips32r2 implementations + that use do_load_double instead of do_load. Make both LUXC1 + versions unpredictable if SizeFGR () != 64. + (SDXC1, SUXC1): Extend to mips32r2, using do_store_double + instead of do_store. Remove unused variable. Make both SUXC1 + versions unpredictable if SizeFGR () != 64. + +2007-10-07 Richard Sandiford + + * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32. + (sc, swxc1): Likewise. Also fix big-endian and reverse-endian + shifts for that case. + +2007-09-04 Nick Clifton + + * interp.c (options enum): Add OPTION_INFO_MEMORY. + (display_mem_info): New static variable. + (mips_option_handler): Handle OPTION_INFO_MEMORY. + (mips_options): Add info-memory and memory-info. + (sim_open): After processing the command line and board + specification, check display_mem_info. If it is set then + call the real handler for the --memory-info command line + switch. + +2007-08-24 Joel Brobecker + + * configure.ac: Change license of multi-run.c to GPL version 3. + * configure: Regenerate. + +2007-06-28 Richard Sandiford + + * configure.ac, configure: Revert last patch. + +2007-06-26 Richard Sandiford + + * configure.ac (sim_mipsisa3264_configs): New variable. + (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make + every configuration support all four targets, using the triplet to + determine the default. + * configure: Regenerate. + +2007-06-25 Richard Sandiford + + * Makefile.in (m16run.o): New rule. + +2007-05-15 Thiemo Seufer + + * mips3264r2.igen (DSHD): Fix compile warning. + +2007-05-14 Thiemo Seufer + + * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, + CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt, + NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS, + RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support + for mips32r2. + +2007-03-01 Thiemo Seufer + + * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32 + and mips64. + +2007-02-20 Thiemo Seufer + + * dsp.igen: Update copyright notice. + * dsp2.igen: Fix copyright notice. + +2007-02-20 Thiemo Seufer + Chao-Ying Fu + + * Makefile.in (IGEN_INCLUDE): Add dsp2.igen. + * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*): + Add dsp2 to sim_igen_machine. + * configure: Regenerate. + * dsp.igen (do_ph_op): Add MUL support when op = 2. + (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph. + (mulq_rs.ph): Use do_ph_mulq. + (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen. + * mips.igen: Add dsp2 model and include dsp2.igen. + (MFHI, MFLO, MTHI, MTLO): Extend these instructions for + for *mips32r2, *mips64r2, *dsp. + (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions + for *mips32r2, *mips64r2, *dsp2. + * dsp2.igen: New file for MIPS DSP REV 2 ASE. + +2007-02-19 Thiemo Seufer + Nigel Stephens + + * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2 + jumps with hazard barrier. + +2007-02-19 Thiemo Seufer + Nigel Stephens + + * interp.c (sim_monitor): Flush stdout and stderr file descriptors + after each call to sim_io_write. + +2007-02-19 Thiemo Seufer + Nigel Stephens + + * interp.c (ColdReset): Set CP0 Config0 to reflect the address size + supported by this simulator. + (decode_coproc): Recognise additional CP0 Config registers + correctly. + +2007-02-19 Thiemo Seufer + Nigel Stephens + David Ung + + * cp1.c (value_fpr): Don't inherit existing FPR_STATE for + uninterpreted formats. If fmt is one of the uninterpreted types + don't update the FPR_STATE. Handle fmt_uninterpreted_32 like + fmt_word, and fmt_uninterpreted_64 like fmt_long. + (store_fpr): When writing an invalid odd register, set the + matching even register to fmt_unknown, not the following register. + * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to + the the memory window at offset 0 set by --memory-size command + line option. + (sim_store_register): Handle storing 4 bytes to an 8 byte floating + point register. + (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte + register. + (sim_monitor): When returning the memory size to the MIPS + application, use the value in STATE_MEM_SIZE, not an arbitrary + hardcoded value. + (cop_lw): Don' mess around with FPR_STATE, just pass + fmt_uninterpreted_32 to StoreFPR. + (cop_sw): Similarly. + (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted. + (cop_sd): Similarly. + * mips.igen (not_word_value): Single version for mips32, mips64 + and mips16. + +2007-02-19 Thiemo Seufer + Nigel Stephens + + * interp.c (MEM_SIZE): Increase default memory size from 2 to 8 + MBytes. + +2007-02-17 Thiemo Seufer + + * configure.ac (mips*-sde-elf*): Move in front of generic machine + configuration. + * configure: Regenerate. + +2007-02-17 Thiemo Seufer + + * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*): + Add mdmx to sim_igen_machine. + (mipsisa64*-*-*): Likewise. Remove dsp. + (mipsisa32*-*-*): Remove dsp. + * configure: Regenerate. + +2007-02-13 Thiemo Seufer + + * configure.ac: Add mips*-sde-elf* target. + * configure: Regenerate. + +2006-12-21 Hans-Peter Nilsson + + * acconfig.h: Remove. + * config.in, configure: Regenerate. + +2006-11-07 Thiemo Seufer + + * dsp.igen (do_w_op): Fix compiler warning. + +2006-08-29 Thiemo Seufer + David Ung + + * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to + sim_igen_machine. + * configure: Regenerate. + * mips.igen (model): Add smartmips. + (MADDU): Increment ACX if carry. + (do_mult): Clear ACX. + (ROR,RORV): Add smartmips. + (include): Include smartmips.igen. + * sim-main.h (ACX): Set to REGISTERS[89]. + * smartmips.igen: New file. + +2006-08-29 Thiemo Seufer + David Ung + + * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and + mips3264r2.igen. Add missing dependency rules. + * m16e.igen: Support for mips16e save/restore instructions. + +2006-06-13 Richard Earnshaw + + * configure: Regenerated. + +2006-06-05 Daniel Jacobowitz + + * configure: Regenerated. + +2006-05-31 Daniel Jacobowitz + + * configure: Regenerated. + +2006-05-15 Chao-ying Fu + + * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions. + +2006-04-18 Nick Clifton + + * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break + statement. + +2006-03-29 Hans-Peter Nilsson + + * configure: Regenerate. + +2005-12-14 Chao-ying Fu + + * Makefile.in (SIM_OBJS): Add dsp.o. + (dsp.o): New dependency. + (IGEN_INCLUDE): Add dsp.igen. + * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*, + mipsisa64*-*-*): Add dsp to sim_igen_machine. + * configure: Regenerate. + * mips.igen: Add dsp model and include dsp.igen. + (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2, + because these instructions are extended in DSP ASE. + * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of + adding 6 DSP accumulator registers and 1 DSP control register. + (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX, + AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT, + DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK, + DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK, + DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK, + DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK, + DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6, + DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK, + DSPCR_CCOND_SMASK): New define. + (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators. + * dsp.c, dsp.igen: New files for MIPS DSP ASE. + +2005-07-08 Ian Lance Taylor + + * tconfig.in (SIM_QUIET_NAN_NEGATED): Define. + +2005-06-16 David Ung + Nigel Stephens + + * mips.igen: New mips16e model and include m16e.igen. + (check_u64): Add mips16e tag. + * m16e.igen: New file for MIPS16e instructions. + * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*, + mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e + models. + * configure: Regenerate. + +2005-05-26 David Ung + + * mips.igen (mips32r2, mips64r2): New ISA models. Add new model + tags to all instructions which are applicable to the new ISAs. + (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from + vr.igen. + * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific + instructions. + * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move + to mips.igen. + * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets. + * configure: Regenerate. + +2005-03-23 Mark Kettenis + + * configure: Regenerate. + +2005-01-14 Andrew Cagney + + * configure.ac: Sinclude aclocal.m4 before common.m4. Add + explicit call to AC_CONFIG_HEADER. + * configure: Regenerate. + +2005-01-12 Andrew Cagney + + * configure.ac: Update to use ../common/common.m4. + * configure: Re-generate. + +2005-01-11 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +2005-01-07 Andrew Cagney + + * configure.ac: Rename configure.in, require autoconf 2.59. + * configure: Re-generate. + +2004-12-08 Hans-Peter Nilsson + + * configure: Regenerate for ../common/aclocal.m4 update. + +2004-09-24 Monika Chaddha + + Committed by Andrew Cagney. + * m16.igen (CMP, CMPI): Fix assembler. + +2004-08-18 Chris Demetriou + + * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine. + * configure: Regenerate. + +2004-06-25 Chris Demetriou + + * configure.in (sim_m16_machine): Include mipsIII. + * configure: Regenerate. + +2004-05-11 Maciej W. Rozycki + + * mips/interp.c (decode_coproc): Sign-extend the address retrieved + from COP0_BADVADDR. + * mips/sim-main.h (COP0_BADVADDR): Remove a cast. + +2004-04-10 Chris Demetriou + + * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New. + +2004-04-09 Chris Demetriou + + * mips.igen (check_fmt): Remove. + (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W) + (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt) + (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt) + (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt) + (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt) + (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats. + (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt) + (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt) + (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt. + (C.cnd.fmta): Remove incorrect call to check_fmt_p. + +2004-04-09 Chris Demetriou + + * sb1.igen (check_sbx): New function. + (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx. + +2004-03-29 Chris Demetriou + Richard Sandiford + + * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD) + (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New. + * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide + separate implementations for mipsIV and mipsV. Use new macros to + determine whether the restrictions apply. + +2004-01-19 Chris Demetriou + + * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo) + (check_mult_hilo): Improve comments. + (check_div_hilo): Likewise. Also, fork off a new version + to handle mips32/mips64 (since there are no hazards to check + in MIPS32/MIPS64). + +2003-06-17 Richard Sandiford + + * mips.igen (do_dmultx): Fix check for negative operands. + +2003-05-16 Ian Lance Taylor + + * Makefile.in (SHELL): Make sure this is defined. + (various): Use $(SHELL) whenever we invoke move-if-change. + +2003-05-03 Chris Demetriou + + * cp1.c: Tweak attribution slightly. + * cp1.h: Likewise. + * mdmx.c: Likewise. + * mdmx.igen: Likewise. + * mips3d.igen: Likewise. + * sb1.igen: Likewise. + +2003-04-15 Richard Sandiford + + * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of + unsigned operands. + +2003-02-27 Andrew Cagney + + * interp.c (sim_open): Rename _bfd to bfd. + (sim_create_inferior): Ditto. + +2003-01-14 Chris Demetriou + + * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64. + +2003-01-14 Chris Demetriou + + * mips.igen (EI, DI): Remove. + +2003-01-05 Richard Sandiford + + * Makefile.in (tmp-run-multi): Fix mips16 filter. + +2003-01-04 Richard Sandiford + Andrew Cagney + Gavin Romig-Koch + Graydon Hoare + Aldy Hernandez + Dave Brolley + Chris Demetriou + + * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1. + (sim_mach_default): New variable. + (mips64vr-*-*, mips64vrel-*-*): New configurations. + Add a new simulator generator, MULTI. + * configure: Regenerate. + * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables. + (multi-run.o): New dependency. + (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables. + (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules. + (tmp-multi): Combine them. + (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi. + (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI. + (distclean-extra): New rule. + * sim-main.h: Include bfd.h. + (MIPS_MACH): New macro. + * mips.igen (vr4120, vr5400, vr5500): New models. + (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500. + * vr.igen: Replace with new version. + +2003-01-04 Chris Demetriou + + * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1). + * configure: Regenerate. + +2002-12-31 Chris Demetriou + + * sim-main.h (check_branch_bug, mark_branch_bug): Remove. + * mips.igen: Remove all invocations of check_branch_bug and + mark_branch_bug. + +2002-12-16 Chris Demetriou + + * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h". + +2002-07-30 Chris Demetriou + + * mips.igen (do_load_double, do_store_double): New functions. + (LDC1, SDC1): Rename to... + (LDC1b, SDC1b): respectively. + (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support. + +2002-07-29 Michael Snyder + + * cp1.c (fp_recip2): Modify initialization expression so that + GCC will recognize it as constant. + +2002-06-18 Chris Demetriou + + * mdmx.c (SD_): Delete. + (Unpredictable): Re-define, for now, to directly invoke + unpredictable_action(). + (mdmx_acc_op): Fix error in .ob immediate handling. + +2002-06-18 Andrew Cagney + + * interp.c (sim_firmware_command): Initialize `address'. + +2002-06-16 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +2002-06-14 Chris Demetriou + Ed Satterthwaite + + * mips3d.igen: New file which contains MIPS-3D ASE instructions. + * Makefile.in (IGEN_INCLUDE): Add mips3d.igen. + * mips.igen: Include mips3d.igen. + (mips3d): New model name for MIPS-3D ASE instructions. + (CVT.W.fmt): Don't use this instruction for word (source) format + instructions. + * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32) + (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32) + (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions. + (NR_FRAC_GUARD, IMPLICIT_1): New macros. + * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2) + (RSquareRoot1, RSquareRoot2): New macros. + (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1) + (fp_rsqrt2): New functions. + * configure.in: Add MIPS-3D support to mipsisa64 simulator. + * configure: Regenerate. + +2002-06-13 Chris Demetriou + Ed Satterthwaite + + * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros. + (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac) + (fp_inv_sqrt, fpu_format_name): Add paired-single support. + (convert): Note that this function is not used for paired-single + format conversions. + (ps_lower, ps_upper, pack_ps, convert_ps): New functions. + * mips.igen (FMT, MOVtf.fmt): Add paired-single support. + (check_fmt_p): Enable paired-single support. + (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS) + (PUU.PS): New instructions. + (CVT.S.fmt): Don't use this instruction for paired-single format + destinations. + * sim-main.h (FP_formats): New value 'fmt_ps.' + (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes. + (PSLower, PSUpper, PackPS, ConvertPS): New macros. + +2002-06-12 Chris Demetriou + + * mips.igen: Fix formatting of function calls in + many FP operations. + +2002-06-12 Chris Demetriou + + * mips.igen (MOVN, MOVZ): Trace result. + (TNEI): Print "tnei" as the opcode name in traces. + (CEIL.W): Add disassembly string for traces. + (RSQRT.fmt): Make location of disassembly string consistent + with other instructions. + +2002-06-12 Chris Demetriou + + * mips.igen (X): Delete unused function. + +2002-06-08 Andrew Cagney + + * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h". + +2002-06-07 Chris Demetriou + Ed Satterthwaite + + * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt) + (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions. + * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd) + (fp_nmsub): New prototypes. + (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd) + (NegMultiplySub): New defines. + * mips.igen (RSQRT.fmt): Use RSquareRoot(). + (MADD.D, MADD.S): Replace with... + (MADD.fmt): New instruction. + (MSUB.D, MSUB.S): Replace with... + (MSUB.fmt): New instruction. + (NMADD.D, NMADD.S): Replace with... + (NMADD.fmt): New instruction. + (NMSUB.D, MSUB.S): Replace with... + (NMSUB.fmt): New instruction. + +2002-06-07 Chris Demetriou + Ed Satterthwaite + + * cp1.c: Fix more comment spelling and formatting. + (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value. + (denorm_mode): New function. + (fpu_unary, fpu_binary): Round results after operation, collect + status from rounding operations, and update the FCSR. + (convert): Collect status from integer conversions and rounding + operations, and update the FCSR. Adjust NaN values that result + from conversions. Convert to use sim_io_eprintf rather than + fprintf, and remove some debugging code. + * cp1.h (fenr_FS): New define. + +2002-06-07 Chris Demetriou + + * cp1.c (convert): Remove unusable debugging code, and move MIPS + rounding mode to sim FP rounding mode flag conversion code into... + (rounding_mode): New function. + +2002-06-07 Chris Demetriou + + * cp1.c: Clean up formatting of a few comments. + (value_fpr): Reformat switch statement. + +2002-06-06 Chris Demetriou + Ed Satterthwaite + + * cp1.h: New file. + * sim-main.h: Include cp1.h. + (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE) + (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF) + (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h. + (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove. + (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes. + (ValueFCR, StoreFCR, TestFCSR, Compare): New macros. + * cp1.c: Don't include sim-fpu.h; already included by + sim-main.h. Clean up formatting of some comments. + (NaN, Equal, Less): Remove. + (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test) + (fp_cmp): New functions. + * mips.igen (do_c_cond_fmt): Remove. + (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with + Compare. Add result tracing. + (CxC1): Remove, replace with... + (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions. + (DMxC1): Remove, replace with... + (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions. + (MxC1): Remove, replace with... + (MFC1a, MFC1b, MTC1a, MTC1b): New instructions. + +2002-06-04 Chris Demetriou + + * sim-main.h (FGRIDX): Remove, replace all uses with... + (FGR_BASE): New macro. + (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros. + (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member. + (NR_FGR, FGR): Likewise. + * interp.c: Replace all uses of FGRIDX with FGR_BASE. + * mips.igen: Likewise. + +2002-06-04 Chris Demetriou + + * cp1.c: Add an FSF Copyright notice to this file. + +2002-06-04 Chris Demetriou + Ed Satterthwaite + + * cp1.c (Infinity): Remove. + * sim-main.h (Infinity): Likewise. + + * cp1.c (fp_unary, fp_binary): New functions. + (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip) + (fp_sqrt): New functions, implemented in terms of the above. + (AbsoluteValue, Negate, Add, Sub, Multiply, Divide) + (Recip, SquareRoot): Remove (replaced by functions above). + * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div) + (fp_recip, fp_sqrt): New prototypes. + (AbsoluteValue, Negate, Add, Sub, Multiply, Divide) + (Recip, SquareRoot): Replace prototypes with #defines which + invoke the functions above. + +2002-06-03 Chris Demetriou + + * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate) + (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in + file, remove PARAMS from prototypes. + (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide + simulator state arguments. + (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to + pass simulator state arguments. + * cp1.c (SD): Redefine as CPU_STATE(cpu). + (store_fpr, convert): Remove 'sd' argument. + (value_fpr): Likewise. Convert to use 'SD' instead. + +2002-06-03 Chris Demetriou + + * cp1.c (Min, Max): Remove #if 0'd functions. + * sim-main.h (Min, Max): Remove. + +2002-06-03 Chris Demetriou + + * cp1.c: fix formatting of switch case and default labels. + * interp.c: Likewise. + * sim-main.c: Likewise. + +2002-06-03 Chris Demetriou + + * cp1.c: Clean up comments which describe FP formats. + (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64. + +2002-06-03 Chris Demetriou + Ed Satterthwaite + + * configure.in (mipsisa64sb1*-*-*): New target for supporting + Broadcom SiByte SB-1 processor configurations. + * configure: Regenerate. + * sb1.igen: New file. + * mips.igen: Include sb1.igen. + (sb1): New model. + * Makefile.in (IGEN_INCLUDE): Add sb1.igen. + * mdmx.igen: Add "sb1" model to all appropriate functions and + instructions. + * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions. + (ob_func, ob_acc): Reference the above. + (qh_acc): Adjust to keep the same size as ob_acc. + * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff) + (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros. + +2002-06-03 Chris Demetriou + + * Makefile.in (IGEN_INCLUDE): Add mdmx.igen. + +2002-06-02 Chris Demetriou + Ed Satterthwaite + + * mips.igen (mdmx): New (pseudo-)model. + * mdmx.c, mdmx.igen: New files. + * Makefile.in (SIM_OBJS): Add mdmx.o. + * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48): + New typedefs. + (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp) + (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA) + (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC) + (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS) + (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES) + (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical) + (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL) + (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND) + (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA) + (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR) + (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB) + (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor) + (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel) + (qh_fmtsel): New macros. + (_sim_cpu): New member "acc". + (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op) + (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions. + +2002-05-01 Chris Demetriou + + * interp.c: Use 'deprecated' rather than 'depreciated.' + * sim-main.h: Likewise. + +2002-05-01 Chris Demetriou + + * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult + which wouldn't compile anyway. + * sim-main.h (unpredictable_action): New function prototype. + (Unpredictable): Define to call igen function unpredictable(). + (NotWordValue): New macro to call igen function not_word_value(). + (UndefinedResult): Remove. + * interp.c (undefined_result): Remove. + (unpredictable_action): New function. + * mips.igen (not_word_value, unpredictable): New functions. + (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL) + (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu) + (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke + NotWordValue() to check for unpredictable inputs, then + Unpredictable() to handle them. + +2002-02-24 Chris Demetriou + + * mips.igen: Fix formatting of calls to Unpredictable(). + +2002-04-20 Andrew Cagney + + * interp.c (sim_open): Revert previous change. + +2002-04-18 Alexandre Oliva + + * interp.c (sim_open): Disable chunk of code that wrote code in + vector table entries. + +2002-03-19 Chris Demetriou + + * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f) + (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove + unused definitions. + +2002-03-19 Chris Demetriou + + * cp1.c: Fix many formatting issues. + +2002-03-19 Chris G. Demetriou + + * cp1.c (fpu_format_name): New function to replace... + (DOFMT): This. Delete, and update all callers. + (fpu_rounding_mode_name): New function to replace... + (RMMODE): This. Delete, and update all callers. + +2002-03-19 Chris G. Demetriou + + * interp.c: Move FPU support routines from here to... + * cp1.c: Here. New file. + * Makefile.in (SIM_OBJS): Add cp1.o to object list. + (cp1.o): New target. + +2002-03-12 Chris Demetriou + + * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets. + * mips.igen (mips32, mips64): New models, add to all instructions + and functions as appropriate. + (loadstore_ea, check_u64): New variant for model mips64. + (check_fmt_p): New variant for models mipsV and mips64, remove + mipsV model marking fro other variant. + (SLL) Rename to... + (SLLa) this. + (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions + for mips32 and mips64. + (DCLO, DCLZ): New instructions for mips64. + +2002-03-07 Chris Demetriou + + * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print + immediate or code as a hex value with the "%#lx" format. + (ANDI): Likewise, and fix printed instruction name. + +2002-03-05 Chris Demetriou + + * sim-main.h (UndefinedResult, Unpredictable): New macros + which currently do nothing. + +2002-03-05 Chris Demetriou + + * sim-main.h (status_UX, status_SX, status_KX, status_TS) + (status_PX, status_MX, status_CU0, status_CU1, status_CU2) + (status_CU3): New definitions. + + * sim-main.h (ExceptionCause): Add new values for MIPS32 + and MIPS64: MDMX, MCheck, CacheErr. Update comments + for DebugBreakPoint and NMIReset to note their status in + MIPS32 and MIPS64. + (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck) + (SignalExceptionCacheErr): New exception macros. + +2002-03-05 Chris Demetriou + + * mips.igen (check_fpu): Enable check for coprocessor 1 usability. + * sim-main.h (COP_Usable): Define, but for now coprocessor 1 + is always enabled. + (SignalExceptionCoProcessorUnusable): Take as argument the + unusable coprocessor number. + +2002-03-05 Chris Demetriou + + * mips.igen: Fix formatting of all SignalException calls. + +2002-03-05 Chris Demetriou + + * sim-main.h (SIGNEXTEND): Remove. + +2002-03-04 Chris Demetriou + + * mips.igen: Remove gencode comment from top of file, fix + spelling in another comment. + +2002-03-04 Chris Demetriou + + * mips.igen (check_fmt, check_fmt_p): New functions to check + whether specific floating point formats are usable. + (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt) + (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt) + (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W): + Use the new functions. + (do_c_cond_fmt): Remove format checks... + (C.cond.fmta, C.cond.fmtb): And move them into all callers. + +2002-03-03 Chris Demetriou + + * mips.igen: Fix formatting of check_fpu calls. + +2002-03-03 Chris Demetriou + + * mips.igen (FLOOR.L.fmt): Store correct destination register. + +2002-03-03 Chris Demetriou + + * mips.igen: Remove whitespace at end of lines. + +2002-03-02 Chris Demetriou + + * mips.igen (loadstore_ea): New function to do effective + address calculations. + (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store, + do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1, + CACHE): Use loadstore_ea to do effective address computations. + +2002-03-02 Chris Demetriou + + * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND. + * mips.igen (LL, CxC1, MxC1): Likewise. + +2002-03-02 Chris Demetriou + + * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt, + CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, + FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt, + MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D, + NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, + SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE): + Don't split opcode fields by hand, use the opcode field values + provided by igen. + +2002-03-01 Chris Demetriou + + * mips.igen (do_divu): Fix spacing. + + * mips.igen (do_dsllv): Move to be right before DSLLV, + to match the rest of the do_ functions. + +2002-03-01 Chris Demetriou + + * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl, + DSRL32, do_dsrlv): Trace inputs and results. + +2002-03-01 Chris Demetriou + + * mips.igen (CACHE): Provide instruction-printing string. + + * interp.c (signal_exception): Comment tokens after #endif. + +2002-02-28 Chris Demetriou + + * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32". + (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt, + NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt, + ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt, + CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta, + C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1, + SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D, + LWC1, SWC1): Add "f" to filter, since these are FP instructions. + +2002-02-28 Chris Demetriou + + * mips.igen (DSRA32, DSRAV): Fix order of arguments in + instruction-printing string. + (LWU): Use '64' as the filter flag. + +2002-02-28 Chris Demetriou + + * mips.igen (SDXC1): Fix instruction-printing string. + +2002-02-28 Chris Demetriou + + * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with + filter flags "32,f". + +2002-02-27 Chris Demetriou + + * mips.igen (PREFX): This is a 64-bit instruction, use '64' + as the filter flag. + +2002-02-27 Chris Demetriou + + * mips.igen (PREFX): Tweak instruction opcode fields (i.e., + add a comma) so that it more closely match the MIPS ISA + documentation opcode partitioning. + (PREF): Put useful names on opcode fields, and include + instruction-printing string. + +2002-02-27 Chris Demetriou + + * mips.igen (check_u64): New function which in the future will + check whether 64-bit instructions are usable and signal an + exception if not. Currently a no-op. + (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL, + DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, + DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1, + LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64. + + * mips.igen (check_fpu): New function which in the future will + check whether FPU instructions are usable and signal an exception + if not. Currently a no-op. + (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb, + CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, + CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1, + LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf, + MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, + NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt, + ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1, + SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu. + +2002-02-27 Chris Demetriou + + * mips.igen (do_load_left, do_load_right): Move to be immediately + following do_load. + (do_store_left, do_store_right): Move to be immediately following + do_store. + +2002-02-27 Chris Demetriou + + * mips.igen (mipsV): New model name. Also, add it to + all instructions and functions where it is appropriate. + +2002-02-18 Chris Demetriou + + * mips.igen: For all functions and instructions, list model + names that support that instruction one per line. + +2002-02-11 Chris Demetriou + + * mips.igen: Add some additional comments about supported + models, and about which instructions go where. + (BC1b, MFC0, MTC0, RFE): Sort supported models in the same + order as is used in the rest of the file. + +2002-02-11 Chris Demetriou + + * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment + indicating that ALU32_END or ALU64_END are there to check + for overflow. + (DADD): Likewise, but also remove previous comment about + overflow checking. + +2002-02-10 Chris Demetriou + + * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32, + DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU, + JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU, + SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI, + ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode + fields (i.e., add and move commas) so that they more closely + match the MIPS ISA documentation opcode partitioning. + +2002-02-10 Chris Demetriou + + * mips.igen (ADDI): Print immediate value. + (BREAK): Print code. + (DADDIU, DSRAV, DSRLV): Print correct instruction name. + (SLL): Print "nop" specially, and don't run the code + that does the shift for the "nop" case. + +2001-11-17 Fred Fish + + * sim-main.h (float_operation): Move enum declaration outside + of _sim_cpu struct declaration. + +2001-04-12 Jim Blandy + + * mips.igen (CFC1, CTC1): Pass the correct register numbers to + PENDING_FILL. Use PENDING_SCHED directly to handle the pending + set of the FCSR. + * sim-main.h (COCIDX): Remove definition; this isn't supported by + PENDING_FILL, and you can get the intended effect gracefully by + calling PENDING_SCHED directly. + +2001-02-23 Ben Elliston + + * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not + already defined elsewhere. + +2001-02-19 Ben Elliston + + * sim-main.h (sim_monitor): Return an int. + * interp.c (sim_monitor): Add return values. + (signal_exception): Handle error conditions from sim_monitor. + +2001-02-08 Ben Elliston + + * sim-main.c (load_memory): Pass cia to sim_core_read* functions. + (store_memory): Likewise, pass cia to sim_core_write*. + +2000-10-19 Frank Ch. Eigler + + On advice from Chris G. Demetriou : + * sim-main.h (GPR_CLEAR): Remove unused alternative macro. + +Thu Jul 27 22:02:05 2000 Andrew Cagney + + From Maciej W. Rozycki : + * Makefile.in: Don't delete *.igen when cleaning directory. + +Wed Jul 19 18:50:51 2000 Andrew Cagney + + * m16.igen (break): Call SignalException not sim_engine_halt. + +Mon Jul 3 11:13:20 2000 Andrew Cagney + + From Jason Eckhardt: + * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT]. + +Tue Jun 13 20:52:07 2000 Andrew Cagney + + * mips.igen (MxC1, DMxC1): Fix printf formatting. + +2000-05-24 Michael Hayes + + * mips.igen (do_dmultx): Fix typo. + +Tue May 23 21:39:23 2000 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Apr 28 20:48:36 2000 Andrew Cagney + + * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call. + +2000-04-12 Frank Ch. Eigler + + * sim-main.h (GPR_CLEAR): Define macro. + +Mon Apr 10 00:07:09 2000 Andrew Cagney + + * interp.c (decode_coproc): Output long using %lx and not %s. + +2000-03-21 Frank Ch. Eigler + + * interp.c (sim_open): Sort & extend dummy memory regions for + --board=jmr3904 for eCos. + +2000-03-02 Frank Ch. Eigler + + * configure: Regenerated. + +Tue Feb 8 18:35:01 2000 Donald Lindsay + + * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf + calls, conditional on the simulator being in verbose mode. + +Fri Feb 4 09:45:15 2000 Donald Lindsay + + * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary + cache don't get ReservedInstruction traps. + +1999-11-29 Mark Salter + + * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask + to clear status bits in sdisr register. This is how the hardware works. + + * interp.c (sim_open): Added more memory aliases for jmr3904 hardware + being used by cygmon. + +1999-11-11 Andrew Haley + + * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0 + instructions. + +Thu Sep 9 15:12:08 1999 Geoffrey Keating + + * mips.igen (MULT): Correct previous mis-applied patch. + +Tue Sep 7 13:34:54 1999 Geoffrey Keating + + * mips.igen (delayslot32): Handle sequence like + mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12 + correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue. + (MULT): Actually pass the third register... + +1999-09-03 Mark Salter + + * interp.c (sim_open): Added more memory aliases for additional + hardware being touched by cygmon on jmr3904 board. + +Thu Sep 2 18:15:53 1999 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Jul 27 16:36:51 1999 Andrew Cagney + + * interp.c (sim_store_register): Handle case where client - GDB - + specifies that a 4 byte register is 8 bytes in size. + (sim_fetch_register): Ditto. + +1999-07-14 Frank Ch. Eigler + + Implement "sim firmware" option, inspired by jimb's version of 1998-01. + * interp.c (firmware_option_p): New global flag: "sim firmware" given. + (idt_monitor_base): Base address for IDT monitor traps. + (pmon_monitor_base): Ditto for PMON. + (lsipmon_monitor_base): Ditto for LSI PMON. + (MONITOR_BASE, MONITOR_SIZE): Removed macros. + (mips_option): Add "firmware" option with new OPTION_FIRMWARE key. + (sim_firmware_command): New function. + (mips_option_handler): Call it for OPTION_FIRMWARE. + (sim_open): Allocate memory for idt_monitor region. If "--board" + option was given, add no monitor by default. Add BREAK hooks only if + monitors are also there. + +Mon Jul 12 00:02:27 1999 Andrew Cagney + + * interp.c (sim_monitor): Flush output before reading input. + +Sun Jul 11 19:28:11 1999 Andrew Cagney + + * tconfig.in (SIM_HANDLES_LMA): Always define. + +Thu Jul 8 16:06:59 1999 Andrew Cagney + + From Mark Salter : + * interp.c (BOARD_BSP): Define. Add to list of possible boards. + (sim_open): Add setup for BSP board. + +Wed Jul 7 12:45:58 1999 Andrew Cagney + + * mips.igen (MULT, MULTU): Add syntax for two operand version. + (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report + them as unimplemented. + +1999-05-08 Felix Lee + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +1999-04-21 Frank Ch. Eigler + + * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub. + +Thu Apr 15 14:15:17 1999 Andrew Cagney + + * configure.in: Any mips64vr5*-*-* target should have + -DTARGET_ENABLE_FR=1. + (default_endian): Any mips64vr*el-*-* target should default to + LITTLE_ENDIAN. + * configure: Re-generate. + +1999-02-19 Gavin Romig-Koch + + * mips.igen (ldl): Extend from _16_, not 32. + +Wed Jan 27 18:51:38 1999 Andrew Cagney + + * interp.c (sim_store_register): Force registers written to by GDB + into an un-interpreted state. + +1999-02-05 Frank Ch. Eigler + + * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the + CPU, start periodic background I/O polls. + (tx3904sio_poll): New function: periodic I/O poller. + +1998-12-30 Frank Ch. Eigler + + * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt. + +Tue Dec 29 16:03:53 1998 Rainer Orth + + * configure.in, configure (mips64vr5*-*-*): Added missing ;; in + case statement. + +1998-12-29 Frank Ch. Eigler + + * interp.c (sim_open): Allocate jm3904 memory in smaller chunks. + (load_word): Call SIM_CORE_SIGNAL hook on error. + (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before + starting. For exception dispatching, pass PC instead of NULL_CIA. + (decode_coproc): Use COP0_BADVADDR to store faulting address. + * sim-main.h (COP0_BADVADDR): Define. + (SIM_CORE_SIGNAL): Define hook to call mips_core_signal. + (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*(). + (_sim_cpu): Add exc_* fields to store register value snapshots. + * mips.igen (*): Replace memory-related SignalException* calls + with references to SIM_CORE_SIGNAL hook. + + * dv-tx3904irc.c (tx3904irc_port_event): printf format warning + fix. + * sim-main.c (*): Minor warning cleanups. + +1998-12-24 Gavin Romig-Koch + + * m16.igen (DADDIU5): Correct type-o. + +Mon Dec 21 10:34:48 1998 Andrew Cagney + + * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp + variables. + +Wed Dec 16 18:20:28 1998 Andrew Cagney + + * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib + to include path. + (interp.o): Add dependency on itable.h + (oengine.c, gencode): Delete remaining references. + (BUILT_SRC_FROM_GEN): Clean up. + +1998-12-16 Gavin Romig-Koch + + * vr4run.c: New. + * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a, + tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack, + tmp-run-hack) : New. + * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU, + DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX): + Drop the "64" qualifier to get the HACK generator working. + Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT. + * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only + qualifier to get the hack generator working. + (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New. + (DSLL): Use do_dsll. + (DSLLV): Use do_dsllv. + (DSRA): Use do_dsra. + (DSRL): Use do_dsrl. + (DSRLV): Use do_dsrlv. + (BC1): Move *vr4100 to get the HACK generator working. + (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to + get the HACK generator working. + (MACC) Rename to get the HACK generator working. + (DMACC,MACCS,DMACCS): Add the 64. + +1998-12-12 Gavin Romig-Koch + + * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts. + * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR. + +1998-12-11 Gavin Romig-Koch + + * mips/interp.c (DEBUG): Cleanups. + +1998-12-10 Frank Ch. Eigler + + * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes. + (tx3904sio_tickle): fflush after a stdout character output. + +1998-12-03 Frank Ch. Eigler + + * interp.c (sim_close): Uninstall modules. + +Wed Nov 25 13:41:03 1998 Andrew Cagney + + * sim-main.h, interp.c (sim_monitor): Change to global + function. + +Wed Nov 25 17:33:24 1998 Andrew Cagney + + * configure.in (vr4100): Only include vr4100 instructions in + simulator. + * configure: Re-generate. + * m16.igen (*): Tag all mips16 instructions as also being vr4100. + +Mon Nov 23 18:20:36 1998 Andrew Cagney + + * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN. + * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping + true alternative. + + * configure.in (sim_default_gen, sim_use_gen): Replace with + sim_gen. + (--enable-sim-igen): Delete config option. Always using IGEN. + * configure: Re-generate. + + * Makefile.in (gencode): Kill, kill, kill. + * gencode.c: Ditto. + +Mon Nov 23 18:07:36 1998 Andrew Cagney + + * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64 + bit mips16 igen simulator. + * configure: Re-generate. + + * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark + as part of vr4100 ISA. + * vr.igen: Mark all instructions as 64 bit only. + +Mon Nov 23 17:07:37 1998 Andrew Cagney + + * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent): + Pacify GCC. + +Mon Nov 23 13:23:40 1998 Andrew Cagney + + * configure.in: Configure mips-lsi-elf nee mips*lsi* as a + mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos. + * configure: Re-generate. + + * m16.igen (BREAK): Define breakpoint instruction. + (JALX32): Mark instruction as mips16 and not r3900. + * mips.igen (C.cond.fmt): Fix typo in instruction format. + + * sim-main.h (PENDING_FILL): Wrap C statements in do/while. + +Sat Nov 7 09:54:38 1998 Andrew Cagney + + * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK + insn as a debug breakpoint. + + * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as + pending.slot_size. + (PENDING_SCHED): Clean up trace statement. + (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL. + (PENDING_FILL): Delay write by only one cycle. + (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE. + + * sim-main.c (pending_tick): Clean up trace statements. Add trace + of pending writes. + (pending_tick): Fix sizes in switch statements, 4 & 8 instead of + 32 & 64. + (pending_tick): Move incrementing of index to FOR statement. + (pending_tick): Only update PENDING_OUT after a write has occured. + + * configure.in: Add explicit mips-lsi-* target. Use gencode to + build simulator. + * configure: Re-generate. + + * interp.c (sim_engine_run OLD): Delete explicit call to + PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK. + +Sat Oct 30 09:49:10 1998 Frank Ch. Eigler + + * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy + interrupt level number to match changed SignalExceptionInterrupt + macro. + +Fri Oct 9 18:02:25 1998 Doug Evans + + * interp.c: #include "itable.h" if WITH_IGEN. + (get_insn_name): New function. + (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS. + * sim-main.h (MAX_INSNS,INSN_NAME): Delete. + +Mon Sep 14 12:36:44 1998 Frank Ch. Eigler + + * configure: Rebuilt to inhale new common/aclocal.m4. + +Tue Sep 1 15:39:18 1998 Frank Ch. Eigler + + * dv-tx3904sio.c: Include sim-assert.h. + +Tue Aug 25 12:49:46 1998 Frank Ch. Eigler + + * dv-tx3904sio.c: New file: tx3904 serial I/O module. + * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target. + Reorganize target-specific sim-hardware checks. + * configure: rebuilt. + * interp.c (sim_open): For tx39 target boards, set + OPERATING_ENVIRONMENT, add tx3904sio devices. + * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading + ROM executables. Install dv-sockser into sim-modules list. + + * dv-tx3904irc.c: Compiler warning clean-up. + * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly + frequent hw-trace messages. + +Fri Jul 31 18:14:16 1998 Andrew Cagney + + * vr.igen (MulAcc): Identify as a vr4100 specific function. + +Sat Jul 25 16:03:14 1998 Andrew Cagney + + * Makefile.in (IGEN_INCLUDE): Add vr.igen. + + * vr.igen: New file. + (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c. + * mips.igen: Define vr4100 model. Include vr.igen. +Mon Jun 29 09:21:07 1998 Gavin Koch + + * mips.igen (check_mf_hilo): Correct check. + +Wed Jun 17 12:20:49 1998 Andrew Cagney + + * sim-main.h (interrupt_event): Add prototype. + + * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused + register_ptr, register_value. + (deliver_tx3904tmr_tick): Fix types passed to printf fmt. + + * sim-main.h (tracefh): Make extern. + +Tue Jun 16 14:39:00 1998 Frank Ch. Eigler + + * dv-tx3904tmr.c: Deschedule timer event after dispatching. + Reduce unnecessarily high timer event frequency. + * dv-tx3904cpu.c: Ditto for interrupt event. + +Wed Jun 10 13:22:32 1998 Frank Ch. Eigler + + * interp.c (decode_coproc): For TX39, add stub COP0 register #7, + to allay warnings. + (interrupt_event): Made non-static. + + * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental + interchange of configuration values for external vs. internal + clock dividers. + +Tue Jun 9 12:46:24 1998 Ian Carmichael + + * mips.igen (BREAK): Moved code to here for + simulator-reserved break instructions. + * gencode.c (build_instruction): Ditto. + * interp.c (signal_exception): Code moved from here. Non- + reserved instructions now use exception vector, rather + than halting sim. + * sim-main.h: Moved magic constants to here. + +Tue Jun 9 12:29:50 1998 Frank Ch. Eigler + + * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE + register upon non-zero interrupt event level, clear upon zero + event value. + * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal + by passing zero event value. + (*_io_{read,write}_buffer): Endianness fixes. + * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes. + (deliver_*_tick): Reduce sim event interval to 75% of count interval. + + * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based + serial I/O and timer module at base address 0xFFFF0000. + +Tue Jun 9 11:52:29 1998 Gavin Koch + + * mips.igen (SWC1) : Correct the handling of ReverseEndian + and BigEndianCPU. + +Tue Jun 9 11:40:57 1998 Gavin Koch + + * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips + parts. + * configure: Update. + +Thu Jun 4 15:37:33 1998 Frank Ch. Eigler + + * dv-tx3904tmr.c: New file - implements tx3904 timer. + * dv-tx3904{irc,cpu}.c: Mild reformatting. + * configure.in: Include tx3904tmr in hw_device list. + * configure: Rebuilt. + * interp.c (sim_open): Instantiate three timer instances. + Fix address typo of tx3904irc instance. + +Tue Jun 2 15:48:02 1998 Ian Carmichael + + * interp.c (signal_exception): SystemCall exception now uses + the exception vector. + +Mon Jun 1 18:18:26 1998 Frank Ch. Eigler + + * interp.c (decode_coproc): For TX39, add stub COP0 register #3, + to allay warnings. + +Fri May 29 11:40:39 1998 Andrew Cagney + + * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39. + +Mon May 25 20:47:45 1998 Andrew Cagney + + * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method. + + * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and + sim-main.h. Declare a struct hw_descriptor instead of struct + hw_device_descriptor. + +Mon May 25 12:41:38 1998 Andrew Cagney + + * mips.igen (do_store_left, do_load_left): Compute nr of left and + right bits and then re-align left hand bytes to correct byte + lanes. Fix incorrect computation in do_store_left when loading + bytes from second word. + +Fri May 22 13:34:20 1998 Andrew Cagney + + * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904. + * interp.c (sim_open): Only create a device tree when HW is + enabled. + + * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC. + * interp.c (signal_exception): Ditto. + +Thu May 21 14:24:11 1998 Gavin Koch + + * gencode.c: Mark BEGEZALL as LIKELY. + +Thu May 21 18:57:19 1998 Andrew Cagney + + * sim-main.h (ALU32_END): Sign extend 32 bit results. + * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace. + +Mon May 18 18:22:42 1998 Frank Ch. Eigler + + * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware + modules. Recognize TX39 target with "mips*tx39" pattern. + * configure: Rebuilt. + * sim-main.h (*): Added many macros defining bits in + TX39 control registers. + (SignalInterrupt): Send actual PC instead of NULL. + (SignalNMIReset): New exception type. + * interp.c (board): New variable for future use to identify + a particular board being simulated. + (mips_option_handler,mips_options): Added "--board" option. + (interrupt_event): Send actual PC. + (sim_open): Make memory layout conditional on board setting. + (signal_exception): Initial implementation of hardware interrupt + handling. Accept another break instruction variant for simulator + exit. + (decode_coproc): Implement RFE instruction for TX39. + (mips.igen): Decode RFE instruction as such. + * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. + * interp.c: Define "jmr3904" and "jmr3904debug" board types and + bbegin to implement memory map. + * dv-tx3904cpu.c: New file. + * dv-tx3904irc.c: New file. + +Wed May 13 14:40:11 1998 Gavin Koch + + * mips.igen (check_mt_hilo): Create a separate r3900 version. + +Wed May 13 14:11:46 1998 Gavin Koch + + * tx.igen (madd,maddu): Replace calls to check_op_hilo + with calls to check_div_hilo. + +Wed May 13 09:59:27 1998 Gavin Koch + + * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo): + Replace check_op_hilo with check_mult_hilo and check_div_hilo. + Add special r3900 version of do_mult_hilo. + (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo + with calls to check_mult_hilo. + (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo + with calls to check_div_hilo. + +Tue May 12 15:22:11 1998 Andrew Cagney + + * configure.in (SUBTARGET_R3900): Define for mipstx39 target. + Document a replacement. + +Fri May 8 17:48:19 1998 Ian Carmichael + + * interp.c (sim_monitor): Make mon_printf work. + +Wed May 6 19:42:19 1998 Doug Evans + + * sim-main.h (INSN_NAME): New arg `cpu'. + +Tue Apr 28 18:33:31 1998 Geoffrey Noer + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Sun Apr 26 15:31:55 1998 Tom Tromey + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Sun Apr 26 15:20:01 1998 Tom Tromey + + * acconfig.h: New file. + * configure.in: Reverted change of Apr 24; use sinclude again. + +Fri Apr 24 14:16:40 1998 Tom Tromey + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Fri Apr 24 11:19:20 1998 Tom Tromey + + * configure.in: Don't call sinclude. + +Fri Apr 24 11:35:01 1998 Andrew Cagney + + * mips.igen (do_store_left): Pass 0 not NULL to store_memory. + +Tue Apr 21 11:59:50 1998 Andrew Cagney + + * mips.igen (ERET): Implement. + + * interp.c (decode_coproc): Return sign-extended EPC. + + * mips.igen (ANDI, LUI, MFC0): Add tracing code. + + * interp.c (signal_exception): Do not ignore Trap. + (signal_exception): On TRAP, restart at exception address. + (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define. + (signal_exception): Update. + (sim_open): Patch V_COMMON interrupt vector with an abort sequence + so that TRAP instructions are caught. + +Mon Apr 20 11:26:55 1998 Andrew Cagney + + * sim-main.h (struct hilo_access, struct hilo_history): Define, + contains HI/LO access history. + (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access. + (HIACCESS, LOACCESS): Delete, replace with + (HIHISTORY, LOHISTORY): New macros. + (CHECKHILO): Delete all, moved to mips.igen + + * gencode.c (build_instruction): Do not generate checks for + correct HI/LO register usage. + + * interp.c (old_engine_run): Delete checks for correct HI/LO + register usage. + + * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo, + check_mf_cycles): New functions. + (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div, + do_divu, domultx, do_mult, do_multu): Use. + + * tx.igen ("madd", "maddu"): Use. + +Wed Apr 15 18:31:54 1998 Andrew Cagney + + * mips.igen (DSRAV): Use function do_dsrav. + (SRAV): Use new function do_srav. + + * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX]. + (B): Sign extend 11 bit immediate. + (EXT-B*): Shift 16 bit immediate left by 1. + (ADDIU*): Don't sign extend immediate value. + +Wed Apr 15 10:32:15 1998 Andrew Cagney + + * m16run.c (sim_engine_run): Restore CIA after handling an event. + + * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use + functions. + + * mips.igen (delayslot32, nullify_next_insn): New functions. + (m16.igen): Always include. + (do_*): Add more tracing. + + * m16.igen (delayslot16): Add NIA argument, could be called by a + 32 bit MIPS16 instruction. + + * interp.c (ifetch16): Move function from here. + * sim-main.c (ifetch16): To here. + + * sim-main.c (ifetch16, ifetch32): Update to match current + implementations of LH, LW. + (signal_exception): Don't print out incorrect hex value of illegal + instruction. + +Wed Apr 15 00:17:25 1998 Andrew Cagney + + * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an + instruction. + + * m16.igen: Implement MIPS16 instructions. + + * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu, + do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav, + do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or, + do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra, + do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move + bodies of corresponding code from 32 bit insn to these. Also used + by MIPS16 versions of functions. + + * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define. + (IMEM16): Drop NR argument from macro. + +Sat Apr 4 22:39:50 1998 Andrew Cagney + + * Makefile.in (SIM_OBJS): Add sim-main.o. + + * sim-main.h (address_translation, load_memory, store_memory, + cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark + as INLINE_SIM_MAIN. + (pr_addr, pr_uword64): Declare. + (sim-main.c): Include when H_REVEALS_MODULE_P. + + * interp.c (address_translation, load_memory, store_memory, + cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move + from here. + * sim-main.c: To here. Fix compilation problems. + + * configure.in: Enable inlining. + * configure: Re-config. + +Sat Apr 4 20:36:25 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Apr 3 04:32:35 1998 Andrew Cagney + + * mips.igen: Include tx.igen. + * Makefile.in (IGEN_INCLUDE): Add tx.igen. + * tx.igen: New file, contains MADD and MADDU. + + * interp.c (load_memory): When shifting bytes, use LOADDRMASK not + the hardwired constant `7'. + (store_memory): Ditto. + (LOADDRMASK): Move definition to sim-main.h. + + mips.igen (MTC0): Enable for r3900. + (ADDU): Add trace. + + mips.igen (do_load_byte): Delete. + (do_load, do_store, do_load_left, do_load_write, do_store_left, + do_store_right): New functions. + (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use. + + configure.in: Let the tx39 use igen again. + configure: Update. + +Thu Apr 2 10:59:39 1998 Andrew Cagney + + * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity, + not an address sized quantity. Return zero for cache sizes. + +Wed Apr 1 23:47:53 1998 Andrew Cagney + + * mips.igen (r3900): r3900 does not support 64 bit integer + operations. + +Mon Mar 30 14:46:05 1998 Gavin Koch + + * configure.in (mipstx39*-*-*): Use gencode simulator rather + than igen one. + * configure : Rebuild. + +Fri Mar 27 16:15:52 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Mar 27 15:01:50 1998 Andrew Cagney + + * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS. + +Wed Mar 25 16:44:27 1998 Ian Carmichael + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Regenerated to track ../common/aclocal.m4 changes. + +Wed Mar 25 12:35:29 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Mar 25 10:05:46 1998 Andrew Cagney + + * interp.c (Max, Min): Comment out functions. Not yet used. + +Wed Mar 18 12:38:12 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Mar 17 19:05:20 1998 Frank Ch. Eigler + + * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added + configurable settings for stand-alone simulator. + + * configure.in: Added X11 search, just in case. + + * configure: Regenerated. + +Wed Mar 11 14:09:10 1998 Andrew Cagney + + * interp.c (sim_write, sim_read, load_memory, store_memory): + Replace sim_core_*_map with read_map, write_map, exec_map resp. + +Tue Mar 3 13:58:43 1998 Andrew Cagney + + * sim-main.h (GETFCC): Return an unsigned value. + +Tue Mar 3 13:21:37 1998 Andrew Cagney + + * mips.igen (DIV): Fix check for -1 / MIN_INT. + (DADD): Result destination is RD not RT. + +Fri Feb 27 13:49:49 1998 Andrew Cagney + + * sim-main.h (HIACCESS, LOACCESS): Always define. + + * mdmx.igen (Maxi, Mini): Rename Max, Min. + + * interp.c (sim_info): Delete. + +Fri Feb 27 18:41:01 1998 Doug Evans + + * interp.c (DECLARE_OPTION_HANDLER): Use it. + (mips_option_handler): New argument `cpu'. + (sim_open): Update call to sim_add_option_table. + +Wed Feb 25 18:56:22 1998 Andrew Cagney + + * mips.igen (CxC1): Add tracing. + +Fri Feb 20 17:43:21 1998 Andrew Cagney + + * sim-main.h (Max, Min): Declare. + + * interp.c (Max, Min): New functions. + + * mips.igen (BC1): Add tracing. + +Thu Feb 19 14:50:00 1998 John Metzler + + * interp.c Added memory map for stack in vr4100 + +Thu Feb 19 10:21:21 1998 Gavin Koch + + * interp.c (load_memory): Add missing "break"'s. + +Tue Feb 17 12:45:35 1998 Andrew Cagney + + * interp.c (sim_store_register, sim_fetch_register): Pass in + length parameter. Return -1. + +Tue Feb 10 11:57:40 1998 Ian Carmichael + + * interp.c: Added hardware init hook, fixed warnings. + +Sat Feb 7 17:16:20 1998 Andrew Cagney + + * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL. + +Tue Feb 3 11:36:02 1998 Andrew Cagney + + * interp.c (ifetch16): New function. + + * sim-main.h (IMEM32): Rename IMEM. + (IMEM16_IMMED): Define. + (IMEM16): Define. + (DELAY_SLOT): Update. + + * m16run.c (sim_engine_run): New file. + + * m16.igen: All instructions except LB. + (LB): Call do_load_byte. + * mips.igen (do_load_byte): New function. + (LB): Call do_load_byte. + + * mips.igen: Move spec for insn bit size and high bit from here. + * Makefile.in (tmp-igen, tmp-m16): To here. + + * m16.dc: New file, decode mips16 instructions. + + * Makefile.in (SIM_NO_ALL): Define. + (tmp-m16): Generate both 16 bit and 32 bit simulator engines. + +Tue Feb 3 11:28:00 1998 Andrew Cagney + + * configure.in (mips_fpu_bitsize): For tx39, restrict floating + point unit to 32 bit registers. + * configure: Re-generate. + +Sun Feb 1 15:47:14 1998 Andrew Cagney + + * configure.in (sim_use_gen): Make IGEN the default simulator + generator for generic 32 and 64 bit mips targets. + * configure: Re-generate. + +Sun Feb 1 16:52:37 1998 Andrew Cagney + + * sim-main.h (SizeFGR): Determine from floating-point and not gpr + bitsize. + + * interp.c (sim_fetch_register, sim_store_register): Read/write + FGR from correct location. + (sim_open): Set size of FGR's according to + WITH_TARGET_FLOATING_POINT_BITSIZE. + + * sim-main.h (FGR): Store floating point registers in a separate + array. + +Sun Feb 1 16:47:51 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Feb 3 00:10:50 1998 Andrew Cagney + + * interp.c (ColdReset): Call PENDING_INVALIDATE. + + * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK. + + * interp.c (pending_tick): New function. Deliver pending writes. + + * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED, + PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that + it can handle mixed sized quantites and single bits. + +Mon Feb 2 17:43:15 1998 Andrew Cagney + + * interp.c (oengine.h): Do not include when building with IGEN. + (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE. + (sim_info): Ditto for PROCESSOR_64BIT. + (sim_monitor): Replace ut_reg with unsigned_word. + (*): Ditto for t_reg. + (LOADDRMASK): Define. + (sim_open): Remove defunct check that host FP is IEEE compliant, + using software to emulate floating point. + (value_fpr, ...): Always compile, was conditional on HASFPU. + +Sun Feb 1 11:15:29 1998 Andrew Cagney + + * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in + size. + + * interp.c (SD, CPU): Define. + (mips_option_handler): Set flags in each CPU. + (interrupt_event): Assume CPU 0 is the one being iterrupted. + (sim_close): Do not clear STATE, deleted anyway. + (sim_write, sim_read): Assume CPU zero's vm should be used for + data transfers. + (sim_create_inferior): Set the PC for all processors. + (sim_monitor, store_word, load_word, mips16_entry): Add cpu + argument. + (mips16_entry): Pass correct nr of args to store_word, load_word. + (ColdReset): Cold reset all cpu's. + (signal_exception): Pass cpu to sim_monitor & mips16_entry. + (sim_monitor, load_memory, store_memory, signal_exception): Use + `CPU' instead of STATE_CPU. + + + * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with + SD or CPU_. + + * sim-main.h (signal_exception): Add sim_cpu arg. + (SignalException*): Pass both SD and CPU to signal_exception. + * interp.c (signal_exception): Update. + + * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c: + Ditto + (sync_operation, prefetch, cache_op, store_memory, load_memory, + address_translation): Ditto + (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto. + +Sat Jan 31 18:15:41 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Sat Jan 31 14:49:24 1998 Andrew Cagney + + * interp.c (sim_engine_run): Add `nr_cpus' argument. + + * mips.igen (model): Map processor names onto BFD name. + + * sim-main.h (CPU_CIA): Delete. + (SET_CIA, GET_CIA): Define + +Wed Jan 21 16:16:27 1998 Andrew Cagney + + * sim-main.h (GPR_SET): Define, used by igen when zeroing a + regiser. + + * configure.in (default_endian): Configure a big-endian simulator + by default. + * configure: Re-generate. + +Mon Jan 19 22:26:29 1998 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Jan 5 20:38:54 1998 Mark Alexander + + * interp.c (sim_monitor): Handle Densan monitor outbyte + and inbyte functions. + +1997-12-29 Felix Lee + + * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c). + +Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com) + + * Makefile.in (tmp-igen): Arrange for $zero to always be + reset to zero after every instruction. + +Mon Dec 15 23:17:11 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com) + + * mips.igen (MSUB): Fix to work like MADD. + * gencode.c (MSUB): Similarly. + +Thu Dec 4 09:21:05 1997 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Nov 26 11:00:23 1997 Andrew Cagney + + * mips.igen (LWC1): Correct assembler - lwc1 not swc1. + +Sun Nov 23 01:45:20 1997 Andrew Cagney + + * sim-main.h (sim-fpu.h): Include. + + * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub, + Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite + using host independant sim_fpu module. + +Thu Nov 20 19:56:22 1997 Andrew Cagney + + * interp.c (signal_exception): Report internal errors with SIGABRT + not SIGQUIT. + + * sim-main.h (C0_CONFIG): New register. + (signal.h): No longer include. + + * interp.c (decode_coproc): Allow access C0_CONFIG to register. + +Tue Nov 18 15:33:48 1997 Doug Evans + + * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS). + +Fri Nov 14 11:56:48 1997 Andrew Cagney + + * mips.igen: Tag vr5000 instructions. + (ANDI): Was missing mipsIV model, fix assembler syntax. + (do_c_cond_fmt): New function. + (C.cond.fmt): Handle mips I-III which do not support CC field + separatly. + (bc1): Handle mips IV which do not have a delaed FCC separatly. + (SDR): Mask paddr when BigEndianMem, not the converse as specified + in IV3.2 spec. + (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle + vr5000 which saves LO in a GPR separatly. + + * configure.in (enable-sim-igen): For vr5000, select vr5000 + specific instructions. + * configure: Re-generate. + +Wed Nov 12 14:42:52 1997 Andrew Cagney + + * Makefile.in (SIM_OBJS): Add sim-fpu module. + + * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and + fmt_uninterpreted_64 bit cases to switch. Convert to + fmt_formatted, + + * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define, + + * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse + as specified in IV3.2 spec. + (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR. + +Tue Nov 11 12:38:23 1997 Andrew Cagney + + * mips.igen: Delay slot branches add OFFSET to NIA not CIA. + (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement. + (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non + PENDING_FILL versions of instructions. Simplify. + (X): New function. + (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of + instructions. + (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to + a signed value. + (MTHI, MFHI): Disable code checking HI-LO. + + * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh + global. + (NULLIFY_NEXT_INSTRUCTION): Call dotrace. + +Thu Nov 6 16:36:35 1997 Andrew Cagney + + * gencode.c (build_mips16_operands): Replace IPC with cia. + + * interp.c (sim_monitor, signal_exception, cache_op, store_fpr, + value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace + IPC to `cia'. + (UndefinedResult): Replace function with macro/function + combination. + (sim_engine_run): Don't save PC in IPC. + + * sim-main.h (IPC): Delete. + + + * interp.c (signal_exception, store_word, load_word, + address_translation, load_memory, store_memory, cache_op, + prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert, + cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add + current instruction address - cia - argument. + (sim_read, sim_write): Call address_translation directly. + (sim_engine_run): Rename variable vaddr to cia. + (signal_exception): Pass cia to sim_monitor + + * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp, + Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW, + COP_LD, COP_SW, COP_SD, DecodeCoproc): Update. + + * sim-main.h (SignalExceptionSimulatorFault): Delete definition. + * interp.c (sim_open): Replace SignalExceptionSimulatorFault with + SIM_ASSERT. + + * interp.c (signal_exception): Pass restart address to + sim_engine_restart. + + * Makefile.in (semantics.o, engine.o, support.o, itable.o, + idecode.o): Add dependency. + + * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK): + Delete definitions + (DELAY_SLOT): Update NIA not PC with branch address. + (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next. + + * mips.igen: Use CIA not PC in branch calculations. + (illegal): Call SignalException. + (BEQ, ADDIU): Fix assembler. + +Wed Nov 5 12:19:56 1997 Andrew Cagney + + * m16.igen (JALX): Was missing. + + * configure.in (enable-sim-igen): New configuration option. + * configure: Re-generate. + + * sim-main.h (MAX_INSNS, INSN_NAME): Define. + + * interp.c (load_memory, store_memory): Delete parameter RAW. + (sim_read, sim_write): Use sim_core_{read,write}_buffer directly + bypassing {load,store}_memory. + + * sim-main.h (ByteSwapMem): Delete definition. + + * Makefile.in (SIM_OBJS): Add sim-memopt module. + + * interp.c (sim_do_command, sim_commands): Delete mips specific + commands. Handled by module sim-options. + + * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module. + (WITH_MODULO_MEMORY): Define. + + * interp.c (sim_info): Delete code printing memory size. + + * interp.c (mips_size): Nee sim_size, delete function. + (power2): Delete. + (monitor, monitor_base, monitor_size): Delete global variables. + (sim_open, sim_close): Delete code creating monitor and other + memory regions. Use sim-memopts module, via sim_do_commandf, to + manage memory regions. + (load_memory, store_memory): Use sim-core for memory model. + + * interp.c (address_translation): Delete all memory map code + except line forcing 32 bit addresses. + +Wed Nov 5 11:21:11 1997 Andrew Cagney + + * sim-main.h (WITH_TRACE): Delete definition. Enables common + trace options. + + * interp.c (logfh, logfile): Delete globals. + (sim_open, sim_close): Delete code opening & closing log file. + (mips_option_handler): Delete -l and -n options. + (OPTION mips_options): Ditto. + + * interp.c (OPTION mips_options): Rename option trace to dinero. + (mips_option_handler): Update. + +Wed Nov 5 09:35:59 1997 Andrew Cagney + + * interp.c (fetch_str): New function. + (sim_monitor): Rewrite using sim_read & sim_write. + (sim_open): Check magic number. + (sim_open): Write monitor vectors into memory using sim_write. + (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define. + (sim_read, sim_write): Simplify - transfer data one byte at a + time. + (load_memory, store_memory): Clarify meaning of parameter RAW. + + * sim-main.h (isHOST): Defete definition. + (isTARGET): Mark as depreciated. + (address_translation): Delete parameter HOST. + + * interp.c (address_translation): Delete parameter HOST. + +Wed Oct 29 11:13:56 1997 Andrew Cagney + + * mips.igen: + + * Makefile.in (IGEN_INCLUDE): Files included by mips.igen. + (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE. + +Tue Oct 28 11:06:47 1997 Andrew Cagney + + * mips.igen: Add model filter field to records. + +Mon Oct 27 17:53:59 1997 Andrew Cagney + + * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0. + + interp.c (sim_engine_run): Do not compile function sim_engine_run + when WITH_IGEN == 1. + + * configure.in (sim_igen_flags, sim_m16_flags): Set according to + target architecture. + + Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to + igen. Replace with configuration variables sim_igen_flags / + sim_m16_flags. + + * m16.igen: New file. Copy mips16 insns here. + * mips.igen: From here. + +Mon Oct 27 13:53:59 1997 Andrew Cagney + + * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ + to top. + (tmp-igen, tmp-m16): Pass -I srcdir to igen. + +Sat Oct 25 16:51:40 1997 Gavin Koch + + * gencode.c (build_instruction): Follow sim_write's lead in using + BigEndianMem instead of !ByteSwapMem. + +Fri Oct 24 17:41:49 1997 Andrew Cagney + + * configure.in (sim_gen): Dependent on target, select type of + generator. Always select old style generator. + + configure: Re-generate. + + Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New + targets. + (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16, + SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN, + IGEN_TRACE, IGEN_INSN, IGEN_DC): Define + (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member + SIM_@sim_gen@_*, set by autoconf. + +Wed Oct 22 12:52:06 1997 Andrew Cagney + + * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define. + + * interp.c (ColdReset): Remove #ifdef HASFPU, check + CURRENT_FLOATING_POINT instead. + + * interp.c (ifetch32): New function. Fetch 32 bit instruction. + (address_translation): Raise exception InstructionFetch when + translation fails and isINSTRUCTION. + + * interp.c (sim_open, sim_write, sim_monitor, store_word, + sim_engine_run): Change type of of vaddr and paddr to + address_word. + (address_translation, prefetch, load_memory, store_memory, + cache_op): Change type of vAddr and pAddr to address_word. + + * gencode.c (build_instruction): Change type of vaddr and paddr to + address_word. + +Mon Oct 20 15:29:04 1997 Andrew Cagney + + * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT + macro to obtain result of ALU op. + +Tue Oct 21 17:39:14 1997 Andrew Cagney + + * interp.c (sim_info): Call profile_print. + +Mon Oct 20 13:31:20 1997 Andrew Cagney + + * Makefile.in (SIM_OBJS): Add sim-profile.o module. + + * sim-main.h (WITH_PROFILE): Do not define, defined in + common/sim-config.h. Use sim-profile module. + (simPROFILE): Delete defintion. + + * interp.c (PROFILE): Delete definition. + (mips_option_handler): Delete 'p', 'y' and 'x' profile options. + (sim_close): Delete code writing profile histogram. + (mips_set_profile, mips_set_profile_size, writeout16, writeout32): + Delete. + (sim_engine_run): Delete code profiling the PC. + +Mon Oct 20 13:31:20 1997 Andrew Cagney + + * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word. + + * interp.c (sim_monitor): Make register pointers of type + unsigned_word*. + + * sim-main.h: Make registers of type unsigned_word not + signed_word. + +Thu Oct 16 10:31:39 1997 Andrew Cagney + + * interp.c (sync_operation): Rename from SyncOperation, make + global, add SD argument. + (prefetch): Rename from Prefetch, make global, add SD argument. + (decode_coproc): Make global. + + * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define. + + * gencode.c (build_instruction): Generate DecodeCoproc not + decode_coproc calls. + + * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h + (SizeFGR): Move to sim-main.h + (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT, + simSIGINT, simJALDELAYSLOT): Move to sim-main.h + (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to + sim-main.h. + (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF, + FP_RM_TOMINF, GETRM): Move to sim-main.h. + (Uncached, CachedNoncoherent, CachedCoherent, Cached, + isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h. + (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian, + BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h + + * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise + exception. + (sim-alu.h): Include. + (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define. + (sim_cia): Typedef to instruction_address. + +Thu Oct 16 10:31:41 1997 Andrew Cagney + + * Makefile.in (interp.o): Rename generated file engine.c to + oengine.c. + + * interp.c: Update. + +Thu Oct 16 10:31:40 1997 Andrew Cagney + + * gencode.c (build_instruction): Use FPR_STATE not fpr_state. + +Thu Oct 16 10:31:39 1997 Andrew Cagney + + * gencode.c (build_instruction): For "FPSQRT", output correct + number of arguments to Recip. + +Tue Oct 14 17:38:18 1997 Andrew Cagney + + * Makefile.in (interp.o): Depends on sim-main.h + + * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers. + + * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state, + ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields. + (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*, + STATE, DSSTATE): Define + (GPR, FGRIDX, ..): Define. + + * interp.c (registers, register_widths, fpr_state, ipc, dspc, + pending_*, hiaccess, loaccess, state, dsstate): Delete globals. + (GPR, FGRIDX, ...): Delete macros. + + * interp.c: Update names to match defines from sim-main.h + +Tue Oct 14 15:11:45 1997 Andrew Cagney + + * interp.c (sim_monitor): Add SD argument. + (sim_warning): Delete. Replace calls with calls to + sim_io_eprintf. + (sim_error): Delete. Replace calls with sim_io_error. + (open_trace, writeout32, writeout16, getnum): Add SD argument. + (mips_set_profile): Rename from sim_set_profile. Add SD argument. + (mips_set_profile_size): Rename from sim_set_profile_size. Add SD + argument. + (mips_size): Rename from sim_size. Add SD argument. + + * interp.c (simulator): Delete global variable. + (callback): Delete global variable. + (mips_option_handler, sim_open, sim_write, sim_read, + sim_store_register, sim_fetch_register, sim_info, sim_do_command, + sim_size,sim_monitor): Use sim_io_* not callback->*. + (sim_open): ZALLOC simulator struct. + (PROFILE): Do not define. + +Tue Oct 14 13:35:48 1997 Andrew Cagney + + * interp.c (sim_open), support.h: Replace CHECKSIM macro found in + support.h with corresponding code. + + * sim-main.h (word64, uword64), support.h: Move definition to + sim-main.h. + (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto. + + * support.h: Delete + * Makefile.in: Update dependencies + * interp.c: Do not include. + +Tue Oct 14 13:35:48 1997 Andrew Cagney + + * interp.c (address_translation, load_memory, store_memory, + cache_op): Rename to from AddressTranslation et.al., make global, + add SD argument + + * sim-main.h (AddressTranslation, LoadMemory, StoreMemory, + CacheOp): Define. + + * interp.c (SignalException): Rename to signal_exception, make + global. + + * interp.c (Interrupt, ...): Move definitions to sim-main.h. + + * sim-main.h (SignalException, SignalExceptionInterrupt, + SignalExceptionInstructionFetch, SignalExceptionAddressStore, + SignalExceptionAddressLoad, SignalExceptionSimulatorFault, + SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable): + Define. + + * interp.c, support.h: Use. + +Tue Oct 14 13:19:20 1997 Andrew Cagney + + * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename + to value_fpr / store_fpr. Add SD argument. + (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub, + Multiply, Divide, Recip, SquareRoot, Convert): Make global. + + * sim-main.h (ValueFPR, StoreFPR): Define. + +Tue Oct 14 13:06:55 1997 Andrew Cagney + + * interp.c (sim_engine_run): Check consistency between configure + WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN + and HASFPU. + + * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE. + (mips_fpu): Configure WITH_FLOATING_POINT. + (mips_endian): Configure WITH_TARGET_ENDIAN. + * configure: Update. + +Fri Oct 3 09:28:00 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Sep 29 14:45:00 1997 Bob Manson + + * configure: Regenerated. + +Fri Sep 26 12:48:18 1997 Mark Alexander + + * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB. + +Thu Sep 25 11:15:22 1997 Andrew Cagney + + * gencode.c (print_igen_insn_models): Assume certain architectures + include all mips* instructions. + (print_igen_insn_format): Use data_size==-1 as marker for MIPS16 + instruction. + + * Makefile.in (tmp.igen): Add target. Generate igen input from + gencode file. + + * gencode.c (FEATURE_IGEN): Define. + (main): Add --igen option. Generate output in igen format. + (process_instructions): Format output according to igen option. + (print_igen_insn_format): New function. + (print_igen_insn_models): New function. + (process_instructions): Only issue warnings and ignore + instructions when no FEATURE_IGEN. + +Wed Sep 24 17:38:57 1997 Andrew Cagney + + * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some + MIPS targets. + +Tue Sep 23 11:04:38 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Sep 23 10:19:51 1997 Andrew Cagney + + * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN, + SIM_RESERVED_BITS): Delete, moved to common. + (SIM_EXTRA_CFLAGS): Update. + +Mon Sep 22 11:46:20 1997 Andrew Cagney + + * configure.in: Configure non-strict memory alignment. + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Sep 19 17:45:25 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Sat Sep 20 14:07:28 1997 Gavin Koch + + * gencode.c (SDBBP,DERET): Added (3900) insns. + (RFE): Turn on for 3900. + * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added. + (dsstate): Made global. + (SUBTARGET_R3900): Added. + (CANCELDELAYSLOT): New. + (SignalException): Ignore SystemCall rather than ignore and + terminate. Add DebugBreakPoint handling. + (decode_coproc): New insns RFE, DERET; and new registers Debug + and DEPC protected by SUBTARGET_R3900. + (sim_engine_run): Use CANCELDELAYSLOT rather than clearing + bits explicitly. + * Makefile.in,configure.in: Add mips subtarget option. + * configure: Update. + +Fri Sep 19 09:33:27 1997 Gavin Koch + + * gencode.c: Add r3900 (tx39). + + +Tue Sep 16 15:52:04 1997 Gavin Koch + + * gencode.c (build_instruction): Don't need to subtract 4 for + JALR, just 2. + +Tue Sep 16 11:32:28 1997 Gavin Koch + + * interp.c: Correct some HASFPU problems. + +Mon Sep 15 17:36:15 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Sep 12 12:01:39 1997 Andrew Cagney + + * interp.c (mips_options): Fix samples option short form, should + be `x'. + +Thu Sep 11 09:35:29 1997 Andrew Cagney + + * interp.c (sim_info): Enable info code. Was just returning. + +Tue Sep 9 17:30:57 1997 Andrew Cagney + + * interp.c (decode_coproc): Clarify warning about unsuported MTC0, + MFC0. + +Tue Sep 9 16:28:28 1997 Andrew Cagney + + * gencode.c (build_instruction): Use SIGNED64 for 64 bit + constants. + (build_instruction): Ditto for LL. + +Thu Sep 4 17:21:23 1997 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Aug 27 18:13:22 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Wed Aug 27 14:12:27 1997 Andrew Cagney + + * interp.c (sim_open): Add call to sim_analyze_program, update + call to sim_config. + +Tue Aug 26 10:40:07 1997 Andrew Cagney + + * interp.c (sim_kill): Delete. + (sim_create_inferior): Add ABFD argument. Set PC from same. + (sim_load): Move code initializing trap handlers from here. + (sim_open): To here. + (sim_load): Delete, use sim-hload.c. + + * Makefile.in (SIM_OBJS): Add sim-hload.o module. + +Mon Aug 25 17:50:22 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Mon Aug 25 15:59:48 1997 Andrew Cagney + + * interp.c (sim_open): Add ABFD argument. + (sim_load): Move call to sim_config from here. + (sim_open): To here. Check return status. + +Fri Jul 25 15:00:45 1997 Gavin Koch + + * gencode.c (build_instruction): Two arg MADD should + not assign result to $0. + +Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com) + + * sim/mips/configure: Change default_sim_endian to 0 (bi-endian) + * sim/mips/configure.in: Regenerate. + +Wed Jul 9 10:29:21 1997 Andrew Cagney + + * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit + signed8, unsigned8 et.al. types. + + * interp.c (SUB_REG_FETCH): Handle both little and big endian + hosts when selecting subreg. + +Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com) + + * interp.c (sim_engine_run): Reset the ZERO register to zero + regardless of FEATURE_WARN_ZERO. + * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO. + +Wed Jun 4 10:43:14 1997 Andrew Cagney + + * interp.c (decode_coproc): Implement MTC0 N, CAUSE. + (SignalException): For BreakPoints ignore any mode bits and just + save the PC. + (SignalException): Always set the CAUSE register. + +Tue Jun 3 05:00:33 1997 Andrew Cagney + + * interp.c (SignalException): Clear the simDELAYSLOT flag when an + exception has been taken. + + * interp.c: Implement the ERET and mt/f sr instructions. + +Sat May 31 00:44:16 1997 Andrew Cagney + + * interp.c (SignalException): Don't bother restarting an + interrupt. + +Fri May 30 23:41:48 1997 Andrew Cagney + + * interp.c (SignalException): Really take an interrupt. + (interrupt_event): Only deliver interrupts when enabled. + +Tue May 27 20:08:06 1997 Andrew Cagney + + * interp.c (sim_info): Only print info when verbose. + (sim_info) Use sim_io_printf for output. + +Tue May 27 14:22:23 1997 Andrew Cagney + + * interp.c (CoProcPresent): Add UNUSED attribute - not used by all + mips architectures. + +Tue May 27 14:22:23 1997 Andrew Cagney + + * interp.c (sim_do_command): Check for common commands if a + simulator specific command fails. + +Thu May 22 09:32:03 1997 Gavin Koch + + * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP + and simBE when DEBUG is defined. + +Wed May 21 09:08:10 1997 Andrew Cagney + + * interp.c (interrupt_event): New function. Pass exception event + onto exception handler. + + * configure.in: Check for stdlib.h. + * configure: Regenerate. + + * gencode.c (build_instruction): Add UNUSED attribute to tempS + variable declaration. + (build_instruction): Initialize memval1. + (build_instruction): Add UNUSED attribute to byte, bigend, + reverse. + (build_operands): Ditto. + + * interp.c: Fix GCC warnings. + (sim_get_quit_code): Delete. + + * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS. + * Makefile.in: Ditto. + * configure: Re-generate. + + * Makefile.in (SIM_OBJS): Add sim-watch.o module. + +Tue May 20 15:08:56 1997 Andrew Cagney + + * interp.c (mips_option_handler): New function parse argumes using + sim-options. + (myname): Replace with STATE_MY_NAME. + (sim_open): Delete check for host endianness - performed by + sim_config. + (simHOSTBE, simBE): Delete, replaced by sim-endian flags. + (sim_open): Move much of the initialization from here. + (sim_load): To here. After the image has been loaded and + endianness set. + (sim_open): Move ColdReset from here. + (sim_create_inferior): To here. + (sim_open): Make FP check less dependant on host endianness. + + * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or + run. + * interp.c (sim_set_callbacks): Delete. + + * interp.c (membank, membank_base, membank_size): Replace with + STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE. + (sim_open): Remove call to callback->init. gdb/run do this. + + * interp.c: Update + + * sim-main.h (SIM_HAVE_FLATMEM): Define. + + * interp.c (big_endian_p): Delete, replaced by + current_target_byte_order. + +Tue May 20 13:55:00 1997 Andrew Cagney + + * interp.c (host_read_long, host_read_word, host_swap_word, + host_swap_long): Delete. Using common sim-endian. + (sim_fetch_register, sim_store_register): Use H2T. + (pipeline_ticks): Delete. Handled by sim-events. + (sim_info): Update. + (sim_engine_run): Update. + +Tue May 20 13:42:03 1997 Andrew Cagney + + * interp.c (sim_stop_reason): Move code determining simEXCEPTION + reason from here. + (SignalException): To here. Signal using sim_engine_halt. + (sim_stop_reason): Delete, moved to common. + +Tue May 20 10:19:48 1997 Andrew Cagney + + * interp.c (sim_open): Add callback argument. + (sim_set_callbacks): Delete SIM_DESC argument. + (sim_size): Ditto. + +Mon May 19 18:20:38 1997 Andrew Cagney + + * Makefile.in (SIM_OBJS): Add common modules. + + * interp.c (sim_set_callbacks): Also set SD callback. + (set_endianness, xfer_*, swap_*): Delete. + (host_read_word, host_read_long, host_swap_word, host_swap_long): + Change to functions using sim-endian macros. + (control_c, sim_stop): Delete, use common version. + (simulate): Convert into. + (sim_engine_run): This function. + (sim_resume): Delete. + + * interp.c (simulation): New variable - the simulator object. + (sim_kind): Delete global - merged into simulation. + (sim_load): Cleanup. Move PC assignment from here. + (sim_create_inferior): To here. + + * sim-main.h: New file. + * interp.c (sim-main.h): Include. + +Thu Apr 24 00:39:51 1997 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Apr 23 17:32:19 1997 Doug Evans + + * tconfig.in (SIM_HAVE_BIENDIAN): Define. + +Mon Apr 21 17:16:13 1997 Gavin Koch + + * gencode.c (build_instruction): DIV instructions: check + for division by zero and integer overflow before using + host's division operation. + +Thu Apr 17 03:18:14 1997 Doug Evans + + * Makefile.in (SIM_OBJS): Add sim-load.o. + * interp.c: #include bfd.h. + (target_byte_order): Delete. + (sim_kind, myname, big_endian_p): New static locals. + (sim_open): Set sim_kind, myname. Move call to set_endianness to + after argument parsing. Recognize -E arg, set endianness accordingly. + (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to + load file into simulator. Set PC from bfd. + (sim_create_inferior): Return SIM_RC. Delete arg start_address. + (set_endianness): Use big_endian_p instead of target_byte_order. + +Wed Apr 16 17:55:37 1997 Andrew Cagney + + * interp.c (sim_size): Delete prototype - conflicts with + definition in remote-sim.h. Correct definition. + +Mon Apr 7 15:45:02 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Wed Apr 2 15:06:28 1997 Doug Evans + + * interp.c (sim_open): New arg `kind'. + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Apr 2 14:34:19 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Mar 25 11:38:22 1997 Doug Evans + + * interp.c (sim_open): Set optind to 0 before calling getopt. + +Wed Mar 19 01:14:00 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Mar 17 10:52:59 1997 Gavin Koch + + * interp.c : Replace uses of pr_addr with pr_uword64 + where the bit length is always 64 independent of SIM_ADDR. + (pr_uword64) : added. + +Mon Mar 17 15:10:07 1997 Andrew Cagney + + * configure: Re-generate. + +Fri Mar 14 10:34:11 1997 Michael Meissner + + * configure: Regenerate to track ../common/aclocal.m4 changes. + +Thu Mar 13 12:51:36 1997 Doug Evans + + * interp.c (sim_open): New SIM_DESC result. Argument is now + in argv form. + (other sim_*): New SIM_DESC argument. + +Mon Feb 24 22:47:14 1997 Dawn Perchik + + * interp.c: Fix printing of addresses for non-64-bit targets. + (pr_addr): Add function to print address based on size. + +Wed Feb 19 14:42:09 1997 Mark Alexander + + * interp.c (simopen): Add support for LSI MiniRISC PMON vectors. + +Thu Feb 13 14:08:30 1997 Ian Lance Taylor + + * gencode.c (build_mips16_operands): Correct computation of base + address for extended PC relative instruction. + +Thu Feb 6 17:16:15 1997 Ian Lance Taylor + + * interp.c (mips16_entry): Add support for floating point cases. + (SignalException): Pass floating point cases to mips16_entry. + (ValueFPR): Don't restrict fmt_single and fmt_word to even + registers. + (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single + or fmt_word. + (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, + and then set the state to fmt_uninterpreted. + (COP_SW): Temporarily set the state to fmt_word while calling + ValueFPR. + +Tue Feb 4 16:48:25 1997 Ian Lance Taylor + + * gencode.c (build_instruction): The high order may be set in the + comparison flags at any ISA level, not just ISA 4. + +Tue Feb 4 13:33:30 1997 Doug Evans + + * Makefile.in (@COMMON_MAKEFILE_FRAG): Use + COMMON_{PRE,POST}_CONFIG_FRAG instead. + * configure.in: sinclude ../common/aclocal.m4. + * configure: Regenerated. + +Fri Jan 31 11:11:45 1997 Ian Lance Taylor + + * configure: Rebuild after change to aclocal.m4. + +Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com) + + * configure configure.in Makefile.in: Update to new configure + scheme which is more compatible with WinGDB builds. + * configure.in: Improve comment on how to run autoconf. + * configure: Re-run autoconf to get new ../common/aclocal.m4. + * Makefile.in: Use autoconf substitution to install common + makefile fragment. + +Wed Jan 8 12:39:03 1997 Jim Wilson + + * gencode.c (build_instruction): Use BigEndianCPU instead of + ByteSwapMem. + +Thu Jan 02 22:23:04 1997 Mark Alexander + + * interp.c (sim_monitor): Make output to stdout visible in + wingdb's I/O log window. + +Tue Dec 31 07:04:00 1996 Mark Alexander + + * support.h: Undo previous change to SIGTRAP + and SIGQUIT values. + +Mon Dec 30 17:36:06 1996 Ian Lance Taylor + + * interp.c (store_word, load_word): New static functions. + (mips16_entry): New static function. + (SignalException): Look for mips16 entry and exit instructions. + (simulate): Use the correct index when setting fpr_state after + doing a pending move. + +Sun Dec 29 09:37:18 1996 Mark Alexander + + * interp.c: Fix byte-swapping code throughout to work on + both little- and big-endian hosts. + +Sun Dec 29 09:18:32 1996 Mark Alexander + + * support.h: Make definitions of SIGTRAP and SIGQUIT consistent + with gdb/config/i386/xm-windows.h. + +Fri Dec 27 22:48:51 1996 Mark Alexander + + * gencode.c (build_instruction): Work around MSVC++ code gen bug + that messes up arithmetic shifts. + +Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com) + + * support.h: Use _WIN32 instead of __WIN32__. Also add defs for + SIGTRAP and SIGQUIT for _WIN32. + +Thu Dec 19 14:07:27 1996 Ian Lance Taylor + + * gencode.c (build_instruction) [MUL]: Cast operands to word64, to + force a 64 bit multiplication. + (build_instruction) [OR]: In mips16 mode, don't do anything if the + destination register is 0, since that is the default mips16 nop + instruction. + +Mon Dec 16 14:59:38 1996 Ian Lance Taylor + + * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI. + (build_endian_shift): Don't check proc64. + (build_instruction): Always set memval to uword64. Cast op2 to + uword64 when shifting it left in memory instructions. Always use + the same code for stores--don't special case proc64. + + * gencode.c (build_mips16_operands): Fix base PC value for PC + relative operands. + (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a + jal instruction. + * interp.c (simJALDELAYSLOT): Define. + (JALDELAYSLOT): Define. + (INDELAYSLOT, INJALDELAYSLOT): Define. + (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared. + +Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com) + + * interp.c (sim_open): add flush_cache as a PMON routine + (sim_monitor): handle flush_cache by ignoring it + +Wed Dec 11 13:53:51 1996 Jim Wilson + + * gencode.c (build_instruction): Use !ByteSwapMem instead of + BigEndianMem. + * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete. + (BigEndianMem): Rename to ByteSwapMem and change sense. + (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change + BigEndianMem references to !ByteSwapMem. + (set_endianness): New function, with prototype. + (sim_open): Call set_endianness. + (sim_info): Use simBE instead of BigEndianMem. + (xfer_direct_word, xfer_direct_long, swap_direct_word, + swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word, + xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER + ifdefs, keeping the prototype declaration. + (swap_word): Rewrite correctly. + (ColdReset): Delete references to CONFIG. Delete endianness related + code; moved to set_endianness. + +Tue Dec 10 11:32:04 1996 Jim Wilson + + * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits. + * interp.c (CHECKHILO): Define away. + (simSIGINT): New macro. + (membank_size): Increase from 1MB to 2MB. + (control_c): New function. + (sim_resume): Rename parameter signal to signal_number. Add local + variable prev. Call signal before and after simulate. + (sim_stop_reason): Add simSIGINT support. + (sim_warning, sim_error, dotrace, SignalException): Define as stdarg + functions always. + (sim_warning): Delete call to SignalException. Do call printf_filtered + if logfh is NULL. + (AddressTranslation): Add #ifdef DEBUG around debugging message and + a call to sim_warning. + +Wed Nov 27 11:53:50 1996 Ian Lance Taylor + + * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD + 16 bit instructions. + +Tue Nov 26 11:53:12 1996 Ian Lance Taylor + + Add support for mips16 (16 bit MIPS implementation): + * gencode.c (inst_type): Add mips16 instruction encoding types. + (GETDATASIZEINSN): Define. + (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add + jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and + mtlo. + (MIPS16_DECODE): New table, for mips16 instructions. + (bitmap_val): New static function. + (struct mips16_op): Define. + (mips16_op_table): New table, for mips16 operands. + (build_mips16_operands): New static function. + (process_instructions): If PC is odd, decode a mips16 + instruction. Break out instruction handling into new + build_instruction function. + (build_instruction): New static function, broken out of + process_instructions. Check modifiers rather than flags for SHIFT + bit count and m[ft]{hi,lo} direction. + (usage): Pass program name to fprintf. + (main): Remove unused variable this_option_optind. Change + ``*loptarg++'' to ``loptarg++''. + (my_strtoul): Parenthesize && within ||. + * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd. + (simulate): If PC is odd, fetch a 16 bit instruction, and + increment PC by 2 rather than 4. + * configure.in: Add case for mips16*-*-*. + * configure: Rebuild. + +Fri Nov 22 08:49:36 1996 Mark Alexander + + * interp.c: Allow -t to enable tracing in standalone simulator. + Fix garbage output in trace file and error messages. + +Wed Nov 20 01:54:37 1996 Doug Evans + + * Makefile.in: Delete stuff moved to ../common/Make-common.in. + (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define. + * configure.in: Simplify using macros in ../common/aclocal.m4. + * configure: Regenerated. + * tconfig.in: New file. + +Tue Nov 12 13:34:00 1996 Dawn Perchik + + * interp.c: Fix bugs in 64-bit port. + Use ansi function declarations for msvc compiler. + Initialize and test file pointer in trace code. + Prevent duplicate definition of LAST_EMED_REGNUM. + +Tue Oct 15 11:07:06 1996 Mark Alexander + + * interp.c (xfer_big_long): Prevent unwanted sign extension. + +Thu Sep 26 17:35:00 1996 James G. Smith + + * interp.c (SignalException): Check for explicit terminating + breakpoint value. + * gencode.c: Pass instruction value through SignalException() + calls for Trap, Breakpoint and Syscall. + +Thu Sep 26 11:35:17 1996 James G. Smith + + * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is + only used on those hosts that provide it. + * configure.in: Add sqrt() to list of functions to be checked for. + * config.in: Re-generated. + * configure: Re-generated. + +Fri Sep 20 15:47:12 1996 Ian Lance Taylor + + * gencode.c (process_instructions): Call build_endian_shift when + expanding STORE RIGHT, to fix swr. + * support.h (SIGNEXTEND): If the sign bit is not set, explicitly + clear the high bits. + * interp.c (Convert): Fix fmt_single to fmt_long to not truncate. + Fix float to int conversions to produce signed values. + +Thu Sep 19 15:34:17 1996 Ian Lance Taylor + + * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction. + (process_instructions): Correct handling of nor instruction. + Correct shift count for 32 bit shift instructions. Correct sign + extension for arithmetic shifts to not shift the number of bits in + the type. Fix 64 bit multiply high word calculation. Fix 32 bit + unsigned multiply. Fix ldxc1 and friends to use coprocessor 1. + Fix madd. + * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC. + It's OK to have a mult follow a mult. What's not OK is to have a + mult follow an mfhi. + (Convert): Comment out incorrect rounding code. + +Mon Sep 16 11:38:16 1996 James G. Smith + + * interp.c (sim_monitor): Improved monitor printf + simulation. Tidied up simulator warnings, and added "--log" option + for directing warning message output. + * gencode.c: Use sim_warning() rather than WARNING macro. + +Thu Aug 22 15:03:12 1996 Ian Lance Taylor + + * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and + getopt1.o, rather than on gencode.c. Link objects together. + Don't link against -liberty. + (gencode.o, getopt.o, getopt1.o): New targets. + * gencode.c: Include and "ansidecl.h". + (AND): Undefine after including "ansidecl.h". + (ULONG_MAX): Define if not defined. + (OP_*): Don't define macros; now defined in opcode/mips.h. + (main): Call my_strtoul rather than strtoul. + (my_strtoul): New static function. + +Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com) + + * gencode.c (process_instructions): Generate word64 and uword64 + instead of `long long' and `unsigned long long' data types. + * interp.c: #include sysdep.h to get signals, and define default + for SIGBUS. + * (Convert): Work around for Visual-C++ compiler bug with type + conversion. + * support.h: Make things compile under Visual-C++ by using + __int64 instead of `long long'. Change many refs to long long + into word64/uword64 typedefs. + +Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) + + * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir, + INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values. + (docdir): Removed. + * configure.in (AC_PREREQ): autoconf 2.5 or higher. + (AC_PROG_INSTALL): Added. + (AC_PROG_CC): Moved to before configure.host call. + * configure: Rebuilt. + +Wed Jun 5 08:28:13 1996 James G. Smith + + * configure.in: Define @SIMCONF@ depending on mips target. + * configure: Rebuild. + * Makefile.in (run): Add @SIMCONF@ to control simulator + construction. + * gencode.c: Change LOADDRMASK to 64bit memory model only. + * interp.c: Remove some debugging, provide more detailed error + messages, update memory accesses to use LOADDRMASK. + +Mon Jun 3 11:55:03 1996 Ian Lance Taylor + + * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS, + AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set + stamp-h. + * configure: Rebuild. + * config.in: New file, generated by autoheader. + * interp.c: Include "config.h". Include , , + and if they exist. Replace #ifdef sun with #ifdef + HAVE_ANINT and HAVE_AINT, as appropriate. + * Makefile.in (run): Use @LIBS@ rather than -lm. + (interp.o): Depend upon config.h. + (Makefile): Just rebuild Makefile. + (clean): Remove stamp-h. + (mostlyclean): Make the same as clean, not as distclean. + (config.h, stamp-h): New targets. + +Fri May 10 00:41:17 1996 James G. Smith + + * interp.c (ColdReset): Fix boolean test. Make all simulator + globals static. + +Wed May 8 15:12:58 1996 James G. Smith + + * interp.c (xfer_direct_word, xfer_direct_long, + swap_direct_word, swap_direct_long, xfer_big_word, + xfer_big_long, xfer_little_word, xfer_little_long, + swap_word,swap_long): Added. + * interp.c (ColdReset): Provide function indirection to + host<->simulated_target transfer routines. + * interp.c (sim_store_register, sim_fetch_register): Updated to + make use of indirected transfer routines. + +Fri Apr 19 15:48:24 1996 James G. Smith + + * gencode.c (process_instructions): Ensure FP ABS instruction + recognised. + * interp.c (AbsoluteValue): Add routine. Also provide simple PMON + system call support. + +Wed Apr 10 09:51:38 1996 James G. Smith + + * interp.c (sim_do_command): Complain if callback structure not + initialised. + +Thu Mar 28 13:50:51 1996 James G. Smith + + * interp.c (Convert): Provide round-to-nearest and round-to-zero + support for Sun hosts. + * Makefile.in (gencode): Ensure the host compiler and libraries + used for cross-hosted build. + +Wed Mar 27 14:42:12 1996 James G. Smith + + * interp.c, gencode.c: Some more (TODO) tidying. + +Thu Mar 7 11:19:33 1996 James G. Smith + + * gencode.c, interp.c: Replaced explicit long long references with + WORD64HI, WORD64LO, SET64HI and SET64LO macro calls. + * support.h (SET64LO, SET64HI): Macros added. + +Wed Feb 21 12:16:21 1996 Ian Lance Taylor + + * configure: Regenerate with autoconf 2.7. + +Tue Jan 30 08:48:18 1996 Fred Fish + + * interp.c (LoadMemory): Enclose text following #endif in /* */. + * support.h: Remove superfluous "1" from #if. + * support.h (CHECKSIM): Remove stray 'a' at end of line. + +Mon Dec 4 11:44:40 1995 Jamie Smith + + * interp.c (StoreFPR): Control UndefinedResult() call on + WARN_RESULT manifest. + +Fri Dec 1 16:37:19 1995 James G. Smith + + * gencode.c: Tidied instruction decoding, and added FP instruction + support. + + * interp.c: Added dineroIII, and BSD profiling support. Also + run-time FP handling. + +Sun Oct 22 00:57:18 1995 James G. Smith + + * Changelog, Makefile.in, README.Cygnus, configure, configure.in, + gencode.c, interp.c, support.h: created.
ChangeLog Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: m16.dc =================================================================== --- m16.dc (nonexistent) +++ m16.dc (revision 33) @@ -0,0 +1,25 @@ +# most instructions +# ------ options ------ : Fst : Lst : ff : fl : fe : word : --- fmt --- : model ... +# { : mask : value : word } + +# Top level - create a very big switch statement. + + padded-switch,combine : 15 : 11 : : : : : : + + switch,combine : 10 : 8 : : : : : : + + switch,combine : 4 : 0 : : : : : : + + switch,combine : 7 : 5 : : : : : : + + +# Extended instructions, decode the same way + + padded-switch,combine : 15 : 11 : : : : 1 : : + + switch,combine : 10 : 8 : : : : 1 : : + + switch,combine : 4 : 0 : : : : 1 : : + + switch,combine : 7 : 5 : : : : 1 : : + Index: m16e.igen =================================================================== --- m16e.igen (nonexistent) +++ m16e.igen (revision 33) @@ -0,0 +1,368 @@ +// -*- C -*- + +// Simulator definition for the MIPS16e instructions. +// Copyright (C) 2005 Free Software Foundation, Inc. +// Contributed by Nigel Stephens (nigel@mips.com) and +// David Ung (davidu@mips.com) of MIPS Technologies. +// +// This file is part of GDB, the GNU debugger. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + + +11101,3.RX,100,10001:RR:16::SEB +"seb r" +*mips16e: +{ + TRACE_ALU_INPUT1 (GPR[TRX]); + GPR[TRX] = EXTEND8 (GPR[TRX]); + TRACE_ALU_RESULT (GPR[TRX]); +} + + +11101,3.RX,101,10001:RR:16::SEH +"seh r" +*mips16e: +{ + TRACE_ALU_INPUT1 (GPR[TRX]); + GPR[TRX] = EXTEND16 (GPR[TRX]); + TRACE_ALU_RESULT (GPR[TRX]); +} + +11101,3.RX,110,10001:RR:16::SEW +"sew r" +*mips16e: +{ + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT1 (GPR[TRX]); + GPR[TRX] = EXTEND32 (GPR[TRX]); + TRACE_ALU_RESULT (GPR[TRX]); +} + +11101,3.RX,000,10001:RR:16::ZEB +"zeb r" +*mips16e: +{ + TRACE_ALU_INPUT1 (GPR[TRX]); + GPR[TRX] = (unsigned_word)(unsigned8)(GPR[TRX]); + TRACE_ALU_RESULT (GPR[TRX]); +} + +11101,3.RX,001,10001:RR:16::ZEH +"zeh r" +*mips16e: +{ + TRACE_ALU_INPUT1 (GPR[TRX]); + GPR[TRX] = (unsigned_word)(unsigned16)(GPR[TRX]); + TRACE_ALU_RESULT (GPR[TRX]); +} + +11101,3.RX,010,10001:RR:16::ZEW +"zew r" +*mips16e: +{ + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT1 (GPR[TRX]); + GPR[TRX] = (unsigned_word)(unsigned32)(GPR[TRX]); + TRACE_ALU_RESULT (GPR[TRX]); +} + + +11101,3.RX,100,00000:RR:16::JRC +"jrc r" +*mips16e: +{ + NIA = GPR[TRX]; +} + + +11101,000,101,00000:RR:16::JRCRA +"jrc ra" +*mips16e: +{ + NIA = RA; +} + + +11101,3.RX,110,00000:RR:16::JALRC +"jalrc r" +*mips16e: +{ + RA = NIA; + NIA = GPR[TRX]; +} + + +// format routines for save/restore +:%s::::RAS:int ras +*mips16e +{ + static char buf[10]; + buf[0] = '\0'; + if (ras & 4) + strcat (buf,"ra,"); + if (ras & 2) + strcat (buf,"s0,"); + if (ras & 1) + strcat (buf,"s1,"); + return (buf); +} + +:%s::::XSREGS:int xsregs +*mips16e +{ + if (xsregs > 6) + return "s2,s3,s4,s5,s6,s7,s8,"; + if (xsregs > 5) + return "s2,s3,s4,s5,s6,s7,"; + if (xsregs > 4) + return "s2,s3,s4,s5,s6,"; + if (xsregs > 3) + return "s2,s3,s4,s5,"; + if (xsregs > 2) + return "s2,s3,s4,"; + if (xsregs > 1) + return "s2,s3,"; + if (xsregs > 0) + return "s2,"; + return ""; +} + +:%s::::AREGS:int aregs +*mips16e +{ + // Fixme: how is the arg/static distinction made by the assembler? + static const char * const aregstr[16] = { + "", + "A3,", + "A2,A3,", + "A1,A2,A3,", + "A0,A1,A2,A3,", + "a0,", + "a0,A3,", + "a0,A2,A3,", + "a0,A1,A2,A3,", + "a0,a1,", + "a0,a1,A3,", + "a0,a1,A2,A3,", + "a0,a1,a2,", + "a0,a1,a2,A3,", + "?," + }; + return aregstr[aregs]; +} + +:compute:::int:SFRAME:FS:((FS == 0) ? 128 \: (FS << 3)) +:compute:::int:BFRAME:FSHI,FSLO:(((FSHI << 4) | FSLO) << 3) + +:function:::void:do_save:int xsregs, int aregs, int ras0s1, int framesize +{ + unsigned_word temp; + int args, astatic; + + temp = GPR[29]; + + /* writes are in the same order as the hardware description... */ + switch (aregs) { + case 0: case 1: case 2: case 3: case 11: + args = 0; + break; + case 4: case 5: case 6: case 7: + args = 1; + break; + case 8: case 9: case 10: + args = 2; + break; + case 12: case 13: + args = 3; + break; + case 14: + args = 4; + break; + default: + sim_engine_abort (SD, CPU, CIA, "save: aregs=%d causes unpredictable results\n", aregs); + } + if (args > 0) { + do_store (SD_, AccessLength_WORD, temp, 0, GPR[4]); + if (args > 1) { + do_store (SD_,AccessLength_WORD, temp, 4 , GPR[5]); + if (args > 2) { + do_store (SD_,AccessLength_WORD, temp, 8 , GPR[6]); + if (args > 3) { + do_store (SD_,AccessLength_WORD, temp, 12, GPR[7]); + } + } + } + } + + if (ras0s1 & 4) + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[31]); + + switch (xsregs) { + case 7: + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[30]); + case 6: + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[23]); + case 5: + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[22]); + case 4: + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[21]); + case 3: + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[20]); + case 2: + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[19]); + case 1: + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[18]); + } + + if (ras0s1 & 1) + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[17]); + if (ras0s1 & 2) + do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[16]); + + switch (aregs) { + case 0: case 4: case 8: case 12: case 14: + astatic = 0; + break; + case 1: case 5: case 9: case 13: + astatic = 1; + break; + case 2: case 6: case 10: + astatic = 2; + break; + case 3: case 7: + astatic = 3; + break; + case 11: + astatic = 4; + break; + default: + sim_engine_abort (SD, CPU, CIA, "save: aregs=%d causes unpredictable results\n", aregs); + } + if (astatic > 0) { + do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[7]); + if (astatic > 1) { + do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[6]); + if (astatic > 2) { + do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[5]); + if (astatic > 3) { + do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[4]); + } + } + } + } + + GPR[29] -= framesize; +} + +01100,100,1,3.RAS,4.FS:I8:16::SAVE +"save %s," +*mips16e +{ + do_save (SD_, 0, 0, RAS, SFRAME); +} + + +11110,3.XSREGS,4.FSHI,4.AREGS + 01100,100,1,3.RAS,4.FSLO:EXT-I8:16::SAVE +"save %s%s%s" +*mips16e +{ + do_save (SD_, XSREGS, AREGS, RAS, BFRAME); +} + + +:function:::void:do_restore:int xsregs, int aregs, int ras0s1, int framesize +*mips16e +{ + unsigned_word temp, temp2; + int astatic; + + temp = GPR[29] + framesize; + temp2 = temp; + + /* reads are in the same order as the hardware description... */ + + if (ras0s1 & 4) + GPR[31] = EXTEND32 (do_load(SD_, AccessLength_WORD, temp -= 4, 0)); + + switch (xsregs) { + case 7: + GPR[30] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + case 6: + GPR[23] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + case 5: + GPR[22] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + case 4: + GPR[21] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + case 3: + GPR[20] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + case 2: + GPR[19] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + case 1: + GPR[18] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + } + + if (ras0s1 & 1) + GPR[17] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + if (ras0s1 & 2) + GPR[16] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + + switch (aregs) { + case 0: case 4: case 8: case 12: case 14: + astatic = 0; + break; + case 1: case 5: case 9: case 13: + astatic = 1; + break; + case 2: case 6: case 10: + astatic = 2; + break; + case 3: case 7: + astatic = 3; + break; + case 11: + astatic = 4; + break; + default: + sim_engine_abort (SD, CPU, CIA, "save: aregs=%d causes unpredictable results\n", aregs); + } + if (astatic > 0) { + GPR[7] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + if (astatic > 1) { + GPR[6] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + if (astatic > 2) { + GPR[5] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + if (astatic > 3) { + GPR[4] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0)); + } + } + } + } + + GPR[29] = temp2; +} + +01100,100,0,3.RAS,4.FS:I8:16::RESTORE +"restore %s," +*mips16e +{ + do_restore (SD_,0,0,RAS,SFRAME); +} + +11110,3.XSREGS,4.FSHI,4.AREGS + 01100,100,0,3.RAS,4.FSLO:EXT-I8:16::RESTORE +"restore %s%s%s" +*mips16e +{ + do_restore (SD_,XSREGS,AREGS,RAS,BFRAME); +} Index: mips.igen =================================================================== --- mips.igen (nonexistent) +++ mips.igen (revision 33) @@ -0,0 +1,5968 @@ +// -*- C -*- +// +// ::= +// { "+" } +// ":" +// ":" +// ":" +// ":" +// +// { } +// { } +// +// + + +// IGEN config - mips16 +// :option:16::insn-bit-size:16 +// :option:16::hi-bit-nr:15 +:option:16::insn-specifying-widths:true +:option:16::gen-delayed-branch:false + +// IGEN config - mips32/64.. +// :option:32::insn-bit-size:32 +// :option:32::hi-bit-nr:31 +:option:32::insn-specifying-widths:true +:option:32::gen-delayed-branch:false + + +// Generate separate simulators for each target +// :option:::multi-sim:true + + +// Models known by this simulator are defined below. +// +// When placing models in the instruction descriptions, please place +// them one per line, in the order given here. + +// MIPS ISAs: +// +// Instructions and related functions for these models are included in +// this file. +:model:::mipsI:mips3000: +:model:::mipsII:mips6000: +:model:::mipsIII:mips4000: +:model:::mipsIV:mips8000: +:model:::mipsV:mipsisaV: +:model:::mips32:mipsisa32: +:model:::mips32r2:mipsisa32r2: +:model:::mips64:mipsisa64: +:model:::mips64r2:mipsisa64r2: + +// Vendor ISAs: +// +// Standard MIPS ISA instructions used for these models are listed here, +// as are functions needed by those standard instructions. Instructions +// which are model-dependent and which are not in the standard MIPS ISAs +// (or which pre-date or use different encodings than the standard +// instructions) are (for the most part) in separate .igen files. +:model:::vr4100:mips4100: // vr.igen +:model:::vr4120:mips4120: +:model:::vr5000:mips5000: +:model:::vr5400:mips5400: +:model:::vr5500:mips5500: +:model:::r3900:mips3900: // tx.igen + +// MIPS Application Specific Extensions (ASEs) +// +// Instructions for the ASEs are in separate .igen files. +// ASEs add instructions on to a base ISA. +:model:::mips16:mips16: // m16.igen (and m16.dc) +:model:::mips16e:mips16e: // m16e.igen +:model:::mips3d:mips3d: // mips3d.igen +:model:::mdmx:mdmx: // mdmx.igen +:model:::dsp:dsp: // dsp.igen +:model:::dsp2:dsp2: // dsp2.igen +:model:::smartmips:smartmips: // smartmips.igen + +// Vendor Extensions +// +// Instructions specific to these extensions are in separate .igen files. +// Extensions add instructions on to a base ISA. +:model:::sb1:sb1: // sb1.igen + + +// Pseudo instructions known by IGEN +:internal::::illegal: +{ + SignalException (ReservedInstruction, 0); +} + + +// Pseudo instructions known by interp.c +// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK +000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD +"rsvd " +{ + SignalException (ReservedInstruction, instruction_0); +} + + + +// Helper: +// +// Simulate a 32 bit delayslot instruction +// + +:function:::address_word:delayslot32:address_word target +{ + instruction_word delay_insn; + sim_events_slip (SD, 1); + DSPC = CIA; + CIA = CIA + 4; /* NOTE not mips16 */ + STATE |= simDELAYSLOT; + delay_insn = IMEM32 (CIA); /* NOTE not mips16 */ + ENGINE_ISSUE_PREFIX_HOOK(); + idecode_issue (CPU_, delay_insn, (CIA)); + STATE &= ~simDELAYSLOT; + return target; +} + +:function:::address_word:nullify_next_insn32: +{ + sim_events_slip (SD, 1); + dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction"); + return CIA + 8; +} + + +// Helper: +// +// Calculate an effective address given a base and an offset. +// + +:function:::address_word:loadstore_ea:address_word base, address_word offset +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*vr4100: +*vr5000: +*r3900: +{ + return base + offset; +} + +:function:::address_word:loadstore_ea:address_word base, address_word offset +*mips64: +*mips64r2: +{ +#if 0 /* XXX FIXME: enable this only after some additional testing. */ + /* If in user mode and UX is not set, use 32-bit compatibility effective + address computations as defined in the MIPS64 Architecture for + Programmers Volume III, Revision 0.95, section 4.9. */ + if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX)) + == (ksu_user << status_KSU_shift)) + return (address_word)((signed32)base + (signed32)offset); +#endif + return base + offset; +} + + +// Helper: +// +// Check that a 32-bit register value is properly sign-extended. +// (See NotWordValue in ISA spec.) +// + +:function:::int:not_word_value:unsigned_word value +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*vr4100: +*vr5000: +*r3900: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +{ +#if WITH_TARGET_WORD_BITSIZE == 64 + return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); +#else + return 0; +#endif +} + +// Helper: +// +// Handle UNPREDICTABLE operation behaviour. The goal here is to prevent +// theoretically portable code which invokes non-portable behaviour from +// running with no indication of the portability issue. +// (See definition of UNPREDICTABLE in ISA spec.) +// + +:function:::void:unpredictable: +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*vr4100: +*vr5000: +*r3900: +{ +} + +:function:::void:unpredictable: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +{ + unpredictable_action (CPU, CIA); +} + + +// Helpers: +// +// Check that an access to a HI/LO register meets timing requirements +// +// In all MIPS ISAs, +// +// OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO}) +// makes subsequent MF{HI or LO} UNPREDICTABLE. (1) +// +// The following restrictions exist for MIPS I - MIPS III: +// +// MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions +// in between makes MF UNPREDICTABLE. (2) +// +// MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions +// in between makes MF UNPREDICTABLE. (3) +// +// On the r3900, restriction (2) is not present, and restriction (3) is not +// present for multiplication. +// +// Unfortunately, there seems to be some confusion about whether the last +// two restrictions should apply to "MIPS IV" as well. One edition of +// the MIPS IV ISA says they do, but references in later ISA documents +// suggest they don't. +// +// In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have +// these restrictions, while others, like the VR5500, don't. To accomodate +// such differences, the MIPS IV and MIPS V version of these helper functions +// use auxillary routines to determine whether the restriction applies. + +// check_mf_cycles: +// +// Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo +// to check for restrictions (2) and (3) above. +// +:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new +{ + if (history->mf.timestamp + 3 > time) + { + sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n", + itable[MY_INDEX].name, + new, (long) CIA, + (long) history->mf.cia); + return 0; + } + return 1; +} + + +// check_mt_hilo: +// +// Check for restriction (2) above (for ISAs/processors that have it), +// and record timestamps for restriction (1) above. +// +:function:::int:check_mt_hilo:hilo_history *history +*mipsI: +*mipsII: +*mipsIII: +*vr4100: +*vr5000: +{ + signed64 time = sim_events_time (SD); + int ok = check_mf_cycles (SD_, history, time, "MT"); + history->mt.timestamp = time; + history->mt.cia = CIA; + return ok; +} + +:function:::int:check_mt_hilo:hilo_history *history +*mipsIV: +*mipsV: +{ + signed64 time = sim_events_time (SD); + int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD) + || check_mf_cycles (SD_, history, time, "MT")); + history->mt.timestamp = time; + history->mt.cia = CIA; + return ok; +} + +:function:::int:check_mt_hilo:hilo_history *history +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*r3900: +{ + signed64 time = sim_events_time (SD); + history->mt.timestamp = time; + history->mt.cia = CIA; + return 1; +} + + +// check_mf_hilo: +// +// Check for restriction (1) above, and record timestamps for +// restriction (2) and (3) above. +// +:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + signed64 time = sim_events_time (SD); + int ok = 1; + if (peer != NULL + && peer->mt.timestamp > history->op.timestamp + && history->mt.timestamp < history->op.timestamp + && ! (history->mf.timestamp > history->op.timestamp + && history->mf.timestamp < peer->mt.timestamp) + && ! (peer->mf.timestamp > history->op.timestamp + && peer->mf.timestamp < peer->mt.timestamp)) + { + /* The peer has been written to since the last OP yet we have + not */ + sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n", + itable[MY_INDEX].name, + (long) CIA, + (long) history->op.cia, + (long) peer->mt.cia); + ok = 0; + } + history->mf.timestamp = time; + history->mf.cia = CIA; + return ok; +} + + + +// check_mult_hilo: +// +// Check for restriction (3) above (for ISAs/processors that have it) +// for MULT ops, and record timestamps for restriction (1) above. +// +:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo +*mipsI: +*mipsII: +*mipsIII: +*vr4100: +*vr5000: +{ + signed64 time = sim_events_time (SD); + int ok = (check_mf_cycles (SD_, hi, time, "OP") + && check_mf_cycles (SD_, lo, time, "OP")); + hi->op.timestamp = time; + lo->op.timestamp = time; + hi->op.cia = CIA; + lo->op.cia = CIA; + return ok; +} + +:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo +*mipsIV: +*mipsV: +{ + signed64 time = sim_events_time (SD); + int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD) + || (check_mf_cycles (SD_, hi, time, "OP") + && check_mf_cycles (SD_, lo, time, "OP"))); + hi->op.timestamp = time; + lo->op.timestamp = time; + hi->op.cia = CIA; + lo->op.cia = CIA; + return ok; +} + +:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*r3900: +{ + /* FIXME: could record the fact that a stall occured if we want */ + signed64 time = sim_events_time (SD); + hi->op.timestamp = time; + lo->op.timestamp = time; + hi->op.cia = CIA; + lo->op.cia = CIA; + return 1; +} + + +// check_div_hilo: +// +// Check for restriction (3) above (for ISAs/processors that have it) +// for DIV ops, and record timestamps for restriction (1) above. +// +:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo +*mipsI: +*mipsII: +*mipsIII: +*vr4100: +*vr5000: +*r3900: +{ + signed64 time = sim_events_time (SD); + int ok = (check_mf_cycles (SD_, hi, time, "OP") + && check_mf_cycles (SD_, lo, time, "OP")); + hi->op.timestamp = time; + lo->op.timestamp = time; + hi->op.cia = CIA; + lo->op.cia = CIA; + return ok; +} + +:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo +*mipsIV: +*mipsV: +{ + signed64 time = sim_events_time (SD); + int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD) + || (check_mf_cycles (SD_, hi, time, "OP") + && check_mf_cycles (SD_, lo, time, "OP"))); + hi->op.timestamp = time; + lo->op.timestamp = time; + hi->op.cia = CIA; + lo->op.cia = CIA; + return ok; +} + +:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo +*mips32: +*mips32r2: +*mips64: +*mips64r2: +{ + signed64 time = sim_events_time (SD); + hi->op.timestamp = time; + lo->op.timestamp = time; + hi->op.cia = CIA; + lo->op.cia = CIA; + return 1; +} + + +// Helper: +// +// Check that the 64-bit instruction can currently be used, and signal +// a ReservedInstruction exception if not. +// + +:function:::void:check_u64:instruction_word insn +*mipsIII: +*mipsIV: +*mipsV: +*vr4100: +*vr5000: +*vr5400: +*vr5500: +{ + // The check should be similar to mips64 for any with PX/UX bit equivalents. +} + +:function:::void:check_u64:instruction_word insn +*mips16e: +*mips64: +*mips64r2: +{ +#if 0 /* XXX FIXME: enable this only after some additional testing. */ + if (UserMode && (SR & (status_UX|status_PX)) == 0) + SignalException (ReservedInstruction, insn); +#endif +} + + + +// +// MIPS Architecture: +// +// CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2) +// + + + +000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD +"add r, r, r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + { + ALU32_BEGIN (GPR[RS]); + ALU32_ADD (GPR[RT]); + ALU32_END (GPR[RD]); /* This checks for overflow. */ + } + TRACE_ALU_RESULT (GPR[RD]); +} + + + +001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI +"addi r, r, " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + if (NotWordValue (GPR[RS])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE)); + { + ALU32_BEGIN (GPR[RS]); + ALU32_ADD (EXTEND16 (IMMEDIATE)); + ALU32_END (GPR[RT]); /* This checks for overflow. */ + } + TRACE_ALU_RESULT (GPR[RT]); +} + + + +:function:::void:do_addiu:int rs, int rt, unsigned16 immediate +{ + if (NotWordValue (GPR[rs])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); + GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate)); + TRACE_ALU_RESULT (GPR[rt]); +} + +001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU +"addiu r, r, " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_addiu (SD_, RS, RT, IMMEDIATE); +} + + + +:function:::void:do_addu:int rs, int rt, int rd +{ + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]); + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU +"addu r, r, r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_addu (SD_, RS, RT, RD); +} + + + +:function:::void:do_and:int rs, int rt, int rd +{ + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = GPR[rs] & GPR[rt]; + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND +"and r, r, r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_and (SD_, RS, RT, RD); +} + + + +001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI +"andi r, r, %#lx" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE); + GPR[RT] = GPR[RS] & IMMEDIATE; + TRACE_ALU_RESULT (GPR[RT]); +} + + + +000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ +"beq r, r, " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) + { + DELAY_SLOT (NIA + offset); + } +} + + + +010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL +"beql r, r, " +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) + { + DELAY_SLOT (NIA + offset); + } + else + NULLIFY_NEXT_INSTRUCTION (); +} + + + +000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ +"bgez r, " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + if ((signed_word) GPR[RS] >= 0) + { + DELAY_SLOT (NIA + offset); + } +} + + + +000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL +"bgezal r, " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + if (RS == 31) + Unpredictable (); + RA = (CIA + 8); + if ((signed_word) GPR[RS] >= 0) + { + DELAY_SLOT (NIA + offset); + } +} + + + +000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL +"bgezall r, " +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + if (RS == 31) + Unpredictable (); + RA = (CIA + 8); + /* NOTE: The branch occurs AFTER the next instruction has been + executed */ + if ((signed_word) GPR[RS] >= 0) + { + DELAY_SLOT (NIA + offset); + } + else + NULLIFY_NEXT_INSTRUCTION (); +} + + + +000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL +"bgezl r, " +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + if ((signed_word) GPR[RS] >= 0) + { + DELAY_SLOT (NIA + offset); + } + else + NULLIFY_NEXT_INSTRUCTION (); +} + + + +000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ +"bgtz r, " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + if ((signed_word) GPR[RS] > 0) + { + DELAY_SLOT (NIA + offset); + } +} + + + +010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL +"bgtzl r, " +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + /* NOTE: The branch occurs AFTER the next instruction has been + executed */ + if ((signed_word) GPR[RS] > 0) + { + DELAY_SLOT (NIA + offset); + } + else + NULLIFY_NEXT_INSTRUCTION (); +} + + + +000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ +"blez r, " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + /* NOTE: The branch occurs AFTER the next instruction has been + executed */ + if ((signed_word) GPR[RS] <= 0) + { + DELAY_SLOT (NIA + offset); + } +} + + + +010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL +"bgezl r, " +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + if ((signed_word) GPR[RS] <= 0) + { + DELAY_SLOT (NIA + offset); + } + else + NULLIFY_NEXT_INSTRUCTION (); +} + + + +000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ +"bltz r, " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + if ((signed_word) GPR[RS] < 0) + { + DELAY_SLOT (NIA + offset); + } +} + + + +000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL +"bltzal r, " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + if (RS == 31) + Unpredictable (); + RA = (CIA + 8); + /* NOTE: The branch occurs AFTER the next instruction has been + executed */ + if ((signed_word) GPR[RS] < 0) + { + DELAY_SLOT (NIA + offset); + } +} + + + +000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL +"bltzall r, " +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + if (RS == 31) + Unpredictable (); + RA = (CIA + 8); + if ((signed_word) GPR[RS] < 0) + { + DELAY_SLOT (NIA + offset); + } + else + NULLIFY_NEXT_INSTRUCTION (); +} + + + +000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL +"bltzl r, " +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + /* NOTE: The branch occurs AFTER the next instruction has been + executed */ + if ((signed_word) GPR[RS] < 0) + { + DELAY_SLOT (NIA + offset); + } + else + NULLIFY_NEXT_INSTRUCTION (); +} + + + +000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE +"bne r, r, " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) + { + DELAY_SLOT (NIA + offset); + } +} + + + +010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL +"bnel r, r, " +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) + { + DELAY_SLOT (NIA + offset); + } + else + NULLIFY_NEXT_INSTRUCTION (); +} + + + +000000,20.CODE,001101:SPECIAL:32::BREAK +"break %#lx" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + /* Check for some break instruction which are reserved for use by the simulator. */ + unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK; + if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) || + break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) + { + sim_engine_halt (SD, CPU, NULL, cia, + sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); + } + else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) || + break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) + { + if (STATE & simDELAYSLOT) + PC = cia - 4; /* reference the branch instruction */ + else + PC = cia; + SignalException (BreakPoint, instruction_0); + } + + else + { + /* If we get this far, we're not an instruction reserved by the sim. Raise + the exception. */ + SignalException (BreakPoint, instruction_0); + } +} + + + +011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO +"clo r, r" +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr5500: +{ + unsigned32 temp = GPR[RS]; + unsigned32 i, mask; + if (RT != RD) + Unpredictable (); + if (NotWordValue (GPR[RS])) + Unpredictable (); + TRACE_ALU_INPUT1 (GPR[RS]); + for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i) + { + if ((temp & mask) == 0) + break; + mask >>= 1; + } + GPR[RD] = EXTEND32 (i); + TRACE_ALU_RESULT (GPR[RD]); +} + + + +011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ +"clz r, r" +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr5500: +{ + unsigned32 temp = GPR[RS]; + unsigned32 i, mask; + if (RT != RD) + Unpredictable (); + if (NotWordValue (GPR[RS])) + Unpredictable (); + TRACE_ALU_INPUT1 (GPR[RS]); + for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i) + { + if ((temp & mask) != 0) + break; + mask >>= 1; + } + GPR[RD] = EXTEND32 (i); + TRACE_ALU_RESULT (GPR[RD]); +} + + + +000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD +"dadd r, r, r" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + { + ALU64_BEGIN (GPR[RS]); + ALU64_ADD (GPR[RT]); + ALU64_END (GPR[RD]); /* This checks for overflow. */ + } + TRACE_ALU_RESULT (GPR[RD]); +} + + + +011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI +"daddi r, r, " +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE)); + { + ALU64_BEGIN (GPR[RS]); + ALU64_ADD (EXTEND16 (IMMEDIATE)); + ALU64_END (GPR[RT]); /* This checks for overflow. */ + } + TRACE_ALU_RESULT (GPR[RT]); +} + + + +:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate +{ + TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); + GPR[rt] = GPR[rs] + EXTEND16 (immediate); + TRACE_ALU_RESULT (GPR[rt]); +} + +011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU +"daddiu r, r, " +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + do_daddiu (SD_, RS, RT, IMMEDIATE); +} + + + +:function:::void:do_daddu:int rs, int rt, int rd +{ + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = GPR[rs] + GPR[rt]; + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU +"daddu r, r, r" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + do_daddu (SD_, RS, RT, RD); +} + + + +011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO +"dclo r, r" +*mips64: +*mips64r2: +*vr5500: +{ + unsigned64 temp = GPR[RS]; + unsigned32 i; + unsigned64 mask; + check_u64 (SD_, instruction_0); + if (RT != RD) + Unpredictable (); + TRACE_ALU_INPUT1 (GPR[RS]); + for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i) + { + if ((temp & mask) == 0) + break; + mask >>= 1; + } + GPR[RD] = EXTEND32 (i); + TRACE_ALU_RESULT (GPR[RD]); +} + + + +011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ +"dclz r, r" +*mips64: +*mips64r2: +*vr5500: +{ + unsigned64 temp = GPR[RS]; + unsigned32 i; + unsigned64 mask; + check_u64 (SD_, instruction_0); + if (RT != RD) + Unpredictable (); + TRACE_ALU_INPUT1 (GPR[RS]); + for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i) + { + if ((temp & mask) != 0) + break; + mask >>= 1; + } + GPR[RD] = EXTEND32 (i); + TRACE_ALU_RESULT (GPR[RD]); +} + + + +:function:::void:do_ddiv:int rs, int rt +{ + check_div_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + { + signed64 n = GPR[rs]; + signed64 d = GPR[rt]; + signed64 hi; + signed64 lo; + if (d == 0) + { + lo = SIGNED64 (0x8000000000000000); + hi = 0; + } + else if (d == -1 && n == SIGNED64 (0x8000000000000000)) + { + lo = SIGNED64 (0x8000000000000000); + hi = 0; + } + else + { + lo = (n / d); + hi = (n % d); + } + HI = hi; + LO = lo; + } + TRACE_ALU_RESULT2 (HI, LO); +} + +000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV +"ddiv r, r" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + do_ddiv (SD_, RS, RT); +} + + + +:function:::void:do_ddivu:int rs, int rt +{ + check_div_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + { + unsigned64 n = GPR[rs]; + unsigned64 d = GPR[rt]; + unsigned64 hi; + unsigned64 lo; + if (d == 0) + { + lo = SIGNED64 (0x8000000000000000); + hi = 0; + } + else + { + lo = (n / d); + hi = (n % d); + } + HI = hi; + LO = lo; + } + TRACE_ALU_RESULT2 (HI, LO); +} + +000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU +"ddivu r, r" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + do_ddivu (SD_, RS, RT); +} + +:function:::void:do_div:int rs, int rt +{ + check_div_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + { + signed32 n = GPR[rs]; + signed32 d = GPR[rt]; + if (d == 0) + { + LO = EXTEND32 (0x80000000); + HI = EXTEND32 (0); + } + else if (n == SIGNED32 (0x80000000) && d == -1) + { + LO = EXTEND32 (0x80000000); + HI = EXTEND32 (0); + } + else + { + LO = EXTEND32 (n / d); + HI = EXTEND32 (n % d); + } + } + TRACE_ALU_RESULT2 (HI, LO); +} + +000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV +"div r, r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_div (SD_, RS, RT); +} + + + +:function:::void:do_divu:int rs, int rt +{ + check_div_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + { + unsigned32 n = GPR[rs]; + unsigned32 d = GPR[rt]; + if (d == 0) + { + LO = EXTEND32 (0x80000000); + HI = EXTEND32 (0); + } + else + { + LO = EXTEND32 (n / d); + HI = EXTEND32 (n % d); + } + } + TRACE_ALU_RESULT2 (HI, LO); +} + +000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU +"divu r, r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_divu (SD_, RS, RT); +} + + +:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p +{ + unsigned64 lo; + unsigned64 hi; + unsigned64 m00; + unsigned64 m01; + unsigned64 m10; + unsigned64 m11; + unsigned64 mid; + int sign; + unsigned64 op1 = GPR[rs]; + unsigned64 op2 = GPR[rt]; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + /* make signed multiply unsigned */ + sign = 0; + if (signed_p) + { + if ((signed64) op1 < 0) + { + op1 = - op1; + ++sign; + } + if ((signed64) op2 < 0) + { + op2 = - op2; + ++sign; + } + } + /* multiply out the 4 sub products */ + m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2)); + m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2)); + m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2)); + m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2)); + /* add the products */ + mid = ((unsigned64) VH4_8 (m00) + + (unsigned64) VL4_8 (m10) + + (unsigned64) VL4_8 (m01)); + lo = U8_4 (mid, m00); + hi = (m11 + + (unsigned64) VH4_8 (mid) + + (unsigned64) VH4_8 (m01) + + (unsigned64) VH4_8 (m10)); + /* fix the sign */ + if (sign & 1) + { + lo = -lo; + if (lo == 0) + hi = -hi; + else + hi = -hi - 1; + } + /* save the result HI/LO (and a gpr) */ + LO = lo; + HI = hi; + if (rd != 0) + GPR[rd] = lo; + TRACE_ALU_RESULT2 (HI, LO); +} + +:function:::void:do_dmult:int rs, int rt, int rd +{ + do_dmultx (SD_, rs, rt, rd, 1); +} + +000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT +"dmult r, r" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +{ + check_u64 (SD_, instruction_0); + do_dmult (SD_, RS, RT, 0); +} + +000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT +"dmult r, r":RD == 0 +"dmult r, r, r" +*vr5000: +{ + check_u64 (SD_, instruction_0); + do_dmult (SD_, RS, RT, RD); +} + + + +:function:::void:do_dmultu:int rs, int rt, int rd +{ + do_dmultx (SD_, rs, rt, rd, 0); +} + +000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU +"dmultu r, r" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +{ + check_u64 (SD_, instruction_0); + do_dmultu (SD_, RS, RT, 0); +} + +000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU +"dmultu r, r, r":RD == 0 +"dmultu r, r" +*vr5000: +{ + check_u64 (SD_, instruction_0); + do_dmultu (SD_, RS, RT, RD); +} + + +:function:::unsigned64:do_dror:unsigned64 x,unsigned64 y +{ + unsigned64 result; + + y &= 63; + TRACE_ALU_INPUT2 (x, y); + result = ROTR64 (x, y); + TRACE_ALU_RESULT (result); + return result; +} + +000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR +"dror r, r, " +*mips64r2: +*vr5400: +*vr5500: +{ + check_u64 (SD_, instruction_0); + GPR[RD] = do_dror (SD_, GPR[RT], SHIFT); +} + +000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32 +"dror32 r, r, " +*mips64r2: +*vr5400: +*vr5500: +{ + check_u64 (SD_, instruction_0); + GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32); +} + +000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV +"drorv r, r, r" +*mips64r2: +*vr5400: +*vr5500: +{ + check_u64 (SD_, instruction_0); + GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]); +} + + +:function:::void:do_dsll:int rt, int rd, int shift +{ + TRACE_ALU_INPUT2 (GPR[rt], shift); + GPR[rd] = GPR[rt] << shift; + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL +"dsll r, r, " +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + do_dsll (SD_, RT, RD, SHIFT); +} + + +000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32 +"dsll32 r, r, " +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + int s = 32 + SHIFT; + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT2 (GPR[RT], s); + GPR[RD] = GPR[RT] << s; + TRACE_ALU_RESULT (GPR[RD]); +} + +:function:::void:do_dsllv:int rs, int rt, int rd +{ + int s = MASKED64 (GPR[rs], 5, 0); + TRACE_ALU_INPUT2 (GPR[rt], s); + GPR[rd] = GPR[rt] << s; + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV +"dsllv r, r, r" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + do_dsllv (SD_, RS, RT, RD); +} + +:function:::void:do_dsra:int rt, int rd, int shift +{ + TRACE_ALU_INPUT2 (GPR[rt], shift); + GPR[rd] = ((signed64) GPR[rt]) >> shift; + TRACE_ALU_RESULT (GPR[rd]); +} + + +000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA +"dsra r, r, " +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + do_dsra (SD_, RT, RD, SHIFT); +} + + +000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32 +"dsra32 r, r, " +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + int s = 32 + SHIFT; + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT2 (GPR[RT], s); + GPR[RD] = ((signed64) GPR[RT]) >> s; + TRACE_ALU_RESULT (GPR[RD]); +} + + +:function:::void:do_dsrav:int rs, int rt, int rd +{ + int s = MASKED64 (GPR[rs], 5, 0); + TRACE_ALU_INPUT2 (GPR[rt], s); + GPR[rd] = ((signed64) GPR[rt]) >> s; + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV +"dsrav r, r, r" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + do_dsrav (SD_, RS, RT, RD); +} + +:function:::void:do_dsrl:int rt, int rd, int shift +{ + TRACE_ALU_INPUT2 (GPR[rt], shift); + GPR[rd] = (unsigned64) GPR[rt] >> shift; + TRACE_ALU_RESULT (GPR[rd]); +} + + +000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL +"dsrl r, r, " +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + do_dsrl (SD_, RT, RD, SHIFT); +} + + +000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32 +"dsrl32 r, r, " +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + int s = 32 + SHIFT; + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT2 (GPR[RT], s); + GPR[RD] = (unsigned64) GPR[RT] >> s; + TRACE_ALU_RESULT (GPR[RD]); +} + + +:function:::void:do_dsrlv:int rs, int rt, int rd +{ + int s = MASKED64 (GPR[rs], 5, 0); + TRACE_ALU_INPUT2 (GPR[rt], s); + GPR[rd] = (unsigned64) GPR[rt] >> s; + TRACE_ALU_RESULT (GPR[rd]); +} + + + +000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV +"dsrlv r, r, r" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + do_dsrlv (SD_, RS, RT, RD); +} + + +000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB +"dsub r, r, r" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + { + ALU64_BEGIN (GPR[RS]); + ALU64_SUB (GPR[RT]); + ALU64_END (GPR[RD]); /* This checks for overflow. */ + } + TRACE_ALU_RESULT (GPR[RD]); +} + + +:function:::void:do_dsubu:int rs, int rt, int rd +{ + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = GPR[rs] - GPR[rt]; + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU +"dsubu r, r, r" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + do_dsubu (SD_, RS, RT, RD); +} + + +000010,26.INSTR_INDEX:NORMAL:32::J +"j " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + /* NOTE: The region used is that of the delay slot NIA and NOT the + current instruction */ + address_word region = (NIA & MASK (63, 28)); + DELAY_SLOT (region | (INSTR_INDEX << 2)); +} + + +000011,26.INSTR_INDEX:NORMAL:32::JAL +"jal " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + /* NOTE: The region used is that of the delay slot and NOT the + current instruction */ + address_word region = (NIA & MASK (63, 28)); + GPR[31] = CIA + 8; + DELAY_SLOT (region | (INSTR_INDEX << 2)); +} + +000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR +"jalr r":RD == 31 +"jalr r, r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + address_word temp = GPR[RS]; + GPR[RD] = CIA + 8; + DELAY_SLOT (temp); +} + +000000,5.RS,00000,5.RD,10000,001001:SPECIAL:32::JALR_HB +"jalr.hb r":RD == 31 +"jalr.hb r, r" +*mips32r2: +*mips64r2: +{ + address_word temp = GPR[RS]; + GPR[RD] = CIA + 8; + DELAY_SLOT (temp); +} + +000000,5.RS,0000000000,00000,001000:SPECIAL:32::JR +"jr r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + DELAY_SLOT (GPR[RS]); +} + +000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB +"jr.hb r" +*mips32r2: +*mips64r2: +{ + DELAY_SLOT (GPR[RS]); +} + +:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset +{ + address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); + address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); + unsigned int byte; + address_word paddr; + int uncached; + unsigned64 memval; + address_word vaddr; + + vaddr = loadstore_ea (SD_, base, offset); + if ((vaddr & access) != 0) + { + SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal); + } + AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); + paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); + LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL); + byte = ((vaddr & mask) ^ bigendiancpu); + return (memval >> (8 * byte)); +} + +:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt +{ + address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = (ReverseEndian ? -1 : 0); + address_word bigendiancpu = (BigEndianCPU ? -1 : 0); + unsigned int byte; + unsigned int word; + address_word paddr; + int uncached; + unsigned64 memval; + address_word vaddr; + int nr_lhs_bits; + int nr_rhs_bits; + unsigned_word lhs_mask; + unsigned_word temp; + + vaddr = loadstore_ea (SD_, base, offset); + AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); + paddr = (paddr ^ (reverseendian & mask)); + if (BigEndianMem == 0) + paddr = paddr & ~access; + + /* compute where within the word/mem we are */ + byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */ + word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */ + nr_lhs_bits = 8 * byte + 8; + nr_rhs_bits = 8 * access - 8 * byte; + /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ + + /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", + (long) ((unsigned64) vaddr >> 32), (long) vaddr, + (long) ((unsigned64) paddr >> 32), (long) paddr, + word, byte, nr_lhs_bits, nr_rhs_bits); */ + + LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL); + if (word == 0) + { + /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */ + temp = (memval << nr_rhs_bits); + } + else + { + /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */ + temp = (memval >> nr_lhs_bits); + } + lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits); + rt = (rt & ~lhs_mask) | (temp & lhs_mask); + + /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n", + (long) ((unsigned64) memval >> 32), (long) memval, + (long) ((unsigned64) temp >> 32), (long) temp, + (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask, + (long) (rt >> 32), (long) rt); */ + return rt; +} + +:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt +{ + address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = (ReverseEndian ? -1 : 0); + address_word bigendiancpu = (BigEndianCPU ? -1 : 0); + unsigned int byte; + address_word paddr; + int uncached; + unsigned64 memval; + address_word vaddr; + + vaddr = loadstore_ea (SD_, base, offset); + AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); + /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */ + paddr = (paddr ^ (reverseendian & mask)); + if (BigEndianMem != 0) + paddr = paddr & ~access; + byte = ((vaddr & mask) ^ (bigendiancpu & mask)); + /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */ + LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL); + /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n", + (long) paddr, byte, (long) paddr, (long) memval); */ + { + unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0); + rt &= ~screen; + rt |= (memval >> (8 * byte)) & screen; + } + return rt; +} + + +100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB +"lb r, (r)" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET))); +} + + +100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU +"lbu r, (r)" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)); +} + + +110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD +"ld r, (r)" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); +} + + +1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz +"ldc r, (r)" +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); +} + + + + +011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL +"ldl r, (r)" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); +} + + +011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR +"ldr r, (r)" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); +} + + +100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH +"lh r, (r)" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET))); +} + + +100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU +"lhu r, (r)" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)); +} + + +110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL +"ll r, (r)" +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + address_word base = GPR[BASE]; + address_word offset = EXTEND16 (OFFSET); + { + address_word vaddr = loadstore_ea (SD_, base, offset); + address_word paddr; + int uncached; + if ((vaddr & 3) != 0) + { + SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal); + } + else + { + if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + unsigned int shift = 2; + unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); + unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); + LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); + byte = ((vaddr & mask) ^ (bigend << shift)); + GPR[RT] = EXTEND32 (memval >> (8 * byte)); + LLBIT = 1; + } + } + } +} + + +110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD +"lld r, (r)" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + address_word base = GPR[BASE]; + address_word offset = EXTEND16 (OFFSET); + check_u64 (SD_, instruction_0); + { + address_word vaddr = loadstore_ea (SD_, base, offset); + address_word paddr; + int uncached; + if ((vaddr & 7) != 0) + { + SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal); + } + else + { + if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); + GPR[RT] = memval; + LLBIT = 1; + } + } + } +} + + +001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI +"lui r, %#lx" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + TRACE_ALU_INPUT1 (IMMEDIATE); + GPR[RT] = EXTEND32 (IMMEDIATE << 16); + TRACE_ALU_RESULT (GPR[RT]); +} + + +100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW +"lw r, (r)" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); +} + + +1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz +"lwc r, (r)" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); +} + + +100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL +"lwl r, (r)" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT])); +} + + +100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR +"lwr r, (r)" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT])); +} + + +100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU +"lwu r, (r)" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)); +} + + + +011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD +"madd r, r" +*mips32: +*mips64: +*vr5500: +{ + signed64 temp; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) + + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS]))); + LO = EXTEND32 (temp); + HI = EXTEND32 (VH4_8 (temp)); + TRACE_ALU_RESULT2 (HI, LO); +} + + +011100,5.RS,5.RT,000,2.AC,00000,000000:SPECIAL2:32::MADD +"madd r, r":AC == 0 +"madd ac, r, r" +*mips32r2: +*mips64r2: +*dsp2: +{ + signed64 temp; + if (AC == 0) + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC))) + + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS]))); + DSPLO(AC) = EXTEND32 (temp); + DSPHI(AC) = EXTEND32 (VH4_8 (temp)); + if (AC == 0) + TRACE_ALU_RESULT2 (HI, LO); +} + + +011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU +"maddu r, r" +*mips32: +*mips64: +*vr5500: +{ + unsigned64 temp; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) + + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT]))); + ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */ + LO = EXTEND32 (temp); + HI = EXTEND32 (VH4_8 (temp)); + TRACE_ALU_RESULT2 (HI, LO); +} + + +011100,5.RS,5.RT,000,2.AC,00000,000001:SPECIAL2:32::MADDU +"maddu r, r":AC == 0 +"maddu ac, r, r" +*mips32r2: +*mips64r2: +*dsp2: +{ + unsigned64 temp; + if (AC == 0) + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC))) + + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT]))); + if (AC == 0) + ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */ + DSPLO(AC) = EXTEND32 (temp); + DSPHI(AC) = EXTEND32 (VH4_8 (temp)); + if (AC == 0) + TRACE_ALU_RESULT2 (HI, LO); +} + + +:function:::void:do_mfhi:int rd +{ + check_mf_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT1 (HI); + GPR[rd] = HI; + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI +"mfhi r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*vr4100: +*vr5000: +*r3900: +*mips32: +*mips64: +{ + do_mfhi (SD_, RD); +} + + +000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHI +"mfhi r":AC == 0 +"mfhi r, ac" +*mips32r2: +*mips64r2: +*dsp: +{ + if (AC == 0) + do_mfhi (SD_, RD); + else + GPR[RD] = DSPHI(AC); +} + + +:function:::void:do_mflo:int rd +{ + check_mf_hilo (SD_, LOHISTORY, HIHISTORY); + TRACE_ALU_INPUT1 (LO); + GPR[rd] = LO; + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO +"mflo r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*vr4100: +*vr5000: +*r3900: +*mips32: +*mips64: +{ + do_mflo (SD_, RD); +} + + +000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLO +"mflo r":AC == 0 +"mflo r, ac" +*mips32r2: +*mips64r2: +*dsp: +{ + if (AC == 0) + do_mflo (SD_, RD); + else + GPR[RD] = DSPLO(AC); +} + + +000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN +"movn r, r, r" +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr5000: +{ + if (GPR[RT] != 0) + { + GPR[RD] = GPR[RS]; + TRACE_ALU_RESULT (GPR[RD]); + } +} + + + +000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ +"movz r, r, r" +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr5000: +{ + if (GPR[RT] == 0) + { + GPR[RD] = GPR[RS]; + TRACE_ALU_RESULT (GPR[RD]); + } +} + + + +011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB +"msub r, r" +*mips32: +*mips64: +*vr5500: +{ + signed64 temp; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) + - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS]))); + LO = EXTEND32 (temp); + HI = EXTEND32 (VH4_8 (temp)); + TRACE_ALU_RESULT2 (HI, LO); +} + + +011100,5.RS,5.RT,000,2.AC,00000,000100:SPECIAL2:32::MSUB +"msub r, r":AC == 0 +"msub ac, r, r" +*mips32r2: +*mips64r2: +*dsp2: +{ + signed64 temp; + if (AC == 0) + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC))) + - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS]))); + DSPLO(AC) = EXTEND32 (temp); + DSPHI(AC) = EXTEND32 (VH4_8 (temp)); + if (AC == 0) + TRACE_ALU_RESULT2 (HI, LO); +} + + +011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU +"msubu r, r" +*mips32: +*mips64: +*vr5500: +{ + unsigned64 temp; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) + - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT]))); + LO = EXTEND32 (temp); + HI = EXTEND32 (VH4_8 (temp)); + TRACE_ALU_RESULT2 (HI, LO); +} + + +011100,5.RS,5.RT,000,2.AC,00000,000101:SPECIAL2:32::MSUBU +"msubu r, r":AC == 0 +"msubu ac, r, r" +*mips32r2: +*mips64r2: +*dsp2: +{ + unsigned64 temp; + if (AC == 0) + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC))) + - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT]))); + DSPLO(AC) = EXTEND32 (temp); + DSPHI(AC) = EXTEND32 (VH4_8 (temp)); + if (AC == 0) + TRACE_ALU_RESULT2 (HI, LO); +} + + +000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI +"mthi r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*vr4100: +*vr5000: +*r3900: +*mips32: +*mips64: +{ + check_mt_hilo (SD_, HIHISTORY); + HI = GPR[RS]; +} + + +000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHI +"mthi r":AC == 0 +"mthi r, ac" +*mips32r2: +*mips64r2: +*dsp: +{ + if (AC == 0) + check_mt_hilo (SD_, HIHISTORY); + DSPHI(AC) = GPR[RS]; +} + + +000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO +"mtlo r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*vr4100: +*vr5000: +*r3900: +*mips32: +*mips64: +{ + check_mt_hilo (SD_, LOHISTORY); + LO = GPR[RS]; +} + + +000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLO +"mtlo r":AC == 0 +"mtlo r, ac" +*mips32r2: +*mips64r2: +*dsp: +{ + if (AC == 0) + check_mt_hilo (SD_, LOHISTORY); + DSPLO(AC) = GPR[RS]; +} + + +011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL +"mul r, r, r" +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr5500: +{ + signed64 prod; + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + prod = (((signed64)(signed32) GPR[RS]) + * ((signed64)(signed32) GPR[RT])); + GPR[RD] = EXTEND32 (VL4_8 (prod)); + TRACE_ALU_RESULT (GPR[RD]); +} + + + +:function:::void:do_mult:int rs, int rt, int rd +{ + signed64 prod; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + prod = (((signed64)(signed32) GPR[rs]) + * ((signed64)(signed32) GPR[rt])); + LO = EXTEND32 (VL4_8 (prod)); + HI = EXTEND32 (VH4_8 (prod)); + ACX = 0; /* SmartMIPS */ + if (rd != 0) + GPR[rd] = LO; + TRACE_ALU_RESULT2 (HI, LO); +} + +000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT +"mult r, r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips64: +*vr4100: +{ + do_mult (SD_, RS, RT, 0); +} + + +000000,5.RS,5.RT,000,2.AC,00000,011000:SPECIAL:32::MULT +"mult r, r":AC == 0 +"mult ac, r, r" +*mips32r2: +*mips64r2: +*dsp2: +{ + signed64 prod; + if (AC == 0) + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + prod = ((signed64)(signed32) GPR[RS]) + * ((signed64)(signed32) GPR[RT]); + DSPLO(AC) = EXTEND32 (VL4_8 (prod)); + DSPHI(AC) = EXTEND32 (VH4_8 (prod)); + if (AC == 0) + { + ACX = 0; /* SmartMIPS */ + TRACE_ALU_RESULT2 (HI, LO); + } +} + + +000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT +"mult r, r":RD == 0 +"mult r, r, r" +*vr5000: +*r3900: +{ + do_mult (SD_, RS, RT, RD); +} + + +:function:::void:do_multu:int rs, int rt, int rd +{ + unsigned64 prod; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + prod = (((unsigned64)(unsigned32) GPR[rs]) + * ((unsigned64)(unsigned32) GPR[rt])); + LO = EXTEND32 (VL4_8 (prod)); + HI = EXTEND32 (VH4_8 (prod)); + if (rd != 0) + GPR[rd] = LO; + TRACE_ALU_RESULT2 (HI, LO); +} + +000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU +"multu r, r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips64: +*vr4100: +{ + do_multu (SD_, RS, RT, 0); +} + + +000000,5.RS,5.RT,000,2.AC,00000,011001:SPECIAL:32::MULTU +"multu r, r":AC == 0 +"multu r, r" +*mips32r2: +*mips64r2: +*dsp2: +{ + unsigned64 prod; + if (AC == 0) + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + prod = ((unsigned64)(unsigned32) GPR[RS]) + * ((unsigned64)(unsigned32) GPR[RT]); + DSPLO(AC) = EXTEND32 (VL4_8 (prod)); + DSPHI(AC) = EXTEND32 (VH4_8 (prod)); + if (AC == 0) + TRACE_ALU_RESULT2 (HI, LO); +} + + +000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU +"multu r, r":RD == 0 +"multu r, r, r" +*vr5000: +*r3900: +{ + do_multu (SD_, RS, RT, RD); +} + + +:function:::void:do_nor:int rs, int rt, int rd +{ + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = ~ (GPR[rs] | GPR[rt]); + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR +"nor r, r, r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_nor (SD_, RS, RT, RD); +} + + +:function:::void:do_or:int rs, int rt, int rd +{ + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = (GPR[rs] | GPR[rt]); + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR +"or r, r, r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_or (SD_, RS, RT, RD); +} + + + +:function:::void:do_ori:int rs, int rt, unsigned immediate +{ + TRACE_ALU_INPUT2 (GPR[rs], immediate); + GPR[rt] = (GPR[rs] | immediate); + TRACE_ALU_RESULT (GPR[rt]); +} + +001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI +"ori r, r, %#lx" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_ori (SD_, RS, RT, IMMEDIATE); +} + + +110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF +"pref , (r)" +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr5000: +{ + address_word base = GPR[BASE]; + address_word offset = EXTEND16 (OFFSET); + { + address_word vaddr = loadstore_ea (SD_, base, offset); + address_word paddr; + int uncached; + { + if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) + Prefetch(uncached,paddr,vaddr,isDATA,HINT); + } + } +} + + +:function:::unsigned64:do_ror:unsigned32 x,unsigned32 y +{ + unsigned64 result; + + y &= 31; + TRACE_ALU_INPUT2 (x, y); + result = EXTEND32 (ROTR32 (x, y)); + TRACE_ALU_RESULT (result); + return result; +} + +000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR +"ror r, r, " +*mips32r2: +*mips64r2: +*smartmips: +*vr5400: +*vr5500: +{ + GPR[RD] = do_ror (SD_, GPR[RT], SHIFT); +} + +000000,5.RS,5.RT,5.RD,00001,000110::32::RORV +"rorv r, r, r" +*mips32r2: +*mips64r2: +*smartmips: +*vr5400: +*vr5500: +{ + GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]); +} + + +:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word +{ + address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); + address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); + unsigned int byte; + address_word paddr; + int uncached; + unsigned64 memval; + address_word vaddr; + + vaddr = loadstore_ea (SD_, base, offset); + if ((vaddr & access) != 0) + { + SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal); + } + AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); + paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); + byte = ((vaddr & mask) ^ bigendiancpu); + memval = (word << (8 * byte)); + StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL); +} + +:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt +{ + address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = (ReverseEndian ? -1 : 0); + address_word bigendiancpu = (BigEndianCPU ? -1 : 0); + unsigned int byte; + unsigned int word; + address_word paddr; + int uncached; + unsigned64 memval; + address_word vaddr; + int nr_lhs_bits; + int nr_rhs_bits; + + vaddr = loadstore_ea (SD_, base, offset); + AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); + paddr = (paddr ^ (reverseendian & mask)); + if (BigEndianMem == 0) + paddr = paddr & ~access; + + /* compute where within the word/mem we are */ + byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */ + word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */ + nr_lhs_bits = 8 * byte + 8; + nr_rhs_bits = 8 * access - 8 * byte; + /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ + /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", + (long) ((unsigned64) vaddr >> 32), (long) vaddr, + (long) ((unsigned64) paddr >> 32), (long) paddr, + word, byte, nr_lhs_bits, nr_rhs_bits); */ + + if (word == 0) + { + memval = (rt >> nr_rhs_bits); + } + else + { + memval = (rt << nr_lhs_bits); + } + /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n", + (long) ((unsigned64) rt >> 32), (long) rt, + (long) ((unsigned64) memval >> 32), (long) memval); */ + StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL); +} + +:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt +{ + address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = (ReverseEndian ? -1 : 0); + address_word bigendiancpu = (BigEndianCPU ? -1 : 0); + unsigned int byte; + address_word paddr; + int uncached; + unsigned64 memval; + address_word vaddr; + + vaddr = loadstore_ea (SD_, base, offset); + AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); + paddr = (paddr ^ (reverseendian & mask)); + if (BigEndianMem != 0) + paddr &= ~access; + byte = ((vaddr & mask) ^ (bigendiancpu & mask)); + memval = (rt << (byte * 8)); + StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL); +} + + +101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB +"sb r, (r)" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); +} + + +111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC +"sc r, (r)" +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + unsigned32 instruction = instruction_0; + address_word base = GPR[BASE]; + address_word offset = EXTEND16 (OFFSET); + { + address_word vaddr = loadstore_ea (SD_, base, offset); + address_word paddr; + int uncached; + if ((vaddr & 3) != 0) + { + SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal); + } + else + { + if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0); + address_word bigendiancpu = (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0); + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); + byte = ((vaddr & mask) ^ bigendiancpu); + memval = ((unsigned64) GPR[RT] << (8 * byte)); + if (LLBIT) + { + StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); + } + GPR[RT] = LLBIT; + } + } + } +} + + +111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD +"scd r, (r)" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + address_word base = GPR[BASE]; + address_word offset = EXTEND16 (OFFSET); + check_u64 (SD_, instruction_0); + { + address_word vaddr = loadstore_ea (SD_, base, offset); + address_word paddr; + int uncached; + if ((vaddr & 7) != 0) + { + SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal); + } + else + { + if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + memval = GPR[RT]; + if (LLBIT) + { + StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); + } + GPR[RT] = LLBIT; + } + } + } +} + + +111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD +"sd r, (r)" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); +} + + +1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz +"sdc r, (r)" +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT)); +} + + +101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL +"sdl r, (r)" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); +} + + +101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR +"sdr r, (r)" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + check_u64 (SD_, instruction_0); + do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); +} + + + +101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH +"sh r, (r)" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); +} + + +:function:::void:do_sll:int rt, int rd, int shift +{ + unsigned32 temp = (GPR[rt] << shift); + TRACE_ALU_INPUT2 (GPR[rt], shift); + GPR[rd] = EXTEND32 (temp); + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa +"nop":RD == 0 && RT == 0 && SHIFT == 0 +"sll r, r, " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*vr4100: +*vr5000: +*r3900: +{ + /* Skip shift for NOP, so that there won't be lots of extraneous + trace output. */ + if (RD != 0 || RT != 0 || SHIFT != 0) + do_sll (SD_, RT, RD, SHIFT); +} + +000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb +"nop":RD == 0 && RT == 0 && SHIFT == 0 +"ssnop":RD == 0 && RT == 0 && SHIFT == 1 +"sll r, r, " +*mips32: +*mips32r2: +*mips64: +*mips64r2: +{ + /* Skip shift for NOP and SSNOP, so that there won't be lots of + extraneous trace output. */ + if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1)) + do_sll (SD_, RT, RD, SHIFT); +} + + +:function:::void:do_sllv:int rs, int rt, int rd +{ + int s = MASKED (GPR[rs], 4, 0); + unsigned32 temp = (GPR[rt] << s); + TRACE_ALU_INPUT2 (GPR[rt], s); + GPR[rd] = EXTEND32 (temp); + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV +"sllv r, r, r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_sllv (SD_, RS, RT, RD); +} + + +:function:::void:do_slt:int rs, int rt, int rd +{ + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]); + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT +"slt r, r, r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_slt (SD_, RS, RT, RD); +} + + +:function:::void:do_slti:int rs, int rt, unsigned16 immediate +{ + TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); + GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate)); + TRACE_ALU_RESULT (GPR[rt]); +} + +001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI +"slti r, r, " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_slti (SD_, RS, RT, IMMEDIATE); +} + + +:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate +{ + TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); + GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate)); + TRACE_ALU_RESULT (GPR[rt]); +} + +001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU +"sltiu r, r, " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_sltiu (SD_, RS, RT, IMMEDIATE); +} + + + +:function:::void:do_sltu:int rs, int rt, int rd +{ + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]); + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU +"sltu r, r, r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_sltu (SD_, RS, RT, RD); +} + + +:function:::void:do_sra:int rt, int rd, int shift +{ + signed32 temp = (signed32) GPR[rt] >> shift; + if (NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rt], shift); + GPR[rd] = EXTEND32 (temp); + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA +"sra r, r, " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_sra (SD_, RT, RD, SHIFT); +} + + + +:function:::void:do_srav:int rs, int rt, int rd +{ + int s = MASKED (GPR[rs], 4, 0); + signed32 temp = (signed32) GPR[rt] >> s; + if (NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rt], s); + GPR[rd] = EXTEND32 (temp); + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV +"srav r, r, r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_srav (SD_, RS, RT, RD); +} + + + +:function:::void:do_srl:int rt, int rd, int shift +{ + unsigned32 temp = (unsigned32) GPR[rt] >> shift; + if (NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rt], shift); + GPR[rd] = EXTEND32 (temp); + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL +"srl r, r, " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_srl (SD_, RT, RD, SHIFT); +} + + +:function:::void:do_srlv:int rs, int rt, int rd +{ + int s = MASKED (GPR[rs], 4, 0); + unsigned32 temp = (unsigned32) GPR[rt] >> s; + if (NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rt], s); + GPR[rd] = EXTEND32 (temp); + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV +"srlv r, r, r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_srlv (SD_, RS, RT, RD); +} + + +000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB +"sub r, r, r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + { + ALU32_BEGIN (GPR[RS]); + ALU32_SUB (GPR[RT]); + ALU32_END (GPR[RD]); /* This checks for overflow. */ + } + TRACE_ALU_RESULT (GPR[RD]); +} + + +:function:::void:do_subu:int rs, int rt, int rd +{ + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]); + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU +"subu r, r, r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_subu (SD_, RS, RT, RD); +} + + +101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW +"sw r, (r)" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*r3900: +*vr5000: +{ + do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); +} + + +1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz +"swc r, (r)" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT)); +} + + +101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL +"swl r, (r)" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); +} + + +101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR +"swr r, (r)" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); +} + + +000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC +"sync":STYPE == 0 +"sync " +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + SyncOperation (STYPE); +} + + +000000,20.CODE,001100:SPECIAL:32::SYSCALL +"syscall %#lx" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + SignalException (SystemCall, instruction_0); +} + + +000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ +"teq r, r" +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) + SignalException (Trap, instruction_0); +} + + +000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI +"teqi r, " +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE)) + SignalException (Trap, instruction_0); +} + + +000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE +"tge r, r" +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + if ((signed_word) GPR[RS] >= (signed_word) GPR[RT]) + SignalException (Trap, instruction_0); +} + + +000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI +"tgei r, " +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE)) + SignalException (Trap, instruction_0); +} + + +000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU +"tgeiu r, " +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE)) + SignalException (Trap, instruction_0); +} + + +000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU +"tgeu r, r" +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT]) + SignalException (Trap, instruction_0); +} + + +000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT +"tlt r, r" +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + if ((signed_word) GPR[RS] < (signed_word) GPR[RT]) + SignalException (Trap, instruction_0); +} + + +000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI +"tlti r, " +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE)) + SignalException (Trap, instruction_0); +} + + +000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU +"tltiu r, " +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE)) + SignalException (Trap, instruction_0); +} + + +000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU +"tltu r, r" +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]) + SignalException (Trap, instruction_0); +} + + +000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE +"tne r, r" +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) + SignalException (Trap, instruction_0); +} + + +000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI +"tnei r, " +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE)) + SignalException (Trap, instruction_0); +} + + +:function:::void:do_xor:int rs, int rt, int rd +{ + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + GPR[rd] = GPR[rs] ^ GPR[rt]; + TRACE_ALU_RESULT (GPR[rd]); +} + +000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR +"xor r, r, r" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_xor (SD_, RS, RT, RD); +} + + +:function:::void:do_xori:int rs, int rt, unsigned16 immediate +{ + TRACE_ALU_INPUT2 (GPR[rs], immediate); + GPR[rt] = GPR[rs] ^ immediate; + TRACE_ALU_RESULT (GPR[rt]); +} + +001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI +"xori r, r, %#lx" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + do_xori (SD_, RS, RT, IMMEDIATE); +} + + +// +// MIPS Architecture: +// +// FPU Instruction Set (COP1 & COP1X) +// + + +:%s::::FMT:int fmt +{ + switch (fmt) + { + case fmt_single: return "s"; + case fmt_double: return "d"; + case fmt_word: return "w"; + case fmt_long: return "l"; + case fmt_ps: return "ps"; + default: return "?"; + } +} + +:%s::::TF:int tf +{ + if (tf) + return "t"; + else + return "f"; +} + +:%s::::ND:int nd +{ + if (nd) + return "l"; + else + return ""; +} + +:%s::::COND:int cond +{ + switch (cond) + { + case 00: return "f"; + case 01: return "un"; + case 02: return "eq"; + case 03: return "ueq"; + case 04: return "olt"; + case 05: return "ult"; + case 06: return "ole"; + case 07: return "ule"; + case 010: return "sf"; + case 011: return "ngle"; + case 012: return "seq"; + case 013: return "ngl"; + case 014: return "lt"; + case 015: return "nge"; + case 016: return "le"; + case 017: return "ngt"; + default: return "?"; + } +} + + +// Helpers: +// +// Check that the given FPU format is usable, and signal a +// ReservedInstruction exception if not. +// + +// check_fmt_p checks that the format is single, double, or paired single. +:function:::void:check_fmt_p:int fmt, instruction_word insn +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mips32: +*vr4100: +*vr5000: +*r3900: +{ + /* None of these ISAs support Paired Single, so just fall back to + the single/double check. */ + if ((fmt != fmt_single) && (fmt != fmt_double)) + SignalException (ReservedInstruction, insn); +} + +:function:::void:check_fmt_p:int fmt, instruction_word insn +*mips32r2: +{ + if ((fmt != fmt_single) && (fmt != fmt_double) && (fmt != fmt_ps)) + SignalException (ReservedInstruction, insn); +} + +:function:::void:check_fmt_p:int fmt, instruction_word insn +*mipsV: +*mips64: +*mips64r2: +{ + if ((fmt != fmt_single) && (fmt != fmt_double) + && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0))) + SignalException (ReservedInstruction, insn); +} + + +// Helper: +// +// Check that the FPU is currently usable, and signal a CoProcessorUnusable +// exception if not. +// + +:function:::void:check_fpu: +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + if (! COP_Usable (1)) + SignalExceptionCoProcessorUnusable (1); +} + + +// Helper: +// +// Load a double word FP value using 2 32-bit memory cycles a la MIPS II +// or MIPS32. do_load cannot be used instead because it returns an +// unsigned_word, which is limited to the size of the machine's registers. +// + +:function:::unsigned64:do_load_double:address_word base, address_word offset +*mipsII: +*mips32: +*mips32r2: +{ + int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); + address_word vaddr; + address_word paddr; + int uncached; + unsigned64 memval; + unsigned64 v; + + vaddr = loadstore_ea (SD_, base, offset); + if ((vaddr & AccessLength_DOUBLEWORD) != 0) + { + SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, + AccessLength_DOUBLEWORD + 1, vaddr, read_transfer, + sim_core_unaligned_signal); + } + AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, + isREAL); + LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr, + isDATA, isREAL); + v = (unsigned64)memval; + LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4, + isDATA, isREAL); + return (bigendian ? ((v << 32) | memval) : (v | (memval << 32))); +} + + +// Helper: +// +// Store a double word FP value using 2 32-bit memory cycles a la MIPS II +// or MIPS32. do_load cannot be used instead because it returns an +// unsigned_word, which is limited to the size of the machine's registers. +// + +:function:::void:do_store_double:address_word base, address_word offset, unsigned64 v +*mipsII: +*mips32: +*mips32r2: +{ + int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); + address_word vaddr; + address_word paddr; + int uncached; + unsigned64 memval; + + vaddr = loadstore_ea (SD_, base, offset); + if ((vaddr & AccessLength_DOUBLEWORD) != 0) + { + SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, + AccessLength_DOUBLEWORD + 1, vaddr, write_transfer, + sim_core_unaligned_signal); + } + AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, + isREAL); + memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF)); + StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr, + isREAL); + memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32)); + StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4, + isREAL); +} + + +010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt +"abs.%s f, f" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt)); +} + + + +010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt +"add.%s f, f, f" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt)); +} + + +010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:32,f::ALNV.PS +"alnv.ps f, f, f, r" +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +{ + unsigned64 fs; + unsigned64 ft; + unsigned64 fd; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + fs = ValueFPR (FS, fmt_ps); + if ((GPR[RS] & 0x3) != 0) + Unpredictable (); + if ((GPR[RS] & 0x4) == 0) + fd = fs; + else + { + ft = ValueFPR (FT, fmt_ps); + if (BigEndianCPU) + fd = PackPS (PSLower (fs), PSUpper (ft)); + else + fd = PackPS (PSLower (ft), PSUpper (fs)); + } + StoreFPR (FD, fmt_ps, fd); +} + + +// BC1F +// BC1FL +// BC1T +// BC1TL + +010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a +"bc1%s%s " +*mipsI: +*mipsII: +*mipsIII: +{ + check_fpu (SD_); + TRACE_BRANCH_INPUT (PREVCOC1()); + if (PREVCOC1() == TF) + { + address_word dest = NIA + (EXTEND16 (OFFSET) << 2); + TRACE_BRANCH_RESULT (dest); + DELAY_SLOT (dest); + } + else if (ND) + { + TRACE_BRANCH_RESULT (0); + NULLIFY_NEXT_INSTRUCTION (); + } + else + { + TRACE_BRANCH_RESULT (NIA); + } +} + +010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b +"bc1%s%s ":CC == 0 +"bc1%s%s , " +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +#*vr4100: +*vr5000: +*r3900: +{ + check_fpu (SD_); + if (GETFCC(CC) == TF) + { + address_word dest = NIA + (EXTEND16 (OFFSET) << 2); + DELAY_SLOT (dest); + } + else if (ND) + { + NULLIFY_NEXT_INSTRUCTION (); + } +} + + +010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta +"c.%s.%s f, f" +*mipsI: +*mipsII: +*mipsIII: +{ + int fmt = FMT; + check_fpu (SD_); + Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0); + TRACE_ALU_RESULT (ValueFCR (31)); +} + +010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb +"c.%s.%s f, f":CC == 0 +"c.%s.%s , f, f" +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC); + TRACE_ALU_RESULT (ValueFCR (31)); +} + + +010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:32,f::CEIL.L.fmt +"ceil.l.%s f, f" +*mipsIII: +*mipsIV: +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt, + fmt_long)); +} + + +010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W +"ceil.w.%s f, f" +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt, + fmt_word)); +} + + +010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a +"cfc1 r, f" +*mipsI: +*mipsII: +*mipsIII: +{ + check_fpu (SD_); + if (FS == 0) + PENDING_FILL (RT, EXTEND32 (FCR0)); + else if (FS == 31) + PENDING_FILL (RT, EXTEND32 (FCR31)); + /* else NOP */ +} + +010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b +"cfc1 r, f" +*mipsIV: +*vr4100: +*vr5000: +*r3900: +{ + check_fpu (SD_); + if (FS == 0 || FS == 31) + { + unsigned_word fcr = ValueFCR (FS); + TRACE_ALU_INPUT1 (fcr); + GPR[RT] = fcr; + } + /* else NOP */ + TRACE_ALU_RESULT (GPR[RT]); +} + +010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c +"cfc1 r, f" +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +{ + check_fpu (SD_); + if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31) + { + unsigned_word fcr = ValueFCR (FS); + TRACE_ALU_INPUT1 (fcr); + GPR[RT] = fcr; + } + /* else NOP */ + TRACE_ALU_RESULT (GPR[RT]); +} + +010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a +"ctc1 r, f" +*mipsI: +*mipsII: +*mipsIII: +{ + check_fpu (SD_); + if (FS == 31) + PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT])); + /* else NOP */ +} + +010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b +"ctc1 r, f" +*mipsIV: +*vr4100: +*vr5000: +*r3900: +{ + check_fpu (SD_); + TRACE_ALU_INPUT1 (GPR[RT]); + if (FS == 31) + StoreFCR (FS, GPR[RT]); + /* else NOP */ +} + +010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c +"ctc1 r, f" +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +{ + check_fpu (SD_); + TRACE_ALU_INPUT1 (GPR[RT]); + if (FS == 25 || FS == 26 || FS == 28 || FS == 31) + StoreFCR (FS, GPR[RT]); + /* else NOP */ +} + + +// +// FIXME: Does not correctly differentiate between mips* +// +010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt +"cvt.d.%s f, f" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + if ((fmt == fmt_double) | 0) + SignalException (ReservedInstruction, instruction_0); + StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt, + fmt_double)); +} + + +010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:32,f::CVT.L.fmt +"cvt.l.%s f, f" +*mipsIII: +*mipsIV: +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word))) + SignalException (ReservedInstruction, instruction_0); + StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt, + fmt_long)); +} + + +010001,10,000,5.FT,5.FS,5.FD,100110:COP1:32,f::CVT.PS.S +"cvt.ps.s f, f, f" +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single), + ValueFPR (FT, fmt_single))); +} + + +// +// FIXME: Does not correctly differentiate between mips* +// +010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt +"cvt.s.%s f, f" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + if ((fmt == fmt_single) | 0) + SignalException (ReservedInstruction, instruction_0); + StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt, + fmt_single)); +} + + +010001,10,110,00000,5.FS,5.FD,101000:COP1:32,f::CVT.S.PL +"cvt.s.pl f, f" +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps))); +} + + +010001,10,110,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.PU +"cvt.s.pu f, f" +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps))); +} + + +010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt +"cvt.w.%s f, f" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word))) + SignalException (ReservedInstruction, instruction_0); + StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt, + fmt_word)); +} + + +010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt +"div.%s f, f, f" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt)); +} + + +010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a +"dmfc1 r, f" +*mipsIII: +{ + unsigned64 v; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + if (SizeFGR () == 64) + v = FGR[FS]; + else if ((FS & 0x1) == 0) + v = SET64HI (FGR[FS+1]) | FGR[FS]; + else + v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0; + PENDING_FILL (RT, v); + TRACE_ALU_RESULT (v); +} + +010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b +"dmfc1 r, f" +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + if (SizeFGR () == 64) + GPR[RT] = FGR[FS]; + else if ((FS & 0x1) == 0) + GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS]; + else + GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0; + TRACE_ALU_RESULT (GPR[RT]); +} + + +010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a +"dmtc1 r, f" +*mipsIII: +{ + unsigned64 v; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + if (SizeFGR () == 64) + PENDING_FILL ((FS + FGR_BASE), GPR[RT]); + else if ((FS & 0x1) == 0) + { + PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT])); + PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT])); + } + else + Unpredictable (); + TRACE_FP_RESULT (GPR[RT]); +} + +010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b +"dmtc1 r, f" +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + if (SizeFGR () == 64) + StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]); + else if ((FS & 0x1) == 0) + StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]); + else + Unpredictable (); +} + + +010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:32,f::FLOOR.L.fmt +"floor.l.%s f, f" +*mipsIII: +*mipsIV: +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt, + fmt_long)); +} + + +010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt +"floor.w.%s f, f" +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt, + fmt_word)); +} + + +110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a +"ldc1 f, (r)" +*mipsII: +*mips32: +*mips32r2: +{ + check_fpu (SD_); + COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET))); +} + + +110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b +"ldc1 f, (r)" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + check_fpu (SD_); + COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); +} + + +010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:32,f::LDXC1 +"ldxc1 f, r(r)" +*mips32r2: +{ + check_fpu (SD_); + COP_LD (1, FD, do_load_double (SD_, GPR[BASE], GPR[INDEX])); +} + + +010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1 +"ldxc1 f, r(r)" +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr5000: +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX])); +} + + +010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:32,f::LUXC1 +"luxc1 f, r(r)" +*mips32r2: +{ + address_word base = GPR[BASE]; + address_word index = GPR[INDEX]; + address_word vaddr = base + index; + check_fpu (SD_); + if (SizeFGR () != 64) + Unpredictable (); + /* Arrange for the bottom 3 bits of (base + index) to be 0. */ + if ((vaddr & 0x7) != 0) + index -= (vaddr & 0x7); + COP_LD (1, FD, do_load_double (SD_, base, index)); +} + + +010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1 +"luxc1 f, r(r)" +*mipsV: +*mips64: +*mips64r2: +{ + address_word base = GPR[BASE]; + address_word index = GPR[INDEX]; + address_word vaddr = base + index; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + if (SizeFGR () != 64) + Unpredictable (); + /* Arrange for the bottom 3 bits of (base + index) to be 0. */ + if ((vaddr & 0x7) != 0) + index -= (vaddr & 0x7); + COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index)); +} + + +110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1 +"lwc1 f, (r)" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + check_fpu (SD_); + COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); +} + + +010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32,f::LWXC1 +"lwxc1 f, r(r)" +*mipsIV: +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +*vr5000: +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX])); +} + + + +010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:32,f::MADD.fmt +"madd.%s f, f, f, f" +*mipsIV: +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +*vr5000: +{ + int fmt = FMT; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt), + ValueFPR (FR, fmt), fmt)); +} + + +010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a +"mfc1 r, f" +*mipsI: +*mipsII: +*mipsIII: +{ + unsigned64 v; + check_fpu (SD_); + v = EXTEND32 (FGR[FS]); + PENDING_FILL (RT, v); + TRACE_ALU_RESULT (v); +} + +010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b +"mfc1 r, f" +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + check_fpu (SD_); + GPR[RT] = EXTEND32 (FGR[FS]); + TRACE_ALU_RESULT (GPR[RT]); +} + + +010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt +"mov.%s f, f" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, ValueFPR (FS, fmt)); +} + + +// MOVF +// MOVT +000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf +"mov%s r, r, " +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr5000: +{ + check_fpu (SD_); + if (GETFCC(CC) == TF) + GPR[RD] = GPR[RS]; +} + + +// MOVF.fmt +// MOVT.fmt +010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt +"mov%s.%s f, f, " +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr5000: +{ + int fmt = FMT; + check_fpu (SD_); + if (fmt != fmt_ps) + { + if (GETFCC(CC) == TF) + StoreFPR (FD, fmt, ValueFPR (FS, fmt)); + else + StoreFPR (FD, fmt, ValueFPR (FD, fmt)); /* set fmt */ + } + else + { + unsigned64 fd; + fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD, + fmt_ps)), + PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD, + fmt_ps))); + StoreFPR (FD, fmt_ps, fd); + } +} + + +010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt +"movn.%s f, f, r" +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr5000: +{ + check_fpu (SD_); + if (GPR[RT] != 0) + StoreFPR (FD, FMT, ValueFPR (FS, FMT)); + else + StoreFPR (FD, FMT, ValueFPR (FD, FMT)); +} + + +// MOVT see MOVtf + + +// MOVT.fmt see MOVtf.fmt + + + +010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt +"movz.%s f, f, r" +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr5000: +{ + check_fpu (SD_); + if (GPR[RT] == 0) + StoreFPR (FD, FMT, ValueFPR (FS, FMT)); + else + StoreFPR (FD, FMT, ValueFPR (FD, FMT)); +} + + +010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:32,f::MSUB.fmt +"msub.%s f, f, f, f" +*mipsIV: +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +*vr5000: +{ + int fmt = FMT; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), + ValueFPR (FR, fmt), fmt)); +} + + +010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a +"mtc1 r, f" +*mipsI: +*mipsII: +*mipsIII: +{ + check_fpu (SD_); + if (SizeFGR () == 64) + PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT]))); + else + PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT])); + TRACE_FP_RESULT (GPR[RT]); +} + +010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b +"mtc1 r, f" +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + check_fpu (SD_); + StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT])); +} + + +010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt +"mul.%s f, f, f" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt)); +} + + +010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt +"neg.%s f, f" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt)); +} + + +010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:32,f::NMADD.fmt +"nmadd.%s f, f, f, f" +*mipsIV: +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +*vr5000: +{ + int fmt = FMT; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt), + ValueFPR (FR, fmt), fmt)); +} + + +010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:32,f::NMSUB.fmt +"nmsub.%s f, f, f, f" +*mipsIV: +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +*vr5000: +{ + int fmt = FMT; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), + ValueFPR (FR, fmt), fmt)); +} + + +010001,10,110,5.FT,5.FS,5.FD,101100:COP1:32,f::PLL.PS +"pll.ps f, f, f" +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)), + PSLower (ValueFPR (FT, fmt_ps)))); +} + + +010001,10,110,5.FT,5.FS,5.FD,101101:COP1:32,f::PLU.PS +"plu.ps f, f, f" +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)), + PSUpper (ValueFPR (FT, fmt_ps)))); +} + + +010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:32::PREFX +"prefx , r(r)" +*mipsIV: +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +*vr5000: +{ + address_word base = GPR[BASE]; + address_word index = GPR[INDEX]; + { + address_word vaddr = loadstore_ea (SD_, base, index); + address_word paddr; + int uncached; + if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) + Prefetch(uncached,paddr,vaddr,isDATA,HINT); + } +} + + +010001,10,110,5.FT,5.FS,5.FD,101110:COP1:32,f::PUL.PS +"pul.ps f, f, f" +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)), + PSLower (ValueFPR (FT, fmt_ps)))); +} + + +010001,10,110,5.FT,5.FS,5.FD,101111:COP1:32,f::PUU.PS +"puu.ps f, f, f" +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)), + PSUpper (ValueFPR (FT, fmt_ps)))); +} + + +010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt +"recip.%s f, f" +*mipsIV: +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +*vr5000: +{ + int fmt = FMT; + check_fpu (SD_); + StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt)); +} + + +010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:32,f::ROUND.L.fmt +"round.l.%s f, f" +*mipsIII: +*mipsIV: +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt, + fmt_long)); +} + + +010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt +"round.w.%s f, f" +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt, + fmt_word)); +} + + +010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt +"rsqrt.%s f, f" +*mipsIV: +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +*vr5000: +{ + int fmt = FMT; + check_fpu (SD_); + StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt)); +} + + +111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a +"sdc1 f, (r)" +*mipsII: +*mips32: +*mips32r2: +{ + check_fpu (SD_); + do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT)); +} + + +111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b +"sdc1 f, (r)" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + check_fpu (SD_); + do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT)); +} + + +010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:32,f::SDXC1 +"sdxc1 f, r(r)" +*mips32r2 +{ + check_fpu (SD_); + do_store_double (SD_, GPR[BASE], GPR[INDEX], COP_SD (1, FS)); +} + + +010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1 +"sdxc1 f, r(r)" +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*vr5000: +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS)); +} + + +010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:32,f::SUXC1 +"suxc1 f, r(r)" +*mips32r2: +{ + address_word base = GPR[BASE]; + address_word index = GPR[INDEX]; + address_word vaddr = base + index; + check_fpu (SD_); + if (SizeFGR () != 64) + Unpredictable (); + /* Arrange for the bottom 3 bits of (base + index) to be 0. */ + if ((vaddr & 0x7) != 0) + index -= (vaddr & 0x7); + do_store_double (SD_, base, index, COP_SD (1, FS)); +} + + +010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1 +"suxc1 f, r(r)" +*mipsV: +*mips64: +*mips64r2: +{ + address_word base = GPR[BASE]; + address_word index = GPR[INDEX]; + address_word vaddr = base + index; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + if (SizeFGR () != 64) + Unpredictable (); + /* Arrange for the bottom 3 bits of (base + index) to be 0. */ + if ((vaddr & 0x7) != 0) + index -= (vaddr & 0x7); + do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS)); +} + + +010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt +"sqrt.%s f, f" +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt))); +} + + +010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt +"sub.%s f, f, f" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt)); +} + + + +111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1 +"swc1 f, (r)" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + address_word base = GPR[BASE]; + address_word offset = EXTEND16 (OFFSET); + check_fpu (SD_); + { + address_word vaddr = loadstore_ea (SD_, base, offset); + address_word paddr; + int uncached; + if ((vaddr & 3) != 0) + { + SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal); + } + else + { + if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) + { + uword64 memval = 0; + uword64 memval1 = 0; + uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0); + address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0); + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); + byte = ((vaddr & mask) ^ bigendiancpu); + memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte)); + StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); + } + } + } +} + + +010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1 +"swxc1 f, r(r)" +*mipsIV: +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +*vr5000: +{ + + address_word base = GPR[BASE]; + address_word index = GPR[INDEX]; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + { + address_word vaddr = loadstore_ea (SD_, base, index); + address_word paddr; + int uncached; + if ((vaddr & 3) != 0) + { + SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal); + } + else + { + if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) + { + unsigned64 memval = 0; + unsigned64 memval1 = 0; + unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0); + address_word bigendiancpu = (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0); + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); + byte = ((vaddr & mask) ^ bigendiancpu); + memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte)); + { + StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); + } + } + } + } +} + + +010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:32,f::TRUNC.L.fmt +"trunc.l.%s f, f" +*mipsIII: +*mipsIV: +*mipsV: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt, + fmt_long)); +} + + +010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W +"trunc.w.%s f, f" +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + int fmt = FMT; + check_fpu (SD_); + StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt, + fmt_word)); +} + + +// +// MIPS Architecture: +// +// System Control Instruction Set (COP0) +// + + +010000,01000,00000,16.OFFSET:COP0:32::BC0F +"bc0f " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: + +010000,01000,00000,16.OFFSET:COP0:32::BC0F +"bc0f " +// stub needed for eCos as tx39 hardware bug workaround +*r3900: +{ + /* do nothing */ +} + + +010000,01000,00010,16.OFFSET:COP0:32::BC0FL +"bc0fl " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: + + +010000,01000,00001,16.OFFSET:COP0:32::BC0T +"bc0t " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: + + +010000,01000,00011,16.OFFSET:COP0:32::BC0TL +"bc0tl " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: + + +101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE +"cache , (r)" +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + address_word base = GPR[BASE]; + address_word offset = EXTEND16 (OFFSET); + { + address_word vaddr = loadstore_ea (SD_, base, offset); + address_word paddr; + int uncached; + if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) + CacheOp(OP,vaddr,paddr,instruction_0); + } +} + + +010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0 +"dmfc0 r, r" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +{ + check_u64 (SD_, instruction_0); + DecodeCoproc (instruction_0); +} + + +010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0 +"dmtc0 r, r" +*mipsIII: +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +{ + check_u64 (SD_, instruction_0); + DecodeCoproc (instruction_0); +} + + +010000,1,0000000000000000000,011000:COP0:32::ERET +"eret" +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +{ + if (SR & status_ERL) + { + /* Oops, not yet available */ + sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported"); + NIA = EPC; + SR &= ~status_ERL; + } + else + { + NIA = EPC; + SR &= ~status_EXL; + } +} + + +010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0 +"mfc0 r, r # " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + TRACE_ALU_INPUT0 (); + DecodeCoproc (instruction_0); + TRACE_ALU_RESULT (GPR[RT]); +} + +010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0 +"mtc0 r, r # " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: +*r3900: +{ + DecodeCoproc (instruction_0); +} + + +010000,1,0000000000000000000,010000:COP0:32::RFE +"rfe" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*vr4100: +*vr5000: +*r3900: +{ + DecodeCoproc (instruction_0); +} + + +0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz +"cop " +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*r3900: +{ + DecodeCoproc (instruction_0); +} + + + +010000,1,0000000000000000000,001000:COP0:32::TLBP +"tlbp" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: + + +010000,1,0000000000000000000,000001:COP0:32::TLBR +"tlbr" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: + + +010000,1,0000000000000000000,000010:COP0:32::TLBWI +"tlbwi" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: + + +010000,1,0000000000000000000,000110:COP0:32::TLBWR +"tlbwr" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips64: +*mips64r2: +*vr4100: +*vr5000: + + +:include:::mips3264r2.igen +:include:::m16.igen +:include:::m16e.igen +:include:::mdmx.igen +:include:::mips3d.igen +:include:::sb1.igen +:include:::tx.igen +:include:::vr.igen +:include:::dsp.igen +:include:::dsp2.igen +:include:::smartmips.igen + Index: dsp2.igen =================================================================== --- dsp2.igen (nonexistent) +++ dsp2.igen (revision 33) @@ -0,0 +1,736 @@ +// -*- C -*- + +// Simulator definition for the MIPS DSP REV 2 ASE. +// Copyright (C) 2007 Free Software Foundation, Inc. +// Contributed by MIPS Technologies, Inc. +// Written by Chao-ying Fu (fu@mips.com). +// +// This file is part of GDB, the GNU debugger. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + + +// op: 0 = ADD, 1 = SUB +// sat: 0 = no saturation, 1 = saturation +:function:::void:do_u_ph_op:int rd, int rs, int rt, int op, int sat +{ + int i; + unsigned32 h0; + unsigned16 h1, h2; + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + unsigned32 result = 0; + for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) + { + h1 = (unsigned16)(v1 & 0xffff); + h2 = (unsigned16)(v2 & 0xffff); + if (op == 0) // ADD + h0 = (unsigned32)h1 + (unsigned32)h2; + else // SUB + h0 = (unsigned32)h1 - (unsigned32)h2; + if (op == 0 && (h0 > (unsigned32)0x0000ffff)) // ADD SAT + { + DSPCR |= DSPCR_OUFLAG4; + if (sat == 1) + h0 = 0xffff; + } + else if (op == 1 && h1 < h2) // SUB SAT + { + DSPCR |= DSPCR_OUFLAG4; + if (sat == 1) + h0 = 0x0; + } + result |= ((unsigned32)((unsigned16)h0) << i); + } + GPR[rd] = EXTEND32 (result); +} + +// op: 0 = ADD, 1 = SUB +// round: 0 = no rounding, 1 = rounding +:function:::void:do_uh_qb_op:int rd, int rs, int rt, int op, int round +{ + int i; + unsigned32 h0; + unsigned8 h1, h2; + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + unsigned32 result = 0; + for (i = 0; i < 32; i += 8, v1 >>= 8, v2 >>= 8) + { + h1 = (unsigned8)(v1 & 0xff); + h2 = (unsigned8)(v2 & 0xff); + if (op == 0) // ADD + h0 = (unsigned32)h1 + (unsigned32)h2; + else // SUB + h0 = (unsigned32)h1 - (unsigned32)h2; + if (round == 1) + h0 = (h0 + 1) >> 1; + else + h0 = h0 >> 1; + result |= ((unsigned32)((unsigned8)h0) << i); + } + GPR[rd] = EXTEND32 (result); +} + +// op: 0 = EQ, 1 = LT, 2 = LE +:function:::void:do_qb_cmpgdu:int rd, int rs, int rt, int op +{ + int i, j; + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + unsigned8 h1, h2; + unsigned32 result = 0; + unsigned32 mask; + for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8) + { + h1 = (unsigned8)(v1 & 0xff); + h2 = (unsigned8)(v2 & 0xff); + mask = ~(1 << (DSPCR_CCOND_SHIFT + j)); + DSPCR &= mask; + if (op == 0) // EQ + { + result |= ((h1 == h2) << j); + DSPCR |= ((h1 == h2) << (DSPCR_CCOND_SHIFT + j)); + } + else if (op == 1) // LT + { + result |= ((h1 < h2) << j); + DSPCR |= ((h1 < h2) << (DSPCR_CCOND_SHIFT + j)); + } + else // LE + { + result |= ((h1 <= h2) << j); + DSPCR |= ((h1 <= h2) << (DSPCR_CCOND_SHIFT + j)); + } + } + GPR[rd] = EXTEND32 (result); +} + +// op: 0 = DPA 1 = DPS +:function:::void:do_w_ph_dot_product:int ac, int rs, int rt, int op +{ + int i; + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + signed16 h1, h2; + signed32 result; + unsigned32 lo = DSPLO(ac); + unsigned32 hi = DSPHI(ac); + signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); + for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) + { + h1 = (signed16)(v1 & 0xffff); + h2 = (signed16)(v2 & 0xffff); + result = (signed32)h1 * (signed32)h2; + if (op == 0) // DPA + prod += (signed64)result; + else // DPS + prod -= (signed64)result; + } + DSPLO(ac) = EXTEND32 (prod); + DSPHI(ac) = EXTEND32 (prod >> 32); +} + +// round: 0 = no rounding, 1 = rounding +:function:::void:do_w_mulq:int rd, int rs, int rt, int round +{ + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + signed32 w1, w2; + signed64 prod; + unsigned32 result; + w1 = (signed32) v1; + w2 = (signed32 )v2; + if (w1 == (signed32) 0x80000000 && w2 == (signed32) 0x80000000) + { + DSPCR |= DSPCR_OUFLAG5; + prod = 0x7fffffff; + } + else + { + prod = ((signed64) w1 * (signed64) w2) << 1; + if (round == 1) + prod += 0x0000000080000000LL; + prod = prod >> 32; + } + result = (unsigned32) prod; + GPR[rd] = EXTEND32 (result); +} + +// round: 0 = no rounding, 1 = rounding +:function:::void:do_precr_sra:int rt, int rs, int sa, int round +{ + unsigned32 v1 = GPR[rt]; + unsigned32 v2 = GPR[rs]; + signed32 w1 = (signed32) v1; + signed32 w2 = (signed32) v2; + signed32 result; + if (sa != 0) + { + if (round == 1 && (w1 & (1 << (sa - 1)))) + w1 = (w1 >> sa) + 1; + else + w1 = w1 >> sa; + + if (round == 1 && (w2 & (1 << (sa - 1)))) + w2 = (w2 >> sa) + 1; + else + w2 = w2 >> sa; + } + result = (w1 << 16) | (w2 & 0xffff); + GPR[rt] = EXTEND32 (result); +} + +// round: 0 = no rounding, 1 = rounding +:function:::void:do_qb_shra:int rd, int rt, int shift, int round +{ + int i, j; + signed8 q0; + unsigned32 v1 = GPR[rt]; + unsigned32 result = 0; + for (i = 0; i < 32; i += 8, v1 >>= 8) + { + q0 = (signed8)(v1 & 0xff); + if (shift != 0) + { + if (round == 1 && (q0 & (1 << (shift - 1)))) + q0 = (q0 >> shift) + 1; + else + q0 = q0 >> shift; + } + result |= ((unsigned32)((unsigned8)q0) << i); + } + GPR[rd] = EXTEND32 (result); +} + +:function:::void:do_ph_shrl:int rd, int rt, int shift +{ + int i, j; + unsigned16 h0; + unsigned32 v1 = GPR[rt]; + unsigned32 result = 0; + for (i = 0; i < 32; i += 16, v1 >>= 16) + { + h0 = (unsigned16)(v1 & 0xffff); + h0 = h0 >> shift; + result |= ((unsigned32)h0 << i); + } + GPR[rd] = EXTEND32 (result); +} + +// op: 0 = ADD, 1 = SUB +// round: 0 = no rounding, 1 = rounding +:function:::void:do_qh_ph_op:int rd, int rs, int rt, int op, int round +{ + int i; + signed32 h0; + signed16 h1, h2; + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + unsigned32 result = 0; + for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) + { + h1 = (signed16)(v1 & 0xffff); + h2 = (signed16)(v2 & 0xffff); + if (op == 0) // ADD + h0 = (signed32)h1 + (signed32)h2; + else // SUB + h0 = (signed32)h1 - (signed32)h2; + if (round == 1) + h0 = (h0 + 1) >> 1; + else + h0 = h0 >> 1; + result |= ((unsigned32)((unsigned16)h0) << i); + } + GPR[rd] = EXTEND32 (result); +} + +// op: 0 = ADD, 1 = SUB +// round: 0 = no rounding, 1 = rounding +:function:::void:do_qh_w_op:int rd, int rs, int rt, int op, int round +{ + int i; + signed64 v0; + signed32 v1 = (signed32)GPR[rs]; + signed32 v2 = (signed32)GPR[rt]; + if (op == 0) // ADD + v0 = (signed64)v1 + (signed64)v2; + else // SUB + v0 = (signed64)v1 - (signed64)v2; + if (round == 1) + v0 = (v0 + 1) >> 1; + else + v0 = v0 >> 1; + GPR[rd] = EXTEND32 (v0); +} + +// op: 0 = DPAX, 1 = DPSX +:function:::void:do_x_w_ph_dot_product:int ac, int rs, int rt, int op +{ + int i; + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + signed16 h1, h2; + signed32 result; + unsigned32 lo = DSPLO(ac); + unsigned32 hi = DSPHI(ac); + signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); + for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16) + { + h1 = (signed16)(v1 & 0xffff); + h2 = (signed16)((v2 & 0xffff0000) >> 16); + result = (signed32)h1 * (signed32)h2; + if (op == 0) // DPAX + prod += (signed64)result; + else // DPSX + prod -= (signed64)result; + } + DSPLO(ac) = EXTEND32 (prod); + DSPHI(ac) = EXTEND32 (prod >> 32); +} + +// op: 0 = DPAQX, 1 = DPSQX +// sat: 0 = no saturation, 1 = saturation of the accumulator +:function:::void:do_qx_w_ph_dot_product:int ac, int rs, int rt, int op, int sat +{ + int i; + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + signed16 h1, h2; + signed32 result; + unsigned32 lo = DSPLO(ac); + unsigned32 hi = DSPHI(ac); + signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); + signed64 max, min; + for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16) + { + h1 = (signed16)(v1 & 0xffff); + h2 = (signed16)((v2 & 0xffff0000) >> 16); + if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000) + { + DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); + result = 0x7fffffff; + } + else + result = ((signed32)h1 * (signed32)h2) << 1; + if (op == 0) // DPAQX + prod += (signed64)result; + else // DPSQX + prod -= (signed64)result; + } + // Saturation on the accumulator. + if (sat == 1) + { + max = (signed64) 0x7fffffffLL; + min = (signed64) 0xffffffff80000000LL; + if (prod > max) + { + DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); + prod = max; + } + else if (prod < min) + { + DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); + prod = min; + } + } + DSPLO(ac) = EXTEND32 (prod); + DSPHI(ac) = EXTEND32 (prod >> 32); +} + +011111,00000,5.RT,5.RD,00001,010010:SPECIAL3:32::ABSQ_S.QB +"absq_s.qb r, r" +*dsp2: +{ + int i; + signed8 q0; + unsigned32 v1 = GPR[RT]; + unsigned32 result = 0; + for (i = 0; i < 32; i += 8, v1 >>= 8) + { + q0 = (signed8)(v1 & 0xff); + if (q0 == (signed8)0x80) + { + DSPCR |= DSPCR_OUFLAG4; + q0 = 0x7f; + } + else if (q0 & 0x80) + q0 = -q0; + result |= ((unsigned32)((unsigned8)q0) << i); + } + GPR[RD] = EXTEND32 (result); +} + +011111,5.RS,5.RT,5.RD,01000,010000:SPECIAL3:32::ADDU.PH +"addu.ph r, r, r" +*dsp2: +{ + do_u_ph_op (SD_, RD, RS, RT, 0, 0); +} + +011111,5.RS,5.RT,5.RD,01100,010000:SPECIAL3:32::ADDU_S.PH +"addu_s.ph r, r, r" +*dsp2: +{ + do_u_ph_op (SD_, RD, RS, RT, 0, 1); +} + +011111,5.RS,5.RT,5.RD,00000,011000:SPECIAL3:32::ADDUH.QB +"adduh.qb r, r, r" +*dsp2: +{ + do_uh_qb_op (SD_, RD, RS, RT, 0, 0); +} + +011111,5.RS,5.RT,5.RD,00010,011000:SPECIAL3:32::ADDUH_R.QB +"adduh_r.qb r, r, r" +*dsp2: +{ + do_uh_qb_op (SD_, RD, RS, RT, 0, 1); +} + +011111,5.RS,5.RT,5.SA,00000,110001:SPECIAL3:32::APPEND +"append r, r, " +*dsp2: +{ + unsigned32 v0 = GPR[RS]; + unsigned32 v1 = GPR[RT]; + unsigned32 result; + unsigned32 mask = (1 << SA) - 1; + result = (v1 << SA) | (v0 & mask); + GPR[RT] = EXTEND32 (result); +} + +011111,5.RS,5.RT,000,2.BP,10000,110001:SPECIAL3:32::BALIGN +"balign r, r, " +*dsp2: +{ + unsigned32 v0 = GPR[RS]; + unsigned32 v1 = GPR[RT]; + unsigned32 result; + if (BP == 0) + result = v1; + else + result = (v1 << 8 * BP) | (v0 >> 8 * (4 - BP)); + GPR[RT] = EXTEND32 (result); +} + +011111,5.RS,5.RT,5.RD,11000,010001:SPECIAL3:32::CMPGDU.EQ.QB +"cmpgdu.eq.qb r, r, r" +*dsp2: +{ + do_qb_cmpgdu (SD_, RD, RS, RT, 0); +} + +011111,5.RS,5.RT,5.RD,11001,010001:SPECIAL3:32::CMPGDU.LT.QB +"cmpgdu.lt.qb r, r, r" +*dsp2: +{ + do_qb_cmpgdu (SD_, RD, RS, RT, 1); +} + +011111,5.RS,5.RT,5.RD,11010,010001:SPECIAL3:32::CMPGDU.LE.QB +"cmpgdu.le.qb r, r, r" +*dsp2: +{ + do_qb_cmpgdu (SD_, RD, RS, RT, 2); +} + +011111,5.RS,5.RT,000,2.AC,00000,110000:SPECIAL3:32::DPA.W.PH +"dpa.w.ph ac, r, r" +*dsp2: +{ + do_w_ph_dot_product (SD_, AC, RS, RT, 0); +} + +011111,5.RS,5.RT,000,2.AC,00001,110000:SPECIAL3:32::DPS.W.PH +"dps.w.ph ac, r, r" +*dsp2: +{ + do_w_ph_dot_product (SD_, AC, RS, RT, 1); +} + +011111,5.RS,5.RT,5.RD,01100,011000:SPECIAL3:32::MUL.PH +"mul.ph r, r, r" +*dsp2: +{ + do_ph_op (SD_, RD, RS, RT, 2, 0); +} + +011111,5.RS,5.RT,5.RD,01110,011000:SPECIAL3:32::MUL_S.PH +"mul_s.ph r, r, r" +*dsp2: +{ + do_ph_op (SD_, RD, RS, RT, 2, 1); +} + +011111,5.RS,5.RT,5.RD,10111,011000:SPECIAL3:32::MULQ_RS.W +"mulq_rs.w r, r, r" +*dsp2: +{ + do_w_mulq (SD_, RD, RS, RT, 1); +} + +011111,5.RS,5.RT,5.RD,11110,010000:SPECIAL3:32::MULQ_S.PH +"mulq_s.ph r, r, r" +*dsp2: +{ + do_ph_mulq (SD_, RD, RS, RT, 0); +} + +011111,5.RS,5.RT,5.RD,10110,011000:SPECIAL3:32::MULQ_S.W +"mulq_s.w r, r, r" +*dsp2: +{ + do_w_mulq (SD_, RD, RS, RT, 0); +} + +011111,5.RS,5.RT,000,2.AC,00010,110000:SPECIAL3:32::MULSA.W.PH +"mulsa.w.ph ac, r, r" +*dsp2: +{ + int i; + unsigned32 v1 = GPR[RS]; + unsigned32 v2 = GPR[RT]; + signed16 h1, h2; + signed32 result; + unsigned32 lo = DSPLO(AC); + unsigned32 hi = DSPHI(AC); + signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); + for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) + { + h1 = (signed16)(v1 & 0xffff); + h2 = (signed16)(v2 & 0xffff); + result = (signed32)h1 * (signed32)h2; + + if (i == 0) + prod -= (signed64) result; + else + prod += (signed64) result; + } + DSPLO(AC) = EXTEND32 (prod); + DSPHI(AC) = EXTEND32 (prod >> 32); +} + +011111,5.RS,5.RT,5.RD,01101,010001:SPECIAL3:32::PRECR.QB.PH +"precr.qb.ph r, r, r" +*dsp2: +{ + unsigned32 v1 = GPR[RS]; + unsigned32 v2 = GPR[RT]; + unsigned32 tempu = (v1 & 0xff0000) >> 16; + unsigned32 tempv = (v1 & 0xff); + unsigned32 tempw = (v2 & 0xff0000) >> 16; + unsigned32 tempx = (v2 & 0xff); + GPR[RD] = EXTEND32 ((tempu << 24) | (tempv << 16) | (tempw << 8) | tempx); +} + +011111,5.RS,5.RT,5.SA,11110,010001:SPECIAL3:32::PRECR_SRA.PH.W +"precr_sra.ph.w r, r, " +*dsp2: +{ + do_precr_sra (SD_, RT, RS, SA, 0); +} + +011111,5.RS,5.RT,5.SA,11111,010001:SPECIAL3:32::PRECR_SRA_R.PH.W +"precr_sra_r.ph.w r, r, " +*dsp2: +{ + do_precr_sra (SD_, RT, RS, SA, 1); +} + +011111,5.RS,5.RT,5.SA,00001,110001:SPECIAL3:32::PREPEND +"prepend r, r, " +*dsp2: +{ + unsigned32 v0 = GPR[RS]; + unsigned32 v1 = GPR[RT]; + unsigned32 result; + if (SA == 0) + result = v1; + else + result = (v0 << (32 - SA)) | (v1 >> SA); + GPR[RT] = EXTEND32 (result); +} + +011111,00,3.SHIFT3,5.RT,5.RD,00100,010011:SPECIAL3:32::SHRA.QB +"shra.qb r, r, " +*dsp2: +{ + do_qb_shra (SD_, RD, RT, SHIFT3, 0); +} + +011111,00,3.SHIFT3,5.RT,5.RD,00101,010011:SPECIAL3:32::SHRA_R.QB +"shra_r.qb r, r, " +*dsp2: +{ + do_qb_shra (SD_, RD, RT, SHIFT3, 1); +} + +011111,5.RS,5.RT,5.RD,00110,010011:SPECIAL3:32::SHRAV.QB +"shrav.qb r, r, r" +*dsp2: +{ + unsigned32 shift = GPR[RS] & 0x7; + do_qb_shra (SD_, RD, RT, shift, 0); +} + +011111,5.RS,5.RT,5.RD,00111,010011:SPECIAL3:32::SHRAV_R.QB +"shrav_r.qb r, r, r" +*dsp2: +{ + unsigned32 shift = GPR[RS] & 0x7; + do_qb_shra (SD_, RD, RT, shift, 1); +} + +011111,0,4.SHIFT4,5.RT,5.RD,11001,010011:SPECIAL3:32::SHRL.PH +"shrl.ph r, r, " +*dsp2: +{ + do_ph_shrl (SD_, RD, RT, SHIFT4); +} + +011111,5.RS,5.RT,5.RD,11011,010011:SPECIAL3:32::SHRLV.PH +"shrlv.ph r, r, r" +*dsp2: +{ + unsigned32 shift = GPR[RS] & 0xf; + do_ph_shrl (SD_, RD, RT, shift); +} + +011111,5.RS,5.RT,5.RD,01001,010000:SPECIAL3:32::SUBU.PH +"subu.ph r, r, r" +*dsp2: +{ + do_u_ph_op (SD_, RD, RS, RT, 1, 0); +} + +011111,5.RS,5.RT,5.RD,01101,010000:SPECIAL3:32::SUBU_S.PH +"subu_s.ph r, r, r" +*dsp2: +{ + do_u_ph_op (SD_, RD, RS, RT, 1, 1); +} + +011111,5.RS,5.RT,5.RD,00001,011000:SPECIAL3:32::SUBUH.QB +"subuh.qb r, r, r" +*dsp2: +{ + do_uh_qb_op (SD_, RD, RS, RT, 1, 0); +} + +011111,5.RS,5.RT,5.RD,00011,011000:SPECIAL3:32::SUBUH_R.QB +"subuh_r.qb r, r, r" +*dsp2: +{ + do_uh_qb_op (SD_, RD, RS, RT, 1, 1); +} + +011111,5.RS,5.RT,5.RD,01000,011000:SPECIAL3:32::ADDQH.PH +"addqh.ph r, r, r" +*dsp2: +{ + do_qh_ph_op (SD_, RD, RS, RT, 0, 0); +} + +011111,5.RS,5.RT,5.RD,01010,011000:SPECIAL3:32::ADDQH_R.PH +"addqh_r.ph r, r, r" +*dsp2: +{ + do_qh_ph_op (SD_, RD, RS, RT, 0, 1); +} + +011111,5.RS,5.RT,5.RD,10000,011000:SPECIAL3:32::ADDQH.W +"addqh.w r, r, r" +*dsp2: +{ + do_qh_w_op (SD_, RD, RS, RT, 0, 0); +} + +011111,5.RS,5.RT,5.RD,10010,011000:SPECIAL3:32::ADDQH_R.W +"addqh_r.w r, r, r" +*dsp2: +{ + do_qh_w_op (SD_, RD, RS, RT, 0, 1); +} + +011111,5.RS,5.RT,5.RD,01001,011000:SPECIAL3:32::SUBQH.PH +"subqh.ph r, r, r" +*dsp2: +{ + do_qh_ph_op (SD_, RD, RS, RT, 1, 0); +} + +011111,5.RS,5.RT,5.RD,01011,011000:SPECIAL3:32::SUBQH_R.PH +"subqh_r.ph r, r, r" +*dsp2: +{ + do_qh_ph_op (SD_, RD, RS, RT, 1, 1); +} + +011111,5.RS,5.RT,5.RD,10001,011000:SPECIAL3:32::SUBQH.W +"subqh.w r, r, r" +*dsp2: +{ + do_qh_w_op (SD_, RD, RS, RT, 1, 0); +} + +011111,5.RS,5.RT,5.RD,10011,011000:SPECIAL3:32::SUBQH_R.W +"subqh_r.w r, r, r" +*dsp2: +{ + do_qh_w_op (SD_, RD, RS, RT, 1, 1); +} + +011111,5.RS,5.RT,000,2.AC,01000,110000:SPECIAL3:32::DPAX.W.PH +"dpax.w.ph ac, r, r" +*dsp2: +{ + do_x_w_ph_dot_product (SD_, AC, RS, RT, 0); +} + +011111,5.RS,5.RT,000,2.AC,01001,110000:SPECIAL3:32::DPSX.W.PH +"dpsx.w.ph ac, r, r" +*dsp2: +{ + do_x_w_ph_dot_product (SD_, AC, RS, RT, 1); +} + +011111,5.RS,5.RT,000,2.AC,11000,110000:SPECIAL3:32::DPAQX_S.W.PH +"dpaqx_s.w.ph ac, r, r" +*dsp2: +{ + do_qx_w_ph_dot_product (SD_, AC, RS, RT, 0, 0); +} + +011111,5.RS,5.RT,000,2.AC,11010,110000:SPECIAL3:32::DPAQX_SA.W.PH +"dpaqx_sa.w.ph ac, r, r" +*dsp2: +{ + do_qx_w_ph_dot_product (SD_, AC, RS, RT, 0, 1); +} + +011111,5.RS,5.RT,000,2.AC,11001,110000:SPECIAL3:32::DPSQX_S.W.PH +"dpsqx_s.w.ph ac, r, r" +*dsp2: +{ + do_qx_w_ph_dot_product (SD_, AC, RS, RT, 1, 0); +} + +011111,5.RS,5.RT,000,2.AC,11011,110000:SPECIAL3:32::DPSQX_SA.W.PH +"dpsqx_sa.w.ph ac, r, r" +*dsp2: +{ + do_qx_w_ph_dot_product (SD_, AC, RS, RT, 1, 1); +} Index: sim-main.c =================================================================== --- sim-main.c (nonexistent) +++ sim-main.c (revision 33) @@ -0,0 +1,564 @@ +/* Copyright (C) 1998, Cygnus Solutions + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + */ + + +#ifndef SIM_MAIN_C +#define SIM_MAIN_C + +#include "sim-main.h" +#include "sim-assert.h" + + +/*---------------------------------------------------------------------------*/ +/*-- simulator engine -------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ + + +/* Description from page A-22 of the "MIPS IV Instruction Set" manual + (revision 3.1) */ +/* Translate a virtual address to a physical address and cache + coherence algorithm describing the mechanism used to resolve the + memory reference. Given the virtual address vAddr, and whether the + reference is to Instructions ot Data (IorD), find the corresponding + physical address (pAddr) and the cache coherence algorithm (CCA) + used to resolve the reference. If the virtual address is in one of + the unmapped address spaces the physical address and the CCA are + determined directly by the virtual address. If the virtual address + is in one of the mapped address spaces then the TLB is used to + determine the physical address and access type; if the required + translation is not present in the TLB or the desired access is not + permitted the function fails and an exception is taken. + + NOTE: Normally (RAW == 0), when address translation fails, this + function raises an exception and does not return. */ + +INLINE_SIM_MAIN +(int) +address_translation (SIM_DESC sd, + sim_cpu * cpu, + address_word cia, + address_word vAddr, + int IorD, + int LorS, + address_word * pAddr, + int *CCA, + int raw) +{ + int res = -1; /* TRUE : Assume good return */ + +#ifdef DEBUG + sim_io_printf (sd, "AddressTranslation(0x%s,%s,%s,...);\n", pr_addr (vAddr), (IorD ? "isDATA" : "isINSTRUCTION"), (LorS ? "iSTORE" : "isLOAD")); +#endif + + /* Check that the address is valid for this memory model */ + + /* For a simple (flat) memory model, we simply pass virtual + addressess through (mostly) unchanged. */ + vAddr &= 0xFFFFFFFF; + + *pAddr = vAddr; /* default for isTARGET */ + *CCA = Uncached; /* not used for isHOST */ + + return (res); +} + + + +/* Description from page A-23 of the "MIPS IV Instruction Set" manual + (revision 3.1) */ +/* Prefetch data from memory. Prefetch is an advisory instruction for + which an implementation specific action is taken. The action taken + may increase performance, but must not change the meaning of the + program, or alter architecturally-visible state. */ + +INLINE_SIM_MAIN (void) +prefetch (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + int CCA, + address_word pAddr, + address_word vAddr, + int DATA, + int hint) +{ +#ifdef DEBUG + sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint); +#endif /* DEBUG */ + + /* For our simple memory model we do nothing */ + return; +} + +/* Description from page A-22 of the "MIPS IV Instruction Set" manual + (revision 3.1) */ +/* Load a value from memory. Use the cache and main memory as + specified in the Cache Coherence Algorithm (CCA) and the sort of + access (IorD) to find the contents of AccessLength memory bytes + starting at physical location pAddr. The data is returned in the + fixed width naturally-aligned memory element (MemElem). The + low-order two (or three) bits of the address and the AccessLength + indicate which of the bytes within MemElem needs to be given to the + processor. If the memory access type of the reference is uncached + then only the referenced bytes are read from memory and valid + within the memory element. If the access type is cached, and the + data is not present in cache, an implementation specific size and + alignment block of memory is read and loaded into the cache to + satisfy a load reference. At a minimum, the block is the entire + memory element. */ +INLINE_SIM_MAIN (void) +load_memory (SIM_DESC SD, + sim_cpu *CPU, + address_word cia, + uword64* memvalp, + uword64* memval1p, + int CCA, + unsigned int AccessLength, + address_word pAddr, + address_word vAddr, + int IorD) +{ + uword64 value = 0; + uword64 value1 = 0; + +#ifdef DEBUG + sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION")); +#endif /* DEBUG */ + +#if defined(WARN_MEM) + if (CCA != uncached) + sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); +#endif /* WARN_MEM */ + + if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) + { + /* In reality this should be a Bus Error */ + sim_io_error (SD, "LOAD AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s\n", + AccessLength, + (LOADDRMASK + 1) << 3, + pr_addr (pAddr)); + } + +#if defined(TRACE) + dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction")); +#endif /* TRACE */ + + /* Read the specified number of bytes from memory. Adjust for + host/target byte ordering/ Align the least significant byte + read. */ + + switch (AccessLength) + { + case AccessLength_QUADWORD: + { + unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr); + value1 = VH8_16 (val); + value = VL8_16 (val); + break; + } + case AccessLength_DOUBLEWORD: + value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr); + break; + case AccessLength_SEPTIBYTE: + value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr); + break; + case AccessLength_SEXTIBYTE: + value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr); + break; + case AccessLength_QUINTIBYTE: + value = sim_core_read_misaligned_5 (CPU, cia, read_map, pAddr); + break; + case AccessLength_WORD: + value = sim_core_read_aligned_4 (CPU, cia, read_map, pAddr); + break; + case AccessLength_TRIPLEBYTE: + value = sim_core_read_misaligned_3 (CPU, cia, read_map, pAddr); + break; + case AccessLength_HALFWORD: + value = sim_core_read_aligned_2 (CPU, cia, read_map, pAddr); + break; + case AccessLength_BYTE: + value = sim_core_read_aligned_1 (CPU, cia, read_map, pAddr); + break; + default: + abort (); + } + +#ifdef DEBUG + printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n", + (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value)); +#endif /* DEBUG */ + + /* See also store_memory. Position data in correct byte lanes. */ + if (AccessLength <= LOADDRMASK) + { + if (BigEndianMem) + /* for big endian target, byte (pAddr&LOADDRMASK == 0) is + shifted to the most significant byte position. */ + value <<= (((LOADDRMASK - (pAddr & LOADDRMASK)) - AccessLength) * 8); + else + /* For little endian target, byte (pAddr&LOADDRMASK == 0) + is already in the correct postition. */ + value <<= ((pAddr & LOADDRMASK) * 8); + } + +#ifdef DEBUG + printf("DBG: LoadMemory() : shifted value = 0x%s%s\n", + pr_uword64(value1),pr_uword64(value)); +#endif /* DEBUG */ + + *memvalp = value; + if (memval1p) *memval1p = value1; +} + + +/* Description from page A-23 of the "MIPS IV Instruction Set" manual + (revision 3.1) */ +/* Store a value to memory. The specified data is stored into the + physical location pAddr using the memory hierarchy (data caches and + main memory) as specified by the Cache Coherence Algorithm + (CCA). The MemElem contains the data for an aligned, fixed-width + memory element (word for 32-bit processors, doubleword for 64-bit + processors), though only the bytes that will actually be stored to + memory need to be valid. The low-order two (or three) bits of pAddr + and the AccessLength field indicates which of the bytes within the + MemElem data should actually be stored; only these bytes in memory + will be changed. */ + +INLINE_SIM_MAIN (void) +store_memory (SIM_DESC SD, + sim_cpu *CPU, + address_word cia, + int CCA, + unsigned int AccessLength, + uword64 MemElem, + uword64 MemElem1, /* High order 64 bits */ + address_word pAddr, + address_word vAddr) +{ +#ifdef DEBUG + sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr)); +#endif /* DEBUG */ + +#if defined(WARN_MEM) + if (CCA != uncached) + sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA); +#endif /* WARN_MEM */ + + if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) + sim_io_error (SD, "STORE AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s\n", + AccessLength, + (LOADDRMASK + 1) << 3, + pr_addr(pAddr)); + +#if defined(TRACE) + dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store"); +#endif /* TRACE */ + +#ifdef DEBUG + printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem)); +#endif /* DEBUG */ + + /* See also load_memory. Position data in correct byte lanes. */ + if (AccessLength <= LOADDRMASK) + { + if (BigEndianMem) + /* for big endian target, byte (pAddr&LOADDRMASK == 0) is + shifted to the most significant byte position. */ + MemElem >>= (((LOADDRMASK - (pAddr & LOADDRMASK)) - AccessLength) * 8); + else + /* For little endian target, byte (pAddr&LOADDRMASK == 0) + is already in the correct postition. */ + MemElem >>= ((pAddr & LOADDRMASK) * 8); + } + +#ifdef DEBUG + printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem)); +#endif /* DEBUG */ + + switch (AccessLength) + { + case AccessLength_QUADWORD: + { + unsigned_16 val = U16_8 (MemElem1, MemElem); + sim_core_write_aligned_16 (CPU, cia, write_map, pAddr, val); + break; + } + case AccessLength_DOUBLEWORD: + sim_core_write_aligned_8 (CPU, cia, write_map, pAddr, MemElem); + break; + case AccessLength_SEPTIBYTE: + sim_core_write_misaligned_7 (CPU, cia, write_map, pAddr, MemElem); + break; + case AccessLength_SEXTIBYTE: + sim_core_write_misaligned_6 (CPU, cia, write_map, pAddr, MemElem); + break; + case AccessLength_QUINTIBYTE: + sim_core_write_misaligned_5 (CPU, cia, write_map, pAddr, MemElem); + break; + case AccessLength_WORD: + sim_core_write_aligned_4 (CPU, cia, write_map, pAddr, MemElem); + break; + case AccessLength_TRIPLEBYTE: + sim_core_write_misaligned_3 (CPU, cia, write_map, pAddr, MemElem); + break; + case AccessLength_HALFWORD: + sim_core_write_aligned_2 (CPU, cia, write_map, pAddr, MemElem); + break; + case AccessLength_BYTE: + sim_core_write_aligned_1 (CPU, cia, write_map, pAddr, MemElem); + break; + default: + abort (); + } + + return; +} + + +INLINE_SIM_MAIN (unsigned32) +ifetch32 (SIM_DESC SD, + sim_cpu *CPU, + address_word cia, + address_word vaddr) +{ + /* Copy the action of the LW instruction */ + address_word mask = LOADDRMASK; + address_word access = AccessLength_WORD; + address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); + address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); + unsigned int byte; + address_word paddr; + int uncached; + unsigned64 memval; + + if ((vaddr & access) != 0) + SignalExceptionInstructionFetch (); + AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL); + paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); + LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isINSTRUCTION, isREAL); + byte = ((vaddr & mask) ^ bigendiancpu); + return (memval >> (8 * byte)); +} + + +INLINE_SIM_MAIN (unsigned16) +ifetch16 (SIM_DESC SD, + sim_cpu *CPU, + address_word cia, + address_word vaddr) +{ + /* Copy the action of the LH instruction */ + address_word mask = LOADDRMASK; + address_word access = AccessLength_HALFWORD; + address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); + address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); + unsigned int byte; + address_word paddr; + int uncached; + unsigned64 memval; + + if ((vaddr & access) != 0) + SignalExceptionInstructionFetch (); + AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL); + paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); + LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isINSTRUCTION, isREAL); + byte = ((vaddr & mask) ^ bigendiancpu); + return (memval >> (8 * byte)); +} + + + +/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */ +/* Order loads and stores to synchronise shared memory. Perform the + action necessary to make the effects of groups of synchronizable + loads and stores indicated by stype occur in the same order for all + processors. */ +INLINE_SIM_MAIN (void) +sync_operation (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + int stype) +{ +#ifdef DEBUG + sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype); +#endif /* DEBUG */ + return; +} + +INLINE_SIM_MAIN (void) +cache_op (SIM_DESC SD, + sim_cpu *CPU, + address_word cia, + int op, + address_word pAddr, + address_word vAddr, + unsigned int instruction) +{ +#if 1 /* stop warning message being displayed (we should really just remove the code) */ + static int icache_warning = 1; + static int dcache_warning = 1; +#else + static int icache_warning = 0; + static int dcache_warning = 0; +#endif + + /* If CP0 is not useable (User or Supervisor mode) and the CP0 + enable bit in the Status Register is clear - a coprocessor + unusable exception is taken. */ +#if 0 + sim_io_printf(SD,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia)); +#endif + + switch (op & 0x3) { + case 0: /* instruction cache */ + switch (op >> 2) { + case 0: /* Index Invalidate */ + case 1: /* Index Load Tag */ + case 2: /* Index Store Tag */ + case 4: /* Hit Invalidate */ + case 5: /* Fill */ + case 6: /* Hit Writeback */ + if (!icache_warning) + { + sim_io_eprintf(SD,"Instruction CACHE operation %d to be coded\n",(op >> 2)); + icache_warning = 1; + } + break; + + default: + SignalException(ReservedInstruction,instruction); + break; + } + break; + + case 1: /* data cache */ + case 3: /* secondary data cache */ + switch (op >> 2) { + case 0: /* Index Writeback Invalidate */ + case 1: /* Index Load Tag */ + case 2: /* Index Store Tag */ + case 3: /* Create Dirty */ + case 4: /* Hit Invalidate */ + case 5: /* Hit Writeback Invalidate */ + case 6: /* Hit Writeback */ + if (!dcache_warning) + { + sim_io_eprintf(SD,"Data CACHE operation %d to be coded\n",(op >> 2)); + dcache_warning = 1; + } + break; + + default: + SignalException(ReservedInstruction,instruction); + break; + } + break; + + default: /* unrecognised cache ID */ + SignalException(ReservedInstruction,instruction); + break; + } + + return; +} + + +INLINE_SIM_MAIN (void) +pending_tick (SIM_DESC SD, + sim_cpu *CPU, + address_word cia) +{ + if (PENDING_TRACE) + sim_io_eprintf (SD, "PENDING_DRAIN - 0x%lx - pending_in = %d, pending_out = %d, pending_total = %d\n", (unsigned long) cia, PENDING_IN, PENDING_OUT, PENDING_TOTAL); + if (PENDING_OUT != PENDING_IN) + { + int loop; + int index = PENDING_OUT; + int total = PENDING_TOTAL; + if (PENDING_TOTAL == 0) + sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n"); + for (loop = 0, index = PENDING_OUT; + (loop < total); + loop++, index = (index + 1) % PSLOTS) + { + if (PENDING_SLOT_DEST[index] != NULL) + { + PENDING_SLOT_DELAY[index] -= 1; + if (PENDING_SLOT_DELAY[index] == 0) + { + if (PENDING_TRACE) + sim_io_eprintf (SD, "PENDING_DRAIN - drained - index %d, dest 0x%lx, bit %d, val 0x%lx, size %d\n", + index, + (unsigned long) PENDING_SLOT_DEST[index], + PENDING_SLOT_BIT[index], + (unsigned long) PENDING_SLOT_VALUE[index], + PENDING_SLOT_SIZE[index]); + if (PENDING_SLOT_BIT[index] >= 0) + switch (PENDING_SLOT_SIZE[index]) + { + case 4: + if (PENDING_SLOT_VALUE[index]) + *(unsigned32*)PENDING_SLOT_DEST[index] |= + BIT32 (PENDING_SLOT_BIT[index]); + else + *(unsigned32*)PENDING_SLOT_DEST[index] &= + BIT32 (PENDING_SLOT_BIT[index]); + break; + case 8: + if (PENDING_SLOT_VALUE[index]) + *(unsigned64*)PENDING_SLOT_DEST[index] |= + BIT64 (PENDING_SLOT_BIT[index]); + else + *(unsigned64*)PENDING_SLOT_DEST[index] &= + BIT64 (PENDING_SLOT_BIT[index]); + break; + } + else + switch (PENDING_SLOT_SIZE[index]) + { + case 4: + *(unsigned32*)PENDING_SLOT_DEST[index] = + PENDING_SLOT_VALUE[index]; + break; + case 8: + *(unsigned64*)PENDING_SLOT_DEST[index] = + PENDING_SLOT_VALUE[index]; + break; + } + if (PENDING_OUT == index) + { + PENDING_SLOT_DEST[index] = NULL; + PENDING_OUT = (PENDING_OUT + 1) % PSLOTS; + PENDING_TOTAL--; + } + } + else if (PENDING_TRACE && PENDING_SLOT_DELAY[index] > 0) + sim_io_eprintf (SD, "PENDING_DRAIN - queued - index %d, delay %d, dest 0x%lx, bit %d, val 0x%lx, size %d\n", + index, PENDING_SLOT_DELAY[index], + (unsigned long) PENDING_SLOT_DEST[index], + PENDING_SLOT_BIT[index], + (unsigned long) PENDING_SLOT_VALUE[index], + PENDING_SLOT_SIZE[index]); + + } + } + } +} + + +#endif
sim-main.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: mips.dc =================================================================== --- mips.dc (nonexistent) +++ mips.dc (revision 33) @@ -0,0 +1,16 @@ +# most instructions +# ------ options ------ : Fst : Lst : ff : fl : fe : word : --- fmt --- : model ... +# { : mask : value : word } + +# Top level - create a very big switch statement. + + padded-switch,combine : 31 : 26 : : : : : : + + switch,combine : 5 : 0 : : : : : : + + switch,combine : 20 : 16 : : : : : : + + switch,combine : 25 : 21 : : : : : : + + switch,combine : 10 : 6 : : : : : : + Index: tconfig.in =================================================================== --- tconfig.in (nonexistent) +++ tconfig.in (revision 33) @@ -0,0 +1,36 @@ +/* mips target configuration file. */ + +/* See sim-hload.c. We properly handle LMA. */ +#ifdef TARGET_TX3904 +#define SIM_HANDLES_LMA 1 + +/* FIXME: This is unnecessarily necessary: */ +#include "ansidecl.h" +#include "gdb/callback.h" +#include "gdb/remote-sim.h" +#include "sim-module.h" + +MODULE_INSTALL_FN dv_sockser_install; +#define MODULE_LIST dv_sockser_install, +#else +#define SIM_HANDLES_LMA 0 +#endif + +/* Define this if the simulator supports profiling. + See the mips simulator for an example. + This enables the `-p foo' and `-s bar' options. + The target is required to provide sim_set_profile{,_size}. */ +#define SIM_HAVE_PROFILE + +/* Define this if the simulator uses an instruction cache. + See the h8/300 simulator for an example. + This enables the `-c size' option to set the size of the cache. + The target is required to provide sim_set_simcache_size. */ +/* #define SIM_HAVE_SIMCACHE */ + +/* Define this if the target cpu is bi-endian + and the simulator supports it. */ +#define SIM_HAVE_BIENDIAN + +/* MIPS uses an unusual format for floating point quiet NaNs. */ +#define SIM_QUIET_NAN_NEGATED Index: sim-main.h =================================================================== --- sim-main.h (nonexistent) +++ sim-main.h (revision 33) @@ -0,0 +1,1020 @@ +/* MIPS Simulator definition. + Copyright (C) 1997, 1998, 2003, 2007, 2008 Free Software Foundation, Inc. + Contributed by Cygnus Support. + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +#ifndef SIM_MAIN_H +#define SIM_MAIN_H + +/* This simulator doesn't cache the Current Instruction Address */ +/* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */ +/* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */ + +#define SIM_HAVE_BIENDIAN + + +/* hobble some common features for moment */ +#define WITH_WATCHPOINTS 1 +#define WITH_MODULO_MEMORY 1 + + +#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ +mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR)) + +#include "sim-basics.h" + +typedef address_word sim_cia; + +#include "sim-base.h" +#include "bfd.h" + +/* Deprecated macros and types for manipulating 64bit values. Use + ../common/sim-bits.h and ../common/sim-endian.h macros instead. */ + +typedef signed64 word64; +typedef unsigned64 uword64; + +#define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF) +#define WORD64HI(t) (unsigned int)(((uword64)(t))>>32) +#define SET64LO(t) (((uword64)(t))&0xFFFFFFFF) +#define SET64HI(t) (((uword64)(t))<<32) +#define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l)))) +#define UWORD64(h,l) (SET64HI(h)|SET64LO(l)) + +/* Check if a value will fit within a halfword: */ +#define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1)) + + + +/* Floating-point operations: */ + +#include "sim-fpu.h" +#include "cp1.h" + +/* FPU registers must be one of the following types. All other values + are reserved (and undefined). */ +typedef enum { + fmt_single = 0, + fmt_double = 1, + fmt_word = 4, + fmt_long = 5, + fmt_ps = 6, + /* The following are well outside the normal acceptable format + range, and are used in the register status vector. */ + fmt_unknown = 0x10000000, + fmt_uninterpreted = 0x20000000, + fmt_uninterpreted_32 = 0x40000000, + fmt_uninterpreted_64 = 0x80000000U, +} FP_formats; + +/* For paired word (pw) operations, the opcode representation is fmt_word, + but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long. */ +#define fmt_pw fmt_long + +/* This should be the COC1 value at the start of the preceding + instruction: */ +#define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0) + +#ifdef TARGET_ENABLE_FR +/* FIXME: this should be enabled for all targets, but needs testing first. */ +#define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \ + ? ((SR & status_FR) ? 64 : 32) \ + : (WITH_TARGET_FLOATING_POINT_BITSIZE)) +#else +#define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE) +#endif + + + + + +/* HI/LO register accesses */ + +/* For some MIPS targets, the HI/LO registers have certain timing + restrictions in that, for instance, a read of a HI register must be + separated by at least three instructions from a preceeding read. + + The struct below is used to record the last access by each of A MT, + MF or other OP instruction to a HI/LO register. See mips.igen for + more details. */ + +typedef struct _hilo_access { + signed64 timestamp; + address_word cia; +} hilo_access; + +typedef struct _hilo_history { + hilo_access mt; + hilo_access mf; + hilo_access op; +} hilo_history; + + + + +/* Integer ALU operations: */ + +#include "sim-alu.h" + +#define ALU32_END(ANS) \ + if (ALU32_HAD_OVERFLOW) \ + SignalExceptionIntegerOverflow (); \ + (ANS) = (signed32) ALU32_OVERFLOW_RESULT + + +#define ALU64_END(ANS) \ + if (ALU64_HAD_OVERFLOW) \ + SignalExceptionIntegerOverflow (); \ + (ANS) = ALU64_OVERFLOW_RESULT; + + + + + +/* The following is probably not used for MIPS IV onwards: */ +/* Slots for delayed register updates. For the moment we just have a + fixed number of slots (rather than a more generic, dynamic + system). This keeps the simulator fast. However, we only allow + for the register update to be delayed for a single instruction + cycle. */ +#define PSLOTS (8) /* Maximum number of instruction cycles */ + +typedef struct _pending_write_queue { + int in; + int out; + int total; + int slot_delay[PSLOTS]; + int slot_size[PSLOTS]; + int slot_bit[PSLOTS]; + void *slot_dest[PSLOTS]; + unsigned64 slot_value[PSLOTS]; +} pending_write_queue; + +#ifndef PENDING_TRACE +#define PENDING_TRACE 0 +#endif +#define PENDING_IN ((CPU)->pending.in) +#define PENDING_OUT ((CPU)->pending.out) +#define PENDING_TOTAL ((CPU)->pending.total) +#define PENDING_SLOT_SIZE ((CPU)->pending.slot_size) +#define PENDING_SLOT_BIT ((CPU)->pending.slot_bit) +#define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay) +#define PENDING_SLOT_DEST ((CPU)->pending.slot_dest) +#define PENDING_SLOT_VALUE ((CPU)->pending.slot_value) + +/* Invalidate the pending write queue, all pending writes are + discarded. */ + +#define PENDING_INVALIDATE() \ +memset (&(CPU)->pending, 0, sizeof ((CPU)->pending)) + +/* Schedule a write to DEST for N cycles time. For 64 bit + destinations, schedule two writes. For floating point registers, + the caller should schedule a write to both the dest register and + the FPR_STATE register. When BIT is non-negative, only BIT of DEST + is updated. */ + +#define PENDING_SCHED(DEST,VAL,DELAY,BIT) \ + do { \ + if (PENDING_SLOT_DEST[PENDING_IN] != NULL) \ + sim_engine_abort (SD, CPU, cia, \ + "PENDING_SCHED - buffer overflow\n"); \ + if (PENDING_TRACE) \ + sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n", \ + (unsigned long) cia, (unsigned long) &(DEST), \ + (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\ + PENDING_IN, PENDING_OUT, PENDING_TOTAL); \ + PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1; \ + PENDING_SLOT_DEST[PENDING_IN] = &(DEST); \ + PENDING_SLOT_VALUE[PENDING_IN] = (VAL); \ + PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST); \ + PENDING_SLOT_BIT[PENDING_IN] = (BIT); \ + PENDING_IN = (PENDING_IN + 1) % PSLOTS; \ + PENDING_TOTAL += 1; \ + } while (0) + +#define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1) +#define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT) + +#define PENDING_TICK() pending_tick (SD, CPU, cia) + +#define PENDING_FLUSH() abort () /* think about this one */ +#define PENDING_FP() abort () /* think about this one */ + +/* For backward compatibility */ +#define PENDING_FILL(R,VAL) \ +do { \ + if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR) \ + { \ + PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1); \ + PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \ + } \ + else \ + PENDING_SCHED(GPR[(R)], VAL, 1, -1); \ +} while (0) + + +enum float_operation + { + FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD, + FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS, + FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23 + }; + + +/* The internal representation of an MDMX accumulator. + Note that 24 and 48 bit accumulator elements are represented in + 32 or 64 bits. Since the accumulators are 2's complement with + overflow suppressed, high-order bits can be ignored in most contexts. */ + +typedef signed32 signed24; +typedef signed64 signed48; + +typedef union { + signed24 ob[8]; + signed48 qh[4]; +} MDMX_accumulator; + + +/* Conventional system arguments. */ +#define SIM_STATE sim_cpu *cpu, address_word cia +#define SIM_ARGS CPU, cia + +struct _sim_cpu { + + + /* The following are internal simulator state variables: */ +#define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0) +#define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA)) + address_word dspc; /* delay-slot PC */ +#define DSPC ((CPU)->dspc) + +#define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET)) +#define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_) + + + /* State of the simulator */ + unsigned int state; + unsigned int dsstate; +#define STATE ((CPU)->state) +#define DSSTATE ((CPU)->dsstate) + +/* Flags in the "state" variable: */ +#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */ +#define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */ +#define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */ +#define simPCOC0 (1 << 17) /* COC[1] from current */ +#define simPCOC1 (1 << 18) /* COC[1] from previous */ +#define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */ +#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */ +#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */ +#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */ + +#ifndef ENGINE_ISSUE_PREFIX_HOOK +#define ENGINE_ISSUE_PREFIX_HOOK() \ + { \ + /* Perform any pending writes */ \ + PENDING_TICK(); \ + /* Set previous flag, depending on current: */ \ + if (STATE & simPCOC0) \ + STATE |= simPCOC1; \ + else \ + STATE &= ~simPCOC1; \ + /* and update the current value: */ \ + if (GETFCC(0)) \ + STATE |= simPCOC0; \ + else \ + STATE &= ~simPCOC0; \ + } +#endif /* ENGINE_ISSUE_PREFIX_HOOK */ + + +/* This is nasty, since we have to rely on matching the register + numbers used by GDB. Unfortunately, depending on the MIPS target + GDB uses different register numbers. We cannot just include the + relevant "gdb/tm.h" link, since GDB may not be configured before + the sim world, and also the GDB header file requires too much other + state. */ + +#ifndef TM_MIPS_H +#define LAST_EMBED_REGNUM (96) +#define NUM_REGS (LAST_EMBED_REGNUM + 1) + +#define FP0_REGNUM 38 /* Floating point register 0 (single float) */ +#define FCRCS_REGNUM 70 /* FP control/status */ +#define FCRIR_REGNUM 71 /* FP implementation/revision */ +#endif + + +/* To keep this default simulator simple, and fast, we use a direct + vector of registers. The internal simulator engine then uses + manifests to access the correct slot. */ + + unsigned_word registers[LAST_EMBED_REGNUM + 1]; + + int register_widths[NUM_REGS]; +#define REGISTERS ((CPU)->registers) + +#define GPR (®ISTERS[0]) +#define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL)) + +#define LO (REGISTERS[33]) +#define HI (REGISTERS[34]) +#define PCIDX 37 +#define PC (REGISTERS[PCIDX]) +#define CAUSE (REGISTERS[36]) +#define SRIDX (32) +#define SR (REGISTERS[SRIDX]) /* CPU status register */ +#define FCR0IDX (71) +#define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */ +#define FCR31IDX (70) +#define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */ +#define FCSR (FCR31) +#define Debug (REGISTERS[86]) +#define DEPC (REGISTERS[87]) +#define EPC (REGISTERS[88]) +#define ACX (REGISTERS[89]) + +#define AC0LOIDX (33) /* Must be the same register as LO */ +#define AC0HIIDX (34) /* Must be the same register as HI */ +#define AC1LOIDX (90) +#define AC1HIIDX (91) +#define AC2LOIDX (92) +#define AC2HIIDX (93) +#define AC3LOIDX (94) +#define AC3HIIDX (95) + +#define DSPLO(N) (REGISTERS[DSPLO_REGNUM[N]]) +#define DSPHI(N) (REGISTERS[DSPHI_REGNUM[N]]) + +#define DSPCRIDX (96) /* DSP control register */ +#define DSPCR (REGISTERS[DSPCRIDX]) + +#define DSPCR_POS_SHIFT (0) +#define DSPCR_POS_MASK (0x3f) +#define DSPCR_POS_SMASK (DSPCR_POS_MASK << DSPCR_POS_SHIFT) + +#define DSPCR_SCOUNT_SHIFT (7) +#define DSPCR_SCOUNT_MASK (0x3f) +#define DSPCR_SCOUNT_SMASK (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT) + +#define DSPCR_CARRY_SHIFT (13) +#define DSPCR_CARRY_MASK (1) +#define DSPCR_CARRY_SMASK (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT) +#define DSPCR_CARRY (1 << DSPCR_CARRY_SHIFT) + +#define DSPCR_EFI_SHIFT (14) +#define DSPCR_EFI_MASK (1) +#define DSPCR_EFI_SMASK (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT) +#define DSPCR_EFI (1 << DSPCR_EFI_MASK) + +#define DSPCR_OUFLAG_SHIFT (16) +#define DSPCR_OUFLAG_MASK (0xff) +#define DSPCR_OUFLAG_SMASK (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT) +#define DSPCR_OUFLAG4 (1 << (DSPCR_OUFLAG_SHIFT + 4)) +#define DSPCR_OUFLAG5 (1 << (DSPCR_OUFLAG_SHIFT + 5)) +#define DSPCR_OUFLAG6 (1 << (DSPCR_OUFLAG_SHIFT + 6)) +#define DSPCR_OUFLAG7 (1 << (DSPCR_OUFLAG_SHIFT + 7)) + +#define DSPCR_CCOND_SHIFT (24) +#define DSPCR_CCOND_MASK (0xf) +#define DSPCR_CCOND_SMASK (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT) + + /* All internal state modified by signal_exception() that may need to be + rolled back for passing moment-of-exception image back to gdb. */ + unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1]; + unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1]; + int exc_suspended; + +#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA) +#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC) +#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC) + + unsigned_word c0_config_reg; +#define C0_CONFIG ((CPU)->c0_config_reg) + +/* The following are pseudonyms for standard registers */ +#define ZERO (REGISTERS[0]) +#define V0 (REGISTERS[2]) +#define A0 (REGISTERS[4]) +#define A1 (REGISTERS[5]) +#define A2 (REGISTERS[6]) +#define A3 (REGISTERS[7]) +#define T8IDX 24 +#define T8 (REGISTERS[T8IDX]) +#define SPIDX 29 +#define SP (REGISTERS[SPIDX]) +#define RAIDX 31 +#define RA (REGISTERS[RAIDX]) + + /* While space is allocated in the main registers arrray for some of + the COP0 registers, that space isn't sufficient. Unknown COP0 + registers overflow into the array below */ + +#define NR_COP0_GPR 32 + unsigned_word cop0_gpr[NR_COP0_GPR]; +#define COP0_GPR ((CPU)->cop0_gpr) +#define COP0_BADVADDR (COP0_GPR[8]) + + /* While space is allocated for the floating point registers in the + main registers array, they are stored separatly. This is because + their size may not necessarily match the size of either the + general-purpose or system specific registers. */ +#define NR_FGR (32) +#define FGR_BASE FP0_REGNUM + fp_word fgr[NR_FGR]; +#define FGR ((CPU)->fgr) + + /* Keep the current format state for each register: */ + FP_formats fpr_state[32]; +#define FPR_STATE ((CPU)->fpr_state) + + pending_write_queue pending; + + /* The MDMX accumulator (used only for MDMX ASE). */ + MDMX_accumulator acc; +#define ACC ((CPU)->acc) + + /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic + read-write instructions. It is set when a linked load occurs. It + is tested and cleared by the conditional store. It is cleared + (during other CPU operations) when a store to the location would + no longer be atomic. In particular, it is cleared by exception + return instructions. */ + int llbit; +#define LLBIT ((CPU)->llbit) + + +/* The HIHISTORY and LOHISTORY timestamps are used to ensure that + corruptions caused by using the HI or LO register too close to a + following operation is spotted. See mips.igen for more details. */ + + hilo_history hi_history; +#define HIHISTORY (&(CPU)->hi_history) + hilo_history lo_history; +#define LOHISTORY (&(CPU)->lo_history) + + + sim_cpu_base base; +}; + + +/* MIPS specific simulator watch config */ + +void watch_options_install PARAMS ((SIM_DESC sd)); + +struct swatch { + sim_event *pc; + sim_event *clock; + sim_event *cycles; +}; + + +/* FIXME: At present much of the simulator is still static */ +struct sim_state { + + struct swatch watch; + + sim_cpu cpu[MAX_NR_PROCESSORS]; +#if (WITH_SMP) +#define STATE_CPU(sd,n) (&(sd)->cpu[n]) +#else +#define STATE_CPU(sd,n) (&(sd)->cpu[0]) +#endif + + + sim_state_base base; +}; + + + +/* Status information: */ + +/* TODO : these should be the bitmasks for these bits within the + status register. At the moment the following are VR4300 + bit-positions: */ +#define status_KSU_mask (0x18) /* mask for KSU bits */ +#define status_KSU_shift (3) /* shift for field */ +#define ksu_kernel (0x0) +#define ksu_supervisor (0x1) +#define ksu_user (0x2) +#define ksu_unknown (0x3) + +#define SR_KSU ((SR & status_KSU_mask) >> status_KSU_shift) + +#define status_IE (1 << 0) /* Interrupt enable */ +#define status_EIE (1 << 16) /* Enable Interrupt Enable */ +#define status_EXL (1 << 1) /* Exception level */ +#define status_RE (1 << 25) /* Reverse Endian in user mode */ +#define status_FR (1 << 26) /* enables MIPS III additional FP registers */ +#define status_SR (1 << 20) /* soft reset or NMI */ +#define status_BEV (1 << 22) /* Location of general exception vectors */ +#define status_TS (1 << 21) /* TLB shutdown has occurred */ +#define status_ERL (1 << 2) /* Error level */ +#define status_IM7 (1 << 15) /* Timer Interrupt Mask */ +#define status_RP (1 << 27) /* Reduced Power mode */ + +/* Specializations for TX39 family */ +#define status_IEc (1 << 0) /* Interrupt enable (current) */ +#define status_KUc (1 << 1) /* Kernel/User mode */ +#define status_IEp (1 << 2) /* Interrupt enable (previous) */ +#define status_KUp (1 << 3) /* Kernel/User mode */ +#define status_IEo (1 << 4) /* Interrupt enable (old) */ +#define status_KUo (1 << 5) /* Kernel/User mode */ +#define status_IM_mask (0xff) /* Interrupt mask */ +#define status_IM_shift (8) +#define status_NMI (1 << 20) /* NMI */ +#define status_NMI (1 << 20) /* NMI */ + +/* Status bits used by MIPS32/MIPS64. */ +#define status_UX (1 << 5) /* 64-bit user addrs */ +#define status_SX (1 << 6) /* 64-bit supervisor addrs */ +#define status_KX (1 << 7) /* 64-bit kernel addrs */ +#define status_TS (1 << 21) /* TLB shutdown has occurred */ +#define status_PX (1 << 23) /* Enable 64 bit operations */ +#define status_MX (1 << 24) /* Enable MDMX resources */ +#define status_CU0 (1 << 28) /* Coprocessor 0 usable */ +#define status_CU1 (1 << 29) /* Coprocessor 1 usable */ +#define status_CU2 (1 << 30) /* Coprocessor 2 usable */ +#define status_CU3 (1 << 31) /* Coprocessor 3 usable */ +/* Bits reserved for implementations: */ +#define status_SBX (1 << 16) /* Enable SiByte SB-1 extensions. */ + +#define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */ +#define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */ +#define cause_CE_mask 0x30000000 /* Coprocessor exception */ +#define cause_CE_shift 28 +#define cause_EXC2_mask 0x00070000 +#define cause_EXC2_shift 16 +#define cause_IP7 (1 << 15) /* Interrupt pending */ +#define cause_SIOP (1 << 12) /* SIO pending */ +#define cause_IP3 (1 << 11) /* Int 0 pending */ +#define cause_IP2 (1 << 10) /* Int 1 pending */ + +#define cause_EXC_mask (0x1c) /* Exception code */ +#define cause_EXC_shift (2) + +#define cause_SW0 (1 << 8) /* Software interrupt 0 */ +#define cause_SW1 (1 << 9) /* Software interrupt 1 */ +#define cause_IP_mask (0x3f) /* Interrupt pending field */ +#define cause_IP_shift (10) + +#define cause_set_EXC(x) CAUSE = (CAUSE & ~cause_EXC_mask) | ((x << cause_EXC_shift) & cause_EXC_mask) +#define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask) + + +/* NOTE: We keep the following status flags as bit values (1 for true, + 0 for false). This allows them to be used in binary boolean + operations without worrying about what exactly the non-zero true + value is. */ + +/* UserMode */ +#ifdef SUBTARGET_R3900 +#define UserMode ((SR & status_KUc) ? 1 : 0) +#else +#define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0) +#endif /* SUBTARGET_R3900 */ + +/* BigEndianMem */ +/* Hardware configuration. Affects endianness of LoadMemory and + StoreMemory and the endianness of Kernel and Supervisor mode + execution. The value is 0 for little-endian; 1 for big-endian. */ +#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) +/*(state & simBE) ? 1 : 0)*/ + +/* ReverseEndian */ +/* This mode is selected if in User mode with the RE bit being set in + SR (Status Register). It reverses the endianness of load and store + instructions. */ +#define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0) + +/* BigEndianCPU */ +/* The endianness for load and store instructions (0=little;1=big). In + User mode this endianness may be switched by setting the state_RE + bit in the SR register. Thus, BigEndianCPU may be computed as + (BigEndianMem EOR ReverseEndian). */ +#define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */ + + + +/* Exceptions: */ + +/* NOTE: These numbers depend on the processor architecture being + simulated: */ +enum ExceptionCause { + Interrupt = 0, + TLBModification = 1, + TLBLoad = 2, + TLBStore = 3, + AddressLoad = 4, + AddressStore = 5, + InstructionFetch = 6, + DataReference = 7, + SystemCall = 8, + BreakPoint = 9, + ReservedInstruction = 10, + CoProcessorUnusable = 11, + IntegerOverflow = 12, /* Arithmetic overflow (IDT monitor raises SIGFPE) */ + Trap = 13, + FPE = 15, + DebugBreakPoint = 16, /* Impl. dep. in MIPS32/MIPS64. */ + MDMX = 22, + Watch = 23, + MCheck = 24, + CacheErr = 30, + NMIReset = 31, /* Reserved in MIPS32/MIPS64. */ + + +/* The following exception code is actually private to the simulator + world. It is *NOT* a processor feature, and is used to signal + run-time errors in the simulator. */ + SimulatorFault = 0xFFFFFFFF +}; + +#define TLB_REFILL (0) +#define TLB_INVALID (1) + + +/* The following break instructions are reserved for use by the + simulator. The first is used to halt the simulation. The second + is used by gdb for break-points. NOTE: Care must be taken, since + this value may be used in later revisions of the MIPS ISA. */ +#define HALT_INSTRUCTION_MASK (0x03FFFFC0) + +#define HALT_INSTRUCTION (0x03ff000d) +#define HALT_INSTRUCTION2 (0x0000ffcd) + + +#define BREAKPOINT_INSTRUCTION (0x0005000d) +#define BREAKPOINT_INSTRUCTION2 (0x0000014d) + + + +void interrupt_event (SIM_DESC sd, void *data); + +void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...); +#define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction)) +#define SignalExceptionInterrupt(level) signal_exception (SD, CPU, cia, Interrupt, level) +#define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch) +#define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore) +#define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad) +#define SignalExceptionDataReference() signal_exception (SD, CPU, cia, DataReference) +#define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf) +#define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE) +#define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow) +#define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable) +#define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset) +#define SignalExceptionTLBRefillStore() signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL) +#define SignalExceptionTLBRefillLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL) +#define SignalExceptionTLBInvalidStore() signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID) +#define SignalExceptionTLBInvalidLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID) +#define SignalExceptionTLBModification() signal_exception (SD, CPU, cia, TLBModification) +#define SignalExceptionMDMX() signal_exception (SD, CPU, cia, MDMX) +#define SignalExceptionWatch() signal_exception (SD, CPU, cia, Watch) +#define SignalExceptionMCheck() signal_exception (SD, CPU, cia, MCheck) +#define SignalExceptionCacheErr() signal_exception (SD, CPU, cia, CacheErr) + +/* Co-processor accesses */ + +/* XXX FIXME: For now, assume that FPU (cp1) is always usable. */ +#define COP_Usable(coproc_num) (coproc_num == 1) + +void cop_lw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword)); +void cop_ld PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword)); +unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg)); +uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg)); + +#define COP_LW(coproc_num,coproc_reg,memword) \ +cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword) +#define COP_LD(coproc_num,coproc_reg,memword) \ +cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword) +#define COP_SW(coproc_num,coproc_reg) \ +cop_sw (SD, CPU, cia, coproc_num, coproc_reg) +#define COP_SD(coproc_num,coproc_reg) \ +cop_sd (SD, CPU, cia, coproc_num, coproc_reg) + + +void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction)); +#define DecodeCoproc(instruction) \ +decode_coproc (SD, CPU, cia, (instruction)) + +int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg); + + +/* FPR access. */ +unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats); +#define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT)) +void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value); +#define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE)) +unsigned64 ps_lower (SIM_STATE, unsigned64 op); +#define PSLower(op) ps_lower (SIM_ARGS, op) +unsigned64 ps_upper (SIM_STATE, unsigned64 op); +#define PSUpper(op) ps_upper (SIM_ARGS, op) +unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from); +#define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single) + + +/* FCR access. */ +unsigned_word value_fcr (SIM_STATE, int fcr); +#define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR)) +void store_fcr (SIM_STATE, int fcr, unsigned_word value); +#define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE)) +void test_fcsr (SIM_STATE); +#define TestFCSR() test_fcsr (SIM_ARGS) + + +/* FPU operations. */ +void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc); +#define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc) +unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt); +#define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt) +unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt); +#define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt) +unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt) +unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt) +unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt) +unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt) +unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt); +#define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt) +unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt); +#define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt) +unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt); +#define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt) +unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2, + unsigned64 op3, FP_formats fmt); +#define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt) +unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2, + unsigned64 op3, FP_formats fmt); +#define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt) +unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2, + unsigned64 op3, FP_formats fmt); +#define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt) +unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2, + unsigned64 op3, FP_formats fmt); +#define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt) +unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to); +#define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to) +unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from, + FP_formats to); +#define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to) + + +/* MIPS-3D ASE operations. */ +#define CompareAbs(op1,op2,fmt,cond,cc) \ +fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc) +unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt) +unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt) +unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt); +#define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt) +unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt) +unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt); +#define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt) +unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt) + + +/* MDMX access. */ + +typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */ +#define ob_fmtsel(sel) (((sel)<<1)|0x0) +#define qh_fmtsel(sel) (((sel)<<2)|0x1) + +#define fmt_mdmx fmt_uninterpreted + +#define MX_VECT_AND (0) +#define MX_VECT_NOR (1) +#define MX_VECT_OR (2) +#define MX_VECT_XOR (3) +#define MX_VECT_SLL (4) +#define MX_VECT_SRL (5) +#define MX_VECT_ADD (6) +#define MX_VECT_SUB (7) +#define MX_VECT_MIN (8) +#define MX_VECT_MAX (9) +#define MX_VECT_MUL (10) +#define MX_VECT_MSGN (11) +#define MX_VECT_SRA (12) +#define MX_VECT_ABSD (13) /* SB-1 only. */ +#define MX_VECT_AVG (14) /* SB-1 only. */ + +unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel); +#define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel) +#define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel) +#define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel) +#define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel) +#define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel) +#define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel) +#define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel) +#define MX_Or(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_OR, op1, vt, fmtsel) +#define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel) +#define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel) +#define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel) +#define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel) +#define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel) +#define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel) +#define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel) + +#define MX_C_EQ 0x1 +#define MX_C_LT 0x4 + +void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel); +#define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel) + +unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel); +#define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel) + +#define MX_VECT_ADDA (0) +#define MX_VECT_ADDL (1) +#define MX_VECT_MULA (2) +#define MX_VECT_MULL (3) +#define MX_VECT_MULS (4) +#define MX_VECT_MULSL (5) +#define MX_VECT_SUBA (6) +#define MX_VECT_SUBL (7) +#define MX_VECT_ABSDA (8) /* SB-1 only. */ + +void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel); +#define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel) +#define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel) +#define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel) +#define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel) +#define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel) +#define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel) +#define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel) +#define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel) +#define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel) + +#define MX_FMT_OB (0) +#define MX_FMT_QH (1) + +/* The following codes chosen to indicate the units of shift. */ +#define MX_RAC_L (0) +#define MX_RAC_M (1) +#define MX_RAC_H (2) + +unsigned64 mdmx_rac_op (SIM_STATE, int, int); +#define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt) + +void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64); +#define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt) +void mdmx_wach (SIM_STATE, int, unsigned64); +#define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs) + +#define MX_RND_AS (0) +#define MX_RND_AU (1) +#define MX_RND_ES (2) +#define MX_RND_EU (3) +#define MX_RND_ZS (4) +#define MX_RND_ZU (5) + +unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel); +#define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt) +#define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt) +#define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt) +#define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt) +#define MX_RZS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt) +#define MX_RZU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt) + +unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64); +#define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2) + + + +/* Memory accesses */ + +/* The following are generic to all versions of the MIPS architecture + to date: */ + +/* Memory Access Types (for CCA): */ +#define Uncached (0) +#define CachedNoncoherent (1) +#define CachedCoherent (2) +#define Cached (3) + +#define isINSTRUCTION (1 == 0) /* FALSE */ +#define isDATA (1 == 1) /* TRUE */ +#define isLOAD (1 == 0) /* FALSE */ +#define isSTORE (1 == 1) /* TRUE */ +#define isREAL (1 == 0) /* FALSE */ +#define isRAW (1 == 1) /* TRUE */ +/* The parameter HOST (isTARGET / isHOST) is ignored */ +#define isTARGET (1 == 0) /* FALSE */ +/* #define isHOST (1 == 1) TRUE */ + +/* The "AccessLength" specifications for Loads and Stores. NOTE: This + is the number of bytes minus 1. */ +#define AccessLength_BYTE (0) +#define AccessLength_HALFWORD (1) +#define AccessLength_TRIPLEBYTE (2) +#define AccessLength_WORD (3) +#define AccessLength_QUINTIBYTE (4) +#define AccessLength_SEXTIBYTE (5) +#define AccessLength_SEPTIBYTE (6) +#define AccessLength_DOUBLEWORD (7) +#define AccessLength_QUADWORD (15) + +#define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \ + ? AccessLength_DOUBLEWORD /*7*/ \ + : AccessLength_WORD /*3*/) +#define PSIZE (WITH_TARGET_ADDRESS_BITSIZE) + + +INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw)); +#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \ +address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw) + +INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD)); +#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \ +load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD) + +INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr)); +#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \ +store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr) + +INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction)); +#define CacheOp(op,pAddr,vAddr,instruction) \ +cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction) + +INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype)); +#define SyncOperation(stype) \ +sync_operation (SD, CPU, cia, (stype)) + +INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint)); +#define Prefetch(CCA,pAddr,vAddr,DATA,hint) \ +prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint) + +void unpredictable_action (sim_cpu *cpu, address_word cia); +#define NotWordValue(val) not_word_value (SD_, (val)) +#define Unpredictable() unpredictable (SD_) +#define UnpredictableResult() /* For now, do nothing. */ + +INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr)); +#define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA)) +INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr)); +#define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1)) +#define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR)) + +void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...)); +extern FILE *tracefh; + +extern int DSPLO_REGNUM[4]; +extern int DSPHI_REGNUM[4]; + +INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia)); +extern SIM_CORE_SIGNAL_FN mips_core_signal; + +char* pr_addr PARAMS ((SIM_ADDR addr)); +char* pr_uword64 PARAMS ((uword64 addr)); + + +#define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0) + +void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc); +void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception); +void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception); + +#ifdef MIPS_MACH_MULTI +extern int mips_mach_multi(SIM_DESC sd); +#define MIPS_MACH(SD) mips_mach_multi(SD) +#else +#define MIPS_MACH(SD) MIPS_MACH_DEFAULT +#endif + +/* Macros for determining whether a MIPS IV or MIPS V part is subject + to the hi/lo restrictions described in mips.igen. */ + +#define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \ + (MIPS_MACH (SD) != bfd_mach_mips5500) + +#define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \ + (MIPS_MACH (SD) != bfd_mach_mips5500) + +#define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \ + (MIPS_MACH (SD) != bfd_mach_mips5500) + +#if H_REVEALS_MODULE_P (SIM_MAIN_INLINE) +#include "sim-main.c" +#endif + +#endif
sim-main.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: smartmips.igen =================================================================== --- smartmips.igen (nonexistent) +++ smartmips.igen (revision 33) @@ -0,0 +1,122 @@ +// -*- C -*- +// +// Simulator definition for the SmartMIPS extensions. +// Copyright (C) 2005 Free Software Foundation, Inc. +// Contributed by Nigel Stephens (nigel@mips.com) and +// David Ung (davidu@mips.com) of MIPS Technologies. +// +// This file is part of GDB, the GNU debugger. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +011100,5.BASE,5.INDEX,5.RD,00010,001000:SPECIAL:32::LWXS +"lwxs r, (r)" +*smartmips: +{ + GPR[RD] = EXTEND32 (do_load(SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]<<2)); +} + +011100,5.RS,5.RT,00000,10001,000001:SPECIAL:32::MADDP +"maddp r, r" +*smartmips: +{ + unsigned64 res; + unsigned64 rs, rt; + int i; + + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + + res = 0; + rs = GPR[RS]; + rt = GPR[RT]; + for (i = 0; i < 32; i++) + { + if (rs & 1) + res ^= rt; + rs >>= 1; + rt <<= 1; + } + LO ^= EXTEND32 (VL4_8 (res)); + HI ^= EXTEND32 (VH4_8 (res)); + TRACE_ALU_RESULT2 (HI, LO); +} + + +000000,0000000000,5.RD,00001,010010:SPECIAL:32::MFLHXU +"mflhxu r" +*smartmips: +{ + check_mf_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT3 (ACX,HI,LO); + GPR[RD] = LO; + LO = HI; + HI = ACX; + ACX = 0; + TRACE_ALU_RESULT4 (ACX,HI,LO,GPR[RD]); +} + +000000,5.RS,000000000000001,010011:SPECIAL:32::MTLHX +"mtlhx r" +*smartmips: +{ + check_mf_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT3 (HI,LO,GPR[RS]); + ACX = HI; + HI = LO; + LO = GPR[RS]; + TRACE_ALU_RESULT4 (ACX,HI,LO,GPR[RS]); +} + +000000,5.RS,5.RT,00000,10001,011001:SPECIAL:32::MULTP +"multp r, r" +*smartmips: +{ + unsigned64 res; + unsigned64 rs, rt; + int i; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + + res = 0; + rs = GPR[RS]; + rt = GPR[RT]; + for (i = 0; i < 32; i++) + { + if (rs & 1) + res ^= rt; + rs >>= 1; + rt <<= 1; + } + LO = EXTEND32 (VL4_8 (res)); + HI = EXTEND32 (VH4_8 (res)); + ACX = 0; + TRACE_ALU_RESULT2 (HI, LO); +} + +011100,5.RS,5.RT,00000,10010,000001:SPECIAL:32::PPERM +"pperm r, r" +*smartmips: +{ + int i; + ACX = (ACX << 6) | MSEXTRACTED(HI,26,31); + HI = EXTEND32 ((HI << 6) | MSEXTRACTED(LO,26,31)); + LO = EXTEND32 (LO << 6); + for (i = 0; i < 6; i++) { + int sbit = 5*i; + int ebit = sbit + 4; + int tbit = EXTRACTED(GPR[RT],sbit,ebit); + LO |= MSEXTRACTED(GPR[RS],tbit,tbit) << i; + } +} Index: dv-tx3904irc.c =================================================================== --- dv-tx3904irc.c (nonexistent) +++ dv-tx3904irc.c (revision 33) @@ -0,0 +1,412 @@ +/* This file is part of the program GDB, the GNU debugger. + + Copyright (C) 1998, 2007, 2008 Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + */ + + +#include "sim-main.h" +#include "hw-main.h" + + +/* DEVICE + + + tx3904irc - tx3904 interrupt controller + + + DESCRIPTION + + + Implements the tx3904 interrupt controller described in the tx3904 + user guide. It does not include the interrupt detection circuit + that preprocesses the eight external interrupts, so assumes that + each event on an input interrupt port signals a new interrupt. + That is, it implements edge- rather than level-triggered + interrupts. + + This implementation does not support multiple concurrent + interrupts. + + + PROPERTIES + + + reg + + Base of IRC control register bank. must equal 0x20. + Registers offsets: 0: ISR: interrupt status register + 4: IMR: interrupt mask register + 16: ILR0: interrupt level register 3..0 + 20: ILR1: interrupt level register 7..4 + 24: ILR2: interrupt level register 11..8 + 28: ILR3: interrupt level register 15..12 + + + + PORTS + + + ip (output) + + Interrupt priority port. An event is generated when an interrupt + of a sufficient priority is passed through the IRC. The value + associated with the event is the interrupt level (16-31), as given + for bits IP[5:0] in the book TMPR3904F Rev. 2.0, pg. 11-3. Note + that even though INT[0] is tied externally to IP[5], we simulate + it as passing through the controller. + + An output level of zero signals the clearing of a level interrupt. + + + int0-7 (input) + + External interrupts. Level = 0 -> level interrupt cleared. + + + dmac0-3 (input) + + DMA internal interrupts, correspond to DMA channels 0-3. Level = 0 -> level interrupt cleared. + + + sio0-1 (input) + + SIO internal interrupts. Level = 0 -> level interrupt cleared. + + + tmr0-2 (input) + + Timer internal interrupts. Level = 0 -> level interrupt cleared. + + */ + + + + + +/* register numbers; each is one word long */ +enum +{ + ISR_REG = 0, + IMR_REG = 1, + ILR0_REG = 4, + ILR1_REG = 5, + ILR2_REG = 6, + ILR3_REG = 7, +}; + + +/* port ID's */ + +enum +{ + /* inputs, ordered to correspond to interrupt sources 0..15 */ + INT1_PORT = 0, INT2_PORT, INT3_PORT, INT4_PORT, INT5_PORT, INT6_PORT, INT7_PORT, + DMAC3_PORT, DMAC2_PORT, DMAC1_PORT, DMAC0_PORT, SIO0_PORT, SIO1_PORT, + TMR0_PORT, TMR1_PORT, TMR2_PORT, + + /* special INT[0] port */ + INT0_PORT, + + /* reset */ + RESET_PORT, + + /* output */ + IP_PORT +}; + + +static const struct hw_port_descriptor tx3904irc_ports[] = { + + /* interrupt output */ + + { "ip", IP_PORT, 0, output_port, }, + + /* interrupt inputs (as names) */ + /* in increasing order of level number */ + + { "int1", INT1_PORT, 0, input_port, }, + { "int2", INT2_PORT, 0, input_port, }, + { "int3", INT3_PORT, 0, input_port, }, + { "int4", INT4_PORT, 0, input_port, }, + { "int5", INT5_PORT, 0, input_port, }, + { "int6", INT6_PORT, 0, input_port, }, + { "int7", INT7_PORT, 0, input_port, }, + + { "dmac3", DMAC3_PORT, 0, input_port, }, + { "dmac2", DMAC2_PORT, 0, input_port, }, + { "dmac1", DMAC1_PORT, 0, input_port, }, + { "dmac0", DMAC0_PORT, 0, input_port, }, + + { "sio0", SIO0_PORT, 0, input_port, }, + { "sio1", SIO1_PORT, 0, input_port, }, + + { "tmr0", TMR0_PORT, 0, input_port, }, + { "tmr1", TMR1_PORT, 0, input_port, }, + { "tmr2", TMR2_PORT, 0, input_port, }, + + { "reset", RESET_PORT, 0, input_port, }, + { "int0", INT0_PORT, 0, input_port, }, + + { NULL, }, +}; + + +#define NR_SOURCES (TMR3_PORT - INT1_PORT + 1) /* 16: number of interrupt sources */ + + +/* The interrupt controller register internal state. Note that we + store state using the control register images, in host endian + order. */ + +struct tx3904irc { + address_word base_address; /* control register base */ + unsigned_4 isr; +#define ISR_SET(c,s) ((c)->isr &= ~ (1 << (s))) + unsigned_4 imr; +#define IMR_GET(c) ((c)->imr) + unsigned_4 ilr[4]; +#define ILR_GET(c,s) LSEXTRACTED32((c)->ilr[(s)/4], (s) % 4 * 8 + 2, (s) % 4 * 8) +}; + + + +/* Finish off the partially created hw device. Attach our local + callbacks. Wire up our port names etc */ + +static hw_io_read_buffer_method tx3904irc_io_read_buffer; +static hw_io_write_buffer_method tx3904irc_io_write_buffer; +static hw_port_event_method tx3904irc_port_event; + +static void +attach_tx3904irc_regs (struct hw *me, + struct tx3904irc *controller) +{ + unsigned_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain one addr/size entry"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, + &attach_address, + me); + hw_unit_size_to_attach_size (hw_parent (me), + ®.size, + &attach_size, me); + + hw_attach_address (hw_parent (me), 0, + attach_space, attach_address, attach_size, + me); + + controller->base_address = attach_address; +} + + +static void +tx3904irc_finish (struct hw *me) +{ + struct tx3904irc *controller; + + controller = HW_ZALLOC (me, struct tx3904irc); + set_hw_data (me, controller); + set_hw_io_read_buffer (me, tx3904irc_io_read_buffer); + set_hw_io_write_buffer (me, tx3904irc_io_write_buffer); + set_hw_ports (me, tx3904irc_ports); + set_hw_port_event (me, tx3904irc_port_event); + + /* Attach ourself to our parent bus */ + attach_tx3904irc_regs (me, controller); + + /* Initialize to reset state */ + controller->isr = 0x0000ffff; + controller->imr = 0; + controller->ilr[0] = + controller->ilr[1] = + controller->ilr[2] = + controller->ilr[3] = 0; +} + + + +/* An event arrives on an interrupt port */ + +static void +tx3904irc_port_event (struct hw *me, + int my_port, + struct hw *source_dev, + int source_port, + int level) +{ + struct tx3904irc *controller = hw_data (me); + + /* handle deactivated interrupt */ + if(level == 0) + { + HW_TRACE ((me, "interrupt cleared on port %d", my_port)); + hw_port_event(me, IP_PORT, 0); + return; + } + + switch (my_port) + { + case INT0_PORT: + { + int ip_number = 32; /* compute IP[5:0] */ + HW_TRACE ((me, "port-event INT[0]")); + hw_port_event(me, IP_PORT, ip_number); + break; + } + + case INT1_PORT: case INT2_PORT: case INT3_PORT: case INT4_PORT: + case INT5_PORT: case INT6_PORT: case INT7_PORT: case DMAC3_PORT: + case DMAC2_PORT: case DMAC1_PORT: case DMAC0_PORT: case SIO0_PORT: + case SIO1_PORT: case TMR0_PORT: case TMR1_PORT: case TMR2_PORT: + { + int source = my_port - INT1_PORT; + + HW_TRACE ((me, "interrupt asserted on port %d", source)); + ISR_SET(controller, source); + if(ILR_GET(controller, source) > IMR_GET(controller)) + { + int ip_number = 16 + source; /* compute IP[4:0] */ + HW_TRACE ((me, "interrupt level %d", ILR_GET(controller,source))); + hw_port_event(me, IP_PORT, ip_number); + } + break; + } + + case RESET_PORT: + { + HW_TRACE ((me, "reset")); + controller->isr = 0x0000ffff; + controller->imr = 0; + controller->ilr[0] = + controller->ilr[1] = + controller->ilr[2] = + controller->ilr[3] = 0; + break; + } + + case IP_PORT: + hw_abort (me, "Event on output port %d", my_port); + break; + + default: + hw_abort (me, "Event on unknown port %d", my_port); + break; + } +} + + +/* generic read/write */ + +static unsigned +tx3904irc_io_read_buffer (struct hw *me, + void *dest, + int space, + unsigned_word base, + unsigned nr_bytes) +{ + struct tx3904irc *controller = hw_data (me); + unsigned byte; + + HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes)); + for (byte = 0; byte < nr_bytes; byte++) + { + address_word address = base + byte; + int reg_number = (address - controller->base_address) / 4; + int reg_offset = (address - controller->base_address) % 4; + unsigned_4 register_value; /* in target byte order */ + + /* fill in entire register_value word */ + switch (reg_number) + { + case ISR_REG: register_value = controller->isr; break; + case IMR_REG: register_value = controller->imr; break; + case ILR0_REG: register_value = controller->ilr[0]; break; + case ILR1_REG: register_value = controller->ilr[1]; break; + case ILR2_REG: register_value = controller->ilr[2]; break; + case ILR3_REG: register_value = controller->ilr[3]; break; + default: register_value = 0; + } + + /* write requested byte out */ + register_value = H2T_4(register_value); + memcpy ((char*) dest + byte, ((char*)& register_value)+reg_offset, 1); + } + + return nr_bytes; +} + + + +static unsigned +tx3904irc_io_write_buffer (struct hw *me, + const void *source, + int space, + unsigned_word base, + unsigned nr_bytes) +{ + struct tx3904irc *controller = hw_data (me); + unsigned byte; + + HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes)); + for (byte = 0; byte < nr_bytes; byte++) + { + address_word address = base + byte; + int reg_number = (address - controller->base_address) / 4; + int reg_offset = (address - controller->base_address) % 4; + unsigned_4* register_ptr; + unsigned_4 register_value; + + /* fill in entire register_value word */ + switch (reg_number) + { + case ISR_REG: register_ptr = & controller->isr; break; + case IMR_REG: register_ptr = & controller->imr; break; + case ILR0_REG: register_ptr = & controller->ilr[0]; break; + case ILR1_REG: register_ptr = & controller->ilr[1]; break; + case ILR2_REG: register_ptr = & controller->ilr[2]; break; + case ILR3_REG: register_ptr = & controller->ilr[3]; break; + default: register_ptr = & register_value; /* used as a dummy */ + } + + /* HW_TRACE ((me, "reg %d pre: %08lx", reg_number, (long) *register_ptr)); */ + + /* overwrite requested byte */ + register_value = H2T_4(* register_ptr); + memcpy (((char*)®ister_value)+reg_offset, (const char*)source + byte, 1); + * register_ptr = T2H_4(register_value); + + /* HW_TRACE ((me, "post: %08lx", (long) *register_ptr)); */ + } + return nr_bytes; +} + + +const struct hw_descriptor dv_tx3904irc_descriptor[] = { + { "tx3904irc", tx3904irc_finish, }, + { NULL }, +};
dv-tx3904irc.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: configure.ac =================================================================== --- configure.ac (nonexistent) +++ configure.ac (revision 33) @@ -0,0 +1,443 @@ +dnl Process this file with autoconf to produce a configure script. +AC_PREREQ(2.59)dnl +AC_INIT(Makefile.in) +AC_CONFIG_HEADER(config.h:config.in) + +sinclude(../common/aclocal.m4) + +# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around +# it by inlining the macro's contents. +sinclude(../common/common.m4) + +dnl Options available in this module +SIM_AC_OPTION_INLINE() +SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT) +SIM_AC_OPTION_HOSTENDIAN +SIM_AC_OPTION_WARNINGS +SIM_AC_OPTION_RESERVED_BITS(1) + +# DEPRECATED +# +# Instead of defining a `subtarget' macro, code should be checking +# the value of {STATE,CPU}_ARCHITECTURE to identify the architecture +# in question. +# +case "${target}" in + mips64vr*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1" ;; + mips*tx39*) SIM_SUBTARGET="-DSUBTARGET_R3900=1";; + mips*-sde-elf*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";; + mipsisa32*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";; + mipsisa64*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";; + *) SIM_SUBTARGET="";; +esac +AC_SUBST(SIM_SUBTARGET) + + + +# +# Select the byte order of the target +# +mips_endian= +default_endian= +case "${target}" in + mips64el*-*-*) mips_endian=LITTLE_ENDIAN ;; + mips64vr*el-*-*) default_endian=LITTLE_ENDIAN ;; + mips64*-*-*) default_endian=BIG_ENDIAN ;; + mips16*-*-*) default_endian=BIG_ENDIAN ;; + mipsisa32*-*-*) default_endian=BIG_ENDIAN ;; + mipsisa64*-*-*) default_endian=BIG_ENDIAN ;; + mips*-*-*) default_endian=BIG_ENDIAN ;; + *) default_endian=BIG_ENDIAN ;; +esac +SIM_AC_OPTION_ENDIAN($mips_endian,$default_endian) + + + +# +# Select the bitsize of the target +# +mips_addr_bitsize= +case "${target}" in + mips*-sde-elf*) mips_bitsize=64 ; mips_msb=63 ;; + mips64*-*-*) mips_bitsize=64 ; mips_msb=63 ;; + mips16*-*-*) mips_bitsize=64 ; mips_msb=63 ;; + mipsisa32*-*-*) mips_bitsize=32 ; mips_msb=31 ;; + mipsisa64*-*-*) mips_bitsize=64 ; mips_msb=63 ;; + mips*-*-*) mips_bitsize=32 ; mips_msb=31 ;; + *) mips_bitsize=64 ; mips_msb=63 ;; +esac +SIM_AC_OPTION_BITSIZE($mips_bitsize,$mips_msb,$mips_addr_bitsize) + + + +# +# Select the floating hardware support of the target +# +mips_fpu=HARDWARE_FLOATING_POINT +mips_fpu_bitsize= +case "${target}" in + mips*tx39*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=32 ;; + mips*-sde-elf*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;; + mips64*-*-*) mips_fpu=HARD_FLOATING_POINT ;; + mips16*-*-*) mips_fpu=HARD_FLOATING_POINT ;; + mipsisa32*-*-*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;; + mipsisa64*-*-*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;; + mips*-*-*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=32 ;; + *) mips_fpu=HARD_FLOATING_POINT ;; +esac +SIM_AC_OPTION_FLOAT($mips_fpu,$mips_fpu_bitsize) + + + +# +# Select the level of SMP support +# +case "${target}" in + *) mips_smp=0 ;; +esac +SIM_AC_OPTION_SMP($mips_smp) + + + +# +# Select the IGEN architecture +# +sim_gen=IGEN +sim_igen_machine="-M mipsIV" +sim_m16_machine="-M mips16,mipsIII" +sim_igen_filter="32,64,f" +sim_m16_filter="16" +sim_mach_default="mips8000" + +case "${target}" in + mips*tx39*) sim_gen=IGEN + sim_igen_filter="32,f" + sim_igen_machine="-M r3900" + ;; + mips64vr43*-*-*) sim_gen=IGEN + sim_igen_machine="-M mipsIV" + sim_mach_default="mips8000" + ;; + mips64vr5*-*-*) sim_gen=IGEN + sim_igen_machine="-M vr5000" + sim_mach_default="mips5000" + ;; + mips64vr41*) sim_gen=M16 + sim_igen_machine="-M vr4100" + sim_m16_machine="-M vr4100" + sim_igen_filter="32,64,f" + sim_m16_filter="16" + sim_mach_default="mips4100" + ;; + mips64vr-*-* | mips64vrel-*-*) + sim_gen=MULTI + sim_multi_configs="\ + vr4100:mipsIII,mips16,vr4100:32,64:mips4100,mips4111\ + vr4120:mipsIII,mips16,vr4120:32,64:mips4120\ + vr5000:mipsIV:32,64,f:mips4300,mips5000\ + vr5400:mipsIV,vr5400:32,64,f:mips5400\ + vr5500:mipsIV,vr5500:32,64,f:mips5500" + sim_multi_default=mips5000 + ;; + mips*-sde-elf*) sim_gen=M16 + sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2,smartmips" + sim_m16_machine="-M mips16,mips16e,mips64r2" + sim_igen_filter="32,64,f" + sim_mach_default="mipsisa64r2" + ;; + mips64*-*-*) sim_igen_filter="32,64,f" + sim_gen=IGEN + ;; + mips16*-*-*) sim_gen=M16 + sim_igen_filter="32,64,f" + sim_m16_filter="16" + ;; + mipsisa32r2*-*-*) sim_gen=M16 + sim_igen_machine="-M mips32r2,mips16,mips16e,mdmx,dsp,dsp2,smartmips" + sim_m16_machine="-M mips16,mips16e,mips32r2" + sim_igen_filter="32,f" + sim_mach_default="mipsisa32r2" + ;; + mipsisa32*-*-*) sim_gen=M16 + sim_igen_machine="-M mips32,mips16,mips16e,smartmips" + sim_m16_machine="-M mips16,mips16e,mips32" + sim_igen_filter="32,f" + sim_mach_default="mipsisa32" + ;; + mipsisa64r2*-*-*) sim_gen=M16 + sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2" + sim_m16_machine="-M mips16,mips16e,mips64r2" + sim_igen_filter="32,64,f" + sim_mach_default="mipsisa64r2" + ;; + mipsisa64sb1*-*-*) sim_gen=IGEN + sim_igen_machine="-M mips64,mips3d,sb1" + sim_igen_filter="32,64,f" + sim_mach_default="mips_sb1" + ;; + mipsisa64*-*-*) sim_gen=M16 + sim_igen_machine="-M mips64,mips3d,mips16,mips16e,mdmx" + sim_m16_machine="-M mips16,mips16e,mips64" + sim_igen_filter="32,64,f" + sim_mach_default="mipsisa64" + ;; + mips*lsi*) sim_gen=M16 + sim_igen_machine="-M mipsIII,mips16" + sim_m16_machine="-M mips16,mipsIII" + sim_igen_filter="32,f" + sim_m16_filter="16" + sim_mach_default="mips4000" + ;; + mips*-*-*) sim_gen=IGEN + sim_igen_filter="32,f" + ;; +esac + +# The MULTI generator can combine several simulation engines into one. +# executable. A configuration which uses the MULTI should set two +# variables: ${sim_multi_configs} and ${sim_multi_default}. +# +# ${sim_multi_configs} is the list of engines to build. Each +# space-separated entry has the form NAME:MACHINE:FILTER:BFDMACHS, +# where: +# +# - NAME is a C-compatible prefix for the engine, +# - MACHINE is a -M argument, +# - FILTER is a -F argument, and +# - BFDMACHS is a comma-separated list of bfd machines that the +# simulator can run. +# +# Each entry will have a separate simulation engine whose prefix is +# m32. If the machine list includes "mips16", there will also +# be a mips16 engine, prefix m16. The mips16 engine will be +# generated using the same machine list as the 32-bit version, +# but the filter will be "16" instead of FILTER. +# +# The simulator compares the bfd mach against BFDMACHS to decide +# which engine to use. Entries in BFDMACHS should be bfd_mach +# values with "bfd_mach_" removed. ${sim_multi_default} says +# which entry should be the default. +if test ${sim_gen} = MULTI; then + + # Simple sanity check. + if test -z "${sim_multi_configs}" || test -z "${sim_multi_default}"; then + AC_MSG_ERROR(Error in configure.in: MULTI simulator not set up correctly) + fi + + # Start in a known state. + rm -f multi-include.h multi-run.c + sim_multi_flags= + sim_multi_src= + sim_multi_obj=multi-run.o + sim_multi_igen_configs= + sim_seen_default=no + + cat << __EOF__ > multi-run.c +/* Main entry point for MULTI simulators. + Copyright (C) 2003, 2007 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + -- + + This file was generated by sim/mips/configure. */ + +#include "sim-main.h" +#include "multi-include.h" + +#define SD sd +#define CPU cpu + +void +sim_engine_run (SIM_DESC sd, + int next_cpu_nr, + int nr_cpus, + int signal) /* ignore */ +{ + int mach; + + if (STATE_ARCHITECTURE (sd) == NULL) + mach = bfd_mach_${sim_multi_default}; + else + mach = STATE_ARCHITECTURE (SD)->mach; + + switch (mach) + { +__EOF__ + + for fc in ${sim_multi_configs}; do + + # Split up the entry. ${c} contains the first three elements. + # Note: outer sqaure brackets are m4 quotes. + c=`echo ${fc} | sed ['s/:[^:]*$//']` + bfdmachs=`echo ${fc} | sed 's/.*://'` + name=`echo ${c} | sed 's/:.*//'` + machine=`echo ${c} | sed 's/.*:\(.*\):.*/\1/'` + filter=`echo ${c} | sed 's/.*://'` + + # Build the following lists: + # + # sim_multi_flags: all -M and -F flags used by the simulator + # sim_multi_src: all makefile-generated source files + # sim_multi_obj: the objects for ${sim_multi_src} + # sim_multi_igen_configs: igen configuration strings. + # + # Each entry in ${sim_multi_igen_configs} is a prefix (m32 + # or m16) followed by the NAME, MACHINE and FILTER part of + # the ${sim_multi_configs} entry. + sim_multi_flags="${sim_multi_flags} -F ${filter} -M ${machine}" + + # Check whether mips16 handling is needed. + case ${c} in + *:*mips16*:*) + # Run igen twice, once for normal mode and once for mips16. + ws="m32 m16" + + # The top-level function for the mips16 simulator is + # in a file m16${name}_run.c, generated by the + # tmp-run-multi Makefile rule. + sim_multi_src="${sim_multi_src} m16${name}_run.c" + sim_multi_obj="${sim_multi_obj} m16${name}_run.o" + sim_multi_flags="${sim_multi_flags} -F 16" + ;; + *) + ws=m32 + ;; + esac + + # Now add the list of igen-generated files to ${sim_multi_src} + # and ${sim_multi_obj}. + for w in ${ws}; do + for base in engine icache idecode model semantics support; do + sim_multi_src="${sim_multi_src} ${w}${name}_${base}.c" + sim_multi_src="${sim_multi_src} ${w}${name}_${base}.h" + sim_multi_obj="${sim_multi_obj} ${w}${name}_${base}.o" + done + sim_multi_igen_configs="${sim_multi_igen_configs} ${w}${c}" + done + + # Add an include for the engine.h file. This file declares the + # top-level foo_engine_run() function. + echo "#include \"${w}${name}_engine.h\"" >> multi-include.h + + # Add case statements for this engine to sim_engine_run(). + for mach in `echo ${bfdmachs} | sed 's/,/ /g'`; do + echo " case bfd_mach_${mach}:" >> multi-run.c + if test ${mach} = ${sim_multi_default}; then + echo " default:" >> multi-run.c + sim_seen_default=yes + fi + done + echo " ${w}${name}_engine_run (sd, next_cpu_nr, nr_cpus, signal);" \ + >> multi-run.c + echo " break;" >> multi-run.c + done + + # Check whether we added a 'default:' label. + if test ${sim_seen_default} = no; then + AC_MSG_ERROR(Error in configure.in: \${sim_multi_configs} doesn't have an entry for \${sim_multi_default}) + fi + + cat << __EOF__ >> multi-run.c + } +} + +int +mips_mach_multi (SIM_DESC sd) +{ + if (STATE_ARCHITECTURE (sd) == NULL) + return bfd_mach_${sim_multi_default}; + + switch (STATE_ARCHITECTURE (SD)->mach) + { +__EOF__ + + # Add case statements for this engine to mips_mach_multi(). + for fc in ${sim_multi_configs}; do + + # Split up the entry. ${c} contains the first three elements. + # Note: outer sqaure brackets are m4 quotes. + c=`echo ${fc} | sed ['s/:[^:]*$//']` + bfdmachs=`echo ${fc} | sed 's/.*://'` + + for mach in `echo ${bfdmachs} | sed 's/,/ /g'`; do + echo " case bfd_mach_${mach}:" >> multi-run.c + done + done + + cat << __EOF__ >> multi-run.c + return (STATE_ARCHITECTURE (SD)->mach); + default: + return bfd_mach_${sim_multi_default}; + } +} +__EOF__ + + SIM_SUBTARGET="$SIM_SUBTARGET -DMIPS_MACH_MULTI" +else + # For clean-extra + sim_multi_src=doesnt-exist.c + + if test x"${sim_mach_default}" = x""; then + AC_MSG_ERROR(Error in configure.in: \${sim_mach_default} not defined) + fi + SIM_SUBTARGET="$SIM_SUBTARGET -DMIPS_MACH_DEFAULT=bfd_mach_${sim_mach_default}" +fi +sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine} ${sim_igen_smp}" +sim_m16_flags=" -F ${sim_m16_filter} ${sim_m16_machine} ${sim_igen_smp}" +AC_SUBST(sim_igen_flags) +AC_SUBST(sim_m16_flags) +AC_SUBST(sim_gen) +AC_SUBST(sim_multi_flags) +AC_SUBST(sim_multi_igen_configs) +AC_SUBST(sim_multi_src) +AC_SUBST(sim_multi_obj) + + +# +# Add simulated hardware devices +# +hw_enabled=no +case "${target}" in + mips*tx39*) + hw_enabled=yes + hw_extra_devices="tx3904cpu tx3904irc tx3904tmr tx3904sio" + mips_extra_objs="dv-sockser.o" + SIM_SUBTARGET="$SIM_SUBTARGET -DTARGET_TX3904=1" + ;; + *) + mips_extra_objs="" + ;; +esac +SIM_AC_OPTION_HARDWARE($hw_enabled,$hw_devices,$hw_extra_devices) +AC_SUBST(mips_extra_objs) + + +# Choose simulator engine +case "${target}" in + *) mips_igen_engine="engine.o" + ;; +esac +AC_SUBST(mips_igen_engine) + + +AC_PATH_X +mips_extra_libs="" +AC_SUBST(mips_extra_libs) + +AC_CHECK_HEADERS(string.h strings.h stdlib.h stdlib.h) +AC_CHECK_LIB(m, fabs) +AC_CHECK_FUNCS(aint anint sqrt) + +SIM_AC_OUTPUT
configure.ac Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: cp1.c =================================================================== --- cp1.c (nonexistent) +++ cp1.c (revision 33) @@ -0,0 +1,1590 @@ +/*> cp1.c <*/ +/* MIPS Simulator FPU (CoProcessor 1) support. + Copyright (C) 2002, 2007, 2008 Free Software Foundation, Inc. + Originally created by Cygnus Solutions. Extensive modifications, + including paired-single operation support and MIPS-3D support + contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom + Corporation (SiByte). + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +/* XXX: The following notice should be removed as soon as is practical: */ +/* Floating Point Support for gdb MIPS simulators + + This file is part of the MIPS sim + + THIS SOFTWARE IS NOT COPYRIGHTED + (by Cygnus.) + + Cygnus offers the following for use in the public domain. Cygnus + makes no warranty with regard to the software or it's performance + and the user accepts the software "AS IS" with all faults. + + CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO + THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + + (Originally, this code was in interp.c) +*/ + +#include "sim-main.h" + +/* Within cp1.c we refer to sim_cpu directly. */ +#define CPU cpu +#define SD CPU_STATE(cpu) + +/*-- FPU support routines ---------------------------------------------------*/ + +/* Numbers are held in normalized form. The SINGLE and DOUBLE binary + formats conform to ANSI/IEEE Std 754-1985. + + SINGLE precision floating: + seeeeeeeefffffffffffffffffffffff + s = 1bit = sign + e = 8bits = exponent + f = 23bits = fraction + + SINGLE precision fixed: + siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii + s = 1bit = sign + i = 31bits = integer + + DOUBLE precision floating: + seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff + s = 1bit = sign + e = 11bits = exponent + f = 52bits = fraction + + DOUBLE precision fixed: + siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii + s = 1bit = sign + i = 63bits = integer + + PAIRED SINGLE precision floating: + seeeeeeeefffffffffffffffffffffffseeeeeeeefffffffffffffffffffffff + | upper || lower | + s = 1bit = sign + e = 8bits = exponent + f = 23bits = fraction + Note: upper = [63..32], lower = [31..0] + */ + +/* Extract packed single values: */ +#define FP_PS_upper(v) (((v) >> 32) & (unsigned)0xFFFFFFFF) +#define FP_PS_lower(v) ((v) & (unsigned)0xFFFFFFFF) +#define FP_PS_cat(u,l) (((unsigned64)((u) & (unsigned)0xFFFFFFFF) << 32) \ + | (unsigned64)((l) & 0xFFFFFFFF)) + +/* Explicit QNaN values. */ +#define FPQNaN_SINGLE (0x7FBFFFFF) +#define FPQNaN_WORD (0x7FFFFFFF) +#define FPQNaN_DOUBLE (UNSIGNED64 (0x7FF7FFFFFFFFFFFF)) +#define FPQNaN_LONG (UNSIGNED64 (0x7FFFFFFFFFFFFFFF)) +#define FPQNaN_PS (FP_PS_cat (FPQNaN_SINGLE, FPQNaN_SINGLE)) + +static const char *fpu_format_name (FP_formats fmt); +#ifdef DEBUG +static const char *fpu_rounding_mode_name (int rm); +#endif + +uword64 +value_fpr (sim_cpu *cpu, + address_word cia, + int fpr, + FP_formats fmt) +{ + uword64 value = 0; + int err = 0; + + /* Treat unused register values, as fixed-point 64bit values. */ + if (fmt == fmt_unknown) + { +#if 1 + /* If request to read data as "unknown", then use the current + encoding: */ + fmt = FPR_STATE[fpr]; +#else + fmt = fmt_long; +#endif + } + + /* For values not yet accessed, set to the desired format. */ + if (fmt < fmt_uninterpreted) + { + if (FPR_STATE[fpr] == fmt_uninterpreted) + { + FPR_STATE[fpr] = fmt; +#ifdef DEBUG + printf ("DBG: Register %d was fmt_uninterpreted. Now %s\n", fpr, + fpu_format_name (fmt)); +#endif /* DEBUG */ + } + else if (fmt != FPR_STATE[fpr]) + { + sim_io_eprintf (SD, "FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n", + fpr, fpu_format_name (FPR_STATE[fpr]), + fpu_format_name (fmt), pr_addr (cia)); + FPR_STATE[fpr] = fmt_unknown; + } + } + + if (FPR_STATE[fpr] == fmt_unknown) + { + /* Set QNaN value: */ + switch (fmt) + { + case fmt_single: value = FPQNaN_SINGLE; break; + case fmt_double: value = FPQNaN_DOUBLE; break; + case fmt_word: value = FPQNaN_WORD; break; + case fmt_long: value = FPQNaN_LONG; break; + case fmt_ps: value = FPQNaN_PS; break; + default: err = -1; break; + } + } + else if (SizeFGR () == 64) + { + switch (fmt) + { + case fmt_uninterpreted_32: + case fmt_single: + case fmt_word: + value = (FGR[fpr] & 0xFFFFFFFF); + break; + + case fmt_uninterpreted_64: + case fmt_uninterpreted: + case fmt_double: + case fmt_long: + case fmt_ps: + value = FGR[fpr]; + break; + + default: + err = -1; + break; + } + } + else + { + switch (fmt) + { + case fmt_uninterpreted_32: + case fmt_single: + case fmt_word: + value = (FGR[fpr] & 0xFFFFFFFF); + break; + + case fmt_uninterpreted_64: + case fmt_uninterpreted: + case fmt_double: + case fmt_long: + if ((fpr & 1) == 0) + { + /* Even register numbers only. */ +#ifdef DEBUG + printf ("DBG: ValueFPR: FGR[%d] = %s, FGR[%d] = %s\n", + fpr + 1, pr_uword64 ((uword64) FGR[fpr+1]), + fpr, pr_uword64 ((uword64) FGR[fpr])); +#endif + value = ((((uword64) FGR[fpr+1]) << 32) + | (FGR[fpr] & 0xFFFFFFFF)); + } + else + { + SignalException (ReservedInstruction, 0); + } + break; + + case fmt_ps: + SignalException (ReservedInstruction, 0); + break; + + default: + err = -1; + break; + } + } + + if (err) + SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR ()"); + +#ifdef DEBUG + printf ("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR () = %d\n", + fpr, fpu_format_name (fmt), pr_uword64 (value), pr_addr (cia), + SizeFGR ()); +#endif /* DEBUG */ + + return (value); +} + +void +store_fpr (sim_cpu *cpu, + address_word cia, + int fpr, + FP_formats fmt, + uword64 value) +{ + int err = 0; + +#ifdef DEBUG + printf ("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR () = %d, \n", + fpr, fpu_format_name (fmt), pr_uword64 (value), pr_addr (cia), + SizeFGR ()); +#endif /* DEBUG */ + + if (SizeFGR () == 64) + { + switch (fmt) + { + case fmt_uninterpreted_32: + fmt = fmt_uninterpreted; + case fmt_single: + case fmt_word: + if (STATE_VERBOSE_P (SD)) + sim_io_eprintf (SD, + "Warning: PC 0x%s: interp.c store_fpr DEADCODE\n", + pr_addr (cia)); + FGR[fpr] = (((uword64) 0xDEADC0DE << 32) | (value & 0xFFFFFFFF)); + FPR_STATE[fpr] = fmt; + break; + + case fmt_uninterpreted_64: + fmt = fmt_uninterpreted; + case fmt_uninterpreted: + case fmt_double: + case fmt_long: + case fmt_ps: + FGR[fpr] = value; + FPR_STATE[fpr] = fmt; + break; + + default: + FPR_STATE[fpr] = fmt_unknown; + err = -1; + break; + } + } + else + { + switch (fmt) + { + case fmt_uninterpreted_32: + fmt = fmt_uninterpreted; + case fmt_single: + case fmt_word: + FGR[fpr] = (value & 0xFFFFFFFF); + FPR_STATE[fpr] = fmt; + break; + + case fmt_uninterpreted_64: + fmt = fmt_uninterpreted; + case fmt_uninterpreted: + case fmt_double: + case fmt_long: + if ((fpr & 1) == 0) + { + /* Even register numbers only. */ + FGR[fpr+1] = (value >> 32); + FGR[fpr] = (value & 0xFFFFFFFF); + FPR_STATE[fpr + 1] = fmt; + FPR_STATE[fpr] = fmt; + } + else + { + FPR_STATE[fpr] = fmt_unknown; + FPR_STATE[fpr ^ 1] = fmt_unknown; + SignalException (ReservedInstruction, 0); + } + break; + + case fmt_ps: + FPR_STATE[fpr] = fmt_unknown; + SignalException (ReservedInstruction, 0); + break; + + default: + FPR_STATE[fpr] = fmt_unknown; + err = -1; + break; + } + } + + if (err) + SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR ()"); + +#ifdef DEBUG + printf ("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n", + fpr, pr_uword64 (FGR[fpr]), fpu_format_name (fmt)); +#endif /* DEBUG */ + + return; +} + + +/* CP1 control/status register access functions. */ + +void +test_fcsr (sim_cpu *cpu, + address_word cia) +{ + unsigned int cause; + + cause = (FCSR & fcsr_CAUSE_mask) >> fcsr_CAUSE_shift; + if ((cause & ((FCSR & fcsr_ENABLES_mask) >> fcsr_ENABLES_shift)) != 0 + || (cause & (1 << UO))) + { + SignalExceptionFPE(); + } +} + +unsigned_word +value_fcr(sim_cpu *cpu, + address_word cia, + int fcr) +{ + unsigned32 value = 0; + + switch (fcr) + { + case 0: /* FP Implementation and Revision Register. */ + value = FCR0; + break; + case 25: /* FP Condition Codes Register (derived from FCSR). */ + value = (FCR31 & fcsr_FCC_mask) >> fcsr_FCC_shift; + value = (value & 0x1) | (value >> 1); /* Close FCC gap. */ + break; + case 26: /* FP Exceptions Register (derived from FCSR). */ + value = FCR31 & (fcsr_CAUSE_mask | fcsr_FLAGS_mask); + break; + case 28: /* FP Enables Register (derived from FCSR). */ + value = FCR31 & (fcsr_ENABLES_mask | fcsr_RM_mask); + if ((FCR31 & fcsr_FS) != 0) + value |= fenr_FS; + break; + case 31: /* FP Control/Status Register (FCSR). */ + value = FCR31 & ~fcsr_ZERO_mask; + break; + } + + return (EXTEND32 (value)); +} + +void +store_fcr(sim_cpu *cpu, + address_word cia, + int fcr, + unsigned_word value) +{ + unsigned32 v; + + v = VL4_8(value); + switch (fcr) + { + case 25: /* FP Condition Codes Register (stored into FCSR). */ + v = (v << 1) | (v & 0x1); /* Adjust for FCC gap. */ + FCR31 &= ~fcsr_FCC_mask; + FCR31 |= ((v << fcsr_FCC_shift) & fcsr_FCC_mask); + break; + case 26: /* FP Exceptions Register (stored into FCSR). */ + FCR31 &= ~(fcsr_CAUSE_mask | fcsr_FLAGS_mask); + FCR31 |= (v & (fcsr_CAUSE_mask | fcsr_FLAGS_mask)); + test_fcsr(cpu, cia); + break; + case 28: /* FP Enables Register (stored into FCSR). */ + if ((v & fenr_FS) != 0) + v |= fcsr_FS; + else + v &= ~fcsr_FS; + FCR31 &= (fcsr_FCC_mask | fcsr_CAUSE_mask | fcsr_FLAGS_mask); + FCR31 |= (v & (fcsr_FS | fcsr_ENABLES_mask | fcsr_RM_mask)); + test_fcsr(cpu, cia); + break; + case 31: /* FP Control/Status Register (FCSR). */ + FCR31 = v & ~fcsr_ZERO_mask; + test_fcsr(cpu, cia); + break; + } +} + +void +update_fcsr (sim_cpu *cpu, + address_word cia, + sim_fpu_status status) +{ + FCSR &= ~fcsr_CAUSE_mask; + + if (status != 0) + { + unsigned int cause = 0; + + /* map between sim_fpu codes and MIPS FCSR */ + if (status & (sim_fpu_status_invalid_snan + | sim_fpu_status_invalid_isi + | sim_fpu_status_invalid_idi + | sim_fpu_status_invalid_zdz + | sim_fpu_status_invalid_imz + | sim_fpu_status_invalid_cmp + | sim_fpu_status_invalid_sqrt + | sim_fpu_status_invalid_cvi)) + cause |= (1 << IO); + if (status & sim_fpu_status_invalid_div0) + cause |= (1 << DZ); + if (status & sim_fpu_status_overflow) + cause |= (1 << OF); + if (status & sim_fpu_status_underflow) + cause |= (1 << UF); + if (status & sim_fpu_status_inexact) + cause |= (1 << IR); +#if 0 /* Not yet. */ + /* Implicit clearing of other bits by unimplemented done by callers. */ + if (status & sim_fpu_status_unimplemented) + cause |= (1 << UO); +#endif + + FCSR |= (cause << fcsr_CAUSE_shift); + test_fcsr (cpu, cia); + FCSR |= ((cause & ~(1 << UO)) << fcsr_FLAGS_shift); + } + return; +} + +static sim_fpu_round +rounding_mode(int rm) +{ + sim_fpu_round round; + + switch (rm) + { + case FP_RM_NEAREST: + /* Round result to nearest representable value. When two + representable values are equally near, round to the value + that has a least significant bit of zero (i.e. is even). */ + round = sim_fpu_round_near; + break; + case FP_RM_TOZERO: + /* Round result to the value closest to, and not greater in + magnitude than, the result. */ + round = sim_fpu_round_zero; + break; + case FP_RM_TOPINF: + /* Round result to the value closest to, and not less than, + the result. */ + round = sim_fpu_round_up; + break; + case FP_RM_TOMINF: + /* Round result to the value closest to, and not greater than, + the result. */ + round = sim_fpu_round_down; + break; + default: + round = 0; + fprintf (stderr, "Bad switch\n"); + abort (); + } + return round; +} + +/* When the FS bit is set, MIPS processors return zero for + denormalized results and optionally replace denormalized inputs + with zero. When FS is clear, some implementation trap on input + and/or output, while other perform the operation in hardware. */ +static sim_fpu_denorm +denorm_mode(sim_cpu *cpu) +{ + sim_fpu_denorm denorm; + + /* XXX: FIXME: Eventually should be CPU model dependent. */ + if (GETFS()) + denorm = sim_fpu_denorm_zero; + else + denorm = 0; + return denorm; +} + + +/* Comparison operations. */ + +static sim_fpu_status +fp_test(unsigned64 op1, + unsigned64 op2, + FP_formats fmt, + int abs, + int cond, + int *condition) +{ + sim_fpu wop1; + sim_fpu wop2; + sim_fpu_status status = 0; + int less, equal, unordered; + + /* The format type has already been checked: */ + switch (fmt) + { + case fmt_single: + { + sim_fpu_32to (&wop1, op1); + sim_fpu_32to (&wop2, op2); + break; + } + case fmt_double: + { + sim_fpu_64to (&wop1, op1); + sim_fpu_64to (&wop2, op2); + break; + } + default: + fprintf (stderr, "Bad switch\n"); + abort (); + } + + if (sim_fpu_is_nan (&wop1) || sim_fpu_is_nan (&wop2)) + { + if ((cond & (1 << 3)) || + sim_fpu_is_snan (&wop1) || sim_fpu_is_snan (&wop2)) + status = sim_fpu_status_invalid_snan; + less = 0; + equal = 0; + unordered = 1; + } + else + { + if (abs) + { + status |= sim_fpu_abs (&wop1, &wop1); + status |= sim_fpu_abs (&wop2, &wop2); + } + equal = sim_fpu_is_eq (&wop1, &wop2); + less = !equal && sim_fpu_is_lt (&wop1, &wop2); + unordered = 0; + } + *condition = (((cond & (1 << 2)) && less) + || ((cond & (1 << 1)) && equal) + || ((cond & (1 << 0)) && unordered)); + return status; +} + +void +fp_cmp(sim_cpu *cpu, + address_word cia, + unsigned64 op1, + unsigned64 op2, + FP_formats fmt, + int abs, + int cond, + int cc) +{ + sim_fpu_status status = 0; + + /* The format type should already have been checked. The FCSR is + updated before the condition codes so that any exceptions will + be signalled before the condition codes are changed. */ + switch (fmt) + { + case fmt_single: + case fmt_double: + { + int result; + status = fp_test(op1, op2, fmt, abs, cond, &result); + update_fcsr (cpu, cia, status); + SETFCC (cc, result); + break; + } + case fmt_ps: + { + int result0, result1; + status = fp_test(FP_PS_lower (op1), FP_PS_lower (op2), fmt_single, + abs, cond, &result0); + status |= fp_test(FP_PS_upper (op1), FP_PS_upper (op2), fmt_single, + abs, cond, &result1); + update_fcsr (cpu, cia, status); + SETFCC (cc, result0); + SETFCC (cc+1, result1); + break; + } + default: + sim_io_eprintf (SD, "Bad switch\n"); + abort (); + } +} + + +/* Basic arithmetic operations. */ + +static unsigned64 +fp_unary(sim_cpu *cpu, + address_word cia, + int (*sim_fpu_op)(sim_fpu *, const sim_fpu *), + unsigned64 op, + FP_formats fmt) +{ + sim_fpu wop; + sim_fpu ans; + sim_fpu_round round = rounding_mode (GETRM()); + sim_fpu_denorm denorm = denorm_mode (cpu); + sim_fpu_status status = 0; + unsigned64 result = 0; + + /* The format type has already been checked: */ + switch (fmt) + { + case fmt_single: + { + unsigned32 res; + sim_fpu_32to (&wop, op); + status |= (*sim_fpu_op) (&ans, &wop); + status |= sim_fpu_round_32 (&ans, round, denorm); + sim_fpu_to32 (&res, &ans); + result = res; + break; + } + case fmt_double: + { + unsigned64 res; + sim_fpu_64to (&wop, op); + status |= (*sim_fpu_op) (&ans, &wop); + status |= sim_fpu_round_64 (&ans, round, denorm); + sim_fpu_to64 (&res, &ans); + result = res; + break; + } + case fmt_ps: + { + int status_u = 0, status_l = 0; + unsigned32 res_u, res_l; + sim_fpu_32to (&wop, FP_PS_upper(op)); + status_u |= (*sim_fpu_op) (&ans, &wop); + sim_fpu_to32 (&res_u, &ans); + sim_fpu_32to (&wop, FP_PS_lower(op)); + status_l |= (*sim_fpu_op) (&ans, &wop); + sim_fpu_to32 (&res_l, &ans); + result = FP_PS_cat(res_u, res_l); + status = status_u | status_l; + break; + } + default: + sim_io_eprintf (SD, "Bad switch\n"); + abort (); + } + + update_fcsr (cpu, cia, status); + return result; +} + +static unsigned64 +fp_binary(sim_cpu *cpu, + address_word cia, + int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *), + unsigned64 op1, + unsigned64 op2, + FP_formats fmt) +{ + sim_fpu wop1; + sim_fpu wop2; + sim_fpu ans; + sim_fpu_round round = rounding_mode (GETRM()); + sim_fpu_denorm denorm = denorm_mode (cpu); + sim_fpu_status status = 0; + unsigned64 result = 0; + + /* The format type has already been checked: */ + switch (fmt) + { + case fmt_single: + { + unsigned32 res; + sim_fpu_32to (&wop1, op1); + sim_fpu_32to (&wop2, op2); + status |= (*sim_fpu_op) (&ans, &wop1, &wop2); + status |= sim_fpu_round_32 (&ans, round, denorm); + sim_fpu_to32 (&res, &ans); + result = res; + break; + } + case fmt_double: + { + unsigned64 res; + sim_fpu_64to (&wop1, op1); + sim_fpu_64to (&wop2, op2); + status |= (*sim_fpu_op) (&ans, &wop1, &wop2); + status |= sim_fpu_round_64 (&ans, round, denorm); + sim_fpu_to64 (&res, &ans); + result = res; + break; + } + case fmt_ps: + { + int status_u = 0, status_l = 0; + unsigned32 res_u, res_l; + sim_fpu_32to (&wop1, FP_PS_upper(op1)); + sim_fpu_32to (&wop2, FP_PS_upper(op2)); + status_u |= (*sim_fpu_op) (&ans, &wop1, &wop2); + sim_fpu_to32 (&res_u, &ans); + sim_fpu_32to (&wop1, FP_PS_lower(op1)); + sim_fpu_32to (&wop2, FP_PS_lower(op2)); + status_l |= (*sim_fpu_op) (&ans, &wop1, &wop2); + sim_fpu_to32 (&res_l, &ans); + result = FP_PS_cat(res_u, res_l); + status = status_u | status_l; + break; + } + default: + sim_io_eprintf (SD, "Bad switch\n"); + abort (); + } + + update_fcsr (cpu, cia, status); + return result; +} + +/* Common MAC code for single operands (.s or .d), defers setting FCSR. */ +static sim_fpu_status +inner_mac(int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *), + unsigned64 op1, + unsigned64 op2, + unsigned64 op3, + int scale, + int negate, + FP_formats fmt, + sim_fpu_round round, + sim_fpu_denorm denorm, + unsigned64 *result) +{ + sim_fpu wop1; + sim_fpu wop2; + sim_fpu ans; + sim_fpu_status status = 0; + sim_fpu_status op_status; + unsigned64 temp = 0; + + switch (fmt) + { + case fmt_single: + { + unsigned32 res; + sim_fpu_32to (&wop1, op1); + sim_fpu_32to (&wop2, op2); + status |= sim_fpu_mul (&ans, &wop1, &wop2); + if (scale != 0 && sim_fpu_is_number (&ans)) /* number or denorm */ + ans.normal_exp += scale; + status |= sim_fpu_round_32 (&ans, round, denorm); + wop1 = ans; + op_status = 0; + sim_fpu_32to (&wop2, op3); + op_status |= (*sim_fpu_op) (&ans, &wop1, &wop2); + op_status |= sim_fpu_round_32 (&ans, round, denorm); + status |= op_status; + if (negate) + { + wop1 = ans; + op_status = sim_fpu_neg (&ans, &wop1); + op_status |= sim_fpu_round_32 (&ans, round, denorm); + status |= op_status; + } + sim_fpu_to32 (&res, &ans); + temp = res; + break; + } + case fmt_double: + { + unsigned64 res; + sim_fpu_64to (&wop1, op1); + sim_fpu_64to (&wop2, op2); + status |= sim_fpu_mul (&ans, &wop1, &wop2); + if (scale != 0 && sim_fpu_is_number (&ans)) /* number or denorm */ + ans.normal_exp += scale; + status |= sim_fpu_round_64 (&ans, round, denorm); + wop1 = ans; + op_status = 0; + sim_fpu_64to (&wop2, op3); + op_status |= (*sim_fpu_op) (&ans, &wop1, &wop2); + op_status |= sim_fpu_round_64 (&ans, round, denorm); + status |= op_status; + if (negate) + { + wop1 = ans; + op_status = sim_fpu_neg (&ans, &wop1); + op_status |= sim_fpu_round_64 (&ans, round, denorm); + status |= op_status; + } + sim_fpu_to64 (&res, &ans); + temp = res; + break; + } + default: + fprintf (stderr, "Bad switch\n"); + abort (); + } + *result = temp; + return status; +} + +/* Common implementation of madd, nmadd, msub, nmsub that does + intermediate rounding per spec. Also used for recip2 and rsqrt2, + which are transformed into equivalent nmsub operations. The scale + argument is an adjustment to the exponent of the intermediate + product op1*op2. It is currently non-zero for rsqrt2 (-1), which + requires an effective division by 2. */ +static unsigned64 +fp_mac(sim_cpu *cpu, + address_word cia, + int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *), + unsigned64 op1, + unsigned64 op2, + unsigned64 op3, + int scale, + int negate, + FP_formats fmt) +{ + sim_fpu_round round = rounding_mode (GETRM()); + sim_fpu_denorm denorm = denorm_mode (cpu); + sim_fpu_status status = 0; + unsigned64 result = 0; + + /* The format type has already been checked: */ + switch (fmt) + { + case fmt_single: + case fmt_double: + status = inner_mac(sim_fpu_op, op1, op2, op3, scale, + negate, fmt, round, denorm, &result); + break; + case fmt_ps: + { + int status_u, status_l; + unsigned64 result_u, result_l; + status_u = inner_mac(sim_fpu_op, FP_PS_upper(op1), FP_PS_upper(op2), + FP_PS_upper(op3), scale, negate, fmt_single, + round, denorm, &result_u); + status_l = inner_mac(sim_fpu_op, FP_PS_lower(op1), FP_PS_lower(op2), + FP_PS_lower(op3), scale, negate, fmt_single, + round, denorm, &result_l); + result = FP_PS_cat(result_u, result_l); + status = status_u | status_l; + break; + } + default: + sim_io_eprintf (SD, "Bad switch\n"); + abort (); + } + + update_fcsr (cpu, cia, status); + return result; +} + +/* Common rsqrt code for single operands (.s or .d), intermediate rounding. */ +static sim_fpu_status +inner_rsqrt(unsigned64 op1, + FP_formats fmt, + sim_fpu_round round, + sim_fpu_denorm denorm, + unsigned64 *result) +{ + sim_fpu wop1; + sim_fpu ans; + sim_fpu_status status = 0; + sim_fpu_status op_status; + unsigned64 temp = 0; + + switch (fmt) + { + case fmt_single: + { + unsigned32 res; + sim_fpu_32to (&wop1, op1); + status |= sim_fpu_sqrt (&ans, &wop1); + status |= sim_fpu_round_32 (&ans, status, round); + wop1 = ans; + op_status = sim_fpu_inv (&ans, &wop1); + op_status |= sim_fpu_round_32 (&ans, round, denorm); + sim_fpu_to32 (&res, &ans); + temp = res; + status |= op_status; + break; + } + case fmt_double: + { + unsigned64 res; + sim_fpu_64to (&wop1, op1); + status |= sim_fpu_sqrt (&ans, &wop1); + status |= sim_fpu_round_64 (&ans, round, denorm); + wop1 = ans; + op_status = sim_fpu_inv (&ans, &wop1); + op_status |= sim_fpu_round_64 (&ans, round, denorm); + sim_fpu_to64 (&res, &ans); + temp = res; + status |= op_status; + break; + } + default: + fprintf (stderr, "Bad switch\n"); + abort (); + } + *result = temp; + return status; +} + +static unsigned64 +fp_inv_sqrt(sim_cpu *cpu, + address_word cia, + unsigned64 op1, + FP_formats fmt) +{ + sim_fpu_round round = rounding_mode (GETRM()); + sim_fpu_round denorm = denorm_mode (cpu); + sim_fpu_status status = 0; + unsigned64 result = 0; + + /* The format type has already been checked: */ + switch (fmt) + { + case fmt_single: + case fmt_double: + status = inner_rsqrt (op1, fmt, round, denorm, &result); + break; + case fmt_ps: + { + int status_u, status_l; + unsigned64 result_u, result_l; + status_u = inner_rsqrt (FP_PS_upper(op1), fmt_single, round, denorm, + &result_u); + status_l = inner_rsqrt (FP_PS_lower(op1), fmt_single, round, denorm, + &result_l); + result = FP_PS_cat(result_u, result_l); + status = status_u | status_l; + break; + } + default: + sim_io_eprintf (SD, "Bad switch\n"); + abort (); + } + + update_fcsr (cpu, cia, status); + return result; +} + + +unsigned64 +fp_abs(sim_cpu *cpu, + address_word cia, + unsigned64 op, + FP_formats fmt) +{ + return fp_unary(cpu, cia, &sim_fpu_abs, op, fmt); +} + +unsigned64 +fp_neg(sim_cpu *cpu, + address_word cia, + unsigned64 op, + FP_formats fmt) +{ + return fp_unary(cpu, cia, &sim_fpu_neg, op, fmt); +} + +unsigned64 +fp_add(sim_cpu *cpu, + address_word cia, + unsigned64 op1, + unsigned64 op2, + FP_formats fmt) +{ + return fp_binary(cpu, cia, &sim_fpu_add, op1, op2, fmt); +} + +unsigned64 +fp_sub(sim_cpu *cpu, + address_word cia, + unsigned64 op1, + unsigned64 op2, + FP_formats fmt) +{ + return fp_binary(cpu, cia, &sim_fpu_sub, op1, op2, fmt); +} + +unsigned64 +fp_mul(sim_cpu *cpu, + address_word cia, + unsigned64 op1, + unsigned64 op2, + FP_formats fmt) +{ + return fp_binary(cpu, cia, &sim_fpu_mul, op1, op2, fmt); +} + +unsigned64 +fp_div(sim_cpu *cpu, + address_word cia, + unsigned64 op1, + unsigned64 op2, + FP_formats fmt) +{ + return fp_binary(cpu, cia, &sim_fpu_div, op1, op2, fmt); +} + +unsigned64 +fp_recip(sim_cpu *cpu, + address_word cia, + unsigned64 op, + FP_formats fmt) +{ + return fp_unary(cpu, cia, &sim_fpu_inv, op, fmt); +} + +unsigned64 +fp_sqrt(sim_cpu *cpu, + address_word cia, + unsigned64 op, + FP_formats fmt) +{ + return fp_unary(cpu, cia, &sim_fpu_sqrt, op, fmt); +} + +unsigned64 +fp_rsqrt(sim_cpu *cpu, + address_word cia, + unsigned64 op, + FP_formats fmt) +{ + return fp_inv_sqrt(cpu, cia, op, fmt); +} + +unsigned64 +fp_madd(sim_cpu *cpu, + address_word cia, + unsigned64 op1, + unsigned64 op2, + unsigned64 op3, + FP_formats fmt) +{ + return fp_mac(cpu, cia, &sim_fpu_add, op1, op2, op3, 0, 0, fmt); +} + +unsigned64 +fp_msub(sim_cpu *cpu, + address_word cia, + unsigned64 op1, + unsigned64 op2, + unsigned64 op3, + FP_formats fmt) +{ + return fp_mac(cpu, cia, &sim_fpu_sub, op1, op2, op3, 0, 0, fmt); +} + +unsigned64 +fp_nmadd(sim_cpu *cpu, + address_word cia, + unsigned64 op1, + unsigned64 op2, + unsigned64 op3, + FP_formats fmt) +{ + return fp_mac(cpu, cia, &sim_fpu_add, op1, op2, op3, 0, 1, fmt); +} + +unsigned64 +fp_nmsub(sim_cpu *cpu, + address_word cia, + unsigned64 op1, + unsigned64 op2, + unsigned64 op3, + FP_formats fmt) +{ + return fp_mac(cpu, cia, &sim_fpu_sub, op1, op2, op3, 0, 1, fmt); +} + + +/* MIPS-3D ASE operations. */ + +/* Variant of fp_binary for *r.ps MIPS-3D operations. */ +static unsigned64 +fp_binary_r(sim_cpu *cpu, + address_word cia, + int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *), + unsigned64 op1, + unsigned64 op2) +{ + sim_fpu wop1; + sim_fpu wop2; + sim_fpu ans; + sim_fpu_round round = rounding_mode (GETRM ()); + sim_fpu_denorm denorm = denorm_mode (cpu); + sim_fpu_status status_u, status_l; + unsigned64 result; + unsigned32 res_u, res_l; + + /* The format must be fmt_ps. */ + status_u = 0; + sim_fpu_32to (&wop1, FP_PS_upper (op1)); + sim_fpu_32to (&wop2, FP_PS_lower (op1)); + status_u |= (*sim_fpu_op) (&ans, &wop1, &wop2); + status_u |= sim_fpu_round_32 (&ans, round, denorm); + sim_fpu_to32 (&res_u, &ans); + status_l = 0; + sim_fpu_32to (&wop1, FP_PS_upper (op2)); + sim_fpu_32to (&wop2, FP_PS_lower (op2)); + status_l |= (*sim_fpu_op) (&ans, &wop1, &wop2); + status_l |= sim_fpu_round_32 (&ans, round, denorm); + sim_fpu_to32 (&res_l, &ans); + result = FP_PS_cat (res_u, res_l); + + update_fcsr (cpu, cia, status_u | status_l); + return result; +} + +unsigned64 +fp_add_r(sim_cpu *cpu, + address_word cia, + unsigned64 op1, + unsigned64 op2, + FP_formats fmt) +{ + return fp_binary_r (cpu, cia, &sim_fpu_add, op1, op2); +} + +unsigned64 +fp_mul_r(sim_cpu *cpu, + address_word cia, + unsigned64 op1, + unsigned64 op2, + FP_formats fmt) +{ + return fp_binary_r (cpu, cia, &sim_fpu_mul, op1, op2); +} + +#define NR_FRAC_GUARD (60) +#define IMPLICIT_1 LSBIT64 (NR_FRAC_GUARD) + +static int +fpu_inv1(sim_fpu *f, const sim_fpu *l) +{ + static const sim_fpu sim_fpu_one = { + sim_fpu_class_number, 0, IMPLICIT_1, 0 + }; + int status = 0; + sim_fpu t; + + if (sim_fpu_is_zero (l)) + { + *f = sim_fpu_maxfp; + f->sign = l->sign; + return sim_fpu_status_invalid_div0; + } + if (sim_fpu_is_infinity (l)) + { + *f = sim_fpu_zero; + f->sign = l->sign; + return status; + } + status |= sim_fpu_div (f, &sim_fpu_one, l); + return status; +} + +static int +fpu_inv1_32(sim_fpu *f, const sim_fpu *l) +{ + if (sim_fpu_is_zero (l)) + { + *f = sim_fpu_max32; + f->sign = l->sign; + return sim_fpu_status_invalid_div0; + } + return fpu_inv1 (f, l); +} + +static int +fpu_inv1_64(sim_fpu *f, const sim_fpu *l) +{ + if (sim_fpu_is_zero (l)) + { + *f = sim_fpu_max64; + f->sign = l->sign; + return sim_fpu_status_invalid_div0; + } + return fpu_inv1 (f, l); +} + +unsigned64 +fp_recip1(sim_cpu *cpu, + address_word cia, + unsigned64 op, + FP_formats fmt) +{ + switch (fmt) + { + case fmt_single: + case fmt_ps: + return fp_unary (cpu, cia, &fpu_inv1_32, op, fmt); + case fmt_double: + return fp_unary (cpu, cia, &fpu_inv1_64, op, fmt); + } + return 0; +} + +unsigned64 +fp_recip2(sim_cpu *cpu, + address_word cia, + unsigned64 op1, + unsigned64 op2, + FP_formats fmt) +{ + static const unsigned64 one_single = UNSIGNED64 (0x3F800000); + static const unsigned64 one_double = UNSIGNED64 (0x3FF0000000000000); + static const unsigned64 one_ps = (UNSIGNED64 (0x3F800000) << 32 | UNSIGNED64 (0x3F800000)); + unsigned64 one; + + /* Implemented as nmsub fd, 1, fs, ft. */ + switch (fmt) + { + case fmt_single: one = one_single; break; + case fmt_double: one = one_double; break; + case fmt_ps: one = one_ps; break; + default: one = 0; abort (); + } + return fp_mac (cpu, cia, &sim_fpu_sub, op1, op2, one, 0, 1, fmt); +} + +static int +fpu_inv_sqrt1(sim_fpu *f, const sim_fpu *l) +{ + static const sim_fpu sim_fpu_one = { + sim_fpu_class_number, 0, IMPLICIT_1, 0 + }; + int status = 0; + sim_fpu t; + + if (sim_fpu_is_zero (l)) + { + *f = sim_fpu_maxfp; + f->sign = l->sign; + return sim_fpu_status_invalid_div0; + } + if (sim_fpu_is_infinity (l)) + { + if (!l->sign) + { + f->class = sim_fpu_class_zero; + f->sign = 0; + } + else + { + *f = sim_fpu_qnan; + status = sim_fpu_status_invalid_sqrt; + } + return status; + } + status |= sim_fpu_sqrt (&t, l); + status |= sim_fpu_div (f, &sim_fpu_one, &t); + return status; +} + +static int +fpu_inv_sqrt1_32(sim_fpu *f, const sim_fpu *l) +{ + if (sim_fpu_is_zero (l)) + { + *f = sim_fpu_max32; + f->sign = l->sign; + return sim_fpu_status_invalid_div0; + } + return fpu_inv_sqrt1 (f, l); +} + +static int +fpu_inv_sqrt1_64(sim_fpu *f, const sim_fpu *l) +{ + if (sim_fpu_is_zero (l)) + { + *f = sim_fpu_max64; + f->sign = l->sign; + return sim_fpu_status_invalid_div0; + } + return fpu_inv_sqrt1 (f, l); +} + +unsigned64 +fp_rsqrt1(sim_cpu *cpu, + address_word cia, + unsigned64 op, + FP_formats fmt) +{ + switch (fmt) + { + case fmt_single: + case fmt_ps: + return fp_unary (cpu, cia, &fpu_inv_sqrt1_32, op, fmt); + case fmt_double: + return fp_unary (cpu, cia, &fpu_inv_sqrt1_64, op, fmt); + } + return 0; +} + +unsigned64 +fp_rsqrt2(sim_cpu *cpu, + address_word cia, + unsigned64 op1, + unsigned64 op2, + FP_formats fmt) +{ + static const unsigned64 half_single = UNSIGNED64 (0x3F000000); + static const unsigned64 half_double = UNSIGNED64 (0x3FE0000000000000); + static const unsigned64 half_ps = (UNSIGNED64 (0x3F000000) << 32 | UNSIGNED64 (0x3F000000)); + unsigned64 half; + + /* Implemented as (nmsub fd, 0.5, fs, ft)/2, where the divide is + done by scaling the exponent during multiply. */ + switch (fmt) + { + case fmt_single: half = half_single; break; + case fmt_double: half = half_double; break; + case fmt_ps: half = half_ps; break; + default: half = 0; abort (); + } + return fp_mac (cpu, cia, &sim_fpu_sub, op1, op2, half, -1, 1, fmt); +} + + +/* Conversion operations. */ + +uword64 +convert (sim_cpu *cpu, + address_word cia, + int rm, + uword64 op, + FP_formats from, + FP_formats to) +{ + sim_fpu wop; + sim_fpu_round round = rounding_mode (rm); + sim_fpu_denorm denorm = denorm_mode (cpu); + unsigned32 result32; + unsigned64 result64; + sim_fpu_status status = 0; + + /* Convert the input to sim_fpu internal format */ + switch (from) + { + case fmt_double: + sim_fpu_64to (&wop, op); + break; + case fmt_single: + sim_fpu_32to (&wop, op); + break; + case fmt_word: + status = sim_fpu_i32to (&wop, op, round); + break; + case fmt_long: + status = sim_fpu_i64to (&wop, op, round); + break; + default: + sim_io_eprintf (SD, "Bad switch\n"); + abort (); + } + + /* Convert sim_fpu format into the output */ + /* The value WOP is converted to the destination format, rounding + using mode RM. When the destination is a fixed-point format, then + a source value of Infinity, NaN or one which would round to an + integer outside the fixed point range then an IEEE Invalid Operation + condition is raised. Not used if destination format is PS. */ + switch (to) + { + case fmt_single: + status |= sim_fpu_round_32 (&wop, round, denorm); + /* For a NaN, normalize mantissa bits (cvt.s.d can't preserve them) */ + if (sim_fpu_is_qnan (&wop)) + wop = sim_fpu_qnan; + sim_fpu_to32 (&result32, &wop); + result64 = result32; + break; + case fmt_double: + status |= sim_fpu_round_64 (&wop, round, denorm); + /* For a NaN, normalize mantissa bits (make cvt.d.s consistent) */ + if (sim_fpu_is_qnan (&wop)) + wop = sim_fpu_qnan; + sim_fpu_to64 (&result64, &wop); + break; + case fmt_word: + status |= sim_fpu_to32i (&result32, &wop, round); + result64 = result32; + break; + case fmt_long: + status |= sim_fpu_to64i (&result64, &wop, round); + break; + default: + result64 = 0; + sim_io_eprintf (SD, "Bad switch\n"); + abort (); + } + + update_fcsr (cpu, cia, status); + return result64; +} + +unsigned64 +ps_lower(sim_cpu *cpu, + address_word cia, + unsigned64 op) +{ + return FP_PS_lower (op); +} + +unsigned64 +ps_upper(sim_cpu *cpu, + address_word cia, + unsigned64 op) +{ + return FP_PS_upper(op); +} + +unsigned64 +pack_ps(sim_cpu *cpu, + address_word cia, + unsigned64 op1, + unsigned64 op2, + FP_formats fmt) +{ + unsigned64 result = 0; + + /* The registers must specify FPRs valid for operands of type + "fmt". If they are not valid, the result is undefined. */ + + /* The format type should already have been checked: */ + switch (fmt) + { + case fmt_single: + { + sim_fpu wop; + unsigned32 res_u, res_l; + sim_fpu_32to (&wop, op1); + sim_fpu_to32 (&res_u, &wop); + sim_fpu_32to (&wop, op2); + sim_fpu_to32 (&res_l, &wop); + result = FP_PS_cat(res_u, res_l); + break; + } + default: + sim_io_eprintf (SD, "Bad switch\n"); + abort (); + } + + return result; +} + +unsigned64 +convert_ps (sim_cpu *cpu, + address_word cia, + int rm, + unsigned64 op, + FP_formats from, + FP_formats to) +{ + sim_fpu wop_u, wop_l; + sim_fpu_round round = rounding_mode (rm); + sim_fpu_denorm denorm = denorm_mode (cpu); + unsigned32 res_u, res_l; + unsigned64 result; + sim_fpu_status status_u = 0, status_l = 0; + + /* As convert, but used only for paired values (formats PS, PW) */ + + /* Convert the input to sim_fpu internal format */ + switch (from) + { + case fmt_word: /* fmt_pw */ + sim_fpu_i32to (&wop_u, (op >> 32) & (unsigned)0xFFFFFFFF, round); + sim_fpu_i32to (&wop_l, op & (unsigned)0xFFFFFFFF, round); + break; + case fmt_ps: + sim_fpu_32to (&wop_u, FP_PS_upper(op)); + sim_fpu_32to (&wop_l, FP_PS_lower(op)); + break; + default: + sim_io_eprintf (SD, "Bad switch\n"); + abort (); + } + + /* Convert sim_fpu format into the output */ + switch (to) + { + case fmt_word: /* fmt_pw */ + status_u |= sim_fpu_to32i (&res_u, &wop_u, round); + status_l |= sim_fpu_to32i (&res_l, &wop_l, round); + result = (((unsigned64)res_u) << 32) | (unsigned64)res_l; + break; + case fmt_ps: + status_u |= sim_fpu_round_32 (&wop_u, 0, round); + status_l |= sim_fpu_round_32 (&wop_l, 0, round); + sim_fpu_to32 (&res_u, &wop_u); + sim_fpu_to32 (&res_l, &wop_l); + result = FP_PS_cat(res_u, res_l); + break; + default: + result = 0; + sim_io_eprintf (SD, "Bad switch\n"); + abort (); + } + + update_fcsr (cpu, cia, status_u | status_l); + return result; +} + +static const char * +fpu_format_name (FP_formats fmt) +{ + switch (fmt) + { + case fmt_single: + return "single"; + case fmt_double: + return "double"; + case fmt_word: + return "word"; + case fmt_long: + return "long"; + case fmt_ps: + return "ps"; + case fmt_unknown: + return ""; + case fmt_uninterpreted: + return ""; + case fmt_uninterpreted_32: + return ""; + case fmt_uninterpreted_64: + return ""; + default: + return ""; + } +} + +#ifdef DEBUG +static const char * +fpu_rounding_mode_name (int rm) +{ + switch (rm) + { + case FP_RM_NEAREST: + return "Round"; + case FP_RM_TOZERO: + return "Trunc"; + case FP_RM_TOPINF: + return "Ceil"; + case FP_RM_TOMINF: + return "Floor"; + default: + return ""; + } +} +#endif /* DEBUG */
cp1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: sb1.igen =================================================================== --- sb1.igen (nonexistent) +++ sb1.igen (revision 33) @@ -0,0 +1,243 @@ +// -*- C -*- + +// Simulator definition for the Broadcom SiByte SB-1 CPU extensions. +// Copyright (C) 2002 Free Software Foundation, Inc. +// Contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom +// Corporation (SiByte). +// +// This file is part of GDB, the GNU debugger. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + + +// Helper: +// +// Check that the SB-1 extension instruction can currently be used, and +// signal a ReservedInstruction exception if not. +// + +:function:::void:check_sbx:instruction_word insn +*sb1: +{ + if ((SR & status_SBX) == 0) + SignalException(ReservedInstruction, insn); +} + + +// MDMX ASE Instructions +// --------------------- +// +// The SB-1 implements the format OB subset of MDMX +// and has three additions (pavg, pabsdiff, pabsdifc). +// In addition, there are a couple of partial-decoding +// issues for the read/write accumulator instructions. +// +// This code is structured so that mdmx.igen can be used by +// selecting the allowed instructions either via model, or by +// using check_mdmx_fmtsel and check_mdmx_fmtop to cause an +// exception if the instruction is not allowed. + + +:function:::void:check_mdmx:instruction_word insn +*sb1: +{ + if (!COP_Usable(1)) + SignalExceptionCoProcessorUnusable(1); + if ((SR & status_MX) == 0) + SignalExceptionMDMX(); + check_u64 (SD_, insn); +} + +:function:::int:check_mdmx_fmtsel:instruction_word insn, int fmtsel +*sb1: +{ + switch (fmtsel & 0x03) + { + case 0x00: /* ob */ + case 0x02: + return 1; + case 0x01: /* qh */ + case 0x03: /* UNPREDICTABLE */ + SignalException (ReservedInstruction, insn); + return 0; + } + return 0; +} + +:function:::int:check_mdmx_fmtop:instruction_word insn, int fmtop +*sb1: +{ + switch (fmtop & 0x01) + { + case 0x00: /* ob */ + return 1; + case 0x01: /* qh */ + SignalException (ReservedInstruction, insn); + return 0; + } + return 0; +} + + +011110,10,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACH.sb1.fmt +"rach.?.%s v" +*sb1: +{ + check_mdmx (SD_, instruction_0); + check_mdmx_fmtop (SD_, instruction_0, FMTOP); + /* No op. */ +} + + +011110,00,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACL.sb1.fmt +"racl.?.%s v" +*sb1: +{ + check_mdmx (SD_, instruction_0); + check_mdmx_fmtop (SD_, instruction_0, FMTOP); + /* No op. */ +} + + +011110,01,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACM.sb1.fmt +"racm.?.%s v" +*sb1: +{ + check_mdmx (SD_, instruction_0); + check_mdmx_fmtop (SD_, instruction_0, FMTOP); + /* No op. */ +} + + +011110,2.X1!0!1!2,2.X2,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RAC.sb1.fmt +"rac?.? v" +*sb1: +{ + check_mdmx (SD_, instruction_0); + check_mdmx_fmtop (SD_, instruction_0, FMTOP); + /* No op. */ +} + + +011110,10,2.X!0,1.FMTOP,00000,5.VS,00000,111110:MDMX:64::WACH.sb1.fmt +"wach.?.%s v" +*sb1: +{ + check_mdmx (SD_, instruction_0); + check_mdmx_fmtop (SD_, instruction_0, FMTOP); + /* No op. */ +} + + +011110,00,2.X!0,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WACL.sb1.fmt +"wacl.?.%s v,v" +*sb1: +{ + check_mdmx (SD_, instruction_0); + check_mdmx_fmtop (SD_, instruction_0, FMTOP); + /* No op. */ +} + + +011110,2.X1!0!2,2.X2,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WAC.sb1.fmt +"wacl?.?.%s v,v" +*sb1: +{ + check_mdmx (SD_, instruction_0); + check_mdmx_fmtop (SD_, instruction_0, FMTOP); + /* No op. */ +} + + +011110,5.FMTSEL,5.VT,5.VS,5.VD,001001:MDMX:64::PABSDIFF.fmt +"pabsdiff.%s v,v,v" +*sb1: +{ + check_mdmx (SD_, instruction_0); + check_sbx (SD_, instruction_0); + check_mdmx_fmtsel (SD_, instruction_0, FMTSEL); + StoreFPR(VD,fmt_mdmx,MX_AbsDiff(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); +} + + +011110,5.FMTSEL,5.VT,5.VS,00000,110101:MDMX:64::PABSDIFC.fmt +"pabsdifc.% v,v" +*sb1: +{ + check_mdmx (SD_, instruction_0); + check_sbx (SD_, instruction_0); + check_mdmx_fmtsel (SD_, instruction_0, FMTSEL); + MX_AbsDiffC(ValueFPR(VS,fmt_mdmx),VT,FMTSEL); +} + + +011110,5.FMTSEL,5.VT,5.VS,5.VD,001000:MDMX:64::PAVG.fmt +"pavg.%s v,v,v" +*sb1: +{ + check_mdmx (SD_, instruction_0); + check_sbx (SD_, instruction_0); + check_mdmx_fmtsel (SD_, instruction_0, FMTSEL); + StoreFPR(VD,fmt_mdmx,MX_Avg(ValueFPR(VS,fmt_mdmx),VT,FMTSEL)); +} + + +// Paired-Single Extension Instructions +// ------------------------------------ +// +// The SB-1 implements several .PS format instructions that are +// extensions to the MIPS64 architecture. + +010001,10,3.FMT=6,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.PS +"div.%s f, f, f" +*sb1: +{ + int fmt = FMT; + check_fpu (SD_); + check_sbx (SD_, instruction_0); + StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt)); +} + + +010001,10,3.FMT=6,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.PS +"recip.%s f, f" +*sb1: +{ + int fmt = FMT; + check_fpu (SD_); + check_sbx (SD_, instruction_0); + StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt)); +} + + +010001,10,3.FMT=6,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.PS +"rsqrt.%s f, f" +*sb1: +{ + int fmt = FMT; + check_fpu (SD_); + check_sbx (SD_, instruction_0); + StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt)); +} + + +010001,10,3.FMT=6,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.PS +"sqrt.%s f, f" +*sb1: +{ + int fmt = FMT; + check_fpu (SD_); + check_sbx (SD_, instruction_0); + StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt))); +} Index: dsp.igen =================================================================== --- dsp.igen (nonexistent) +++ dsp.igen (revision 33) @@ -0,0 +1,1775 @@ +// -*- C -*- + +// Simulator definition for the MIPS DSP ASE. +// Copyright (C) 2005, 2007 Free Software Foundation, Inc. +// Contributed by MIPS Technologies, Inc. Written by Chao-ying Fu. +// +// This file is part of GDB, the GNU debugger. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + + +// op: 0 = ADD, 1 = SUB, 2 = MUL +// sat: 0 = no saturation, 1 = saturation +:function:::void:do_ph_op:int rd, int rs, int rt, int op, int sat +{ + int i; + signed32 h0 = 0; + signed16 h1, h2; + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + unsigned32 result = 0; + for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) + { + h1 = (signed16)(v1 & 0xffff); + h2 = (signed16)(v2 & 0xffff); + if (op == 0) // ADD + h0 = (signed32)h1 + (signed32)h2; + else if (op == 1) // SUB + h0 = (signed32)h1 - (signed32)h2; + else // MUL + h0 = (signed32)h1 * (signed32)h2; + if (h0 > (signed32)0x7fff || h0 < (signed32)0xffff8000) + { + if (op == 0 || op == 1) // ADD, SUB + DSPCR |= DSPCR_OUFLAG4; + else if (op == 2) // MUL + DSPCR |= DSPCR_OUFLAG5; + if (sat == 1) + { + if (h0 > (signed32)0x7fff) + h0 = 0x7fff; + else + h0 = 0x8000; + } + } + result |= ((unsigned32)((unsigned16)h0) << i); + } + GPR[rd] = EXTEND32 (result); +} + +// op: 0 = ADD, 1 = SUB +:function:::void:do_w_op:int rd, int rs, int rt, int op +{ + signed64 h0; + signed32 h1, h2; + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + unsigned32 result = 0; + h1 = (signed32)v1; + h2 = (signed32)v2; + if (op == 0) // ADD + h0 = (signed64)h1 + (signed64)h2; + else // SUB + h0 = (signed64)h1 - (signed64)h2; + if (((h0 & 0x100000000LL) >> 1) != (h0 & 0x80000000)) + { + DSPCR |= DSPCR_OUFLAG4; + if (h0 & 0x100000000LL) + h0 = 0x80000000; + else + h0 = 0x7fffffff; + } + GPR[rd] = EXTEND32 (h0); +} + +// op: 0 = ADD, 1 = SUB +// sat: 0 = no saturation, 1 = saturation +:function:::void:do_qb_op:int rd, int rs, int rt, int op, int sat +{ + int i; + unsigned32 h0; + unsigned8 h1, h2; + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + unsigned32 result = 0; + for (i = 0; i < 32; i += 8, v1 >>= 8, v2 >>= 8) + { + h1 = (unsigned8)(v1 & 0xff); + h2 = (unsigned8)(v2 & 0xff); + if (op == 0) // ADD + h0 = (unsigned32)h1 + (unsigned32)h2; + else // SUB + h0 = (unsigned32)h1 - (unsigned32)h2; + if (h0 & 0x100) + { + DSPCR |= DSPCR_OUFLAG4; + if (sat == 1) + { + if (op == 0) // ADD + h0 = 0xff; + else // SUB + h0 = 0; + } + } + result |= ((unsigned32)((unsigned8)h0) << i); + } + GPR[rd] = EXTEND32 (result); +} + +// op: 0 = left, 1 = right +:function:::void:do_qb_shift:int rd, int rt, int shift, int op +{ + int i, j; + unsigned8 h0; + unsigned32 v1 = GPR[rt]; + unsigned32 result = 0; + for (i = 0; i < 32; i += 8, v1 >>= 8) + { + h0 = (unsigned8)(v1 & 0xff); + if (op == 0) // left + { + for (j = 7; j >= 8 - shift; j--) + { + if (h0 & (1<> shift; + result |= ((unsigned32)h0 << i); + } + GPR[rd] = EXTEND32 (result); +} + +// op: 0 = left, 1 = right +// sat: 0 = no saturation/rounding, 1 = saturation/rounding +:function:::void:do_ph_shift:int rd, int rt, int shift, int op, int sat +{ + int i, j; + signed16 h0; + unsigned32 v1 = GPR[rt]; + unsigned32 result = 0; + int setcond; + for (i = 0; i < 32; i += 16, v1 >>= 16) + { + h0 = (signed16)(v1 & 0xffff); + if (op == 0) // left + { + setcond = 0; + if (h0 & (1<<15)) + { + for (j = 14; j >= 15 - shift; j--) + { + if (!(h0 & (1 << j))) + { + DSPCR |= DSPCR_OUFLAG6; + setcond = 1; + break; + } + } + } + else + { + for (j = 14; j >= 15 - shift; j--) + { + if (h0 & (1 << j)) + { + DSPCR |= DSPCR_OUFLAG6; + setcond = 2; + break; + } + } + } + h0 = h0 << shift; + if (sat == 1) + { + if (setcond == 2) + h0 = 0x7fff; + else if (setcond == 1) + h0 = 0x8000; + } + } + else // right + { + if (sat == 1 && shift != 0 && (h0 & (1 << (shift-1)))) + h0 = (h0 >> shift) + 1; + else + h0 = h0 >> shift; + } + + result |= ((unsigned32)((unsigned16)h0) << i); + } + GPR[rd] = EXTEND32 (result); +} + +:function:::void:do_w_shll:int rd, int rt, int shift +{ + int i; + unsigned32 v1 = GPR[rt]; + unsigned32 result = 0; + int setcond = 0; + if (v1 & (1 << 31)) + { + for (i = 30; i >= 31 - shift; i--) + { + if (!(v1 & (1 << i))) + { + DSPCR |= DSPCR_OUFLAG6; + setcond = 1; + break; + } + } + } + else + { + for (i = 30; i >= 31 - shift; i--) + { + if (v1 & (1 << i)) + { + DSPCR |= DSPCR_OUFLAG6; + setcond = 2; + break; + } + } + } + if (setcond == 2) + result = 0x7fffffff; + else if (setcond == 1) + result = 0x80000000; + else + result = v1 << shift; + GPR[rd] = EXTEND32 (result); +} + +:function:::void:do_w_shra:int rd, int rt, int shift +{ + unsigned32 result = GPR[rt]; + signed32 h0 = (signed32)result; + if (shift != 0 && (h0 & (1 << (shift-1)))) + h0 = (h0 >> shift) + 1; + else + h0 = h0 >> shift; + GPR[rd] = EXTEND32 (h0); +} + +011111,5.RS,5.RT,5.RD,01010,010000:SPECIAL3:32::ADDQ.PH +"addq.ph r, r, r" +*dsp: +{ + do_ph_op (SD_, RD, RS, RT, 0, 0); +} + +011111,5.RS,5.RT,5.RD,01110,010000:SPECIAL3:32::ADDQ_S.PH +"addq_s.ph r, r, r" +*dsp: +{ + do_ph_op (SD_, RD, RS, RT, 0, 1); +} + +011111,5.RS,5.RT,5.RD,10110,010000:SPECIAL3:32::ADDQ_S.W +"addq_s.w r, r, r" +*dsp: +{ + do_w_op (SD_, RD, RS, RT, 0); +} + +011111,5.RS,5.RT,5.RD,00000,010000:SPECIAL3:32::ADDU.QB +"addu.qb r, r, r" +*dsp: +{ + do_qb_op (SD_, RD, RS, RT, 0, 0); +} + +011111,5.RS,5.RT,5.RD,00100,010000:SPECIAL3:32::ADDU_S.QB +"addu_s.qb r, r, r" +*dsp: +{ + do_qb_op (SD_, RD, RS, RT, 0, 1); +} + +011111,5.RS,5.RT,5.RD,01011,010000:SPECIAL3:32::SUBQ.PH +"subq.ph r, r, r" +*dsp: +{ + do_ph_op (SD_, RD, RS, RT, 1, 0); +} + +011111,5.RS,5.RT,5.RD,01111,010000:SPECIAL3:32::SUBQ_S.PH +"subq_s.ph r, r, r" +*dsp: +{ + do_ph_op (SD_, RD, RS, RT, 1, 1); +} + +011111,5.RS,5.RT,5.RD,10111,010000:SPECIAL3:32::SUBQ_S.W +"subq_s.w r, r, r" +*dsp: +{ + do_w_op (SD_, RD, RS, RT, 1); +} + +011111,5.RS,5.RT,5.RD,00001,010000:SPECIAL3:32::SUBU.QB +"subu.qb r, r, r" +*dsp: +{ + do_qb_op (SD_, RD, RS, RT, 1, 0); +} + +011111,5.RS,5.RT,5.RD,00101,010000:SPECIAL3:32::SUBU_S.QB +"subu_s.qb r, r, r" +*dsp: +{ + do_qb_op (SD_, RD, RS, RT, 1, 1); +} + +011111,5.RS,5.RT,5.RD,10000,010000:SPECIAL3:32::ADDSC +"addsc r, r, r" +*dsp: +{ + unsigned32 v1 = GPR[RS]; + unsigned32 v2 = GPR[RT]; + unsigned64 h0; + h0 = (unsigned64)v1 + (unsigned64)v2; + if (h0 & 0x100000000LL) + DSPCR |= DSPCR_CARRY; + GPR[RD] = EXTEND32 (h0); +} + +011111,5.RS,5.RT,5.RD,10001,010000:SPECIAL3:32::ADDWC +"addwc r, r, r" +*dsp: +{ + unsigned32 v1 = GPR[RS]; + unsigned32 v2 = GPR[RT]; + unsigned64 h0; + signed32 h1 = (signed32) v1; + signed32 h2 = (signed32) v2; + h0 = (signed64)h1 + (signed64)h2 + + (signed64)((DSPCR >> DSPCR_CARRY_SHIFT) & DSPCR_CARRY_MASK); + if (((h0 & 0x100000000LL) >> 1) != (h0 & 0x80000000)) + DSPCR |= DSPCR_OUFLAG4; + GPR[RD] = EXTEND32 (h0); +} + +011111,5.RS,5.RT,5.RD,10010,010000:SPECIAL3:32::MODSUB +"modsub r, r, r" +*dsp: +{ + unsigned32 result = 0; + unsigned32 v1 = GPR[RS]; + unsigned32 v2 = GPR[RT]; + unsigned32 decr = v2 & 0xff; + unsigned32 lastindex = (v2 & 0xffff00) >> 8; + if (v1 == 0) + result = lastindex; + else + result = v1 - decr; + GPR[RD] = EXTEND32 (result); +} + +011111,5.RS,00000,5.RD,10100,010000:SPECIAL3:32::RADDU.W.QB +"raddu.w.qb r, r" +*dsp: +{ + int i; + unsigned8 h0; + unsigned32 v1 = GPR[RS]; + unsigned32 result = 0; + for (i = 0; i < 32; i += 8, v1 >>= 8) + { + h0 = (unsigned8)(v1 & 0xff); + result += (unsigned32)h0; + } + GPR[RD] = EXTEND32 (result); +} + +011111,00000,5.RT,5.RD,01001,010010:SPECIAL3:32::ABSQ_S.PH +"absq_s.ph r, r" +*dsp: +{ + int i; + signed16 h0; + unsigned32 v1 = GPR[RT]; + unsigned32 result = 0; + for (i = 0; i < 32; i += 16, v1 >>= 16) + { + h0 = (signed16)(v1 & 0xffff); + if (h0 == (signed16)0x8000) + { + DSPCR |= DSPCR_OUFLAG4; + h0 = 0x7fff; + } + else if (h0 & 0x8000) + h0 = -h0; + result |= ((unsigned32)((unsigned16)h0) << i); + } + GPR[RD] = EXTEND32 (result); +} + +011111,00000,5.RT,5.RD,10001,010010:SPECIAL3:32::ABSQ_S.W +"absq_s.w r, r" +*dsp: +{ + unsigned32 v1 = GPR[RT]; + signed32 h0 = (signed32)v1; + if (h0 == (signed32)0x80000000) + { + DSPCR |= DSPCR_OUFLAG4; + h0 = 0x7fffffff; + } + else if (h0 & 0x80000000) + h0 = -h0; + GPR[RD] = EXTEND32 (h0); +} + +011111,5.RS,5.RT,5.RD,01100,010001:SPECIAL3:32::PRECRQ.QB.PH +"precrq.qb.ph r, r, r" +*dsp: +{ + unsigned32 v1 = GPR[RS]; + unsigned32 v2 = GPR[RT]; + unsigned32 tempu = (v1 & 0xff000000) >> 24; + unsigned32 tempv = (v1 & 0xff00) >> 8; + unsigned32 tempw = (v2 & 0xff000000) >> 24; + unsigned32 tempx = (v2 & 0xff00) >> 8; + GPR[RD] = EXTEND32 ((tempu << 24) | (tempv << 16) | (tempw << 8) | tempx); +} + +011111,5.RS,5.RT,5.RD,10100,010001:SPECIAL3:32::PRECRQ.PH.W +"precrq.ph.w r, r, r" +*dsp: +{ + unsigned32 v1 = GPR[RS]; + unsigned32 v2 = GPR[RT]; + unsigned32 tempu = (v1 & 0xffff0000) >> 16; + unsigned32 tempv = (v2 & 0xffff0000) >> 16; + GPR[RD] = EXTEND32 ((tempu << 16) | tempv); +} + +011111,5.RS,5.RT,5.RD,10101,010001:SPECIAL3:32::PRECRQ_RS.PH.W +"precrq_rs.ph.w r, r, r" +*dsp: +{ + unsigned32 v1 = GPR[RS]; + unsigned32 v2 = GPR[RT]; + signed32 h1 = (signed32)v1; + signed32 h2 = (signed32)v2; + signed64 temp1 = (signed64)h1 + (signed64)0x8000; + signed32 temp2; + signed64 temp3 = (signed64)h2 + (signed64)0x8000; + signed32 temp4; + if (((temp1 & 0x100000000LL) >> 1) != (temp1 & 0x80000000)) + { + DSPCR |= DSPCR_OUFLAG6; + temp2 = 0x7fff; + } + else + temp2 = (signed32)((temp1 & 0xffff0000) >> 16); + if (((temp3 & 0x100000000LL) >> 1) != (temp3 & 0x80000000)) + { + DSPCR |= DSPCR_OUFLAG6; + temp4 = 0x7fff; + } + else + temp4 = (signed32)((temp3 & 0xffff0000) >> 16); + GPR[RD] = EXTEND32 ((temp2 << 16) | temp4); +} + +011111,5.RS,5.RT,5.RD,01111,010001:SPECIAL3:32::PRECRQU_S.QB.PH +"precrqu_s.qb.ph r, r, r" +*dsp: +{ + unsigned32 v1 = GPR[RS]; + unsigned32 v2 = GPR[RT]; + unsigned32 tempu, tempv, tempw, tempx; + if (v1 & 0x80000000) + { + DSPCR |= DSPCR_OUFLAG6; + tempu = 0; + } + else if (!(v1 & 0x80000000) && ((v1 >> 16) > (unsigned32)0x7f80)) + { + DSPCR |= DSPCR_OUFLAG6; + tempu = 0xff; + } + else + tempu = (v1 & 0x7f800000) >> 23; + if (v1 & 0x8000) + { + DSPCR |= DSPCR_OUFLAG6; + tempv = 0; + } + else if (!(v1 & 0x8000) && ((v1 & 0xffff) > (unsigned32)0x7f80)) + { + DSPCR |= DSPCR_OUFLAG6; + tempv = 0xff; + } + else + tempv = (v1 & 0x7f80) >> 7; + if (v2 & 0x80000000) + { + DSPCR |= DSPCR_OUFLAG6; + tempw = 0; + } + else if (!(v2 & 0x80000000) && ((v2 >> 16) > (unsigned32)0x7f80)) + { + DSPCR |= DSPCR_OUFLAG6; + tempw = 0xff; + } + else + tempw = (v2 & 0x7f800000) >> 23; + if (v2 & 0x8000) + { + DSPCR |= DSPCR_OUFLAG6; + tempx = 0; + } + else if (!(v2 & 0x8000) && ((v2 & 0xffff) > (unsigned32)0x7f80)) + { + DSPCR |= DSPCR_OUFLAG6; + tempx = 0xff; + } + else + tempx = (v2 & 0x7f80) >> 7; + GPR[RD] = EXTEND32 ((tempu << 24) | (tempv << 16) | (tempw << 8) | tempx); +} + +011111,00000,5.RT,5.RD,01100,010010:SPECIAL3:32::PRECEQ.W.PHL +"preceq.w.phl r, r" +*dsp: +{ + unsigned32 v1 = GPR[RT]; + GPR[RD] = EXTEND32 (v1 & 0xffff0000); +} + +011111,00000,5.RT,5.RD,01101,010010:SPECIAL3:32::PRECEQ.W.PHR +"preceq.w.phr r, r" +*dsp: +{ + unsigned32 v1 = GPR[RT]; + GPR[RD] = EXTEND32 ((v1 & 0xffff) << 16); +} + +011111,00000,5.RT,5.RD,00100,010010:SPECIAL3:32::PRECEQU.PH.QBL +"precequ.ph.qbl r, r" +*dsp: +{ + unsigned32 v1 = GPR[RT]; + GPR[RD] = EXTEND32 ((v1 & 0xff000000) >> 1) | ((v1 & 0xff0000) >> 9); +} + +011111,00000,5.RT,5.RD,00101,010010:SPECIAL3:32::PRECEQU.PH.QBR +"precequ.ph.qbr r, r" +*dsp: +{ + unsigned32 v1 = GPR[RT]; + GPR[RD] = EXTEND32 ((v1 & 0xff00) << 15) | ((v1 & 0xff) << 7); +} + +011111,00000,5.RT,5.RD,00110,010010:SPECIAL3:32::PRECEQU.PH.QBLA +"precequ.ph.qbla r, r" +*dsp: +{ + unsigned32 v1 = GPR[RT]; + GPR[RD] = EXTEND32 ((v1 & 0xff000000) >> 1) | ((v1 & 0xff00) >> 1); +} + +011111,00000,5.RT,5.RD,00111,010010:SPECIAL3:32::PRECEQU.PH.QBRA +"precequ.ph.qbra r, r" +*dsp: +{ + unsigned32 v1 = GPR[RT]; + GPR[RD] = EXTEND32 ((v1 & 0xff0000) << 7) | ((v1 & 0xff) << 7); +} + +011111,00000,5.RT,5.RD,11100,010010:SPECIAL3:32::PRECEU.PH.QBL +"preceu.ph.qbl r, r" +*dsp: +{ + unsigned32 v1 = GPR[RT]; + GPR[RD] = EXTEND32 ((v1 & 0xff000000) >> 8) | ((v1 & 0xff0000) >> 16); +} + +011111,00000,5.RT,5.RD,11101,010010:SPECIAL3:32::PRECEU.PH.QBR +"preceu.ph.qbr r, r" +*dsp: +{ + unsigned32 v1 = GPR[RT]; + GPR[RD] = EXTEND32 ((v1 & 0xff00) << 8) | (v1 & 0xff); +} + +011111,00000,5.RT,5.RD,11110,010010:SPECIAL3:32::PRECEU.PH.QBLA +"preceu.ph.qbla r, r" +*dsp: +{ + unsigned32 v1 = GPR[RT]; + GPR[RD] = EXTEND32 ((v1 & 0xff000000) >> 8) | ((v1 & 0xff00) >> 8); +} + +011111,00000,5.RT,5.RD,11111,010010:SPECIAL3:32::PRECEU.PH.QBRA +"preceu.ph.qbra r, r" +*dsp: +{ + unsigned32 v1 = GPR[RT]; + GPR[RD] = EXTEND32 ((v1 & 0xff0000) | (v1 & 0xff)); +} + +011111,00,3.SHIFT3,5.RT,5.RD,00000,010011:SPECIAL3:32::SHLL.QB +"shll.qb r, r, " +*dsp: +{ + do_qb_shift (SD_, RD, RT, SHIFT3, 0); +} + +011111,5.RS,5.RT,5.RD,00010,010011:SPECIAL3:32::SHLLV.QB +"shllv.qb r, r, r" +*dsp: +{ + unsigned32 shift = GPR[RS] & 0x7; + do_qb_shift (SD_, RD, RT, shift, 0); +} + +011111,0,4.SHIFT4,5.RT,5.RD,01000,010011:SPECIAL3:32::SHLL.PH +"shll.ph r, r, " +*dsp: +{ + do_ph_shift (SD_, RD, RT, SHIFT4, 0, 0); +} + +011111,5.RS,5.RT,5.RD,01010,010011:SPECIAL3:32::SHLLV.PH +"shllv.ph r, r, r" +*dsp: +{ + unsigned32 shift = GPR[RS] & 0xf; + do_ph_shift (SD_, RD, RT, shift, 0, 0); +} + +011111,0,4.SHIFT4,5.RT,5.RD,01100,010011:SPECIAL3:32::SHLL_S.PH +"shll_s.ph r, r, " +*dsp: +{ + do_ph_shift (SD_, RD, RT, SHIFT4, 0, 1); +} + +011111,5.RS,5.RT,5.RD,01110,010011:SPECIAL3:32::SHLLV_S.PH +"shllv_s.ph r, r, r" +*dsp: +{ + unsigned32 shift = GPR[RS] & 0xf; + do_ph_shift (SD_, RD, RT, shift, 0, 1); +} + +011111,5.SHIFT5,5.RT,5.RD,10100,010011:SPECIAL3:32::SHLL_S.W +"shll_s.w r, r, " +*dsp: +{ + do_w_shll (SD_, RD, RT, SHIFT5); +} + +011111,5.RS,5.RT,5.RD,10110,010011:SPECIAL3:32::SHLLV_S.W +"shllv_s.w r, r, r" +*dsp: +{ + unsigned32 shift = GPR[RS] & 0x1f; + do_w_shll (SD_, RD, RT, shift); +} + +011111,00,3.SHIFT3,5.RT,5.RD,00001,010011:SPECIAL3:32::SHRL.QB +"shrl.qb r, r, " +*dsp: +{ + do_qb_shift (SD_, RD, RT, SHIFT3, 1); +} + +011111,5.RS,5.RT,5.RD,00011,010011:SPECIAL3:32::SHRLV.QB +"shrlv.qb r, r, r" +*dsp: +{ + unsigned32 shift = GPR[RS] & 0x7; + do_qb_shift (SD_, RD, RT, shift, 1); +} + +011111,0,4.SHIFT4,5.RT,5.RD,01001,010011:SPECIAL3:32::SHRA.PH +"shra.ph r, r, " +*dsp: +{ + do_ph_shift (SD_, RD, RT, SHIFT4, 1, 0); +} + +011111,5.RS,5.RT,5.RD,01011,010011:SPECIAL3:32::SHRAV.PH +"shrav.ph r, r, r" +*dsp: +{ + unsigned32 shift = GPR[RS] & 0xf; + do_ph_shift (SD_, RD, RT, shift, 1, 0); +} + +011111,0,4.SHIFT4,5.RT,5.RD,01101,010011:SPECIAL3:32::SHRA_R.PH +"shra_r.ph r, r, " +*dsp: +{ + do_ph_shift (SD_, RD, RT, SHIFT4, 1, 1); +} + +011111,5.RS,5.RT,5.RD,01111,010011:SPECIAL3:32::SHRAV_R.PH +"shrav_r.ph r, r, r" +*dsp: +{ + unsigned32 shift = GPR[RS] & 0xf; + do_ph_shift (SD_, RD, RT, shift, 1, 1); +} + +011111,5.SHIFT5,5.RT,5.RD,10101,010011:SPECIAL3:32::SHRA_R.W +"shra_r.w r, r, " +*dsp: +{ + do_w_shra (SD_, RD, RT, SHIFT5); +} + +011111,5.RS,5.RT,5.RD,10111,010011:SPECIAL3:32::SHRAV_R.W +"shrav_r.w r, r, r" +*dsp: +{ + unsigned32 shift = GPR[RS] & 0x1f; + do_w_shra (SD_, RD, RT, shift); +} + +// loc: 0 = qhl, 1 = qhr +:function:::void:do_qb_muleu:int rd, int rs, int rt, int loc +{ + int i; + unsigned32 result = 0; + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + unsigned16 h1, h2; + unsigned32 prod; + if (loc == 0) + v1 >>= 16; + for (i = 0; i < 32; i += 16, v1 >>= 8, v2 >>= 16) + { + h1 = (unsigned16)(v1 & 0xff); + h2 = (unsigned16)(v2 & 0xffff); + prod = (unsigned32)h1 * (unsigned32)h2; + if (prod > 0xffff) + { + DSPCR |= DSPCR_OUFLAG5; + prod = 0xffff; + } + result |= ((unsigned32)prod << i); + } + GPR[rd] = EXTEND32 (result); +} + +011111,5.RS,5.RT,5.RD,00110,010000:SPECIAL3:32::MULEU_S.PH.QBL +"muleu_s.ph.qbl r, r, r" +*dsp: +{ + do_qb_muleu (SD_, RD, RS, RT, 0); +} + +011111,5.RS,5.RT,5.RD,00111,010000:SPECIAL3:32::MULEU_S.PH.QBR +"muleu_s.ph.qbr r, r, r" +*dsp: +{ + do_qb_muleu (SD_, RD, RS, RT, 1); +} + +// round: 0 = no rounding, 1 = rounding +:function:::void:do_ph_mulq:int rd, int rs, int rt, int round +{ + int i; + unsigned32 result = 0; + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + signed16 h1, h2; + signed32 prod; + for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) + { + h1 = (signed16)(v1 & 0xffff); + h2 = (signed16)(v2 & 0xffff); + if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000) + { + DSPCR |= DSPCR_OUFLAG5; + prod = 0x7fffffff; + } + else + { + prod = ((signed32)h1 * (signed32)h2) << 1; + if (round == 1) + prod += (signed32)0x8000; + } + result |= (((unsigned32)prod >> 16) << i); + } + GPR[rd] = EXTEND32 (result); +} + +011111,5.RS,5.RT,5.RD,11111,010000:SPECIAL3:32::MULQ_RS.PH +"mulq_rs.ph r, r, r" +*dsp: +{ + do_ph_mulq (SD_, RD, RS, RT, 1); +} + +// loc: 0 = phl, 1 = phr +:function:::void:do_ph_muleq:int rd, int rs, int rt, int loc +{ + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + signed16 h1, h2; + signed32 prod; + if (loc == 0) + { + h1 = (signed16)(v1 >> 16); + h2 = (signed16)(v2 >> 16); + } + else + { + h1 = (signed16)(v1 & 0xffff); + h2 = (signed16)(v2 & 0xffff); + } + if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000) + { + DSPCR |= DSPCR_OUFLAG5; + prod = 0x7fffffff; + } + else + prod = ((signed32)h1 * (signed32)h2) << 1; + GPR[rd] = EXTEND32 (prod); +} + +011111,5.RS,5.RT,5.RD,11100,010000:SPECIAL3:32::MULEQ_S.W.PHL +"muleq_s.w.phl r, r, r" +*dsp: +{ + do_ph_muleq (SD_, RD, RS, RT, 0); +} + +011111,5.RS,5.RT,5.RD,11101,010000:SPECIAL3:32::MULEQ_S.W.PHR +"muleq_s.w.phr r, r, r" +*dsp: +{ + do_ph_muleq (SD_, RD, RS, RT, 1); +} + +// op: 0 = DPAU 1 = DPSU +// loc: 0 = qbl, 1 = qbr +:function:::void:do_qb_dot_product:int ac, int rs, int rt, int op, int loc +{ + int i; + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + unsigned8 h1, h2; + unsigned32 lo = DSPLO(ac); + unsigned32 hi = DSPHI(ac); + unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo; + if (loc == 0) + { + v1 >>= 16; + v2 >>= 16; + } + for (i = 0; i < 16; i += 8, v1 >>= 8, v2 >>= 8) + { + h1 = (unsigned8)(v1 & 0xff); + h2 = (unsigned8)(v2 & 0xff); + if (op == 0) // DPAU + prod += (unsigned64)h1 * (unsigned64)h2; + else // DPSU + prod -= (unsigned64)h1 * (unsigned64)h2; + } + DSPLO(ac) = EXTEND32 (prod); + DSPHI(ac) = EXTEND32 (prod >> 32); +} + +011111,5.RS,5.RT,000,2.AC,00011,110000:SPECIAL3:32::DPAU.H.QBL +"dpau.h.qbl ac, r, r" +*dsp: +{ + do_qb_dot_product (SD_, AC, RS, RT, 0, 0); +} + +011111,5.RS,5.RT,000,2.AC,00111,110000:SPECIAL3:32::DPAU.H.QBR +"dpau.h.qbr ac, r, r" +*dsp: +{ + do_qb_dot_product (SD_, AC, RS, RT, 0, 1); +} + +011111,5.RS,5.RT,000,2.AC,01011,110000:SPECIAL3:32::DPSU.H.QBL +"dpsu.h.qbl ac, r, r" +*dsp: +{ + do_qb_dot_product (SD_, AC, RS, RT, 1, 0); +} + +011111,5.RS,5.RT,000,2.AC,01111,110000:SPECIAL3:32::DPSU.H.QBR +"dpsu.h.qbr ac, r, r" +*dsp: +{ + do_qb_dot_product (SD_, AC, RS, RT, 1, 1); +} + +// op: 0 = DPAQ 1 = DPSQ +:function:::void:do_ph_dot_product:int ac, int rs, int rt, int op +{ + int i; + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + signed16 h1, h2; + signed32 result; + unsigned32 lo = DSPLO(ac); + unsigned32 hi = DSPHI(ac); + signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); + for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) + { + h1 = (signed16)(v1 & 0xffff); + h2 = (signed16)(v2 & 0xffff); + if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000) + { + DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); + result = (signed32)0x7fffffff; + } + else + result = ((signed32)h1 * (signed32)h2) << 1; + + if (op == 0) // DPAQ + prod += (signed64)result; + else // DPSQ + prod -= (signed64)result; + } + DSPLO(ac) = EXTEND32 (prod); + DSPHI(ac) = EXTEND32 (prod >> 32); +} + +011111,5.RS,5.RT,000,2.AC,00100,110000:SPECIAL3:32::DPAQ_S.W.PH +"dpaq_s.w.ph ac, r, r" +*dsp: +{ + do_ph_dot_product (SD_, AC, RS, RT, 0); +} + +011111,5.RS,5.RT,000,2.AC,00101,110000:SPECIAL3:32::DPSQ_S.W.PH +"dpsq_s.w.ph ac, r, r" +*dsp: +{ + do_ph_dot_product (SD_, AC, RS, RT, 1); +} + +011111,5.RS,5.RT,000,2.AC,00110,110000:SPECIAL3:32::MULSAQ_S.W.PH +"mulsaq_s.w.ph ac, r, r" +*dsp: +{ + int i; + unsigned32 v1 = GPR[RS]; + unsigned32 v2 = GPR[RT]; + signed16 h1, h2; + signed32 result; + unsigned32 lo = DSPLO(AC); + unsigned32 hi = DSPHI(AC); + signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); + for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) + { + h1 = (signed16)(v1 & 0xffff); + h2 = (signed16)(v2 & 0xffff); + if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000) + { + DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + AC)); + result = (signed32) 0x7fffffff; + } + else + result = ((signed32)h1 * (signed32)h2) << 1; + + if (i == 0) + prod -= (signed64) result; + else + prod += (signed64) result; + } + DSPLO(AC) = EXTEND32 (prod); + DSPHI(AC) = EXTEND32 (prod >> 32); +} + +// op: 0 = DPAQ 1 = DPSQ +:function:::void:do_w_dot_product:int ac, int rs, int rt, int op +{ + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + signed32 h1, h2; + signed64 result; + unsigned32 lo = DSPLO(ac); + unsigned32 hi = DSPHI(ac); + unsigned32 resultlo; + unsigned32 resulthi; + unsigned32 carry; + unsigned64 temp1; + signed64 temp2; + h1 = (signed32) v1; + h2 = (signed32) v2; + if (h1 == 0x80000000 && h2 == 0x80000000) + { + DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); + result = (signed64) 0x7fffffffffffffffLL; + } + else + result = ((signed64)h1 * (signed64)h2) << 1; + resultlo = (unsigned32)(result); + resulthi = (unsigned32)(result >> 32); + if (op ==0) // DPAQ + { + temp1 = (unsigned64)lo + (unsigned64)resultlo; + carry = (unsigned32)((temp1 >> 32) & 1); + temp2 = (signed64)((signed32)hi) + (signed64)((signed32)resulthi) + + (signed64)((signed32)carry); + } + else // DPSQ + { + temp1 = (unsigned64)lo - (unsigned64)resultlo; + carry = (unsigned32)((temp1 >> 32) & 1); + temp2 = (signed64)((signed32)hi) - (signed64)((signed32)resulthi) - + (signed64)((signed32)carry); + } + if (((temp2 & 0x100000000LL) >> 1) != (temp2 & 0x80000000LL)) + { + DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); + if (temp2 & 0x100000000LL) + { + DSPLO(ac) = EXTEND32 (0x00000000); + DSPHI(ac) = EXTEND32 (0x80000000); + } + else + { + DSPLO(ac) = EXTEND32 (0xffffffff); + DSPHI(ac) = EXTEND32 (0x7fffffff); + } + } + else + { + DSPLO(ac) = EXTEND32 (temp1); + DSPHI(ac) = EXTEND32 (temp2); + } +} + +011111,5.RS,5.RT,000,2.AC,01100,110000:SPECIAL3:32::DPAQ_SA.L.W +"dpaq_sa.l.w ac, r, r" +*dsp: +{ + do_w_dot_product (SD_, AC, RS, RT, 0); +} + +011111,5.RS,5.RT,000,2.AC,01101,110000:SPECIAL3:32::DPSQ_SA.L.W +"dpsq_sa.l.w ac, r, r" +*dsp: +{ + do_w_dot_product (SD_, AC, RS, RT, 1); +} + +// op: 0 = MAQ_S 1 = MAQ_SA +// loc: 0 = phl, 1 = phr +:function:::void:do_ph_maq:int ac, int rs, int rt, int op, int loc +{ + int i; + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + signed16 h1, h2; + signed32 result; + unsigned32 lo = DSPLO(ac); + unsigned32 hi = DSPHI(ac); + signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); + if (loc == 0) + { + h1 = (signed16)(v1 >> 16); + h2 = (signed16)(v2 >> 16); + } + else + { + h1 = (signed16)(v1 & 0xffff); + h2 = (signed16)(v2 & 0xffff); + } + if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000) + { + DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); + result = (signed32)0x7fffffff; + } + else + result = ((signed32)h1 * (signed32)h2) << 1; + prod += (signed64)result; + if (op == 1) // MAQ_SA + { + if (prod & 0x8000000000000000LL) + { + for (i = 62; i >= 31; i--) + { + if (!(prod & ((signed64)1 << i))) + { + DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); + prod = 0xffffffff80000000LL; + break; + } + } + } + else + { + for (i = 62; i >= 31; i--) + { + if (prod & ((signed64)1 << i)) + { + DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); + prod = 0x7fffffff; + break; + } + } + } + } + DSPLO(ac) = EXTEND32 (prod); + DSPHI(ac) = EXTEND32 (prod >> 32); +} + +011111,5.RS,5.RT,000,2.AC,10100,110000:SPECIAL3:32::MAQ_S.W.PHL +"maq_s.w.phl ac, r, r" +*dsp: +{ + do_ph_maq (SD_, AC, RS, RT, 0, 0); +} + +011111,5.RS,5.RT,000,2.AC,10110,110000:SPECIAL3:32::MAQ_S.W.PHR +"maq_s.w.phr ac, r, r" +*dsp: +{ + do_ph_maq (SD_, AC, RS, RT, 0, 1); +} + +011111,5.RS,5.RT,000,2.AC,10000,110000:SPECIAL3:32::MAQ_SA.W.PHL +"maq_sa.w.phl ac, r, r" +*dsp: +{ + do_ph_maq (SD_, AC, RS, RT, 1, 0); +} + +011111,5.RS,5.RT,000,2.AC,10010,110000:SPECIAL3:32::MAQ_SA.W.PHR +"maq_sa.w.phr ac, r, r" +*dsp: +{ + do_ph_maq (SD_, AC, RS, RT, 1, 1); +} + +011111,00000,5.RT,5.RD,11011,010010:SPECIAL3:32::BITREV +"bitrev r, r" +*dsp: +{ + int i; + unsigned32 v1 = GPR[RT]; + unsigned32 h1 = 0; + for (i = 0; i < 16; i++) + { + if (v1 & (1 << i)) + h1 |= (1 << (15 - i)); + } + GPR[RD] = EXTEND32 (h1); +} + +011111,5.RS,5.RT,00000,00000,001100:SPECIAL3:32::INSV +"insv r, r" +*dsp: +{ + unsigned32 v1 = GPR[RS]; + unsigned32 v2 = GPR[RT]; + unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; + unsigned32 size = (DSPCR >> DSPCR_SCOUNT_SHIFT) & DSPCR_SCOUNT_MASK; + unsigned32 mask1, mask2, mask3, result; + if (size < 32) + mask1 = (1 << size) - 1; + else + mask1 = 0xffffffff; + mask2 = (1 << pos) - 1; + if (pos + size < 32) + mask3 = ~((1 << (pos + size)) - 1); + else + mask3 = 0; + result = (v2 & mask3) | ((v1 & mask1) << pos) | (v2 & mask2); + GPR[RT] = EXTEND32 (result); +} + +011111,00,8.IMM8,5.RD,00010,010010:SPECIAL3:32::REPL.QB +"repl.qb r, " +*dsp: +{ + GPR[RD] = EXTEND32 ((IMM8 << 24) | (IMM8 << 16) | (IMM8 << 8) | IMM8); +} + +011111,00000,5.RT,5.RD,00011,010010:SPECIAL3:32::REPLV.QB +"replv.qb r, r" +*dsp: +{ + unsigned32 v1 = GPR[RT]; + v1 = v1 & 0xff; + GPR[RD] = EXTEND32 ((v1 << 24) | (v1 << 16) | (v1 << 8) | v1); +} + +011111,10.IMM10,5.RD,01010,010010:SPECIAL3:32::REPL.PH +"repl.ph r, " +*dsp: +{ + signed32 v1 = IMM10; + if (v1 & 0x200) + v1 |= 0xfffffc00; + GPR[RD] = EXTEND32 ((v1 << 16) | (v1 & 0xffff)); +} + +011111,00000,5.RT,5.RD,01011,010010:SPECIAL3:32::REPLV.PH +"replv.ph r, r" +*dsp: +{ + unsigned32 v1 = GPR[RT]; + v1 = v1 & 0xffff; + GPR[RD] = EXTEND32 ((v1 << 16) | v1); +} + +// op: 0 = EQ, 1 = LT, 2 = LE +:function:::void:do_qb_cmpu:int rs, int rt, int op +{ + int i, j; + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + unsigned8 h1, h2; + unsigned32 mask; + for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8) + { + h1 = (unsigned8)(v1 & 0xff); + h2 = (unsigned8)(v2 & 0xff); + mask = ~(1 << (DSPCR_CCOND_SHIFT + j)); + DSPCR &= mask; + if (op == 0) // EQ + DSPCR |= ((h1 == h2) << (DSPCR_CCOND_SHIFT + j)); + else if (op == 1) // LT + DSPCR |= ((h1 < h2) << (DSPCR_CCOND_SHIFT + j)); + else // LE + DSPCR |= ((h1 <= h2) << (DSPCR_CCOND_SHIFT + j)); + } +} + +011111,5.RS,5.RT,00000,00000,010001:SPECIAL3:32::CMPU.EQ.QB +"cmpu.eq.qb r, r" +*dsp: +{ + do_qb_cmpu (SD_, RS, RT, 0); +} + +011111,5.RS,5.RT,00000,00001,010001:SPECIAL3:32::CMPU.LT.QB +"cmpu.lt.qb r, r" +*dsp: +{ + do_qb_cmpu (SD_, RS, RT, 1); +} + +011111,5.RS,5.RT,00000,00010,010001:SPECIAL3:32::CMPU.LE.QB +"cmpu.le.qb r, r" +*dsp: +{ + do_qb_cmpu (SD_, RS, RT, 2); +} + +// op: 0 = EQ, 1 = LT, 2 = LE +:function:::void:do_qb_cmpgu:int rd, int rs, int rt, int op +{ + int i, j; + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + unsigned8 h1, h2; + unsigned32 result = 0; + for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8) + { + h1 = (unsigned8)(v1 & 0xff); + h2 = (unsigned8)(v2 & 0xff); + if (op == 0) // EQ + result |= ((h1 == h2) << j); + else if (op == 1) // LT + result |= ((h1 < h2) << j); + else // LE + result |= ((h1 <= h2) << j); + } + GPR[rd] = EXTEND32 (result); +} + +011111,5.RS,5.RT,5.RD,00100,010001:SPECIAL3:32::CMPGU.EQ.QB +"cmpgu.eq.qb r, r, r" +*dsp: +{ + do_qb_cmpgu (SD_, RD, RS, RT, 0); +} + +011111,5.RS,5.RT,5.RD,00101,010001:SPECIAL3:32::CMPGU.LT.QB +"cmpgu.lt.qb r, r, r" +*dsp: +{ + do_qb_cmpgu (SD_, RD, RS, RT, 1); +} + +011111,5.RS,5.RT,5.RD,00110,010001:SPECIAL3:32::CMPGU.LE.QB +"cmpgu.le.qb r, r, r" +*dsp: +{ + do_qb_cmpgu (SD_, RD, RS, RT, 2); +} + +// op: 0 = EQ, 1 = LT, 2 = LE +:function:::void:do_ph_cmpu:int rs, int rt, int op +{ + int i, j; + unsigned32 v1 = GPR[rs]; + unsigned32 v2 = GPR[rt]; + signed16 h1, h2; + unsigned32 mask; + for (i = 0, j = 0; i < 32; i += 16, j++, v1 >>= 16, v2 >>= 16) + { + h1 = (signed16)(v1 & 0xffff); + h2 = (signed16)(v2 & 0xffff); + mask = ~(1 << (DSPCR_CCOND_SHIFT + j)); + DSPCR &= mask; + if (op == 0) // EQ + DSPCR |= ((h1 == h2) << (DSPCR_CCOND_SHIFT + j)); + else if (op == 1) // LT + DSPCR |= ((h1 < h2) << (DSPCR_CCOND_SHIFT + j)); + else // LE + DSPCR |= ((h1 <= h2) << (DSPCR_CCOND_SHIFT + j)); + } +} + +011111,5.RS,5.RT,00000,01000,010001:SPECIAL3:32::CMP.EQ.PH +"cmp.eq.ph r, r" +*dsp: +{ + do_ph_cmpu (SD_, RS, RT, 0); +} + +011111,5.RS,5.RT,00000,01001,010001:SPECIAL3:32::CMP.LT.PH +"cmp.lt.ph r, r" +*dsp: +{ + do_ph_cmpu (SD_, RS, RT, 1); +} + +011111,5.RS,5.RT,00000,01010,010001:SPECIAL3:32::CMP.LE.PH +"cmp.le.ph r, r" +*dsp: +{ + do_ph_cmpu (SD_, RS, RT, 2); +} + +011111,5.RS,5.RT,5.RD,00011,010001:SPECIAL3:32::PICK.QB +"pick.qb r, r, r" +*dsp: +{ + int i, j; + unsigned32 v1 = GPR[RS]; + unsigned32 v2 = GPR[RT]; + unsigned8 h1, h2; + unsigned32 result = 0; + for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8) + { + h1 = (unsigned8)(v1 & 0xff); + h2 = (unsigned8)(v2 & 0xff); + if (DSPCR & (1 << (DSPCR_CCOND_SHIFT + j))) + result |= (unsigned32)(h1 << i); + else + result |= (unsigned32)(h2 << i); + } + GPR[RD] = EXTEND32 (result); +} + +011111,5.RS,5.RT,5.RD,01011,010001:SPECIAL3:32::PICK.PH +"pick.ph r, r, r" +*dsp: +{ + int i, j; + unsigned32 v1 = GPR[RS]; + unsigned32 v2 = GPR[RT]; + unsigned16 h1, h2; + unsigned32 result = 0; + for (i = 0, j = 0; i < 32; i += 16, j++, v1 >>= 16, v2 >>= 16) + { + h1 = (unsigned16)(v1 & 0xffff); + h2 = (unsigned16)(v2 & 0xffff); + if (DSPCR & (1 << (DSPCR_CCOND_SHIFT + j))) + result |= (unsigned32)(h1 << i); + else + result |= (unsigned32)(h2 << i); + } + GPR[RD] = EXTEND32 (result); +} + +011111,5.RS,5.RT,5.RD,01110,010001:SPECIAL3:32::PACKRL.PH +"packrl.ph r, r, r" +*dsp: +{ + unsigned32 v1 = GPR[RS]; + unsigned32 v2 = GPR[RT]; + GPR[RD] = EXTEND32 ((v1 << 16) + (v2 >> 16)); +} + +// op: 0 = EXTR, 1 = EXTR_R, 2 = EXTR_RS +:function:::void:do_w_extr:int rt, int ac, int shift, int op +{ + int i; + unsigned32 lo = DSPLO(ac); + unsigned32 hi = DSPHI(ac); + unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo; + signed64 result = (signed64)prod; + int setcond = 0; + if (!(prod & 0x8000000000000000LL)) + { + for (i = 62; i >= (shift + 31); i--) + { + if (prod & ((unsigned64)1 << i)) + { + DSPCR |= DSPCR_OUFLAG7; + setcond = 1; + break; + } + } + if (((prod >> (shift - 1)) & 0xffffffffLL) == 0xffffffffLL) + { + DSPCR |= DSPCR_OUFLAG7; + setcond = 1; + } + } + else + { + for (i = 62; i >= (shift + 31); i--) + { + if (!(prod & ((unsigned64)1 << i))) + { + DSPCR |= DSPCR_OUFLAG7; + setcond = 2; + break; + } + } + } + if (op == 0) // EXTR + result = result >> shift; + else if (op == 1) // EXTR_R + { + if (shift != 0) + result = ((result >> (shift - 1)) + 1) >> 1; + else + result = result >> shift; + } + else // EXTR_RS + { + if (setcond == 1) + result = 0x7fffffff; + else if (setcond == 2) + result = 0x80000000; + else + { + if (shift != 0) + result = ((result >> (shift - 1)) + 1) >> 1; + else + result = result >> shift; + } + } + GPR[rt] = EXTEND32 (result); +} + +011111,5.SHIFT,5.RT,000,2.AC,00000,111000:SPECIAL3:32::EXTR.W +"extr.w r, ac, " +*dsp: +{ + do_w_extr (SD_, RT, AC, SHIFT, 0); +} + +011111,5.RS,5.RT,000,2.AC,00001,111000:SPECIAL3:32::EXTRV.W +"extrv.w r, ac, r" +*dsp: +{ + unsigned32 shift = GPR[RS] & 0x1f; + do_w_extr (SD_, RT, AC, shift, 0); +} + +011111,5.SHIFT,5.RT,000,2.AC,00100,111000:SPECIAL3:32::EXTR_R.W +"extr_r.w r, ac, " +*dsp: +{ + do_w_extr (SD_, RT, AC, SHIFT, 1); +} + +011111,5.RS,5.RT,000,2.AC,00101,111000:SPECIAL3:32::EXTRV_R.W +"extrv_r.w r, ac, r" +*dsp: +{ + unsigned32 shift = GPR[RS] & 0x1f; + do_w_extr (SD_, RT, AC, shift, 1); +} + +011111,5.SHIFT,5.RT,000,2.AC,00110,111000:SPECIAL3:32::EXTR_RS.W +"extr_rs.w r, ac, " +*dsp: +{ + do_w_extr (SD_, RT, AC, SHIFT, 2); +} + +011111,5.RS,5.RT,000,2.AC,00111,111000:SPECIAL3:32::EXTRV_RS.W +"extrv_rs.w r, ac, r" +*dsp: +{ + unsigned32 shift = GPR[RS] & 0x1f; + do_w_extr (SD_, RT, AC, shift, 2); +} + +:function:::void:do_h_extr:int rt, int ac, int shift +{ + int i; + unsigned32 lo = DSPLO(ac); + unsigned32 hi = DSPHI(ac); + unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo; + signed64 result = (signed64)prod; + signed64 value = 0xffffffffffff8000LL; + result >>= shift; + if (result > 0x7fff) + { + result = 0x7fff; + DSPCR |= DSPCR_OUFLAG7; + } + else if (result < value) + { + result = value; + DSPCR |= DSPCR_OUFLAG7; + } + GPR[rt] = EXTEND32 (result); +} + +011111,5.SHIFT,5.RT,000,2.AC,01110,111000:SPECIAL3:32::EXTR_S.H +"extr_s.h r, ac, " +*dsp: +{ + do_h_extr (SD_, RT, AC, SHIFT); +} + +011111,5.RS,5.RT,000,2.AC,01111,111000:SPECIAL3:32::EXTRV_S.H +"extrv_s.h r, ac, r" +*dsp: +{ + unsigned32 shift = GPR[RS] & 0x1f; + do_h_extr (SD_, RT, AC, shift); +} + +// op: 0 = EXTP, 1 = EXTPDP +:function:::void:do_extp:int rt, int ac, int size, int op +{ + signed32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; + unsigned32 lo = DSPLO(ac); + unsigned32 hi = DSPHI(ac); + unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo; + unsigned64 result = 0; + if (pos - (size + 1) >= -1) + { + prod >>= (pos - size); + result = prod & (((unsigned64)1 << (size + 1)) - 1); + DSPCR &= (~DSPCR_EFI_SMASK); + if (op == 1) // EXTPDP + { + if (pos - (size + 1) >= 0) + { + DSPCR &= (~DSPCR_POS_SMASK); + DSPCR |= ((pos - (size + 1)) & DSPCR_POS_MASK) << DSPCR_POS_SHIFT; + } + else if (pos - (size + 1) == -1) + { + DSPCR |= DSPCR_POS_SMASK; + } + } + } + else + { + DSPCR |= DSPCR_EFI; + Unpredictable (); + } + GPR[rt] = EXTEND32 (result); +} + +011111,5.SIZE,5.RT,000,2.AC,00010,111000:SPECIAL3:32::EXTP +"extp r, ac, " +*dsp: +{ + do_extp (SD_, RT, AC, SIZE, 0); +} + +011111,5.RS,5.RT,000,2.AC,00011,111000:SPECIAL3:32::EXTPV +"extpv r, ac, r" +*dsp: +{ + unsigned32 size = GPR[RS] & 0x1f; + do_extp (SD_, RT, AC, size, 0); +} + +011111,5.SIZE,5.RT,000,2.AC,01010,111000:SPECIAL3:32::EXTPDP +"extpdp r, ac, " +*dsp: +{ + do_extp (SD_, RT, AC, SIZE, 1); +} + +011111,5.RS,5.RT,000,2.AC,01011,111000:SPECIAL3:32::EXTPDPV +"extpdpv r, ac, r" +*dsp: +{ + unsigned32 size = GPR[RS] & 0x1f; + do_extp (SD_, RT, AC, size, 1); +} + +:function:::void:do_shilo:int ac, int shift +{ + unsigned32 lo = DSPLO(ac); + unsigned32 hi = DSPHI(ac); + unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo; + if (shift > 31) + shift = shift - 64; + if (shift >= 0) + prod >>= shift; + else + prod <<= (-shift); + DSPLO(ac) = EXTEND32 (prod); + DSPHI(ac) = EXTEND32 (prod >> 32); +} + +011111,6.SHIFT6,0000,000,2.AC,11010,111000:SPECIAL3:32::SHILO +"shilo ac, " +*dsp: +{ + do_shilo (SD_, AC, SHIFT6); +} + +011111,5.RS,00000,000,2.AC,11011,111000:SPECIAL3:32::SHILOV +"shilov ac, r" +*dsp: +{ + signed32 shift = GPR[RS] & 0x3f; + do_shilo (SD_, AC, shift); +} + +011111,5.RS,00000,000,2.AC,11111,111000:SPECIAL3:32::MTHLIP +"mthlip r, ac" +*dsp: +{ + unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; + DSPHI(AC) = DSPLO(AC); + DSPLO(AC) = GPR[RS]; + if (pos >= 32) + Unpredictable (); + else + pos += 32; + DSPCR &= (~DSPCR_POS_SMASK); + DSPCR |= (pos & DSPCR_POS_MASK) << DSPCR_POS_SHIFT; +} + +011111,5.RS,10.MASK10,10011,111000:SPECIAL3:32::WRDSP +"wrdsp r":MASK10 == 1111111111 +"wrdsp r, " +*dsp: +{ + unsigned32 v1 = GPR[RS]; + if (MASK10 & 0x1) + { + DSPCR &= (~DSPCR_POS_SMASK); + DSPCR |= (v1 & DSPCR_POS_SMASK); + } + if (MASK10 & 0x2) + { + DSPCR &= (~DSPCR_SCOUNT_SMASK); + DSPCR |= (v1 & DSPCR_SCOUNT_SMASK); + } + if (MASK10 & 0x4) + { + DSPCR &= (~DSPCR_CARRY_SMASK); + DSPCR |= (v1 & DSPCR_CARRY_SMASK); + } + if (MASK10 & 0x8) + { + DSPCR &= (~DSPCR_OUFLAG_SMASK); + DSPCR |= (v1 & DSPCR_OUFLAG_SMASK); + } + if (MASK10 & 0x10) + { + DSPCR &= (~DSPCR_CCOND_SMASK); + DSPCR |= (v1 & DSPCR_CCOND_SMASK); + } + if (MASK10 & 0x20) + { + DSPCR &= (~DSPCR_EFI_SMASK); + DSPCR |= (v1 & DSPCR_EFI_SMASK); + } +} + +011111,10.MASK10,5.RD,10010,111000:SPECIAL3:32::RDDSP +"rddsp r":MASK10 == 1111111111 +"rddsp r, " +*dsp: +{ + unsigned32 result = 0; + if (MASK10 & 0x1) + { + result &= (~DSPCR_POS_SMASK); + result |= (DSPCR & DSPCR_POS_SMASK); + } + if (MASK10 & 0x2) + { + result &= (~DSPCR_SCOUNT_SMASK); + result |= (DSPCR & DSPCR_SCOUNT_SMASK); + } + if (MASK10 & 0x4) + { + result &= (~DSPCR_CARRY_SMASK); + result |= (DSPCR & DSPCR_CARRY_SMASK); + } + if (MASK10 & 0x8) + { + result &= (~DSPCR_OUFLAG_SMASK); + result |= (DSPCR & DSPCR_OUFLAG_SMASK); + } + if (MASK10 & 0x10) + { + result &= (~DSPCR_CCOND_SMASK); + result |= (DSPCR & DSPCR_CCOND_SMASK); + } + if (MASK10 & 0x20) + { + result &= (~DSPCR_EFI_SMASK); + result |= (DSPCR & DSPCR_EFI_SMASK); + } + GPR[RD] = EXTEND32 (result); +} + +011111,5.BASE,5.INDEX,5.RD,00110,001010:SPECIAL3:32::LBUX +"lbux r, r(r)" +*dsp: +{ + GPR[RD] = do_load (SD_, AccessLength_BYTE, GPR[BASE], GPR[INDEX]); +} + +011111,5.BASE,5.INDEX,5.RD,00100,001010:SPECIAL3:32::LHX +"lhx r, r(r)" +*dsp: +{ + GPR[RD] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], GPR[INDEX])); +} + +011111,5.BASE,5.INDEX,5.RD,00000,001010:SPECIAL3:32::LWX +"lwx r, r(r)" +*dsp: +{ + GPR[RD] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX])); +} + +000001,00000,11100,16.OFFSET:REGIMM:32::BPOSGE32 +"bposge32 " +*dsp: +{ + unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; + address_word offset = EXTEND16 (OFFSET) << 2; + if (pos >= 32) + { + DELAY_SLOT (NIA + offset); + } +} Index: dsp.c =================================================================== --- dsp.c (nonexistent) +++ dsp.c (revision 33) @@ -0,0 +1,36 @@ +/* Simulation code for the MIPS DSP ASE. + Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc. + Contributed by MIPS Technologies, Inc. Written by Chao-ying Fu. + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +#include "sim-main.h" + +int DSPLO_REGNUM[4] = +{ + AC0LOIDX, + AC1LOIDX, + AC2LOIDX, + AC3LOIDX, +}; + +int DSPHI_REGNUM[4] = +{ + AC0HIIDX, + AC1HIIDX, + AC2HIIDX, + AC3HIIDX, +};
dsp.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: vr.igen =================================================================== --- vr.igen (nonexistent) +++ vr.igen (revision 33) @@ -0,0 +1,257 @@ +// -*- C -*- +// +// NEC specific instructions +// + +:%s::::MFHI:int hi +{ + return hi ? "hi" : ""; +} + +:%s::::SAT:int s +{ + return s ? "s" : ""; +} + +:%s::::UNS:int u +{ + return u ? "u" : ""; +} + +// Simulate the various kinds of multiply and multiply-accumulate instructions. +// Perform an operation of the form: +// +// LHS (+/-) GPR[RS] * GPR[RT] +// +// and store it in the 64-bit accumulator. Optionally copy either LO or +// HI into a general purpose register. +// +// - RD is the destination register of the LO or HI move +// - RS are RT are the multiplication source registers +// - ACCUMULATE_P is true if LHS should be the value of the 64-bit accumulator, +// false if it should be 0. +// - STORE_HI_P is true if HI should be stored in RD, false if LO should be. +// - UNSIGNED_P is true if the operation should be unsigned. +// - SATURATE_P is true if the result should be saturated to a 32-bit value. +// - SUBTRACT_P is true if the right hand side should be subtraced from LHS, +// false if it should be added. +// - SHORT_P is true if RS and RT must be 16-bit numbers. +// - DOUBLE_P is true if the 64-bit accumulator is in LO, false it is a +// concatenation of the low 32 bits of HI and LO. +:function:::void:do_vr_mul_op:int rd, int rs, int rt, int accumulate_p, int store_hi_p, int unsigned_p, int saturate_p, int subtract_p, int short_p, int double_p +{ + unsigned64 lhs, x, y, xcut, ycut, product, result; + + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + + lhs = (!accumulate_p ? 0 : double_p ? LO : U8_4 (HI, LO)); + x = GPR[rs]; + y = GPR[rt]; + + /* Work out the canonical form of X and Y from their significant bits. */ + if (!short_p) + { + /* Normal sign-extension rule for 32-bit operands. */ + xcut = EXTEND32 (x); + ycut = EXTEND32 (y); + } + else if (unsigned_p) + { + /* Operands must be zero-extended 16-bit numbers. */ + xcut = x & 0xffff; + ycut = y & 0xffff; + } + else + { + /* Likewise but sign-extended. */ + xcut = EXTEND16 (x); + ycut = EXTEND16 (y); + } + if (x != xcut || y != ycut) + sim_engine_abort (SD, CPU, CIA, + "invalid multiplication operand at 0x%08lx\n", + (long) CIA); + + TRACE_ALU_INPUT2 (x, y); + product = (unsigned_p + ? V8_4 (x, 1) * V8_4 (y, 1) + : EXTEND32 (x) * EXTEND32 (y)); + result = (subtract_p ? lhs - product : lhs + product); + if (saturate_p) + { + /* Saturate the result to 32 bits. An unsigned, unsaturated + result is zero-extended to 64 bits, but unsigned overflow + causes all 64 bits to be set. */ + if (!unsigned_p && (unsigned64) EXTEND32 (result) != result) + result = ((signed64) result < 0 ? -0x7fffffff - 1 : 0x7fffffff); + else if (unsigned_p && (result >> 32) != 0) + result = (unsigned64) 0 - 1; + } + TRACE_ALU_RESULT (result); + + if (double_p) + LO = result; + else + { + LO = EXTEND32 (result); + HI = EXTEND32 (VH4_8 (result)); + } + if (rd != 0) + GPR[rd] = store_hi_p ? HI : LO; +} + +// VR4100 instructions. + +000000,5.RS,5.RT,00000,00000,101000::32::MADD16 +"madd16 r, r" +*vr4100: +{ + do_vr_mul_op (SD_, 0, RS, RT, + 1 /* accumulate */, + 0 /* store in LO */, + 0 /* signed arithmetic */, + 0 /* don't saturate */, + 0 /* don't subtract */, + 1 /* short */, + 0 /* single */); +} + +000000,5.RS,5.RT,00000,00000,101001::64::DMADD16 +"dmadd16 r, r" +*vr4100: +{ + do_vr_mul_op (SD_, 0, RS, RT, + 1 /* accumulate */, + 0 /* store in LO */, + 0 /* signed arithmetic */, + 0 /* don't saturate */, + 0 /* don't subtract */, + 1 /* short */, + 1 /* double */); +} + + + +// VR4120 and VR4130 instructions. + +000000,5.RS,5.RT,5.RD,1.SAT,1.MFHI,00,1.UNS,101001::64::DMACC +"dmacc%s%s%s r, r, r" +*vr4120: +{ + do_vr_mul_op (SD_, RD, RS, RT, + 1 /* accumulate */, + MFHI, UNS, SAT, + 0 /* don't subtract */, + SAT /* short */, + 1 /* double */); +} + +000000,5.RS,5.RT,5.RD,1.SAT,1.MFHI,00,1.UNS,101000::32::MACC_4120 +"macc%s%s%s r, r, r" +*vr4120: +{ + do_vr_mul_op (SD_, RD, RS, RT, + 1 /* accumulate */, + MFHI, UNS, SAT, + 0 /* don't subtract */, + SAT /* short */, + 0 /* single */); +} + + +// VR5400 and VR5500 instructions. + +000000,5.RS,5.RT,5.RD,0,1.MFHI,001,01100,1.UNS::32::MUL +"mul%s%s r, r, r" +*vr5400: +*vr5500: +{ + do_vr_mul_op (SD_, RD, RS, RT, + 0 /* don't accumulate */, + MFHI, UNS, + 0 /* don't saturate */, + 0 /* don't subtract */, + 0 /* not short */, + 0 /* single */); +} + +000000,5.RS,5.RT,5.RD,0,1.MFHI,011,01100,1.UNS::32::MULS +"muls%s%s r, r, r" +*vr5400: +*vr5500: +{ + do_vr_mul_op (SD_, RD, RS, RT, + 0 /* don't accumulate */, + MFHI, UNS, + 0 /* don't saturate */, + 1 /* subtract */, + 0 /* not short */, + 0 /* single */); +} + +000000,5.RS,5.RT,5.RD,0,1.MFHI,101,01100,1.UNS::32::MACC_5xxx +"macc%s%s r, r, r" +*vr5400: +*vr5500: +{ + do_vr_mul_op (SD_, RD, RS, RT, + 1 /* accumulate */, + MFHI, UNS, + 0 /* don't saturate */, + 0 /* don't subtract */, + 0 /* not short */, + 0 /* single */); +} + +000000,5.RS,5.RT,5.RD,0,1.MFHI,111,01100,1.UNS::32::MSAC +"msac%s%s r, r, r" +*vr5400: +*vr5500: +{ + do_vr_mul_op (SD_, RD, RS, RT, + 1 /* accumulate */, + MFHI, UNS, + 0 /* don't saturate */, + 1 /* subtract */, + 0 /* not short */, + 0 /* single */); +} + + +010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64::LUXC1 +"luxc1 f, r(r)" +*vr5500: +{ + check_fpu (SD_); + COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, + (GPR[BASE] + GPR[INDEX]) & ~MASK64 (2, 0), 0)); +} + +010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64::SUXC1 +"suxc1 f, r(r)" +*vr5500: +{ + check_fpu (SD_); + do_store (SD_, AccessLength_DOUBLEWORD, + (GPR[BASE] + GPR[INDEX]) & ~MASK64 (2, 0), 0, + COP_SD (1, FS)); +} + +010000,1,19.*,100000:COP0:32::WAIT +"wait" +*vr5500: + +011100,00000,5.RT,5.DR,00000,111101:SPECIAL:64::MFDR +"mfdr r, r" +*vr5400: +*vr5500: + +011100,00100,5.RT,5.DR,00000,111101:SPECIAL:64::MTDR +"mtdr r, r" +*vr5400: +*vr5500: + +011100,00000,00000,00000,00000,111110:SPECIAL:64::DRET +"dret" +*vr5400: +*vr5500: Index: cp1.h =================================================================== --- cp1.h (nonexistent) +++ cp1.h (revision 33) @@ -0,0 +1,82 @@ +/*> cp1.h <*/ +/* MIPS Simulator FPU (CoProcessor 1) definitions. + Copyright (C) 1997, 1998, 2002, 2007, 2008 Free Software Foundation, Inc. + Derived from sim-main.h contributed by Cygnus Solutions, + modified substantially by Ed Satterthwaite of Broadcom Corporation + (SiByte). + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +#ifndef CP1_H +#define CP1_H + +/* See sim-main.h for allocation of registers FCR0 and FCR31 (FCSR) + in CPU state (struct sim_cpu), and for FPU functions. */ + +#define fcsr_FCC_mask (0xFE800000) +#define fcsr_FCC_shift (23) +#define fcsr_FCC_bit(cc) ((cc) == 0 ? 23 : (24 + (cc))) +#define fcsr_FS (1 << 24) /* MIPS III onwards : Flush to Zero */ +#define fcsr_ZERO_mask (0x007C0000) +#define fcsr_CAUSE_mask (0x0003F000) +#define fcsr_CAUSE_shift (12) +#define fcsr_ENABLES_mask (0x00000F80) +#define fcsr_ENABLES_shift (7) +#define fcsr_FLAGS_mask (0x0000007C) +#define fcsr_FLAGS_shift (2) +#define fcsr_RM_mask (0x00000003) +#define fcsr_RM_shift (0) + +#define fenr_FS (0x00000004) + +/* Macros to update and retrieve the FCSR condition-code bits. This + is complicated by the fact that there is a hole in the index range + of the bits within the FCSR register. (Note that the number of bits + visible depends on the ISA in use, but that is handled elsewhere.) */ +#define SETFCC(cc,v) \ + do { \ + (FCSR = ((FCSR & ~(1 << fcsr_FCC_bit(cc))) | ((v) << fcsr_FCC_bit(cc)))); \ + } while (0) +#define GETFCC(cc) ((FCSR & (1 << fcsr_FCC_bit(cc))) != 0 ? 1 : 0) + + +/* Read flush-to-zero bit (not right-justified). */ +#define GETFS() ((int)(FCSR & fcsr_FS)) + + +/* FCSR flag bits definitions and access macros. */ +#define IR 0 /* I: Inexact Result */ +#define UF 1 /* U: UnderFlow */ +#define OF 2 /* O: OverFlow */ +#define DZ 3 /* Z: Division by Zero */ +#define IO 4 /* V: Invalid Operation */ +#define UO 5 /* E: Unimplemented Operation (CAUSE field only) */ + +#define FP_FLAGS(b) (1 << ((b) + fcsr_FLAGS_shift)) +#define FP_ENABLE(b) (1 << ((b) + fcsr_ENABLES_shift)) +#define FP_CAUSE(b) (1 << ((b) + fcsr_CAUSE_shift)) + + +/* Rounding mode bit definitions and access macros. */ +#define FP_RM_NEAREST 0 /* Round to nearest (Round). */ +#define FP_RM_TOZERO 1 /* Round to zero (Trunc). */ +#define FP_RM_TOPINF 2 /* Round to Plus infinity (Ceil). */ +#define FP_RM_TOMINF 3 /* Round to Minus infinity (Floor). */ + +#define GETRM() ((FCSR >> fcsr_RM_shift) & fcsr_RM_mask) + + +#endif /* CP1_H */
cp1.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: m16run.c =================================================================== --- m16run.c (nonexistent) +++ m16run.c (revision 33) @@ -0,0 +1,74 @@ +/* This file is part of the program psim. + + Copyright (C) 1998, Andrew Cagney + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + */ + +#include "sim-main.h" +#include "m16_idecode.h" +#include "m32_idecode.h" +#include "bfd.h" + + +#define SD sd +#define CPU cpu + +void +sim_engine_run (SIM_DESC sd, + int next_cpu_nr, + int nr_cpus, /* ignore */ + int siggnal) /* ignore */ +{ + sim_cpu *cpu = STATE_CPU (sd, next_cpu_nr); + address_word cia = CIA_GET (cpu); + + while (1) + { + address_word nia; + +#if defined (ENGINE_ISSUE_PREFIX_HOOK) + ENGINE_ISSUE_PREFIX_HOOK (); +#endif + + if ((cia & 1)) + { + m16_instruction_word instruction_0 = IMEM16 (cia); + nia = m16_idecode_issue (sd, instruction_0, cia); + } + else + { + m32_instruction_word instruction_0 = IMEM32 (cia); + nia = m32_idecode_issue (sd, instruction_0, cia); + } + +#if defined (ENGINE_ISSUE_POSTFIX_HOOK) + ENGINE_ISSUE_POSTFIX_HOOK (); +#endif + + /* Update the instruction address */ + cia = nia; + + /* process any events */ + if (sim_events_tick (sd)) + { + CIA_SET (CPU, cia); + sim_events_process (sd); + cia = CIA_GET (CPU); + } + + } +}
m16run.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: config.in =================================================================== --- config.in (nonexistent) +++ config.in (revision 33) @@ -0,0 +1,108 @@ +/* config.in. Generated from configure.ac by autoheader. */ + +/* Define to 1 if translation of program messages to the user's native + language is requested. */ +#undef ENABLE_NLS + +/* Define to 1 if you have the `aint' function. */ +#undef HAVE_AINT + +/* Define to 1 if you have the `anint' function. */ +#undef HAVE_ANINT + +/* Define to 1 if you have the header file. */ +#undef HAVE_DLFCN_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_ERRNO_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_FCNTL_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_FPU_CONTROL_H + +/* Define to 1 if you have the `getrusage' function. */ +#undef HAVE_GETRUSAGE + +/* Define to 1 if you have the header file. */ +#undef HAVE_INTTYPES_H + +/* Define to 1 if you have the `m' library (-lm). */ +#undef HAVE_LIBM + +/* Define to 1 if you have the `nsl' library (-lnsl). */ +#undef HAVE_LIBNSL + +/* Define to 1 if you have the `socket' library (-lsocket). */ +#undef HAVE_LIBSOCKET + +/* Define to 1 if you have the header file. */ +#undef HAVE_MEMORY_H + +/* Define to 1 if you have the `sigaction' function. */ +#undef HAVE_SIGACTION + +/* Define to 1 if you have the `sqrt' function. */ +#undef HAVE_SQRT + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDINT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDLIB_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRINGS_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRING_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_RESOURCE_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_STAT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TIME_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TYPES_H + +/* Define to 1 if you have the `time' function. */ +#undef HAVE_TIME + +/* Define to 1 if you have the header file. */ +#undef HAVE_TIME_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_UNISTD_H + +/* Define to 1 if you have the `__setfpucw' function. */ +#undef HAVE___SETFPUCW + +/* Define to the address where bug reports for this package should be sent. */ +#undef PACKAGE_BUGREPORT + +/* Define to the full name of this package. */ +#undef PACKAGE_NAME + +/* Define to the full name and version of this package. */ +#undef PACKAGE_STRING + +/* Define to the one symbol short name of this package. */ +#undef PACKAGE_TARNAME + +/* Define to the version of this package. */ +#undef PACKAGE_VERSION + +/* Define as the return type of signal handlers (`int' or `void'). */ +#undef RETSIGTYPE + +/* Define to 1 if you have the ANSI C header files. */ +#undef STDC_HEADERS + +/* Define to 1 if your processor stores words with the most significant byte + first (like Motorola and SPARC, unlike Intel and VAX). */ +#undef WORDS_BIGENDIAN Index: dv-tx3904cpu.c =================================================================== --- dv-tx3904cpu.c (nonexistent) +++ dv-tx3904cpu.c (revision 33) @@ -0,0 +1,245 @@ +/* This file is part of the program GDB, the GNU debugger. + + Copyright (C) 1998, 2007, 2008 Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + */ + + +#include "sim-main.h" +#include "hw-main.h" + +/* DEVICE + + + tx3904cpu - tx3904 cpu virtual device + + + DESCRIPTION + + + Implements the external tx3904 functionality. This includes the + delivery of of interrupts generated from other devices and the + handling of device specific registers. + + + PROPERTIES + + none + + + PORTS + + + reset (input) + + Currently ignored. + + + nmi (input) + + Deliver a non-maskable interrupt to the processor. + + + level (input) + + Deliver a maskable interrupt of given level, corresponding to + IP[5:0], to processor. + + + + BUGS + + + When delivering an interrupt, this code assumes that there is only + one processor (number 0). + + This code does not attempt to be efficient at handling pending + interrupts. It simply schedules the interrupt delivery handler + every instruction cycle until all pending interrupts go away. An + alternative implementation might modify instructions that change + the PSW and have them check to see if the change makes an interrupt + delivery possible. + + */ + + + +struct tx3904cpu { + /* Pending interrupts for delivery by event handler */ + int pending_reset, pending_nmi, pending_level; + struct hw_event* event; +}; + + + +/* input port ID's */ + +enum { + RESET_PORT, + NMI_PORT, + LEVEL_PORT, +}; + + +static const struct hw_port_descriptor tx3904cpu_ports[] = { + + /* interrupt inputs */ + { "reset", RESET_PORT, 0, input_port, }, + { "nmi", NMI_PORT, 0, input_port, }, + { "level", LEVEL_PORT, 0, input_port, }, + + { NULL, }, +}; + + +/* Finish off the partially created hw device. Attach our local + callbacks. Wire up our port names etc */ + +static hw_port_event_method tx3904cpu_port_event; + + + +static void +tx3904cpu_finish (struct hw *me) +{ + struct tx3904cpu *controller; + + controller = HW_ZALLOC (me, struct tx3904cpu); + set_hw_data (me, controller); + set_hw_ports (me, tx3904cpu_ports); + set_hw_port_event (me, tx3904cpu_port_event); + + /* Initialize the pending interrupt flags */ + controller->pending_level = 0; + controller->pending_reset = 0; + controller->pending_nmi = 0; + controller->event = NULL; +} + + + +/* An event arrives on an interrupt port */ + +static void +deliver_tx3904cpu_interrupt (struct hw *me, + void *data) +{ + struct tx3904cpu *controller = hw_data (me); + SIM_DESC sd = hw_system (me); + sim_cpu *cpu = STATE_CPU (sd, 0); /* NB: fix CPU 0. */ + address_word cia = CIA_GET (cpu); + +#define CPU cpu +#define SD current_state + + if (controller->pending_reset) + { + controller->pending_reset = 0; + HW_TRACE ((me, "reset pc=0x%08lx", (long) CIA_GET (cpu))); + SignalExceptionNMIReset(); + } + else if (controller->pending_nmi) + { + controller->pending_nmi = 0; + HW_TRACE ((me, "nmi pc=0x%08lx", (long) CIA_GET (cpu))); + SignalExceptionNMIReset(); + } + else if (controller->pending_level) + { + HW_TRACE ((me, "interrupt level=%d pc=0x%08lx sr=0x%08lx", + controller->pending_level, + (long) CIA_GET (cpu), (long) SR)); + + /* Clear CAUSE register. It may stay this way if the interrupt + was cleared with a negative pending_level. */ + CAUSE &= ~ (cause_IP_mask << cause_IP_shift); + + if(controller->pending_level > 0) /* interrupt set */ + { + /* set hardware-interrupt subfields of CAUSE register */ + CAUSE |= (controller->pending_level & cause_IP_mask) << cause_IP_shift; + + /* check for enabled / unmasked interrupts */ + if((SR & status_IEc) && + (controller->pending_level & ((SR >> status_IM_shift) & status_IM_mask))) + { + controller->pending_level = 0; + SignalExceptionInterrupt(0 /* dummy value */); + } + else + { + /* reschedule soon */ + if(controller->event != NULL) + hw_event_queue_deschedule(me, controller->event); + controller->event = + hw_event_queue_schedule (me, 1, deliver_tx3904cpu_interrupt, NULL); + } + } /* interrupt set */ + } +#undef CPU cpu +#undef SD current_state +} + + +static void +tx3904cpu_port_event (struct hw *me, + int my_port, + struct hw *source, + int source_port, + int level) +{ + struct tx3904cpu *controller = hw_data (me); + + switch (my_port) + { + case RESET_PORT: + controller->pending_reset = 1; + HW_TRACE ((me, "port-in reset")); + break; + + case NMI_PORT: + controller->pending_nmi = 1; + HW_TRACE ((me, "port-in nmi")); + break; + + case LEVEL_PORT: + /* level == 0 means that the interrupt was cleared */ + if(level == 0) + controller->pending_level = -1; /* signal end of interrupt */ + else + controller->pending_level = level; + HW_TRACE ((me, "port-in level=%d", level)); + break; + + default: + hw_abort (me, "bad switch"); + break; + } + + /* Schedule an event to be delivered immediately after current + instruction. */ + if(controller->event != NULL) + hw_event_queue_deschedule(me, controller->event); + controller->event = + hw_event_queue_schedule (me, 0, deliver_tx3904cpu_interrupt, NULL); +} + + +const struct hw_descriptor dv_tx3904cpu_descriptor[] = { + { "tx3904cpu", tx3904cpu_finish, }, + { NULL }, +};
dv-tx3904cpu.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: tx.igen =================================================================== --- tx.igen (nonexistent) +++ tx.igen (revision 33) @@ -0,0 +1,46 @@ +// -*- C -*- +// +// toshiba specific instructions. +// + +011100,5.RS,5.RT,5.RD,00000000000:MMINORM:::MADD +"madd r, r":RD == 0 +"madd r, r, r" +*r3900 +{ + signed64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO)) + + ((signed64) EXTEND32 (GPR[RT]) + * (signed64) EXTEND32 (GPR[RS]))); + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + LO = EXTEND32 (prod); + HI = EXTEND32 (VH4_8 (prod)); + TRACE_ALU_RESULT2 (HI, LO); + if(RD != 0 ) + GPR[RD] = LO; +} + + +011100,5.RS,5.RT,5.RD,00000000001:MMINORM:::MADDU +"maddu r, r":RD == 0 +"maddu r, r, r" +*r3900 +{ + unsigned64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO)) + + ((unsigned64) VL4_8 (GPR[RS]) + * (unsigned64) VL4_8 (GPR[RT]))); + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + LO = EXTEND32 (prod); + HI = EXTEND32 (VH4_8 (prod)); + TRACE_ALU_RESULT2 (HI, LO); + if(RD != 0) + GPR[RD] = LO; +} + +000000,CODE.20,001110::CO1:::SDBBP +"sdbbp" +*r3900: +{ + SignalException (DebugBreakPoint, instruction); +} Index: mips3264r2.igen =================================================================== --- mips3264r2.igen (nonexistent) +++ mips3264r2.igen (revision 33) @@ -0,0 +1,259 @@ +// -*- C -*- + +// Simulator definition for the MIPS 32/64 revision 2 instructions. +// Copyright (C) 2004 Free Software Foundation, Inc. +// Contributed by David Ung, of MIPS Technologies. +// +// This file is part of GDB, the GNU debugger. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + + +011111,5.RS,5.RT,5.SIZE,5.LSB,000011::64::DEXT +"dext r, r, , " +*mips64r2: +{ + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); + GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE, LSB); + TRACE_ALU_RESULT1 (GPR[RT]); +} + +011111,5.RS,5.RT,5.SIZE,5.LSB,000001::64::DEXTM +"dextm r, r, , " +*mips64r2: +{ + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); + GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE + 32, LSB); + TRACE_ALU_RESULT1 (GPR[RT]); +} + +011111,5.RS,5.RT,5.SIZE,5.LSB,000010::64::DEXTU +"dextu r, r, , " +*mips64r2: +{ + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); + GPR[RT] = EXTRACTED64 (GPR[RS], LSB + 32 + SIZE, LSB + 32); + TRACE_ALU_RESULT1 (GPR[RT]); +} + + +010000,01011,5.RT,01100,00000,0,00,000::32::DI +"di":RT == 0 +"di r" +*mips32r2: +*mips64r2: +{ + TRACE_ALU_INPUT0 (); + GPR[RT] = EXTEND32 (SR); + SR &= ~status_IE; + TRACE_ALU_RESULT1 (GPR[RT]); +} + + +011111,5.RS,5.RT,5.MSB,5.LSB,000111::64::DINS +"dins r, r, , " +*mips64r2: +{ + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); + if (LSB <= MSB) + GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB, LSB); + TRACE_ALU_RESULT1 (GPR[RT]); +} + +011111,5.RS,5.RT,5.MSB,5.LSB,000101::64::DINSM +"dinsm r, r, , " +*mips64r2: +{ + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); + if (LSB <= MSB + 32) + GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB + 32, LSB); + TRACE_ALU_RESULT1 (GPR[RT]); +} + +011111,5.RS,5.RT,5.MSB,5.LSB,000110::64::DINSU +"dinsu r, r, , " +*mips64r2: +{ + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); + if (LSB <= MSB) + GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << (LSB + 32))) + & MASK64 (MSB + 32, LSB + 32); + TRACE_ALU_RESULT1 (GPR[RT]); +} + + +011111,00000,5.RT,5.RD,00010,100100::64::DSBH +"dsbh r, r" +*mips64r2: +{ + union { unsigned64 d; unsigned16 h[4]; } u; + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT1 (GPR[RT]); + u.d = GPR[RT]; + u.h[0] = SWAP_2 (u.h[0]); + u.h[1] = SWAP_2 (u.h[1]); + u.h[2] = SWAP_2 (u.h[2]); + u.h[3] = SWAP_2 (u.h[3]); + GPR[RD] = u.d; + TRACE_ALU_RESULT1 (GPR[RD]); +} + +011111,00000,5.RT,5.RD,00101,100100::64::DSHD +"dshd r, r" +*mips64r2: +{ + unsigned64 d; + check_u64 (SD_, instruction_0); + TRACE_ALU_INPUT1 (GPR[RT]); + d = GPR[RT]; + GPR[RD] = ((d >> 48) + | (d << 48) + | ((d & 0x0000ffff00000000ULL) >> 16) + | ((d & 0x00000000ffff0000ULL) << 16)); + TRACE_ALU_RESULT1 (GPR[RD]); +} + + +010000,01011,5.RT,01100,00000,1,00,000::32::EI +"ei":RT == 0 +"ei r" +*mips32r2: +*mips64r2: +{ + TRACE_ALU_INPUT0 (); + GPR[RT] = EXTEND32 (SR); + SR |= status_IE; + TRACE_ALU_RESULT1 (GPR[RT]); +} + + +011111,5.RS,5.RT,5.SIZE,5.LSB,000000::32::EXT +"ext r, r, , " +*mips32r2: +*mips64r2: +{ + TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE); + GPR[RT] = EXTEND32 (EXTRACTED32 (GPR[RS], LSB + SIZE, LSB)); + TRACE_ALU_RESULT1 (GPR[RT]); +} + + +010001,00011,5.RT,5.FS,00000000000:COP1Sa:32,f::MFHC1 +"mfhc1 r, f" +*mips32r2: +*mips64r2: +{ + check_fpu (SD_); + if (SizeFGR() == 64) + GPR[RT] = EXTEND32 (WORD64HI (FGR[FS])); + else if ((FS & 0x1) == 0) + GPR[RT] = EXTEND32 (FGR[FS + 1]); + else + { + if (STATE_VERBOSE_P(SD)) + sim_io_eprintf (SD, + "Warning: PC 0x%lx: MFHC1 32-bit use of odd FPR number\n", + (long) CIA); + GPR[RT] = EXTEND32 (0xBADF00D); + } + TRACE_ALU_RESULT (GPR[RT]); +} + +010001,00111,5.RT,5.FS,00000000000:COP1Sa:32,f::MTHC1 +"mthc1 r, f" +*mips32r2: +*mips64r2: +{ + check_fpu (SD_); + if (SizeFGR() == 64) + StoreFPR (FS, fmt_uninterpreted_64, SET64HI (GPR[RT]) | VL4_8 (FGR[FS])); + else if ((FS & 0x1) == 0) + StoreFPR (FS + 1, fmt_uninterpreted_32, VL4_8 (GPR[RT])); + else + { + if (STATE_VERBOSE_P(SD)) + sim_io_eprintf (SD, + "Warning: PC 0x%lx: MTHC1 32-bit use of odd FPR number\n", + (long) CIA); + StoreFPR (FS, fmt_uninterpreted_32, 0xDEADC0DE); + } + TRACE_FP_RESULT (GPR[RT]); +} + + +011111,5.RS,5.RT,5.MSB,5.LSB,000100::32::INS +"ins r, r, , " +*mips32r2: +*mips64r2: +{ + TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB); + if (LSB <= MSB) + GPR[RT] = EXTEND32 (GPR[RT] ^ + ((GPR[RT] ^ (GPR[RS] << LSB)) & MASK32 (MSB, LSB))); + TRACE_ALU_RESULT1 (GPR[RT]); +} + + +011111,00000,5.RT,5.RD,10000,100000::32::SEB +"seb r, r" +*mips32r2: +*mips64r2: +{ + TRACE_ALU_INPUT1 (GPR[RT]); + GPR[RD] = EXTEND8 (GPR[RT]); + TRACE_ALU_RESULT1 (GPR[RD]); +} + +011111,00000,5.RT,5.RD,11000,100000::32::SEH +"seh r, r" +*mips32r2: +*mips64r2: +{ + TRACE_ALU_INPUT1 (GPR[RT]); + GPR[RD] = EXTEND16 (GPR[RT]); + TRACE_ALU_RESULT1 (GPR[RD]); +} + + +000001,5.BASE,11111,16.OFFSET::32::SYNCI +"synci (r)" +*mips32r2: +*mips64r2: +{ + // sync i-cache - nothing to do currently +} + + +011111,00000,5.RT,5.RD,00010,100000::32::WSBH +"wsbh r, r" +*mips32r2: +*mips64r2: +{ + union { unsigned32 w; unsigned16 h[2]; } u; + TRACE_ALU_INPUT1 (GPR[RT]); + u.w = GPR[RT]; + u.h[0] = SWAP_2 (u.h[0]); + u.h[1] = SWAP_2 (u.h[1]); + GPR[RD] = EXTEND32 (u.w); + TRACE_ALU_RESULT1 (GPR[RD]); +} + + + Index: dv-tx3904sio.c =================================================================== --- dv-tx3904sio.c (nonexistent) +++ dv-tx3904sio.c (revision 33) @@ -0,0 +1,621 @@ +/* This file is part of the program GDB, the GNU debugger. + + Copyright (C) 1998, 1999, 2007, 2008 Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + */ + + +#include "sim-main.h" +#include "hw-main.h" +#include "dv-sockser.h" +#include "sim-assert.h" + + +/* DEVICE + + + tx3904sio - tx3904 serial I/O + + + DESCRIPTION + + + Implements one tx3904 serial I/O controller described in the tx3904 + user guide. Three instances are required for SIO0 and SIO1 within + the tx3904, at different base addresses. + + Both internal and system clocks are synthesized as divided versions + of the simulator clock. + + There is no support for: + - CTS/RTS flow control + - baud rate emulation - use infinite speed instead + - general frame format - use 8N1 + - multi-controller system + - DMA - use interrupt-driven or polled-I/O instead + + + PROPERTIES + + + reg + + Base of SIO control register bank. must equal 0x100. + Register offsets: 0: SLCR: line control register + 4: SLSR: line status register + 8: SDICR: DMA/interrupt control register + 12: SDISR: DMA/interrupt status register + 16: SFCR: FIFO control register + 20: SBGR: baud rate control register + 32: transfer FIFO buffer + 48: transfer FIFO buffer + + backend {tcp | stdio} + + Use dv-sockser TCP-port backend or stdio for backend. Default: stdio. + + + + PORTS + + + int (output) + + Interrupt port. An event is generated when a timer interrupt + occurs. + + + reset (input) + + Reset port. + + */ + + + +/* static functions */ + +struct tx3904sio_fifo; + +static void tx3904sio_tickle(struct hw*); +static int tx3904sio_fifo_nonempty(struct hw*, struct tx3904sio_fifo*); +static char tx3904sio_fifo_pop(struct hw*, struct tx3904sio_fifo*); +static void tx3904sio_fifo_push(struct hw*, struct tx3904sio_fifo*, char); +static void tx3904sio_fifo_reset(struct hw*, struct tx3904sio_fifo*); +static void tx3904sio_poll(struct hw*, void* data); + + +/* register numbers; each is one word long */ +enum +{ + SLCR_REG = 0, + SLSR_REG = 1, + SDICR_REG = 2, + SDISR_REG = 3, + SFCR_REG = 4, + SBGR_REG = 5, + TFIFO_REG = 8, + SFIFO_REG = 12, +}; + + + +/* port ID's */ + +enum + { + RESET_PORT, + INT_PORT, +}; + + +static const struct hw_port_descriptor tx3904sio_ports[] = +{ + { "int", INT_PORT, 0, output_port, }, + { "reset", RESET_PORT, 0, input_port, }, + { NULL, }, +}; + + + +/* Generic FIFO */ +struct tx3904sio_fifo +{ + int size, used; + unsigned_1 *buffer; +}; + + + +/* The timer/counter register internal state. Note that we store + state using the control register images, in host endian order. */ + +struct tx3904sio +{ + address_word base_address; /* control register base */ + enum {sio_tcp, sio_stdio} backend; /* backend */ + + struct tx3904sio_fifo rx_fifo, tx_fifo; /* FIFOs */ + + unsigned_4 slcr; +#define SLCR_WR_MASK 0xe17f0000U +#define SLCR_SET_BYTE(c,o,b) ((c)->slcr = SLCR_WR_MASK & (((c)->slcr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8))) + unsigned_4 slsr; +#define SLSR_WR_MASK 0x00000000 /* UFER/UPER/UOER unimplemented */ + unsigned_4 sdicr; +#define SDICR_WR_MASK 0x000f0000U +#define SDICR_SET_BYTE(c,o,b) ((c)->sdicr = SDICR_WR_MASK & (((c)->sdicr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8))) +#define SDICR_GET_SDMAE(c) ((c)->sdicr & 0x00080000) +#define SDICR_GET_ERIE(c) ((c)->sdicr & 0x00040000) +#define SDICR_GET_TDIE(c) ((c)->sdicr & 0x00020000) +#define SDICR_GET_RDIE(c) ((c)->sdicr & 0x00010000) + unsigned_4 sdisr; +#define SDISR_WR_MASK 0x00070000U +#define SDISR_SET_BYTE(c,o,b) ((c)->sdisr = SDISR_WR_MASK & (((c)->sdisr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8))) +#define SDISR_CLEAR_FLAG_BYTE(c,o,b) ((c)->sdisr = SDISR_WR_MASK & (((c)->sdisr & ~LSMASK32((o)*8+7,(o)*8)) & ((b)<< (o)*8))) +#define SDISR_GET_TDIS(c) ((c)->sdisr & 0x00020000) +#define SDISR_SET_TDIS(c) ((c)->sdisr |= 0x00020000) +#define SDISR_GET_RDIS(c) ((c)->sdisr & 0x00010000) +#define SDISR_SET_RDIS(c) ((c)->sdisr |= 0x00010000) + unsigned_4 sfcr; +#define SFCR_WR_MASK 0x001f0000U +#define SFCR_SET_BYTE(c,o,b) ((c)->sfcr = SFCR_WR_MASK & (((c)->sfcr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8))) +#define SFCR_GET_TFRST(c) ((c)->sfcr & 0x00040000) +#define SFCR_GET_RFRST(c) ((c)->sfcr & 0x00020000) +#define SFCR_GET_FRSTE(c) ((c)->sfcr & 0x00010000) + unsigned_4 sbgr; +#define SBGR_WR_MASK 0x03ff0000U +#define SBGR_SET_BYTE(c,o,b) ((c)->sbgr = SBGR_WR_MASK & (((c)->sbgr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8))) + + /* Periodic I/O polling */ + struct hw_event* poll_event; +}; + + + +/* Finish off the partially created hw device. Attach our local + callbacks. Wire up our port names etc */ + +static hw_io_read_buffer_method tx3904sio_io_read_buffer; +static hw_io_write_buffer_method tx3904sio_io_write_buffer; +static hw_port_event_method tx3904sio_port_event; + + +static void +attach_tx3904sio_regs (struct hw *me, + struct tx3904sio *controller) +{ + unsigned_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain one addr/size entry"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, + &attach_address, + me); + hw_unit_size_to_attach_size (hw_parent (me), + ®.size, + &attach_size, me); + + hw_attach_address (hw_parent (me), 0, + attach_space, attach_address, attach_size, + me); + + if(hw_find_property(me, "backend") != NULL) + { + const char* value = hw_find_string_property(me, "backend"); + if(! strcmp(value, "tcp")) + controller->backend = sio_tcp; + else if(! strcmp(value, "stdio")) + controller->backend = sio_stdio; + else + hw_abort(me, "illegal value for backend parameter `%s': use tcp or stdio", value); + } + + controller->base_address = attach_address; +} + + +static void +tx3904sio_finish (struct hw *me) +{ + struct tx3904sio *controller; + + controller = HW_ZALLOC (me, struct tx3904sio); + set_hw_data (me, controller); + set_hw_io_read_buffer (me, tx3904sio_io_read_buffer); + set_hw_io_write_buffer (me, tx3904sio_io_write_buffer); + set_hw_ports (me, tx3904sio_ports); + set_hw_port_event (me, tx3904sio_port_event); + + /* Preset defaults */ + controller->backend = sio_stdio; + + /* Attach ourself to our parent bus */ + attach_tx3904sio_regs (me, controller); + + /* Initialize to reset state */ + tx3904sio_fifo_reset(me, & controller->rx_fifo); + tx3904sio_fifo_reset(me, & controller->tx_fifo); + controller->slsr = controller->sdicr + = controller->sdisr = controller->sfcr + = controller->sbgr = 0; + controller->slcr = 0x40000000; /* set TWUB */ + controller->sbgr = 0x03ff0000; /* set BCLK=3, BRD=FF */ + controller->poll_event = NULL; +} + + + +/* An event arrives on an interrupt port */ + +static void +tx3904sio_port_event (struct hw *me, + int my_port, + struct hw *source, + int source_port, + int level) +{ + struct tx3904sio *controller = hw_data (me); + + switch (my_port) + { + case RESET_PORT: + { + HW_TRACE ((me, "reset")); + + tx3904sio_fifo_reset(me, & controller->rx_fifo); + tx3904sio_fifo_reset(me, & controller->tx_fifo); + controller->slsr = controller->sdicr + = controller->sdisr = controller->sfcr + = controller->sbgr = 0; + controller->slcr = 0x40000000; /* set TWUB */ + controller->sbgr = 0x03ff0000; /* set BCLK=3, BRD=FF */ + /* Don't interfere with I/O poller. */ + break; + } + + default: + hw_abort (me, "Event on unknown port %d", my_port); + break; + } +} + + +/* generic read/write */ + +static unsigned +tx3904sio_io_read_buffer (struct hw *me, + void *dest, + int space, + unsigned_word base, + unsigned nr_bytes) +{ + struct tx3904sio *controller = hw_data (me); + unsigned byte; + + HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes)); + + /* tickle fifos */ + tx3904sio_tickle(me); + + for (byte = 0; byte < nr_bytes; byte++) + { + address_word address = base + byte; + int reg_number = (address - controller->base_address) / 4; + int reg_offset = (address - controller->base_address) % 4; + unsigned_4 register_value; /* in target byte order */ + + /* fill in entire register_value word */ + switch (reg_number) + { + case SLCR_REG: register_value = controller->slcr; break; + case SLSR_REG: register_value = controller->slsr; break; + case SDICR_REG: register_value = controller->sdicr; break; + case SDISR_REG: register_value = controller->sdisr; break; + case SFCR_REG: register_value = controller->sfcr; break; + case SBGR_REG: register_value = controller->sbgr; break; + case TFIFO_REG: register_value = 0; break; + case SFIFO_REG: + /* consume rx fifo for MS byte */ + if(reg_offset == 0 && tx3904sio_fifo_nonempty(me, & controller->rx_fifo)) + register_value = (tx3904sio_fifo_pop(me, & controller->rx_fifo) << 24); + else + register_value = 0; + break; + default: register_value = 0; + } + + /* write requested byte out */ + register_value = H2T_4(register_value); + /* HW_TRACE ((me, "byte %d %02x", reg_offset, ((char*)& register_value)[reg_offset])); */ + memcpy ((char*) dest + byte, ((char*)& register_value)+reg_offset, 1); + } + + return nr_bytes; +} + + + +static unsigned +tx3904sio_io_write_buffer (struct hw *me, + const void *source, + int space, + unsigned_word base, + unsigned nr_bytes) +{ + struct tx3904sio *controller = hw_data (me); + unsigned byte; + + HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes)); + for (byte = 0; byte < nr_bytes; byte++) + { + address_word address = base + byte; + unsigned_1 write_byte = ((const unsigned char*) source)[byte]; + int reg_number = (address - controller->base_address) / 4; + int reg_offset = 3 - (address - controller->base_address) % 4; + + /* HW_TRACE ((me, "byte %d %02x", reg_offset, write_byte)); */ + + /* fill in entire register_value word */ + switch (reg_number) + { + case SLCR_REG: + SLCR_SET_BYTE(controller, reg_offset, write_byte); + break; + + case SLSR_REG: /* unwriteable */ break; + + case SDICR_REG: + { + unsigned_4 last_int, next_int; + + /* deassert interrupt upon clear */ + last_int = controller->sdisr & controller->sdicr; + /* HW_TRACE ((me, "sdicr - sdisr %08x sdicr %08x", + controller->sdisr, controller->sdicr)); */ + SDICR_SET_BYTE(controller, reg_offset, write_byte); + /* HW_TRACE ((me, "sdicr + sdisr %08x sdicr %08x", + controller->sdisr, controller->sdicr)); */ + next_int = controller->sdisr & controller->sdicr; + + if(SDICR_GET_SDMAE(controller)) + hw_abort(me, "Cannot support DMA-driven sio."); + + if(~last_int & next_int) /* any bits set? */ + hw_port_event(me, INT_PORT, 1); + if(last_int & ~next_int) /* any bits cleared? */ + hw_port_event(me, INT_PORT, 0); + } + break; + + case SDISR_REG: + { + unsigned_4 last_int, next_int; + + /* deassert interrupt upon clear */ + last_int = controller->sdisr & controller->sdicr; + /* HW_TRACE ((me, "sdisr - sdisr %08x sdicr %08x", + controller->sdisr, controller->sdicr)); */ + SDISR_CLEAR_FLAG_BYTE(controller, reg_offset, write_byte); + /* HW_TRACE ((me, "sdisr + sdisr %08x sdicr %08x", + controller->sdisr, controller->sdicr)); */ + next_int = controller->sdisr & controller->sdicr; + + if(~last_int & next_int) /* any bits set? */ + hw_port_event(me, INT_PORT, 1); + if(last_int & ~next_int) /* any bits cleared? */ + hw_port_event(me, INT_PORT, 0); + } + break; + + case SFCR_REG: + SFCR_SET_BYTE(controller, reg_offset, write_byte); + if(SFCR_GET_FRSTE(controller)) + { + if(SFCR_GET_TFRST(controller)) tx3904sio_fifo_reset(me, & controller->tx_fifo); + if(SFCR_GET_RFRST(controller)) tx3904sio_fifo_reset(me, & controller->rx_fifo); + } + break; + + case SBGR_REG: + SBGR_SET_BYTE(controller, reg_offset, write_byte); + break; + + case SFIFO_REG: /* unwriteable */ break; + + case TFIFO_REG: + if(reg_offset == 3) /* first byte */ + tx3904sio_fifo_push(me, & controller->tx_fifo, write_byte); + break; + + default: + HW_TRACE ((me, "write to illegal register %d", reg_number)); + } + } /* loop over bytes */ + + /* tickle fifos */ + tx3904sio_tickle(me); + + return nr_bytes; +} + + + + + + +/* Send enqueued characters from tx_fifo and trigger TX interrupt. +Receive characters into rx_fifo and trigger RX interrupt. */ +void +tx3904sio_tickle(struct hw *me) +{ + struct tx3904sio* controller = hw_data(me); + int c; + char cc; + unsigned_4 last_int, next_int; + + /* HW_TRACE ((me, "tickle backend: %02x", controller->backend)); */ + switch(controller->backend) + { + case sio_tcp: + + while(tx3904sio_fifo_nonempty(me, & controller->tx_fifo)) + { + cc = tx3904sio_fifo_pop(me, & controller->tx_fifo); + dv_sockser_write(hw_system(me), cc); + HW_TRACE ((me, "tcp output: %02x", cc)); + } + + c = dv_sockser_read(hw_system(me)); + while(c != -1) + { + cc = (char) c; + HW_TRACE ((me, "tcp input: %02x", cc)); + tx3904sio_fifo_push(me, & controller->rx_fifo, cc); + c = dv_sockser_read(hw_system(me)); + } + break; + + case sio_stdio: + + while(tx3904sio_fifo_nonempty(me, & controller->tx_fifo)) + { + cc = tx3904sio_fifo_pop(me, & controller->tx_fifo); + sim_io_write_stdout(hw_system(me), & cc, 1); + sim_io_flush_stdout(hw_system(me)); + HW_TRACE ((me, "stdio output: %02x", cc)); + } + + c = sim_io_poll_read(hw_system(me), 0 /* stdin */, & cc, 1); + while(c == 1) + { + HW_TRACE ((me, "stdio input: %02x", cc)); + tx3904sio_fifo_push(me, & controller->rx_fifo, cc); + c = sim_io_poll_read(hw_system(me), 0 /* stdin */, & cc, 1); + } + + break; + + default: + hw_abort(me, "Illegal backend mode: %d", controller->backend); + } + + /* Update RDIS / TDIS flags */ + last_int = controller->sdisr & controller->sdicr; + /* HW_TRACE ((me, "tickle - sdisr %08x sdicr %08x", controller->sdisr, controller->sdicr)); */ + if(tx3904sio_fifo_nonempty(me, & controller->rx_fifo)) + SDISR_SET_RDIS(controller); + if(! tx3904sio_fifo_nonempty(me, & controller->tx_fifo)) + SDISR_SET_TDIS(controller); + next_int = controller->sdisr & controller->sdicr; + /* HW_TRACE ((me, "tickle + sdisr %08x sdicr %08x", controller->sdisr, controller->sdicr)); */ + + if(~last_int & next_int) /* any bits set? */ + hw_port_event(me, INT_PORT, 1); + if(last_int & ~next_int) /* any bits cleared? */ + hw_port_event(me, INT_PORT, 0); + + /* Add periodic polling for this port, if it's not already going. */ + if(controller->poll_event == NULL) + { + controller->poll_event = hw_event_queue_schedule (me, 1000, + tx3904sio_poll, NULL); + + } +} + + + + +int +tx3904sio_fifo_nonempty(struct hw* me, struct tx3904sio_fifo* fifo) +{ + /* HW_TRACE ((me, "fifo used: %d", fifo->used)); */ + return(fifo->used > 0); +} + + +char +tx3904sio_fifo_pop(struct hw* me, struct tx3904sio_fifo* fifo) +{ + char it; + ASSERT(fifo->used > 0); + ASSERT(fifo->buffer != NULL); + it = fifo->buffer[0]; + memcpy(& fifo->buffer[0], & fifo->buffer[1], fifo->used - 1); + fifo->used --; + /* HW_TRACE ((me, "pop fifo -> %02x", it)); */ + return it; +} + + +void +tx3904sio_fifo_push(struct hw* me, struct tx3904sio_fifo* fifo, char it) +{ + /* HW_TRACE ((me, "push %02x -> fifo", it)); */ + if(fifo->size == fifo->used) /* full */ + { + int next_size = fifo->size * 2 + 16; + char* next_buf = zalloc(next_size); + memcpy(next_buf, fifo->buffer, fifo->used); + + if(fifo->buffer != NULL) zfree(fifo->buffer); + fifo->buffer = next_buf; + fifo->size = next_size; + } + + fifo->buffer[fifo->used] = it; + fifo->used ++; +} + + +void +tx3904sio_fifo_reset(struct hw* me, struct tx3904sio_fifo* fifo) +{ + /* HW_TRACE ((me, "reset fifo")); */ + fifo->used = 0; + fifo->size = 0; + zfree(fifo->buffer); + fifo->buffer = 0; +} + + +void +tx3904sio_poll(struct hw* me, void* ignored) +{ + struct tx3904sio* controller = hw_data (me); + tx3904sio_tickle (me); + hw_event_queue_deschedule (me, controller->poll_event); + controller->poll_event = hw_event_queue_schedule (me, 1000, + tx3904sio_poll, NULL); +} + + + +const struct hw_descriptor dv_tx3904sio_descriptor[] = { + { "tx3904sio", tx3904sio_finish, }, + { NULL }, +};
dv-tx3904sio.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property

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