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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

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  • This comparison shows the changes necessary to convert path
    /openrisc/tags/gdb/gdb-6.8/gdb-6.8.openrisc-2.1/sim/testsuite/sim/arm/xscale
    from Rev 24 to Rev 33
    Reverse comparison

Rev 24 → Rev 33

/blx.cgs
0,0 → 1,31
# arm testcase for bl$cond $offset24
# mach: all
 
.include "testutils.inc"
 
start
 
.arm
blx thumb
.thumb
.thumb_func
thumb:
nop
blx next
blx PASS
nop
nop
 
.section text1, "ax"
.arm
next:
add r0, r1, r0
bx lr
 
FAIL:
fail
PASS:
pass
 
 
/mia.cgs
0,0 → 1,35
# XSCALE testcase for MIA
# mach: xscale
# as: -mcpu=xscale
 
.include "testutils.inc"
 
start
 
.global mia
mia:
# Enable access to CoProcessors 0 & 1 before
# we attempt these instructions.
 
mvi_h_gr r1, 3
mcr p15, 0, r1, cr15, cr1, 0
 
# Test Multilply Accumulate
mvi_h_gr r0, 0x11223344
mvi_h_gr r1, 0x55667788
mvi_h_gr r2, 0x12345678
mvi_h_gr r3, 0x9abcdef0
 
mar acc0, r0, r1
 
mia acc0, r2, r3
mra r0, r1, acc0
test_h_gr r0, 0x354f53c4
test_h_gr r1, 0x4e330b5e
test_h_gr r2, 0x12345678
test_h_gr r3, 0x9abcdef0
 
pass
/miaxy.cgs
0,0 → 1,89
# XSCALE testcase for MIAxy
# mach: xscale
# as: -mcpu=xscale
 
.include "testutils.inc"
 
start
 
.global miaXY
miaXY:
# Enable access to CoProcessors 0 & 1 before
# we attempt these instructions.
 
mvi_h_gr r1, 3
mcr p15, 0, r1, cr15, cr1, 0
 
# Test Bottom Bottom Multilply Accumulate
mvi_h_gr r0, 0x11223344
mvi_h_gr r1, 0x55667788
mvi_h_gr r2, 0x12345678
mvi_h_gr r3, 0x9abcdef0
 
mar acc0, r0, r1
 
miaBB acc0, r2, r3
mra r0, r1, acc0
test_h_gr r0, 0x05f753c4
test_h_gr r1, 0x55667788
test_h_gr r2, 0x12345678
test_h_gr r3, 0x9abcdef0
 
# Test Bottom Top Multilply Accumulate
mvi_h_gr r0, 0x11223344
mvi_h_gr r1, 0x55667788
mvi_h_gr r2, 0x12345678
mvi_h_gr r3, 0x9abcdef0
 
mar acc0, r0, r1
 
miaBT acc0, r2, r3
mra r0, r1, acc0
test_h_gr r0, 0xeeede364
test_h_gr r1, 0x55667787
test_h_gr r2, 0x12345678
test_h_gr r3, 0x9abcdef0
 
# Test Top Bottom Multilply Accumulate
mvi_h_gr r0, 0x11223344
mvi_h_gr r1, 0x55667788
mvi_h_gr r2, 0x12345678
mvi_h_gr r3, 0x9abcdef0
 
mar acc0, r0, r1
 
miaTB acc0, r2, r3
mra r0, r1, acc0
test_h_gr r0, 0x0ec85c04
test_h_gr r1, 0x55667788
test_h_gr r2, 0x12345678
test_h_gr r3, 0x9abcdef0
 
# Test Top Top Multilply Accumulate
mvi_h_gr r0, 0x11223344
mvi_h_gr r1, 0x55667788
mvi_h_gr r2, 0x12345678
mvi_h_gr r3, 0x9abcdef0
 
mar acc0, r0, r1
 
miaTT acc0, r2, r3
mra r0, r1, acc0
test_h_gr r0, 0x09eed974
test_h_gr r1, 0x55667788
test_h_gr r2, 0x12345678
test_h_gr r3, 0x9abcdef0
 
pass
/testutils.inc
0,0 → 1,118
# r0-r3 are used as tmps, consider them call clobbered by these macros.
# This uses the angel rom monitor calls.
# ??? How do we use the \@ facility of .macros ???
# @ is the comment char!
 
.macro mvi_h_gr reg, val
ldr \reg,[pc]
b . + 8
.word \val
.endm
 
.macro mvaddr_h_gr reg, addr
ldr \reg,[pc]
b . + 8
.word \addr
.endm
 
.macro start
.data
failmsg:
.asciz "fail\n"
passmsg:
.asciz "pass\n"
.text
 
do_pass:
ldr r1, passmsg_addr
mov r0, #4
swi #0x123456
exit 0
passmsg_addr:
.word passmsg
 
do_fail:
ldr r1, failmsg_addr
mov r0, #4
swi #0x123456
exit 1
failmsg_addr:
.word failmsg
 
.global _start
_start:
.endm
 
# *** Other macros know pass/fail are 4 bytes in size! Yuck.
 
.macro pass
b do_pass
.endm
 
.macro fail
b do_fail
.endm
 
.macro exit rc
# ??? This works with the ARMulator but maybe not others.
#mov r0, #\rc
#swi #1
# This seems to be portable (though it ignores rc).
mov r0,#0x18
mvi_h_gr r1, 0x20026
swi #0x123456
# If that returns, punt with a sigill.
stc 0,cr0,[r0]
.endm
 
# Other macros know this only clobbers r0.
# WARNING: It also clobbers the condition codes (FIXME).
.macro test_h_gr reg, val
mvaddr_h_gr r0, \val
cmp \reg, r0
beq . + 8
fail
.endm
 
.macro mvi_h_cnvz c, n, v, z
mov r0, #0
.if \c
orr r0, r0, #0x20000000
.endif
.if \n
orr r0, r0, #0x80000000
.endif
.if \v
orr r0, r0, #0x10000000
.endif
.if \z
orr r0, r0, #0x40000000
.endif
mrs r1, cpsr
bic r1, r1, #0xf0000000
orr r1, r1, r0
msr cpsr, r1
# ??? nops needed
.endm
 
# ??? Preserve condition codes?
.macro test_h_cnvz c, n, v, z
mov r0, #0
.if \c
orr r0, r0, #0x20000000
.endif
.if \n
orr r0, r0, #0x80000000
.endif
.if \v
orr r0, r0, #0x10000000
.endif
.if \z
orr r0, r0, #0x40000000
.endif
mrs r1, cpsr
and r1, r1, #0xf0000000
cmp r0, r1
beq . + 8
fail
.endm
/miaph.cgs
0,0 → 1,35
# XSCALE testcase for MIAPH
# mach: xscale
# as: -mcpu=xscale
 
.include "testutils.inc"
 
start
 
.global miaph
miaph:
# Enable access to CoProcessors 0 & 1 before
# we attempt these instructions.
 
mvi_h_gr r1, 3
mcr p15, 0, r1, cr15, cr1, 0
 
# Test Multilply Accumulate
mvi_h_gr r0, 0x11223344
mvi_h_gr r1, 0x55667788
mvi_h_gr r2, 0x12345678
mvi_h_gr r3, 0x9abcdef0
 
mar acc0, r0, r1
 
miaph acc0, r2, r3
mra r0, r1, acc0
test_h_gr r0, 0xfec3f9f4
test_h_gr r1, 0x55667787
test_h_gr r2, 0x12345678
test_h_gr r3, 0x9abcdef0
 
pass
/mra.cgs
0,0 → 1,30
# XScale testcase for MAR and MRA
# mach: xscale
# as: -mcpu=xscale
 
.include "testutils.inc"
 
start
 
.global mar_mra
mar_mra:
mvi_h_gr r2,0
mvi_h_gr r3,0
mvi_h_gr r4,0x0000EFA0
mvi_h_gr r5,0xA0A0A0A0
 
# Enable access to CoProcessors 0 & 1 before
# we attempt these instructions.
 
mvi_h_gr r1, 3
mcr p15, 0, r1, cr15, cr1, 0
mar acc0, r5, r4
mra r2, r3, acc0
test_h_gr r2,0xA0A0A0A0
test_h_gr r3,0x0000EFA0
test_h_gr r4,0x0000EFA0
test_h_gr r5,0xA0A0A0A0
pass
/xscale.exp
0,0 → 1,28
# XSCALE simulator testsuite.
 
if { [istarget xscale*-*-*] } {
# load support procs (none yet)
# load_lib cgen.exp
 
# all machines
set all_machs "xscale"
 
if [is_remote host] {
remote_download host $srcdir/$subdir/testutils.inc
}
 
# The .cgs suffix is for "cgen .s".
foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] {
# If we're only testing specific files and this isn't one of them,
# skip it.
if ![runtest_file_p $runtests $src] {
continue
}
 
run_sim_test $src $all_machs
}
 
if [is_remote host] {
remote_file host delete testutils.inc
}
}

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