URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
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- This comparison shows the changes necessary to convert path
/openrisc/tags/gdb/gdb-6.8/gdb-6.8.openrisc-2.1/sim/testsuite/sim/cris/asm
- from Rev 24 to Rev 33
- ↔ Reverse comparison
Rev 24 → Rev 33
/cmpr.ms
0,0 → 1,102
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: ffffffff\n2\nffff\nffffffff\n78134452\nffffffff\n2\nffff\nfedaffff\n78134452\nffffffff\n2\nff\nfeda49ff\n78134452\n85649222\n |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
moveq -2,r4 |
cmp.d r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
moveq 1,r4 |
cmp.d r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xffff,r3 |
move.d -0xffff,r4 |
cmp.d r4,r3 |
test_cc 0 0 0 1 |
dumpr3 ; ffff |
|
moveq 1,r4 |
moveq -1,r3 |
cmp.d r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d -0x5432f789,r4 |
move.d 0x78134452,r3 |
cmp.d r4,r3 |
test_cc 1 0 1 1 |
dumpr3 ; 78134452 |
|
moveq -1,r3 |
moveq -2,r4 |
cmp.w r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
moveq 1,r4 |
cmp.w r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xffff,r3 |
move.d -0xffff,r4 |
cmp.w r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; ffff |
|
move.d 0xfedaffff,r3 |
move.d -0xfedaffff,r4 |
cmp.w r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fedaffff |
|
move.d -0x5432f789,r4 |
move.d 0x78134452,r3 |
cmp.w r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 78134452 |
|
moveq -1,r3 |
moveq -2,r4 |
cmp.b r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
moveq 1,r4 |
cmp.b r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d -0xff,r4 |
move.d 0xff,r3 |
cmp.b r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; ff |
|
move.d -0xfeda49ff,r4 |
move.d 0xfeda49ff,r3 |
cmp.b r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; feda49ff |
|
move.d -0x5432f789,r4 |
move.d 0x78134452,r3 |
cmp.b r4,r3 |
test_cc 1 0 0 1 |
dumpr3 ; 78134452 |
|
move.d 0x85649222,r3 |
move.d 0x77445622,r4 |
cmp.b r4,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 85649222 |
|
quit |
/x7-v10.ms
0,0 → 1,31
#mach: crisv10 |
#ld: --section-start=.text=0 |
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n |
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: c 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnzvc 4\n |
#output: e 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 10 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n |
#output: 14 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 3\n |
#output: 18 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 3\n |
#output: 20 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 4\n |
#sim: --cris-trace=basic |
|
; With a "--cris-trace=all", cycles for the third and last line would be 5. |
|
; Check that prefix+insn are traced as one. |
|
.include "testutils.inc" |
startnostack |
nop |
move.d [0f],r3 |
nop |
moveq 0,r4 |
move.d [r3+r4.b],r5 |
move.d [r3+4],r5 |
bdap.d 0,r3 |
move.d [r3],r5 |
break 15 |
.p2align 2 |
0: |
.dword 0b |
.dword 0b |
/tmvm1.ms
0,0 → 1,53
#mach: crisv32 |
#output: Basic clock cycles, total @: 18\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 6\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
|
; Check that movem to register followed by register write dword |
; to one of the registers is logged as needing two stall cycles, |
; regardless of size. |
|
.include "testutils.inc" |
startnostack |
move.d 0f,r5 |
moveq 0,r8 |
moveq 0,r9 |
|
movem [r5],r4 |
move.d r8,r1 |
addq 1,r1 ; 2 cycles. |
|
movem [r5],r4 |
move.w r8,r1 |
addq 1,r1 ; 2 cycles. |
|
movem [r5],r4 |
move.b r8,r1 |
addq 1,r1 ; 2 cycles. |
|
movem [r5],r4 |
move.b r8,r1 |
addq 1,r9 |
|
movem [r5],r4 |
move.d r8,r1 |
addq 1,r8 |
|
break 15 |
|
.data |
.p2align 5 |
0: |
.dword 0b |
.dword 0b |
.dword 0b |
.dword 0b |
.dword 0b |
/x5-v32.ms
0,0 → 1,9
#mach: crisv32 |
#ld: --section-start=.text=0 |
#sim: --cris-trace=basic |
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n |
#output: 8 0 0 0 0 0 14 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: a 0 0 0 0 1 14 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: c 0 0 0 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: e 0 0 2 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
.include "tmemv10.ms" |
/movsr.ms
0,0 → 1,46
# mach: crisv3 crisv8 crisv10 crisv32 |
# output: 5\nfffffff5\n5\nfffffff5\n0\n |
|
; Movs between registers. Check that sign-extension is performed and the |
; full register is set. |
|
.include "testutils.inc" |
start |
moveq -1,r5 |
moveq 5,r4 |
move.b r4,r5 |
moveq -1,r3 |
movs.b r5,r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
moveq 0,r5 |
moveq -11,r4 |
move.b r4,r5 |
moveq 0,r3 |
movs.b r5,r3 |
test_move_cc 1 0 0 0 |
dumpr3 |
|
moveq -1,r5 |
moveq 5,r4 |
move.w r4,r5 |
moveq -1,r3 |
movs.w r5,r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
moveq 0,r5 |
moveq -11,r4 |
move.w r4,r5 |
moveq 0,r3 |
movs.w r5,r3 |
test_move_cc 1 0 0 0 |
dumpr3 |
|
moveq 0,r5 |
movs.b r5,r3 |
test_move_cc 0 1 0 0 |
dumpr3 |
|
quit |
/movempc.ms
0,0 → 1,8
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
move.d _start,r12 |
move.d [r12],pc |
/movur.ms
0,0 → 1,45
# mach: crisv3 crisv8 crisv10 crisv32 |
# output: 5\nf5\n5\nfff5\n0\n |
|
; Movu between registers. Check that zero-extension is performed and the |
; full register is set. |
|
.include "testutils.inc" |
start |
moveq -1,r5 |
moveq 5,r4 |
move.b r4,r5 |
moveq -1,r3 |
movu.b r5,r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
moveq 0,r5 |
moveq -11,r4 |
move.b r4,r5 |
moveq -1,r3 |
movu.b r5,r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
moveq -1,r5 |
moveq 5,r4 |
move.w r4,r5 |
moveq -1,r3 |
movu.w r5,r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
moveq 0,r5 |
moveq -11,r4 |
move.w r4,r5 |
moveq -1,r3 |
movu.w r5,r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
movu.w 0,r3 |
test_move_cc 0 1 0 0 |
dumpr3 |
|
quit |
/clrjmp1.ms
0,0 → 1,36
# mach: crisv3 crisv8 crisv10 crisv32 |
# output: ffffff00\n |
|
; A bug resulting in a non-effectual clear.b discovered running the GCC |
; testsuite; jump actually wrote to p0. |
|
.include "testutils.inc" |
|
start |
jump 1f |
nop |
.p2align 8 |
1: |
move.d y,r4 |
|
.if 0 == ..asm.arch.cris.v32 |
; There was a bug causing this insn to set special register p0 |
; (byte-clear) to 8 (low 8 bits of location after insn). |
jump [r4+] |
.endif |
|
1: |
move.d 0f,r4 |
|
; The corresponding bug would cause this insn too, to set p0. |
jump r4 |
nop |
quit |
0: |
moveq -1,r3 |
clear.b r3 |
dumpr3 |
quit |
|
y: |
.dword 1b |
/swap.ms
0,0 → 1,87
# mach: crisv8 crisv10 crisv32 |
# output: 1ec8224a\n13785244\nc81e4a22\n44527813\n224a1ec8\n52441378\n4a22c81e\n87ecbbad\ne137ddb5\nec87adbb\n37e1b5dd\nbbad87ec\nddb5e137\nadbbec87\nb5dd37e1\n0\n |
|
.include "testutils.inc" |
start |
move.d 0x78134452,r4 |
move.d r4,r3 |
swapr r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1ec8224a |
|
move.d r4,r3 |
swapb r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 13785244 |
|
move.d r4,r3 |
swapbr r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; c81e4a22 |
|
move.d r4,r3 |
swapw r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 44527813 |
|
move.d r4,r3 |
swapwr r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 224a1ec8 |
|
move.d r4,r3 |
swapwb r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 52441378 |
|
move.d r4,r3 |
swapwbr r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 4a22c81e |
|
move.d r4,r3 |
swapn r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; 87ecbbad |
|
move.d r4,r3 |
swapnr r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; e137ddb5 |
|
move.d r4,r3 |
swapnb r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ec87adbb |
|
move.d r4,r3 |
swapnbr r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 37e1b5dd |
|
move.d r4,r3 |
swapnw r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; bbad87ec |
|
move.d r4,r3 |
swapnwr r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ddb5e137 |
|
move.d r4,r3 |
swapnwb r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; adbbec87 |
|
move.d r4,r3 |
swapnwbr r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; b5dd37e1 |
|
moveq -1,r3 |
swapnwbr r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
|
quit |
/raw2.ms
0,0 → 1,22
; Checking read-after-write: write-then-write unaffected. |
#mach: crisv32 |
#output: Basic clock cycles, total @: 4\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
.include "testutils.inc" |
startnostack |
.lcomm x,4 |
.lcomm y,4 |
move.d x,$r0 |
move.d y,$r1 |
move.d $r1,[$r0] |
move.d $r0,[$r1] |
break 15 |
/subr.ms
0,0 → 1,102
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n85649200\n |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
moveq -2,r4 |
sub.d r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
|
moveq 2,r3 |
moveq 1,r4 |
sub.d r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
|
move.d 0xffff,r3 |
move.d -0xffff,r4 |
sub.d r4,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1fffe |
|
moveq 1,r4 |
moveq -1,r3 |
sub.d r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fffffffe |
|
move.d -0x5432f789,r4 |
move.d 0x78134452,r3 |
sub.d r4,r3 |
test_cc 1 0 1 1 |
dumpr3 ; cc463bdb |
|
moveq -1,r3 |
moveq -2,r4 |
sub.w r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; ffff0001 |
|
moveq 2,r3 |
moveq 1,r4 |
sub.w r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
|
move.d 0xffff,r3 |
move.d -0xffff,r4 |
sub.w r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fffe |
|
move.d 0xfedaffff,r3 |
move.d -0xfedaffff,r4 |
sub.w r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fedafffe |
|
move.d -0x5432f789,r4 |
move.d 0x78134452,r3 |
sub.w r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 78133bdb |
|
moveq -1,r3 |
moveq -2,r4 |
sub.b r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; ffffff01 |
|
moveq 2,r3 |
moveq 1,r4 |
sub.b r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
|
move.d -0xff,r4 |
move.d 0xff,r3 |
sub.b r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fe |
|
move.d -0xfeda49ff,r4 |
move.d 0xfeda49ff,r3 |
sub.b r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; feda49fe |
|
move.d -0x5432f789,r4 |
move.d 0x78134452,r3 |
sub.b r4,r3 |
test_cc 1 0 0 1 |
dumpr3 ; 781344db |
|
move.d 0x85649222,r3 |
move.d 0x77445622,r4 |
sub.b r4,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 85649200 |
|
quit |
/x10-v10.ms
0,0 → 1,21
#mach: crisv10 |
#ld: --section-start=.text=0 |
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n |
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 3\n |
#output: 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#sim: --cris-trace=basic |
|
; Check that "add.d x,pc" gets 3 cycles. |
|
.include "testutils.inc" |
startnostack |
nop |
nop |
add.d 1f-0f,$pc |
0: |
nop |
1: |
nop |
break 15 |
/addcpc.ms
0,0 → 1,35
# mach: crisv3 crisv8 crisv10 |
# output: 2f\n31\n |
|
# Test that the special case add.d const,pc works. |
|
.include "testutils.inc" |
start |
x: |
add.d y-y0,pc |
y0: |
quit |
|
.space 1000 |
quit |
quit |
quit |
quit |
quit |
z: |
move.d 49,r3 |
dumpr3 |
quit |
|
.space 1000 |
quit |
quit |
quit |
quit |
quit |
y: |
move.d 47,r3 |
dumpr3 |
add.d z-z0,pc |
z0: |
quit |
/nonvcv32.ms
0,0 → 1,167
# mach: crisv32 |
|
.include "testutils.inc" |
|
; Check for various non-arithmetic insns that C and V are not affected |
; on v32 (where they were on v10), as the generic tests don't cover |
; that; they are cleared before testing. |
|
; First, a macro testing that VC are unaffected, not counting previous |
; register contents. |
.macro nonvc0 insn op |
move.d $r0,$r3 |
setf vc |
.ifnc \insn,swapnwbr |
\insn \op,$r3 |
.else |
\insn $r3 |
.endif |
bcc 9f |
nop |
bvc 9f |
nop |
move.d $r0,$r3 |
clearf vc |
.ifnc \insn,swapnwbr |
\insn \op,$r3 |
.else |
\insn $r3 |
.endif |
bcs 9f |
nop |
bvc 8f |
nop |
9: |
fail |
8: |
.endm |
|
; Use the above, but initialize the non-parameter operand to a value. |
.macro nonvc1 insn val op |
move.d \val,$r0 |
nonvc0 \insn,\op |
.endm |
|
; Use the above, iterating over various values. |
.macro nonvc2 insn op |
.irp p,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000 |
nonvc1 \insn,\p,\op |
nonvc1 \insn,-\p,\op |
.endr |
.endm |
|
.macro nonvc2q insn op min=-63 max=63 |
.if \op >= \min &&&& \op <= \max |
nonvc2 \insn,\op |
.endif |
.endm |
|
; The above, for each .b .w .d insn variant. |
.macro nonvcbwd insn op |
.irp s,.b,.w,.d |
nonvc2 \insn\s,\op |
.endr |
.endm |
|
; For various insns with register, dword constant and memory operands. |
.macro nonvcitermcd op=[$r4] |
nonvc2 and.d,\op |
nonvc2 move.d,\op |
nonvc2 or.d,\op |
.endm |
|
; Similar, for various insns with register, word constant and memory operands. |
.macro nonvcitermcw op=[$r4] |
nonvcitermcd \op |
nonvc2 and.w,\op |
nonvc2 move.w,\op |
nonvc2 or.w,\op |
nonvc2 movs.w,\op |
nonvc2 movu.w,\op |
.endm |
|
; Similar, for various insns with register, byte constant and memory operands. |
.macro nonvcitermcb op=[$r4] |
nonvcitermcw \op |
nonvc2 and.b,\op |
nonvc2 move.b,\op |
nonvc2 or.b,\op |
nonvc2 movs.b,\op |
nonvc2 movu.b,\op |
.endm |
|
; Similar, for insns with quick constant operands. |
.macro nonvciterq op |
nonvcitermcb \op |
nonvc2 bound.b,\op |
nonvc2q andq,\op,min=-32,max=31 |
nonvc2q asrq,\op,min=0,max=31 |
nonvc2q lsrq,\op,min=0,max=31 |
nonvc2q orq,\op,min=-32,max=31 |
nonvc2q moveq,\op,min=-32,max=31 |
.endm |
|
; Similar, for insns with register operands. |
.macro nonvciterr op |
nonvcitermcb \op |
nonvcbwd bound,\op |
nonvc2 abs,\op |
nonvcbwd asr,\op |
nonvc2 dstep,\op |
nonvcbwd lsr,\op |
nonvcbwd lsl,\op |
nonvc2 lz,\op |
nonvc2 swapnwbr |
nonvc2 xor,\op |
.endm |
|
; Test all applicable constant, register and memory variants of a value. |
.macro tst op |
; Constants |
.if (\op <= 31 &&&& \op >= -32) |
nonvciterq \op |
.elseif (\op <= 255 &&&& \op >= -128) |
nonvcitermcb \op |
nonvcbwd bound,\op |
.elseif (\op <= 65535 &&&& \op >= -32767) |
nonvcitermcw \op |
nonvc2 bound.w,\op |
nonvc2 bound.d,\op |
.else |
nonvcitermcd \op |
nonvc2 bound.d,\op |
.endif |
; Registers |
move.d \op,$r4 |
nonvciterr $r4 |
; Memory |
nonvcitermcb [$r5] |
addq 4,$r5 |
.section .rodata |
.dword \op |
.previous |
.endm |
|
; As above but negation too. |
.macro tstpm op |
tst \op |
tst -\op |
.endm |
|
|
; Set up for the actual test. |
|
start |
move.d c0,$r5 |
|
.section .rodata |
c0: |
.previous |
|
; Finally, test. |
|
.irp x,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000 |
tstpm \x |
.endr |
|
pass |
/test.ms
0,0 → 1,80
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 1\n |
|
.include "testutils.inc" |
.data |
x: |
.dword 0,2,-1,0x80000000,0x5432f789 |
.word 0,2,-1,0xffff,0xf789 |
.byte 0,2,0xff,0x89 |
|
start |
clearf nzvc |
moveq -1,r3 |
move.d x,r5 |
setf vc |
test.d [r5+] |
test_cc 0 1 0 0 |
|
setf vc |
test.d [r5] |
test_cc 0 0 0 0 |
|
addq 4,r5 |
|
setf vc |
test.d [r5+] |
test_cc 1 0 0 0 |
|
setf vc |
test.d [r5+] |
test_cc 1 0 0 0 |
|
setf vc |
test.d [r5+] |
test_cc 0 0 0 0 |
|
setf vc |
test.w [r5+] |
test_cc 0 1 0 0 |
|
setf vc |
test.w [r5] |
test_cc 0 0 0 0 |
|
addq 2,r5 |
|
setf vc |
test.w [r5+] |
test_cc 1 0 0 0 |
|
setf vc |
test.w [r5+] |
test_cc 1 0 0 0 |
|
setf vc |
test.w [r5+] |
test_cc 1 0 0 0 |
|
setf vc |
test.b [r5] |
test_cc 0 1 0 0 |
|
addq 1,r5 |
|
setf vc |
test.b [r5+] |
test_cc 0 0 0 0 |
|
setf vc |
test.b [r5+] |
test_cc 1 0 0 0 |
|
setf vc |
test.b [r5] |
test_cc 1 0 0 0 |
|
moveq 1,r3 |
dumpr3 |
|
quit |
/mcp.ms
0,0 → 1,49
# mach: crisv32 |
# output: fffffffe\n1\n1ffff\nfffffffe\ncc463bdc\n4c463bdc\n0\n |
|
.include "testutils.inc" |
start |
|
; Set R, clear C. |
move 0x100,ccs |
moveq -5,r3 |
move 2,mof |
mcp mof,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fffffffe |
|
moveq 2,r3 |
move -1,srp |
mcp srp,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
|
move 0xffff,srp |
move srp,r3 |
mcp srp,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1ffff |
|
move -1,mof |
move mof,r3 |
mcp mof,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fffffffe |
|
move 0x5432f789,mof |
move.d 0x78134452,r3 |
mcp mof,r3 |
test_cc 1 0 1 0 |
dumpr3 ; cc463bdc |
|
move 0x80000000,srp |
mcp srp,r3 |
test_cc 0 0 1 0 |
dumpr3 ; 4c463bdc |
|
move 0xb3b9c423,srp |
mcp srp,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 0 |
|
quit |
/dstep.ms
0,0 → 1,42
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: fffffffc\n4\nffff\nfffffffe\n9bf3911b\n0\n |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
moveq 2,r4 |
dstep r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fffffffc |
|
moveq 2,r3 |
moveq -1,r4 |
dstep r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 4 |
|
move.d 0xffff,r4 |
move.d r4,r3 |
dstep r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
moveq -1,r4 |
move.d r4,r3 |
dstep r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fffffffe |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
dstep r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; 9bf3911b |
|
move.d 0xffff,r3 |
move.d 0x1fffe,r4 |
dstep r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
|
quit |
/movecrt10.ms
0,0 → 1,17
#mach: crisv10 |
#output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n |
#output: Basic clock cycles, total @: 82\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
.include "movecr.ms" |
|
# This test-case is accidentally the same; gets the same cycle |
# count as movecrt32.ms, but please keep them separate. |
/subxc.ms
0,0 → 1,92
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 3\n3\nffffff03\nffff0003\nff00\n0\n10000\n10000\n0\nffffff00\n0\n781343c9\n781344c9\n78124cc9\n78134cc9\nc450\n7ffff8ce\n |
|
.include "testutils.inc" |
start |
moveq 2,r3 |
subs.b 0xff,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 3 |
|
moveq 2,r3 |
subs.w 0xffff,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 3 |
|
moveq 2,r3 |
subu.b 0xff,r3 |
test_cc 1 0 0 1 |
dumpr3 ; ffffff03 |
|
moveq 2,r3 |
move.d 0xffffffff,r4 |
subu.w -1,r3 |
test_cc 1 0 0 1 |
dumpr3 ; ffff0003 |
|
move.d 0xffff,r3 |
subu.b -1,r3 |
test_cc 0 0 0 0 |
dumpr3 ; ff00 |
|
move.d 0xffff,r3 |
subu.w -1,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0xffff,r3 |
subs.b 0xff,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 10000 |
|
move.d 0xffff,r3 |
subs.w 0xffff,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 10000 |
|
moveq -1,r3 |
subs.b 0xff,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 0 |
|
moveq -1,r3 |
subs.w 0xff,r3 |
test_cc 1 0 0 0 |
dumpr3 ; ffffff00 |
|
moveq -1,r3 |
subs.w 0xffff,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0x78134452,r3 |
subu.b 0x89,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 781343c9 |
|
move.d 0x78134452,r3 |
subs.b 0x89,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 781344c9 |
|
move.d 0x78134452,r3 |
subu.w 0xf789,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 78124cc9 |
|
move.d 0x78134452,r3 |
subs.w 0xf789,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 78134cc9 |
|
move.d 0x4452,r3 |
subs.w 0x8002,r3 |
test_cc 0 0 0 1 |
dumpr3 ; c450 |
|
move.d 0x80000032,r3 |
subu.w 0x764,r3 |
test_cc 0 0 1 0 |
dumpr3 ; 7ffff8ce |
|
quit |
/andr.ms
0,0 → 1,95
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 2\n2\nffff\nffffffff\n50124400\nffff0002\n2\nfffff\nfedaff0f\n78134400\nffffff02\n2\nf02\n78134401\n78134400\n |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
moveq 2,r4 |
and.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
moveq 2,r3 |
moveq -1,r4 |
and.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xffff,r4 |
move.d r4,r3 |
and.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
moveq -1,r4 |
move.d r4,r3 |
and.d r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
and.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 50124400 |
|
moveq -1,r3 |
moveq 2,r4 |
and.w r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff0002 |
|
moveq 2,r3 |
moveq -1,r4 |
and.w r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xfffff,r3 |
move.d 0xffff,r4 |
and.w r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fffff |
|
move.d 0xfedaffaf,r3 |
move.d 0xff5f,r4 |
and.w r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fedaff0f |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
and.w r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 78134400 |
|
moveq -1,r3 |
moveq 2,r4 |
and.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffffff02 |
|
moveq 2,r3 |
moveq -1,r4 |
and.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0x5a,r4 |
move.d 0xfa7,r3 |
and.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; f02 |
|
move.d 0x5432f789,r4 |
move.d 0x78134453,r3 |
and.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 78134401 |
|
moveq 0,r7 |
and.b r7,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 78134400 |
|
quit |
/ftagd.ms
0,0 → 1,9
# mach: crisv32 |
# xerror: |
# output: FTAGD isn't implemented\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
ftagd [r11] |
|
quit |
/movumpc.ms
0,0 → 1,8
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
move.d _start,r1 |
movu.b [r1+],pc |
/io2.ms
0,0 → 1,18
# mach: crisv32 |
# sim: --cris-900000xx |
# xerror: |
# output: b1e\n |
|
; Check correct "fail" exit. |
|
.include "testutils.inc" |
start |
move.d 0xb1e,$r3 |
dumpr3 |
move.d 0x90000008,$acr |
move.d $acr,[$acr] |
move.d 0xbadc0de,$r3 |
dumpr3 |
0: |
ba 0b |
nop |
/boundr.ms
0,0 → 1,125
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 2\n2\nffff\nffffffff\n5432f789\n2\n2\nffff\nffff\nffff\nf789\n2\n2\nff\nff\n89\nfeda4953\nfeda4962\n0\n0\n |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
moveq 2,r4 |
bound.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
moveq 2,r3 |
moveq -1,r4 |
bound.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xffff,r4 |
move.d r4,r3 |
bound.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
moveq -1,r4 |
move.d r4,r3 |
bound.d r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
bound.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 5432f789 |
|
moveq -1,r3 |
moveq 2,r4 |
bound.w r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
moveq 2,r3 |
moveq -1,r4 |
bound.w r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
moveq -1,r3 |
bound.w r3,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
move.d 0xffff,r4 |
move.d r4,r3 |
bound.w r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
move.d 0xfedaffff,r4 |
move.d r4,r3 |
bound.w r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
bound.w r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; f789 |
|
moveq -1,r3 |
moveq 2,r4 |
bound.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
moveq 2,r3 |
moveq -1,r4 |
bound.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xff,r4 |
move.d r4,r3 |
bound.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ff |
|
move.d 0xfeda49ff,r4 |
move.d r4,r3 |
bound.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ff |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
bound.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 89 |
|
move.d 0xfeda4956,r3 |
move.d 0xfeda4953,r4 |
bound.d r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; feda4953 |
|
move.d 0xfeda4962,r3 |
move.d 0xfeda4963,r4 |
bound.d r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; feda4962 |
|
move.d 0xfeda4956,r3 |
move.d 0,r4 |
bound.d r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0xfeda4956,r4 |
move.d 0,r3 |
bound.d r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
|
quit |
/movpmv32.ms
0,0 → 1,35
# mach: crisv32 |
# output: 11223320\nbb113344\naa557711\n |
|
# Test v32-specific special registers. FIXME: more registers. |
|
.include "testutils.inc" |
start |
.data |
store: |
.dword 0x11223344 |
.dword 0x77665544 |
|
.text |
moveq -1,r3 |
move.d store,r4 |
move vr,[r4] |
move [r4+],mof |
move mof,r3 |
dumpr3 |
|
moveq -1,r3 |
clearf zcvn |
move 0xbb113344,mof |
test_cc 0 0 0 0 |
move mof,r3 |
dumpr3 |
|
setf zcvn |
move 0xaa557711,mof |
test_cc 1 1 1 1 |
move mof,[r4] |
move.d [r4],r3 |
dumpr3 |
|
quit |
/movprv10.ms
0,0 → 1,21
# mach: crisv10 |
# output: ffffff0a\nbb113344\n |
|
# Test v10-specific special registers. FIXME: ccr, irp, bar, brp, usp. |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
setf zcvn |
move vr,r3 |
test_cc 1 1 1 1 |
dumpr3 |
|
moveq -1,r3 |
move.d 0xbb113344,r4 |
clearf zcvn |
move r4,mof |
move mof,r3 |
test_cc 0 0 0 0 |
dumpr3 |
quit |
/addc.ms
0,0 → 1,81
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
add.d 2,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1 |
|
moveq 2,r3 |
add.d -1,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1 |
|
move.d 0xffff,r3 |
add.d 0xffff,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1fffe |
|
moveq -1,r3 |
add.d -1,r3 |
test_cc 1 0 0 1 |
dumpr3 ; fffffffe |
|
move.d 0x78134452,r3 |
add.d 0x5432f789,r3 |
test_cc 1 0 1 0 |
dumpr3 ; cc463bdb |
|
moveq -1,r3 |
add.w 2,r3 |
test_cc 0 0 0 1 |
dumpr3 ; ffff0001 |
|
moveq 2,r3 |
add.w -1,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1 |
|
move.d 0xffff,r3 |
add.w 0xffff,r3 |
test_cc 1 0 0 1 |
dumpr3 ; fffe |
|
move.d 0xfedaffff,r3 |
add.w 0xffff,r3 |
test_cc 1 0 0 1 |
dumpr3 ; fedafffe |
|
move.d 0x78134452,r3 |
add.w 0xf789,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 78133bdb |
|
moveq -1,r3 |
add.b 2,r3 |
test_cc 0 0 0 1 |
dumpr3 ; ffffff01 |
|
moveq 2,r3 |
add.b -1,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1 |
|
move.d 0xff,r3 |
add.b 0xff,r3 |
test_cc 1 0 0 1 |
dumpr3 ; fe |
|
move.d 0xfeda49ff,r3 |
add.b 0xff,r3 |
test_cc 1 0 0 1 |
dumpr3 ; feda49fe |
|
move.d 0x78134452,r3 |
add.b 0x89,r3 |
test_cc 1 0 0 0 |
dumpr3 ; 781344db |
|
quit |
/cmpm.ms
0,0 → 1,96
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: ffffffff\n2\nffff\nffffffff\n78134452\nffffffff\n2\nffff\nfedaffff\n78134452\nffffffff\n2\nff\nfeda49ff\n78134452\n85649222\n |
|
.include "testutils.inc" |
.data |
x: |
.dword -2,1,-0xffff,1,-0x5432f789 |
.word -2,1,1,0x877 |
.byte -2,1,0x77 |
.byte 0x22 |
|
start |
moveq -1,r3 |
move.d x,r5 |
cmp.d [r5+],r3 |
test_cc 0 0 0 0 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
cmp.d [r5],r3 |
test_cc 0 0 0 0 |
addq 4,r5 |
dumpr3 ; 2 |
|
move.d 0xffff,r3 |
cmp.d [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; ffff |
|
moveq -1,r3 |
cmp.d [r5+],r3 |
test_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d 0x78134452,r3 |
cmp.d [r5+],r3 |
test_cc 1 0 1 1 |
dumpr3 ; 78134452 |
|
moveq -1,r3 |
cmp.w [r5+],r3 |
test_cc 0 0 0 0 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
cmp.w [r5+],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xffff,r3 |
cmp.w [r5],r3 |
test_cc 1 0 0 0 |
dumpr3 ; ffff |
|
move.d 0xfedaffff,r3 |
cmp.w [r5+],r3 |
test_cc 1 0 0 0 |
dumpr3 ; fedaffff |
|
move.d 0x78134452,r3 |
cmp.w [r5+],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 78134452 |
|
moveq -1,r3 |
cmp.b [r5],r3 |
test_cc 0 0 0 0 |
addq 1,r5 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
cmp.b [r5],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xff,r3 |
cmp.b [r5],r3 |
test_cc 1 0 0 0 |
dumpr3 ; ff |
|
move.d 0xfeda49ff,r3 |
cmp.b [r5+],r3 |
test_cc 1 0 0 0 |
dumpr3 ; feda49ff |
|
move.d 0x78134452,r3 |
cmp.b [r5+],r3 |
test_cc 1 0 0 1 |
dumpr3 ; 78134452 |
|
move.d 0x85649222,r3 |
cmp.b [r5],r3 |
test_cc 0 1 0 0 |
dumpr3 ; 85649222 |
|
quit |
/movemrv10.ms
0,0 → 1,101
# mach: crisv0 crisv3 crisv8 crisv10 |
# output: 15\nffff1234\n2\n7\nb\n16\nf\n2\nf\nffffffef\n7\nfffffff4\nf\nfffffff2\nd\n10\nfffffff2\n8\nfffffff4\n |
|
.include "testutils.inc" |
.data |
x: |
.dword 8,9,10,11 |
y: |
.dword -12,13,-14,15,16 |
|
start |
moveq 7,r0 |
moveq 2,r1 |
move.d 0xffff1234,r2 |
moveq 21,r3 |
move.d x,r4 |
setf zcvn |
movem r2,[r4+] |
test_cc 1 1 1 1 |
subq 12,r4 |
|
dumpr3 ; 15 |
|
move.d [r4+],r3 |
dumpr3 ; ffff1234 |
|
move.d [r4+],r3 |
dumpr3 ; 2 |
|
move.d [r4+],r3 |
dumpr3 ; 7 |
|
move.d [r4+],r3 |
dumpr3 ; b |
|
subq 16,r4 |
moveq 22,r0 |
moveq 15,r1 |
clearf zcvn |
movem r0,[r4] |
test_cc 0 0 0 0 |
move.d [r4+],r3 |
dumpr3 ; 16 |
|
move.d r1,r3 |
dumpr3 ; f |
|
move.d [r4+],r3 |
dumpr3 ; 2 |
|
moveq 10,r2 |
moveq -17,r0 |
clearf zc |
setf vn |
movem r1,[r4=r4-8] |
test_cc 1 0 1 0 |
move.d [r4+],r3 |
dumpr3 ; f |
|
move.d [r4+],r3 |
dumpr3 ; ffffffef |
|
move.d [r4+],r3 |
dumpr3 ; 7 |
|
move.d y,r4 |
setf zc |
clearf vn |
movem [r4+],r3 |
test_cc 0 1 0 1 |
dumpr3 ; fffffff4 |
|
move.d r0,r3 |
dumpr3 ; f |
|
move.d r1,r3 |
dumpr3 ; fffffff2 |
|
moveq -12,r1 |
|
move.d r2,r3 |
dumpr3 ; d |
|
move.d [r4],r3 |
dumpr3 ; 10 |
|
setf zcvn |
movem [r5=r4-8],r0 |
test_cc 1 1 1 1 |
move.d r0,r3 |
dumpr3 ; fffffff2 |
|
sub.d r5,r4 |
move.d r4,r3 |
dumpr3 ; 8 |
|
move.d r1,r3 |
dumpr3 ; fffffff4 |
|
quit |
|
/opterr2.ms
0,0 → 1,5
# mach: crisv3 crisv8 crisv10 crisv32 |
# xerror: |
# output: *: unrecognized option `--cris-xyz'\n |
# sim: --cris-xyz |
.include "nopv32t.ms" |
/raw15.ms
0,0 → 1,14
; Checking read-after-write: cycles included in "all". |
#mach: crisv32 |
#output: All accounted clock cycles, total @: 6\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 2\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=all |
.include "raw4.ms" |
/dflags.ms
0,0 → 1,62
# mach: crisv3 crisv8 crisv10 crisv32 |
# output: 31\n |
|
; Check that flag settings in the delay slot for a conditional branch do |
; not affect the branch. |
|
.include "testutils.inc" |
|
start |
moveq 1,r3 |
moveq 0,r4 |
|
; 8-bit branches. |
|
move.d r4,r4 |
bne 0f |
move.d r3,r3 |
bne 1f |
move.d r4,r4 |
nop |
0: |
quit |
|
1: |
move.d r3,r3 |
beq 0b |
move.d r4,r4 |
beq 4f |
move.d r3,r3 |
nop |
quit |
4: |
jump 2f |
nop |
.space 1000 |
|
; 16-bit branches |
|
2: |
move.d r4,r4 |
bne 0b |
move.d r3,r3 |
bne 3f |
move.d r4,r4 |
nop |
quit |
.space 1000 |
|
3: |
move.d r3,r3 |
beq 0b |
move.d r4,r4 |
beq 4f |
move.d r3,r3 |
nop |
quit |
.space 1000 |
|
4: |
move.d 0x31,r3 |
dumpr3 |
quit |
/movsm.ms
0,0 → 1,44
# mach: crisv3 crisv8 crisv10 crisv32 |
# output: 5\nfffffff5\n5\nfffffff5\n0\n |
|
; Movs between registers. Check that sign-extension is performed and the |
; full register is set. |
|
.include "testutils.inc" |
|
.data |
x: |
.byte 5,-11 |
.word 5,-11 |
.word 0 |
|
start |
move.d x,r5 |
|
moveq -1,r3 |
movs.b [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
moveq 0,r3 |
movs.b [r5],r3 |
test_move_cc 1 0 0 0 |
addq 1,r5 |
dumpr3 |
|
moveq -1,r3 |
movs.w [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
moveq 0,r3 |
movs.w [r5],r3 |
test_move_cc 1 0 0 0 |
addq 2,r5 |
dumpr3 |
|
movs.w [r5],r3 |
test_move_cc 0 1 0 0 |
dumpr3 |
|
quit |
/x6-v10.ms
0,0 → 1,11
#mach: crisv10 |
#ld: --section-start=.text=0 |
#sim: --cris-trace=basic |
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n |
#output: 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 6 0 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 8 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: a 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n |
#output: c 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n |
#output: e 1 2 0 2 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n |
.include "tmulv10.ms" |
/moverwpc.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
startnostack |
setf |
move.d r5,pc |
quit |
/movum.ms
0,0 → 1,40
# mach: crisv3 crisv8 crisv10 crisv32 |
# output: 5\nf5\n5\nfff5\n0\n |
|
; Movu between registers. Check that zero-extension is performed and the |
; full register is set. |
|
.include "testutils.inc" |
|
.data |
x: |
.byte 5,-11 |
.word 5,-11 |
.word 0 |
|
start |
move.d x,r5 |
|
movu.b [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
movu.b [r5],r3 |
test_move_cc 0 0 0 0 |
addq 1,r5 |
dumpr3 |
|
movu.w [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
movu.w [r5],r3 |
test_move_cc 0 0 0 0 |
addq 2,r5 |
dumpr3 |
|
movu.w [r5],r3 |
test_move_cc 0 1 0 0 |
dumpr3 |
|
quit |
/fidxi.ms
0,0 → 1,9
# mach: crisv32 |
# xerror: |
# output: FIDXI isn't implemented\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
fidxi [r5] |
|
quit |
/x4-v32.ms
0,0 → 1,23
#mach: crisv32 |
#ld: --section-start=.text=0 |
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n |
#output: 8 0 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: e 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 10 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 12 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 14 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 16 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 18 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 1a 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 1e 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 24 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 26 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 28 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 2a 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 2e 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 34 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 36 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 38 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#sim: --cris-trace=basic |
|
.include "tjmpsrv32.ms" |
/abs.ms
0,0 → 1,50
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 1\n0\n80000000\n7fffffff\n2a\n1\nffff\n1f\n0\n |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
|
abs r3,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1 |
|
moveq 0,r3 |
dumpr3 ; 0 |
|
move.d 0x80000000,r4 |
abs r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; 80000000 |
|
move.d 0x7fffffff,r4 |
abs r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 7fffffff |
|
move.d 42,r3 |
abs r3,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2a |
|
moveq 1,r6 |
abs r6,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1 |
|
move.d 0xffff,r3 |
abs r3,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
moveq -31,r5 |
abs r5,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1f |
|
moveq 0,r5 |
abs r5,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
|
quit |
/subm.ms
0,0 → 1,96
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n85649200\n |
|
.include "testutils.inc" |
.data |
x: |
.dword -2,1,-0xffff,1,-0x5432f789 |
.word -2,1,1,0x877 |
.byte -2,1,0x77 |
.byte 0x22 |
|
start |
moveq -1,r3 |
move.d x,r5 |
sub.d [r5+],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
|
moveq 2,r3 |
sub.d [r5],r3 |
test_cc 0 0 0 0 |
addq 4,r5 |
dumpr3 ; 1 |
|
move.d 0xffff,r3 |
sub.d [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1fffe |
|
moveq -1,r3 |
sub.d [r5+],r3 |
test_cc 1 0 0 0 |
dumpr3 ; fffffffe |
|
move.d 0x78134452,r3 |
sub.d [r5+],r3 |
test_cc 1 0 1 1 |
dumpr3 ; cc463bdb |
|
moveq -1,r3 |
sub.w [r5+],r3 |
test_cc 0 0 0 0 |
dumpr3 ; ffff0001 |
|
moveq 2,r3 |
sub.w [r5+],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
|
move.d 0xffff,r3 |
sub.w [r5],r3 |
test_cc 1 0 0 0 |
dumpr3 ; fffe |
|
move.d 0xfedaffff,r3 |
sub.w [r5+],r3 |
test_cc 1 0 0 0 |
dumpr3 ; fedafffe |
|
move.d 0x78134452,r3 |
sub.w [r5+],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 78133bdb |
|
moveq -1,r3 |
sub.b [r5],r3 |
test_cc 0 0 0 0 |
addq 1,r5 |
dumpr3 ; ffffff01 |
|
moveq 2,r3 |
sub.b [r5],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
|
move.d 0xff,r3 |
sub.b [r5],r3 |
test_cc 1 0 0 0 |
dumpr3 ; fe |
|
move.d 0xfeda49ff,r3 |
sub.b [r5+],r3 |
test_cc 1 0 0 0 |
dumpr3 ; feda49fe |
|
move.d 0x78134452,r3 |
sub.b [r5+],r3 |
test_cc 1 0 0 1 |
dumpr3 ; 781344db |
|
move.d 0x85649222,r3 |
sub.b [r5],r3 |
test_cc 0 1 0 0 |
dumpr3 ; 85649200 |
|
quit |
/nopv10t.ms
0,0 → 1,13
#mach: crisv0 crisv3 crisv8 crisv10 |
#output: Basic clock cycles, total @: 5\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
.include "nopv32t.ms" |
/addoc.ms
0,0 → 1,44
# mach: crisv32 |
# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n |
|
.include "testutils.inc" |
.data |
x: |
.dword 0x55aa77ff |
.dword 0xccff2244 |
.dword 0x88ccee19 |
|
start |
moveq -1,r0 |
move.d x-32768,r5 |
addo.d 32769,r5,acr |
move.d [acr],r3 |
dumpr3 ; 4455aa77 |
|
addu.w 32770,r5 |
addo.w -1,r5,acr |
move.d [acr],r3 |
dumpr3 ; 4455aa77 |
|
addo.d 5,acr,acr |
move.d [acr],r3 |
dumpr3 ; ee19ccff |
|
addo.b 3,r5,acr |
movu.w [acr],r3 |
dumpr3 ; ff22 |
|
addo.b -4,acr,acr |
move.d [acr],r3 |
dumpr3 ; 4455aa77 |
|
addo.w 2,acr,acr |
move.d [acr],r3 |
dumpr3 ; ff224455 |
|
addo.d -76789887,r5,acr |
add.d 76789885,acr |
move.d [acr],r3 |
dumpr3 ; 55aa77ff |
|
quit |
/sfe.ms
0,0 → 1,51
# mach: crisv32 |
# output: 4000c800\nc3221800\nc8606400\n48606400\n419d8260\n |
|
; Check that SFE affects CCS the right way. |
|
.include "testutils.inc" |
start |
|
; Set SPC to 1 to disable single step exceptions when S flag is set. |
move 1,spc |
|
; CCS: |
; 31 24 23 16 15 8 7 0 |
; +---+-----------+-------+-------+-----------+---+---------------+ |
; |Q M|S R P U I X N Z V C|S R P U I X N Z V C|S R P U I X N Z V C| |
; | |2 2 2 2 2 2 2 2 2 2|1 1 1 1 1 1 1 1 1 1| | |
; +---+-----------+-------+-------+-----------+---+---------------+ |
|
move 0x40000000,ccs |
setf ixv |
sfe |
move ccs,r3 |
dumpr3 ; 0x4000c800 |
or.d 0x80000000,r3 |
move r3,ccs |
|
setf pzv |
sfe |
move ccs,r3 |
dumpr3 ; 0xc3221800 |
|
setf xnc |
sfe |
move ccs,r3 |
dumpr3 ; 0xc8606400 |
|
; Clear Q, so we don't get S and Q at the same time when we set S. |
lslq 1,r3 |
lsrq 1,r3 |
move r3,ccs |
move ccs,r3 |
dumpr3 ; 0x48606400 |
|
or.w 0x300,r3 |
move r3,ccs |
setf ui |
sfe |
move ccs,r3 |
dumpr3 ; 0x419d8260 |
|
quit |
/raw5.ms
0,0 → 1,23
; Checking read-after-write: write-then-nop-read 2 cycles. |
#mach: crisv32 |
#output: Basic clock cycles, total @: 5\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 2\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
.include "testutils.inc" |
startnostack |
.lcomm x,4 |
.lcomm y,4 |
move.d x,$r0 |
move.d y,$r1 |
move.d $r1,[$r0] |
nop |
move.d [$r1],$r2 |
break 15 |
/moverdpc.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
startnostack |
setf |
move.d r5,pc |
quit |
/andm.ms
0,0 → 1,90
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 2\n2\nffff\nffffffff\n50124400\nffff0002\n2\nfffff\nfedaff0f\n78134400\nffffff02\n2\nf02\n78134401\n78134400\n |
|
.include "testutils.inc" |
.data |
x: |
.dword 2,-1,0xffff,-1,0x5432f789 |
.word 2,-1,0xffff,0xff5f,0xf789 |
.byte 2,-1,0x5a,0x89,0 |
|
start |
moveq -1,r3 |
move.d x,r5 |
and.d [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
moveq 2,r3 |
and.d [r5],r3 |
test_move_cc 0 0 0 0 |
addq 4,r5 |
dumpr3 ; 2 |
|
move.d 0xffff,r3 |
and.d [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
moveq -1,r3 |
and.d [r5+],r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d 0x78134452,r3 |
and.d [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 50124400 |
|
moveq -1,r3 |
and.w [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff0002 |
|
moveq 2,r3 |
and.w [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xfffff,r3 |
and.w [r5],r3 |
test_move_cc 1 0 0 0 |
addq 2,r5 |
dumpr3 ; fffff |
|
move.d 0xfedaffaf,r3 |
and.w [r5+],r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fedaff0f |
|
move.d 0x78134452,r3 |
and.w [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 78134400 |
|
moveq -1,r3 |
and.b [r5],r3 |
test_move_cc 0 0 0 0 |
addq 1,r5 |
dumpr3 ; ffffff02 |
|
moveq 2,r3 |
and.b [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xfa7,r3 |
and.b [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; f02 |
|
move.d 0x78134453,r3 |
and.b [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 78134401 |
|
and.b [r5],r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 78134400 |
|
quit |
/ccs-v32.ms
0,0 → 1,73
# mach: crisv32 |
# output: bf\n0\n80\n20\n10\n8\n4\n2\n1\n40\nfade040\n3ade0040\nfade040\n42\n |
|
; Check flag settings. |
|
.include "testutils.inc" |
start |
clear.d r3 |
setf pixnzvc ; Setting U(ser mode) would restrict tests of other flags. |
move ccs,r3 |
dumpr3 |
|
clear.d r3 |
clearf puixnzvc |
move ccs,r3 |
dumpr3 |
|
.macro testf BIT |
clear.d r3 |
clearf puixnzvc |
setf \BIT |
move ccs,r3 |
dumpr3 |
.endm |
|
testf p |
testf i |
testf x |
testf n |
testf z |
testf v |
testf c |
testf u ; Can't test i-flag or clear u after this point. |
|
.macro test_get_cc N Z V C |
clearf znvc |
move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),ccs |
test_cc \N \Z \V \C |
setf znvc |
move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),ccs |
test_cc \N \Z \V \C |
move.d ((\N << 3)|(\Z << 2)|(\V << 1)|\C),r4 |
setf znvc |
move r4,ccs |
test_cc \N \Z \V \C |
clearf znvc |
move r4,ccs |
test_cc \N \Z \V \C |
.endm |
|
test_get_cc 1 0 0 0 |
test_get_cc 0 1 0 0 |
test_get_cc 0 0 1 0 |
test_get_cc 0 0 0 1 |
|
; Test that the U bit sticks. |
move 0x0fade000,ccs |
move ccs,r3 |
dumpr3 |
|
; Check that the M and Q bits can't be set in user mode. |
move 0xfade0000,ccs |
move ccs,r3 |
dumpr3 |
|
move 0x0fade000,ccs |
move ccs,r3 |
dumpr3 |
|
move.d 0x42,r3 |
dumpr3 |
|
quit |
/boundm.ms
0,0 → 1,105
# mach: crisv0 crisv3 crisv8 crisv10 |
# output: 2\n2\nffff\nffffffff\n5432f789\n2\nffff\n2\nffff\nffff\nf789\n2\n2\nff\nff\nff\n89\n0\n |
|
.include "testutils.inc" |
.data |
x: |
.dword 2,-1,0xffff,-1,0x5432f789 |
.word 2,0xffff,0xf789 |
.byte 2,0xff,0x89,0 |
|
start |
move.d x,r5 |
|
moveq -1,r3 |
moveq 2,r4 |
bound.d [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
moveq 2,r3 |
bound.d [r5],r3 |
test_move_cc 0 0 0 0 |
addq 4,r5 |
dumpr3 ; 2 |
|
move.d 0xffff,r3 |
bound.d [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
moveq -1,r3 |
bound.d [r5+],r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d 0x78134452,r3 |
bound.d [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 5432f789 |
|
moveq -1,r3 |
bound.w [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
moveq -1,r3 |
bound.w [r5],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
moveq 2,r3 |
bound.w [r5],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xffff,r3 |
bound.w [r5],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
move.d 0xfedaffff,r3 |
bound.w [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
move.d 0x78134452,r3 |
bound.w [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; f789 |
|
moveq -1,r3 |
bound.b [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
moveq 2,r3 |
bound.b [r5],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
moveq -1,r3 |
bound.b [r5],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ff |
|
move.d 0xff,r3 |
bound.b [r5],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ff |
|
move.d 0xfeda49ff,r3 |
bound.b [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ff |
|
move.d 0x78134452,r3 |
bound.b [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 89 |
|
bound.b [r5],r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
|
quit |
/break.ms
0,0 → 1,15
# mach: crisv3 crisv8 crisv10 crisv32 |
# sim: --trace-core=on |
# ld: --section-start=.text=0 |
# output: read-2 exec:0x00000002 -> 0x05b0\nread-2 exec:0x00000004 -> 0xe93f\n |
|
; First test: Must exit gracefully. |
|
.include "testutils.inc" |
|
; This first insn isn't executed (it's a filler); it would fail |
; ungracefully if executed. |
|
startnostack |
setf |
quit |
/movesmp.ms
0,0 → 1,28
# mach: crisv3 crisv8 crisv10 |
# output: bed0bed1\nabedab0d\nbed0bed1\n |
|
# Test that move to and from special register and memory clears the |
# "prefixed" bit. |
|
.include "testutils.inc" |
.data |
w: |
.dword 0 |
y: |
.dword 0xbed0bed1 |
z: |
.dword 0xabedab0d |
|
start |
x: |
move.d y,r3 |
clear.d [w] |
move.d [r3],r3 |
dumpr3 ; bed0bed1 |
move.d z,r3 |
move [w+4],srp |
move.d [r3],r3 |
dumpr3 ; abedab0d |
move srp,r3 |
dumpr3 ; bed0bed1 |
quit |
/option2.ms
0,0 → 1,5
#mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
#sim: --sysroot=/non/exist/dir |
#output: run: can't change directory to "/non/exist/dir"\n |
#xerror: |
.include "option1.ms" |
/raw10.ms
0,0 → 1,22
; Checking read-after-write: swrite-then-read 2 cycles. |
#mach: crisv32 |
#output: Basic clock cycles, total @: 4\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 2\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
.include "testutils.inc" |
startnostack |
.lcomm x,4 |
.lcomm y,4 |
move.d x,$r0 |
move.d y,$r1 |
clear.d [$r0] |
move [$r1],$srp |
break 15 |
/movurpc.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
setf |
movu.b r3,pc |
quit |
/msteppc1.ms
0,0 → 1,8
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register read of PC is not implemented.\n |
# output: program stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
mstep pc,r2 |
/io5.ms
0,0 → 1,17
# mach: crisv32 |
# output: ce11d0c\n |
|
; Check correct "pass" exit. |
|
.include "testutils.inc" |
start |
move.d 0x0ce11d0c,$r3 |
dumpr3 |
moveq 1,$r9 |
moveq 0,$r10 |
break 13 |
move.d 0xbadc0de,$r3 |
dumpr3 |
0: |
ba 0b |
nop |
/movmp.ms
0,0 → 1,127
# mach: crisv3 crisv8 crisv10 crisv32 |
# output: ffffff00\nffff0000\n0\nffffff00\nffff0000\n0\nffffff00\nffff0000\n0\nbb113344\n664433aa\ncc557788\nabcde012\nabcde000\n77880000\n0\n |
|
# Test generic "move Ps,[]" and "move [],Pd" insns; the ones with |
# functionality common to all models. |
|
.include "testutils.inc" |
start |
|
.data |
filler: |
.byte 0xaa |
.word 0x4433 |
.dword 0x55778866 |
.byte 0xcc |
|
.text |
; Test that writing to zero-registers is a nop |
.if 0 |
; We used to just ignore the writes, but now an error is emitted. We |
; keep the test-code but disabled, in case we need to change this again. |
move 0xaa,p0 |
move 0x4433,p4 |
move 0x55774433,p8 |
.endif |
|
moveq -1,r3 |
setf zcvn |
clear.b r3 |
test_cc 1 1 1 1 |
dumpr3 |
|
moveq -1,r3 |
clearf zcvn |
clear.w r3 |
test_cc 0 0 0 0 |
dumpr3 |
|
moveq -1,r3 |
clear.d r3 |
dumpr3 |
|
; "Write" using ordinary memory references too. |
.if 0 ; See ".if 0" above. |
move.d filler,r6 |
move [r6],p0 |
move [r6],p4 |
move [r6],p8 |
.endif |
|
moveq -1,r3 |
clear.b r3 |
dumpr3 |
|
moveq -1,r3 |
clear.w r3 |
dumpr3 |
|
moveq -1,r3 |
clear.d r3 |
dumpr3 |
|
; And postincremented. |
.if 0 ; See ".if 0" above. |
move [r6+],p0 |
move [r6+],p4 |
move [r6+],p8 |
.endif |
|
moveq -1,r3 |
clear.b r3 |
dumpr3 |
|
moveq -1,r3 |
clear.w r3 |
dumpr3 |
|
moveq -1,r3 |
clear.d r3 |
dumpr3 |
|
; Now see that we can write to the registers too. |
|
; [PC+] |
move.d filler,r9 |
move 0xbb113344,srp |
move srp,r3 |
dumpr3 |
|
; [R+] |
move [r9+],srp |
move srp,r3 |
dumpr3 |
|
; [R] |
move [r9],srp |
move srp,r3 |
dumpr3 |
|
; And check writing to memory, clear and srp. |
|
move.d filler,r9 |
move 0xabcde012,srp |
setf zcvn |
move srp,[r9+] |
test_cc 1 1 1 1 |
subq 4,r9 |
move.d [r9],r3 |
dumpr3 |
|
clearf zcvn |
clear.b [r9] |
test_cc 0 0 0 0 |
move.d [r9],r3 |
dumpr3 |
|
addq 2,r9 |
clear.w [r9+] |
subq 2,r9 |
move.d [r9],r3 |
dumpr3 |
|
clear.d [r9] |
move.d [r9],r3 |
dumpr3 |
|
quit |
/fidxd.ms
0,0 → 1,9
# mach: crisv32 |
# xerror: |
# output: FIDXD isn't implemented\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
fidxd [r3] |
|
quit |
/nopv32t3.ms
0,0 → 1,13
#mach: crisv10 crisv32 |
#output: Schedulable clock cycles, total @: 5\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=schedulable |
.include "nopv32t.ms" |
/lsr.ms
0,0 → 1,217
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: ffffffff\n1\n1\n1ffff\n5a67f\n1\n0\n0\n3699fc67\nffffffff\n1\n1\n1ffff\n5a67f\nda670000\nda670000\nda670000\nda673c67\nffffffff\nffff7fff\n1\nffff0000\nffff0001\n5a67000f\nda67f100\nda67f100\nda67f100\nda67f127\nffffffff\nffffff7f\n1\nffffff00\nffffff00\nffffff01\n5a67f100\n5a67f109\n |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
lsrq 0,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
lsrq 1,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1 |
|
moveq -1,r3 |
lsrq 31,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1 |
|
moveq -1,r3 |
lsrq 15,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1ffff |
|
move.d 0x5a67f19f,r3 |
lsrq 12,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 5a67f |
|
move.d 0xda67f19f,r3 |
move.d 31,r4 |
lsr.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1 |
|
move.d 0xda67f19f,r3 |
move.d 32,r4 |
lsr.d r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0xda67f19f,r3 |
move.d 33,r4 |
lsr.d r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0xda67f19f,r3 |
move.d 66,r4 |
lsr.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 3699fc67 |
|
moveq -1,r3 |
moveq 0,r4 |
lsr.d r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
moveq 1,r4 |
lsr.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1 |
|
moveq -1,r3 |
moveq 31,r4 |
lsr.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1 |
|
moveq -1,r3 |
moveq 15,r4 |
lsr.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1ffff |
|
move.d 0x5a67f19f,r3 |
moveq 12,r4 |
lsr.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 5a67f |
|
move.d 0xda67f19f,r3 |
move.d 31,r4 |
lsr.w r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; da670000 |
|
move.d 0xda67f19f,r3 |
move.d 32,r4 |
lsr.w r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; da670000 |
|
move.d 0xda67f19f,r3 |
move.d 33,r4 |
lsr.w r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; da670000 |
|
move.d 0xda67f19f,r3 |
move.d 66,r4 |
lsr.w r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; da673c67 |
|
moveq -1,r3 |
moveq 0,r4 |
lsr.w r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
moveq 1,r4 |
lsr.w r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff7fff |
|
moveq 2,r3 |
moveq 1,r4 |
lsr.w r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1 |
|
moveq -1,r3 |
moveq 31,r4 |
lsr.w r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; ffff0000 |
|
moveq -1,r3 |
moveq 15,r4 |
lsr.w r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff0001 |
|
move.d 0x5a67f19f,r3 |
moveq 12,r4 |
lsr.w r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 5a67000f |
|
move.d 0xda67f19f,r3 |
move.d 31,r4 |
lsr.b r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; da67f100 |
|
move.d 0xda67f19f,r3 |
move.d 32,r4 |
lsr.b r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; da67f100 |
|
move.d 0xda67f19f,r3 |
move.d 33,r4 |
lsr.b r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; da67f100 |
|
move.d 0xda67f19f,r3 |
move.d 66,r4 |
lsr.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; da67f127 |
|
moveq -1,r3 |
moveq 0,r4 |
lsr.b r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
moveq 1,r4 |
lsr.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffffff7f |
|
moveq 2,r3 |
moveq 1,r4 |
lsr.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1 |
|
moveq -1,r3 |
moveq 31,r4 |
lsr.b r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; ffffff00 |
|
moveq -1,r3 |
moveq 15,r4 |
lsr.b r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; ffffff00 |
|
moveq -1,r3 |
moveq 7,r4 |
lsr.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffffff01 |
|
move.d 0x5a67f19f,r3 |
moveq 12,r4 |
lsr.b r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 5a67f100 |
|
move.d 0x5a67f19f,r3 |
moveq 4,r4 |
lsr.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 5a67f109 |
|
quit |
/not.ms
0,0 → 1,31
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: fffffffe\nfffffffd\nffff0f00\n0\n87ecbbad\n |
|
.include "testutils.inc" |
start |
moveq 1,r3 |
not r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fffffffe |
|
moveq 2,r3 |
not r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fffffffd |
|
move.d 0xf0ff,r3 |
not r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffff0f00 |
|
moveq -1,r3 |
not r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0x78134452,r3 |
not r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; 87ecbbad |
|
quit |
/x5-v10.ms
0,0 → 1,9
#mach: crisv10 |
#ld: --section-start=.text=0 |
#sim: --cris-trace=basic |
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n |
#output: 8 0 0 0 0 0 14 0 0 0 0 0 0 0 0 * ixnzvc 2\n |
#output: a 0 0 0 0 1 14 0 0 0 0 0 0 0 0 * ixnzvc 2\n |
#output: c 0 0 0 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 2\n |
#output: e 0 0 2 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 2\n |
.include "tmemv10.ms" |
/orq.ms
0,0 → 1,41
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 3\n3\nffffffff\nffffffff\n1f\nffffffe0\n7813445e\n |
|
.include "testutils.inc" |
start |
moveq 1,r3 |
orq 2,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 3 |
|
moveq 2,r3 |
orq 1,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 3 |
|
move.d 0xf0ff,r3 |
orq -1,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq 0,r3 |
orq -1,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq 0,r3 |
orq 31,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1f |
|
moveq 0,r3 |
orq -32,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffe0 |
|
move.d 0x78134452,r3 |
orq 12,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 7813445e |
|
quit |
/x3-v32.ms
0,0 → 1,10
#mach: crisv32 |
#ld: --section-start=.text=0 |
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n |
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: a 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 12 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 1e 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#sim: --cris-trace=basic |
|
.include "tjsrcv10.ms" |
/bas.ms
0,0 → 1,102
# mach: crisv32 |
# output: 0\n0\n0\nfb349abc\n0\n12124243\n0\n0\neab5baad\n0\nefb37832\n |
|
.include "testutils.inc" |
start |
x: |
setf zncv |
bsr 0f |
nop |
0: |
test_cc 1 1 1 1 |
move srp,r3 |
sub.d 0b,r3 |
dumpr3 |
|
bas 1f,mof |
moveq 0,r0 |
6: |
nop |
quit |
|
2: |
move srp,r3 |
sub.d 3f,r3 |
dumpr3 |
move srp,r4 |
subq 4,r4 |
move.d [r4],r3 |
dumpr3 |
|
basc 4f,mof |
nop |
.dword 0x12124243 |
7: |
nop |
quit |
|
8: |
move mof,r3 |
sub.d 7f,r3 |
dumpr3 |
|
move mof,r4 |
subq 4,r4 |
move.d [r4],r3 |
dumpr3 |
|
jasc 9f,mof |
nop |
.dword 0xefb37832 |
0: |
quit |
|
quit |
9: |
move mof,r3 |
sub.d 0b,r3 |
dumpr3 |
|
move mof,r4 |
subq 4,r4 |
move.d [r4],r3 |
dumpr3 |
|
quit |
|
4: |
move mof,r3 |
sub.d 7b,r3 |
dumpr3 |
move mof,r4 |
subq 4,r4 |
move.d [r4],r3 |
dumpr3 |
basc 5f,bz |
moveq 0,r3 |
.dword 0x7634aeba |
quit |
|
.space 32770,0 |
1: |
move mof,r3 |
sub.d 6b,r3 |
dumpr3 |
|
bsrc 2b |
nop |
.dword 0xfb349abc |
3: |
|
quit |
|
5: |
move mof,r3 |
sub.d 7b,r3 |
dumpr3 |
move.d 8b,r6 |
jasc r6,mof |
nop |
.dword 0xeab5baad |
7: |
quit |
/neg.ms
0,0 → 1,102
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: ffffffff\nffffffff\n0\n80000000\n1\nba987655\nffff\nffff\n0\n89ab8000\nffff0001\n45677655\nff\nff\n0\n89abae80\nffffff01\n45678955\n |
|
.include "testutils.inc" |
start |
moveq 0,r3 |
moveq 1,r4 |
neg.d r4,r3 |
test_cc 1 0 0 1 |
dumpr3 ; ffffffff |
|
moveq 1,r3 |
moveq 0,r4 |
neg.d r3,r3 |
test_cc 1 0 0 1 |
dumpr3 ; ffffffff |
|
moveq 0,r3 |
neg.d r3,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0x80000000,r3 |
neg.d r3,r3 |
test_cc 1 0 1 1 |
dumpr3 ; 80000000 |
|
moveq -1,r3 |
neg.d r3,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1 |
|
move.d 0x456789ab,r3 |
neg.d r3,r3 |
test_cc 1 0 0 1 |
dumpr3 ; ba987655 |
|
moveq 0,r3 |
moveq 1,r4 |
neg.w r4,r3 |
test_cc 1 0 0 1 |
dumpr3 ; ffff |
|
moveq 1,r3 |
moveq 0,r4 |
neg.w r3,r3 |
test_cc 1 0 0 1 |
dumpr3 ; ffff |
|
moveq 0,r3 |
neg.w r3,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0x89ab8000,r3 |
neg.w r3,r3 |
test_cc 1 0 1 1 |
dumpr3 ; 89ab8000 |
|
moveq -1,r3 |
neg.w r3,r3 |
test_cc 0 0 0 1 |
dumpr3 ; ffff0001 |
|
move.d 0x456789ab,r3 |
neg.w r3,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 45677655 |
|
moveq 0,r3 |
moveq 1,r4 |
neg.b r4,r3 |
test_cc 1 0 0 1 |
dumpr3 ; ff |
|
moveq 1,r3 |
moveq 0,r4 |
neg.b r3,r3 |
test_cc 1 0 0 1 |
dumpr3 ; ff |
|
moveq 0,r3 |
neg.b r3,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0x89abae80,r3 |
neg.b r3,r3 |
test_cc 1 0 1 1 |
dumpr3 ; 89abae80 |
|
moveq -1,r3 |
neg.b r3,r3 |
test_cc 0 0 0 1 |
dumpr3 ; ffffff01 |
|
move.d 0x456789ab,r3 |
neg.b r3,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 45678955 |
|
quit |
/movscpc.ms
0,0 → 1,13
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
movs.b 0x42,pc |
dumpr3 |
|
movs.w 0x4321,pc |
dumpr3 |
|
quit |
/rfg.ms
0,0 → 1,9
# mach: crisv32 |
# xerror: |
# output: RFG isn't implemented\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
rfg |
|
quit |
/raw8.ms
0,0 → 1,26
; Checking read-after-write: movemwrite-then-nop-read 2 cycles. |
#mach: crisv32 |
#ld: --section-start=.text=0 |
#output: Basic clock cycles, total @: 7\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 2\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 1\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
.include "testutils.inc" |
startnostack |
.lcomm x,4*11 |
.lcomm y,4 |
move.d x,$r0 |
move.d y,$r1 |
nop |
nop |
movem $r10,[$r0] |
nop |
move.d [$r1],$r2 |
break 15 |
/cmpc.ms
0,0 → 1,86
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: ffffffff\n2\nffff\nffffffff\n78134452\nffffffff\n2\nffff\nfedaffff\n78134452\nffffffff\n2\nff\nfeda49ff\n78134452\n85649282\n |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
cmp.d -2,r3 |
test_cc 0 0 0 0 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
cmp.d 1,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xffff,r3 |
cmp.d -0xffff,r3 |
test_cc 0 0 0 1 |
dumpr3 ; ffff |
|
moveq -1,r3 |
cmp.d 1,r3 |
test_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d 0x78134452,r3 |
cmp.d -0x5432f789,r3 |
test_cc 1 0 1 1 |
dumpr3 ; 78134452 |
|
moveq -1,r3 |
cmp.w -2,r3 |
test_cc 0 0 0 0 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
cmp.w 1,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xffff,r3 |
cmp.w 1,r3 |
test_cc 1 0 0 0 |
dumpr3 ; ffff |
|
move.d 0xfedaffff,r3 |
cmp.w 1,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fedaffff |
|
move.d 0x78134452,r3 |
cmp.w 0x877,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 78134452 |
|
moveq -1,r3 |
cmp.b -2,r3 |
test_cc 0 0 0 0 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
cmp.b 1,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xff,r3 |
cmp.b 1,r3 |
test_cc 1 0 0 0 |
dumpr3 ; ff |
|
move.d 0xfeda49ff,r3 |
cmp.b 1,r3 |
test_cc 1 0 0 0 |
dumpr3 ; feda49ff |
|
move.d 0x78134452,r3 |
cmp.b 0x77,r3 |
test_cc 1 0 0 1 |
dumpr3 ; 78134452 |
|
move.d 0x85649282,r3 |
cmp.b 0x82,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 85649282 |
|
quit |
/ba.ms
0,0 → 1,93
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: a\n |
|
.include "testutils.inc" |
|
.if ..asm.arch.cris.v32 |
.set smalloffset,0 |
.set largeoffset,0 |
.else |
.set smalloffset,2 |
.set largeoffset,4 |
.endif |
|
start |
moveq 0,r3 |
|
; Short forward branch. |
ba 0f |
addq 1,r3 |
fail |
|
; Max short forward branch. |
1: |
ba 2f |
addq 1,r3 |
fail |
|
; Short backward branch. |
0: |
ba 1b |
addq 1,r3 |
fail |
|
.space 254-2+smalloffset+1b-.,0 |
moveq 0,r3 |
|
2: |
; Transit branch (long). |
ba 3f |
addq 1,r3 |
fail |
|
moveq 0,r3 |
4: |
; Long forward branch. |
ba 5f |
addq 1,r3 |
fail |
|
.space 256-2-smalloffset+4b-.,0 |
|
moveq 0,r3 |
|
; Max short backward branch. |
3: |
ba 4b |
addq 1,r3 |
fail |
|
5: |
; Max long forward branch. |
ba 6f |
addq 1,r3 |
fail |
|
.space 32766+largeoffset-2+5b-.,0 |
|
moveq 0,r3 |
6: |
; Transit branch. |
ba 7f |
addq 1,r3 |
fail |
|
moveq 0,r3 |
9: |
dumpr3 |
quit |
|
; Transit branch. |
moveq 0,r3 |
7: |
ba 8f |
addq 1,r3 |
fail |
|
.space 32768-largeoffset+9b-.,0 |
|
8: |
; Max long backward branch. |
ba 9b |
addq 1,r3 |
fail |
/asr.ms
0,0 → 1,228
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: ffffffff\n1\nffffffff\nffffffff\n5a67f\nffffffff\nffffffff\nffffffff\nf699fc67\nffffffff\n1\nffffffff\nffffffff\n5a67f\nda67ffff\nda67ffff\nda67ffff\nda67fc67\nffffffff\nffffffff\n1\nffffffff\nffffffff\n5a670007\nda67f1ff\nda67f1ff\nda67f1ff\nda67f1e7\nffffffff\nffffffff\n1\nffffffff\nffffffff\nffffffff\n5a67f1ff\n5a67f1f9\n0\n5a670000\n |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
asrq 0,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
asrq 1,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1 |
|
moveq -1,r3 |
asrq 31,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
asrq 15,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d 0x5a67f19f,r3 |
asrq 12,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 5a67f |
|
move.d 0xda67f19f,r3 |
move.d 31,r4 |
asr.d r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d 0xda67f19f,r3 |
move.d 32,r4 |
asr.d r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d 0xda67f19f,r3 |
move.d 33,r4 |
asr.d r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d 0xda67f19f,r3 |
move.d 66,r4 |
asr.d r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; f699fc67 |
|
moveq -1,r3 |
moveq 0,r4 |
asr.d r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
moveq 1,r4 |
asr.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1 |
|
moveq -1,r3 |
moveq 31,r4 |
asr.d r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
moveq 15,r4 |
asr.d r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d 0x5a67f19f,r3 |
moveq 12,r4 |
asr.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 5a67f |
|
move.d 0xda67f19f,r3 |
move.d 31,r4 |
asr.w r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; da67ffff |
|
move.d 0xda67f19f,r3 |
move.d 32,r4 |
asr.w r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; da67ffff |
|
move.d 0xda67f19f,r3 |
move.d 33,r4 |
asr.w r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; da67ffff |
|
move.d 0xda67f19f,r3 |
move.d 66,r4 |
asr.w r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; da67fc67 |
|
moveq -1,r3 |
moveq 0,r4 |
asr.w r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
moveq 1,r4 |
asr.w r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
moveq 1,r4 |
asr.w r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1 |
|
moveq -1,r3 |
moveq 31,r4 |
asr.w r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
moveq 15,r4 |
asr.w r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d 0x5a67719f,r3 |
moveq 12,r4 |
asr.w r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 5a670007 |
|
move.d 0xda67f19f,r3 |
move.d 31,r4 |
asr.b r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; da67f1ff |
|
move.d 0xda67f19f,r3 |
move.d 32,r4 |
asr.b r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; da67f1ff |
|
move.d 0xda67f19f,r3 |
move.d 33,r4 |
asr.b r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; da67f1ff |
|
move.d 0xda67f19f,r3 |
move.d 66,r4 |
asr.b r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; da67f1e7 |
|
moveq -1,r3 |
moveq 0,r4 |
asr.b r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
moveq 1,r4 |
asr.b r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
moveq 1,r4 |
asr.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1 |
|
moveq -1,r3 |
moveq 31,r4 |
asr.b r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
moveq 15,r4 |
asr.b r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
moveq 7,r4 |
asr.b r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d 0x5a67f19f,r3 |
moveq 12,r4 |
asr.b r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; 5a67f1ff |
|
move.d 0x5a67f19f,r3 |
moveq 4,r4 |
asr.b r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; 5a67f1f9 |
|
move.d 0x5a67f19f,r3 |
asrq 31,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0x5a67419f,r3 |
moveq 16,r4 |
asr.w r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 5a670000 |
|
quit |
/movpmv10.ms
0,0 → 1,35
# mach: crisv10 |
# output: 1122330a\nbb113344\naa557711\n |
|
# Test v10-specific special registers. FIXME: ccr, irp, bar, brp, usp. |
|
.include "testutils.inc" |
start |
.data |
store: |
.dword 0x11223344 |
.dword 0x77665544 |
|
.text |
moveq -1,r3 |
move.d store,r4 |
clearf zcvn |
move vr,[r4] |
test_cc 0 0 0 0 |
move [r4+],mof |
move mof,r3 |
dumpr3 |
|
moveq -1,r3 |
move 0xbb113344,mof |
move mof,r3 |
dumpr3 |
|
move 0xaa557711,mof |
setf zcvn |
move mof,[r4] |
test_cc 1 1 1 1 |
move.d [r4],r3 |
dumpr3 |
|
quit |
/jumppv32.ms
0,0 → 1,28
# mach: crisv32 |
# output: 2222\n |
|
# Test that jump Pd works. |
|
.include "testutils.inc" |
start |
x: |
setf zvnc |
move 0f,srp |
test_cc 1 1 1 1 |
jump srp |
nop |
quit |
|
0: |
test_cc 1 1 1 1 |
move 1f,mof |
jump mof |
nop |
quit |
|
.space 32768,0 |
quit |
1: |
move.d 0x2222,r3 |
dumpr3 |
quit |
/movmp8.ms
0,0 → 1,33
# mach: crisv3 crisv8 crisv10 |
|
# Make sure that "move [$sp=$sp+16],$p8" works; used in Linux. |
|
.include "testutils.inc" |
startnostack |
move.d x,$sp |
moveq 0,$r3 |
move [$sp=$sp+16],$p8 |
; Z not changed. |
bne 0f |
nop |
cmp.d x+16,$sp |
bne 0f |
nop |
move $p8,$r3 |
; Z not changed. |
bne 0f |
; P8 still 0. |
test.d $r3 |
bne 0f |
nop |
pass |
0: |
fail |
|
.data |
x: |
.dword 0xffffffff |
.dword 0xffffffff |
.dword 0xffffffff |
.dword 0xffffffff |
.dword 0xffffffff |
/bccb.ms
0,0 → 1,181
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 1c\n |
|
.include "testutils.inc" |
start |
moveq 0,r3 |
|
clearf nzvc |
setf nzv |
bcc 0f |
addq 1,r3 |
fail |
|
0: |
clearf nzvc |
setf nzv |
bcs dofail |
addq 1,r3 |
|
clearf nzvc |
setf ncv |
bne 1f |
addq 1,r3 |
|
dofail: |
fail |
|
1: |
clearf nzvc |
setf ncv |
beq dofail |
addq 1,r3 |
|
clearf nzvc |
setf ncz |
bvc 2f |
addq 1,r3 |
fail |
|
2: |
clearf nzvc |
setf ncz |
bvs dofail |
addq 1,r3 |
|
clearf nzvc |
setf vcz |
bpl 3f |
addq 1,r3 |
fail |
|
3: |
clearf nzvc |
setf vcz |
bmi dofail |
addq 1,r3 |
|
clearf nzvc |
setf nv |
bls dofail |
addq 1,r3 |
|
clearf nzvc |
setf nv |
bhi 4f |
addq 1,r3 |
fail |
|
4: |
clearf nzvc |
setf zc |
bge 5f |
addq 1,r3 |
fail |
|
5: |
clearf nzvc |
setf zc |
blt dofail |
addq 1,r3 |
|
clearf nzvc |
setf c |
bgt 6f |
addq 1,r3 |
fail |
|
6: |
clearf nzvc |
setf c |
ble dofail |
addq 1,r3 |
|
;;;;;;;;;; |
|
setf nzvc |
clearf nzv |
bcc dofail |
addq 1,r3 |
|
setf nzvc |
clearf nzv |
bcs 0f |
addq 1,r3 |
fail |
|
0: |
setf nzvc |
clearf ncv |
bne dofail |
addq 1,r3 |
|
setf nzvc |
clearf ncv |
beq 1f |
addq 1,r3 |
fail |
|
1: |
setf nzvc |
clearf ncz |
bvc dofail |
addq 1,r3 |
|
setf nzvc |
clearf ncz |
bvs 2f |
addq 1,r3 |
fail |
|
2: |
setf nzvc |
clearf vcz |
bpl dofail |
addq 1,r3 |
|
setf nzvc |
clearf vcz |
bmi 3f |
addq 1,r3 |
fail |
|
3: |
setf nzvc |
clearf nv |
bls 4f |
addq 1,r3 |
fail |
|
4: |
setf nzvc |
clearf nv |
bhi dofail |
addq 1,r3 |
|
setf zvc |
clearf nzc |
bge dofail |
addq 1,r3 |
|
setf nzc |
clearf vzc |
blt 5f |
addq 1,r3 |
fail |
|
5: |
setf nzvc |
clearf c |
bgt dofail |
addq 1,r3 |
|
setf nzvc |
clearf c |
ble 6f |
addq 1,r3 |
fail |
|
6: |
dumpr3 |
quit |
/movrss.ms
0,0 → 1,8
# mach: crisv32 |
# xerror: |
# output: Write to support register is unimplemented\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
move R3,S0 |
|
/subc.ms
0,0 → 1,86
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n85649200\n |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
sub.d -2,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
|
moveq 2,r3 |
sub.d 1,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
|
move.d 0xffff,r3 |
sub.d -0xffff,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1fffe |
|
moveq -1,r3 |
sub.d 1,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fffffffe |
|
move.d 0x78134452,r3 |
sub.d -0x5432f789,r3 |
test_cc 1 0 1 1 |
dumpr3 ; cc463bdb |
|
moveq -1,r3 |
sub.w -2,r3 |
test_cc 0 0 0 0 |
dumpr3 ; ffff0001 |
|
moveq 2,r3 |
sub.w 1,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
|
move.d 0xffff,r3 |
sub.w 1,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fffe |
|
move.d 0xfedaffff,r3 |
sub.w 1,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fedafffe |
|
move.d 0x78134452,r3 |
sub.w 0x877,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 78133bdb |
|
moveq -1,r3 |
sub.b -2,r3 |
test_cc 0 0 0 0 |
dumpr3 ; ffffff01 |
|
moveq 2,r3 |
sub.b 1,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
|
move.d 0xff,r3 |
sub.b 1,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fe |
|
move.d 0xfeda49ff,r3 |
sub.b 1,r3 |
test_cc 1 0 0 0 |
dumpr3 ; feda49fe |
|
move.d 0x78134452,r3 |
sub.b 0x77,r3 |
test_cc 1 0 0 1 |
dumpr3 ; 781344db |
|
move.d 0x85649282,r3 |
sub.b 0x82,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 85649200 |
|
quit |
/tmemv32.ms
0,0 → 1,14
#mach: crisv32 |
#output: Basic clock cycles, total @: 4\n |
#output: Memory source stall cycles: 1\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
|
.include "tmemv10.ms" |
/subqpc.ms
0,0 → 1,8
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
subq 31,pc |
|
/raw13.ms
0,0 → 1,22
; Checking read-after-write: write-MOF-then-read unaffected. |
#mach: crisv32 |
#output: Basic clock cycles, total @: 4\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
.include "testutils.inc" |
startnostack |
.lcomm x,4 |
.lcomm y,4 |
move.d x,$r0 |
move.d y,$r1 |
move [$r0],$mof |
move [$r1],$srp |
break 15 |
/asm.exp
0,0 → 1,45
# Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc. |
# |
# This program is free software; you can redistribute it and/or modify |
# it under the terms of the GNU General Public License as published by |
# the Free Software Foundation; either version 3 of the License, or |
# (at your option) any later version. |
# |
# This program is distributed in the hope that it will be useful, |
# but WITHOUT ANY WARRANTY; without even the implied warranty of |
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
# GNU General Public License for more details. |
# |
# You should have received a copy of the GNU General Public License |
# along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
# Miscellaneous CRIS simulator testcases in assembly code. |
|
if [istarget cris*-*-*] { |
global ASFLAGS_FOR_TARGET |
# All machines we test and the corresponding assembler option. Needs |
# update if we build the simulator for crisv0 crisv3 and crisv8 too. |
|
set combos {{"crisv10" "--march=v10 --no-mul-bug-abort"} |
{"crisv32" "--march=v32"}} |
|
# We need to pass different assembler flags for each machine. |
# Specifying it here rather than adding a specifier to each and every |
# test-file is preferrable. |
|
foreach combo $combos { |
set mach [lindex $combo 0] |
set ASFLAGS_FOR_TARGET "[lindex $combo 1]" |
|
# The .ms suffix is for "miscellaneous .s". |
foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { |
# If we're only testing specific files and this isn't one of them, |
# skip it. |
if ![runtest_file_p $runtests $src] { |
continue |
} |
|
run_sim_test $src $mach |
} |
} |
} |
/io8.ms
0,0 → 1,21
# mach: crisv32 |
# ld: --section-start=.text=0 |
# xerror: |
# output: b1e\n |
# output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n |
# output: program stopped with signal 11.\n |
|
; Check invalid access valid with --cris-900000xx. |
; "FAIL" area. |
|
.include "testutils.inc" |
start |
move.d 0xb1e,$r3 |
dumpr3 |
move.d 0x90000008,$acr |
move.d $acr,[$acr] |
move.d 0xbadc0de,$r3 |
dumpr3 |
0: |
ba 0b |
nop |
/tmvrmv32.ms
0,0 → 1,14
#mach: crisv32 |
#output: Basic clock cycles, total @: 14\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 3\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
|
.include "tmvrmv10.ms" |
/x2-v32.ms
0,0 → 1,59
#mach: crisv32 |
#ld: --section-start=.text=0 |
#sim: --cris-trace=basic |
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n |
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n |
#output: c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n |
#output: 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n |
#output: 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 16 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 18 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 1a 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 16 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 18 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 1a 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 16 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 18 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 1a 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 16 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 18 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 1a 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n |
#output: 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n |
#output: 1a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n |
#output: 1c ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n |
#output: 1e ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n |
#output: 20 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n |
#output: 22 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n |
#output: 26 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n |
#output: 230 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n |
#output: 232 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n |
#output: 236 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n |
#output: 440 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n |
#output: 442 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n |
#output: 446 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n |
#output: 650 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n |
#output: 654 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n |
#output: 442 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 446 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 650 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 654 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 442 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 446 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 650 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 654 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 442 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 446 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 650 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 654 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 442 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n |
#output: 446 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n |
#output: 650 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n |
#output: 654 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n |
#output: 656 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n |
#output: 658 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n |
#output: 65a ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n |
.include "tb.ms" |
/addi.ms
0,0 → 1,57
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 0\n1\n2\n4\nbe02460f\n69d035a6\nc16c14d4\n |
|
.include "testutils.inc" |
start |
moveq 0,r3 |
moveq 0,r4 |
clearf zcvn |
addi r4.b,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 0 |
|
moveq 0,r3 |
moveq 1,r4 |
setf zcvn |
addi r4.b,r3 |
test_cc 1 1 1 1 |
dumpr3 ; 1 |
|
moveq 0,r3 |
moveq 1,r4 |
setf cv |
clearf zn |
addi r4.w,r3 |
test_cc 0 0 1 1 |
dumpr3 ; 2 |
|
moveq 0,r3 |
moveq 1,r4 |
clearf cv |
setf zn |
addi r4.d,r3 |
test_cc 1 1 0 0 |
dumpr3 ; 4 |
|
move.d 0x12345678,r3 |
move.d 0xabcdef97,r4 |
clearf cn |
setf zv |
addi r4.b,r3 |
test_cc 0 1 1 0 |
dumpr3 ; be02460f |
|
move.d 0x12345678,r3 |
move.d 0xabcdef97,r4 |
setf cn |
clearf zv |
addi r4.w,r3 |
test_cc 1 0 0 1 |
dumpr3 ; 69d035a6 |
|
move.d 0x12345678,r3 |
move.d 0xabcdef97,r4 |
addi r4.d,r3 |
dumpr3 ; c16c14d4 |
|
quit |
/addxr.ms
0,0 → 1,93
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 1\n1\n101\n10001\n100fe\n1fffe\nfffe\nfffe\nfffffffe\nfe\nfffffffe\n781344db\n781343db\n78143bdb\n78133bdb\n800000ed\n0\n |
|
.include "testutils.inc" |
start |
moveq 2,r3 |
move.d 0xff,r4 |
adds.b r4,r3 |
dumpr3 ; 1 |
|
moveq 2,r3 |
move.d 0xffff,r4 |
adds.w r4,r3 |
dumpr3 ; 1 |
|
moveq 2,r3 |
move.d 0xffff,r4 |
addu.b r4,r3 |
dumpr3 ; 101 |
|
moveq 2,r3 |
move.d 0xffffffff,r4 |
addu.w r4,r3 |
dumpr3 ; 10001 |
|
move.d 0xffff,r3 |
move.d 0xffffffff,r4 |
addu.b r4,r3 |
dumpr3 ; 100fe |
|
move.d 0xffff,r3 |
move.d 0xffffffff,r4 |
addu.w r4,r3 |
dumpr3 ; 1fffe |
|
move.d 0xffff,r3 |
move.d 0xff,r4 |
adds.b r4,r3 |
dumpr3 ; fffe |
|
move.d 0xffff,r4 |
move.d r4,r3 |
adds.w r4,r3 |
dumpr3 ; fffe |
|
moveq -1,r3 |
move.d 0xff,r4 |
adds.b r4,r3 |
dumpr3 ; fffffffe |
|
moveq -1,r3 |
move.d 0xff,r4 |
adds.w r4,r3 |
dumpr3 ; fe |
|
moveq -1,r3 |
move.d 0xffff,r4 |
adds.w r4,r3 |
dumpr3 ; fffffffe |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
addu.b r4,r3 |
dumpr3 ; 781344db |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
adds.b r4,r3 |
dumpr3 ; 781343db |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
addu.w r4,r3 |
dumpr3 ; 78143bdb |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
adds.w r4,r3 |
dumpr3 ; 78133bdb |
|
move.d 0x7fffffee,r3 |
move.d 0xff,r4 |
addu.b r4,r3 |
test_cc 1 0 1 0 |
dumpr3 ; 800000ed |
|
move.d 0x1,r3 |
move.d 0xffff,r4 |
adds.w r4,r3 |
test_cc 0 1 0 1 |
dumpr3 ; 0 |
|
quit |
/tmvm2.ms
0,0 → 1,351
#mach: crisv32 |
#output: Basic clock cycles, total @: *\n |
#output: Memory source stall cycles: 82\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 6\n |
#output: Movem destination stall cycles: 880\n |
#output: Movem address stall cycles: 4\n |
#output: Multiplication source stall cycles: 18\n |
#output: Jump source stall cycles: 6\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
|
.include "testutils.inc" |
|
; Macros for testing correctness of movem destination stall |
; cycles for various insn types. Beware: macro parameters can |
; be comma or space-delimited. There are problems (i.e. bugs) |
; with using space-delimited operands and operands with |
; non-alphanumeric characters, like "[]-." so use comma for |
; them. Lots of trouble passing empty parameters and parameters |
; with comma. Ugh. FIXME: Report bugs, fix bugs, fix other |
; shortcomings, fix that darn old macro-parameter-in-string. |
|
; Helper macro. Unfortunately I find no cleaner way to unify |
; one and two-operand cases, the main problem being the comma |
; operand delimiter clashing with macro operand delimiter. |
.macro t_S_x_y S insn x y=none |
movem [r7],r6 |
.ifc \y,none |
.ifc \S,none |
\insn \x |
.else |
\insn\S \x |
.endif |
.else |
.ifc \S,none |
\insn \x,\y |
.else |
\insn\S \x,\y |
.endif |
.endif |
nop |
nop |
nop |
.endm |
|
; An insn-type that has a single register operand. The register |
; may or may not be a source register for the insn. |
.macro t_r insn |
t_S_x_y none,\insn,r3 |
t_S_x_y none,\insn,r8 |
.endm |
|
; An insn-type that jumps to the destination of the register. |
.macro t_r_j insn |
move.d 0f,r7 |
move.d 1f,r8 |
move.d r8,r9 |
nop |
nop |
nop |
.section ".rodata" |
.p2align 5 |
0: |
.dword 1f |
.dword 1f |
.dword 1f |
.dword 1f |
.dword 1f |
.dword 1f |
.dword 1f |
.previous |
t_r \insn |
1: |
.endm |
|
; An insn-type that has a size-modifier and two register |
; operands. |
.macro t_xr_r S insn |
t_S_x_y \S \insn r3 r8 |
t_S_x_y \S \insn r8 r3 |
move.d r3,r9 |
t_S_x_y \S \insn r4 r3 |
t_S_x_y \S \insn r8 r9 |
.endm |
|
; An insn-type that has two register operands. |
.macro t_r_r insn |
t_xr_r none \insn |
.endm |
|
; An t_r_rx insn with a byte or word-size modifier. |
.macro t_wbr_r insn |
t_xr_r .b,\insn |
t_xr_r .w,\insn |
.endm |
|
; Ditto with a dword-size modifier. |
.macro t_dwbr_r insn |
t_xr_r .d,\insn |
t_wbr_r \insn |
.endm |
|
; An insn-type that has a size-modifier, a constant and a |
; register operand. |
.macro t_xc_r S insn |
t_S_x_y \S \insn 24 r3 |
move.d r3,r9 |
t_S_x_y \S \insn 24 r8 |
.endm |
|
; An insn-type that has a constant and a register operand. |
.macro t_c_r insn |
t_xc_r none \insn |
.endm |
|
; An t_c_r insn with a byte or word-size modifier. |
.macro t_wbc_r insn |
t_xc_r .b,\insn |
t_xc_r .w,\insn |
.endm |
|
; Ditto with a dword-size modifier. |
.macro t_dwbc_r insn |
t_xc_r .d,\insn |
t_wbc_r \insn |
.endm |
|
; An insn-type that has size-modifier, a memory operand and a |
; register operand. |
.macro t_xm_r S insn |
move.d 9b,r8 |
t_S_x_y \S,\insn,[r4],r3 |
move.d r3,r9 |
t_S_x_y \S,\insn,[r8],r5 |
move.d r5,r9 |
t_S_x_y \S,\insn,[r3],r9 |
t_S_x_y \S,\insn,[r8],r9 |
.endm |
|
; Ditto, to memory. |
.macro t_xr_m S insn |
move.d 9b,r8 |
t_S_x_y \S,\insn,r3,[r4] |
t_S_x_y \S,\insn,r8,[r3] |
t_S_x_y \S,\insn,r3,[r8] |
t_S_x_y \S,\insn,r9,[r8] |
.endm |
|
; An insn-type that has a memory operand and a register operand. |
.macro t_m_r insn |
t_xm_r none \insn |
.endm |
|
; An t_m_r insn with a byte or word-size modifier. |
.macro t_wbm_r insn |
t_xm_r .b,\insn |
t_xm_r .w,\insn |
.endm |
|
; Ditto with a dword-size modifier. |
.macro t_dwbm_r insn |
t_xm_r .d,\insn |
t_wbm_r \insn |
.endm |
|
; Insn types of the regular type (r, c, m, size d w b). |
.macro t_dwb insn |
t_dwbr_r \insn |
t_dwbc_r \insn |
t_dwbm_r \insn |
.endm |
|
; Similar, sizes w b. |
.macro t_wb insn |
t_wbr_r \insn |
t_wbc_r \insn |
t_wbm_r \insn |
.endm |
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
|
startnostack |
|
; Initialize registers so they don't contain unknowns. |
|
move.d 9f,r7 |
move.d r7,r8 |
moveq 0,r9 |
|
; Movem source area. Register contents must be valid |
; addresses, aligned on a cache boundary. |
.section ".rodata" |
.p2align 5 |
9: |
.dword 9b |
.dword 9b |
.dword 9b |
.dword 9b |
.dword 9b |
.dword 9b |
.dword 9b |
.dword 9b |
.dword 9b |
.dword 9b |
.previous |
|
; The actual tests. The numbers in the comments specify the |
; number of movem destination stall cycles. Some of them may be |
; filed as memory source address stalls, multiplication source |
; stalls or jump source stalls, duly marked so. |
|
t_r_r abs ; 3+3 |
|
t_dwb add ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) |
|
t_r_r addc ; (3+3+3) |
t_c_r addc ; 3 |
t_m_r addc ; (3+3+3) (2 mem src) |
|
t_dwb move ; (3+3)+(3+3+3)*2+3*2+(3+3+3)*3 (6 mem src) |
t_xr_m .b move ; 3+3+3 (2 mem src) |
t_xr_m .w move ; 3+3+3 (2 mem src) |
t_xr_m .d move ; 3+3+3 (2 mem src) |
|
t_S_x_y none addi r3.b r8 ; 3 |
t_S_x_y none addi r8.w r3 ; 3 |
t_S_x_y none addi r4.d r3 ; 3 |
t_S_x_y none addi r8.w r9 |
|
; Addo has three-operand syntax, so we have to expand (a useful |
; subset of) "t_dwb". |
t_S_x_y none addi r3.b "r8,acr" ; 3 |
t_S_x_y none addi r8.w "r3,acr" ; 3 |
t_S_x_y none addi r4.d "r3,acr" ; 3 |
t_S_x_y none addi r8.w "r9,acr" |
|
t_S_x_y .b addo 42 "r8,acr" |
t_S_x_y .w addo 4200 "r3,acr" ; 3 |
t_S_x_y .d addo 420000 "r3,acr" ; 3 |
|
move.d 9b,r8 |
t_S_x_y .d,addo,[r4],"r3,acr" ; 3 (1 mem src) |
t_S_x_y .b,addo,[r3],"r8,acr" ; 3 (1 mem src) |
t_S_x_y .w,addo,[r8],"r3,acr" ; 3 |
t_S_x_y .w,addo,[r8],"r9,acr" |
|
; Similar for addoq. |
t_S_x_y none addoq 42 "r8,acr" |
t_S_x_y none addoq 42 "r3,acr" ; 3 |
|
t_c_r addq ; 3 |
|
t_wb adds ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src) |
t_wb addu ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src) |
|
t_dwb and ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) |
t_c_r andq ; 3 |
|
t_dwbr_r asr ; (3+3+3)*3 |
t_c_r asrq ; 3 |
|
t_dwbr_r bound ; (3+3+3)*3 |
t_dwbc_r bound ; 3*3 |
|
t_r_r btst ; (3+3+3) |
t_c_r btstq ; 3 |
|
t_dwb cmp ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) |
t_c_r cmpq ; 3 |
|
t_wbc_r cmps ; 3*2 |
t_wbc_r cmpu ; 3*2 |
t_wbm_r cmps ; (3+3+3)*2 (4 mem src) |
t_wbm_r cmpu ; (3+3+3)*2 (4 mem src) |
|
t_r_r dstep ; (3+3+3) |
|
; FIXME: idxd, fidxi, ftagd, ftagi when supported. |
|
t_r_j jsr ; 3 (2 jump src) |
t_r_j jump ; 3 (2 jump src) |
|
t_c_r lapc.d |
|
; The "quick operand" must be in range [. to .+15*2] so we can't |
; use t_c_r. |
t_S_x_y none lapcq .+4 r3 |
t_S_x_y none lapcq .+4 r8 |
|
t_dwbr_r lsl ; (3+3+3)*3 |
t_c_r lslq ; 3 |
|
t_dwbr_r lsr ; (3+3+3)*3 |
t_c_r lsrq ; 3 |
|
t_r_r lz ; 3+3 |
|
t_S_x_y none mcp srp r3 ; 3 |
t_S_x_y none mcp srp r8 |
|
t_c_r moveq |
|
t_S_x_y none move srp r8 |
t_S_x_y none move srp r3 |
t_S_x_y none move r8 srp |
t_S_x_y none move r3 srp ; 3 |
|
; FIXME: move supreg,Rd and move Rs,supreg when supported. |
|
t_wb movs ; (3+3)*2+0+(3+3)*2 (4 mem src) |
t_wb movu ; (3+3)*2+0+(3+3)*2 (4 mem src) |
|
t_dwbr_r muls ; (3+3+3)*3 (9 mul src) |
t_dwbr_r mulu ; (3+3+3)*3 (9 mul src) |
|
t_dwbr_r neg ; (3+3)*3 |
|
t_r not ; 3 cycles. |
|
t_dwb or ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) |
t_c_r orq ; 3 |
|
t_r seq |
|
t_dwb sub ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src) |
t_c_r subq ; 3 |
|
t_wb subs ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src) |
t_wb subu ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src) |
|
t_r swapw ; 3 cycles. |
t_r swapnwbr ; 3 cycles. |
|
t_r_j jsrc ; 3 (2 jump src) |
|
t_r_r xor ; (3+3+3) |
|
move.d 9b,r7 |
nop |
nop |
nop |
t_xm_r none movem ; (3+3) (2 mem src, 1+1 movem addr) |
; As implied by the comment, all movem destination penalty |
; cycles (but one) are accounted for as memory source address |
; and movem source penalties. There are also two movem address |
; cache-line straddle penalties. |
t_xr_m none movem ; (3+3+2+2) (2 mem, 6 movem src, +2 movem addr) |
|
break 15 |
/andc.ms
0,0 → 1,80
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 2\n2\nffff\nffffffff\n50124400\nffff0002\n2\nfffff\nfedaff0f\n78134400\nffffff02\n2\nf02\n78134401\n78134400\n |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
and.d 2,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
moveq 2,r3 |
and.d -1,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xffff,r3 |
and.d 0xffff,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
moveq -1,r3 |
and.d -1,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d 0x78134452,r3 |
and.d 0x5432f789,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 50124400 |
|
moveq -1,r3 |
and.w 2,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff0002 |
|
moveq 2,r3 |
and.w -1,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xfffff,r3 |
and.w 0xffff,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fffff |
|
move.d 0xfedaffaf,r3 |
and.w 0xff5f,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fedaff0f |
|
move.d 0x78134452,r3 |
and.w 0xf789,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 78134400 |
|
moveq -1,r3 |
and.b 2,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffffff02 |
|
moveq 2,r3 |
and.b -1,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xfa7,r3 |
and.b 0x5a,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; f02 |
|
move.d 0x78134453,r3 |
and.b 0x89,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 78134401 |
|
and.b 0,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 78134400 |
|
quit |
/moverm.ms
0,0 → 1,45
# mach: crisv3 crisv8 crisv10 crisv32 |
# output: 7823fec2\n10231879\n102318fe\n |
|
.include "testutils.inc" |
start |
|
.data |
mem1: |
.dword 0x12345678 |
mem2: |
.word 0x4567 |
mem3: |
.byte 0x23 |
.dword 0x76543210 |
.byte 0xaa,0x11,0x99 |
|
.text |
move.d mem1,r2 |
move.d 0x7823fec2,r4 |
setf nzvc |
move.d r4,[r2+] |
test_cc 1 1 1 1 |
subq 4,r2 |
move.d [r2],r3 |
dumpr3 ; 7823fec2 |
|
move.d mem2,r3 |
move.d 0x45231879,r4 |
clearf nzvc |
move.w r4,[r3] |
test_cc 0 0 0 0 |
move.d [r3],r3 |
dumpr3 ; 10231879 |
|
move.d mem2,r2 |
moveq -2,r4 |
clearf nc |
setf zv |
move.b r4,[r2+] |
test_cc 0 1 1 0 |
subq 1,r2 |
move.d [r2],r3 |
dumpr3 ; 102318ff |
|
quit |
/jumpmp.ms
0,0 → 1,21
# mach: crisv3 crisv8 crisv10 |
# output: bed0bed1\n |
|
# Test that jump indirect clears the "prefixed" |
# bit. |
|
.include "testutils.inc" |
.data |
w: |
.dword x1 |
y: |
.dword 0xbed0bed1 |
|
start |
x: |
move.d y,r3 |
jump [w] |
x1: |
move.d [r3],r3 |
dumpr3 ; bed0bed1 |
quit |
/addq.ms
0,0 → 1,47
# mach: crisv3 crisv8 crisv10 crisv32 |
# output: ffffffff\n0\n1\n100\n10000\n47\n67\na6\n80000001\n |
|
.include "testutils.inc" |
start |
moveq -2,r3 |
addq 1,r3 |
test_cc 1 0 0 0 |
dumpr3 |
|
addq 1,r3 |
test_cc 0 1 0 1 |
dumpr3 |
|
addq 1,r3 |
test_cc 0 0 0 0 |
dumpr3 |
|
move.d 0xff,r3 |
addq 1,r3 |
test_cc 0 0 0 0 |
dumpr3 |
|
move.d 0xffff,r3 |
addq 1,r3 |
test_cc 0 0 0 0 |
dumpr3 |
|
move.d 0x42,r3 |
addq 5,r3 |
test_cc 0 0 0 0 |
dumpr3 |
|
addq 32,r3 |
test_cc 0 0 0 0 |
dumpr3 |
|
addq 63,r3 |
test_cc 0 0 0 0 |
dumpr3 |
|
move.d 0x7ffffffe,r3 |
addq 3,r3 |
test_cc 1 0 1 0 |
dumpr3 |
|
quit |
/tjmpsrv32.ms
0,0 → 1,50
#mach: crisv32 |
#output: Basic clock cycles, total @: 17\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 5\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
|
; Check that "ret"-type insns get the right number of penalty |
; cycles for the special register source. |
|
.include "testutils.inc" |
startnostack |
move.d 1f,$r1 |
move.d 0f,$r0 |
move $r0,$mof |
jump $mof ; 2 cycles penalty. |
nop |
|
0: |
move [$r1],$srp |
nop |
ret ; 1 cycle penalty. |
nop |
|
break 15 |
|
0: |
move 2f,$nrp |
nop |
nop |
jump $nrp ; no penalty. |
nop |
|
break 15 |
|
2: |
move 3f,$srp ; 2 cycles penalty. |
ret |
nop |
|
3: |
break 15 |
1: |
.dword 0b |
/boundc.ms
0,0 → 1,101
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 2\n2\nffff\nffffffff\n5432f789\n2\nffff\n2\nffff\nffff\nf789\n2\n2\nff\nff\nff\n89\n0\nff\n |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
moveq 2,r4 |
bound.d 2,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
moveq 2,r3 |
bound.d 0xffffffff,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xffff,r3 |
bound.d 0xffff,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
moveq -1,r3 |
bound.d 0xffffffff,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d 0x78134452,r3 |
bound.d 0x5432f789,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 5432f789 |
|
moveq -1,r3 |
bound.w 2,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
moveq -1,r3 |
bound.w 0xffff,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
moveq 2,r3 |
bound.w 0xffff,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xffff,r3 |
bound.w 0xffff,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
move.d 0xfedaffff,r3 |
bound.w 0xffff,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
move.d 0x78134452,r3 |
bound.w 0xf789,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; f789 |
|
moveq -1,r3 |
bound.b 2,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
moveq 2,r3 |
bound.b 0xff,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
moveq -1,r3 |
bound.b 0xff,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ff |
|
move.d 0xff,r3 |
bound.b 0xff,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ff |
|
move.d 0xfeda49ff,r3 |
bound.b 0xff,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ff |
|
move.d 0x78134452,r3 |
bound.b 0x89,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 89 |
|
bound.w 0,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0xffff,r3 |
bound.b -1,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ff |
|
quit |
/nopv32t.ms
0,0 → 1,21
#mach: crisv32 |
#output: Basic clock cycles, total @: 5\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
.include "testutils.inc" |
.global _start |
_start: |
nop |
nop |
nop |
nop |
nop |
break 15 |
/biap.ms
0,0 → 1,56
# mach: crisv0 crisv3 crisv8 crisv10 |
# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n |
|
.include "testutils.inc" |
.data |
x: |
.dword 0x55aa77ff |
.dword 0xccff2244 |
.dword 0x88ccee19 |
|
start |
moveq -1,r0 |
move.d x-32768,r5 |
move.d 32769,r6 |
move.d [r5+r6.b],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 4455aa77 |
|
addu.w 32771,r5 |
moveq -1,r8 |
move.d [r11=r5+r8.w],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 4455aa77 |
|
moveq 5,r10 |
move.d [r11+r10.b],r3 |
test_cc 1 0 0 0 |
dumpr3 ; ee19ccff |
|
subq 1,r5 |
move.d r5,r8 |
subq 1,r8 |
moveq 1,r9 |
movu.w [r12=r8+r9.d],r3 |
test_cc 0 0 0 0 |
dumpr3 ; ff22 |
|
moveq -2,r11 |
move.d [r13=r12+r11.w],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 4455aa77 |
|
subq 18,r13 |
moveq 5,r9 |
move.d [r13+r9.d],r3 |
test_cc 1 0 0 0 |
dumpr3 ; ff224455 |
|
move.d r5,r7 |
add.d 76789886,r7 |
move.d -76789888/4,r12 |
move.d [r7+r12.d],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 55aa77ff |
|
quit |
/raw3.ms
0,0 → 1,22
; Checking read-after-write: read-then-write unaffected. |
#mach: crisv32 |
#output: Basic clock cycles, total @: 4\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
.include "testutils.inc" |
startnostack |
.lcomm x,4 |
.lcomm y,4 |
move.d x,$r0 |
move.d y,$r1 |
move.d [$r0],$r2 |
move.d $r0,[$r1] |
break 15 |
/dip.ms
0,0 → 1,41
# mach: crisv0 crisv3 crisv8 crisv10 |
# output: 4455aa77\nee19ccff\nb232765a\nff22\n5a88ccee\n |
|
.include "testutils.inc" |
.data |
x: |
.dword 0x55aa77ff |
.dword 0xccff2244 |
.dword 0x88ccee19 |
.dword 0xb232765a |
y: |
.dword x+12 |
.dword x+5 |
.dword x+9 |
|
start |
moveq -1,r0 |
moveq -1,r2 |
move.d [x+1],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 4455aa77 |
|
move.d [x+6],r3 |
test_cc 1 0 0 0 |
dumpr3 ; ee19ccff |
|
move.d y,r8 |
move.d [[r8+]],r3 |
test_cc 1 0 0 0 |
dumpr3 ; b232765a |
|
movu.w [[r8]],r3 |
test_cc 0 0 0 0 |
dumpr3 ; ff22 |
addq 4,r8 |
|
move.d [[r8]],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 5a88ccee |
|
quit |
/tjsrcv32.ms
0,0 → 1,13
#mach: crisv32 |
#output: Basic clock cycles, total @: 6\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 2\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
.include "tjsrcv10.ms" |
/bdapm.ms
0,0 → 1,56
# mach: crisv0 crisv3 crisv8 crisv10 |
# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n |
|
.include "testutils.inc" |
.data |
x: |
.dword 0x55aa77ff |
.dword 0xccff2244 |
.dword 0x88ccee19 |
y: |
.dword 32769 |
.word -1 |
.dword 5 |
.byte 3,-4 |
.word 2 |
.dword -76789887 |
|
start |
moveq -1,r0 |
move.d x-32768,r5 |
move.d y,r13 |
bdap.d [r13+],r5 |
move.d [r3],r9 |
test_move_cc 0 0 0 0 |
dumpr3 ; 4455aa77 |
|
addu.w 32770,r5 |
bdap.w [r13+],r5 |
move.d [r9+],r3 |
dumpr3 ; 4455aa77 |
|
bdap.d [r13],r9 |
move.d [r3],r7 |
addq 4,r13 |
dumpr3 ; ee19ccff |
|
bdap.b [r13+],r5 |
movu.w [r7+],r3 |
dumpr3 ; ff22 |
|
bdap.b [r13],r7 |
move.d [r7+],r3 |
addq 1,r13 |
dumpr3 ; 4455aa77 |
|
bdap.w [r13],r7 |
move.d [r3],r3 |
addq 2,r13 |
dumpr3 ; ff224455 |
|
add.d 76789885,r5 |
bdap.d [r13+],r5 |
move.d [r3],r9 |
dumpr3 ; 55aa77ff |
|
quit |
/addswpc.ms
0,0 → 1,61
# mach: crisv3 crisv8 crisv10 |
# output: 7\n |
|
# Test that the special case adds.w [pc+rN.w],pc works. |
|
.include "testutils.inc" |
start |
x: |
moveq 0,r3 |
ba xy |
moveq 5,r2 |
|
ok: |
moveq 7,r3 |
dumpr3 |
quit |
|
xy: |
adds.w [pc+r2.w],pc |
y: |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word ok-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
.word x0-y |
x0: |
quit |
/clearfv32.ms
0,0 → 1,12
# mach: crisv32 |
# output: ef\n |
|
; Check that "clearf x" doesn't trivially fail. |
|
.include "testutils.inc" |
start |
setf puixnzvc |
clearf x ; Actually, x would be cleared by almost-all other insns. |
move ccs,r3 |
dumpr3 |
quit |
/addoq.ms
0,0 → 1,31
# mach: crisv32 |
# output: ccff2244\n88ccee19\n55aa77ff\n19cc\n |
|
.include "testutils.inc" |
.data |
x: |
.dword 0x55aa77ff |
.dword 0xccff2244 |
.dword 0x88ccee19 |
start |
moveq -1,r0 |
move.d x+4,r5 |
setf zvnc |
addoq 0,r5,acr |
test_cc 1 1 1 1 |
move.d [acr],r3 |
dumpr3 ; ccff2244 |
setf zvnc |
addoq 4,r5,acr |
test_cc 1 1 1 1 |
move.d [acr],r3 |
dumpr3 ; 88ccee19 |
clearf zvnc |
addoq -8,acr,acr |
test_cc 0 0 0 0 |
move.d [acr],r3 |
dumpr3 ; 55aa77ff |
addoq 3,r5,acr |
movu.w [acr],r3 |
dumpr3 ; 19cc |
quit |
/io3.ms
0,0 → 1,17
# mach: crisv32 |
# sim: --cris-900000xx |
# output: ce11d0c\n |
|
; Check correct "pass" exit. |
|
.include "testutils.inc" |
start |
move.d 0x0ce11d0c,$r3 |
dumpr3 |
move.d 0x90000004,$acr |
move.d $acr,[$acr] |
move.d 0xbadc0de,$r3 |
dumpr3 |
0: |
ba 0b |
nop |
/sbfs.ms
0,0 → 1,7
# mach: crisv10 |
# xerror: |
# output: SBFS isn't implemented\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
sbfs [r10] |
/addxm.ms
0,0 → 1,106
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 1\n1\n101\n10001\n100fe\n1fffe\nfffe\nfffe\nfffffffe\nfe\nfffffffe\n781344db\n781343db\n78143bdb\n78133bdb\n800000ed\n0\n |
|
.include "testutils.inc" |
.data |
x: |
.byte 0xff |
.word 0xffff |
.word 0xff |
.word 0xffff |
.byte 0x89 |
.word 0xf789 |
.byte 0xff |
.word 0xffff |
|
start |
moveq 2,r3 |
move.d x,r5 |
adds.b [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1 |
|
moveq 2,r3 |
adds.w [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1 |
|
moveq 2,r3 |
subq 3,r5 |
addu.b [r5+],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 101 |
|
moveq 2,r3 |
addu.w [r5+],r3 |
subq 3,r5 |
test_cc 0 0 0 0 |
dumpr3 ; 10001 |
|
move.d 0xffff,r3 |
addu.b [r5],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 100fe |
|
move.d 0xffff,r3 |
addu.w [r5],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1fffe |
|
move.d 0xffff,r3 |
adds.b [r5],r3 |
test_cc 0 0 0 1 |
dumpr3 ; fffe |
|
move.d 0xffff,r3 |
adds.w [r5],r3 |
test_cc 0 0 0 1 |
dumpr3 ; fffe |
|
moveq -1,r3 |
adds.b [r5],r3 |
test_cc 1 0 0 1 |
addq 3,r5 |
dumpr3 ; fffffffe |
|
moveq -1,r3 |
adds.w [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; fe |
|
moveq -1,r3 |
adds.w [r5+],r3 |
test_cc 1 0 0 1 |
dumpr3 ; fffffffe |
|
move.d 0x78134452,r3 |
addu.b [r5],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 781344db |
|
move.d 0x78134452,r3 |
adds.b [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 781343db |
|
move.d 0x78134452,r3 |
addu.w [r5],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 78143bdb |
|
move.d 0x78134452,r3 |
adds.w [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 78133bdb |
|
move.d 0x7fffffee,r3 |
addu.b [r5+],r3 |
test_cc 1 0 1 0 |
dumpr3 ; 800000ed |
|
move.d 0x1,r3 |
adds.w [r5+],r3 |
test_cc 0 1 0 1 |
dumpr3 ; 0 |
|
quit |
/x3-v10.ms
0,0 → 1,12
#mach: crisv10 |
#ld: --section-start=.text=0 |
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n |
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: a 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 2\n |
#output: 12 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 1e 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 2\n |
#sim: --cris-trace=basic |
|
; With a "--cris-trace=all", cycles for the third line would be 3. |
|
.include "tjsrcv10.ms" |
/x1-v32.ms
0,0 → 1,8
#mach: crisv32 |
#ld: --section-start=.text=0 |
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n |
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: a 0 0 0 0 0 ff004567 0 0 0 0 0 0 0 0 * ixNzvc 1 0\n |
#sim: --cris-trace=basic |
|
.include "movect10.ms" |
/raw16.ms
0,0 → 1,14
; Checking read-after-write: cycles included in "unaligned". |
#mach: crisv32 |
#output: Clock cycles including stall cycles for unaligned accesses @: 4\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 2\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=unaligned |
.include "raw4.ms" |
/movpr.ms
0,0 → 1,28
# mach: crisv3 crisv8 crisv10 crisv32 |
# output: ffffff00\nffff0000\n0\nbb113344\n |
|
# Test generic "move Ps,Rd" and "move Rs,Pd" insns; the ones with |
# functionality common to all models. |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
clear.b r3 |
dumpr3 |
|
moveq -1,r3 |
clear.w r3 |
dumpr3 |
|
moveq -1,r3 |
clear.d r3 |
dumpr3 |
|
moveq -1,r3 |
move.d 0xbb113344,r4 |
setf zcvn |
move r4,srp |
move srp,r3 |
test_cc 1 1 1 1 |
dumpr3 |
quit |
/movppc.ms
0,0 → 1,7
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
move srp,[PC+] |
/pcplus.ms
0,0 → 1,46
# mach: crisv0 crisv3 crisv8 crisv10 |
|
; Test that a forward as well as backward 32-bit "branch" expansion |
; works including that the right offset is applied. |
|
.macro nop32 |
.rept 32 |
nop |
.endr |
.endm |
|
.include "testutils.inc" |
start |
jump start1 |
fail |
|
nop32 |
subq 63,$r10 |
9: subq 1,$r10 |
nop32 |
jump 0f |
|
fail |
0: move [$pc=$pc+1f-6-0b],$p0 |
nop32 |
fail |
|
.skip 32768,0 |
|
nop32 |
subq 63,$r10 |
1: |
subq 1,$r10 |
nop32 |
test.d $r10 |
bne 7f |
nop |
pass |
7: |
fail |
|
start1: |
moveq 2,$r10 |
0: move [$pc=$pc+9b-6-0b],$p0 |
subq 63,$r10 |
fail |
/addcv32r.ms
0,0 → 1,57
# mach: crisv32 |
# output: 0\n0\n1\n1\n2\n1ffff\nfffffffe\ncc463bdc\n |
|
.include "testutils.inc" |
start |
clearf cz |
moveq 0,r3 |
moveq 0,r4 |
addc r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 0 |
|
setf z |
moveq 0,r3 |
moveq 0,r4 |
addc r4,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 0 |
|
setf cz |
moveq 0,r3 |
moveq 0,r4 |
addc r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
|
moveq -1,r3 |
moveq 2,r4 |
addc r4,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1+c |
|
moveq 2,r3 |
moveq -1,r4 |
addc r4,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 2+c |
|
move.d 0xffff,r4 |
move.d r4,r3 |
addc r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1ffff |
|
moveq -1,r4 |
move.d r4,r3 |
addc r4,r3 |
test_cc 1 0 0 1 |
dumpr3 ; fffffffe+c |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
addc r4,r3 |
test_cc 1 0 1 0 |
dumpr3 ; cc463bdc |
|
quit |
/movscr.ms
0,0 → 1,29
# mach: crisv3 crisv8 crisv10 crisv32 |
# output: 42\nffffff85\n7685\nffff8765\n0\n |
|
; Move constant byte, word, dword to register. Check that sign-extension |
; is performed. |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
movs.b 0x42,r3 |
dumpr3 |
|
movs.b 0x85,r3 |
test_move_cc 1 0 0 0 |
dumpr3 |
|
movs.w 0x7685,r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
movs.w 0x8765,r3 |
test_move_cc 1 0 0 0 |
dumpr3 |
|
movs.w 0,r3 |
test_move_cc 0 1 0 0 |
dumpr3 |
|
quit |
/moveqpc.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
startnostack |
setf |
moveq -30,pc |
quit |
/ccr-v10.ms
0,0 → 1,79
# mach: crisv10 |
# output: ff\nff\n0\n0\n80\n40\n20\n10\n8\n4\n2\n1\n80\n40\n20\n10\n8\n4\n2\n1\n42\n |
|
; Check that flag settings affect ccr and dccr and vice versa. |
|
.include "testutils.inc" |
start |
clear.d r3 |
setf mbixnzvc |
move ccr,r3 |
dumpr3 |
|
clear.d r3 |
setf mbixnzvc |
move dccr,r3 |
dumpr3 |
|
clear.d r3 |
clearf mbixnzvc |
move ccr,r3 |
dumpr3 |
|
clear.d r3 |
clearf mbixnzvc |
move dccr,r3 |
dumpr3 |
|
.macro testfr BIT REG |
clear.d r3 |
clearf mbixnzvc |
setf \BIT |
move \REG,r3 |
dumpr3 |
.endm |
|
testfr m ccr |
testfr b ccr |
testfr i ccr |
testfr x ccr |
testfr n ccr |
testfr z ccr |
testfr v ccr |
testfr c ccr |
|
testfr m dccr |
testfr b dccr |
testfr i dccr |
testfr x dccr |
testfr n dccr |
testfr z dccr |
testfr v dccr |
testfr c dccr |
|
; Check only the nzvc bits; do the other bits in special tests as they're |
; implemented. |
.macro test_get_cc N Z V C |
clearf znvc |
move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),ccr |
test_cc \N \Z \V \C |
setf znvc |
move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),dccr |
test_cc \N \Z \V \C |
move.d ((\N << 3)|(\Z << 2)|(\V << 1)|\C),r4 |
setf znvc |
move r4,ccr |
test_cc \N \Z \V \C |
clearf znvc |
move r4,dccr |
test_cc \N \Z \V \C |
.endm |
|
test_get_cc 1 0 0 0 |
test_get_cc 0 1 0 0 |
test_get_cc 0 0 1 0 |
test_get_cc 0 0 0 1 |
|
move.d 0x42,r3 |
dumpr3 |
quit |
/rfe.ms
0,0 → 1,47
# mach: crisv32 |
# output: 4000c3af\n40000020\n40000080\n40000000\n |
|
; Check that RFE affects CCS the right way. |
|
.include "testutils.inc" |
start |
|
; Set SPC to 1 to disable single step exceptions when S flag is set. |
move 1,spc |
|
; CCS: |
; 31 24 23 16 15 8 7 0 |
; +---+-----------+-------+-------+-----------+---+---------------+ |
; |Q M|S R P U I X N Z V C|S R P U I X N Z V C|S R P U I X N Z V C| |
; | |2 2 2 2 2 2 2 2 2 2|1 1 1 1 1 1 1 1 1 1| | |
; +---+-----------+-------+-------+-----------+---+---------------+ |
|
; Clear S R P U I X N Z V C, set S1 R1 P1 (not U1) I1 X1 N1 Z1 V1 C1, |
; clear S2 R2 P2 U2 N2 Z2 V2 C2, Q; set I2 X2 M: |
; 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 |
move 0x430efc00,ccs |
|
test_cc 0 0 0 0 |
|
rfe |
test_cc 1 1 1 1 |
move ccs,r3 |
dumpr3 ; 0x4000c3af |
|
rfe |
test_cc 0 0 0 0 |
move ccs,r3 |
dumpr3 ; 0x40000020 |
|
rfe |
test_cc 0 0 0 0 |
move ccs,r3 |
dumpr3 ; 0x40000080 |
|
or.w 0x100,r3 |
move $r3,ccs |
rfe |
move ccs,r3 |
dumpr3 ; 0x40000000 |
|
quit |
/raw6.ms
0,0 → 1,24
; Checking read-after-write: write-then-nop-nop-read unaffected. |
#mach: crisv32 |
#output: Basic clock cycles, total @: 6\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
.include "testutils.inc" |
startnostack |
.lcomm x,4 |
.lcomm y,4 |
move.d x,$r0 |
move.d y,$r1 |
move.d $r1,[$r0] |
nop |
nop |
move.d [$r1],$r2 |
break 15 |
/lapc.ms
0,0 → 1,78
# mach: crisv32 |
# output: 0\n0\nfffffffa\nfffffffe\nffffffda\n1e\n1e\n0\n |
|
.include "testutils.inc" |
|
; To accommodate dumpr3 with more than one instruction, keep it |
; out of lapc operand ranges and difference calculations. |
|
start |
lapc.d 0f,r3 |
0: |
sub.d .,r3 |
dumpr3 ; 0 |
|
lapcq 0f,r3 |
0: |
sub.d .,r3 |
dumpr3 ; 0 |
|
lapc.d .,r3 |
sub.d .,r3 |
dumpr3 ; fffffffa |
|
lapcq .,r3 |
sub.d .,r3 |
dumpr3 ; fffffffe |
|
0: |
.rept 16 |
nop |
.endr |
lapc.d 0b,r3 |
sub.d .,r3 |
dumpr3 ; ffffffda |
|
setf zcvn |
lapc.d 0f,r3 |
test_cc 1 1 1 1 |
sub.d .,r3 |
nop |
nop |
nop |
nop |
nop |
nop |
nop |
nop |
nop |
nop |
nop |
nop |
0: |
dumpr3 ; 1e |
0: |
lapcq 0f,r3 |
sub.d 0b,r3 |
nop |
nop |
nop |
nop |
nop |
nop |
nop |
nop |
nop |
nop |
nop |
0: |
dumpr3 ; 1e |
clearf cn |
setf zv |
1: |
lapcq .,r3 |
test_cc 0 1 1 0 |
sub.d 1b,r3 |
dumpr3 ; 0 |
|
quit |
/movei.ms
0,0 → 1,47
# mach: crisv32 |
# output: fffffffe\n |
# output: fffffffe\n |
|
; Check basic integral-write semantics regarding flags. |
|
.include "testutils.inc" |
start |
|
; A write that works. Check that flags are set correspondingly. |
move.d d,r4 |
moveq -2,r5 |
setf c |
clearf p |
move.d [r4],r3 |
ax |
move.d r5,[r4] |
move.d [r4],r3 |
|
bcc 0f |
nop |
fail |
|
0: |
dumpr3 ; fffffffe |
|
; A write that fails; check flags too. |
move.d d,r4 |
moveq 23,r5 |
setf p |
clearf c |
move.d [r4],r3 |
ax |
move.d r5,[r4] |
move.d [r4],r3 |
|
bcs 0f |
nop |
fail |
|
0: |
dumpr3 ; fffffffe |
quit |
|
.data |
d: |
.dword 42424242 |
/moverpcd.ms
0,0 → 1,13
# mach: crisv3 crisv8 crisv10 |
# output: 4\n |
|
# Test that move.d pc,R works. |
|
.include "testutils.inc" |
start |
x: |
move.d pc,r3 |
y: |
sub.d y-4,r3 |
dumpr3 |
quit |
/cmpxm.ms
0,0 → 1,106
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 2\n2\n2\n2\nffff\nffff\nffff\nffff\nffffffff\nffffffff\nffffffff\n78134452\n78134452\n78134452\n78134452\n4452\n80000032\n |
|
.include "testutils.inc" |
.data |
x: |
.byte 0xff |
.word 0xffff |
.word 0xff |
.word 0xffff |
.byte 0x89 |
.word 0xf789 |
.word 0x8002 |
.word 0x764 |
|
start |
moveq 2,r3 |
move.d x,r5 |
cmps.b [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 2 |
|
moveq 2,r3 |
cmps.w [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 2 |
|
moveq 2,r3 |
subq 3,r5 |
cmpu.b [r5+],r3 |
test_cc 1 0 0 1 |
dumpr3 ; 2 |
|
moveq 2,r3 |
cmpu.w [r5+],r3 |
test_cc 1 0 0 1 |
subq 3,r5 |
dumpr3 ; 2 |
|
move.d 0xffff,r3 |
cmpu.b [r5],r3 |
test_cc 0 0 0 0 |
dumpr3 ; ffff |
|
move.d 0xffff,r3 |
cmpu.w [r5],r3 |
test_cc 0 1 0 0 |
dumpr3 ; ffff |
|
move.d 0xffff,r3 |
cmps.b [r5],r3 |
test_cc 0 0 0 1 |
dumpr3 ; ffff |
|
move.d 0xffff,r3 |
cmps.w [r5],r3 |
test_cc 0 0 0 1 |
dumpr3 ; ffff |
|
moveq -1,r3 |
cmps.b [r5],r3 |
test_cc 0 1 0 0 |
addq 3,r5 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
cmps.w [r5+],r3 |
test_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
cmps.w [r5+],r3 |
test_cc 0 1 0 0 |
dumpr3 ; ffffffff |
|
move.d 0x78134452,r3 |
cmpu.b [r5],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 78134452 |
|
move.d 0x78134452,r3 |
cmps.b [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 78134452 |
|
move.d 0x78134452,r3 |
cmpu.w [r5],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 78134452 |
|
move.d 0x78134452,r3 |
cmps.w [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 78134452 |
|
move.d 0x4452,r3 |
cmps.w [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 4452 |
|
move.d 0x80000032,r3 |
cmpu.w [r5+],r3 |
test_cc 0 0 1 0 |
dumpr3 ; 80000032 |
|
quit |
/movsmpc.ms
0,0 → 1,8
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
move.d _start,r12 |
movs.w [r12],pc |
/moveq.ms
0,0 → 1,15
# mach: crisv3 crisv8 crisv10 crisv32 |
# sim: --trace-core=on |
# ld: --section-start=.text=0 |
# output: read-2 exec:0x00000002 -> 0x3262\nread-2 exec:0x00000004 -> 0xe93e\nffffffe2\nread-2 exec:0x00000006 -> 0x324d\nread-2 exec:0x00000008 -> 0xe93e\nd\nread-2 exec:0x0000000a -> 0xe93f\n |
|
; Output a positive and a negative number, set from moveq. |
|
.include "testutils.inc" |
startnostack |
moveq -30,r3 |
dumpr3 |
moveq 13,r3 |
dumpr3 |
quit |
|
/tmemv10.ms
0,0 → 1,27
#mach: crisv10 |
#output: Basic clock cycles, total @: 8\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
|
; Check that the memory indirection doesn't make the simulator barf. |
; Nothing deeper. |
|
.include "testutils.inc" |
startnostack |
move.d 0f,r5 |
move.d [r5],r4 |
move.d [r5+],r3 |
move.d [r5],r2 |
break 15 |
nop |
.p2align 2 |
0: |
.dword 1,2,3 |
/movssr.ms
0,0 → 1,8
# mach: crisv32 |
# xerror: |
# output: Read of support register is unimplemented\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
move S0,R3 |
|
/bare1.ms
0,0 → 1,24
# mach: crisv32 |
# ld: --section-start=.text=0 |
# output: 0\n0\n4\n42\n |
# sim: --cris-naked |
|
; Check that we don't get signs of an initialized environment |
; when --cris-naked. |
|
.include "testutils.inc" |
.text |
.global _start |
_start: |
nop |
nop |
start2: |
move.d $r10,$r3 |
dumpr3 |
move.d $sp,$r3 |
dumpr3 |
lapc start2,$r3 |
dumpr3 |
move.d 0x42,$r3 |
dumpr3 |
quit |
/raw11.ms
0,0 → 1,23
; Checking read-after-write: swrite-then-nop-read 2 cycles. |
#mach: crisv32 |
#output: Basic clock cycles, total @: 5\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 2\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
.include "testutils.inc" |
startnostack |
.lcomm x,4 |
.lcomm y,4 |
move.d x,$r0 |
move.d y,$r1 |
clear.d [$r0] |
nop |
move [$r1],$srp |
break 15 |
/option3.ms
0,0 → 1,7
#mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
#sim: --cris-cycles=foo |
#xerror: |
#output: Unknown option `--cris-cycles=foo'\n |
.include "testutils.inc" |
start |
fail |
/tmvrmv10.ms
0,0 → 1,40
#mach: crisv10 |
#output: Basic clock cycles, total @: 31\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
|
; Check that movem to memory basically looks ok cycle-wise. |
; Nothing deep. |
|
.include "testutils.inc" |
startnostack |
move.d 0f,r4 |
moveq 0,r0 |
moveq 1,r3 |
moveq 2,r1 |
moveq 1,r2 |
movem r3,[r4] ; 2 cycles penalty for v32 |
movem r3,[r4] ; 0 cycles penalty for v32 |
moveq 1,r3 |
nop |
movem r3,[r4] ; 1 cycle penalty for v32 |
moveq 1,r3 |
nop |
nop |
movem r3,[r4] ; 0 cycles penalty for v32 |
break 15 |
|
.data |
0: |
.dword 0 |
.dword 0 |
.dword 0 |
.dword 0 |
/msteppc2.ms
0,0 → 1,8
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register read of PC is not implemented.\n |
# output: program stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
mstep r2,pc |
/io6.ms
0,0 → 1,22
# mach: crisv32 |
# ld: --section-start=.text=0 |
# sim: --cris-900000xx |
# xerror: |
# output: b1e\n |
# output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n |
# output: program stopped with signal 11.\n |
|
; Check that invalid access to the simulator area is recognized. |
; "FAIL" area. |
|
.include "testutils.inc" |
start |
move.d 0xb1e,$r3 |
dumpr3 |
move.d 0x90000008,$acr |
clear.d [$acr] |
move.d 0xbadc0de,$r3 |
dumpr3 |
0: |
ba 0b |
nop |
/x2-v10.ms
0,0 → 1,59
#mach: crisv10 |
#ld: --section-start=.text=0 |
#sim: --cris-trace=basic |
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n |
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1\n |
#output: c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1\n |
#output: 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1\n |
#output: 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 16 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 18 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 1a 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 16 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 18 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 1a 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 16 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 18 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 1a 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 16 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 18 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 1a 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n |
#output: 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n |
#output: 1a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n |
#output: 1c ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n |
#output: 1e ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n |
#output: 20 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n |
#output: 22 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n |
#output: 26 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 2\n |
#output: 230 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n |
#output: 232 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n |
#output: 236 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 2\n |
#output: 440 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n |
#output: 442 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 446 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n |
#output: 650 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 654 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n |
#output: 442 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 446 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n |
#output: 650 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 654 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n |
#output: 442 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 446 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n |
#output: 650 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 654 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n |
#output: 442 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 446 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n |
#output: 650 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: 654 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n |
#output: 442 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n |
#output: 446 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 2\n |
#output: 650 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n |
#output: 654 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 2\n |
#output: 656 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n |
#output: 658 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n |
#output: 65a ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n |
.include "tb.ms" |
/nopv32t4.ms
0,0 → 1,13
#mach: crisv10 crisv32 |
#output: All accounted clock cycles, total @: 5\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=all |
.include "nopv32t.ms" |
/x0-v32.ms
0,0 → 1,7
#mach: crisv32 |
#ld: --section-start=.text=0 |
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[0-9a-f][0-9a-f][0-9a-f] ixnzvc 0 0\n |
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[0-9a-f][0-9a-f][0-9a-f] ixnzvc 1 0\n |
#sim: --cris-trace=basic |
|
.include "break.ms" |
/cmpq.ms
0,0 → 1,75
# mach: crisv3 crisv8 crisv10 crisv32 |
# output: 1\n1\n1\n1f\n1f\nffffffe1\nffffffe1\nffffffe0\n0\n0\nffffffff\nffffffff\n10000\n100\n5678900\n |
|
.include "testutils.inc" |
start |
moveq 1,r3 |
cmpq 1,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 1 |
|
cmpq -1,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1 |
|
cmpq 31,r3 |
test_cc 1 0 0 1 |
dumpr3 ; 1 |
|
moveq 31,r3 |
cmpq 31,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 1f |
|
cmpq -31,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1f |
|
movs.b -31,r3 |
cmpq -31,r3 |
test_cc 0 1 0 0 |
dumpr3 ; ffffffe1 |
|
cmpq -32,r3 |
test_cc 0 0 0 0 |
dumpr3 ; ffffffe1 |
|
movs.b -32,r3 |
cmpq -32,r3 |
test_cc 0 1 0 0 |
dumpr3 ; ffffffe0 |
|
moveq 0,r3 |
cmpq 1,r3 |
test_cc 1 0 0 1 |
dumpr3 ; 0 |
|
cmpq -32,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 0 |
|
moveq -1,r3 |
cmpq 1,r3 |
test_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
cmpq -1,r3 |
test_cc 0 1 0 0 |
dumpr3 ; ffffffff |
|
move.d 0x10000,r3 |
cmpq 1,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 10000 |
|
move.d 0x100,r3 |
cmpq 1,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 100 |
|
move.d 0x5678900,r3 |
cmpq 7,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 5678900 |
|
quit |
/orr.ms
0,0 → 1,84
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 3\n3\nffff\nffffffff\n7c33f7db\nffff0003\n3\nfedaffff\n7813f7db\n3\n3\nfeb\n781344db\n |
|
.include "testutils.inc" |
start |
moveq 1,r3 |
moveq 2,r4 |
or.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 3 |
|
moveq 2,r3 |
moveq 1,r4 |
or.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 3 |
|
move.d 0xff0f,r4 |
move.d 0xf0ff,r3 |
or.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
moveq -1,r4 |
move.d r4,r3 |
or.d r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
or.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 7c33f7db |
|
move.d 0xffff0001,r3 |
moveq 2,r4 |
or.w r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff0003 |
|
moveq 2,r3 |
move.d 0xffff0001,r4 |
or.w r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 3 |
|
move.d 0xfedaffaf,r3 |
move.d 0xffffff5f,r4 |
or.w r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fedaffff |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
or.w r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; 7813f7db |
|
moveq 1,r3 |
move.d 0xffffff02,r4 |
or.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 3 |
|
moveq 2,r3 |
moveq 1,r4 |
or.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 3 |
|
move.d 0x4a,r4 |
move.d 0xfa3,r3 |
or.b r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; feb |
|
move.d 0x5432f789,r4 |
move.d 0x78134453,r3 |
or.b r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; 781344db |
|
quit |
/addcv32m.ms
0,0 → 1,69
# mach: crisv32 |
# output: 0\n0\n1\n0\n1\n1\n2\n1ffff\nfffffffe\ncc463bdc\n |
|
.include "testutils.inc" |
.data |
x: |
.dword 0,0,2,-1,0xffff,-1,0x5432f789 |
|
start |
move.d x,r5 |
clearf cz |
moveq 0,r3 |
addc [r5],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 0 |
|
setf z |
moveq 0,r3 |
addc [r5],r3 |
test_cc 0 1 0 0 |
dumpr3 ; 0 |
|
setf c |
moveq 0,r3 |
addc [r5],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
|
clearf c |
moveq 0,r3 |
addc [r5+],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 0 |
|
setf c |
moveq 0,r3 |
addc [r5+],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
|
clearf c |
moveq -1,r3 |
addc [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1+c |
|
moveq 2,r3 |
addc [r5],r3 |
moveq 4,r6 |
addi r6.b,r5 |
test_cc 0 0 0 1 |
dumpr3 ; 2+c |
|
move.d 0xffff,r3 |
addc [r5+],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1ffff |
|
moveq -1,r3 |
addc [r5+],r3 |
test_cc 1 0 0 1 |
dumpr3 ; fffffffe+c |
|
move.d 0x78134452,r3 |
addc [r5+],r3 |
test_cc 1 0 1 0 |
dumpr3 ; cc463bdc |
|
quit |
/bdapc.ms
0,0 → 1,57
# mach: crisv0 crisv3 crisv8 crisv10 |
# output: 4455aa77\n4455aa77\nee19ccff\n88ccee19\nff22\n4455aa77\nff224455\n55aa77ff\n |
|
.include "testutils.inc" |
.data |
x: |
.dword 0x55aa77ff |
.dword 0xccff2244 |
.dword 0x88ccee19 |
.dword 0xb232765a |
|
start |
moveq -1,r0 |
moveq -1,r2 |
move.d x-32768,r5 |
move.d [r5+32769],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 4455aa77 |
|
addu.w 32770,r5 |
bdap.w -1,r5 |
move.d [r0],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 4455aa77 |
|
bdap.d 4,r5 |
move.d [r2+],r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ee19ccff |
|
bdap.b 2,r2 |
move.d [r3],r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; 88ccee19 |
|
bdap.b 3,r5 |
movu.w [r4+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ff22 |
|
bdap.b -4,r4 |
move.d [r6+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 4455aa77 |
|
bdap.w 2,r6 |
move.d [r3],r9 |
test_move_cc 1 0 0 0 |
dumpr3 ; ff224455 |
|
add.d 76789885,r5 |
bdap.d -76789887,r5 |
move.d [r3],r9 |
test_move_cc 0 0 0 0 |
dumpr3 ; 55aa77ff |
|
quit |
/raw1.ms
0,0 → 1,22
; Checking read-after-write: read-then-read unaffected. |
#mach: crisv32 |
#output: Basic clock cycles, total @: 4\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
.include "testutils.inc" |
startnostack |
.lcomm x,4 |
.lcomm y,4 |
move.d x,$r0 |
move.d y,$r1 |
move.d [$r0],$r2 |
move.d [$r1],$r4 |
break 15 |
/subq.ms
0,0 → 1,52
# mach: crisv3 crisv8 crisv10 crisv32 |
# output: 0\nffffffff\nfffffffe\nffff\nff\n56788f9\n56788d9\n567889a\n0\n7ffffffc\n |
|
.include "testutils.inc" |
start |
moveq 1,r3 |
subq 1,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 0 |
|
subq 1,r3 |
test_cc 1 0 0 1 |
dumpr3 ; ffffffff |
|
subq 1,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fffffffe |
|
move.d 0x10000,r3 |
subq 1,r3 |
test_cc 0 0 0 0 |
dumpr3 ; ffff |
|
move.d 0x100,r3 |
subq 1,r3 |
test_cc 0 0 0 0 |
dumpr3 ; ff |
|
move.d 0x5678900,r3 |
subq 7,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 56788f9 |
|
subq 32,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 56788d9 |
|
subq 63,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 567889a |
|
move.d 34,r3 |
subq 34,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0x80000024,r3 |
subq 40,r3 |
test_cc 0 0 1 0 |
dumpr3 ; 7ffffffc |
|
quit |
/tjsrcv10.ms
0,0 → 1,29
#mach: crisv10 |
#output: Basic clock cycles, total @: 6\n |
#output: Memory source stall cycles: 1\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
|
; Check that the 4-byte-skip doesn't make the simulator barf. |
; Nothing deeper. |
|
.include "testutils.inc" |
startnostack |
nop |
move.d 0f,r5 |
jsrc r5 |
nop |
.dword -1 |
0: |
jsrc 1f |
nop |
.dword -2 |
1: |
break 15 |
/tmulv32.ms
0,0 → 1,14
#mach: crisv32 |
#output: Basic clock cycles, total @: 6\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 2\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
|
.include "tmulv10.ms" |
/raw9.ms
0,0 → 1,27
; Checking read-after-write: movemwrite-then-nop-nop-read unaffected. |
#mach: crisv32 |
#ld: --section-start=.text=0 |
#output: Basic clock cycles, total @: 8\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 1\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
.include "testutils.inc" |
startnostack |
.lcomm x,4*11 |
.lcomm y,4 |
move.d x,$r0 |
move.d y,$r1 |
nop |
nop |
movem $r10,[$r0] |
nop |
nop |
move.d [$r1],$r2 |
break 15 |
/andq.ms
0,0 → 1,46
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 2\n2\nffff\nffffffff\n1f\nffffffe0\n78134452\n0\n |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
andq 2,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
moveq 2,r3 |
andq -1,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2 |
|
move.d 0xffff,r3 |
andq -1,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
moveq -1,r3 |
andq -1,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
andq 31,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1f |
|
moveq -1,r3 |
andq -32,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffe0 |
|
move.d 0x78134457,r3 |
andq -14,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 78134452 |
|
moveq 0,r3 |
andq -14,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
|
quit |
/addxc.ms
0,0 → 1,91
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 1\n1\n101\n10001\n100fe\n1fffe\nfffe\nfffe\nfffffffe\nfe\nfffffffe\n781344db\n781343db\n78143bdb\n78133bdb\n800000ed\n0\n |
|
.include "testutils.inc" |
start |
moveq 2,r3 |
adds.b 0xff,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1 |
|
moveq 2,r3 |
adds.w 0xffff,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1 |
|
moveq 2,r3 |
addu.b 0xff,r3 |
dumpr3 ; 101 |
|
moveq 2,r3 |
move.d 0xffffffff,r4 |
addu.w -1,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 10001 |
|
move.d 0xffff,r3 |
addu.b -1,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 100fe |
|
move.d 0xffff,r3 |
addu.w -1,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1fffe |
|
move.d 0xffff,r3 |
adds.b 0xff,r3 |
test_cc 0 0 0 1 |
dumpr3 ; fffe |
|
move.d 0xffff,r3 |
adds.w 0xffff,r3 |
test_cc 0 0 0 1 |
dumpr3 ; fffe |
|
moveq -1,r3 |
adds.b 0xff,r3 |
test_cc 1 0 0 1 |
dumpr3 ; fffffffe |
|
moveq -1,r3 |
adds.w 0xff,r3 |
test_cc 0 0 0 1 |
dumpr3 ; fe |
|
moveq -1,r3 |
adds.w 0xffff,r3 |
test_cc 1 0 0 1 |
dumpr3 ; fffffffe |
|
move.d 0x78134452,r3 |
addu.b 0x89,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 781344db |
|
move.d 0x78134452,r3 |
adds.b 0x89,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 781343db |
|
move.d 0x78134452,r3 |
addu.w 0xf789,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 78143bdb |
|
move.d 0x78134452,r3 |
adds.w 0xf789,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 78133bdb |
|
move.d 0x7fffffee,r3 |
addu.b 0xff,r3 |
test_cc 1 0 1 0 |
dumpr3 ; 800000ed |
|
move.d 0x1,r3 |
adds.w 0xffff,r3 |
test_cc 0 1 0 1 |
dumpr3 ; 0 |
|
quit |
/clearfv10.ms
0,0 → 1,12
# mach: crisv10 |
# output: ef\n |
|
; Check that "clearf x" doesn't trivially fail. |
|
.include "testutils.inc" |
start |
setf mbixnzvc |
clearf x ; Actually, x would be cleared by almost-all other insns. |
move dccr,r3 |
dumpr3 |
quit |
/io1.ms
0,0 → 1,8
# mach: crisv32 |
# sim: --cris-900000xx --memory-region 0x90000000,0x10 |
# xerror: |
# output: Seeing --cris-900000xx with memory defined there\n |
|
; Check that I/O region overlap is detected. |
|
.include "nopv32t.ms" |
/mulv32.ms
0,0 → 1,51
# mach: crisv32 |
# output: fffffffe\n |
# output: ffffffff\n |
# output: fffffffe\n |
# output: 1\n |
# output: fffffffe\n |
# output: ffffffff\n |
# output: fffffffe\n |
# output: 1\n |
|
; Check that carry is not modified on v32. |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
moveq 2,r4 |
setf c |
muls.d r4,r3 |
test_cc 1 0 0 1 |
dumpr3 ; fffffffe |
move mof,r3 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
moveq 2,r4 |
setf c |
mulu.d r4,r3 |
test_cc 0 0 1 1 |
dumpr3 ; fffffffe |
move mof,r3 |
dumpr3 ; 1 |
|
moveq -1,r3 |
moveq 2,r4 |
clearf c |
muls.d r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fffffffe |
move mof,r3 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
moveq 2,r4 |
clearf c |
mulu.d r4,r3 |
test_cc 0 0 1 0 |
dumpr3 ; fffffffe |
move mof,r3 |
dumpr3 ; 1 |
|
quit |
/movsrpc.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
setf |
movs.w r0,pc |
quit |
/ret.ms
0,0 → 1,25
# mach: crisv3 crisv8 crisv10 |
# output: 3\n |
|
# Test that ret works. |
|
.include "testutils.inc" |
start |
x: |
moveq 0,r3 |
jsr z |
w: |
quit |
y: |
addq 1,r3 |
dumpr3 |
quit |
|
z: |
addq 1,r3 |
move srp,r2 |
add.d y-w,r2 |
move r2,srp |
ret |
addq 1,r3 |
quit |
/movecr.ms
0,0 → 1,37
# mach: crisv3 crisv8 crisv10 crisv32 |
# output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n |
|
; Move constant byte, word, dword to register. Check that no extension is |
; performed, that only part of the register is set. |
|
.include "testutils.inc" |
startnostack |
moveq -1,r3 |
move.b 0x42,r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
moveq 0,r3 |
move.b 0x94,r3 |
test_move_cc 1 0 0 0 |
dumpr3 |
|
moveq -1,r3 |
move.w 0x4321,r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
moveq 0,r3 |
move.w 0x9234,r3 |
test_move_cc 1 0 0 0 |
dumpr3 |
|
move.d 0x76543210,r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
move.w 0,r3 |
test_move_cc 0 1 0 0 |
dumpr3 |
|
quit |
/movecpc.ms
0,0 → 1,19
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register * PC is not implemented.\nprogram stopped with signal 5.\n |
|
# We deliberately match both "read from" and "write to" above. |
|
.include "testutils.inc" |
startnostack |
moveq -1,r3 |
move.b 0x42,pc |
dumpr3 |
|
move.w 0x4321,pc |
dumpr3 |
|
move.d 0x76543210,pc |
dumpr3 |
|
quit |
/opterr1.ms
0,0 → 1,5
# mach: crisv3 crisv8 crisv10 crisv32 |
# xerror: |
# output: *: unrecognized option `--cris-stats=xyz'\n |
# sim: --cris-stats=xyz |
.include "nopv32t.ms" |
/x1-v10.ms
0,0 → 1,10
#mach: crisv10 |
#ld: --section-start=.text=0 |
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n |
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#output: a 0 0 0 0 0 ff004567 0 0 0 0 0 0 0 0 * ixNzvc 2\n |
#sim: --cris-trace=basic |
|
; With a "--cris-trace=all", cycles for the last line would be 3. |
|
.include "movect10.ms" |
/movepcd.ms
0,0 → 1,16
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register * PC is not implemented.\nprogram stopped with signal 5.\n |
|
# Both source and dest contain PC for "test.d r" (move.d r,r). Ideally, |
# the output message should say "read" of PC, but we allow PC as source in |
# a move.d r,R insn, so there's no logical way to get that, short of a |
# special pattern, which would be just too ugly. The output message says |
# "write", but let's match "read" too so we won't fail if things suddenly |
# improve. |
|
.include "testutils.inc" |
startnostack |
setf |
test.d pc |
quit |
/orm.ms
0,0 → 1,75
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 3\n3\nffff\nffffffff\n7c33f7db\nffff0003\n3\nfedaffff\n7813f7db\n3\n3\nfeb\n781344db\n |
|
.include "testutils.inc" |
.data |
x: |
.dword 2,1,0xff0f,-1,0x5432f789 |
.word 2,1,0xff5f,0xf789 |
.byte 2,1,0x4a,0x89 |
|
start |
moveq 1,r3 |
move.d x,r5 |
or.d [r5+],r3 |
dumpr3 ; 3 |
|
moveq 2,r3 |
or.d [r5],r3 |
addq 4,r5 |
dumpr3 ; 3 |
|
move.d 0xf0ff,r3 |
or.d [r5+],r3 |
dumpr3 ; ffff |
|
moveq -1,r3 |
or.d [r5+],r3 |
dumpr3 ; ffffffff |
|
move.d 0x78134452,r3 |
or.d [r5+],r3 |
dumpr3 ; 7c33f7db |
|
move.d 0xffff0001,r3 |
or.w [r5+],r3 |
dumpr3 ; ffff0003 |
|
moveq 2,r3 |
or.w [r5],r3 |
addq 2,r5 |
test_move_cc 0 0 0 0 |
dumpr3 ; 3 |
|
move.d 0xfedaffaf,r3 |
or.w [r5+],r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fedaffff |
|
move.d 0x78134452,r3 |
or.w [r5+],r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; 7813f7db |
|
moveq 1,r3 |
or.b [r5+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 3 |
|
moveq 2,r3 |
or.b [r5],r3 |
addq 1,r5 |
test_move_cc 0 0 0 0 |
dumpr3 ; 3 |
|
move.d 0xfa3,r3 |
or.b [r5+],r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; feb |
|
move.d 0x78134453,r3 |
or.b [r5],r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; 781344db |
|
quit |
/raw14.ms
0,0 → 1,14
; Checking read-after-write: cycles included in "schedulable". |
#mach: crisv32 |
#output: Schedulable clock cycles, total @: 6\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 2\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=schedulable |
.include "raw4.ms" |
/io9.ms
0,0 → 1,21
# mach: crisv32 |
# ld: --section-start=.text=0 |
# xerror: |
# output: ce11d0c\n |
# output: core: 4 byte write to unmapped address 0x90000004 at 0x16\n |
# output: program stopped with signal 11.\n |
|
; Check invalid access valid with --cris-900000xx. |
; "PASS" area. |
|
.include "testutils.inc" |
start |
move.d 0x0ce11d0c,$r3 |
dumpr3 |
move.d 0x90000004,$acr |
move.d $acr,[$acr] |
move.d 0xbadc0de,$r3 |
dumpr3 |
0: |
ba 0b |
nop |
/tmvmrv32.ms
0,0 → 1,14
#mach: crisv32 |
#output: Basic clock cycles, total @: 17\n |
#output: Memory source stall cycles: 1\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 10\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
|
.include "tmvmrv10.ms" |
/op3.ms
0,0 → 1,98
# mach: crisv0 crisv3 crisv8 crisv10 |
# output: ee19cd0b\nee197761\nccff2244\n55aa77ff\nffffaa77\naa\n4243ab11\n424377ab\nfdedaaf0\n4242dd68\n4242dd68\n40025567\n57eb77ff\n55aa77ff\n |
|
.include "testutils.inc" |
.data |
x: |
.dword 0x55aa77ff |
.dword 0xccff2244 |
.dword 0x88ccee19 |
|
start |
move.d x,r10 |
moveq 0,r3 |
moveq 12,r4 |
add.d [r10+6],r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; ee19cd0b |
|
move.d 0x1267,r7 |
subu.w [r10+2],r3,r8 |
test_cc 1 0 0 0 |
move.d r8,r3 |
dumpr3 ; ee197761 |
|
moveq 1,r8 |
bound.d [r10+r8.d],r3,r5 |
test_move_cc 1 0 0 0 |
move.d r5,r3 |
dumpr3 ; ccff2244 |
|
; Also applies to move insns. Bleah. |
moveq 0,r5 |
bdap 0,r10 |
move.d [r3],r5 |
test_move_cc 0 0 0 0 |
dumpr3 ; 55aa77ff |
|
moveq 0,r5 |
bdap 1,r10 |
movs.w [r3],r5 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffaa77 |
|
moveq 0,r5 |
bdap 2,r10 |
movu.b [r3],r5 |
test_move_cc 0 0 0 0 |
dumpr3 ; aa |
|
move.d 0x42435567,r8 |
bdap 2,r10 |
adds.w [r3],r8 |
test_cc 0 0 0 0 |
dumpr3 ; 4243ab11 |
|
move.d 0x42435567,r8 |
bdap 4,r10 |
addu.w [r3],r8 |
test_cc 0 0 0 0 |
dumpr3 ; 424377ab |
|
move.d 0x42435567,r8 |
bdap 1,r10 |
sub.d [r3],r8 |
test_cc 1 0 0 1 |
dumpr3 ; fdedaaf0 |
|
move.d 0x42435567,r8 |
bdap 0,r10 |
subs.w [r3],r8 |
test_cc 0 0 0 0 |
dumpr3 ; 4242dd68 |
|
move.d 0x42435567,r8 |
bdap 0,r10 |
subu.w [r3],r8 |
test_cc 0 0 0 0 |
dumpr3 ; 4242dd68 |
|
move.d 0x42435567,r8 |
bdap 0,r10 |
and.d [r3],r8 |
test_move_cc 0 0 0 0 |
dumpr3 ; 40025567 |
|
move.d 0x42435567,r8 |
bdap 0,r10 |
or.d [r3],r8 |
test_move_cc 0 0 0 0 |
dumpr3 ; 57eb77ff |
|
move.d 0xc2435567,r8 |
bdap 0,r10 |
bound.d [r3],r8 |
test_move_cc 0 0 0 0 |
dumpr3 ; 55aa77ff |
|
quit |
/moverpcw.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
startnostack |
setf |
move.w pc,r2 |
quit |
/jsrmv10.ms
0,0 → 1,40
# mach: crisv3 crisv8 crisv10 |
# output: 23\n |
|
# Test that jsr [] records the correct return-address. |
|
.include "testutils.inc" |
start |
x: |
moveq 0,r3 |
jsr [z] |
addq 1,r3 |
nop |
nop |
nop |
nop |
nop |
move.d w,r2 |
jsr [r2] |
addq 1,r3 |
nop |
nop |
nop |
nop |
nop |
dumpr3 ; 23 |
quit |
y: |
ret |
addq 1,r3 |
quit |
|
v: |
ret |
addq 32,r3 |
quit |
|
z: |
.dword y |
w: |
.dword v |
/subxr.ms
0,0 → 1,108
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 3\n3\nffffff03\nffff0003\nff00\n0\n10000\n10000\n0\nffffff00\n0\n781343c9\n781344c9\n78124cc9\n78134cc9\nc450\n7ffff8ce\n |
|
.include "testutils.inc" |
start |
moveq 2,r3 |
move.d 0xff,r4 |
subs.b r4,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 3 |
|
moveq 2,r3 |
move.d 0xffff,r4 |
subs.w r4,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 3 |
|
moveq 2,r3 |
move.d 0xffff,r4 |
subu.b r4,r3 |
test_cc 1 0 0 1 |
dumpr3 ; ffffff03 |
|
moveq 2,r3 |
move.d 0xffffffff,r4 |
subu.w r4,r3 |
test_cc 1 0 0 1 |
dumpr3 ; ffff0003 |
|
move.d 0xffff,r3 |
move.d 0xffffffff,r4 |
subu.b r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; ff00 |
|
move.d 0xffff,r3 |
move.d 0xffffffff,r4 |
subu.w r4,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0xffff,r3 |
move.d 0xff,r4 |
subs.b r4,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 10000 |
|
move.d 0xffff,r4 |
move.d r4,r3 |
subs.w r4,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 10000 |
|
moveq -1,r3 |
move.d 0xff,r4 |
subs.b r4,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 0 |
|
moveq -1,r3 |
move.d 0xff,r4 |
subs.w r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; ffffff00 |
|
moveq -1,r3 |
move.d 0xffff,r4 |
subs.w r4,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
subu.b r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 781343c9 |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
subs.b r4,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 781344c9 |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
subu.w r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 78124cc9 |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
subs.w r4,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 78134cc9 |
|
move.d 0x4452,r3 |
move.d 0x78568002,r4 |
subs.w r4,r3 |
test_cc 0 0 0 1 |
dumpr3 ; c450 |
|
move.d 0x80000032,r3 |
move.d 0xffff0764,r4 |
subu.w r4,r3 |
test_cc 0 0 1 0 |
dumpr3 ; 7ffff8ce |
|
quit |
/x9-v10.ms
0,0 → 1,23
#mach: crisv10 |
#ld: --section-start=.text=0 |
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n |
#output: 4 0 0 0 0 0 0 0 0 0 1 0 0 0 0 * ixnzvc 1\n |
#output: 10 0 0 0 0 0 0 0 0 0 1 0 0 0 0 * ixnzvc 4\n |
#output: 12 0 0 0 0 0 0 0 0 0 1 0 0 0 0 * ixnzvc 1\n |
#sim: --cris-trace=basic |
|
; Check that "adds.w [$pc+$r9.w],$pc" gets 4 cycles. |
|
.include "testutils.inc" |
startnostack |
moveq 1,r9 |
adds.w [$pc+$r9.w],$pc |
0: |
.word 1f-0b |
.word 2f-0b |
.word 1f-0b |
1: |
break 15 |
2: |
nop |
break 15 |
/movemr.ms
0,0 → 1,79
# mach: crisv3 crisv8 crisv10 crisv32 |
# output: 12345678\n10234567\n12345678\n12344567\n12344523\n76543210\nffffffaa\naa\n9911\nffff9911\n78\n56\n3456\n6712\n |
|
.include "testutils.inc" |
start |
|
.data |
mem1: |
.dword 0x12345678 |
mem2: |
.word 0x4567 |
mem3: |
.byte 0x23 |
.dword 0x76543210 |
.byte 0xaa,0x11,0x99 |
|
.text |
move.d mem1,r2 |
move.d [r2],r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
move.d mem2,r3 |
move.d [r3],r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
move.d mem1,r2 |
move.d [r2+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
move.w [r2+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
move.b [r2+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
move.d [r2+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
movs.b [r2],r3 |
test_move_cc 1 0 0 0 |
dumpr3 |
|
movu.b [r2+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
movu.w [r2],r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
movs.w [r2+],r3 |
test_move_cc 1 0 0 0 |
dumpr3 |
|
move.d mem1,r13 |
movs.b [r13+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
movu.b [r13],r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
movs.w [r13+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
movu.w [r13+],r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
quit |
|
/tb.ms
0,0 → 1,72
#mach: crisv32 |
#output: Basic clock cycles, total @: 54\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 18\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
|
; Check branch penalties. It is assumed that the taken-counters |
; in the bimodal branch-predictors start at 0, meaning two taken |
; branches are required for a branch to be predicted as taken |
; for each counter, from reset. None of these branches go |
; to the end of a cache-line and none map to the same counter. |
|
.include "testutils.inc" |
startnostack |
ba 0f ; No penalty: always-taken condition not "predicted". |
nop |
nop |
0: |
setf c |
bcs 0f ; Penalty 2 cycles. |
nop |
|
nop |
0: |
clearf c |
bcc 0f ; Penalty 2 cycles, though branch is a nop. |
moveq 4,r0 ; Execute 5 times: |
|
0: |
move.d r0,r0 |
bne 0b ; Mispredicted 3 out of 5 times: penalty 3*2 cycles. |
subq 1,r0 |
|
0: |
beq 0f ; Not taken; no penalty. |
nop |
|
nop |
0: |
|
; (Almost) same insns, but with 16-bit bCC insns. |
|
ba 0f ; No penalty: always-taken condition not "predicted". |
nop |
.space 520 |
0: |
setf c |
bcs 0f ; Penalty 2 cycles. |
nop |
|
.space 520 |
0: |
moveq 4,r0 ; Execute 5 times: |
0: |
ba 1f |
move.d r0,r0 ; Mispredicted 3 out of 5 times: |
.space 520 |
1: |
bne 0b ; Penalty 3*2 cycles. |
subq 1,r0 |
|
beq 0f ; Not taken; no penalty. |
nop |
0: |
break 15 |
/x7-v32.ms
0,0 → 1,19
#mach: crisv32 |
#ld: --section-start=.text=0 |
#sim: --cris-trace=basic |
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n |
#output: 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvc 1 aa424243\n |
#output: a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 55212121\n |
#output: c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 1\n |
#output: e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
|
; Check that trace with changing ACR works. |
|
.include "testutils.inc" |
startnostack |
move.d 0xaa424243,$acr |
lsrq 1,$acr |
moveq 1,$acr |
clear.d $acr |
break 15 |
nop |
/xor.ms
0,0 → 1,47
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 3\n3\nff0\n0\n2c21b3db\n0\nffffffff\n |
|
.include "testutils.inc" |
start |
moveq 1,r3 |
moveq 2,r4 |
xor r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 3 |
|
moveq 2,r3 |
moveq 1,r4 |
xor r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 3 |
|
move.d 0xff0f,r4 |
move.d 0xf0ff,r3 |
xor r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ff0 |
|
moveq -1,r4 |
move.d r4,r3 |
xor r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
xor r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2c21b3db |
|
moveq 0,r4 |
moveq 0,r3 |
xor r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0x7fffffff,r3 |
move.d 0x80000000,r4 |
xor r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
quit |
/tjmpsrv32-2.ms
0,0 → 1,55
#mach: crisv32 |
#output: Basic clock cycles, total @: 37\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 6\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
|
; Check that we correctly account for that a "jas N,Pn", |
; "jasc N,Pn", "bas N,Pn" and "basc N,Pn" sets the specific |
; special register and causes a pipeline hazard. The amount |
; of nops below is a bit inflated, in an attempt to make |
; errors more discernible. For special registers, we just |
; check SRP. |
|
.include "testutils.inc" |
startnostack |
move.d 0f,$r0 |
jsr 0f |
nop |
nop |
nop |
jsrc 0f |
nop |
.dword -1 |
nop |
nop |
jsr $r0 |
nop |
nop |
nop |
jsrc $r0 |
nop |
.dword -1 |
nop |
nop |
bsr 0f |
nop |
nop |
nop |
bsrc 0f |
nop |
.dword -1 |
nop |
nop |
break 15 |
|
0: |
ret ; 1 cycle penalty. |
nop |
/addr.ms
0,0 → 1,96
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
moveq 2,r4 |
add.d r4,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1 |
|
moveq 2,r3 |
moveq -1,r4 |
add.d r4,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1 |
|
move.d 0xffff,r4 |
move.d r4,r3 |
add.d r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1fffe |
|
moveq -1,r4 |
move.d r4,r3 |
add.d r4,r3 |
test_cc 1 0 0 1 |
dumpr3 ; fffffffe |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
add.d r4,r3 |
test_cc 1 0 1 0 |
dumpr3 ; cc463bdb |
|
moveq -1,r3 |
moveq 2,r4 |
add.w r4,r3 |
test_cc 0 0 0 1 |
dumpr3 ; ffff0001 |
|
moveq 2,r3 |
moveq -1,r4 |
add.w r4,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1 |
|
move.d 0xffff,r4 |
move.d r4,r3 |
add.w r4,r3 |
test_cc 1 0 0 1 |
dumpr3 ; fffe |
|
move.d 0xfedaffff,r4 |
move.d r4,r3 |
add.w r4,r3 |
test_cc 1 0 0 1 |
dumpr3 ; fedafffe |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
add.w r4,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 78133bdb |
|
moveq -1,r3 |
moveq 2,r4 |
add.b r4,r3 |
test_cc 0 0 0 1 |
dumpr3 ; ffffff01 |
|
moveq 2,r3 |
moveq -1,r4 |
add.b r4,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1 |
|
move.d 0xff,r4 |
move.d r4,r3 |
add.b r4,r3 |
test_cc 1 0 0 1 |
dumpr3 ; fe |
|
move.d 0xfeda49ff,r4 |
move.d r4,r3 |
add.b r4,r3 |
test_cc 1 0 0 1 |
dumpr3 ; feda49fe |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
add.b r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; 781344db |
|
quit |
/cmpxc.ms
0,0 → 1,92
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 2\n2\n2\n2\nffff\nffff\nffff\nffff\nffffffff\nffffffff\nffffffff\n78134452\n78134452\n78134452\n78134452\n4452\n80000032\n |
|
.include "testutils.inc" |
start |
moveq 2,r3 |
cmps.b 0xff,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 2 |
|
moveq 2,r3 |
cmps.w 0xffff,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 2 |
|
moveq 2,r3 |
cmpu.b 0xff,r3 |
test_cc 1 0 0 1 |
dumpr3 ; 2 |
|
moveq 2,r3 |
move.d 0xffffffff,r4 |
cmpu.w -1,r3 |
test_cc 1 0 0 1 |
dumpr3 ; 2 |
|
move.d 0xffff,r3 |
cmpu.b -1,r3 |
test_cc 0 0 0 0 |
dumpr3 ; ffff |
|
move.d 0xffff,r3 |
cmpu.w -1,r3 |
test_cc 0 1 0 0 |
dumpr3 ; ffff |
|
move.d 0xffff,r3 |
cmps.b 0xff,r3 |
test_cc 0 0 0 1 |
dumpr3 ; ffff |
|
move.d 0xffff,r3 |
cmps.w 0xffff,r3 |
test_cc 0 0 0 1 |
dumpr3 ; ffff |
|
moveq -1,r3 |
cmps.b 0xff,r3 |
test_cc 0 1 0 0 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
cmps.w 0xff,r3 |
test_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
cmps.w 0xffff,r3 |
test_cc 0 1 0 0 |
dumpr3 ; ffffffff |
|
move.d 0x78134452,r3 |
cmpu.b 0x89,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 78134452 |
|
move.d 0x78134452,r3 |
cmps.b 0x89,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 78134452 |
|
move.d 0x78134452,r3 |
cmpu.w 0xf789,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 78134452 |
|
move.d 0x78134452,r3 |
cmps.w 0xf789,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 78134452 |
|
move.d 0x4452,r3 |
cmps.w 0x8002,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 4452 |
|
move.d 0x80000032,r3 |
cmpu.w 0x764,r3 |
test_cc 0 0 1 0 |
dumpr3 ; 80000032 |
|
quit |
/movucr.ms
0,0 → 1,33
# mach: crisv3 crisv8 crisv10 crisv32 |
# output: 42\n85\n7685\n8765\n0\n |
|
; Move constant byte, word, dword to register. Check that zero-extension |
; is performed. |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
movu.b 0x42,r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
moveq -1,r3 |
movu.b 0x85,r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
moveq -1,r3 |
movu.w 0x7685,r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
moveq -1,r3 |
movu.w 0x8765,r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
movu.b 0,r3 |
test_move_cc 0 1 0 0 |
dumpr3 |
|
quit |
/movucpc.ms
0,0 → 1,10
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
movu.w 0x4321,pc |
dumpr3 |
|
quit |
/movdelsr1.ms
0,0 → 1,33
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: aa117acd\n |
# output: eeaabb42\n |
|
; Bug with move to special register in delay slot, due to |
; special flush-insn-cache simulator use. Ordinary move worked; |
; special register caused branch to fail. |
|
.include "testutils.inc" |
start |
move -1,srp |
|
move.d 0xaa117acd,r1 |
moveq 3,r9 |
cmpq 1,r9 |
bhi 0f |
move.d r1,r3 |
|
fail |
0: |
dumpr3 |
|
move.d 0xeeaabb42,r1 |
moveq 3,r9 |
cmpq 1,r9 |
bhi 0f |
move r1,srp |
|
fail |
0: |
move srp,r3 |
dumpr3 |
quit |
/moverpcb.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
startnostack |
setf |
move.b pc,r5 |
quit |
/raw4.ms
0,0 → 1,22
; Checking read-after-write: write-then-read 2 cycles. |
#mach: crisv32 |
#output: Basic clock cycles, total @: 4\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 2\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
.include "testutils.inc" |
startnostack |
.lcomm x,4 |
.lcomm y,4 |
move.d x,$r0 |
move.d y,$r1 |
move.d $r1,[$r0] |
move.d [$r1],$r2 |
break 15 |
/user.ms
0,0 → 1,75
# mach: crisv32 |
# output: 40\n40\n140\nabadefb0\n6543789c\n0\n0\n0\n0\n0\n0\n0\n0\n |
|
; Check for protected operations being NOP in user mode, for the |
; parts implemented in this simulator. |
|
.include "testutils.inc" |
start |
move 0,ccs |
move 0,usp |
move 0,pid |
move 0,srs |
move 0,ebp |
move 0,spc |
setf u |
|
; Flag settings, besides what's tested in rfn.ms, rfe.ms and |
; sfe.ms. |
setf i |
move ccs,r3 |
dumpr3 ; 0x40 |
|
clearf u |
move ccs,r3 |
dumpr3 ; 0x40 |
|
move 0xc0000300,ccs |
move ccs,r3 |
dumpr3 ; 0x140 |
|
; R14==USP |
move.d 0xabadefb0,r14 |
nop |
nop |
nop |
move usp,r3 |
dumpr3 ; 0xabadefb0 |
move 0x6543789c,usp |
nop |
nop |
nop |
move.d r14,r3 |
dumpr3 ; 0x6543789c |
|
; We can't go back to kernel mode, so we can't check that R14 in |
; kernel mode wasn't affected. |
|
; Moves to protected special registers. |
.macro testsr reg,val=-1 |
move \val,\reg |
; Registers shorter than dword will not affect the rest of the |
; general register when copied using a move insn. |
clear.d r3 |
; Three cycles are needed between move to protected register and |
; read from it, to avoid reading undefined contents due to |
; incomplete forwarding. |
nop |
nop |
move \reg,r3 |
dumpr3 |
moveq \val,r3 |
move r3,\reg |
clear.d r3 |
nop |
nop |
move \reg,r3 |
dumpr3 |
.endm |
|
testsr pid ; 0 0 |
testsr srs,3 ; 0 0 |
testsr ebp ; 0 0 |
testsr spc ; 0 0 |
|
quit |
/movecrt32.ms
0,0 → 1,14
#mach: crisv32 |
#output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n |
#output: Basic clock cycles, total @: 82\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
.include "movecr.ms" |
/lz.ms
0,0 → 1,52
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 0\n20\n0\n1\n1\n1a\n1f\n10\n1e\n |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
|
lz r3,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
|
moveq 0,r3 |
lz r3,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 20 |
|
move.d 0x80000000,r4 |
lz r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0x40000000,r4 |
lz r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1 |
|
move.d 0x7fffffff,r4 |
lz r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1 |
|
move.d 42,r3 |
lz r3,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1a |
|
moveq 1,r6 |
lz r6,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1f |
|
move.d 0xffff,r3 |
lz r3,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 10 |
|
moveq 2,r5 |
lz r5,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1e |
|
quit |
/mulx.ms
0,0 → 1,246
# mach: crisv10 crisv32 |
# output: fffffffe\nffffffff\nfffffffe\n1\nfffffffe\nffffffff\nfffffffe\n1\nfffe0001\n0\nfffe0001\n0\n1\n0\n1\nfffffffe\n193eade2\n277e3a49\n193eade2\n277e3a49\nfffffffe\nffffffff\n1fffe\n0\nfffffffe\nffffffff\n1fffe\n0\n1\n0\nfffe0001\n0\nfdbdade2\nffffffff\n420fade2\n0\nfffffffe\nffffffff\n1fe\n0\nfffffffe\nffffffff\n1fe\n0\n1\n0\nfe01\n0\n1\n0\nfe01\n0\nffffd9e2\nffffffff\n2be2\n0\n0\n0\n0\n0\n |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
moveq 2,r4 |
muls.d r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fffffffe |
move mof,r3 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
moveq 2,r4 |
mulu.d r4,r3 |
test_cc 0 0 1 0 |
dumpr3 ; fffffffe |
move mof,r3 |
dumpr3 ; 1 |
|
moveq 2,r3 |
moveq -1,r4 |
muls.d r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fffffffe |
move mof,r3 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
moveq -1,r4 |
mulu.d r4,r3 |
test_cc 0 0 1 0 |
dumpr3 ; fffffffe |
move mof,r3 |
dumpr3 ; 1 |
|
move.d 0xffff,r4 |
move.d r4,r3 |
muls.d r4,r3 |
test_cc 0 0 1 0 |
dumpr3 ; fffe0001 |
move mof,r3 |
dumpr3 ; 0 |
|
move.d 0xffff,r4 |
move.d r4,r3 |
mulu.d r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; fffe0001 |
move mof,r3 |
dumpr3 ; 0 |
|
moveq -1,r4 |
move.d r4,r3 |
muls.d r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
move mof,r3 |
dumpr3 ; 0 |
|
moveq -1,r4 |
move.d r4,r3 |
mulu.d r4,r3 |
test_cc 1 0 1 0 |
dumpr3 ; 1 |
move mof,r3 |
dumpr3 ; fffffffe |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
muls.d r4,r3 |
test_cc 0 0 1 0 |
dumpr3 ; 193eade2 |
move mof,r3 |
dumpr3 ; 277e3a49 |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
mulu.d r4,r3 |
test_cc 0 0 1 0 |
dumpr3 ; 193eade2 |
move mof,r3 |
dumpr3 ; 277e3a49 |
|
move.d 0xffff,r3 |
moveq 2,r4 |
muls.w r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fffffffe |
move mof,r3 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
moveq 2,r4 |
mulu.w r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1fffe |
move mof,r3 |
dumpr3 ; 0 |
|
moveq 2,r3 |
move.d 0xffff,r4 |
muls.w r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fffffffe |
move mof,r3 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
moveq -1,r4 |
mulu.w r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1fffe |
move mof,r3 |
dumpr3 ; 0 |
|
move.d 0xffff,r4 |
move.d r4,r3 |
muls.w r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
move mof,r3 |
dumpr3 ; 0 |
|
moveq -1,r4 |
move.d r4,r3 |
mulu.w r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; fffe0001 |
move mof,r3 |
dumpr3 ; 0 |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
muls.w r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fdbdade2 |
move mof,r3 |
dumpr3 ; ffffffff |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
mulu.w r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 420fade2 |
move mof,r3 |
dumpr3 ; 0 |
|
move.d 0xff,r3 |
moveq 2,r4 |
muls.b r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fffffffe |
move mof,r3 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
moveq 2,r4 |
mulu.b r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1fe |
move mof,r3 |
dumpr3 ; 0 |
|
moveq 2,r3 |
moveq -1,r4 |
muls.b r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fffffffe |
move mof,r3 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
moveq -1,r4 |
mulu.b r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1fe |
move mof,r3 |
dumpr3 ; 0 |
|
move.d 0xff,r4 |
move.d r4,r3 |
muls.b r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
move mof,r3 |
dumpr3 ; 0 |
|
moveq -1,r4 |
move.d r4,r3 |
mulu.b r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; fe01 |
move mof,r3 |
dumpr3 ; 0 |
|
move.d 0xfeda49ff,r4 |
move.d r4,r3 |
muls.b r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
move mof,r3 |
dumpr3 ; 0 |
|
move.d 0xfeda49ff,r4 |
move.d r4,r3 |
mulu.b r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; fe01 |
move mof,r3 |
dumpr3 ; 0 |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
muls.b r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; ffffd9e2 |
move mof,r3 |
dumpr3 ; ffffffff |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
mulu.b r4,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 2be2 |
move mof,r3 |
dumpr3 ; 0 |
|
moveq 0,r3 |
move.d 0xf87f4aeb,r4 |
muls.d r4,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 0 |
move mof,r3 |
dumpr3 ; 0 |
|
move.d 0xf87f4aeb,r3 |
moveq 0,r4 |
mulu.d r4,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 0 |
move mof,r3 |
dumpr3 ; 0 |
|
quit |
/addcv32c.ms
0,0 → 1,50
# mach: crisv32 |
# output: 0\n0\n1\n1\n2\n1ffff\nfffffffe\ncc463bdc\n |
|
.include "testutils.inc" |
start |
clearf cz |
moveq 0,r3 |
addc 0,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 0 |
|
setf z |
moveq 0,r3 |
addc 0,r3 |
test_cc 0 1 0 0 |
dumpr3 ; 0 |
|
setf cz |
moveq 0,r3 |
addc 0,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1 |
|
clearf c |
moveq -1,r3 |
addc 2,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1+c |
|
moveq 2,r3 |
addc -1,r3 |
test_cc 0 0 0 1 |
dumpr3 ; 2+c |
|
move.d 0xffff,r3 |
addc 0xffff,r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1ffff |
|
moveq -1,r3 |
addc -1,r3 |
test_cc 1 0 0 1 |
dumpr3 ; fffffffe+c |
|
move.d 0x78134452,r3 |
addc 0x5432f789,r3 |
test_cc 1 0 1 0 |
dumpr3 ; cc463bdc |
|
quit |
/option1.ms
0,0 → 1,7
#mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
#sim: --cris-trace=foo |
#xerror: |
#output: Unknown option `--cris-trace=foo'\n |
.include "testutils.inc" |
start |
fail |
/io4.ms
0,0 → 1,18
# mach: crisv32 |
# xerror: |
# output: b1e\n |
|
; Check correct "fail" exit. |
|
.include "testutils.inc" |
start |
move.d 0xb1e,$r3 |
dumpr3 |
moveq 1,$r9 |
moveq 2,$r10 |
break 13 |
move.d 0xbadc0de,$r3 |
dumpr3 |
0: |
ba 0b |
nop |
/x0-v10.ms
0,0 → 1,7
#mach: crisv10 |
#ld: --section-start=.text=0 |
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[0-9a-f][0-9a-f][0-9a-f] ixnzvc 0\n |
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[0-9a-f][0-9a-f][0-9a-f] ixnzvc 1\n |
#sim: --cris-trace=basic |
|
.include "break.ms" |
/addqpc.ms
0,0 → 1,8
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
addq 1,pc |
|
/nopv32t2.ms
0,0 → 1,13
#mach: crisv10 crisv32 |
#output: Clock cycles including stall cycles for unaligned accesses @: 5\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=unaligned |
.include "nopv32t.ms" |
/movprv32.ms
0,0 → 1,21
# mach: crisv32 |
# output: ffffff20\nbb113344\n |
|
# Test v32-specific special registers. FIXME: more registers. |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
setf zcvn |
move vr,r3 |
test_cc 1 1 1 1 |
dumpr3 |
|
moveq -1,r3 |
move.d 0xbb113344,r4 |
clearf cvnz |
move r4,mof |
test_cc 0 0 0 0 |
move mof,r3 |
dumpr3 |
quit |
/movect10.ms
0,0 → 1,18
#mach: crisv10 |
#output: Basic clock cycles, total @: 3\n |
#output: Memory source stall cycles: 1\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
|
.include "testutils.inc" |
startnostack |
nop |
move.d 0xff004567,r5 |
break 15 |
/subxm.ms
0,0 → 1,106
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 3\n3\nffffff03\nffff0003\nff00\n0\n10000\n10000\n0\nffffff00\n0\n781343c9\n781344c9\n78124cc9\n78134cc9\nc450\n7ffff8ce\n |
|
.include "testutils.inc" |
.data |
x: |
.byte 0xff |
.word 0xffff |
.word 0xff |
.word 0xffff |
.byte 0x89 |
.word 0xf789 |
.word 0x8002 |
.word 0x764 |
|
start |
moveq 2,r3 |
move.d x,r5 |
subs.b [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 3 |
|
moveq 2,r3 |
subs.w [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 3 |
|
moveq 2,r3 |
subq 3,r5 |
subu.b [r5+],r3 |
test_cc 1 0 0 1 |
dumpr3 ; ffffff03 |
|
moveq 2,r3 |
subu.w [r5+],r3 |
test_cc 1 0 0 1 |
subq 3,r5 |
dumpr3 ; ffff0003 |
|
move.d 0xffff,r3 |
subu.b [r5],r3 |
test_cc 0 0 0 0 |
dumpr3 ; ff00 |
|
move.d 0xffff,r3 |
subu.w [r5],r3 |
test_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0xffff,r3 |
subs.b [r5],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 10000 |
|
move.d 0xffff,r3 |
subs.w [r5],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 10000 |
|
moveq -1,r3 |
subs.b [r5],r3 |
test_cc 0 1 0 0 |
addq 3,r5 |
dumpr3 ; 0 |
|
moveq -1,r3 |
subs.w [r5+],r3 |
test_cc 1 0 0 0 |
dumpr3 ; ffffff00 |
|
moveq -1,r3 |
subs.w [r5+],r3 |
test_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0x78134452,r3 |
subu.b [r5],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 781343c9 |
|
move.d 0x78134452,r3 |
subs.b [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 781344c9 |
|
move.d 0x78134452,r3 |
subu.w [r5],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 78124cc9 |
|
move.d 0x78134452,r3 |
subs.w [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 78134cc9 |
|
move.d 0x4452,r3 |
subs.w [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; c450 |
|
move.d 0x80000032,r3 |
subu.w [r5+],r3 |
test_cc 0 0 1 0 |
dumpr3 ; 7ffff8ce |
|
quit |
/movemrv32.ms
0,0 → 1,97
# mach: crisv32 |
# output: 15\n7\n2\nffff1234\nb\n16\nf\n2\nffffffef\nf\nffff1234\nf\nfffffff4\nd\nfffffff2\n10\nfffffff2\nd\n |
|
.include "testutils.inc" |
.data |
x: |
.dword 8,9,10,11 |
y: |
.dword -12,13,-14,15,16 |
|
start |
moveq 7,r0 |
moveq 2,r1 |
move.d 0xffff1234,r2 |
moveq 21,r3 |
move.d x,r4 |
setf zcvn |
movem r2,[r4+] |
test_cc 1 1 1 1 |
subq 12,r4 |
|
dumpr3 ; 15 |
|
move.d [r4+],r3 |
dumpr3 ; 7 |
|
move.d [r4+],r3 |
dumpr3 ; 2 |
|
move.d [r4+],r3 |
dumpr3 ; ffff1234 |
|
move.d [r4+],r3 |
dumpr3 ; b |
|
subq 16,r4 |
moveq 22,r0 |
moveq 15,r1 |
clearf zcvn |
movem r0,[r4] |
test_cc 0 0 0 0 |
move.d [r4+],r3 |
dumpr3 ; 16 |
|
move.d r1,r3 |
dumpr3 ; f |
|
move.d [r4+],r3 |
dumpr3 ; 2 |
|
subq 8,r4 |
moveq 10,r2 |
moveq -17,r0 |
clearf zc |
setf vn |
movem r1,[r4] |
test_cc 1 0 1 0 |
move.d [r4+],r3 |
dumpr3 ; ffffffef |
|
move.d [r4+],r3 |
dumpr3 ; f |
|
move.d [r4+],r3 |
dumpr3 ; ffff1234 |
|
move.d y,r4 |
setf zc |
clearf vn |
movem [r4+],r3 |
test_cc 0 1 0 1 |
dumpr3 ; f |
|
move.d r0,r3 |
dumpr3 ; fffffff4 |
|
move.d r1,r3 |
dumpr3 ; d |
|
move.d r2,r3 |
dumpr3 ; fffffff2 |
|
move.d [r4],r3 |
dumpr3 ; 10 |
|
subq 8,r4 |
setf zcvn |
movem [r4+],r0 |
test_cc 1 1 1 1 |
move.d r0,r3 |
dumpr3 ; fffffff2 |
|
move.d r1,r3 |
dumpr3 ; d |
|
quit |
|
/raw17.ms
0,0 → 1,29
; Checking read-after-write: different read-after-write combinations. |
#mach: crisv32 |
#output: Basic clock cycles, total @: 11\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 8\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
.include "testutils.inc" |
startnostack |
.lcomm x,4 |
.lcomm y,4 |
move.d x,$r0 |
move.d y,$r1 |
move.d $r1,[$r0] |
move.d [$r1],$r2 |
move.d [$r1],$r2 |
clear.d [$r0] |
move.d [$r1],$r2 |
movem $r0,[$r1] |
movem [$r1],$r0 |
move $srp,[$r1] |
move.d [$r1],$r0 |
break 15 |
/x8-v10.ms
0,0 → 1,20
#mach: crisv10 |
#ld: --section-start=.text=0 |
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n |
#output: 8 0 0 0 0 0 10 0 0 0 0 0 0 0 0 * ixnzvc 2\n |
#output: c 0 0 0 0 0 10 0 0 0 0 0 0 0 0 * ixnzvc 2\n |
#output: e 0 0 0 0 0 10 0 0 0 0 0 0 0 0 * ixnzvc 1\n |
#sim: --cris-trace=basic |
|
; Check that "jump [rN]" gets 2 cycles. |
|
.include "testutils.inc" |
startnostack |
move.d 0f,r5 |
jump [r5] |
break 15 |
1: |
nop |
break 15 |
0: |
.dword 1b |
/addm.ms
0,0 → 1,96
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n781344d0\n |
|
.include "testutils.inc" |
.data |
x: |
.dword 2,-1,0xffff,-1,0x5432f789 |
.word 2,-1,0xffff,0xf789 |
.byte 2,0xff,0x89 |
.byte 0x7e |
|
start |
moveq -1,r3 |
move.d x,r5 |
add.d [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1 |
|
moveq 2,r3 |
add.d [r5],r3 |
test_cc 0 0 0 1 |
addq 4,r5 |
dumpr3 ; 1 |
|
move.d 0xffff,r3 |
add.d [r5+],r3 |
test_cc 0 0 0 0 |
dumpr3 ; 1fffe |
|
moveq -1,r3 |
add.d [r5+],r3 |
test_cc 1 0 0 1 |
dumpr3 ; fffffffe |
|
move.d 0x78134452,r3 |
add.d [r5+],r3 |
test_cc 1 0 1 0 |
dumpr3 ; cc463bdb |
|
moveq -1,r3 |
add.w [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; ffff0001 |
|
moveq 2,r3 |
add.w [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1 |
|
move.d 0xffff,r3 |
add.w [r5],r3 |
test_cc 1 0 0 1 |
dumpr3 ; fffe |
|
move.d 0xfedaffff,r3 |
add.w [r5+],r3 |
test_cc 1 0 0 1 |
dumpr3 ; fedafffe |
|
move.d 0x78134452,r3 |
add.w [r5+],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 78133bdb |
|
moveq -1,r3 |
add.b [r5],r3 |
test_cc 0 0 0 1 |
addq 1,r5 |
dumpr3 ; ffffff01 |
|
moveq 2,r3 |
add.b [r5],r3 |
test_cc 0 0 0 1 |
dumpr3 ; 1 |
|
move.d 0xff,r3 |
add.b [r5],r3 |
test_cc 1 0 0 1 |
dumpr3 ; fe |
|
move.d 0xfeda49ff,r3 |
add.b [r5+],r3 |
test_cc 1 0 0 1 |
dumpr3 ; feda49fe |
|
move.d 0x78134452,r3 |
add.b [r5+],r3 |
test_cc 1 0 0 0 |
dumpr3 ; 781344db |
|
move.d 0x78134452,r3 |
add.b [r5],r3 |
test_cc 1 0 1 0 |
dumpr3 ; 781344d0 |
|
quit |
/x6-v32.ms
0,0 → 1,11
#mach: crisv32 |
#ld: --section-start=.text=0 |
#sim: --cris-trace=basic |
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n |
#output: 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 6 0 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: 8 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: a 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: c 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
#output: e 1 2 0 2 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n |
.include "tmulv10.ms" |
/scc.ms
0,0 → 1,89
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 1\n0\n1\n0\n1\n0\n1\n0\n0\n1\n1\n0\n1\n0\n1\n0\n1\n0\n0\n1\n0\n1\n1\n0\n1\n0\n0\n1\n1\n0\n1\n1\n0\n |
|
.include "testutils.inc" |
|
start |
clearf nzvc |
scc r3 |
dumpr3 ; 1 |
scs r3 |
dumpr3 ; 0 |
sne r3 |
dumpr3 ; 1 |
seq r3 |
dumpr3 ; 0 |
svc r3 |
dumpr3 ; 1 |
svs r3 |
dumpr3 ; 0 |
spl r3 |
dumpr3 ; 1 |
smi r3 |
dumpr3 ; 0 |
sls r3 |
dumpr3 ; 0 |
shi r3 |
dumpr3 ; 1 |
sge r3 |
dumpr3 ; 1 |
slt r3 |
dumpr3 ; 0 |
sgt r3 |
dumpr3 ; 1 |
sle r3 |
dumpr3 ; 0 |
sa r3 |
dumpr3 ; 1 |
setf nzvc |
scc r3 |
dumpr3 ; 0 |
scs r3 |
dumpr3 ; 1 |
sne r3 |
dumpr3 ; 0 |
svc r3 |
dumpr3 ; 0 |
svs r3 |
dumpr3 ; 1 |
spl r3 |
dumpr3 ; 0 |
smi r3 |
dumpr3 ; 1 |
sls r3 |
dumpr3 ; 1 |
shi r3 |
dumpr3 ; 0 |
sge r3 |
dumpr3 ; 1 |
slt r3 |
dumpr3 ; 0 |
sgt r3 |
dumpr3 ; 0 |
sle r3 |
dumpr3 ; 1 |
sa r3 |
dumpr3 ; 1 |
clearf n |
sge r3 |
dumpr3 ; 0 |
slt r3 |
dumpr3 ; 1 |
|
.if ..asm.arch.cris.v32 |
setf p |
ssb r3 |
.else |
moveq 1,r3 |
.endif |
dumpr3 ; 1 |
|
.if ..asm.arch.cris.v32 |
clearf p |
ssb r3 |
.else |
moveq 0,r3 |
.endif |
dumpr3 ; 0 |
|
quit |
/tmulv10.ms
0,0 → 1,26
#mach: crisv10 |
#output: Basic clock cycles, total @: 9\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
|
; Check that multiplications do not make the simulator barf. |
; Nothing deeper. |
|
.include "testutils.inc" |
startnostack |
moveq 1,r3 |
moveq 2,r1 |
moveq 1,r0 |
muls.d r0,r1 |
muls.d r0,r3 |
mulu.d r1,r3 |
break 15 |
nop |
/bdapqpc.ms
0,0 → 1,30
# mach: crisv3 crisv8 crisv10 |
# output: aaeebb11\nde378218\n |
|
# Test that the special case "X [pc+I],Y" works, where I byte-sized. |
|
.include "testutils.inc" |
start |
x: |
; FIXME: Gas bugs are making this a bit harder than necessary. |
; move.d [pc+y-(.+2)],r3 |
move.d [pc+8],r3 |
yy: |
jump zz |
|
y: |
.dword 0xaaeebb11 |
y2: |
.dword 0xde378218 |
|
zz: |
dumpr3 |
jump z |
quit |
|
; Check a negative offset. |
.space 50 |
z: |
move.d [pc+y2-(.+2)],r3 |
dumpr3 |
quit |
/btst.ms
0,0 → 1,87
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 1111\n |
|
.include "testutils.inc" |
start |
clearf nzvc |
moveq -1,r3 |
.if ..asm.arch.cris.v32 |
.else |
setf vc |
.endif |
btstq 0,r3 |
test_cc 1 0 0 0 |
|
moveq 2,r3 |
btstq 1,r3 |
test_cc 1 0 0 0 |
|
moveq 4,r3 |
btstq 1,r3 |
test_cc 0 1 0 0 |
|
moveq -1,r3 |
btstq 31,r3 |
test_cc 1 0 0 0 |
|
move.d 0x5a67f19f,r3 |
btstq 12,r3 |
test_cc 1 0 0 0 |
|
move.d 0xda67f19f,r3 |
move.d 29,r4 |
btst r4,r3 |
test_cc 0 0 0 0 |
|
move.d 0xda67f19f,r3 |
move.d 32,r4 |
btst r4,r3 |
test_cc 1 0 0 0 |
|
move.d 0xda67f191,r3 |
move.d 33,r4 |
btst r4,r3 |
test_cc 0 0 0 0 |
|
moveq -1,r3 |
moveq 0,r4 |
btst r4,r3 |
test_cc 1 0 0 0 |
|
moveq 2,r3 |
moveq 1,r4 |
btst r4,r3 |
test_cc 1 0 0 0 |
|
moveq -1,r3 |
moveq 31,r4 |
btst r4,r3 |
test_cc 1 0 0 0 |
|
moveq 4,r3 |
btstq 1,r3 |
test_cc 0 1 0 0 |
|
moveq -1,r3 |
moveq 15,r4 |
btst r4,r3 |
test_cc 1 0 0 0 |
|
move.d 0x5a67f19f,r3 |
moveq 12,r4 |
btst r4,r3 |
test_cc 1 0 0 0 |
|
move.d 0x5a678000,r3 |
moveq 11,r4 |
btst r4,r3 |
test_cc 0 1 0 0 |
|
move.d 0x5a67f19f,r3 |
btst r3,r3 |
test_cc 0 0 0 0 |
|
move.d 0x1111,r3 |
dumpr3 |
|
quit |
/moverbpc.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
startnostack |
setf |
move.d r5,pc |
quit |
/boundmv32.ms
0,0 → 1,15
# mach: crisv32 |
# xerror: |
# output: program stopped with signal 4.\n |
.include "testutils.inc" |
|
; Check that bound with a memory operand is invalid. |
start |
move.d 0f,r5 |
move.d r5,r3 |
.byte 0xd5,0x39 ; bound.d [r5],r3 -- we can't assemble it. |
pass |
|
0: |
.dword 0b |
|
/movepcw.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
startnostack |
setf |
test.w pc |
quit |
/raw7.ms
0,0 → 1,25
; Checking read-after-write: movemwrite-then-read 2 cycles. |
#mach: crisv32 |
#ld: --section-start=.text=0 |
#output: Basic clock cycles, total @: 6\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 2\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 1\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
.include "testutils.inc" |
startnostack |
.lcomm x,4*11 |
.lcomm y,4 |
move.d x,$r0 |
move.d y,$r1 |
nop |
nop |
movem $r10,[$r0] |
move.d [$r1],$r2 |
break 15 |
/orc.ms
0,0 → 1,71
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: 3\n3\nffff\nffffffff\n7c33f7db\nffff0003\n3\nfedaffff\n7813f7db\n3\n3\nfeb\n781344db\n |
|
.include "testutils.inc" |
start |
moveq 1,r3 |
or.d 2,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 3 |
|
moveq 2,r3 |
or.d 1,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 3 |
|
move.d 0xf0ff,r3 |
or.d 0xff0f,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff |
|
moveq -1,r3 |
or.d -1,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d 0x78134452,r3 |
or.d 0x5432f789,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 7c33f7db |
|
move.d 0xffff0001,r3 |
or.w 2,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; ffff0003 |
|
moveq 2,r3 |
or.w 1,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 3 |
|
move.d 0xfedaffaf,r3 |
or.w 0xff5f,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fedaffff |
|
move.d 0x78134452,r3 |
or.w 0xf789,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; 7813f7db |
|
moveq 1,r3 |
or.b 2,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 3 |
|
moveq 2,r3 |
or.b 1,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 3 |
|
move.d 0xfa3,r3 |
or.b 0x4a,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; feb |
|
move.d 0x78134453,r3 |
or.b 0x89,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; 781344db |
|
quit |
/addom.ms
0,0 → 1,55
# mach: crisv32 |
# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n |
|
.include "testutils.inc" |
.data |
x: |
.dword 0x55aa77ff |
.dword 0xccff2244 |
.dword 0x88ccee19 |
y: |
.dword 32769 |
.word -1 |
.dword 5 |
.byte 3,-4 |
.word 2 |
.dword -76789887 |
|
start |
moveq -1,r0 |
move.d x-32768,r5 |
move.d y,r13 |
addo.d [r13+],r5,acr |
move.d [acr],r3 |
dumpr3 ; 4455aa77 |
|
addu.w 32770,r5 |
addo.w [r13+],r5,acr |
move.d [acr],r3 |
dumpr3 ; 4455aa77 |
|
addo.d [r13],acr,acr |
addq 4,r13 |
move.d [acr],r3 |
dumpr3 ; ee19ccff |
|
addo.b [r13+],r5,acr |
movu.w [acr],r3 |
dumpr3 ; ff22 |
|
addo.b [r13],acr,acr |
addq 1,r13 |
move.d [acr],r3 |
dumpr3 ; 4455aa77 |
|
addo.w [r13],acr,acr |
addq 2,r13 |
move.d [acr],r3 |
dumpr3 ; ff224455 |
|
addo.d [r13+],r5,acr |
add.d 76789885,acr |
move.d [acr],r3 |
dumpr3 ; 55aa77ff |
|
quit |
/mulv10.ms
0,0 → 1,29
# mach: crisv8 crisv10 |
# output: fffffffe\n |
# output: ffffffff\n |
# output: fffffffe\n |
# output: 1\n |
|
; Check that carry is cleared on v8, v10. |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
moveq 2,r4 |
setf c |
muls.d r4,r3 |
test_cc 1 0 0 0 |
dumpr3 ; fffffffe |
move mof,r3 |
dumpr3 ; ffffffff |
|
moveq -1,r3 |
moveq 2,r4 |
setf c |
mulu.d r4,r3 |
test_cc 0 0 1 0 |
dumpr3 ; fffffffe |
move mof,r3 |
dumpr3 ; 1 |
|
quit |
/rfn.ms
0,0 → 1,53
# mach: crisv32 |
# output: c008c1af\n40000220\n40000080\n40000000\n |
|
; Check that RFN affects CCS the right way. |
|
.include "testutils.inc" |
start |
|
; Set SPC to 1 to disable single step exceptions when S flag is set. |
move 1,spc |
|
; CCS: |
; 31 24 23 16 15 8 7 0 |
; +---+-----------+-------+-------+-----------+---+---------------+ |
; |Q M|S R P U I X N Z V C|S R P U I X N Z V C|S R P U I X N Z V C| |
; | |2 2 2 2 2 2 2 2 2 2|1 1 1 1 1 1 1 1 1 1| | |
; +---+-----------+-------+-------+-----------+---+---------------+ |
|
; Clear S R P U I X N Z V C, set R1 P1 (not U1) I1 X1 N1 Z1 V1 C1, |
; clear S1 R2 P2 U2 N2 Z2 V2 C2, set S2 I2 X2 Q, clear M: |
; 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 |
move 0xa306fc00,ccs |
|
test_cc 0 0 0 0 |
|
rfn |
test_cc 1 1 1 1 |
move ccs,r3 |
dumpr3 ; 0xc008c1af |
|
and.d 0x3fffffff,r3 |
move r3,ccs |
rfn |
test_cc 0 0 0 0 |
move ccs,r3 |
dumpr3 ; 0x40000220 |
|
and.d 0x3fffffff,r3 |
move r3,ccs |
rfn |
test_cc 0 0 0 0 |
move ccs,r3 |
dumpr3 ; 0x40000080 |
|
and.d 0x3fffffff,r3 |
move r3,ccs |
or.w 0x100,r3 |
move r3,ccs |
rfn |
move ccs,r3 |
dumpr3 ; 0x40000000 |
|
quit |
/bdapq.ms
0,0 → 1,29
# mach: crisv0 crisv3 crisv8 crisv10 |
# output: ccff2244\n88ccee19\n55aa77ff\n19cc\n0\n |
|
.include "testutils.inc" |
.data |
x: |
.dword 0x55aa77ff |
.dword 0xccff2244 |
.dword 0x88ccee19 |
.dword 0 |
start |
moveq -1,r0 |
move.d x+4,r5 |
move.d [r5+0],r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ccff2244 |
move.d [r5=r5+4],r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; 88ccee19 |
move.d [r5=r5-8],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 55aa77ff |
movu.w [r5+7],r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 19cc |
move.d [r5+12],r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
quit |
/mstep.ms
0,0 → 1,108
# mach: crisv3 crisv8 crisv10 |
#output: fffffffe\n |
#output: 3\n |
#output: 1fffe\n |
#output: 2fffd\n |
#output: fffffffd\n |
#output: ffffffff\n |
#output: f02688a4\n |
#output: 1fffe\n |
#output: fffffffe\n |
#output: fffffffe\n |
#output: fffffff9\n |
#output: 0\n |
#output: 4459802d\n |
#output: 4459802d\n |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
moveq 2,r4 |
mstep r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fffffffe |
|
moveq 2,r3 |
moveq -1,r4 |
mstep r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 3 |
|
move.d 0xffff,r4 |
move.d r4,r3 |
mstep r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1fffe |
|
move.d 0xffff,r4 |
move.d r4,r3 |
setf n |
mstep r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 2fffd |
|
moveq -1,r4 |
move.d r4,r3 |
mstep r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fffffffd |
|
moveq -1,r3 |
moveq 1,r4 |
setf n |
mstep r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
mstep r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; f02688a4 |
|
move.d 0xffff,r3 |
move.d 0x1fffe,r4 |
mstep r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 1fffe |
|
move.d 0x7fffffff,r3 |
moveq 5,r5 |
mstep r5,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fffffffe |
|
move.d 0x7fffffff,r3 |
moveq 0,r5 |
mstep r5,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fffffffe |
|
move.d 0x7fffffff,r3 |
moveq -5,r5 |
mstep r5,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fffffff9 |
|
move.d 0x7fffffff,r3 |
moveq 2,r5 |
setf n |
mstep r5,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
setf n |
mstep r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 4459802d |
|
move.d 0x5432f789,r4 |
move.d 0x78134452,r3 |
setf nc |
mstep r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 4459802d |
|
quit |
/mover.ms
0,0 → 1,29
# mach: crisv3 crisv8 crisv10 crisv32 |
# output: ffffff05\nffff0005\n5\nffffff00\n |
|
; Move between registers. Check that just the subreg is copied. |
|
.include "testutils.inc" |
startnostack |
moveq -30,r3 |
moveq 5,r4 |
move.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
move.w r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
move.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 |
|
moveq -1,r3 |
moveq 0,r4 |
move.b r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 |
|
quit |
|
/halt.ms
0,0 → 1,9
# mach: crisv32 |
# xerror: |
# output: HALT isn't implemented\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
halt |
|
quit |
/lsl.ms
0,0 → 1,217
# mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
# output: ffffffff\n4\n80000000\nffff8000\n7f19f000\n80000000\n0\n0\n699fc67c\nffffffff\n4\n80000000\nffff8000\n7f19f000\nda670000\nda670000\nda670000\nda67c67c\nffffffff\nfffafffe\n4\nffff0000\nffff8000\n5a67f000\nda67f100\nda67f100\nda67f100\nda67f17c\nfff3faff\nfff3fafe\n4\nffffff00\nffffff00\nffffff80\n5a67f100\n5a67f1f0\n |
|
.include "testutils.inc" |
start |
moveq -1,r3 |
lslq 0,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
lslq 1,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 4 |
|
moveq -1,r3 |
lslq 31,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; 80000000 |
|
moveq -1,r3 |
lslq 15,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffff8000 |
|
move.d 0x5a67f19f,r3 |
lslq 12,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 7f19f000 |
|
move.d 0xda67f19f,r3 |
move.d 31,r4 |
lsl.d r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; 80000000 |
|
move.d 0xda67f19f,r3 |
move.d 32,r4 |
lsl.d r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0xda67f19f,r3 |
move.d 33,r4 |
lsl.d r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 0 |
|
move.d 0xda67f19f,r3 |
move.d 66,r4 |
lsl.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 699fc67c |
|
moveq -1,r3 |
moveq 0,r4 |
lsl.d r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
moveq 2,r3 |
moveq 1,r4 |
lsl.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 4 |
|
moveq -1,r3 |
moveq 31,r4 |
lsl.d r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; 80000000 |
|
moveq -1,r3 |
moveq 15,r4 |
lsl.d r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffff8000 |
|
move.d 0x5a67f19f,r3 |
moveq 12,r4 |
lsl.d r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 7f19f000 |
|
move.d 0xda67f19f,r3 |
move.d 31,r4 |
lsl.w r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; da670000 |
|
move.d 0xda67f19f,r3 |
move.d 32,r4 |
lsl.w r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; da670000 |
|
move.d 0xda67f19f,r3 |
move.d 33,r4 |
lsl.w r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; da670000 |
|
move.d 0xda67f19f,r3 |
move.d 66,r4 |
lsl.w r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; da67c67c |
|
moveq -1,r3 |
moveq 0,r4 |
lsl.w r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffffff |
|
move.d 0xfffaffff,r3 |
moveq 1,r4 |
lsl.w r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fffafffe |
|
moveq 2,r3 |
moveq 1,r4 |
lsl.w r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 4 |
|
moveq -1,r3 |
moveq 31,r4 |
lsl.w r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; ffff0000 |
|
moveq -1,r3 |
moveq 15,r4 |
lsl.w r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffff8000 |
|
move.d 0x5a67f19f,r3 |
moveq 12,r4 |
lsl.w r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; 5a67f000 |
|
move.d 0xda67f19f,r3 |
move.d 31,r4 |
lsl.b r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; da67f100 |
|
move.d 0xda67f19f,r3 |
move.d 32,r4 |
lsl.b r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; da67f100 |
|
move.d 0xda67f19f,r3 |
move.d 33,r4 |
lsl.b r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; da67f100 |
|
move.d 0xda67f19f,r3 |
move.d 66,r4 |
lsl.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; da67f17c |
|
move.d 0xfff3faff,r3 |
moveq 0,r4 |
lsl.b r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fff3faff |
|
move.d 0xfff3faff,r3 |
moveq 1,r4 |
lsl.b r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; fff3fafe |
|
moveq 2,r3 |
moveq 1,r4 |
lsl.b r4,r3 |
test_move_cc 0 0 0 0 |
dumpr3 ; 4 |
|
moveq -1,r3 |
moveq 31,r4 |
lsl.b r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; ffffff00 |
|
moveq -1,r3 |
moveq 15,r4 |
lsl.b r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; ffffff00 |
|
moveq -1,r3 |
moveq 7,r4 |
lsl.b r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; ffffff80 |
|
move.d 0x5a67f19f,r3 |
moveq 12,r4 |
lsl.b r4,r3 |
test_move_cc 0 1 0 0 |
dumpr3 ; 5a67f100 |
|
move.d 0x5a67f19f,r3 |
moveq 4,r4 |
lsl.b r4,r3 |
test_move_cc 1 0 0 0 |
dumpr3 ; 5a67f1f0 |
|
quit |
/ftagi.ms
0,0 → 1,9
# mach: crisv32 |
# xerror: |
# output: FTAGI isn't implemented\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
ftagi [r8] |
|
quit |
/testutils.inc
0,0 → 1,361
; Copied from fr30 and modified. |
; r9, r11-r13 are used as tmps, consider them call clobbered by these macros. |
; |
; Do not use the macro counter \@ in macros, there's a bug in |
; gas 2.9.1 when it is also a line-separator. |
; |
|
; Don't require the $-prefix on registers. |
.syntax no_register_prefix |
|
.macro startnostack |
.data |
.space 64,0 ; Simple stack |
stackhi: |
failmsg: |
.ascii "fail\n" |
passmsg: |
.ascii "pass\n" |
.text |
break 11 |
.global _start |
_start: |
.endm |
|
.macro start |
startnostack |
move.d stackhi,sp |
.endm |
|
; Exit with return code |
.macro exit rc |
move.d \rc,r10 |
moveq 1,r9 ; == __NR_exit |
break 13 |
break 15 |
.endm |
|
; Pass the test case |
.macro pass |
moveq 5,r12 |
move.d passmsg,r11 |
move.d 1,r10 |
moveq 4,r9 ; == __NR_write |
break 13 |
exit 0 |
.endm |
|
; Fail the testcase |
.macro fail |
; moveq 5,r12 |
; move.d failmsg,r11 |
; move.d 1,r10 |
; moveq 4,r1 |
; break 13 |
; exit 1 |
break 15 |
.endm |
|
.macro quit |
break 15 |
.endm |
|
.macro dumpr3 |
break 14 |
.endm |
|
; Load an immediate value into a general register |
; TODO: use minimal sized insn |
.macro mvi_h_gr val reg |
move.d \val,\reg |
.endm |
|
; Load an immediate value into a dedicated register |
.macro mvi_h_dr val reg |
move.d \val,r9 |
move.d r9,\reg |
.endm |
|
; Load a general register into another general register |
.macro mvr_h_gr src targ |
move.d \src,\targ |
.endm |
|
; Store an immediate into a word in memory |
.macro mvi_h_mem val addr |
mvi_h_gr \val r11 |
mvr_h_mem r11,\addr |
.endm |
|
; Store a register into a word in memory |
.macro mvr_h_mem reg addr |
move.d \addr,$r13 |
move.d \reg,[$r13] |
.endm |
|
; Store the current ps on the stack |
.macro save_ps |
.if ..asm.arch.cris.v32 |
move ccs,acr ; Push will do a "subq" first. |
push acr |
.else |
push dccr |
.endif |
.endm |
|
; Load a word value from memory |
.macro ldmem_h_gr addr reg |
move.d \addr,$r13 |
move.d [$r13],\reg |
.endm |
|
; Add 2 general registers |
.macro add_h_gr reg1 reg2 |
add.d \reg1,\reg2 |
.endm |
|
; Increment a register by and immediate |
.macro inci_h_gr inc reg |
mvi_h_gr \inc,r11 |
add.d r11,\reg |
.endm |
|
; Test the value of an immediate against a general register |
.macro test_h_gr val reg |
cmp.d \val,\reg |
beq 9f |
nop |
fail |
9: |
.endm |
|
; compare two general registers |
.macro testr_h_gr reg1 reg2 |
cmp.d \reg1,\reg2 |
beq 9f |
fail |
9: |
.endm |
|
; Test the value of an immediate against a dedicated register |
.macro test_h_dr val reg |
move \reg,$r12 |
test_h_gr \val $r12 |
.endm |
|
; Test the value of an general register against a dedicated register |
.macro testr_h_dr gr dr |
move \dr,$r12 |
testr_h_gr \gr $r12 |
.endm |
|
; Compare an immediate with word in memory |
.macro test_h_mem val addr |
ldmem_h_gr \addr $r12 |
test_h_gr \val $r12 |
.endm |
|
; Compare a general register with word in memory |
.macro testr_h_mem reg addr |
ldmem_h_gr \addr r12 |
testr_h_gr \reg r12 |
.endm |
|
; Set the condition codes |
; The lower bits of the mask *are* nzvc, so we don't |
; have to do anything strange. |
.macro set_cc mask |
move.w \mask,r13 |
.if ..asm.arch.cris.v32 |
move r13,ccs |
.else |
move r13,ccr |
.endif |
.endm |
|
; Set the stack mode |
; .macro set_s_user |
; orccr 0x20 |
; .endm |
; |
; .macro set_s_system |
; andccr 0x1f |
; .endm |
; |
;; Test the stack mode |
; .macro test_s_user |
; mvr_h_gr ps,r9 |
; mvi_h_gr 0x20,r11 |
; and r11,r9 |
; test_h_gr 0x20,r9 |
; .endm |
; |
; .macro test_s_system |
; mvr_h_gr ps,r9 |
; mvi_h_gr 0x20,r11 |
; and r11,r9 |
; test_h_gr 0x0,r9 |
; .endm |
|
; Set the interrupt bit |
; ??? Do they mean "enable interrupts" or "disable interrupts"? |
; Assuming enable here. |
.macro set_i val |
.if (\val == 1) |
ei |
.else |
di |
.endif |
.endm |
|
; Test the stack mode |
; .macro test_i val |
; mvr_h_gr ps,r9 |
; mvi_h_gr 0x10,r11 |
; and r11,r9 |
; .if (\val == 1) |
; test_h_gr 0x10,r9 |
; .else |
; test_h_gr 0x0,r9 |
; .endif |
; .endm |
; |
;; Set the ilm |
; .macro set_ilm val |
; stilm \val |
; .endm |
; |
;; Test the ilm |
; .macro test_ilm val |
; mvr_h_gr ps,r9 |
; mvi_h_gr 0x1f0000,r11 |
; and r11,r9 |
; mvi_h_gr \val,r12 |
; mvi_h_gr 0x1f,r11 |
; and r11,r12 |
; lsl 15,r12 |
; lsl 1,r12 |
; testr_h_gr r9,r12 |
; .endm |
; |
; Test the condition codes |
.macro test_cc N Z V C |
.if \N |
bpl 9f |
nop |
.else |
bmi 9f |
nop |
.endif |
.if \Z |
bne 9f |
nop |
.else |
beq 9f |
nop |
.endif |
.if \V |
bvc 9f |
nop |
.else |
bvs 9f |
nop |
.endif |
.if \C |
bcc 9f |
nop |
.else |
bcs 9f |
nop |
.endif |
ba 8f |
nop |
9: |
fail |
8: |
.endm |
|
.macro test_move_cc N Z V C |
.if ..asm.arch.cris.v32 |
; V and C aren't affected on v32, so to re-use the test-cases, |
; we fake them cleared. There's a separate test, nonvcv32.ms |
; covering this omission. |
clearf vc |
test_cc \N \Z 0 0 |
.else |
test_cc \N \Z \V \C |
.endif |
.endm |
|
; Set the division bits |
; .macro set_dbits val |
; mvr_h_gr ps,r12 |
; mvi_h_gr 0xfffff8ff,r11 |
; and r11,r12 |
; mvi_h_gr \val,r9 |
; mvi_h_gr 3,r11 |
; and r11,r9 |
; lsl 9,r9 |
; or r9,r12 |
; mvr_h_gr r12,ps |
; .endm |
; |
;; Test the division bits |
; .macro test_dbits val |
; mvr_h_gr ps,r9 |
; lsr 9,r9 |
; mvi_h_gr 3,r11 |
; and r11,r9 |
; test_h_gr \val,r9 |
; .endm |
; |
; Save the return pointer |
.macro save_rp |
push srp |
.ENDM |
|
; restore the return pointer |
.macro restore_rp |
pop srp |
.endm |
|
; Ensure branch taken |
.macro take_branch opcode |
\opcode 9f |
nop |
fail |
9: |
.endm |
|
.macro take_branch_d opcode val |
\opcode 9f |
nop |
move.d \val,r9 |
fail |
9: |
test_h_gr \val,r9 |
.endm |
|
; Ensure branch not taken |
.macro no_branch opcode |
\opcode 9f |
nop |
ba 8f |
nop |
9: |
fail |
8: |
.endm |
|
.macro no_branch_d opcode val |
\opcode 9f |
move.d \val,r9 |
nop |
ba 8f |
nop |
9: |
fail |
8: |
test_h_gr \val,r9 |
.endm |
|
/movepcb.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n |
|
.include "testutils.inc" |
startnostack |
setf |
test.b pc |
quit |
/bare2.ms
0,0 → 1,9
# mach: crisv32 |
# output: 0\n0\n4\n42\n |
# sim: --cris-naked --target binary --architecture crisv32 |
# ld: --oformat binary |
|
; Check that we can run a naked binary with the same expected |
; results as an ELF "executable". |
|
.include "bare1.ms" |
/addiv32.ms
0,0 → 1,62
# mach: crisv32 |
# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n |
|
.include "testutils.inc" |
.data |
x: |
.dword 0x55aa77ff |
.dword 0xccff2244 |
.dword 0x88ccee19 |
|
start |
setf cv |
moveq -1,r0 |
move.d x-32768,r5 |
move.d 32769,r6 |
addi r6.b,r5,acr |
test_cc 0 0 1 1 |
move.d [acr],r3 |
dumpr3 ; 4455aa77 |
|
addu.w 32771,r5 |
setf znvc |
moveq -1,r8 |
addi r8.w,r5,acr |
test_cc 1 1 1 1 |
move.d [acr],r3 |
dumpr3 ; 4455aa77 |
|
moveq 5,r10 |
clearf znvc |
addi r10.b,acr,acr |
test_cc 0 0 0 0 |
move.d [acr],r3 |
dumpr3 ; ee19ccff |
|
subq 1,r5 |
move.d r5,r8 |
subq 1,r8 |
moveq 1,r9 |
addi r9.d,r8,acr |
test_cc 0 0 0 0 |
movu.w [acr],r3 |
dumpr3 ; ff22 |
|
moveq -2,r11 |
addi r11.w,acr,acr |
move.d [acr],r3 |
dumpr3 ; 4455aa77 |
|
moveq 5,r9 |
addi r9.d,acr,acr |
subq 18,acr |
move.d [acr],r3 |
dumpr3 ; ff224455 |
|
move.d -76789888/4,r12 |
addi r12.d,r5,acr |
add.d 76789886,acr |
move.d [acr],r3 |
dumpr3 ; 55aa77ff |
|
quit |
/option4.ms
0,0 → 1,7
#mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
#sim: --cris-unknown-syscall=foo |
#xerror: |
#output: Unknown option `--cris-unknown-syscall=foo'\n |
.include "testutils.inc" |
start |
fail |
/raw12.ms
0,0 → 1,24
; Checking read-after-write: swrite-then-nop-nop-read unaffected. |
#mach: crisv32 |
#output: Basic clock cycles, total @: 6\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
.include "testutils.inc" |
startnostack |
.lcomm x,4 |
.lcomm y,4 |
move.d x,$r0 |
move.d y,$r1 |
clear.d [$r0] |
nop |
nop |
move [$r1],$srp |
break 15 |
/tmvmrv10.ms
0,0 → 1,50
#mach: crisv10 |
#output: Basic clock cycles, total @: 45\n |
#output: Memory source stall cycles: 0\n |
#output: Memory read-after-write stall cycles: 0\n |
#output: Movem source stall cycles: 0\n |
#output: Movem destination stall cycles: 0\n |
#output: Movem address stall cycles: 0\n |
#output: Multiplication source stall cycles: 0\n |
#output: Jump source stall cycles: 0\n |
#output: Branch misprediction stall cycles: 0\n |
#output: Jump target stall cycles: 0\n |
#sim: --cris-cycles=basic |
|
; Check that movem to register basically looks ok cycle-wise. |
; Nothing deep. |
|
.include "testutils.inc" |
startnostack |
move.d 0f,r5 |
moveq 0,r8 |
moveq 0,r9 |
|
; Adapted from crisv32 movem-to-memory penalty examples many |
; revisions ago. |
|
movem [r5],r4 |
test.d [r3] ; 3 cycle penalty on v32 (2 memory source, 1 movem dest). |
movem [r5],r4 |
subq 1,r8 |
test.d [r3] ; 2 cycle penalty on v32. |
movem [r5],r4 |
subq 1,r1 ; 3 cycle penalty on v32. |
movem [r5],r4 |
add.d r8,r9 |
subq 1,r1 ; 2 cycle penalty on v32. |
movem [r5],r4 |
add.d r8,r9 |
subq 1, r9 |
subq 1, r1 ; 1 cycle penalty on v32. |
break 15 |
|
.data |
.p2align 5 |
0: |
.dword 0b |
.dword 0b |
.dword 0b |
.dword 0b |
.dword 0b |
|
/jsr.ms
0,0 → 1,86
# mach: crisv3 crisv8 crisv10 crisv32 |
# output: 0\n0\n0\n0\n0\n0\n |
|
# Test that jsr Rn and jsr [PC+] work. |
|
.include "testutils.inc" |
start |
x: |
move.d 0f,r6 |
setf nzvc |
jsr r6 |
.if ..asm.arch.cris.v32 |
nop |
.endif |
0: |
test_move_cc 1 1 1 1 |
move srp,r3 |
sub.d 0b,r3 |
dumpr3 |
|
move.d 1f,r0 |
setf nzvc |
jsr r0 |
.if ..asm.arch.cris.v32 |
moveq 0,r0 |
.endif |
6: |
nop |
quit |
|
2: |
test_move_cc 0 0 0 0 |
move srp,r3 |
sub.d 3f,r3 |
dumpr3 |
jsr 4f |
.if ..asm.arch.cris.v32 |
nop |
.endif |
7: |
nop |
quit |
|
; Can't use local label 8 or 9, as they're used by test_move_cc. |
y: |
move srp,r3 |
sub.d 7b,r3 |
dumpr3 |
quit |
|
4: |
move srp,r3 |
sub.d 7b,r3 |
dumpr3 |
move.d 5f,r3 |
jump r3 |
.if ..asm.arch.cris.v32 |
moveq 0,r3 |
.endif |
quit |
|
.space 32770,0 |
1: |
test_move_cc 1 1 1 1 |
move srp,r3 |
sub.d 6b,r3 |
dumpr3 |
|
clearf cznv |
jsr 2b |
.if ..asm.arch.cris.v32 |
nop |
.endif |
3: |
|
quit |
|
5: |
move srp,r3 |
sub.d 7b,r3 |
dumpr3 |
jump y |
.if ..asm.arch.cris.v32 |
nop |
.endif |
quit |
/io7.ms
0,0 → 1,22
# mach: crisv32 |
# ld: --section-start=.text=0 |
# sim: --cris-900000xx |
# xerror: |
# output: ce11d0c\n |
# output: core: 4 byte write to unmapped address 0x90000004 at 0x16\n |
# output: program stopped with signal 11.\n |
|
; Check that invalid access to the simulator area is recognized. |
; "PASS" area. |
|
.include "testutils.inc" |
start |
move.d 0x0ce11d0c,$r3 |
dumpr3 |
move.d 0x90000004,$acr |
clear.d [$acr] |
move.d 0xbadc0de,$r3 |
dumpr3 |
0: |
ba 0b |
nop |
/msteppc3.ms
0,0 → 1,8
# mach: crisv3 crisv8 crisv10 |
# xerror: |
# output: General register read of PC is not implemented.\n |
# output: program stopped with signal 5.\n |
|
.include "testutils.inc" |
start |
mstep pc,pc |