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/openrisc/tags/gdb/gdb-6.8/gdb-6.8.openrisc-2.1/sim/testsuite/sim/frv/fr400
- from Rev 24 to Rev 33
- ↔ Reverse comparison
Rev 24 → Rev 33
/smu.cgs
0,0 → 1,237
# frv testcase for smu $GRi,$GRj |
# mach: fr405 fr450 |
|
.include "../testutils.inc" |
|
start |
|
.global smu |
smu1: |
; Positive operands |
set_gr_immed 3,gr7 ; multiply small numbers |
set_gr_immed 2,gr8 |
smu gr7,gr8 |
test_gr_immed 3,gr7 |
test_gr_immed 2,gr8 |
test_spr_immed 6,iacc0l |
test_spr_immed 0,iacc0h |
smu2: |
set_gr_immed 1,gr7 ; multiply by 1 |
set_gr_immed 2,gr8 |
smu gr7,gr8 |
test_gr_immed 1,gr7 |
test_gr_immed 2,gr8 |
test_spr_immed 2,iacc0l |
test_spr_immed 0,iacc0h |
smu3: |
set_gr_immed 2,gr7 ; multiply by 1 |
set_gr_immed 1,gr8 |
smu gr7,gr8 |
test_gr_immed 1,gr8 |
test_gr_immed 2,gr7 |
test_spr_immed 2,iacc0l |
test_spr_immed 0,iacc0h |
smu4: |
set_gr_immed 0,gr7 ; multiply by 0 |
set_gr_immed 2,gr8 |
smu gr7,gr8 |
test_gr_immed 2,gr8 |
test_gr_immed 0,gr7 |
test_spr_immed 0,iacc0l |
test_spr_immed 0,iacc0h |
smu5: |
set_gr_immed 2,gr7 ; multiply by 0 |
set_gr_immed 0,gr8 |
smu gr7,gr8 |
test_gr_immed 0,gr8 |
test_gr_immed 2,gr7 |
test_spr_immed 0,iacc0l |
test_spr_immed 0,iacc0h |
smu6: |
set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result |
set_gr_immed 2,gr8 |
smu gr7,gr8 |
test_gr_immed 2,gr8 |
test_gr_limmed 0x3fff,0xffff,gr7 |
test_spr_limmed 0x7fff,0xfffe,iacc0l |
test_spr_immed 0,iacc0h |
smu7: |
set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result |
set_gr_immed 2,gr8 |
smu gr7,gr8 |
test_gr_immed 2,gr8 |
test_gr_limmed 0x4000,0x0000,gr7 |
test_spr_limmed 0x8000,0x0000,iacc0l |
test_spr_immed 0,iacc0h |
smu8: |
set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result |
set_gr_immed 4,gr8 |
smu gr7,gr8 |
test_gr_immed 4,gr8 |
test_gr_limmed 0x4000,0x0000,gr7 |
test_spr_immed 0,iacc0l |
test_spr_immed 1,iacc0h |
smu9: |
set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result |
set_gr_limmed 0x7fff,0xffff,gr8 |
smu gr7,gr8 |
test_gr_limmed 0x7fff,0xffff,gr8 |
test_gr_limmed 0x7fff,0xffff,gr7 |
test_spr_immed 0x00000001,iacc0l |
test_spr_limmed 0x3fff,0xffff,iacc0h |
smu10: |
; Mixed operands |
set_gr_immed -3,gr7 ; multiply small numbers |
set_gr_immed 2,gr8 |
smu gr7,gr8 |
test_gr_immed 2,gr8 |
test_gr_immed -3,gr7 |
test_spr_immed -6,iacc0l |
test_spr_immed -1,iacc0h |
smu11: |
set_gr_immed 3,gr7 ; multiply small numbers |
set_gr_immed -2,gr8 |
smu gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_immed 3,gr7 |
test_spr_immed -6,iacc0l |
test_spr_immed -1,iacc0h |
smu12: |
set_gr_immed 1,gr7 ; multiply by 1 |
set_gr_immed -2,gr8 |
smu gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_immed 1,gr7 |
test_spr_immed -2,iacc0l |
test_spr_immed -1,iacc0h |
smu13: |
set_gr_immed -2,gr7 ; multiply by 1 |
set_gr_immed 1,gr8 |
smu gr7,gr8 |
test_gr_immed 1,gr8 |
test_gr_immed -2,gr7 |
test_spr_immed -2,iacc0l |
test_spr_immed -1,iacc0h |
smu14: |
set_gr_immed 0,gr7 ; multiply by 0 |
set_gr_immed -2,gr8 |
smu gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_immed 0,gr7 |
test_spr_immed 0,iacc0l |
test_spr_immed 0,iacc0h |
smu15: |
set_gr_immed -2,gr7 ; multiply by 0 |
set_gr_immed 0,gr8 |
smu gr7,gr8 |
test_gr_immed 0,gr8 |
test_gr_immed -2,gr7 |
test_spr_immed 0,iacc0l |
test_spr_immed 0,iacc0h |
smu16: |
set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result |
set_gr_immed -2,gr8 |
smu gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_limmed 0x2000,0x0001,gr7 |
test_spr_limmed 0xbfff,0xfffe,iacc0l |
test_spr_limmed 0xffff,0xffff,iacc0h |
smu17: |
set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result |
set_gr_immed -2,gr8 |
smu gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_limmed 0x4000,0x0000,gr7 |
test_spr_limmed 0x8000,0x0000,iacc0l |
test_spr_limmed 0xffff,0xffff,iacc0h |
smu18: |
set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result |
set_gr_immed -2,gr8 |
smu gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_limmed 0x4000,0x0001,gr7 |
test_spr_limmed 0x7fff,0xfffe,iacc0l |
test_spr_limmed 0xffff,0xffff,iacc0h |
smu19: |
set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result |
set_gr_immed -4,gr8 |
smu gr7,gr8 |
test_gr_immed -4,gr8 |
test_gr_limmed 0x4000,0x0000,gr7 |
test_spr_limmed 0x0000,0x0000,iacc0l |
test_spr_limmed 0xffff,0xffff,iacc0h |
smu20: |
set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result |
set_gr_limmed 0x8000,0x0000,gr8 |
smu gr7,gr8 |
test_gr_limmed 0x8000,0x0000,gr8 |
test_gr_limmed 0x7fff,0xffff,gr7 |
test_spr_limmed 0x8000,0x0000,iacc0l |
test_spr_limmed 0xc000,0x0000,iacc0h |
smu21: |
; Negative operands |
set_gr_immed -3,gr7 ; multiply small numbers |
set_gr_immed -2,gr8 |
smu gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_immed -3,gr7 |
test_spr_immed 6,iacc0l |
test_spr_immed 0,iacc0h |
smu22: |
set_gr_immed -1,gr7 ; multiply by 1 |
set_gr_immed -2,gr8 |
smu gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_immed -1,gr7 |
test_spr_immed 2,iacc0l |
test_spr_immed 0,iacc0h |
smu23: |
set_gr_immed -2,gr7 ; multiply by 1 |
set_gr_immed -1,gr8 |
smu gr7,gr8 |
test_gr_immed -1,gr8 |
test_gr_immed -2,gr7 |
test_spr_immed 2,iacc0l |
test_spr_immed 0,iacc0h |
smu24: |
set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result |
set_gr_immed -2,gr8 |
smu gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_limmed 0xc000,0x0001,gr7 |
test_spr_limmed 0x7fff,0xfffe,iacc0l |
test_spr_immed 0,iacc0h |
smu25: |
set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result |
set_gr_immed -2,gr8 |
smu gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_limmed 0xc000,0x0000,gr7 |
test_spr_limmed 0x8000,0x0000,iacc0l |
test_spr_immed 0,iacc0h |
smu26: |
set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result |
set_gr_immed -4,gr8 |
smu gr7,gr8 |
test_gr_immed -4,gr8 |
test_gr_limmed 0xc000,0x0000,gr7 |
test_spr_immed 0x00000000,iacc0l |
test_spr_immed 1,iacc0h |
smu27: |
set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result |
set_gr_limmed 0x8000,0x0001,gr8 |
smu gr7,gr8 |
test_gr_limmed 0x8000,0x0001,gr8 |
test_gr_limmed 0x8000,0x0001,gr7 |
test_spr_immed 0x00000001,iacc0l |
test_spr_limmed 0x3fff,0xffff,iacc0h |
smu28: |
set_gr_limmed 0x8000,0x0000,gr7 ; max positive result |
set_gr_limmed 0x8000,0x0000,gr8 |
smu gr7,gr8 |
test_gr_limmed 0x8000,0x0000,gr8 |
test_gr_limmed 0x8000,0x0000,gr7 |
test_spr_immed 0x00000000,iacc0l |
test_spr_limmed 0x4000,0x0000,iacc0h |
|
pass |
/mclracc.cgs
0,0 → 1,79
# frv testcase for mclracc $ACC40k,$A |
# mach: all |
|
.include "../testutils.inc" |
|
start |
|
.global mclracc |
mclracc: |
set_accg_immed 0xff,accg0 |
set_acc_immed -1,acc0 |
set_accg_immed 0xff,accg1 |
set_acc_immed -1,acc1 |
set_accg_immed 0xff,accg2 |
set_acc_immed -1,acc2 |
set_accg_immed 0xff,accg3 |
set_acc_immed -1,acc3 |
|
mclracc acc8,0 ; nop |
test_accg_immed 0xff,accg0 |
test_acc_immed -1,acc0 |
test_accg_immed 0xff,accg1 |
test_acc_immed -1,acc1 |
test_accg_immed 0xff,accg2 |
test_acc_immed -1,acc2 |
test_accg_immed 0xff,accg3 |
test_acc_immed -1,acc3 |
|
mclracc acc8,1 ; nop |
test_accg_immed 0xff,accg0 |
test_acc_immed -1,acc0 |
test_accg_immed 0xff,accg1 |
test_acc_immed -1,acc1 |
test_accg_immed 0xff,accg2 |
test_acc_immed -1,acc2 |
test_accg_immed 0xff,accg3 |
test_acc_immed -1,acc3 |
|
mclracc acc2,0 |
test_accg_immed 0xff,accg0 |
test_acc_immed -1,acc0 |
test_accg_immed 0xff,accg1 |
test_acc_immed -1,acc1 |
test_accg_immed 0,accg2 |
test_acc_immed 0,acc2 |
test_accg_immed 0xff,accg3 |
test_acc_immed -1,acc3 |
|
mclracc acc3,1 |
test_accg_immed 0xff,accg0 |
test_acc_immed -1,acc0 |
test_accg_immed 0xff,accg1 |
test_acc_immed -1,acc1 |
test_accg_immed 0,accg2 |
test_acc_immed 0,acc2 |
test_accg_immed 0,accg3 |
test_acc_immed 0,acc3 |
|
mclracc acc0,0 |
test_accg_immed 0,accg0 |
test_acc_immed 0,acc0 |
test_accg_immed 0xff,accg1 |
test_acc_immed -1,acc1 |
test_accg_immed 0,accg2 |
test_acc_immed 0,acc2 |
test_accg_immed 0,accg3 |
test_acc_immed 0,acc3 |
|
mclracc acc0,1 |
test_accg_immed 0,accg0 |
test_acc_immed 0,acc0 |
test_accg_immed 0,accg1 |
test_acc_immed 0,acc1 |
test_accg_immed 0,accg2 |
test_acc_immed 0,acc2 |
test_accg_immed 0,accg3 |
test_acc_immed 0,acc3 |
|
pass |
/sdiv.cgs
0,0 → 1,71
# frv testcase for sdiv $GRi,$GRj,$GRk |
# mach: all |
|
.include "../testutils.inc" |
|
start |
|
.global sdiv |
sdiv: |
; simple division 12 / 3 |
set_gr_immed 3,gr3 |
set_gr_immed 12,gr1 |
sdiv gr1,gr3,gr2 |
test_gr_immed 4,gr2 |
|
; Random example |
set_gr_limmed 0x0123,0x4567,gr3 |
set_gr_limmed 0xfedc,0xba98,gr1 |
sdiv gr1,gr3,gr2 |
test_gr_immed -1,gr2 |
|
; Special case from the Arch Spec Vol 2 |
or_spr_immed 0x20,isr ; turn on isr.edem |
set_gr_immed -1,gr3 |
set_gr_limmed 0x8000,0x0000,gr1 |
sdiv gr1,gr3,gr2 |
test_gr_limmed 0x7fff,0xffff,gr2 |
test_spr_bits 0x4,2,1,isr ; isr.aexc is set |
|
and_spr_immed -33,isr ; turn off isr.edem |
; set up exception handler |
set_psr_et 1 |
and_spr_immed -4081,tbr ; clear tbr.tt |
set_gr_spr tbr,gr17 |
inc_gr_immed 0x170,gr17 ; address of exception handler |
set_bctrlr_0_0 gr17 |
set_spr_immed 128,lcr |
set_gr_immed 0,gr15 |
|
; divide will cause overflow |
set_spr_addr ok1,lr |
set_gr_immed -1,gr3 |
set_gr_limmed 0x8000,0x0000,gr1 |
e1: sdiv gr1,gr3,gr2 ; overflow |
test_gr_immed 1,gr15 |
test_gr_limmed 0x8000,0x0000,gr2; gr2 updated |
|
; divide by zero |
set_spr_addr ok2,lr |
set_gr_immed 0xdeadbeef,gr2 |
e2: sdiv gr1,gr0,gr2 ; divide by zero |
test_gr_immed 2,gr15 ; handler called |
test_gr_immed 0xdeadbeef,gr2 ; gr2 not updated. |
|
pass |
|
ok1: ; exception handler for overflow |
test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set |
test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid |
test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set |
inc_gr_immed 1,gr15 |
rett 0 |
fail |
|
ok2: ; exception handler for divide by zero |
test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set |
test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid |
test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set |
inc_gr_immed 1,gr15 |
rett 0 |
fail |
/udiv.cgs
0,0 → 1,46
# frv testcase for udiv $GRi,$GRj,$GRk |
# mach: fr400 |
|
.include "../testutils.inc" |
|
start |
|
.global udiv |
udiv: |
; simple division 12 / 3 |
set_gr_immed 0x00000003,gr2 |
set_gr_immed 0x0000000c,gr3 |
udiv gr3,gr2,gr3 |
test_gr_immed 0x00000003,gr2 |
test_gr_immed 0x00000004,gr3 |
|
; example 1 from udiv in the fr30 manual |
set_gr_limmed 0x0123,0x4567,gr2 |
set_gr_limmed 0xfedc,0xba98,gr3 |
udiv gr3,gr2,gr3 |
test_gr_limmed 0x0123,0x4567,gr2 |
test_gr_immed 0x000000e0,gr3 |
|
; set up exception handler |
set_psr_et 1 |
and_spr_immed -4081,tbr ; clear tbr.tt |
set_gr_spr tbr,gr17 |
inc_gr_immed 0x170,gr17 ; address of exception handler |
set_bctrlr_0_0 gr17 |
set_spr_immed 128,lcr |
set_gr_immed 0,gr15 |
|
; divide by zero |
set_spr_addr ok1,lr |
e1: udiv gr1,gr0,gr2 ; divide by zero |
test_gr_immed 1,gr15 |
|
pass |
|
ok1: ; exception handler for divide by zero |
test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set |
test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid |
test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set |
inc_gr_immed 1,gr15 |
rett 0 |
fail |
/mhdsets.cgs
0,0 → 1,20
# frv testcase for mhdsets $s12,$FRk |
# mach: all |
|
.include "../testutils.inc" |
|
start |
|
.global mhdsets |
mhdsets: |
set_fr_immed 0,fr1 |
mhdsets 0,fr1 |
test_fr_iimmed 0,fr1 |
mhdsets 1,fr1 |
test_fr_iimmed 0x00010001,fr1 |
mhdsets 0x7ff,fr1 |
test_fr_iimmed 0x07ff07ff,fr1 |
mhdsets -2048,fr1 |
test_fr_iimmed 0xf800f800,fr1 |
|
pass |
/smsss.cgs
0,0 → 1,354
# frv testcase for smsss $GRi,$GRj |
# mach: fr405 fr450 |
|
.include "../testutils.inc" |
|
start |
|
.global smsss |
smsss1: |
; Positive operands |
set_gr_immed 3,gr7 ; multiply small numbers |
set_gr_immed 2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 7,iacc0l |
smsss gr7,gr8 |
test_gr_immed 3,gr7 |
test_gr_immed 2,gr8 |
test_spr_immed 1,iacc0l ; result 7-3*2 |
test_spr_immed 0,iacc0h |
smsss2: |
set_gr_immed 1,gr7 ; multiply by 1 |
set_gr_immed 2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 3,iacc0l |
smsss gr7,gr8 |
test_gr_immed 1,gr7 |
test_gr_immed 2,gr8 |
test_spr_immed 1,iacc0l ; result 3-1*2 |
test_spr_immed 0,iacc0h |
smsss3: |
set_gr_immed 2,gr7 ; multiply by 1 |
set_gr_immed 1,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 3,iacc0l |
smsss gr7,gr8 |
test_gr_immed 1,gr8 |
test_gr_immed 2,gr7 |
test_spr_immed 1,iacc0l ; result 3-2*1 |
test_spr_immed 0,iacc0h |
smsss4: |
set_gr_immed 0,gr7 ; multiply by 0 |
set_gr_immed 2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smsss gr7,gr8 |
test_gr_immed 2,gr8 |
test_gr_immed 0,gr7 |
test_spr_immed 1,iacc0l ; result 1-0*2 |
test_spr_immed 0,iacc0h |
smsss5: |
set_gr_immed 2,gr7 ; multiply by 0 |
set_gr_immed 0,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smsss gr7,gr8 |
test_gr_immed 0,gr8 |
test_gr_immed 2,gr7 |
test_spr_immed 1,iacc0l ; result 1-2*0 |
test_spr_immed 0,iacc0h |
smsss6: |
set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result |
set_gr_immed 2,gr8 |
set_spr_immed -1,iacc0h |
set_spr_immed -1,iacc0l |
smsss gr7,gr8 |
test_gr_immed 2,gr8 |
test_gr_limmed 0x3fff,0xffff,gr7 |
test_spr_limmed 0x8000,0x0001,iacc0l ; -1-3fffffff*2 |
test_spr_immed -1,iacc0h |
smsss7: |
set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result |
set_gr_immed 2,gr8 |
set_spr_immed -1,iacc0h |
set_spr_limmed 0x8000,0x0001,iacc0l |
smsss gr7,gr8 |
test_gr_immed 2,gr8 |
test_gr_limmed 0x4000,0x0000,gr7 |
test_spr_immed 1,iacc0l ; ffffffff80000001-40000000*2 |
test_spr_immed -1,iacc0h |
smsss8: |
set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result |
set_gr_immed 4,gr8 |
set_spr_immed -1,iacc0h |
set_spr_immed 1,iacc0l |
smsss gr7,gr8 |
test_gr_immed 4,gr8 |
test_gr_limmed 0x4000,0x0000,gr7 |
test_spr_immed 1,iacc0l ; ffffffff00000001-40000000*4 |
test_spr_immed -2,iacc0h |
smsss9: |
set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result |
set_gr_limmed 0x7fff,0xffff,gr8 |
set_spr_limmed 0x7fff,0xffff,iacc0h |
set_spr_immed -1,iacc0l |
smsss gr7,gr8 |
test_gr_limmed 0x7fff,0xffff,gr8 |
test_gr_limmed 0x7fff,0xffff,gr7 |
test_spr_limmed 0xffff,0xfffe,iacc0l ; 7fffffffffffffff-7fffffff*7fffffff |
test_spr_limmed 0x4000,0x0000,iacc0h |
smsss10: |
; Mixed operands |
set_gr_immed -3,gr7 ; multiply small numbers |
set_gr_immed 2,gr8 |
set_spr_immed -1,iacc0h |
set_spr_immed -5,iacc0l |
smsss gr7,gr8 |
test_gr_immed 2,gr8 |
test_gr_immed -3,gr7 |
test_spr_immed 1,iacc0l ; -5-(-3*2) |
test_spr_immed 0,iacc0h |
smsss11: |
set_gr_immed 3,gr7 ; multiply small numbers |
set_gr_immed -2,gr8 |
set_spr_immed -1,iacc0h |
set_spr_immed -5,iacc0l |
smsss gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_immed 3,gr7 |
test_spr_immed 1,iacc0l ; -5-(3*-2) |
test_spr_immed 0,iacc0h |
smsss12: |
set_gr_immed 1,gr7 ; multiply by 1 |
set_gr_immed -2,gr8 |
set_spr_immed -1,iacc0h |
set_spr_immed -1,iacc0l |
smsss gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_immed 1,gr7 |
test_spr_immed 1,iacc0l ; -1-(1*-2) |
test_spr_immed 0,iacc0h |
smsss13: |
set_gr_immed -2,gr7 ; multiply by 1 |
set_gr_immed 1,gr8 |
set_spr_immed -1,iacc0h |
set_spr_immed -1,iacc0l |
smsss gr7,gr8 |
test_gr_immed 1,gr8 |
test_gr_immed -2,gr7 |
test_spr_immed 1,iacc0l ; -1-(-2*1) |
test_spr_immed 0,iacc0h |
smsss14: |
set_gr_immed 0,gr7 ; multiply by 0 |
set_gr_immed -2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smsss gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_immed 0,gr7 |
test_spr_immed 1,iacc0l ; 1-(0*-2) |
test_spr_immed 0,iacc0h |
smsss15: |
set_gr_immed -2,gr7 ; multiply by 0 |
set_gr_immed 0,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smsss gr7,gr8 |
test_gr_immed 0,gr8 |
test_gr_immed -2,gr7 |
test_spr_immed 1,iacc0l ; 1-(-2*0) |
test_spr_immed 0,iacc0h |
smsss16: |
set_gr_limmed 0x2000,0x0000,gr7 ; 31 bit result |
set_gr_immed -2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_limmed 0x3fff,0xffff,iacc0l |
smsss gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_limmed 0x2000,0x0000,gr7 |
test_spr_limmed 0x7fff,0xffff,iacc0l |
test_spr_immed 0,iacc0h ; 3fffffff-20000001*-2 |
smsss17: |
set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result |
set_gr_immed -2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smsss gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_limmed 0x4000,0x0000,gr7 |
test_spr_limmed 0x8000,0x0001,iacc0l ; 1-40000000*-2 |
test_spr_immed 0,iacc0h |
smsss18: |
set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result |
set_gr_immed -2,gr8 |
set_spr_immed -1,iacc0h |
set_spr_immed -1,iacc0l |
smsss gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_limmed 0x4000,0x0000,gr7 |
test_spr_limmed 0x7fff,0xffff,iacc0l |
test_spr_immed 0,iacc0h ; -1-40000000*-2 |
smsss19: |
set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result |
set_gr_immed -4,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smsss gr7,gr8 |
test_gr_immed -4,gr8 |
test_gr_limmed 0x4000,0x0000,gr7 |
test_spr_immed 1,iacc0l ; 200000001-(40000000*-4) |
test_spr_immed 1,iacc0h |
smsss20: |
set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result |
set_gr_limmed 0x7fff,0xffff,gr8 |
set_spr_limmed 0xbfff,0xffff,iacc0h |
set_spr_limmed 0x0000,0x0001,iacc0l |
smsss gr7,gr8 |
test_gr_limmed 0x7fff,0xffff,gr8 |
test_gr_limmed 0x7fff,0xffff,gr7 |
test_spr_immed 0,iacc0l ; bfffffff00000001-(7fffffff*7fffffff) |
test_spr_limmed 0x8000,0x0000,iacc0h |
smsss21: |
; Negative operands |
set_gr_immed -3,gr7 ; multiply small numbers |
set_gr_immed -2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 7,iacc0l |
smsss gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_immed -3,gr7 |
test_spr_immed 1,iacc0l ; 7-(-3*-2) |
test_spr_immed 0,iacc0h |
smsss22: |
set_gr_immed -1,gr7 ; multiply by 1 |
set_gr_immed -2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 3,iacc0l |
smsss gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_immed -1,gr7 |
test_spr_immed 1,iacc0l ; 3-(-1*-2) |
test_spr_immed 0,iacc0h |
smsss23: |
set_gr_immed -2,gr7 ; multiply by 1 |
set_gr_immed -1,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 3,iacc0l |
smsss gr7,gr8 |
test_gr_immed -1,gr8 |
test_gr_immed -2,gr7 |
test_spr_immed 1,iacc0l ; 3-(-2*-1) |
test_spr_immed 0,iacc0h |
smsss24: |
set_gr_immed -32768,gr7 ; 31 bit result |
set_gr_immed -32768,gr8 |
set_spr_immed 0,iacc0h |
set_spr_limmed 0xbfff,0xffff,iacc0l |
smsss gr7,gr8 |
test_gr_immed -32768,gr8 |
test_gr_immed -32768,gr7 |
test_spr_limmed 0x7fff,0xffff,iacc0l ; 7ffffffb-(-2*-2) |
test_spr_immed 0,iacc0h |
smsss25: |
set_gr_immed 0xffff,gr7 ; 32 bit result |
set_gr_immed 0xffff,gr8 |
set_spr_immed 1,iacc0h |
set_spr_limmed 0xfffe,0x0000,iacc0l |
smsss gr7,gr8 |
test_gr_immed 0xffff,gr8 |
test_gr_immed 0xffff,gr7 |
test_spr_limmed 0xffff,0xffff,iacc0l ; 1fffe0000-ffff*ffff |
test_spr_immed 0,iacc0h |
smsss26: |
set_gr_limmed 0x0001,0x0000,gr7 ; 33 bit result |
set_gr_limmed 0x0001,0x0000,gr8 |
set_spr_immed 2,iacc0h |
set_spr_immed 1,iacc0l |
smsss gr7,gr8 |
test_gr_limmed 0x0001,0x0000,gr8 |
test_gr_limmed 0x0001,0x0000,gr7 |
test_spr_immed 1,iacc0l ; 0x200000001-0x10000*0x10000 |
test_spr_immed 1,iacc0h |
smsss27: |
set_gr_immed -2,gr7 ; almost max positive result |
set_gr_immed -2,gr8 |
set_spr_limmed 0x7fff,0xffff,iacc0h |
set_spr_limmed 0xffff,0xffff,iacc0l |
smsss gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_immed -2,gr7 |
test_spr_limmed 0xffff,0xfffb,iacc0l ; maxpos - (-2*-2) |
test_spr_limmed 0x7fff,0xffff,iacc0h |
smsss28: |
set_gr_immed 0,gr7 ; max positive result |
set_gr_immed 0,gr8 |
set_spr_limmed 0x7fff,0xffff,iacc0h |
set_spr_limmed 0xffff,0xffff,iacc0l |
smsss gr7,gr8 |
test_gr_immed 0,gr8 |
test_gr_immed 0,gr7 |
test_spr_limmed 0xffff,0xffff,iacc0l ; maxpos-(0*0) |
test_spr_limmed 0x7fff,0xffff,iacc0h |
smsss29: |
set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (pos) |
set_gr_limmed 0x8000,0x0000,gr8 |
set_spr_limmed 0x4000,0x0000,iacc0h |
set_spr_limmed 0x7fff,0xffff,iacc0l |
smsss gr7,gr8 |
test_gr_limmed 0x8000,0x0000,gr8 |
test_gr_limmed 0x7fff,0xffff,gr7 |
test_spr_limmed 0xffff,0xffff,iacc0l ; 400000007fffffff - |
test_spr_limmed 0x7fff,0xffff,iacc0h ; 0x80000000*0x7fffffff |
smsss30: |
set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (pos) |
set_gr_limmed 0x8000,0x0000,gr8 |
set_spr_limmed 0x4000,0x0000,iacc0h |
set_spr_limmed 0x8000,0x0000,iacc0l |
smsss gr7,gr8 |
test_gr_limmed 0x8000,0x0000,gr8 |
test_gr_limmed 0x7fff,0xffff,gr7 |
test_spr_limmed 0xffff,0xffff,iacc0l ; 4000000080000000 - |
test_spr_limmed 0x7fff,0xffff,iacc0h ; 0x80000000*0x7fffffff |
|
smsss31: |
set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (pos) |
set_gr_limmed 0x8000,0x0000,gr8 |
set_spr_limmed 0xffff,0xffff,iacc0l |
set_spr_limmed 0x7fff,0xffff,iacc0h |
smsss gr7,gr8 |
test_gr_limmed 0x8000,0x0000,gr8 |
test_gr_limmed 0x7fff,0xffff,gr7 |
test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffffffffffff - |
test_spr_limmed 0x7fff,0xffff,iacc0h ; 80000000*80000000 |
smsss32: |
set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (neg) |
set_gr_limmed 0x7fff,0xffff,gr8 |
set_spr_immed 1,iacc0l |
set_spr_limmed 0xbfff,0xffff,iacc0h |
smsss gr7,gr8 |
test_gr_limmed 0x7fff,0xffff,gr8 |
test_gr_limmed 0x7fff,0xffff,gr7 |
test_spr_limmed 0x0000,0x0000,iacc0l ; bfffffff00000001 - |
test_spr_limmed 0x8000,0x0000,iacc0h ; 0x7fffffff*0x7fffffff |
smsss33: |
set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (neg) |
set_gr_limmed 0x7fff,0xffff,gr8 |
set_spr_immed 0,iacc0l |
set_spr_limmed 0xbfff,0xffff,iacc0h |
smsss gr7,gr8 |
test_gr_limmed 0x7fff,0xffff,gr8 |
test_gr_limmed 0x7fff,0xffff,gr7 |
test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ |
test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff7fffffff |
smsss34: |
set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (neg) |
set_gr_limmed 0x7fff,0xffff,gr8 |
set_spr_limmed 0x0000,0x0000,iacc0l |
set_spr_limmed 0x8000,0x0000,iacc0h |
smsss gr7,gr8 |
test_gr_limmed 0x7fff,0xffff,gr8 |
test_gr_limmed 0x7fff,0xffff,gr7 |
test_spr_limmed 0x0000,0x0000,iacc0l ; 8000000000000000- |
test_spr_limmed 0x8000,0x0000,iacc0h ; 7fffffff*7fffffff+ |
|
pass |
/csdiv.cgs
0,0 → 1,187
# frv testcase for csdiv $GRi,$GRj,$GRk,$CCi,$cond |
# mach: all |
|
.include "../testutils.inc" |
|
start |
|
.global csdiv |
csdiv: |
set_spr_immed 0x1b1b,cccr |
|
; simple division 12 / 3 |
set_gr_immed 3,gr3 |
set_gr_immed 12,gr1 |
csdiv gr1,gr3,gr2,cc4,1 |
test_gr_immed 4,gr2 |
|
; Random example |
set_gr_limmed 0x0123,0x4567,gr3 |
set_gr_limmed 0xfedc,0xba98,gr1 |
csdiv gr1,gr3,gr2,cc4,1 |
test_gr_immed -1,gr2 |
|
; Special case from the Arch Spec Vol 2 |
and_spr_immed -33,isr ; turn off isr.edem |
; set up exception handler |
set_psr_et 1 |
and_spr_immed -4081,tbr ; clear tbr.tt |
set_gr_spr tbr,gr17 |
inc_gr_immed 0x170,gr17 ; address of exception handler |
set_bctrlr_0_0 gr17 |
set_spr_immed 128,lcr |
set_gr_immed 0,gr15 |
|
; divide will cause overflow |
set_spr_addr ok1,lr |
set_gr_immed -1,gr3 |
set_gr_limmed 0x8000,0x0000,gr1 |
e1: csdiv gr1,gr3,gr2,cc4,1 |
test_gr_immed 1,gr15 |
test_gr_limmed 0x8000,0x0000,gr2 |
|
; Special case from the Arch Spec Vol 2 |
or_spr_immed 0x20,isr ; turn on isr.edem |
set_gr_immed -1,gr3 |
set_gr_limmed 0x8000,0x0000,gr1 |
csdiv gr1,gr3,gr2,cc4,1 |
test_gr_limmed 0x7fff,0xffff,gr2 |
|
; simple division 12 / 3 |
set_gr_immed 3,gr3 |
set_gr_immed 12,gr1 |
csdiv gr1,gr3,gr2,cc4,0 |
test_gr_limmed 0x7fff,0xffff,gr2 |
|
; Random example |
set_gr_limmed 0x0123,0x4567,gr3 |
set_gr_limmed 0xfedc,0xba98,gr1 |
csdiv gr1,gr3,gr2,cc4,0 |
test_gr_limmed 0x7fff,0xffff,gr2 |
|
; Special case from the Arch Spec Vol 2 |
and_spr_immed -33,isr ; turn off isr.edem |
set_gr_immed -1,gr3 |
set_gr_limmed 0x8000,0x0000,gr1 |
csdiv gr1,gr3,gr2,cc4,0 |
test_gr_limmed 0x7fff,0xffff,gr2 |
|
or_spr_immed 0x20,isr ; turn on isr.edem |
set_gr_immed -1,gr3 |
set_gr_limmed 0x8000,0x0000,gr1 |
csdiv gr1,gr3,gr2,cc4,0 |
test_gr_limmed 0x7fff,0xffff,gr2 |
|
; simple division 12 / 3 |
set_gr_immed 3,gr3 |
set_gr_immed 12,gr1 |
csdiv gr1,gr3,gr2,cc5,0 |
test_gr_immed 4,gr2 |
|
; Random example |
set_gr_limmed 0x0123,0x4567,gr3 |
set_gr_limmed 0xfedc,0xba98,gr1 |
csdiv gr1,gr3,gr2,cc5,0 |
test_gr_immed -1,gr2 |
|
; Special case from the Arch Spec Vol 2 |
and_spr_immed -33,isr ; turn off isr.edem |
; divide will cause overflow |
set_spr_addr ok1,lr |
set_gr_immed -1,gr3 |
set_gr_limmed 0x8000,0x0000,gr1 |
e2: csdiv gr1,gr3,gr2,cc5,0 |
test_gr_immed 2,gr15 |
test_gr_limmed 0x8000,0x0000,gr2 |
|
; Special case from the Arch Spec Vol 2 |
or_spr_immed 0x20,isr ; turn on isr.edem |
set_gr_immed -1,gr3 |
set_gr_limmed 0x8000,0x0000,gr1 |
csdiv gr1,gr3,gr2,cc5,0 |
test_gr_limmed 0x7fff,0xffff,gr2 |
|
; simple division 12 / 3 |
set_gr_immed 3,gr3 |
set_gr_immed 12,gr1 |
csdiv gr1,gr3,gr2,cc5,1 |
test_gr_limmed 0x7fff,0xffff,gr2 |
|
; Random example |
set_gr_limmed 0x0123,0x4567,gr3 |
set_gr_limmed 0xfedc,0xba98,gr1 |
csdiv gr1,gr3,gr2,cc5,1 |
test_gr_limmed 0x7fff,0xffff,gr2 |
|
; Special case from the Arch Spec Vol 2 |
and_spr_immed -33,isr ; turn off isr.edem |
set_gr_immed -1,gr3 |
set_gr_limmed 0x8000,0x0000,gr1 |
csdiv gr1,gr3,gr2,cc5,1 |
test_gr_limmed 0x7fff,0xffff,gr2 |
|
or_spr_immed 0x20,isr ; turn on isr.edem |
set_gr_immed -1,gr3 |
set_gr_limmed 0x8000,0x0000,gr1 |
csdiv gr1,gr3,gr2,cc5,1 |
test_gr_limmed 0x7fff,0xffff,gr2 |
|
; simple division 12 / 3 |
set_gr_immed 3,gr3 |
set_gr_immed 12,gr1 |
csdiv gr1,gr3,gr2,cc6,0 |
test_gr_limmed 0x7fff,0xffff,gr2 |
|
; Random example |
set_gr_limmed 0x0123,0x4567,gr3 |
set_gr_limmed 0xfedc,0xba98,gr1 |
csdiv gr1,gr3,gr2,cc6,0 |
test_gr_limmed 0x7fff,0xffff,gr2 |
|
; Special case from the Arch Spec Vol 2 |
and_spr_immed -33,isr ; turn off isr.edem |
set_gr_immed -1,gr3 |
set_gr_limmed 0x8000,0x0000,gr1 |
csdiv gr1,gr3,gr2,cc6,0 |
test_gr_limmed 0x7fff,0xffff,gr2 |
|
or_spr_immed 0x20,isr ; turn on isr.edem |
set_gr_immed -1,gr3 |
set_gr_limmed 0x8000,0x0000,gr1 |
csdiv gr1,gr3,gr2,cc6,0 |
test_gr_limmed 0x7fff,0xffff,gr2 |
|
; simple division 12 / 3 |
set_gr_immed 3,gr3 |
set_gr_immed 12,gr1 |
csdiv gr1,gr3,gr2,cc7,1 |
test_gr_limmed 0x7fff,0xffff,gr2 |
|
; Random example |
set_gr_limmed 0x0123,0x4567,gr3 |
set_gr_limmed 0xfedc,0xba98,gr1 |
csdiv gr1,gr3,gr2,cc7,1 |
test_gr_limmed 0x7fff,0xffff,gr2 |
|
; Special case from the Arch Spec Vol 2 |
and_spr_immed -33,isr ; turn off isr.edem |
set_gr_immed -1,gr3 |
set_gr_limmed 0x8000,0x0000,gr1 |
csdiv gr1,gr3,gr2,cc7,1 |
test_gr_limmed 0x7fff,0xffff,gr2 |
|
or_spr_immed 0x20,isr ; turn on isr.edem |
set_gr_immed -1,gr3 |
set_gr_limmed 0x8000,0x0000,gr1 |
csdiv gr1,gr3,gr2,cc7,1 |
test_gr_limmed 0x7fff,0xffff,gr2 |
|
pass |
|
ok1: ; exception handler for overflow |
test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set |
test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid |
test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set |
inc_gr_immed 1,gr15 |
rett 0 |
fail |
/mhsethih.cgs
0,0 → 1,22
# frv testcase for mhsethih $s12,$FRk |
# mach: all |
|
.include "../testutils.inc" |
|
start |
|
.global mhsethih |
mhsethih: |
set_fr_immed 0,fr1 |
mhsethih 0,fr1 |
test_fr_iimmed 0,fr1 |
mhsethih 1,fr1 |
test_fr_iimmed 0x08000000,fr1 |
mhsethih 0xf,fr1 |
test_fr_iimmed 0x78000000,fr1 |
mhsethih -16,fr1 |
test_fr_iimmed 0x80000000,fr1 |
mhsethih -1,fr1 |
test_fr_iimmed 0xf8000000,fr1 |
|
pass |
/masaccs.cgs
0,0 → 1,151
# frv testcase for masaccs $ACC40Si,$ACC40Sk |
# mach: fr400 |
|
.include "../testutils.inc" |
|
start |
|
.global masaccs |
masaccs: |
set_accg_immed 0,accg0 |
set_acc_immed 0x00000000,acc0 |
set_accg_immed 0,accg1 |
set_acc_immed 0x00000000,acc1 |
masaccs acc0,acc2 |
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set |
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set |
test_accg_immed 0,accg2 |
test_acc_limmed 0x0000,0x0000,acc2 |
test_accg_immed 0,accg3 |
test_acc_limmed 0x0000,0x0000,acc3 |
|
set_accg_immed 0,accg0 |
set_acc_immed 0xdead0000,acc0 |
set_accg_immed 0,accg1 |
set_acc_immed 0x0000beef,acc1 |
masaccs acc0,acc2 |
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set |
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set |
test_accg_immed 0,accg2 |
test_acc_limmed 0xdead,0xbeef,acc2 |
test_accg_immed 0,accg3 |
test_acc_limmed 0xdeac,0x4111,acc3 |
|
set_accg_immed 0,accg0 |
set_acc_immed 0x0000dead,acc0 |
set_accg_immed 0,accg1 |
set_acc_immed 0xbeef0000,acc1 |
masaccs acc0,acc2 |
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set |
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set |
test_accg_immed 0,accg2 |
test_acc_limmed 0xbeef,0xdead,acc2 |
test_accg_immed 0xff,accg3 |
test_acc_limmed 0x4111,0xdead,acc3 |
|
set_accg_immed 0,accg0 |
set_acc_immed 0x12345678,acc0 |
set_accg_immed 0,accg1 |
set_acc_immed 0x11111111,acc1 |
masaccs acc0,acc2 |
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set |
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set |
test_accg_immed 0,accg2 |
test_acc_limmed 0x2345,0x6789,acc2 |
test_accg_immed 0,accg3 |
test_acc_limmed 0x0123,0x4567,acc3 |
|
set_accg_immed 0,accg0 |
set_acc_immed 0x12345678,acc0 |
set_accg_immed 0,accg1 |
set_acc_immed 0xffffffff,acc1 |
masaccs acc0,acc2 |
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set |
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set |
test_accg_immed 1,accg2 |
test_acc_limmed 0x1234,0x5677,acc2 |
test_accg_immed 0xff,accg3 |
test_acc_limmed 0x1234,0x5679,acc3 |
|
set_accg_immed 0,accg0 |
set_acc_immed 0x12345678,acc0 |
set_accg_immed 0xff,accg1 |
set_acc_immed 0xffffffff,acc1 |
masaccs acc0,acc2 |
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set |
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set |
test_accg_immed 0,accg2 |
test_acc_limmed 0x1234,0x5677,acc2 |
test_accg_immed 0,accg3 |
test_acc_limmed 0x1234,0x5679,acc3 |
|
set_spr_immed 0,msr0 |
set_accg_immed 0x7f,accg0 |
set_acc_immed 0xfffe7ffe,acc0 |
set_accg_immed 0x0,accg1 |
set_acc_immed 0x00020001,acc1 |
masaccs acc0,acc2 |
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set |
test_spr_bits 2,1,1,msr0 ; msr0.ovf set |
test_spr_bits 1,0,1,msr0 ; msr0.aovf set |
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set |
test_accg_immed 0x7f,accg2 |
test_acc_limmed 0xffff,0xffff,acc2 |
test_accg_immed 0x7f,accg3 |
test_acc_limmed 0xfffc,0x7ffd,acc3 |
|
set_spr_immed 0,msr0 |
set_accg_immed 0x80,accg0 |
set_acc_immed 0x00000001,acc0 |
set_accg_immed 0xff,accg1 |
set_acc_immed 0xfffffffe,acc1 |
masaccs acc0,acc2 |
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set |
test_spr_bits 2,1,1,msr0 ; msr0.ovf set |
test_spr_bits 1,0,1,msr0 ; msr0.aovf set |
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set |
test_accg_immed 0x80,accg2 |
test_acc_limmed 0x0000,0x0000,acc2 |
test_accg_immed 0x80,accg3 |
test_acc_limmed 0x0000,0x0003,acc3 |
|
set_spr_immed 0,msr0 |
set_spr_immed 0,msr1 |
set_accg_immed 0,accg0 |
set_acc_immed 0x00000001,acc0 |
set_accg_immed 0,accg1 |
set_acc_immed 0x00000001,acc1 |
set_accg_immed 0,accg2 |
set_acc_immed 0x00000001,acc2 |
set_accg_immed 0x7f,accg3 |
set_acc_immed 0xffffffff,acc3 |
masaccs.p acc0,acc0 |
masaccs acc2,acc2 |
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set |
test_spr_bits 2,1,1,msr1 ; msr1.ovf set |
test_spr_bits 1,0,1,msr0 ; msr0.aovf set |
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set |
test_accg_immed 0,accg0 |
test_acc_limmed 0x0000,0x0002,acc0 |
test_accg_immed 0,accg1 |
test_acc_limmed 0x0000,0x0000,acc1 |
test_accg_immed 0x7f,accg2 |
test_acc_limmed 0xffff,0xffff,acc2 |
test_accg_immed 0x80,accg3 |
test_acc_limmed 0x0000,0x0002,acc3 |
|
pass |
/sdivi.cgs
0,0 → 1,70
# frv testcase for sdivi $GRi,$s12,$GRk |
# mach: all |
|
.include "../testutils.inc" |
|
start |
|
.global sdivi |
sdivi: |
; simple division 12 / 3 |
set_gr_immed 12,gr1 |
sdivi gr1,3,gr2 |
test_gr_immed 4,gr2 |
|
; Random example |
set_gr_limmed 0xfedc,0xba98,gr1 |
sdivi gr1,0x7ff,gr2 |
test_gr_limmed 0xffff,0xdb93,gr2 |
|
; Random negative example |
set_gr_limmed 0xfedc,0xba98,gr1 |
sdivi gr1,-2048,gr2 |
test_gr_immed 0x2468,gr2 |
|
; Special case from the Arch Spec Vol 2 |
or_spr_immed 0x20,isr ; turn on isr.edem |
set_gr_limmed 0x8000,0x0000,gr1 |
sdivi gr1,-1,gr2 |
test_gr_limmed 0x7fff,0xffff,gr2 |
test_spr_bits 0x4,2,1,isr ; isr.aexc is set |
|
and_spr_immed -33,isr ; turn off isr.edem |
; set up exception handler |
set_psr_et 1 |
and_spr_immed -4081,tbr ; clear tbr.tt |
set_gr_spr tbr,gr17 |
inc_gr_immed 0x170,gr17 ; address of exception handler |
set_bctrlr_0_0 gr17 |
set_spr_immed 128,lcr |
set_gr_immed 0,gr15 |
|
; divide will cause overflow |
set_spr_addr ok1,lr |
set_gr_limmed 0x8000,0x0000,gr1 |
e1: sdivi gr1,-1,gr2 |
test_gr_immed 1,gr15 |
test_gr_limmed 0x8000,0x0000,gr2 |
|
; divide by zero |
set_spr_addr ok2,lr |
e2: sdivi gr1,0,gr2 ; divide by zero |
test_gr_immed 2,gr15 |
|
pass |
|
ok1: ; exception handler for overflow |
test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set |
test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid |
test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set |
inc_gr_immed 1,gr15 |
rett 0 |
fail |
|
ok2: ; exception handler for divide by zero |
test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set |
test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid |
test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set |
inc_gr_immed 1,gr15 |
rett 0 |
fail |
/allinsn.exp
0,0 → 1,19
# FRV simulator testsuite. |
|
if [istarget frv*-*] { |
# load support procs (none yet) |
# load_lib cgen.exp |
# all machines |
set all_machs "fr400 fr405 fr450 fr550" |
set cpu_option -mcpu |
|
# The .cgs suffix is for "cgen .s". |
foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { |
# If we're only testing specific files and this isn't one of them, |
# skip it. |
if ![runtest_file_p $runtests $src] { |
continue |
} |
run_sim_test $src $all_machs |
} |
} |
/udivi.cgs
0,0 → 1,47
# frv testcase for udivi $GRi,$s12,$GRk |
# mach: fr400 |
|
.include "../testutils.inc" |
|
start |
|
.global udivi |
udivi: |
; simple division 12 / 3 |
set_gr_immed 0x0000000c,gr3 |
udivi gr3,3,gr3 |
test_gr_immed 0x00000004,gr3 |
|
; random example |
set_gr_limmed 0xfedc,0xba98,gr3 |
udivi gr3,0x7ff,gr3 |
test_gr_limmed 0x001f,0xdf93,gr3 |
|
; random example |
set_gr_limmed 0xffff,0xffff,gr3 |
udivi gr3,-2048,gr3 |
test_gr_immed 1,gr3 |
|
; set up exception handler |
set_psr_et 1 |
and_spr_immed -4081,tbr ; clear tbr.tt |
set_gr_spr tbr,gr17 |
inc_gr_immed 0x170,gr17 ; address of exception handler |
set_bctrlr_0_0 gr17 |
set_spr_immed 128,lcr |
set_gr_immed 0,gr15 |
|
; divide by zero |
set_spr_addr ok1,lr |
e1: udivi gr1,0,gr2 ; divide by zero |
test_gr_immed 1,gr15 |
|
pass |
|
ok1: ; exception handler for divide by zero |
test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set |
test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid |
test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set |
inc_gr_immed 1,gr15 |
rett 0 |
fail |
/mhsetloh.cgs
0,0 → 1,27
# frv testcase for mhsetloh $s12,$FRk |
# mach: all |
|
.include "../testutils.inc" |
|
start |
|
.global mhsetloh |
mhsetloh: |
set_fr_immed 0,fr1 |
mhsetloh 0,fr1 |
test_fr_iimmed 0,fr1 |
mhsetloh 1,fr1 |
test_fr_iimmed 0x0000800,fr1 |
mhsetloh 0xf,fr1 |
test_fr_iimmed 0x00007800,fr1 |
mhsetloh -16,fr1 |
test_fr_iimmed 0x00008000,fr1 |
mhsetloh -1,fr1 |
test_fr_iimmed 0x0000f800,fr1 |
|
; Try parallel write to both hi and lo |
mhsetloh.p 1,fr1 |
mhsethih 0xf,fr1 |
test_fr_iimmed 0x78000800,fr1 |
|
pass |
/scutss.cgs
0,0 → 1,664
# frv testcase for scutss $FRj,$FRk |
# mach: fr405 fr450 |
|
.include "../testutils.inc" |
|
start |
|
.global scutss |
scutss: |
set_spr_immed 0xffffffe7,iacc0h |
set_spr_immed 0x89abcdef,iacc0l |
|
set_gr_immed 0,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xffe8,gr11 |
|
set_gr_immed 1,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xffcf,gr11 |
|
set_gr_immed 2,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xff9e,gr11 |
|
set_gr_immed 3,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xff3c,gr11 |
|
set_gr_immed 4,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xfe79,gr11 |
|
set_gr_immed 5,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xfcf1,gr11 |
|
set_gr_immed 6,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xf9e2,gr11 |
|
set_gr_immed 7,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xf3c5,gr11 |
|
set_gr_immed 8,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xe78a,gr11 |
|
set_gr_immed 9,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xcf13,gr11 |
|
set_gr_immed 10,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0x9e27,gr11 |
|
set_gr_immed 11,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0x3c4d,gr11 |
|
set_gr_immed 12,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xfffe,0x789b,gr11 |
|
set_gr_immed 13,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xfffc,0xf135,gr11 |
|
set_gr_immed 14,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xfff9,0xe26b,gr11 |
|
set_gr_immed 15,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xfff3,0xc4d6,gr11 |
|
set_gr_immed 16,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffe7,0x89ac,gr11 |
|
set_gr_immed 17,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffcf,0x1358,gr11 |
|
set_gr_immed 18,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xff9e,0x26af,gr11 |
|
set_gr_immed 19,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xff3c,0x4d5e,gr11 |
|
set_gr_immed 20,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xfe78,0x9abd,gr11 |
|
set_gr_immed 21,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xfcf1,0x357a,gr11 |
|
set_gr_immed 22,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xf9e2,0x6af3,gr11 |
|
set_gr_immed 23,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xf3c4,0xd5e7,gr11 |
|
set_gr_immed 24,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xe789,0xabce,gr11 |
|
set_gr_immed 25,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xcf13,0x579c,gr11 |
|
set_gr_immed 26,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x9e26,0xaf38,gr11 |
|
set_gr_immed 27,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 28,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 29,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 30,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 31,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 32,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 33,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 34,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 35,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 36,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 37,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 38,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 39,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 40,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 41,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 42,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 43,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 44,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 45,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 46,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 47,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 48,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 49,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 50,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 51,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 52,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 53,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 54,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 55,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 56,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 57,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 58,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 59,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 60,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 61,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 62,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 63,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
set_gr_immed 64,gr10 ; same as -64 |
scutss gr10,gr11 |
test_gr_immed 0,gr11 |
|
set_gr_immed 128,gr10 ; same as 0 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xffe8,gr11 |
|
.global scutss2 |
scutss2: |
set_spr_immed 0xe789abcd,iacc0h |
set_spr_immed 0xefa5a5a5,iacc0l |
|
set_gr_limmed 0xffff,0xffff,gr10 ; -1 |
scutss gr10,gr11 |
test_gr_limmed 0xf3c4,0xd5e7,gr11 |
|
set_gr_limmed 0x0000,0x007e,gr10 ; -2 (only lower 7 bits matter) |
scutss gr10,gr11 |
test_gr_limmed 0xf9e2,0x6af3,gr11 |
|
set_gr_immed -3,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xfcf1,0x357a,gr11 |
|
set_gr_immed -4,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xfe78,0x9abd,gr11 |
|
set_gr_immed -5,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xff3c,0x4d5e,gr11 |
|
set_gr_immed -6,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xff9e,0x26af,gr11 |
|
set_gr_immed -7,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffcf,0x1358,gr11 |
|
set_gr_immed -8,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffe7,0x89ac,gr11 |
|
set_gr_immed -9,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xfff3,0xc4d6,gr11 |
|
set_gr_immed -10,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xfff9,0xe26b,gr11 |
|
set_gr_immed -11,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xfffc,0xf135,gr11 |
|
set_gr_immed -12,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xfffe,0x789b,gr11 |
|
set_gr_immed -13,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0x3c4d,gr11 |
|
set_gr_immed -14,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0x9e27,gr11 |
|
set_gr_immed -15,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xcf13,gr11 |
|
set_gr_immed -16,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xe78a,gr11 |
|
set_gr_immed -17,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xf3c5,gr11 |
|
set_gr_immed -18,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xf9e2,gr11 |
|
set_gr_immed -19,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xfcf1,gr11 |
|
set_gr_immed -20,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xfe79,gr11 |
|
set_gr_immed -21,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xff3c,gr11 |
|
set_gr_immed -22,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xff9e,gr11 |
|
set_gr_immed -23,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xffcf,gr11 |
|
set_gr_immed -24,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xffe8,gr11 |
|
set_gr_immed -25,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xfff4,gr11 |
|
set_gr_immed -26,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xfffa,gr11 |
|
set_gr_immed -27,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xfffd,gr11 |
|
set_gr_immed -28,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xfffe,gr11 |
|
set_gr_immed -29,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xffff,gr11 |
|
set_gr_immed -30,gr10 |
scutss gr10,gr11 |
test_gr_immed 0,gr11 |
|
set_gr_immed -31,gr10 |
scutss gr10,gr11 |
test_gr_immed 0,gr11 |
|
set_gr_immed -32,gr10 |
scutss gr10,gr11 |
test_gr_immed 0,gr11 |
|
set_gr_limmed 0,64,gr10 ; same as -32 |
scutss gr10,gr11 |
test_gr_immed 0,gr11 |
|
set_spr_immed 0x6789abcd,iacc0h |
set_spr_immed 0xefa5a5a5,iacc0l |
|
set_gr_limmed 0xffff,0xffff,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x33c4,0xd5e7,gr11 |
|
set_gr_limmed 0x0000,0x007e,gr10 ; -2 (only lower 7 bits matter) |
scutss gr10,gr11 |
test_gr_limmed 0x19e2,0x6af3,gr11 |
|
set_gr_immed -3,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0cf1,0x357a,gr11 |
|
set_gr_immed -4,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0678,0x9abd,gr11 |
|
set_gr_immed -5,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x033c,0x4d5e,gr11 |
|
set_gr_immed -6,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x019e,0x26af,gr11 |
|
set_gr_immed -7,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x00cf,0x1358,gr11 |
|
set_gr_immed -8,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0067,0x89ac,gr11 |
|
set_gr_immed -9,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0033,0xc4d6,gr11 |
|
set_gr_immed -10,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0019,0xe26b,gr11 |
|
set_gr_immed -11,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x000c,0xf135,gr11 |
|
set_gr_immed -12,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0006,0x789b,gr11 |
|
set_gr_immed -13,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0003,0x3c4d,gr11 |
|
set_gr_immed -14,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0001,0x9e27,gr11 |
|
set_gr_immed -15,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0000,0xcf13,gr11 |
|
set_gr_immed -16,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0000,0x678a,gr11 |
|
set_gr_immed -17,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0000,0x33c5,gr11 |
|
set_gr_immed -18,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0000,0x19e2,gr11 |
|
set_gr_immed -19,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0000,0x0cf1,gr11 |
|
set_gr_immed -20,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0000,0x0679,gr11 |
|
set_gr_immed -21,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0000,0x033c,gr11 |
|
set_gr_immed -22,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0000,0x019e,gr11 |
|
set_gr_immed -23,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0000,0x00cf,gr11 |
|
set_gr_immed -24,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0000,0x0068,gr11 |
|
set_gr_immed -25,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0000,0x0034,gr11 |
|
set_gr_immed -26,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0000,0x001a,gr11 |
|
set_gr_immed -27,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0000,0x000d,gr11 |
|
set_gr_immed -28,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0000,0x0006,gr11 |
|
set_gr_immed -29,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0000,0x0003,gr11 |
|
set_gr_immed -30,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0000,0x0002,gr11 |
|
set_gr_immed -31,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0000,0x0001,gr11 |
|
set_gr_immed -32,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x0000,0x0000,gr11 |
|
set_gr_immed 64,gr10 ; same as -32 |
scutss gr10,gr11 |
test_gr_limmed 0x0000,0x0000,gr11 |
|
; Examples from the customer (modified for iacc0) |
set_spr_immed 0xffffffff,iacc0h |
set_spr_immed 0xffe00000,iacc0l |
|
set_gr_limmed 0,16,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xffe0,gr11 |
|
set_gr_limmed 0,17,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xffc0,gr11 |
|
set_gr_limmed 0,18,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xff80,gr11 |
|
set_spr_immed 0,iacc0h |
set_spr_immed 0x003fffff,iacc0l |
|
set_gr_limmed 0,40,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x3fff,0xff00,gr11 |
|
set_gr_limmed 0,41,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x7fff,0xfe00,gr11 |
|
set_spr_immed 0x7f,iacc0h |
set_spr_immed 0xffe00000,iacc0l |
|
set_gr_limmed 0,40,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x7fff,0xffff,gr11 ; saturated |
|
set_gr_limmed 0,41,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x7fff,0xffff,gr11 ; saturated |
|
set_gr_limmed 0,42,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x7fff,0xffff,gr11 ; saturated |
|
set_spr_immed 0x08,iacc0h |
set_spr_immed 0x003fffff,iacc0l |
|
set_gr_limmed 0,40,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x7fff,0xffff,gr11 ; saturated |
|
set_gr_limmed 0,41,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x7fff,0xffff,gr11 ; saturated |
|
set_spr_immed 0xffffffff,iacc0h |
set_spr_immed 0xefe00000,iacc0l |
|
set_gr_limmed 0,40,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 ; saturated |
|
set_gr_limmed 0,41,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 ; saturated |
|
set_gr_limmed 0,42,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 ; saturated |
|
set_spr_immed 0x80000000,iacc0h |
set_spr_immed 0x003fffff,iacc0l |
|
set_gr_limmed 0,16,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 ; saturated |
|
set_gr_limmed 0,17,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 ; saturated |
|
set_spr_immed 0xaf5a5a5a,iacc0h |
set_spr_immed 0x5a5a5a5a,iacc0l |
|
set_gr_limmed 0xffff,0xfffc,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xfaf5,0xa5a6,gr11 |
|
set_spr_immed 0x2f5a5a5a,iacc0h |
set_spr_immed 0x5a5a5a5a,iacc0l |
|
set_gr_limmed 0xffff,0xfff9,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x005e,0xb4b5,gr11 |
|
# From the manual |
.global scutss3 |
scutss3: |
set_spr_immed 0xfffffedc,iacc0h |
set_spr_immed 0xba987654,iacc0l |
|
set_gr_immed 16,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xfedc,0xba98,gr11 |
|
set_gr_immed 12,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffed,0xcbaa,gr11 |
|
set_gr_immed -4,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0xffff,0xffee,gr11 |
|
set_gr_immed 24,gr10 |
scutss gr10,gr11 |
test_gr_limmed 0x8000,0x0000,gr11 |
|
pass |
/mhsethis.cgs
0,0 → 1,25
# frv testcase for mhsethis $s12,$FRk |
# mach: all |
|
.include "../testutils.inc" |
|
start |
|
.global mhsethis |
mhsethis: |
set_fr_immed 0,fr1 |
mhsethis 0,fr1 |
test_fr_iimmed 0,fr1 |
mhsethis 1,fr1 |
test_fr_iimmed 0x00010000,fr1 |
mhsethis 0x7ff,fr1 |
test_fr_iimmed 0x07ff0000,fr1 |
mhsethis -2048,fr1 |
test_fr_iimmed 0xf8000000,fr1 |
|
; Try parallel set of hi and lo at the same time |
mhsethis.p 1,fr1 |
mhsetlos 2,fr1 |
test_fr_iimmed 0x00010002,fr1 |
|
pass |
/slass.cgs
0,0 → 1,104
# frv testcase for slass $GRi,$GRj,$GRk |
# mach: fr405 fr450 |
|
.include "../testutils.inc" |
|
start |
|
.global sll |
slass0: |
set_gr_immed 0,gr7 ; Shift by 0 |
set_gr_immed 2,gr8 |
slass gr8,gr7,gr6 |
test_gr_immed 2,gr8 |
test_gr_immed 0,gr7 |
test_gr_immed 2,gr6 |
slass1: |
set_gr_immed 1,gr7 ; Shift by 1 |
set_gr_immed 2,gr8 |
slass gr8,gr7,gr6 |
test_gr_immed 2,gr8 |
test_gr_immed 1,gr7 |
test_gr_immed 4,gr6 |
|
slass2: |
set_gr_immed 31,gr7 ; Shift 1 by 31 |
set_gr_immed 1,gr8 |
slass gr8,gr7,gr6 |
test_gr_immed 1,gr8 |
test_gr_immed 31,gr7 |
test_gr_limmed 0x7fff,0xffff,gr6 |
|
slass3: |
set_gr_immed 31,gr7 ; Shift -1 by 31 |
set_gr_immed -1,gr8 |
slass gr8,gr7,gr6 |
test_gr_immed -1,gr8 |
test_gr_immed 31,gr7 |
test_gr_limmed 0x8000,0x0000,gr6 |
|
slass4: |
set_gr_immed 14,gr7 ; Shift 0xffff0000 by 14 |
set_gr_limmed 0xffff,0x0000,gr8 |
slass gr8,gr7,gr6 |
test_gr_limmed 0xffff,0x0000,gr8 |
test_gr_immed 14,gr7 |
test_gr_limmed 0xc000,0x0000,gr6 |
|
slass5: |
set_gr_immed 15,gr7 ; Shift 0xffff0000 by 15 |
set_gr_limmed 0xffff,0x0000,gr8 |
slass gr8,gr7,gr6 |
test_gr_limmed 0xffff,0x0000,gr8 |
test_gr_immed 15,gr7 |
test_gr_limmed 0x8000,0x0000,gr6 |
|
slass6: |
set_gr_immed 20,gr7 ; Shift 0xffff0000 by 20 |
set_gr_limmed 0xffff,0x0000,gr8 |
slass gr8,gr7,gr6 |
test_gr_limmed 0xffff,0x0000,gr8 |
test_gr_immed 20,gr7 |
test_gr_limmed 0x8000,0x0000,gr6 |
|
slass7: |
set_gr_immed 14,gr7 ; Shift 0x0000ffff by 14 |
set_gr_limmed 0x0000,0xffff,gr8 |
slass gr8,gr7,gr6 |
test_gr_limmed 0x0000,0xffff,gr8 |
test_gr_immed 14,gr7 |
test_gr_limmed 0x3fff,0xc000,gr6 |
|
slass8: |
set_gr_immed 15,gr7 ; Shift 0x0000ffff by 15 |
set_gr_limmed 0x0000,0xffff,gr8 |
slass gr8,gr7,gr6 |
test_gr_limmed 0x0000,0xffff,gr8 |
test_gr_immed 15,gr7 |
test_gr_limmed 0x7fff,0x8000,gr6 |
|
slass9: |
set_gr_immed 20,gr7 ; Shift 0x0000ffff by 20 |
set_gr_limmed 0x0000,0xffff,gr8 |
slass gr8,gr7,gr6 |
test_gr_limmed 0x0000,0xffff,gr8 |
test_gr_immed 20,gr7 |
test_gr_limmed 0x7fff,0xffff,gr6 |
|
slass10: |
set_gr_immed 30,gr7 ; Shift 1 by 30 |
set_gr_immed 1,gr8 |
slass gr8,gr7,gr6 |
test_gr_immed 1,gr8 |
test_gr_immed 30,gr7 |
test_gr_limmed 0x4000,0x0000,gr6 |
|
slass11: |
set_gr_immed 30,gr7 ; Shift -1 by 30 |
set_gr_immed -1,gr8 |
slass gr8,gr7,gr6 |
test_gr_immed -1,gr8 |
test_gr_immed 30,gr7 |
test_gr_limmed 0xc000,0000,gr6 |
|
pass |
/smass.cgs
0,0 → 1,359
# frv testcase for smass $GRi,$GRj |
# mach: fr405 fr450 |
|
.include "../testutils.inc" |
|
start |
|
.global smass |
smass1: |
; Positive operands |
set_gr_immed 3,gr7 ; multiply small numbers |
set_gr_immed 2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed 3,gr7 |
test_gr_immed 2,gr8 |
test_spr_immed 7,iacc0l ; result 3*2+1 |
test_spr_immed 0,iacc0h |
smass2: |
set_gr_immed 1,gr7 ; multiply by 1 |
set_gr_immed 2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed 1,gr7 |
test_gr_immed 2,gr8 |
test_spr_immed 3,iacc0l ; result 1*2+1 |
test_spr_immed 0,iacc0h |
smass3: |
set_gr_immed 2,gr7 ; multiply by 1 |
set_gr_immed 1,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed 1,gr8 |
test_gr_immed 2,gr7 |
test_spr_immed 3,iacc0l ; result 2*1+1 |
test_spr_immed 0,iacc0h |
smass4: |
set_gr_immed 0,gr7 ; multiply by 0 |
set_gr_immed 2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed 2,gr8 |
test_gr_immed 0,gr7 |
test_spr_immed 1,iacc0l ; result 0*2+1 |
test_spr_immed 0,iacc0h |
smass5: |
set_gr_immed 2,gr7 ; multiply by 0 |
set_gr_immed 0,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed 0,gr8 |
test_gr_immed 2,gr7 |
test_spr_immed 1,iacc0l ; result 2*0+1 |
test_spr_immed 0,iacc0h |
smass6: |
set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result |
set_gr_immed 2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed 2,gr8 |
test_gr_limmed 0x3fff,0xffff,gr7 |
test_spr_limmed 0x7fff,0xffff,iacc0l ; 3fffffff*2+1 |
test_spr_immed 0,iacc0h |
smass7: |
set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result |
set_gr_immed 2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed 2,gr8 |
test_gr_limmed 0x4000,0x0000,gr7 |
test_spr_limmed 0x8000,0x0001,iacc0l ; 40000000*2+1 |
test_spr_immed 0,iacc0h |
smass8: |
set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result |
set_gr_immed 4,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed 4,gr8 |
test_gr_limmed 0x4000,0x0000,gr7 |
test_spr_immed 1,iacc0l ; 40000000*4+1 |
test_spr_immed 1,iacc0h |
smass9: |
set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result |
set_gr_limmed 0x7fff,0xffff,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_limmed 0x7fff,0xffff,gr8 |
test_gr_limmed 0x7fff,0xffff,gr7 |
test_spr_immed 0x00000002,iacc0l ; 7fffffff*7fffffff+1 |
test_spr_limmed 0x3fff,0xffff,iacc0h |
smass10: |
; Mixed operands |
set_gr_immed -3,gr7 ; multiply small numbers |
set_gr_immed 2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed 2,gr8 |
test_gr_immed -3,gr7 |
test_spr_immed -5,iacc0l ; -3*2+1 |
test_spr_immed -1,iacc0h |
smass11: |
set_gr_immed 3,gr7 ; multiply small numbers |
set_gr_immed -2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_immed 3,gr7 |
test_spr_immed -5,iacc0l ; 3*-2+1 |
test_spr_immed -1,iacc0h |
smass12: |
set_gr_immed 1,gr7 ; multiply by 1 |
set_gr_immed -2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_immed 1,gr7 |
test_spr_immed -1,iacc0l ; 1*-2+1 |
test_spr_immed -1,iacc0h |
smass13: |
set_gr_immed -2,gr7 ; multiply by 1 |
set_gr_immed 1,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed 1,gr8 |
test_gr_immed -2,gr7 |
test_spr_immed -1,iacc0l ; -2*1+1 |
test_spr_immed -1,iacc0h |
smass14: |
set_gr_immed 0,gr7 ; multiply by 0 |
set_gr_immed -2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_immed 0,gr7 |
test_spr_immed 1,iacc0l ; 0*-2+1 |
test_spr_immed 0,iacc0h |
smass15: |
set_gr_immed -2,gr7 ; multiply by 0 |
set_gr_immed 0,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed 0,gr8 |
test_gr_immed -2,gr7 |
test_spr_immed 1,iacc0l ; -2*0+1 |
test_spr_immed 0,iacc0h |
smass16: |
set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result |
set_gr_immed -2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_limmed 0x2000,0x0001,gr7 |
test_spr_limmed 0xbfff,0xffff,iacc0l ; 20000001*-2+1 |
test_spr_limmed 0xffff,0xffff,iacc0h |
smass17: |
set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result |
set_gr_immed -2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_limmed 0x4000,0x0000,gr7 |
test_spr_limmed 0x8000,0x0001,iacc0l ; 40000000*-2+1 |
test_spr_limmed 0xffff,0xffff,iacc0h |
smass18: |
set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result |
set_gr_immed -2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_limmed 0x4000,0x0001,gr7 |
test_spr_limmed 0x7fff,0xffff,iacc0l ; 40000001*-2+1 |
test_spr_limmed 0xffff,0xffff,iacc0h |
smass19: |
set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result |
set_gr_immed -4,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed -4,gr8 |
test_gr_limmed 0x4000,0x0000,gr7 |
test_spr_limmed 0x0000,0x0001,iacc0l ; 40000000*-4+1 |
test_spr_limmed 0xffff,0xffff,iacc0h |
smass20: |
set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result |
set_gr_limmed 0x8000,0x0000,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_limmed 0x8000,0x0000,gr8 |
test_gr_limmed 0x7fff,0xffff,gr7 |
test_spr_limmed 0x8000,0x0001,iacc0l ; 7fffffff*80000000+1 |
test_spr_limmed 0xc000,0x0000,iacc0h |
smass21: |
; Negative operands |
set_gr_immed -3,gr7 ; multiply small numbers |
set_gr_immed -2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_immed -3,gr7 |
test_spr_immed 7,iacc0l ; -3*-2+1 |
test_spr_immed 0,iacc0h |
smass22: |
set_gr_immed -1,gr7 ; multiply by 1 |
set_gr_immed -2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_immed -1,gr7 |
test_spr_immed 3,iacc0l ; -1*-2+1 |
test_spr_immed 0,iacc0h |
smass23: |
set_gr_immed -2,gr7 ; multiply by 1 |
set_gr_immed -1,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed -1,gr8 |
test_gr_immed -2,gr7 |
test_spr_immed 3,iacc0l ; -2*-1+1 |
test_spr_immed 0,iacc0h |
smass24: |
set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result |
set_gr_immed -2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_limmed 0xc000,0x0001,gr7 |
test_spr_limmed 0x7fff,0xffff,iacc0l ; c0000001*-2+1 |
test_spr_immed 0,iacc0h |
smass25: |
set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result |
set_gr_immed -2,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed -2,gr8 |
test_gr_limmed 0xc000,0x0000,gr7 |
test_spr_limmed 0x8000,0x0001,iacc0l ; c0000000*-2+1 |
test_spr_immed 0,iacc0h |
smass26: |
set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result |
set_gr_immed -4,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_immed -4,gr8 |
test_gr_limmed 0xc000,0x0000,gr7 |
test_spr_immed 0x00000001,iacc0l ; c0000000*-4+1 |
test_spr_immed 1,iacc0h |
smass27: |
set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result |
set_gr_limmed 0x8000,0x0001,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_limmed 0x8000,0x0001,gr8 |
test_gr_limmed 0x8000,0x0001,gr7 |
test_spr_immed 0x00000002,iacc0l ; 80000001*80000001+1 |
test_spr_limmed 0x3fff,0xffff,iacc0h |
smass28: |
set_gr_limmed 0x8000,0x0000,gr7 ; max positive result |
set_gr_limmed 0x8000,0x0000,gr8 |
set_spr_immed 0,iacc0h |
set_spr_immed 1,iacc0l |
smass gr7,gr8 |
test_gr_limmed 0x8000,0x0000,gr8 |
test_gr_limmed 0x8000,0x0000,gr7 |
test_spr_immed 0x00000001,iacc0l ; 80000000*80000000+1 |
test_spr_limmed 0x4000,0x0000,iacc0h |
|
smass29: |
set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (pos) |
set_gr_limmed 0x7fff,0xffff,gr8 |
set_spr_limmed 0xffff,0xfffe,iacc0l |
set_spr_limmed 0x4000,0x0000,iacc0h |
smass gr7,gr8 |
test_gr_limmed 0x7fff,0xffff,gr8 |
test_gr_limmed 0x7fff,0xffff,gr7 |
test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+ |
test_spr_limmed 0x7fff,0xffff,iacc0h ; 40000000fffffffe |
|
smass30: |
set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (pos) |
set_gr_limmed 0x7fff,0xffff,gr8 |
set_spr_limmed 0xffff,0xffff,iacc0l |
set_spr_limmed 0x4000,0x0000,iacc0h |
smass gr7,gr8 |
test_gr_limmed 0x7fff,0xffff,gr8 |
test_gr_limmed 0x7fff,0xffff,gr7 |
test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+ |
test_spr_limmed 0x7fff,0xffff,iacc0h ; 40000000ffffffff |
|
smass31: |
set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (pos) |
set_gr_limmed 0x7fff,0xffff,gr8 |
set_spr_limmed 0xffff,0xffff,iacc0l |
set_spr_limmed 0x7fff,0xffff,iacc0h |
smass gr7,gr8 |
test_gr_limmed 0x7fff,0xffff,gr8 |
test_gr_limmed 0x7fff,0xffff,gr7 |
test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+ |
test_spr_limmed 0x7fff,0xffff,iacc0h ; 7fffffffffffffff |
|
smass32: |
set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (neg) |
set_gr_limmed 0x8000,0x0000,gr8 |
set_spr_limmed 0x8000,0x0000,iacc0l |
set_spr_limmed 0xbfff,0xffff,iacc0h |
smass gr7,gr8 |
test_gr_limmed 0x8000,0x0000,gr8 |
test_gr_limmed 0x7fff,0xffff,gr7 |
test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ |
test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff80000000 |
|
smass33: |
set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (neg) |
set_gr_limmed 0x8000,0x0000,gr8 |
set_spr_limmed 0x7fff,0xffff,iacc0l |
set_spr_limmed 0xbfff,0xffff,iacc0h |
smass gr7,gr8 |
test_gr_limmed 0x8000,0x0000,gr8 |
test_gr_limmed 0x7fff,0xffff,gr7 |
test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ |
test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff7fffffff |
|
smass34: |
set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (neg) |
set_gr_limmed 0x8000,0x0000,gr8 |
set_spr_limmed 0x0000,0x0000,iacc0l |
set_spr_limmed 0x8000,0x0000,iacc0h |
smass gr7,gr8 |
test_gr_limmed 0x8000,0x0000,gr8 |
test_gr_limmed 0x7fff,0xffff,gr7 |
test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ |
test_spr_limmed 0x8000,0x0000,iacc0h ; 8000000000000000 |
|
pass |
/movsg.cgs
0,0 → 1,65
# frv testcase for movsg iacc0[hl],$GRj |
# mach: fr400 |
|
.include "../testutils.inc" |
|
start |
|
.global movsg |
Iacc0h: |
set_spr_limmed 0xdead,0xbeef,iacc0h |
set_gr_limmed 0,0,gr8 |
movsg iacc0h,gr8 |
test_gr_limmed 0xdead,0xbeef,gr8 |
test_spr_limmed 0xdead,0xbeef,iacc0h |
Iacc0l: |
set_spr_limmed 0xdead,0xbeef,iacc0l |
set_gr_limmed 0,0,gr8 |
movsg iacc0l,gr8 |
test_gr_limmed 0xdead,0xbeef,gr8 |
test_spr_limmed 0xdead,0xbeef,iacc0l |
|
Spr280: |
set_spr_limmed 0xdead,0xbeef,spr[280] |
set_gr_limmed 0,0,gr8 |
movsg spr[280],gr8 |
test_gr_limmed 0xdead,0xbeef,gr8 |
test_spr_limmed 0xdead,0xbeef,spr[280] |
Spr281: |
set_spr_limmed 0xdead,0xbeef,spr[281] |
set_gr_limmed 0,0,gr8 |
movsg spr[281],gr8 |
test_gr_limmed 0xdead,0xbeef,gr8 |
test_spr_limmed 0xdead,0xbeef,spr[281] |
|
Iacc0h_spr280: |
set_spr_limmed 0xdead,0xbeef,spr[280] |
set_spr_limmed 0xdead,0xbeef,iacc0h |
set_gr_limmed 0,0,gr8 |
movsg iacc0h,gr8 |
test_gr_limmed 0xdead,0xbeef,gr8 |
test_spr_limmed 0xdead,0xbeef,spr[280] |
Iacc0l_spr281: |
set_spr_limmed 0xdead,0xbeef,spr[281] |
set_spr_limmed 0xdead,0xbeef,iacc0l |
set_gr_limmed 0,0,gr8 |
movsg iacc0l,gr8 |
test_gr_limmed 0xdead,0xbeef,gr8 |
test_spr_limmed 0xdead,0xbeef,spr[281] |
|
Spr280_iacc0h: |
set_spr_limmed 0xdead,0xbeef,spr[280] |
set_spr_limmed 0xdead,0xbeef,iacc0h |
set_gr_limmed 0,0,gr8 |
movsg spr[280],gr8 |
test_gr_limmed 0xdead,0xbeef,gr8 |
test_spr_limmed 0xdead,0xbeef,iacc0h |
Spr281_iacc0l: |
set_spr_limmed 0xdead,0xbeef,spr[281] |
set_spr_limmed 0xdead,0xbeef,iacc0l |
set_gr_limmed 0,0,gr8 |
movsg spr[281],gr8 |
test_gr_limmed 0xdead,0xbeef,gr8 |
test_spr_limmed 0xdead,0xbeef,iacc0l |
|
pass |
/movgs.cgs
0,0 → 1,50
# frv testcase for movgs $GRj,iacc0[hl] |
# mach: fr400 |
|
.include "../testutils.inc" |
|
start |
|
.global movgs |
IACC0H: |
set_gr_limmed 0xdead,0xbeef,gr8 |
and_spr_immed 0,iacc0h |
movgs gr8,iacc0h |
test_gr_limmed 0xdead,0xbeef,gr8 |
test_spr_limmed 0xdead,0xbeef,iacc0h |
SPR280: |
; try alternate names for iacc0h |
and_spr_immed 0,280 |
movgs gr8,spr[280] ; iacc0h is spr number 280 |
test_gr_limmed 0xdead,0xbeef,gr8 |
test_spr_limmed 0xdead,0xbeef,spr[280] |
|
IACC0L: |
set_gr_limmed 0xdead,0xbeef,gr8 |
and_spr_immed 0,iacc0l |
movgs gr8,iacc0l |
test_gr_limmed 0xdead,0xbeef,gr8 |
test_spr_limmed 0xdead,0xbeef,iacc0l |
SPR281: |
; try alternate names for iacc0l |
and_spr_immed 0,281 |
movgs gr8,spr[281] ; iacc0l is spr number 281 |
test_gr_limmed 0xdead,0xbeef,gr8 |
test_spr_limmed 0xdead,0xbeef,spr[281] |
|
IACC0L_SPR281: |
; try crossing between iacc0l and spr[281] |
and_spr_immed 0,281 |
and_spr_immed 0,iacc0l |
movgs gr8,spr[281] ; iacc0l is spr number 281 |
test_gr_limmed 0xdead,0xbeef,gr8 |
test_spr_limmed 0xdead,0xbeef,iacc0l |
|
SPR280_IACC0H: |
and_spr_immed 0,280 |
and_spr_immed 0,iacc0h |
movgs gr8,iacc0h ; iacc0h is spr number 280 |
test_gr_limmed 0xdead,0xbeef,gr8 |
test_spr_limmed 0xdead,0xbeef,spr[280] |
|
pass |
/mhdseth.cgs
0,0 → 1,22
# frv testcase for mhdseth $s12,$FRk |
# mach: all |
|
.include "../testutils.inc" |
|
start |
|
.global mhdseth |
mhdseth: |
set_fr_immed 0,fr1 |
mhdseth 0,fr1 |
test_fr_iimmed 0,fr1 |
mhdseth 1,fr1 |
test_fr_iimmed 0x08000800,fr1 |
mhdseth 0xf,fr1 |
test_fr_iimmed 0x78007800,fr1 |
mhdseth -16,fr1 |
test_fr_iimmed 0x80008000,fr1 |
mhdseth -1,fr1 |
test_fr_iimmed 0xf800f800,fr1 |
|
pass |
/mhsetlos.cgs
0,0 → 1,25
# frv testcase for mhsetlos $s12,$FRk |
# mach: all |
|
.include "../testutils.inc" |
|
start |
|
.global mhsetlos |
mhsetlos: |
set_fr_immed 0,fr1 |
mhsetlos 0,fr1 |
test_fr_iimmed 0,fr1 |
mhsetlos 1,fr1 |
test_fr_iimmed 0x00000001,fr1 |
mhsetlos 0x7ff,fr1 |
test_fr_iimmed 0x000007ff,fr1 |
mhsetlos -2048,fr1 |
test_fr_iimmed 0x0000f800,fr1 |
|
; Try parallel set of hi and lo at the same time |
mhsethis.p 1,fr1 |
mhsetlos 2,fr1 |
test_fr_iimmed 0x00010002,fr1 |
|
pass |
/addss.cgs
0,0 → 1,36
# frv testcase for addss $GRi,$GRj,$GRk |
# mach: fr405 fr450 |
|
.include "../testutils.inc" |
|
start |
|
.global add |
add_nosaturate: |
set_gr_immed 1,gr7 |
set_gr_immed 2,gr8 |
addss gr7,gr8,gr8 |
test_gr_immed 3,gr8 |
add_saturate_pos: |
set_gr_limmed 0x7fff,0xffff,gr7 |
set_gr_immed 1,gr8 |
addss gr7,gr8,gr8 |
test_gr_limmed 0x7fff,0xffff,gr8 |
|
set_gr_limmed 0x4000,0x0000,gr7 |
set_gr_limmed 0x4000,0x0000,gr8 |
addss gr7,gr8,gr8 |
test_gr_limmed 0x7fff,0xffff,gr8 |
|
add_saturate_neg: |
set_gr_limmed 0x8000,0x0000,gr7 |
set_gr_limmed 0xffff,0xffff,gr8 |
addss gr7,gr8,gr8 |
test_gr_limmed 0x8000,0x0000,gr8 |
|
set_gr_limmed 0x8000,0x0001,gr7 |
set_gr_limmed 0x8000,0x0001,gr8 |
addss gr7,gr8,gr8 |
test_gr_limmed 0x8000,0x0000,gr8 |
|
pass |
/maddaccs.cgs
0,0 → 1,131
# frv testcase for maddaccs $ACC40Si,$ACC40Sk |
# mach: fr400 |
|
.include "../testutils.inc" |
|
start |
|
.global maddaccs |
maddaccs: |
set_accg_immed 0,accg0 |
set_acc_immed 0x00000000,acc0 |
set_accg_immed 0,accg1 |
set_acc_immed 0x00000000,acc1 |
maddaccs acc0,acc3 |
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set |
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set |
test_accg_immed 0,accg3 |
test_acc_limmed 0x0000,0x0000,acc3 |
|
set_accg_immed 0,accg0 |
set_acc_immed 0xdead0000,acc0 |
set_accg_immed 0,accg1 |
set_acc_immed 0x0000beef,acc1 |
maddaccs acc0,acc3 |
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set |
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set |
test_accg_immed 0,accg3 |
test_acc_limmed 0xdead,0xbeef,acc3 |
|
set_accg_immed 0,accg0 |
set_acc_immed 0x0000dead,acc0 |
set_accg_immed 0,accg1 |
set_acc_immed 0xbeef0000,acc1 |
maddaccs acc0,acc3 |
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set |
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set |
test_accg_immed 0,accg3 |
test_acc_limmed 0xbeef,0xdead,acc3 |
|
set_accg_immed 0,accg0 |
set_acc_immed 0x12345678,acc0 |
set_accg_immed 0,accg1 |
set_acc_immed 0x11111111,acc1 |
maddaccs acc0,acc3 |
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set |
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set |
test_accg_immed 0,accg3 |
test_acc_limmed 0x2345,0x6789,acc3 |
|
set_accg_immed 0,accg0 |
set_acc_immed 0x12345678,acc0 |
set_accg_immed 0,accg1 |
set_acc_immed 0xffffffff,acc1 |
maddaccs acc0,acc3 |
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set |
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set |
test_accg_immed 1,accg3 |
test_acc_limmed 0x1234,0x5677,acc3 |
|
set_accg_immed 0,accg0 |
set_acc_immed 0x12345678,acc0 |
set_accg_immed 0xff,accg1 |
set_acc_immed 0xffffffff,acc1 |
maddaccs acc0,acc3 |
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set |
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set |
test_accg_immed 0,accg3 |
test_acc_limmed 0x1234,0x5677,acc3 |
|
set_spr_immed 0,msr0 |
set_accg_immed 0x7f,accg0 |
set_acc_immed 0xfffe7ffe,acc0 |
set_accg_immed 0x0,accg1 |
set_acc_immed 0x00020001,acc1 |
maddaccs acc0,acc3 |
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set |
test_spr_bits 2,1,1,msr0 ; msr0.ovf set |
test_spr_bits 1,0,1,msr0 ; msr0.aovf set |
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set |
test_accg_immed 0x7f,accg3 |
test_acc_limmed 0xffff,0xffff,acc3 |
|
set_spr_immed 0,msr0 |
set_accg_immed 0x80,accg0 |
set_acc_immed 0x00000001,acc0 |
set_accg_immed 0xff,accg1 |
set_acc_immed 0xfffffffe,acc1 |
maddaccs acc0,acc3 |
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set |
test_spr_bits 2,1,1,msr0 ; msr0.ovf set |
test_spr_bits 1,0,1,msr0 ; msr0.aovf set |
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set |
test_accg_immed 0x80,accg3 |
test_acc_limmed 0x0000,0x0000,acc3 |
|
set_spr_immed 0,msr0 |
set_spr_immed 0,msr1 |
set_accg_immed 0,accg0 |
set_acc_immed 0x00000001,acc0 |
set_accg_immed 0,accg1 |
set_acc_immed 0x00000001,acc1 |
set_accg_immed 0,accg2 |
set_acc_immed 0x00000001,acc2 |
set_accg_immed 0x7f,accg3 |
set_acc_immed 0xffffffff,acc3 |
maddaccs.p acc0,acc1 |
maddaccs acc2,acc3 |
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set |
test_spr_bits 2,1,1,msr1 ; msr1.ovf set |
test_spr_bits 1,0,1,msr0 ; msr0.aovf set |
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set |
test_accg_immed 0,accg1 |
test_acc_limmed 0x0000,0x0002,acc1 |
test_accg_immed 0x7f,accg3 |
test_acc_limmed 0xffff,0xffff,acc3 |
|
pass |
/subss.cgs
0,0 → 1,43
# frv testcase for subss $GRi,$GRj,$GRk |
# mach: fr405 fr450 |
|
.include "../testutils.inc" |
|
start |
|
.global sub |
sub_no_saturate: |
set_gr_immed 1,gr7 |
set_gr_immed 2,gr8 |
subss gr8,gr7,gr8 |
test_gr_immed 1,gr8 |
|
set_gr_immed 2,gr7 |
set_gr_immed 1,gr8 |
subss gr8,gr7,gr8 |
test_gr_limmed 0xffff,0xffff,gr8 |
|
sub_saturate_neg: |
set_gr_immed 1,gr7 |
set_gr_limmed 0x8000,0x0000,gr8 |
subss gr8,gr7,gr8 |
test_gr_limmed 0x8000,0x0000,gr8 |
|
set_gr_limmed 0x7fff,0xffff,gr7 |
set_gr_limmed 0xffff,0xfff0,gr8 |
subss gr8,gr7,gr8 |
test_gr_limmed 0x8000,0x0000,gr8 |
|
sub_saturate_pos: |
set_gr_limmed 0xffff,0xffff,gr7 |
set_gr_limmed 0x7fff,0xffff,gr8 |
subss gr8,gr7,gr8 |
test_gr_limmed 0x7fff,0xffff,gr8 |
|
set_gr_immed 0x0010,gr8 |
set_gr_limmed 0x8000,0x0000,gr7 |
subss gr8,gr7,gr8 |
test_gr_limmed 0x7fff,0xffff,gr8 |
|
|
pass |
/maveh.cgs
0,0 → 1,319
# frv testcase for maveh $FRi,$FRj,$FRj on fr400 machines |
# mach: all |
|
.include "../testutils.inc" |
|
start |
|
.global maveh |
maveh: |
; Test Rounding toward positive infinity via RDAV |
or_spr_immed 0x20000000,msr0 |
and_spr_immed 0xefffffff,msr0 |
|
set_fr_iimmed 0x0000,0x0000,fr10 |
set_fr_iimmed 0x0000,0x0000,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x0000,0x0000,fr12 |
|
set_fr_iimmed 0x0001,0x0000,fr10 |
set_fr_iimmed 0x0002,0x0001,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x0002,0x0001,fr12 |
|
set_fr_iimmed 0x0000,0xffff,fr10 |
set_fr_iimmed 0xffff,0xfffe,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x0000,0xffff,fr12 |
|
set_fr_iimmed 0xdead,0x0000,fr10 |
set_fr_iimmed 0x0000,0xbeef,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xef57,0xdf78,fr12 |
|
set_fr_iimmed 0x0000,0xdead,fr10 |
set_fr_iimmed 0xbeef,0x0000,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xdf78,0xef57,fr12 |
|
set_fr_iimmed 0x1234,0x5678,fr10 |
set_fr_iimmed 0x1111,0x1111,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x11a3,0x33c5,fr12 |
|
set_fr_iimmed 0x1234,0x5678,fr10 |
set_fr_iimmed 0xffff,0xffff,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x091a,0x2b3c,fr12 |
|
set_fr_iimmed 0x7ffe,0x7ffe,fr10 |
set_fr_iimmed 0x0002,0x0001,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x4000,0x4000,fr12 |
|
set_fr_iimmed 0x8001,0x8001,fr10 |
set_fr_iimmed 0xffff,0xfffe,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xc000,0xc000,fr12 |
|
set_fr_iimmed 0x8001,0x8001,fr10 |
set_fr_iimmed 0xfffe,0xfffe,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xc000,0xc000,fr12 |
|
set_fr_iimmed 0x8000,0x8000,fr10 |
set_fr_iimmed 0x7fff,0x7fff,fr11 |
maveh.p fr10,fr10,fr12 |
maveh fr11,fr11,fr13 |
test_fr_limmed 0x8000,0x8000,fr12 |
test_fr_limmed 0x7fff,0x7fff,fr13 |
|
; Test Rounding toward nearest via RD |
or_spr_immed 0x10000000,msr0 |
and_spr_immed 0x3fffffff,msr0 |
|
set_fr_iimmed 0x0000,0x0000,fr10 |
set_fr_iimmed 0x0000,0x0000,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x0000,0x0000,fr12 |
|
set_fr_iimmed 0x0001,0x0000,fr10 |
set_fr_iimmed 0x0002,0x0001,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x0002,0x0001,fr12 |
|
set_fr_iimmed 0x0000,0xffff,fr10 |
set_fr_iimmed 0xffff,0xfffe,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xffff,0xfffe,fr12 |
|
set_fr_iimmed 0xdead,0x0000,fr10 |
set_fr_iimmed 0x0000,0xbeef,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xef56,0xdf77,fr12 |
|
set_fr_iimmed 0x0000,0xdead,fr10 |
set_fr_iimmed 0xbeef,0x0000,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xdf77,0xef56,fr12 |
|
set_fr_iimmed 0x1234,0x5678,fr10 |
set_fr_iimmed 0x1111,0x1111,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x11a3,0x33c5,fr12 |
|
set_fr_iimmed 0x1234,0x5678,fr10 |
set_fr_iimmed 0xffff,0xffff,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x091a,0x2b3c,fr12 |
|
set_fr_iimmed 0x7ffe,0x7ffe,fr10 |
set_fr_iimmed 0x0002,0x0001,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x4000,0x4000,fr12 |
|
set_fr_iimmed 0x8001,0x8001,fr10 |
set_fr_iimmed 0xffff,0xfffe,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xc000,0xbfff,fr12 |
|
set_fr_iimmed 0x8001,0x8001,fr10 |
set_fr_iimmed 0xfffe,0xfffe,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xbfff,0xbfff,fr12 |
|
set_fr_iimmed 0x8000,0x8000,fr10 |
set_fr_iimmed 0x7fff,0x7fff,fr11 |
maveh.p fr10,fr10,fr12 |
maveh fr11,fr11,fr13 |
test_fr_limmed 0x8000,0x8000,fr12 |
test_fr_limmed 0x7fff,0x7fff,fr13 |
|
; Test Rounding toward zero via RD |
or_spr_immed 0x50000000,msr0 |
and_spr_immed 0x7fffffff,msr0 |
|
set_fr_iimmed 0x0000,0x0000,fr10 |
set_fr_iimmed 0x0000,0x0000,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x0000,0x0000,fr12 |
|
set_fr_iimmed 0x0001,0x0000,fr10 |
set_fr_iimmed 0x0002,0x0001,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x0001,0x0000,fr12 |
|
set_fr_iimmed 0x0000,0xffff,fr10 |
set_fr_iimmed 0xffff,0xfffe,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x0000,0xffff,fr12 |
|
set_fr_iimmed 0xdead,0x0000,fr10 |
set_fr_iimmed 0x0000,0xbeef,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xef57,0xdf78,fr12 |
|
set_fr_iimmed 0x0000,0xdead,fr10 |
set_fr_iimmed 0xbeef,0x0000,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xdf78,0xef57,fr12 |
|
set_fr_iimmed 0x1234,0x5678,fr10 |
set_fr_iimmed 0x1111,0x1111,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x11a2,0x33c4,fr12 |
|
set_fr_iimmed 0x1234,0x5678,fr10 |
set_fr_iimmed 0xffff,0xffff,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x0919,0x2b3b,fr12 |
|
set_fr_iimmed 0x7ffe,0x7ffe,fr10 |
set_fr_iimmed 0x0002,0x0001,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x4000,0x3fff,fr12 |
|
set_fr_iimmed 0x8001,0x8001,fr10 |
set_fr_iimmed 0xffff,0xfffe,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xc000,0xc000,fr12 |
|
set_fr_iimmed 0x8001,0x8001,fr10 |
set_fr_iimmed 0xfffe,0xfffe,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xc000,0xc000,fr12 |
|
set_fr_iimmed 0x8000,0x8000,fr10 |
set_fr_iimmed 0x7fff,0x7fff,fr11 |
maveh.p fr10,fr10,fr12 |
maveh fr11,fr11,fr13 |
test_fr_limmed 0x8000,0x8000,fr12 |
test_fr_limmed 0x7fff,0x7fff,fr13 |
|
; Test Rounding toward positive infinity via RD |
or_spr_immed 0x90000000,msr0 |
and_spr_immed 0xbfffffff,msr0 |
|
set_fr_iimmed 0x0000,0x0000,fr10 |
set_fr_iimmed 0x0000,0x0000,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x0000,0x0000,fr12 |
|
set_fr_iimmed 0x0001,0x0000,fr10 |
set_fr_iimmed 0x0002,0x0001,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x0002,0x0001,fr12 |
|
set_fr_iimmed 0x0000,0xffff,fr10 |
set_fr_iimmed 0xffff,0xfffe,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x0000,0xffff,fr12 |
|
set_fr_iimmed 0xdead,0x0000,fr10 |
set_fr_iimmed 0x0000,0xbeef,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xef57,0xdf78,fr12 |
|
set_fr_iimmed 0x0000,0xdead,fr10 |
set_fr_iimmed 0xbeef,0x0000,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xdf78,0xef57,fr12 |
|
set_fr_iimmed 0x1234,0x5678,fr10 |
set_fr_iimmed 0x1111,0x1111,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x11a3,0x33c5,fr12 |
|
set_fr_iimmed 0x1234,0x5678,fr10 |
set_fr_iimmed 0xffff,0xffff,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x091a,0x2b3c,fr12 |
|
set_fr_iimmed 0x7ffe,0x7ffe,fr10 |
set_fr_iimmed 0x0002,0x0001,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x4000,0x4000,fr12 |
|
set_fr_iimmed 0x8001,0x8001,fr10 |
set_fr_iimmed 0xffff,0xfffe,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xc000,0xc000,fr12 |
|
set_fr_iimmed 0x8001,0x8001,fr10 |
set_fr_iimmed 0xfffe,0xfffe,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xc000,0xc000,fr12 |
|
set_fr_iimmed 0x8000,0x8000,fr10 |
set_fr_iimmed 0x7fff,0x7fff,fr11 |
maveh.p fr10,fr10,fr12 |
maveh fr11,fr11,fr13 |
test_fr_limmed 0x8000,0x8000,fr12 |
test_fr_limmed 0x7fff,0x7fff,fr13 |
|
; Test Rounding toward negative infinity via RD |
or_spr_immed 0xd0000000,msr0 |
|
set_fr_iimmed 0x0000,0x0000,fr10 |
set_fr_iimmed 0x0000,0x0000,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x0000,0x0000,fr12 |
|
set_fr_iimmed 0x0001,0x0000,fr10 |
set_fr_iimmed 0x0002,0x0001,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x0001,0x0000,fr12 |
|
set_fr_iimmed 0x0000,0xffff,fr10 |
set_fr_iimmed 0xffff,0xfffe,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xffff,0xfffe,fr12 |
|
set_fr_iimmed 0xdead,0x0000,fr10 |
set_fr_iimmed 0x0000,0xbeef,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xef56,0xdf77,fr12 |
|
set_fr_iimmed 0x0000,0xdead,fr10 |
set_fr_iimmed 0xbeef,0x0000,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xdf77,0xef56,fr12 |
|
set_fr_iimmed 0x1234,0x5678,fr10 |
set_fr_iimmed 0x1111,0x1111,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x11a2,0x33c4,fr12 |
|
set_fr_iimmed 0x1234,0x5678,fr10 |
set_fr_iimmed 0xffff,0xffff,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x0919,0x2b3b,fr12 |
|
set_spr_immed 0,msr0 |
set_fr_iimmed 0x7ffe,0x7ffe,fr10 |
set_fr_iimmed 0x0002,0x0001,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0x4000,0x3fff,fr12 |
|
set_spr_immed 0,msr0 |
set_fr_iimmed 0x8001,0x8001,fr10 |
set_fr_iimmed 0xffff,0xfffe,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xc000,0xbfff,fr12 |
|
set_spr_immed 0,msr0 |
set_fr_iimmed 0x8001,0x8001,fr10 |
set_fr_iimmed 0xfffe,0xfffe,fr11 |
maveh fr10,fr11,fr12 |
test_fr_limmed 0xbfff,0xbfff,fr12 |
|
set_spr_immed 0,msr0 |
set_spr_immed 0,msr1 |
set_fr_iimmed 0x8000,0x8000,fr10 |
set_fr_iimmed 0x7fff,0x7fff,fr11 |
maveh.p fr10,fr10,fr12 |
maveh fr11,fr11,fr13 |
test_fr_limmed 0x8000,0x8000,fr12 |
test_fr_limmed 0x7fff,0x7fff,fr13 |
|
pass |
/msubaccs.cgs
0,0 → 1,131
# frv testcase for msubaccs $ACC40Si,$ACC40Sk |
# mach: fr400 |
|
.include "../testutils.inc" |
|
start |
|
.global msubaccs |
msubaccs: |
set_accg_immed 0,accg0 |
set_acc_immed 0x00000000,acc0 |
set_accg_immed 0,accg1 |
set_acc_immed 0x00000000,acc1 |
msubaccs acc0,acc3 |
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set |
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set |
test_accg_immed 0,accg3 |
test_acc_limmed 0x0000,0x0000,acc3 |
|
set_accg_immed 0,accg0 |
set_acc_immed 0xdead0000,acc0 |
set_accg_immed 0,accg1 |
set_acc_immed 0x0000beef,acc1 |
msubaccs acc0,acc3 |
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set |
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set |
test_accg_immed 0,accg3 |
test_acc_limmed 0xdeac,0x4111,acc3 |
|
set_accg_immed 0,accg0 |
set_acc_immed 0x0000dead,acc0 |
set_accg_immed 0,accg1 |
set_acc_immed 0xbeef0000,acc1 |
msubaccs acc0,acc3 |
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set |
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set |
test_accg_immed 0xff,accg3 |
test_acc_limmed 0x4111,0xdead,acc3 |
|
set_accg_immed 0,accg0 |
set_acc_immed 0x12345678,acc0 |
set_accg_immed 0,accg1 |
set_acc_immed 0x11111111,acc1 |
msubaccs acc0,acc3 |
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set |
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set |
test_accg_immed 0,accg3 |
test_acc_limmed 0x0123,0x4567,acc3 |
|
set_accg_immed 0,accg0 |
set_acc_immed 0x12345678,acc0 |
set_accg_immed 0,accg1 |
set_acc_immed 0xffffffff,acc1 |
msubaccs acc0,acc3 |
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set |
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set |
test_accg_immed 0xff,accg3 |
test_acc_limmed 0x1234,0x5679,acc3 |
|
set_accg_immed 0,accg0 |
set_acc_immed 0x12345678,acc0 |
set_accg_immed 0xff,accg1 |
set_acc_immed 0xffffffff,acc1 |
msubaccs acc0,acc3 |
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set |
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set |
test_accg_immed 0,accg3 |
test_acc_limmed 0x1234,0x5679,acc3 |
|
set_spr_immed 0,msr0 |
set_accg_immed 0x7f,accg0 |
set_acc_immed 0xfffffffe,acc0 |
set_accg_immed 0xff,accg1 |
set_acc_immed 0xfffffffe,acc1 |
msubaccs acc0,acc3 |
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set |
test_spr_bits 2,1,1,msr0 ; msr0.ovf set |
test_spr_bits 1,0,1,msr0 ; msr0.aovf set |
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set |
test_accg_immed 0x7f,accg3 |
test_acc_limmed 0xffff,0xffff,acc3 |
|
set_spr_immed 0,msr0 |
set_accg_immed 0x80,accg0 |
set_acc_immed 0x00000001,acc0 |
set_accg_immed 0,accg1 |
set_acc_immed 0x00000002,acc1 |
msubaccs acc0,acc3 |
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set |
test_spr_bits 2,1,1,msr0 ; msr0.ovf set |
test_spr_bits 1,0,1,msr0 ; msr0.aovf set |
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set |
test_accg_immed 0x80,accg3 |
test_acc_limmed 0x0000,0x0000,acc3 |
|
set_spr_immed 0,msr0 |
set_spr_immed 0,msr1 |
set_accg_immed 0,accg0 |
set_acc_immed 0x00000001,acc0 |
set_accg_immed 0,accg1 |
set_acc_immed 0x00000001,acc1 |
set_accg_immed 0,accg2 |
set_acc_immed 0x00000001,acc2 |
set_accg_immed 0x80,accg3 |
set_acc_immed 0x00000000,acc3 |
msubaccs.p acc0,acc1 |
msubaccs acc2,acc3 |
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear |
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set |
test_spr_bits 0x3c,2,0x8,msr1 ; msr0.sie is set |
test_spr_bits 2,1,1,msr1 ; msr1.ovf set |
test_spr_bits 1,0,1,msr0 ; msr0.aovf set |
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set |
test_accg_immed 0,accg1 |
test_acc_limmed 0x0000,0x0000,acc1 |
test_accg_immed 0x7f,accg3 |
test_acc_limmed 0xffff,0xffff,acc3 |
|
pass |