OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

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  • This comparison shows the changes necessary to convert path 
    /openrisc/tags/gdb/gdb-6.8/gdb-6.8.openrisc-2.1/sim/testsuite/sim/frv/fr550
    from Rev 24 to Rev 33
    ↔ Reverse comparison
  •

Rev 24 → Rev 33

/mqaddhss.cgs
0,0 → 1,76
# frv testcase for mqaddhss $FRi,$FRj,$FRj
# mach: all
 
.include "../testutils.inc"
 
start
 
.global mqaddhss
mqaddhss:
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
mqaddhss fr10,fr12,fr14
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0xdead,0xbeef,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
mqaddhss fr10,fr12,fr14
test_fr_limmed 0xbeef,0xdead,fr14
test_fr_limmed 0x2345,0x6789,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0xffff,0xffff,fr12
set_fr_iimmed 0x0002,0x0001,fr13
mqaddhss fr10,fr12,fr14
test_fr_limmed 0x1233,0x5677,fr14
test_fr_limmed 0x7fff,0x7fff,fr15
test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8001,0x8001,fr11
set_fr_iimmed 0xffff,0xfffe,fr12
set_fr_iimmed 0xfffe,0xfffe,fr13
mqaddhss fr10,fr12,fr14
test_fr_limmed 0x8000,0x8000,fr14
test_fr_limmed 0x8000,0x8000,fr15
test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0xffff,0xffff,fr11
set_fr_iimmed 0x7fff,0x0000,fr12
set_fr_iimmed 0x0000,0x8000,fr13
mqaddhss.p fr10,fr10,fr14
mqaddhss fr12,fr12,fr16
test_fr_limmed 0x0002,0x0002,fr14
test_fr_limmed 0xfffe,0xfffe,fr15
test_fr_limmed 0x7fff,0x0000,fr16
test_fr_limmed 0x0000,0x8000,fr17
test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
pass
/mqaddhus.cgs
0,0 → 1,62
# frv testcase for mqaddhus $FRi,$FRj,$FRj
# mach: all
 
.include "../testutils.inc"
 
start
 
.global mqaddhus
mqaddhus:
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
mqaddhus fr10,fr12,fr14
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0xdead,0xbeef,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
mqaddhus fr10,fr12,fr14
test_fr_limmed 0xbeef,0xdead,fr14
test_fr_limmed 0x2345,0x6789,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
set_fr_iimmed 0x0002,0x0001,fr12
set_fr_iimmed 0x0001,0x0002,fr13
mqaddhus fr10,fr12,fr14
test_fr_limmed 0x8000,0x7fff,fr14
test_fr_limmed 0xffff,0xffff,fr15
test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0002,0x0001,fr10
set_fr_iimmed 0x0001,0x0001,fr11
set_fr_iimmed 0xfffe,0xfffe,fr12
set_fr_iimmed 0x8000,0x8000,fr13
mqaddhus.p fr10,fr10,fr14
mqaddhus fr12,fr12,fr16
test_fr_limmed 0x0004,0x0002,fr14
test_fr_limmed 0x0002,0x0002,fr15
test_fr_limmed 0xffff,0xffff,fr16
test_fr_limmed 0xffff,0xffff,fr17
test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
pass
/udiv.cgs
0,0 → 1,48
# frv testcase for udiv $GRi,$GRj,$GRk
# mach: all
 
.include "../testutils.inc"
 
start
 
.global udiv
udiv:
; simple division 12 / 3
set_gr_immed 0x00000003,gr2
set_gr_immed 0x0000000c,gr3
udiv gr3,gr2,gr3
test_gr_immed 0x00000003,gr2
test_gr_immed 0x00000004,gr3
 
; example 1 from udiv in the fr30 manual
set_gr_limmed 0x0123,0x4567,gr2
set_gr_limmed 0xfedc,0xba98,gr3
udiv gr3,gr2,gr3
test_gr_limmed 0x0123,0x4567,gr2
test_gr_immed 0x000000e0,gr3
 
; set up exception handler
set_psr_et 1
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x170,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
set_spr_immed 128,lcr
set_gr_immed 0,gr15
 
; divide by zero
set_spr_addr ok1,lr
set_gr_addr e1,gr17
e1: udiv gr1,gr0,gr2 ; divide by zero
test_gr_immed 1,gr15
 
pass
 
ok1: ; exception handler for divide by zero
test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set
test_spr_gr epcr0,gr17 ; return address set
test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set
inc_gr_immed 1,gr15
rett 0
fail
/mmachs.cgs
0,0 → 1,259
# frv testcase for mmachs $GRi,$GRj,$ACCk
# mach: all
 
.include "../testutils.inc"
 
start
 
.global mmachs
mmachs:
; Positive operands
set_fr_iimmed 2,3,fr7 ; multiply small numbers
set_fr_iimmed 3,2,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
 
set_fr_iimmed 0,1,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
 
set_fr_iimmed 2,1,fr7 ; multiply by 1
set_fr_iimmed 1,2,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 8,acc0
test_accg_immed 0,accg1
test_acc_immed 8,acc1
 
set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0,0x8006,acc0
test_accg_immed 0,accg1
test_acc_limmed 0,0x8006,acc1
 
set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
set_fr_iimmed 2,0x4000,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0001,0x0006,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0001,0x0006,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x4000,0x0007,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x4000,0x0007,acc1
 
; Mixed operands
set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers
set_fr_iimmed 0xfffd,2,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x4000,0x0001,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x4000,0x0001,acc1
 
set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1
set_fr_iimmed 1,0xfffe,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0xffff,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0xffff,acc1
 
set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0
set_fr_iimmed 0,0xfffe,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0xffff,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0xffff,acc1
 
set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result
set_fr_iimmed 0xfffe,0x2001,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0xbffd,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0xbffd,acc1
 
set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result
set_fr_iimmed 0xfffe,0x4000,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0x3ffd,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0x3ffd,acc1
 
set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result
set_fr_iimmed 0x8000,0x7fff,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xbffd,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xbffd,acc1
 
; Negative operands
set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers
set_fr_iimmed 0xfffd,0xfffe,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xc003,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xc003,acc1
 
set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1
set_fr_iimmed 0xfffe,0xffff,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xc005,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xc005,acc1
 
set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result
set_fr_iimmed 0x8001,0x8001,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0x3ffec006,acc0
test_accg_immed 0,accg1
test_acc_immed 0x3ffec006,acc1
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0x7ffec006,acc0
test_accg_immed 0,accg1
test_acc_immed 0x7ffec006,acc1
 
set_accg_immed 0x7f,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0x7f,accg1
set_acc_immed 0xffffffff,acc1
set_fr_iimmed 1,1,fr7
set_fr_iimmed 1,1,fr8
mmachs fr7,fr8,acc0
test_accg_immed 0x7f,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xffff,0xffff,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x7f,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xffff,0xffff,acc1
 
set_accg_immed 0x80,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed 0x80,accg1
set_acc_immed 0,acc1
set_fr_iimmed 0xffff,0,fr7
set_fr_iimmed 1,0xffff,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x80,accg0
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x0000,0x8000,fr7 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr8
mmachs fr7,fr8,acc0
test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x80,accg0
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
 
pass
 
 
/cmcpxiu.cgs
0,0 → 1,492
# frv testcase for cmcpxiu $GRi,$GRj,$GRk,$CCi,$cond
# mach: all
 
.include "../testutils.inc"
 
start
 
.global cmcpxiu
cmcpxiu:
set_spr_immed 0x1b1b,cccr
 
set_fr_iimmed 4,2,fr7 ; multiply small numbers
set_fr_iimmed 3,5,fr8
cmcpxiu fr7,fr8,acc0,cc0,1
test_accg_immed 0,accg0
test_acc_immed 26,acc0
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 1,3,fr8
cmcpxiu fr7,fr8,acc0,cc0,1
test_accg_immed 0,accg0
test_acc_immed 5,acc0
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 0,2,fr8
cmcpxiu fr7,fr8,acc0,cc0,1
test_accg_immed 0,accg0
test_acc_immed 0,acc0
 
set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
set_fr_iimmed 0x0001,2,fr8
cmcpxiu fr7,fr8,acc0,cc0,1
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x7fff,acc0
 
set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
set_fr_iimmed 0x0001,2,fr8
cmcpxiu fr7,fr8,acc0,cc0,1
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8001,acc0
 
set_fr_iimmed 0x4000,1,fr7 ; 17 bit result
set_fr_iimmed 0x0001,4,fr8
cmcpxiu fr7,fr8,acc0,cc0,1
test_accg_immed 0,accg0
test_acc_immed 0x00010001,acc0
 
set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmcpxiu fr7,fr8,acc0,cc4,1
test_accg_immed 0,accg0
test_acc_immed 0x3fff0001,acc0
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x0000,0x8000,fr8
cmcpxiu fr7,fr8,acc0,cc4,1
test_accg_immed 0,accg0
test_acc_limmed 0x4000,0x0000,acc0
 
set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc4,1
test_accg_immed 0,accg0
test_acc_limmed 0xfffe,0x0001,acc0
 
set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc4,1
test_accg_immed 1,accg0
test_acc_immed 0xfffb0003,acc0
 
set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc4,1
test_accg_immed 1,accg0
test_acc_immed 0xfffc0002,acc0
 
set_fr_iimmed 4,2,fr7 ; multiply small numbers
set_fr_iimmed 3,5,fr8
cmcpxiu fr7,fr8,acc0,cc1,0
test_accg_immed 0,accg0
test_acc_immed 26,acc0
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 1,3,fr8
cmcpxiu fr7,fr8,acc0,cc1,0
test_accg_immed 0,accg0
test_acc_immed 5,acc0
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 0,2,fr8
cmcpxiu fr7,fr8,acc0,cc1,0
test_accg_immed 0,accg0
test_acc_immed 0,acc0
 
set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
set_fr_iimmed 0x0001,2,fr8
cmcpxiu fr7,fr8,acc0,cc1,0
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x7fff,acc0
 
set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
set_fr_iimmed 0x0001,2,fr8
cmcpxiu fr7,fr8,acc0,cc1,0
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8001,acc0
 
set_fr_iimmed 0x4000,1,fr7 ; 17 bit result
set_fr_iimmed 0x0001,4,fr8
cmcpxiu fr7,fr8,acc0,cc1,0
test_accg_immed 0,accg0
test_acc_immed 0x00010001,acc0
 
set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmcpxiu fr7,fr8,acc0,cc5,0
test_accg_immed 0,accg0
test_acc_immed 0x3fff0001,acc0
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x0000,0x8000,fr8
cmcpxiu fr7,fr8,acc0,cc5,0
test_accg_immed 0,accg0
test_acc_limmed 0x4000,0x0000,acc0
 
set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc5,0
test_accg_immed 0,accg0
test_acc_limmed 0xfffe,0x0001,acc0
 
set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc5,0
test_accg_immed 1,accg0
test_acc_immed 0xfffb0003,acc0
 
set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc5,0
test_accg_immed 1,accg0
test_acc_immed 0xfffc0002,acc0
 
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_fr_iimmed 4,2,fr7 ; multiply small numbers
set_fr_iimmed 3,5,fr8
cmcpxiu fr7,fr8,acc0,cc0,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 1,3,fr8
cmcpxiu fr7,fr8,acc0,cc0,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 0,2,fr8
cmcpxiu fr7,fr8,acc0,cc0,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
set_fr_iimmed 0x0001,2,fr8
cmcpxiu fr7,fr8,acc0,cc0,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
set_fr_iimmed 0x0001,4,fr8
cmcpxiu fr7,fr8,acc0,cc0,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
set_fr_iimmed 0x0001,4,fr8
cmcpxiu fr7,fr8,acc0,cc0,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmcpxiu fr7,fr8,acc0,cc4,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x0000,0x8000,fr8
cmcpxiu fr7,fr8,acc0,cc4,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc4,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
set_fr_iimmed 0x0001,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_fr_iimmed 4,2,fr7 ; multiply small numbers
set_fr_iimmed 3,5,fr8
cmcpxiu fr7,fr8,acc0,cc1,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 1,3,fr8
cmcpxiu fr7,fr8,acc0,cc1,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 0,2,fr8
cmcpxiu fr7,fr8,acc0,cc1,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
set_fr_iimmed 0x0001,2,fr8
cmcpxiu fr7,fr8,acc0,cc1,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
set_fr_iimmed 0x0001,4,fr8
cmcpxiu fr7,fr8,acc0,cc1,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
set_fr_iimmed 0x0001,4,fr8
cmcpxiu fr7,fr8,acc0,cc1,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmcpxiu fr7,fr8,acc0,cc5,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x0000,0x8000,fr8
cmcpxiu fr7,fr8,acc0,cc5,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc5,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
set_fr_iimmed 0x0001,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_fr_iimmed 4,2,fr7 ; multiply small numbers
set_fr_iimmed 3,5,fr8
cmcpxiu fr7,fr8,acc0,cc2,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 1,3,fr8
cmcpxiu fr7,fr8,acc0,cc2,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 0,2,fr8
cmcpxiu fr7,fr8,acc0,cc2,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
set_fr_iimmed 0x0001,2,fr8
cmcpxiu fr7,fr8,acc0,cc2,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
set_fr_iimmed 0x0001,4,fr8
cmcpxiu fr7,fr8,acc0,cc2,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
set_fr_iimmed 0x0001,4,fr8
cmcpxiu fr7,fr8,acc0,cc2,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmcpxiu fr7,fr8,acc0,cc6,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x0000,0x8000,fr8
cmcpxiu fr7,fr8,acc0,cc6,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc6,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
set_fr_iimmed 0x0001,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc6,0
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc6,1
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc6,0
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_fr_iimmed 4,2,fr7 ; multiply small numbers
set_fr_iimmed 3,5,fr8
cmcpxiu fr7,fr8,acc0,cc3,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 1,3,fr8
cmcpxiu fr7,fr8,acc0,cc3,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 0,2,fr8
cmcpxiu fr7,fr8,acc0,cc3,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
set_fr_iimmed 0x0001,2,fr8
cmcpxiu fr7,fr8,acc0,cc3,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
set_fr_iimmed 0x0001,4,fr8
cmcpxiu fr7,fr8,acc0,cc3,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
set_fr_iimmed 0x0001,4,fr8
cmcpxiu fr7,fr8,acc0,cc3,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmcpxiu fr7,fr8,acc0,cc7,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x0000,0x8000,fr8
cmcpxiu fr7,fr8,acc0,cc7,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc7,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
set_fr_iimmed 0x0001,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc7,0
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc7,1
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxiu fr7,fr8,acc0,cc7,0
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
pass
/cmqsubhss.cgs
0,0 → 1,429
# frv testcase for cmqsubhss $FRi,$FRj,$FRj,$CCi,$cond
# mach: all
 
.include "../testutils.inc"
 
start
 
.global msubhss
msubhss:
set_spr_immed 0x1b1b,cccr
 
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
cmqsubhss fr10,fr12,fr14,cc0,1
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0xdead,0x4111,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
cmqsubhss fr10,fr12,fr14,cc0,1
test_fr_limmed 0x4111,0xdead,fr14
test_fr_limmed 0x0123,0x4567,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0xffff,0xffff,fr12
set_fr_iimmed 0xfffe,0xffff,fr13
cmqsubhss fr10,fr12,fr14,cc0,1
test_fr_limmed 0x1235,0x5679,fr14
test_fr_limmed 0x7fff,0x7fff,fr15
test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8001,0x8001,fr11
set_fr_iimmed 0x0001,0x0002,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqsubhss fr10,fr12,fr14,cc4,1
test_fr_limmed 0x8000,0x8000,fr14
test_fr_limmed 0x8000,0x8000,fr15
test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0xffff,0xffff,fr11
set_fr_iimmed 0x8000,0x8000,fr12
set_fr_iimmed 0x8000,0x8000,fr13
cmqsubhss.p fr10,fr10,fr14,cc4,1
cmqsubhss fr12,fr10,fr16,cc4,1
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0x0000,0x0000,fr15
test_fr_limmed 0x8000,0x8000,fr16
test_fr_limmed 0x8001,0x8001,fr17
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
cmqsubhss fr10,fr12,fr14,cc1,0
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0xdead,0x4111,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
cmqsubhss fr10,fr12,fr14,cc1,0
test_fr_limmed 0x4111,0xdead,fr14
test_fr_limmed 0x0123,0x4567,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0xffff,0xffff,fr12
set_fr_iimmed 0xfffe,0xffff,fr13
cmqsubhss fr10,fr12,fr14,cc1,0
test_fr_limmed 0x1235,0x5679,fr14
test_fr_limmed 0x7fff,0x7fff,fr15
test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8001,0x8001,fr11
set_fr_iimmed 0x0001,0x0002,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqsubhss fr10,fr12,fr14,cc5,0
test_fr_limmed 0x8000,0x8000,fr14
test_fr_limmed 0x8000,0x8000,fr15
test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0xffff,0xffff,fr11
set_fr_iimmed 0x8000,0x8000,fr12
set_fr_iimmed 0x8000,0x8000,fr13
cmqsubhss.p fr10,fr10,fr14,cc5,0
cmqsubhss fr12,fr10,fr16,cc5,0
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0x0000,0x0000,fr15
test_fr_limmed 0x8000,0x8000,fr16
test_fr_limmed 0x8001,0x8001,fr17
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf not set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_fr_iimmed 0x1111,0x1111,fr14
set_fr_iimmed 0x2222,0x2222,fr15
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
cmqsubhss fr10,fr12,fr14,cc0,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
cmqsubhss fr10,fr12,fr14,cc0,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0xffff,0xffff,fr12
set_fr_iimmed 0xfffe,0xffff,fr13
cmqsubhss fr10,fr12,fr14,cc0,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8001,0x8001,fr11
set_fr_iimmed 0x0001,0x0002,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqsubhss fr10,fr12,fr14,cc4,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x3333,0x3333,fr16
set_fr_iimmed 0x4444,0x4444,fr17
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0xffff,0xffff,fr11
set_fr_iimmed 0x8000,0x8000,fr12
set_fr_iimmed 0x8000,0x8000,fr13
cmqsubhss.p fr10,fr10,fr14,cc4,0
cmqsubhss fr12,fr10,fr16,cc4,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_fr_limmed 0x3333,0x3333,fr16
test_fr_limmed 0x4444,0x4444,fr17
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1111,0x1111,fr14
set_fr_iimmed 0x2222,0x2222,fr15
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
cmqsubhss fr10,fr12,fr14,cc1,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
cmqsubhss fr10,fr12,fr14,cc1,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0xffff,0xffff,fr12
set_fr_iimmed 0xfffe,0xffff,fr13
cmqsubhss fr10,fr12,fr14,cc1,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8001,0x8001,fr11
set_fr_iimmed 0x0001,0x0002,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqsubhss fr10,fr12,fr14,cc5,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x3333,0x3333,fr16
set_fr_iimmed 0x4444,0x4444,fr17
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0xffff,0xffff,fr11
set_fr_iimmed 0x8000,0x8000,fr12
set_fr_iimmed 0x8000,0x8000,fr13
cmqsubhss.p fr10,fr10,fr14,cc5,1
cmqsubhss fr12,fr10,fr16,cc5,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_fr_limmed 0x3333,0x3333,fr16
test_fr_limmed 0x4444,0x4444,fr17
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1111,0x1111,fr14
set_fr_iimmed 0x2222,0x2222,fr15
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
cmqsubhss fr10,fr12,fr14,cc2,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
cmqsubhss fr10,fr12,fr14,cc2,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0xffff,0xffff,fr12
set_fr_iimmed 0xfffe,0xffff,fr13
cmqsubhss fr10,fr12,fr14,cc2,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8001,0x8001,fr11
set_fr_iimmed 0x0001,0x0002,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqsubhss fr10,fr12,fr14,cc6,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x3333,0x3333,fr16
set_fr_iimmed 0x4444,0x4444,fr17
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0xffff,0xffff,fr11
set_fr_iimmed 0x8000,0x8000,fr12
set_fr_iimmed 0x8000,0x8000,fr13
cmqsubhss.p fr10,fr10,fr14,cc6,1
cmqsubhss fr12,fr10,fr16,cc6,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_fr_limmed 0x3333,0x3333,fr16
test_fr_limmed 0x4444,0x4444,fr17
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is set
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1111,0x1111,fr14
set_fr_iimmed 0x2222,0x2222,fr15
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
cmqsubhss fr10,fr12,fr14,cc3,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
cmqsubhss fr10,fr12,fr14,cc3,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0xffff,0xffff,fr12
set_fr_iimmed 0xfffe,0xffff,fr13
cmqsubhss fr10,fr12,fr14,cc3,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8001,0x8001,fr11
set_fr_iimmed 0x0001,0x0002,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqsubhss fr10,fr12,fr14,cc7,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x3333,0x3333,fr16
set_fr_iimmed 0x4444,0x4444,fr17
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0xffff,0xffff,fr11
set_fr_iimmed 0x8000,0x8000,fr12
set_fr_iimmed 0x8000,0x8000,fr13
cmqsubhss.p fr10,fr10,fr14,cc7,1
cmqsubhss fr12,fr10,fr16,cc7,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_fr_limmed 0x3333,0x3333,fr16
test_fr_limmed 0x4444,0x4444,fr17
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is set
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
pass
/mqxmacxhs.cgs
0,0 → 1,211
# frv testcase for mqxmacxhs $GRi,$GRj,$ACCk
# mach: all
 
.include "../testutils.inc"
 
start
 
.global mqxmacxhs
mqxmacxhs:
; Positive operands
set_fr_iimmed 2,3,fr8 ; multiply small numbers
set_fr_iimmed 2,3,fr10
set_fr_iimmed 0,1,fr9 ; multiply by 0
set_fr_iimmed 0,2,fr11
mqxmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
test_accg_immed 0,accg2
test_acc_immed 6,acc2
test_accg_immed 0,accg3
test_acc_immed 6,acc3
 
set_fr_iimmed 2,1,fr8 ; multiply by 1
set_fr_iimmed 2,1,fr10
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
set_fr_iimmed 0x3fff,2,fr11
mqxmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg2
test_acc_immed 8,acc2
test_accg_immed 0,accg3
test_acc_immed 8,acc3
test_accg_immed 0,accg0
test_acc_limmed 0,0x7ffe,acc0
test_accg_immed 0,accg1
test_acc_limmed 0,0x7ffe,acc1
 
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
set_fr_iimmed 0x4000,2,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr11
mqxmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg2
test_acc_limmed 0x0000,0x8008,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x0000,0x8008,acc3
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0x7fff,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0x7fff,acc1
 
; Mixed operands
set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 2,0xfffd,fr10
set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
set_fr_iimmed 0xfffe,1,fr11
mqxmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg2
test_acc_limmed 0x0000,0x8002,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x0000,0x8002,acc3
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0x7ffd,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0x7ffd,acc1
 
set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
set_fr_iimmed 0xfffe,0,fr10
set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
set_fr_iimmed 0x2001,0xfffe,fr11
mqxmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg2
test_acc_limmed 0x0000,0x8002,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x0000,0x8002,acc3
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0x3ffb,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0x3ffb,acc1
 
set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
set_fr_iimmed 0x4000,0xfffe,fr10
set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
set_fr_iimmed 0x7fff,0x8000,fr11
mqxmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg2
test_acc_limmed 0x0000,0x0002,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x0000,0x0002,acc3
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xbffb,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xbffb,acc1
 
; Negative operands
set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 0xfffe,0xfffd,fr10
set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
set_fr_iimmed 0xffff,0xfffe,fr11
mqxmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg2
test_acc_limmed 0x0000,0x0008,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x0000,0x0008,acc3
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xbffd,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xbffd,acc1
 
set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr11
mqxmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg2
test_acc_immed 0x3fff0009,acc2
test_accg_immed 0,accg3
test_acc_immed 0x3fff0009,acc3
test_accg_immed 0,accg0
test_acc_immed 0x3fffbffd,acc0
test_accg_immed 0,accg1
test_acc_immed 0x3fffbffd,acc1
 
set_accg_immed 0x7f,accg2 ; saturation
set_acc_immed 0xffffffff,acc2
set_accg_immed 0x7f,accg3
set_acc_immed 0xffffffff,acc3
set_accg_immed 0x7f,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0x7f,accg1
set_acc_immed 0xffffffff,acc1
set_fr_iimmed 1,1,fr8
set_fr_iimmed 1,1,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
mqxmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x7f,accg2
test_acc_limmed 0xffff,0xffff,acc2
test_accg_immed 0x7f,accg3
test_acc_limmed 0xffff,0xffff,acc3
test_accg_immed 0x7f,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xffff,0xffff,acc1
 
set_accg_immed 0x80,accg2 ; saturation
set_acc_immed 0,acc2
set_accg_immed 0x80,accg3
set_acc_immed 0,acc3
set_accg_immed 0x80,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed 0x80,accg1
set_acc_immed 0,acc1
set_fr_iimmed 0xffff,0,fr8
set_fr_iimmed 0xffff,1,fr10
set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
mqxmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x80,accg2
test_acc_immed 0,acc2
test_accg_immed 0x80,accg3
test_acc_immed 0,acc3
test_accg_immed 0x80,accg0
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
 
pass
 
 
/mmachu.cgs
0,0 → 1,146
# frv testcase for mmachu $GRi,$GRj,$GRk
# mach: all
 
.include "../testutils.inc"
 
start
 
.global mmachu
mmachu:
set_fr_iimmed 3,2,fr7 ; multiply small numbers
set_fr_iimmed 2,3,fr8
mmachu fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 2,1,fr8
mmachu fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 8,acc0
test_accg_immed 0,accg1
test_acc_immed 8,acc1
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
mmachu fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 8,acc0
test_accg_immed 0,accg1
test_acc_immed 8,acc1
 
set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr8
mmachu fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8006,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x8006,acc1
 
set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
set_fr_iimmed 2,0x4000,fr8
mmachu fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0001,0x0006,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0001,0x0006,acc1
 
set_fr_iimmed 0x8000,2,fr7 ; 17 bit result
set_fr_iimmed 2,0x8000,fr8
mmachu fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0x00020006,acc0
test_accg_immed 0,accg1
test_acc_immed 0x00020006,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
mmachu fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0x40010007,acc0
test_accg_immed 0,accg1
test_acc_immed 0x40010007,acc1
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr8
mmachu fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x8001,0x0007,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x8001,0x0007,acc1
 
set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
mmachu fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 1,accg0
test_acc_limmed 0x7fff,0x0008,acc0
test_accg_immed 1,accg1
test_acc_limmed 0x7fff,0x0008,acc1
 
set_accg_immed 0xff,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xffffffff,acc1
set_fr_iimmed 1,1,fr7
set_fr_iimmed 1,1,fr8
mmachu fr7,fr8,acc0
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xffff,acc1
 
set_fr_iimmed 0xffff,0x0000,fr7
set_fr_iimmed 0xffff,0xffff,fr8
mmachu fr7,fr8,acc0
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xffff,acc1
 
pass
/masaccs.cgs
0,0 → 1,148
# frv testcase for masaccs $ACC40Si,$ACC40Sk
# mach: all
 
.include "../testutils.inc"
 
start
 
.global masaccs
masaccs:
set_accg_immed 0,accg0
set_acc_immed 0x00000000,acc0
set_accg_immed 0,accg1
set_acc_immed 0x00000000,acc1
masaccs acc0,acc2
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set
test_accg_immed 0,accg2
test_acc_limmed 0x0000,0x0000,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x0000,0x0000,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0xdead0000,acc0
set_accg_immed 0,accg1
set_acc_immed 0x0000beef,acc1
masaccs acc0,acc2
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set
test_accg_immed 0,accg2
test_acc_limmed 0xdead,0xbeef,acc2
test_accg_immed 0,accg3
test_acc_limmed 0xdeac,0x4111,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0x0000dead,acc0
set_accg_immed 0,accg1
set_acc_immed 0xbeef0000,acc1
masaccs acc0,acc2
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set
test_accg_immed 0,accg2
test_acc_limmed 0xbeef,0xdead,acc2
test_accg_immed 0xff,accg3
test_acc_limmed 0x4111,0xdead,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0x12345678,acc0
set_accg_immed 0,accg1
set_acc_immed 0x11111111,acc1
masaccs acc0,acc2
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set
test_accg_immed 0,accg2
test_acc_limmed 0x2345,0x6789,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x0123,0x4567,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0x12345678,acc0
set_accg_immed 0,accg1
set_acc_immed 0xffffffff,acc1
masaccs acc0,acc2
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set
test_accg_immed 1,accg2
test_acc_limmed 0x1234,0x5677,acc2
test_accg_immed 0xff,accg3
test_acc_limmed 0x1234,0x5679,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0x12345678,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xffffffff,acc1
masaccs acc0,acc2
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set
test_accg_immed 0,accg2
test_acc_limmed 0x1234,0x5677,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x1234,0x5679,acc3
 
set_spr_immed 0,msr0
set_accg_immed 0x7f,accg0
set_acc_immed 0xfffe7ffe,acc0
set_accg_immed 0x0,accg1
set_acc_immed 0x00020001,acc1
masaccs acc0,acc2
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
test_accg_immed 0x7f,accg2
test_acc_limmed 0xffff,0xffff,acc2
test_accg_immed 0x7f,accg3
test_acc_limmed 0xfffc,0x7ffd,acc3
 
set_spr_immed 0,msr0
set_accg_immed 0x80,accg0
set_acc_immed 0x00000001,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xfffffffe,acc1
masaccs acc0,acc2
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
test_accg_immed 0x80,accg2
test_acc_limmed 0x0000,0x0000,acc2
test_accg_immed 0x80,accg3
test_acc_limmed 0x0000,0x0003,acc3
 
set_spr_immed 0,msr0
set_accg_immed 0,accg0
set_acc_immed 0x00000001,acc0
set_accg_immed 0,accg1
set_acc_immed 0x00000001,acc1
set_accg_immed 0,accg4
set_acc_immed 0x00000001,acc4
set_accg_immed 0x7f,accg5
set_acc_immed 0xffffffff,acc5
masaccs.p acc0,acc0
masaccs acc4,acc4
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x0002,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x0000,acc1
test_accg_immed 0x7f,accg4
test_acc_limmed 0xffff,0xffff,acc4
test_accg_immed 0x80,accg5
test_acc_limmed 0x0000,0x0002,acc5
 
pass
/cmqsubhus.cgs
0,0 → 1,351
# frv testcase for cmqsubhus $FRi,$FRj,$FRj,$CCi,$cond
# mach: all
 
.include "../testutils.inc"
 
start
 
.global cmqsubhus
cmqsubhus:
set_spr_immed 0x1b1b,cccr
 
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0xbeef,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0x0000,fr13
cmqsubhus fr10,fr12,fr14,cc0,1
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0xdead,0xbeef,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0x1111,0x1111,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqsubhus fr10,fr12,fr14,cc0,1
test_fr_limmed 0x0123,0x4567,fr14
test_fr_limmed 0x7ffc,0x7ffd,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0001,0x0001,fr11
set_fr_iimmed 0x0001,0x0002,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqsubhus fr10,fr12,fr14,cc4,1
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0x0000,0x0000,fr15
test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0002,fr11
set_fr_iimmed 0x0000,0x0001,fr12
set_fr_iimmed 0x0002,0x0003,fr13
cmqsubhus.p fr10,fr10,fr14,cc4,1
cmqsubhus fr10,fr12,fr16,cc4,1
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0x0000,0x0000,fr15
test_fr_limmed 0x0001,0x0000,fr16
test_fr_limmed 0x0000,0x0000,fr17
test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0xbeef,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0x0000,fr13
cmqsubhus fr10,fr12,fr14,cc1,0
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0xdead,0xbeef,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0x1111,0x1111,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqsubhus fr10,fr12,fr14,cc1,0
test_fr_limmed 0x0123,0x4567,fr14
test_fr_limmed 0x7ffc,0x7ffd,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0001,0x0001,fr11
set_fr_iimmed 0x0001,0x0002,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqsubhus fr10,fr12,fr14,cc5,0
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0x0000,0x0000,fr15
test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0002,fr11
set_fr_iimmed 0x0000,0x0001,fr12
set_fr_iimmed 0x0002,0x0003,fr13
cmqsubhus.p fr10,fr10,fr14,cc5,0
cmqsubhus fr10,fr12,fr16,cc5,0
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0x0000,0x0000,fr15
test_fr_limmed 0x0001,0x0000,fr16
test_fr_limmed 0x0000,0x0000,fr17
test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_fr_iimmed 0x1111,0x1111,fr14
set_fr_iimmed 0x2222,0x2222,fr15
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0xbeef,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0x0000,fr13
cmqsubhus fr10,fr12,fr14,cc0,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0x1111,0x1111,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqsubhus fr10,fr12,fr14,cc0,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0001,0x0001,fr11
set_fr_iimmed 0x0001,0x0002,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqsubhus fr10,fr12,fr14,cc4,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x3333,0x3333,fr16
set_fr_iimmed 0x4444,0x4444,fr17
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0002,fr11
set_fr_iimmed 0x0000,0x0001,fr12
set_fr_iimmed 0x0002,0x0003,fr13
cmqsubhus.p fr10,fr10,fr14,cc4,0
cmqsubhus fr10,fr12,fr16,cc4,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_fr_limmed 0x3333,0x3333,fr16
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_fr_limmed 0x4444,0x4444,fr17
 
set_fr_iimmed 0x1111,0x1111,fr14
set_fr_iimmed 0x2222,0x2222,fr15
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0xbeef,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0x0000,fr13
cmqsubhus fr10,fr12,fr14,cc1,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0x1111,0x1111,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqsubhus fr10,fr12,fr14,cc1,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0001,0x0001,fr11
set_fr_iimmed 0x0001,0x0002,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqsubhus fr10,fr12,fr14,cc5,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x3333,0x3333,fr16
set_fr_iimmed 0x4444,0x4444,fr17
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0002,fr11
set_fr_iimmed 0x0000,0x0001,fr12
set_fr_iimmed 0x0002,0x0003,fr13
cmqsubhus.p fr10,fr10,fr14,cc5,1
cmqsubhus fr10,fr12,fr16,cc5,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_fr_limmed 0x3333,0x3333,fr16
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_fr_limmed 0x4444,0x4444,fr17
 
set_fr_iimmed 0x1111,0x1111,fr14
set_fr_iimmed 0x2222,0x2222,fr15
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0xbeef,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0x0000,fr13
cmqsubhus fr10,fr12,fr14,cc2,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0x1111,0x1111,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqsubhus fr10,fr12,fr14,cc2,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0001,0x0001,fr11
set_fr_iimmed 0x0001,0x0002,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqsubhus fr10,fr12,fr14,cc6,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x3333,0x3333,fr16
set_fr_iimmed 0x4444,0x4444,fr17
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0002,fr11
set_fr_iimmed 0x0000,0x0001,fr12
set_fr_iimmed 0x0002,0x0003,fr13
cmqsubhus.p fr10,fr10,fr14,cc6,0
cmqsubhus fr10,fr12,fr16,cc6,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_fr_limmed 0x3333,0x3333,fr16
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_fr_limmed 0x4444,0x4444,fr17
;
set_fr_iimmed 0x1111,0x1111,fr14
set_fr_iimmed 0x2222,0x2222,fr15
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0xbeef,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0x0000,fr13
cmqsubhus fr10,fr12,fr14,cc3,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0x1111,0x1111,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqsubhus fr10,fr12,fr14,cc3,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0001,0x0001,fr11
set_fr_iimmed 0x0001,0x0002,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqsubhus fr10,fr12,fr14,cc7,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x3333,0x3333,fr16
set_fr_iimmed 0x4444,0x4444,fr17
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0002,fr11
set_fr_iimmed 0x0000,0x0001,fr12
set_fr_iimmed 0x0002,0x0003,fr13
cmqsubhus.p fr10,fr10,fr14,cc7,0
cmqsubhus fr10,fr12,fr16,cc7,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_fr_limmed 0x3333,0x3333,fr16
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_fr_limmed 0x4444,0x4444,fr17
 
pass
/mdasaccs.cgs
0,0 → 1,122
# frv testcase for mdasaccs $ACC40Si,$ACC40Sk
# mach: all
 
.include "../testutils.inc"
 
start
 
.global mdasaccs
mdasaccs:
set_accg_immed 0,accg0
set_acc_immed 0x00000000,acc0
set_accg_immed 0,accg1
set_acc_immed 0x00000000,acc1
set_accg_immed 0,accg2
set_acc_immed 0xdead0000,acc2
set_accg_immed 0,accg3
set_acc_immed 0x0000beef,acc3
mdasaccs acc0,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x0000,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x0000,acc1
test_accg_immed 0,accg2
test_acc_limmed 0xdead,0xbeef,acc2
test_accg_immed 0,accg3
test_acc_limmed 0xdeac,0x4111,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0x0000dead,acc0
set_accg_immed 0,accg1
set_acc_immed 0xbeef0000,acc1
set_accg_immed 0,accg2
set_acc_immed 0x12345678,acc2
set_accg_immed 0,accg3
set_acc_immed 0x11111111,acc3
mdasaccs acc0,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0xbeef,0xdead,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0x4111,0xdead,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x2345,0x6789,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x0123,0x4567,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0x12345678,acc0
set_accg_immed 0,accg1
set_acc_immed 0xffffffff,acc1
set_accg_immed 0,accg2
set_acc_immed 0x12345678,acc2
set_accg_immed 0xff,accg3
set_acc_immed 0xffffffff,acc3
mdasaccs acc0,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 1,accg0
test_acc_limmed 0x1234,0x5677,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0x1234,0x5679,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x1234,0x5677,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x1234,0x5679,acc3
 
set_spr_immed 0,msr0
set_accg_immed 0x7f,accg0
set_acc_immed 0xfffe7ffe,acc0
set_accg_immed 0x0,accg1
set_acc_immed 0x00020001,acc1
set_accg_immed 0x80,accg2
set_acc_immed 0x00000001,acc2
set_accg_immed 0xff,accg3
set_acc_immed 0xfffffffe,acc3
mdasaccs acc0,acc0
test_spr_bits 0x3c,2,0xa,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
test_accg_immed 0x7f,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xfffc,0x7ffd,acc1
test_accg_immed 0x80,accg2
test_acc_limmed 0x0000,0x0000,acc2
test_accg_immed 0x80,accg3
test_acc_limmed 0x0000,0x0003,acc3
 
set_spr_immed 0,msr0
set_accg_immed 0,accg0
set_acc_immed 0x00000001,acc0
set_accg_immed 0,accg1
set_acc_immed 0x00000001,acc1
set_accg_immed 0,accg2
set_acc_immed 0x00000001,acc2
set_accg_immed 0x7f,accg3
set_acc_immed 0xffffffff,acc3
mdasaccs acc0,acc0
test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x0002,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x0000,acc1
test_accg_immed 0x7f,accg2
test_acc_limmed 0xffff,0xffff,acc2
test_accg_immed 0x80,accg3
test_acc_limmed 0x0000,0x0002,acc3
 
pass
/mqmacxhs.cgs
0,0 → 1,211
# frv testcase for mqmacxhs $GRi,$GRj,$ACCk
# mach: all
 
.include "../testutils.inc"
 
start
 
.global mqmacxhs
mqmacxhs:
; Positive operands
set_fr_iimmed 2,3,fr8 ; multiply small numbers
set_fr_iimmed 2,3,fr10
set_fr_iimmed 0,1,fr9 ; multiply by 0
set_fr_iimmed 0,2,fr11
mqmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
test_accg_immed 0,accg2
test_acc_immed 0,acc2
test_accg_immed 0,accg3
test_acc_immed 0,acc3
 
set_fr_iimmed 2,1,fr8 ; multiply by 1
set_fr_iimmed 2,1,fr10
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
set_fr_iimmed 0x3fff,2,fr11
mqmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 8,acc0
test_accg_immed 0,accg1
test_acc_immed 8,acc1
test_accg_immed 0,accg2
test_acc_limmed 0,0x7ffe,acc2
test_accg_immed 0,accg3
test_acc_limmed 0,0x7ffe,acc3
 
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
set_fr_iimmed 0x4000,2,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr11
mqmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8008,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x8008,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x3fff,0x7fff,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x3fff,0x7fff,acc3
 
; Mixed operands
set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 2,0xfffd,fr10
set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
set_fr_iimmed 0xfffe,1,fr11
mqmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8002,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x8002,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x3fff,0x7ffd,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x3fff,0x7ffd,acc3
 
set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
set_fr_iimmed 0xfffe,0,fr10
set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
set_fr_iimmed 0x2001,0xfffe,fr11
mqmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8002,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x8002,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x3fff,0x3ffb,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x3fff,0x3ffb,acc3
 
set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
set_fr_iimmed 0x4000,0xfffe,fr10
set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
set_fr_iimmed 0x7fff,0x8000,fr11
mqmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x0002,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x0002,acc1
test_accg_immed 0xff,accg2
test_acc_limmed 0xffff,0xbffb,acc2
test_accg_immed 0xff,accg3
test_acc_limmed 0xffff,0xbffb,acc3
 
; Negative operands
set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 0xfffe,0xfffd,fr10
set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
set_fr_iimmed 0xffff,0xfffe,fr11
mqmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x0008,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x0008,acc1
test_accg_immed 0xff,accg2
test_acc_limmed 0xffff,0xbffd,acc2
test_accg_immed 0xff,accg3
test_acc_limmed 0xffff,0xbffd,acc3
 
set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr11
mqmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0x3fff0009,acc0
test_accg_immed 0,accg1
test_acc_immed 0x3fff0009,acc1
test_accg_immed 0,accg2
test_acc_immed 0x3fffbffd,acc2
test_accg_immed 0,accg3
test_acc_immed 0x3fffbffd,acc3
 
set_accg_immed 0x7f,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0x7f,accg1
set_acc_immed 0xffffffff,acc1
set_accg_immed 0x7f,accg2 ; saturation
set_acc_immed 0xffffffff,acc2
set_accg_immed 0x7f,accg3
set_acc_immed 0xffffffff,acc3
set_fr_iimmed 1,1,fr8
set_fr_iimmed 1,1,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
mqmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x7f,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xffff,0xffff,acc1
test_accg_immed 0x7f,accg2
test_acc_limmed 0xffff,0xffff,acc2
test_accg_immed 0x7f,accg3
test_acc_limmed 0xffff,0xffff,acc3
 
set_accg_immed 0x80,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed 0x80,accg1
set_acc_immed 0,acc1
set_accg_immed 0x80,accg2 ; saturation
set_acc_immed 0,acc2
set_accg_immed 0x80,accg3
set_acc_immed 0,acc3
set_fr_iimmed 0xffff,0,fr8
set_fr_iimmed 0xffff,1,fr10
set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
mqmacxhs fr8,fr10,acc0
test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x80,accg0
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
test_accg_immed 0x80,accg2
test_acc_immed 0,acc2
test_accg_immed 0x80,accg3
test_acc_immed 0,acc3
 
pass
 
 
/mtrap.cgs
0,0 → 1,50
# frv testcase for mp_exception
# mach: all
 
.include "../testutils.inc"
 
start
 
.global mp_exception
mpx:
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr7
inc_gr_immed 0x0e0,gr7 ; address of exception handler
set_bctrlr_0_0 gr7
set_spr_immed 128,lcr
set_spr_addr ok1,lr
set_psr_et 1
set_gr_immed 0,gr5
 
set_spr_immed 0,msr0
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0xffff,0xffff,fr12
set_fr_iimmed 0x0002,0x0001,fr13
mqaddhss fr10,fr12,fr14
test_fr_limmed 0x1233,0x5677,fr14
test_fr_limmed 0x7fff,0x7fff,fr15
test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
mtrap ; generate interrupt
test_gr_immed 1,gr5
 
and_spr_immed 0xffffc000,msr0 ; Clear msr0 fields
mcmpsh fr10,fr11,fcc0 ; no exception
test_spr_bits 0x7000,12,1,msr0; msr0.mtt is always set
mtrap ; nop
test_gr_immed 1,gr5
 
pass
 
; exception handler
ok1:
test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
inc_gr_immed 1,gr5
rett 0
fail
/msubhss.cgs
0,0 → 1,97
# frv testcase for msubhss $FRi,$FRj,$FRj
# mach: all
 
.include "../testutils.inc"
 
start
 
.global msubhss
msubhss:
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
msubhss fr10,fr11,fr12
test_fr_limmed 0x0000,0x0000,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0x0000,fr10
set_fr_iimmed 0x0000,0xbeef,fr11
msubhss fr10,fr11,fr12
test_fr_limmed 0xdead,0x4111,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
msubhss fr10,fr11,fr12
test_fr_limmed 0x4111,0xdead,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
msubhss fr10,fr11,fr12
test_fr_limmed 0x0123,0x4567,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0xffff,0xffff,fr11
msubhss fr10,fr11,fr12
test_fr_limmed 0x1235,0x5679,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0xfffe,0xffff,fr11
msubhss fr10,fr11,fr12
test_fr_limmed 0x7fff,0x7fff,fr12
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x0001,0x0002,fr11
msubhss fr10,fr11,fr12
test_fr_limmed 0x8000,0x8000,fr12
test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x0002,0x0001,fr11
msubhss fr10,fr11,fr12
test_fr_limmed 0x8000,0x8000,fr12
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x8000,0x8000,fr11
msubhss.p fr10,fr10,fr12
msubhss fr11,fr10,fr13
test_fr_limmed 0x0000,0x0000,fr12
test_fr_limmed 0x8000,0x8000,fr13
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
pass
/msubhus.cgs
0,0 → 1,77
# frv testcase for msubhus $FRi,$FRj,$FRj
# mach: all
 
.include "../testutils.inc"
 
start
 
.global msubhus
msubhus:
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
msubhus fr10,fr11,fr12
test_fr_limmed 0x0000,0x0000,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0xbeef,fr10
set_fr_iimmed 0x0000,0x0000,fr11
msubhus fr10,fr11,fr12
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
msubhus fr10,fr11,fr12
test_fr_limmed 0x0123,0x4567,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
msubhus fr10,fr11,fr12
test_fr_limmed 0x7ffc,0x7ffd,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0001,0x0002,fr11
msubhus fr10,fr11,fr12
test_fr_limmed 0x0000,0x0000,fr12
test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0001,fr11
msubhus fr10,fr11,fr12
test_fr_limmed 0x0000,0x0000,fr12
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0002,fr11
msubhus.p fr10,fr10,fr12
msubhus fr10,fr11,fr13
test_fr_limmed 0x0000,0x0000,fr12
test_fr_limmed 0x0000,0x0000,fr13
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
pass
/cmsubhss.cgs
0,0 → 1,547
# frv testcase for cmsubhss $FRi,$FRj,$FRj,$CCi,$cond
# mach: all
 
.include "../testutils.inc"
 
start
 
.global cmsubhss
cmsubhss:
set_spr_immed 0x1b1b,cccr
 
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmsubhss fr10,fr11,fr12,cc0,1
test_fr_limmed 0x0000,0x0000,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0x0000,fr10
set_fr_iimmed 0x0000,0xbeef,fr11
cmsubhss fr10,fr11,fr12,cc0,1
test_fr_limmed 0xdead,0x4111,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
cmsubhss fr10,fr11,fr12,cc0,1
test_fr_limmed 0x4111,0xdead,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmsubhss fr10,fr11,fr12,cc0,1
test_fr_limmed 0x0123,0x4567,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0xffff,0xffff,fr11
cmsubhss fr10,fr11,fr12,cc0,1
test_fr_limmed 0x1235,0x5679,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0xfffe,0xffff,fr11
cmsubhss fr10,fr11,fr12,cc4,1
test_fr_limmed 0x7fff,0x7fff,fr12
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x0001,0x0002,fr11
cmsubhss fr10,fr11,fr12,cc4,1
test_fr_limmed 0x8000,0x8000,fr12
test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmsubhss fr10,fr11,fr12,cc4,1
test_fr_limmed 0x8000,0x8000,fr12
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x8000,0x8000,fr11
cmsubhss.p fr10,fr10,fr12,cc4,1
cmsubhss fr11,fr10,fr13,cc4,1
test_fr_limmed 0x0000,0x0000,fr12
test_fr_limmed 0x8000,0x8000,fr13
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmsubhss fr10,fr11,fr12,cc1,0
test_fr_limmed 0x0000,0x0000,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0x0000,fr10
set_fr_iimmed 0x0000,0xbeef,fr11
cmsubhss fr10,fr11,fr12,cc1,0
test_fr_limmed 0xdead,0x4111,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
cmsubhss fr10,fr11,fr12,cc1,0
test_fr_limmed 0x4111,0xdead,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmsubhss fr10,fr11,fr12,cc1,0
test_fr_limmed 0x0123,0x4567,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0xffff,0xffff,fr11
cmsubhss fr10,fr11,fr12,cc1,0
test_fr_limmed 0x1235,0x5679,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0xfffe,0xffff,fr11
cmsubhss fr10,fr11,fr12,cc5,0
test_fr_limmed 0x7fff,0x7fff,fr12
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x0001,0x0002,fr11
cmsubhss fr10,fr11,fr12,cc5,0
test_fr_limmed 0x8000,0x8000,fr12
test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmsubhss fr10,fr11,fr12,cc5,0
test_fr_limmed 0x8000,0x8000,fr12
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x8000,0x8000,fr11
cmsubhss.p fr10,fr10,fr12,cc5,0
cmsubhss fr11,fr10,fr13,cc5,0
test_fr_limmed 0x0000,0x0000,fr12
test_fr_limmed 0x8000,0x8000,fr13
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_fr_iimmed 0xdead,0xbeef,fr12
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmsubhss fr10,fr11,fr12,cc0,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0x0000,fr10
set_fr_iimmed 0x0000,0xbeef,fr11
cmsubhss fr10,fr11,fr12,cc0,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
cmsubhss fr10,fr11,fr12,cc0,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmsubhss fr10,fr11,fr12,cc0,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0xffff,0xffff,fr11
cmsubhss fr10,fr11,fr12,cc0,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0xfffe,0xffff,fr11
cmsubhss fr10,fr11,fr12,cc4,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x0001,0x0002,fr11
cmsubhss fr10,fr11,fr12,cc4,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmsubhss fr10,fr11,fr12,cc4,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr13
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x8000,0x8000,fr11
cmsubhss.p fr10,fr10,fr12,cc4,0
cmsubhss fr11,fr10,fr13,cc4,0
test_fr_limmed 0xdead,0xbeef,fr12
test_fr_limmed 0xbeef,0xdead,fr13
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0xbeef,fr12
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmsubhss fr10,fr11,fr12,cc1,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0x0000,fr10
set_fr_iimmed 0x0000,0xbeef,fr11
cmsubhss fr10,fr11,fr12,cc1,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
cmsubhss fr10,fr11,fr12,cc1,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmsubhss fr10,fr11,fr12,cc1,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0xffff,0xffff,fr11
cmsubhss fr10,fr11,fr12,cc1,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0xfffe,0xffff,fr11
cmsubhss fr10,fr11,fr12,cc5,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x0001,0x0002,fr11
cmsubhss fr10,fr11,fr12,cc5,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmsubhss fr10,fr11,fr12,cc5,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr13
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x8000,0x8000,fr11
cmsubhss.p fr10,fr10,fr12,cc5,1
cmsubhss fr11,fr10,fr13,cc5,1
test_fr_limmed 0xdead,0xbeef,fr12
test_fr_limmed 0xbeef,0xdead,fr13
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0xbeef,fr12
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmsubhss fr10,fr11,fr12,cc2,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0x0000,fr10
set_fr_iimmed 0x0000,0xbeef,fr11
cmsubhss fr10,fr11,fr12,cc2,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
cmsubhss fr10,fr11,fr12,cc2,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmsubhss fr10,fr11,fr12,cc2,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0xffff,0xffff,fr11
cmsubhss fr10,fr11,fr12,cc2,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0xfffe,0xffff,fr11
cmsubhss fr10,fr11,fr12,cc6,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x0001,0x0002,fr11
cmsubhss fr10,fr11,fr12,cc6,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmsubhss fr10,fr11,fr12,cc6,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr13
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x8000,0x8000,fr11
cmsubhss.p fr10,fr10,fr12,cc6,1
cmsubhss fr11,fr10,fr13,cc6,0
test_fr_limmed 0xdead,0xbeef,fr12
test_fr_limmed 0xbeef,0xdead,fr13
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
;
set_fr_iimmed 0xdead,0xbeef,fr12
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmsubhss fr10,fr11,fr12,cc3,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0x0000,fr10
set_fr_iimmed 0x0000,0xbeef,fr11
cmsubhss fr10,fr11,fr12,cc3,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
cmsubhss fr10,fr11,fr12,cc3,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmsubhss fr10,fr11,fr12,cc3,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0xffff,0xffff,fr11
cmsubhss fr10,fr11,fr12,cc3,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0xfffe,0xffff,fr11
cmsubhss fr10,fr11,fr12,cc7,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x0001,0x0002,fr11
cmsubhss fr10,fr11,fr12,cc7,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmsubhss fr10,fr11,fr12,cc7,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr13
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x8000,0x8000,fr11
cmsubhss.p fr10,fr10,fr12,cc7,1
cmsubhss fr11,fr10,fr13,cc7,0
test_fr_limmed 0xdead,0xbeef,fr12
test_fr_limmed 0xbeef,0xdead,fr13
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
pass
/dcul.cgs
0,0 → 1,118
# FRV testcase for dcul GRi
# mach: all
 
.include "../testutils.inc"
 
start
 
.global dcul
dcul:
or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode
 
; preload and lock all the lines in set 0 of the data cache
set_gr_immed 0x70000,gr10
lock_data_cache gr10
set_mem_immed 0x11111111,gr10
test_mem_immed 0x11111111,gr10
 
inc_gr_immed 0x2000,gr10
set_gr_immed 1,gr11
lock_data_cache gr10
set_mem_immed 0x22222222,gr10
test_mem_immed 0x22222222,gr10
 
inc_gr_immed 0x2000,gr10
set_gr_immed 63,gr11
lock_data_cache gr10
set_mem_immed 0x33333333,gr10
test_mem_immed 0x33333333,gr10
 
inc_gr_immed 0x2000,gr10
set_gr_immed 64,gr11
lock_data_cache gr10
set_mem_immed 0x44444444,gr10
test_mem_immed 0x44444444,gr10
 
; Now write to another address which should be in the same set
; the write should go through to memory, since all the lines in the
; set are locked
inc_gr_immed 0x2000,gr10
set_mem_immed 0xdeadbeef,gr10
test_mem_immed 0xdeadbeef,gr10
 
; Invalidate the data cache. Only the last value stored should have made
; it through to memory
set_gr_immed 0x70000,gr10
invalidate_data_cache gr10
test_mem_immed 0,gr10
 
inc_gr_immed 0x2000,gr10
invalidate_data_cache gr10
test_mem_immed 0,gr10
 
inc_gr_immed 0x2000,gr10
invalidate_data_cache gr10
test_mem_immed 0,gr10
 
inc_gr_immed 0x2000,gr10
invalidate_data_cache gr10
test_mem_immed 0,gr10
 
inc_gr_immed 0x2000,gr10
invalidate_data_cache gr10
test_mem_immed 0xdeadbeef,gr10
 
; Now preload load and lock all the lines in set 0 of the data cache
; again
set_gr_immed 0x70000,gr10
lock_data_cache gr10
set_mem_immed 0x11111111,gr10
test_mem_immed 0x11111111,gr10
 
inc_gr_immed 0x2000,gr10
set_gr_immed 1,gr11
lock_data_cache gr10
set_mem_immed 0x22222222,gr10
test_mem_immed 0x22222222,gr10
 
inc_gr_immed 0x2000,gr10
set_gr_immed 63,gr11
lock_data_cache gr10
set_mem_immed 0x33333333,gr10
test_mem_immed 0x33333333,gr10
 
inc_gr_immed 0x2000,gr10
set_gr_immed 64,gr11
lock_data_cache gr10
set_mem_immed 0x44444444,gr10
test_mem_immed 0x44444444,gr10
 
; unlock one line
set_gr_immed 0x78000,gr10
dcul gr10
 
; Now write to another address which should be in the same set.
set_gr_immed 0x7a000,gr10
set_mem_immed 0xbeefdead,gr10
 
; All of the stored values should be retrievable
 
set_gr_immed 0x70000,gr10
test_mem_immed 0x11111111,gr10
 
inc_gr_immed 0x2000,gr10
test_mem_immed 0x22222222,gr10
 
inc_gr_immed 0x2000,gr10
test_mem_immed 0x33333333,gr10
 
inc_gr_immed 0x2000,gr10
test_mem_immed 0x44444444,gr10
 
inc_gr_immed 0x2000,gr10
test_mem_immed 0xdeadbeef,gr10
 
inc_gr_immed 0x2000,gr10
test_mem_immed 0xbeefdead,gr10
 
pass
/cmsubhus.cgs
0,0 → 1,427
# frv testcase for cmsubhus $FRi,$FRj,$FRj,$CCi,$cond
# mach: all
 
.include "../testutils.inc"
 
start
 
.global cmsubhus
cmsubhus:
set_spr_immed 0x1b1b,cccr
 
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmsubhus fr10,fr11,fr12,cc0,1
test_fr_limmed 0x0000,0x0000,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0xbeef,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmsubhus fr10,fr11,fr12,cc0,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmsubhus fr10,fr11,fr12,cc0,1
test_fr_limmed 0x0123,0x4567,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmsubhus fr10,fr11,fr12,cc0,1
test_fr_limmed 0x7ffc,0x7ffd,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0001,0x0002,fr11
cmsubhus fr10,fr11,fr12,cc4,1
test_fr_limmed 0x0000,0x0000,fr12
test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmsubhus fr10,fr11,fr12,cc4,1
test_fr_limmed 0x0000,0x0000,fr12
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0002,fr11
cmsubhus.p fr10,fr10,fr12,cc4,1
cmsubhus fr10,fr11,fr13,cc4,1
test_fr_limmed 0x0000,0x0000,fr12
test_fr_limmed 0x0000,0x0000,fr13
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmsubhus fr10,fr11,fr12,cc1,0
test_fr_limmed 0x0000,0x0000,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0xbeef,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmsubhus fr10,fr11,fr12,cc1,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmsubhus fr10,fr11,fr12,cc1,0
test_fr_limmed 0x0123,0x4567,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmsubhus fr10,fr11,fr12,cc1,0
test_fr_limmed 0x7ffc,0x7ffd,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0001,0x0002,fr11
cmsubhus fr10,fr11,fr12,cc5,0
test_fr_limmed 0x0000,0x0000,fr12
test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmsubhus fr10,fr11,fr12,cc5,0
test_fr_limmed 0x0000,0x0000,fr12
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0002,fr11
cmsubhus.p fr10,fr10,fr12,cc5,0
cmsubhus fr10,fr11,fr13,cc5,0
test_fr_limmed 0x0000,0x0000,fr12
test_fr_limmed 0x0000,0x0000,fr13
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_fr_iimmed 0xdead,0xbeef,fr12
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmsubhus fr10,fr11,fr12,cc0,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmsubhus fr10,fr11,fr12,cc0,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmsubhus fr10,fr11,fr12,cc0,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmsubhus fr10,fr11,fr12,cc0,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0001,0x0002,fr11
cmsubhus fr10,fr11,fr12,cc4,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmsubhus fr10,fr11,fr12,cc4,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr13
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0002,fr11
cmsubhus.p fr10,fr10,fr12,cc4,0
cmsubhus fr10,fr11,fr13,cc4,0
test_fr_limmed 0xdead,0xbeef,fr12
test_fr_limmed 0xbeef,0xdead,fr13
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0xbeef,fr12
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmsubhus fr10,fr11,fr12,cc1,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmsubhus fr10,fr11,fr12,cc1,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmsubhus fr10,fr11,fr12,cc1,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmsubhus fr10,fr11,fr12,cc1,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0001,0x0002,fr11
cmsubhus fr10,fr11,fr12,cc5,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmsubhus fr10,fr11,fr12,cc5,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr13
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0002,fr11
cmsubhus.p fr10,fr10,fr12,cc5,1
cmsubhus fr10,fr11,fr13,cc5,1
test_fr_limmed 0xdead,0xbeef,fr12
test_fr_limmed 0xbeef,0xdead,fr13
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0xbeef,fr12
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmsubhus fr10,fr11,fr12,cc2,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmsubhus fr10,fr11,fr12,cc2,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmsubhus fr10,fr11,fr12,cc2,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmsubhus fr10,fr11,fr12,cc2,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0001,0x0002,fr11
cmsubhus fr10,fr11,fr12,cc6,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmsubhus fr10,fr11,fr12,cc6,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr13
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0002,fr11
cmsubhus.p fr10,fr10,fr12,cc6,0
cmsubhus fr10,fr11,fr13,cc6,1
test_fr_limmed 0xdead,0xbeef,fr12
test_fr_limmed 0xbeef,0xdead,fr13
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
;
set_fr_iimmed 0xdead,0xbeef,fr12
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmsubhus fr10,fr11,fr12,cc3,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmsubhus fr10,fr11,fr12,cc3,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmsubhus fr10,fr11,fr12,cc3,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmsubhus fr10,fr11,fr12,cc3,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0001,0x0002,fr11
cmsubhus fr10,fr11,fr12,cc7,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmsubhus fr10,fr11,fr12,cc7,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr13
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0002,fr11
cmsubhus.p fr10,fr10,fr12,cc7,0
cmsubhus fr10,fr11,fr13,cc7,1
test_fr_limmed 0xdead,0xbeef,fr12
test_fr_limmed 0xbeef,0xdead,fr13
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
pass
/maddaccs.cgs
0,0 → 1,128
# frv testcase for maddaccs $ACC40Si,$ACC40Sk
# mach: all
 
.include "../testutils.inc"
 
start
 
.global maddaccs
maddaccs:
set_accg_immed 0,accg0
set_acc_immed 0x00000000,acc0
set_accg_immed 0,accg1
set_acc_immed 0x00000000,acc1
maddaccs acc0,acc3
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg3
test_acc_limmed 0x0000,0x0000,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0xdead0000,acc0
set_accg_immed 0,accg1
set_acc_immed 0x0000beef,acc1
maddaccs acc0,acc3
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg3
test_acc_limmed 0xdead,0xbeef,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0x0000dead,acc0
set_accg_immed 0,accg1
set_acc_immed 0xbeef0000,acc1
maddaccs acc0,acc3
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg3
test_acc_limmed 0xbeef,0xdead,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0x12345678,acc0
set_accg_immed 0,accg1
set_acc_immed 0x11111111,acc1
maddaccs acc0,acc3
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg3
test_acc_limmed 0x2345,0x6789,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0x12345678,acc0
set_accg_immed 0,accg1
set_acc_immed 0xffffffff,acc1
maddaccs acc0,acc3
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 1,accg3
test_acc_limmed 0x1234,0x5677,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0x12345678,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xffffffff,acc1
maddaccs acc0,acc3
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg3
test_acc_limmed 0x1234,0x5677,acc3
 
set_spr_immed 0,msr0
set_accg_immed 0x7f,accg0
set_acc_immed 0xfffe7ffe,acc0
set_accg_immed 0x0,accg1
set_acc_immed 0x00020001,acc1
maddaccs acc0,acc3
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
test_accg_immed 0x7f,accg3
test_acc_limmed 0xffff,0xffff,acc3
 
set_spr_immed 0,msr0
set_accg_immed 0x80,accg0
set_acc_immed 0x00000001,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xfffffffe,acc1
maddaccs acc0,acc3
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
test_accg_immed 0x80,accg3
test_acc_limmed 0x0000,0x0000,acc3
 
set_spr_immed 0,msr0
set_accg_immed 0,accg0
set_acc_immed 0x00000001,acc0
set_accg_immed 0,accg1
set_acc_immed 0x00000001,acc1
set_accg_immed 0,accg4
set_acc_immed 0x00000001,acc4
set_accg_immed 0x7f,accg5
set_acc_immed 0xffffffff,acc5
maddaccs.p acc0,acc1
maddaccs acc4,acc5
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x0002,acc1
test_accg_immed 0x7f,accg5
test_acc_limmed 0xffff,0xffff,acc5
 
pass
/msubaccs.cgs
0,0 → 1,128
# frv testcase for msubaccs $ACC40Si,$ACC40Sk
# mach: all
 
.include "../testutils.inc"
 
start
 
.global msubaccs
msubaccs:
set_accg_immed 0,accg0
set_acc_immed 0x00000000,acc0
set_accg_immed 0,accg1
set_acc_immed 0x00000000,acc1
msubaccs acc0,acc3
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg3
test_acc_limmed 0x0000,0x0000,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0xdead0000,acc0
set_accg_immed 0,accg1
set_acc_immed 0x0000beef,acc1
msubaccs acc0,acc3
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg3
test_acc_limmed 0xdeac,0x4111,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0x0000dead,acc0
set_accg_immed 0,accg1
set_acc_immed 0xbeef0000,acc1
msubaccs acc0,acc3
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg3
test_acc_limmed 0x4111,0xdead,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0x12345678,acc0
set_accg_immed 0,accg1
set_acc_immed 0x11111111,acc1
msubaccs acc0,acc3
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg3
test_acc_limmed 0x0123,0x4567,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0x12345678,acc0
set_accg_immed 0,accg1
set_acc_immed 0xffffffff,acc1
msubaccs acc0,acc3
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg3
test_acc_limmed 0x1234,0x5679,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0x12345678,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xffffffff,acc1
msubaccs acc0,acc3
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg3
test_acc_limmed 0x1234,0x5679,acc3
 
set_spr_immed 0,msr0
set_accg_immed 0x7f,accg0
set_acc_immed 0xfffffffe,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xfffffffe,acc1
msubaccs acc0,acc3
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
test_accg_immed 0x7f,accg3
test_acc_limmed 0xffff,0xffff,acc3
 
set_spr_immed 0,msr0
set_accg_immed 0x80,accg0
set_acc_immed 0x00000001,acc0
set_accg_immed 0,accg1
set_acc_immed 0x00000002,acc1
msubaccs acc0,acc3
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
test_accg_immed 0x80,accg3
test_acc_limmed 0x0000,0x0000,acc3
 
set_spr_immed 0,msr0
set_accg_immed 0,accg0
set_acc_immed 0x00000001,acc0
set_accg_immed 0,accg1
set_acc_immed 0x00000001,acc1
set_accg_immed 0,accg4
set_acc_immed 0x00000001,acc4
set_accg_immed 0x80,accg5
set_acc_immed 0x00000000,acc5
msubaccs.p acc0,acc1
msubaccs acc4,acc5
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x0000,acc1
test_accg_immed 0x7f,accg5
test_acc_limmed 0xffff,0xffff,acc5
 
pass
/mdaddaccs.cgs
0,0 → 1,102
# frv testcase for mdaddaccs $ACC40Si,$ACC40Sk
# mach: all
 
.include "../testutils.inc"
 
start
 
.global mdaddaccs
mdaddaccs:
set_accg_immed 0,accg0
set_acc_immed 0x00000000,acc0
set_accg_immed 0,accg1
set_acc_immed 0x00000000,acc1
set_accg_immed 0,accg2
set_acc_immed 0xdead0000,acc2
set_accg_immed 0,accg3
set_acc_immed 0x0000beef,acc3
mdaddaccs acc0,acc2
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg2
test_acc_limmed 0x0000,0x0000,acc2
test_accg_immed 0,accg3
test_acc_limmed 0xdead,0xbeef,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0x0000dead,acc0
set_accg_immed 0,accg1
set_acc_immed 0xbeef0000,acc1
set_accg_immed 0,accg2
set_acc_immed 0x12345678,acc2
set_accg_immed 0,accg3
set_acc_immed 0x11111111,acc3
mdaddaccs acc0,acc2
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg2
test_acc_limmed 0xbeef,0xdead,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x2345,0x6789,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0x12345678,acc0
set_accg_immed 0,accg1
set_acc_immed 0xffffffff,acc1
set_accg_immed 0,accg2
set_acc_immed 0x12345678,acc2
set_accg_immed 0xff,accg3
set_acc_immed 0xffffffff,acc3
mdaddaccs acc0,acc2
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 1,accg2
test_acc_limmed 0x1234,0x5677,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x1234,0x5677,acc3
 
set_spr_immed 0,msr0
set_accg_immed 0x7f,accg0
set_acc_immed 0xfffe7ffe,acc0
set_accg_immed 0x0,accg1
set_acc_immed 0x00020001,acc1
set_accg_immed 0x80,accg2
set_acc_immed 0x00000001,acc2
set_accg_immed 0xff,accg3
set_acc_immed 0xfffffffe,acc3
mdaddaccs acc0,acc2
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
test_accg_immed 0x7f,accg2
test_acc_limmed 0xffff,0xffff,acc2
test_accg_immed 0x80,accg3
test_acc_limmed 0x0000,0x0000,acc3
 
set_spr_immed 0,msr0
set_accg_immed 0,accg0
set_acc_immed 0x00000001,acc0
set_accg_immed 0,accg1
set_acc_immed 0x00000001,acc1
set_accg_immed 0,accg2
set_acc_immed 0x00000001,acc2
set_accg_immed 0x7f,accg3
set_acc_immed 0xffffffff,acc3
mdaddaccs acc0,acc2
test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
test_accg_immed 0,accg2
test_acc_limmed 0x0000,0x0002,acc2
test_accg_immed 0x7f,accg3
test_acc_limmed 0xffff,0xffff,acc3
 
pass
/mdsubaccs.cgs
0,0 → 1,102
# frv testcase for mdsubaccs $ACC40Si,$ACC40Sk
# mach: all
 
.include "../testutils.inc"
 
start
 
.global mdsubaccs
mdsubaccs:
set_accg_immed 0,accg0
set_acc_immed 0x00000000,acc0
set_accg_immed 0,accg1
set_acc_immed 0x00000000,acc1
set_accg_immed 0,accg2
set_acc_immed 0xdead0000,acc2
set_accg_immed 0,accg3
set_acc_immed 0x0000beef,acc3
mdsubaccs acc0,acc2
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg2
test_acc_limmed 0x0000,0x0000,acc2
test_accg_immed 0,accg3
test_acc_limmed 0xdeac,0x4111,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0x0000dead,acc0
set_accg_immed 0,accg1
set_acc_immed 0xbeef0000,acc1
set_accg_immed 0,accg2
set_acc_immed 0x12345678,acc2
set_accg_immed 0,accg3
set_acc_immed 0x11111111,acc3
mdsubaccs acc0,acc2
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg2
test_acc_limmed 0x4111,0xdead,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x0123,0x4567,acc3
 
set_accg_immed 0,accg0
set_acc_immed 0x12345678,acc0
set_accg_immed 0,accg1
set_acc_immed 0xffffffff,acc1
set_accg_immed 0,accg2
set_acc_immed 0x12345678,acc2
set_accg_immed 0xff,accg3
set_acc_immed 0xffffffff,acc3
mdsubaccs acc0,acc2
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg2
test_acc_limmed 0x1234,0x5679,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x1234,0x5679,acc3
 
set_spr_immed 0,msr0
set_accg_immed 0x7f,accg0
set_acc_immed 0xfffffffe,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xfffffffe,acc1
set_accg_immed 0x80,accg2
set_acc_immed 0x00000001,acc2
set_accg_immed 0,accg3
set_acc_immed 0x00000002,acc3
mdsubaccs acc0,acc2
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
test_accg_immed 0x7f,accg2
test_acc_limmed 0xffff,0xffff,acc2
test_accg_immed 0x80,accg3
test_acc_limmed 0x0000,0x0000,acc3
 
set_spr_immed 0,msr0
set_accg_immed 0,accg0
set_acc_immed 0x00000001,acc0
set_accg_immed 0,accg1
set_acc_immed 0x00000001,acc1
set_accg_immed 0,accg2
set_acc_immed 0x00000001,acc2
set_accg_immed 0x80,accg3
set_acc_immed 0x00000000,acc3
mdsubaccs acc0,acc2
test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
test_accg_immed 0,accg2
test_acc_limmed 0x0000,0x0000,acc2
test_accg_immed 0x7f,accg3
test_acc_limmed 0xffff,0xffff,acc3
 
pass
/mqsubhss.cgs
0,0 → 1,76
# frv testcase for mqsubhss $FRi,$FRj,$FRj
# mach: all
 
.include "../testutils.inc"
 
start
 
.global msubhss
msubhss:
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
mqsubhss fr10,fr12,fr14
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0xdead,0x4111,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
mqsubhss fr10,fr12,fr14
test_fr_limmed 0x4111,0xdead,fr14
test_fr_limmed 0x0123,0x4567,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0xffff,0xffff,fr12
set_fr_iimmed 0xfffe,0xffff,fr13
mqsubhss fr10,fr12,fr14
test_fr_limmed 0x1235,0x5679,fr14
test_fr_limmed 0x7fff,0x7fff,fr15
test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8001,0x8001,fr11
set_fr_iimmed 0x0001,0x0002,fr12
set_fr_iimmed 0x0002,0x0001,fr13
mqsubhss fr10,fr12,fr14
test_fr_limmed 0x8000,0x8000,fr14
test_fr_limmed 0x8000,0x8000,fr15
test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0xffff,0xffff,fr11
set_fr_iimmed 0x8000,0x8000,fr12
set_fr_iimmed 0x8000,0x8000,fr13
mqsubhss.p fr10,fr10,fr14
mqsubhss fr12,fr10,fr16
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0x0000,0x0000,fr15
test_fr_limmed 0x8000,0x8000,fr16
test_fr_limmed 0x8001,0x8001,fr17
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
pass
/mqsubhus.cgs
0,0 → 1,63
# frv testcase for msubhus $FRi,$FRj,$FRj
# mach: all
 
.include "../testutils.inc"
 
start
 
.global msubhus
msubhus:
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0xbeef,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0x0000,fr13
mqsubhus fr10,fr12,fr14
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0xdead,0xbeef,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0x1111,0x1111,fr12
set_fr_iimmed 0x0002,0x0001,fr13
mqsubhus fr10,fr12,fr14
test_fr_limmed 0x0123,0x4567,fr14
test_fr_limmed 0x7ffc,0x7ffd,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0001,0x0001,fr11
set_fr_iimmed 0x0001,0x0002,fr12
set_fr_iimmed 0x0002,0x0001,fr13
mqsubhus fr10,fr12,fr14
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0x0000,0x0000,fr15
test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x0002,0x0002,fr11
set_fr_iimmed 0x0000,0x0001,fr12
set_fr_iimmed 0x0002,0x0003,fr13
mqsubhus.p fr10,fr10,fr14
mqsubhus fr10,fr12,fr16
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0x0000,0x0000,fr15
test_fr_limmed 0x0001,0x0000,fr16
test_fr_limmed 0x0000,0x0000,fr17
test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
pass
/cmqaddhss.cgs
0,0 → 1,429
# frv testcase for cmqaddhss $FRi,$FRj,$FRj,$CCi,$cond
# mach: all
 
.include "../testutils.inc"
 
start
 
.global cmqaddhss
cmqaddhss:
set_spr_immed 0x1b1b,cccr
 
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
cmqaddhss fr10,fr12,fr14,cc0,1
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0xdead,0xbeef,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
cmqaddhss fr10,fr12,fr14,cc0,1
test_fr_limmed 0xbeef,0xdead,fr14
test_fr_limmed 0x2345,0x6789,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0xffff,0xffff,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqaddhss fr10,fr12,fr14,cc0,1
test_fr_limmed 0x1233,0x5677,fr14
test_fr_limmed 0x7fff,0x7fff,fr15
test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8001,0x8001,fr11
set_fr_iimmed 0xffff,0xfffe,fr12
set_fr_iimmed 0xfffe,0xfffe,fr13
cmqaddhss fr10,fr12,fr14,cc4,1
test_fr_limmed 0x8000,0x8000,fr14
test_fr_limmed 0x8000,0x8000,fr15
test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0xffff,0xffff,fr11
set_fr_iimmed 0x7fff,0x0000,fr12
set_fr_iimmed 0x0000,0x8000,fr13
cmqaddhss.p fr10,fr10,fr14,cc4,1
cmqaddhss fr12,fr12,fr16,cc4,1
test_fr_limmed 0x0002,0x0002,fr14
test_fr_limmed 0xfffe,0xfffe,fr15
test_fr_limmed 0x7fff,0x0000,fr16
test_fr_limmed 0x0000,0x8000,fr17
test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
cmqaddhss fr10,fr12,fr14,cc1,0
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0xdead,0xbeef,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
cmqaddhss fr10,fr12,fr14,cc1,0
test_fr_limmed 0xbeef,0xdead,fr14
test_fr_limmed 0x2345,0x6789,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0xffff,0xffff,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqaddhss fr10,fr12,fr14,cc1,0
test_fr_limmed 0x1233,0x5677,fr14
test_fr_limmed 0x7fff,0x7fff,fr15
test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8001,0x8001,fr11
set_fr_iimmed 0xffff,0xfffe,fr12
set_fr_iimmed 0xfffe,0xfffe,fr13
cmqaddhss fr10,fr12,fr14,cc5,0
test_fr_limmed 0x8000,0x8000,fr14
test_fr_limmed 0x8000,0x8000,fr15
test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0xffff,0xffff,fr11
set_fr_iimmed 0x7fff,0x0000,fr12
set_fr_iimmed 0x0000,0x8000,fr13
cmqaddhss.p fr10,fr10,fr14,cc5,0
cmqaddhss fr12,fr12,fr16,cc5,0
test_fr_limmed 0x0002,0x0002,fr14
test_fr_limmed 0xfffe,0xfffe,fr15
test_fr_limmed 0x7fff,0x0000,fr16
test_fr_limmed 0x0000,0x8000,fr17
test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_fr_iimmed 0x1111,0x1111,fr14
set_fr_iimmed 0x2222,0x2222,fr15
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
cmqaddhss fr10,fr12,fr14,cc0,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
cmqaddhss fr10,fr12,fr14,cc0,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0xffff,0xffff,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqaddhss fr10,fr12,fr14,cc0,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8001,0x8001,fr11
set_fr_iimmed 0xffff,0xfffe,fr12
set_fr_iimmed 0xfffe,0xfffe,fr13
cmqaddhss fr10,fr12,fr14,cc4,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x3333,0x3333,fr16
set_fr_iimmed 0x4444,0x4444,fr17
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0xffff,0xffff,fr11
set_fr_iimmed 0x7fff,0x0000,fr12
set_fr_iimmed 0x0000,0x8000,fr13
cmqaddhss.p fr10,fr10,fr14,cc4,0
cmqaddhss fr12,fr12,fr16,cc4,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_fr_limmed 0x3333,0x3333,fr16
test_fr_limmed 0x4444,0x4444,fr17
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1111,0x1111,fr14
set_fr_iimmed 0x2222,0x2222,fr15
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
cmqaddhss fr10,fr12,fr14,cc1,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
cmqaddhss fr10,fr12,fr14,cc1,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0xffff,0xffff,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqaddhss fr10,fr12,fr14,cc1,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8001,0x8001,fr11
set_fr_iimmed 0xffff,0xfffe,fr12
set_fr_iimmed 0xfffe,0xfffe,fr13
cmqaddhss fr10,fr12,fr14,cc5,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x3333,0x3333,fr16
set_fr_iimmed 0x4444,0x4444,fr17
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0xffff,0xffff,fr11
set_fr_iimmed 0x7fff,0x0000,fr12
set_fr_iimmed 0x0000,0x8000,fr13
cmqaddhss.p fr10,fr10,fr14,cc5,1
cmqaddhss fr12,fr12,fr16,cc5,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_fr_limmed 0x3333,0x3333,fr16
test_fr_limmed 0x4444,0x4444,fr17
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1111,0x1111,fr14
set_fr_iimmed 0x2222,0x2222,fr15
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
cmqaddhss fr10,fr12,fr14,cc2,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
cmqaddhss fr10,fr12,fr14,cc2,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0xffff,0xffff,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqaddhss fr10,fr12,fr14,cc2,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8001,0x8001,fr11
set_fr_iimmed 0xffff,0xfffe,fr12
set_fr_iimmed 0xfffe,0xfffe,fr13
cmqaddhss fr10,fr12,fr14,cc6,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x3333,0x3333,fr16
set_fr_iimmed 0x4444,0x4444,fr17
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0xffff,0xffff,fr11
set_fr_iimmed 0x7fff,0x0000,fr12
set_fr_iimmed 0x0000,0x8000,fr13
cmqaddhss.p fr10,fr10,fr14,cc6,1
cmqaddhss fr12,fr12,fr16,cc6,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_fr_limmed 0x3333,0x3333,fr16
test_fr_limmed 0x4444,0x4444,fr17
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
;
set_fr_iimmed 0x1111,0x1111,fr14
set_fr_iimmed 0x2222,0x2222,fr15
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
cmqaddhss fr10,fr12,fr14,cc3,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
cmqaddhss fr10,fr12,fr14,cc3,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x7ffe,0x7ffe,fr11
set_fr_iimmed 0xffff,0xffff,fr12
set_fr_iimmed 0x0002,0x0001,fr13
cmqaddhss fr10,fr12,fr14,cc3,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8001,0x8001,fr11
set_fr_iimmed 0xffff,0xfffe,fr12
set_fr_iimmed 0xfffe,0xfffe,fr13
cmqaddhss fr10,fr12,fr14,cc7,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x3333,0x3333,fr16
set_fr_iimmed 0x4444,0x4444,fr17
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0xffff,0xffff,fr11
set_fr_iimmed 0x7fff,0x0000,fr12
set_fr_iimmed 0x0000,0x8000,fr13
cmqaddhss.p fr10,fr10,fr14,cc7,1
cmqaddhss fr12,fr12,fr16,cc7,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_fr_limmed 0x3333,0x3333,fr16
test_fr_limmed 0x4444,0x4444,fr17
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
pass
/cmqaddhus.cgs
0,0 → 1,345
# frv testcase for cmqaddhus $FRi,$FRj,$FRj,$CCi,$cond
# mach: all
 
.include "../testutils.inc"
 
start
 
.global cmqaddhus
cmqaddhus:
set_spr_immed 0x1b1b,cccr
 
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
cmqaddhus fr10,fr12,fr14,cc0,1
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0xdead,0xbeef,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
cmqaddhus fr10,fr12,fr14,cc0,1
test_fr_limmed 0xbeef,0xdead,fr14
test_fr_limmed 0x2345,0x6789,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
set_fr_iimmed 0x0002,0x0001,fr12
set_fr_iimmed 0x0001,0x0002,fr13
cmqaddhus fr10,fr12,fr14,cc4,1
test_fr_limmed 0x8000,0x7fff,fr14
test_fr_limmed 0xffff,0xffff,fr15
test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0002,0x0001,fr10
set_fr_iimmed 0x0001,0x0001,fr11
set_fr_iimmed 0xfffe,0xfffe,fr12
set_fr_iimmed 0x8000,0x8000,fr13
cmqaddhus.p fr10,fr10,fr14,cc4,1
cmqaddhus fr12,fr12,fr16,cc4,1
test_fr_limmed 0x0004,0x0002,fr14
test_fr_limmed 0x0002,0x0002,fr15
test_fr_limmed 0xffff,0xffff,fr16
test_fr_limmed 0xffff,0xffff,fr17
test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
cmqaddhus fr10,fr12,fr14,cc1,0
test_fr_limmed 0x0000,0x0000,fr14
test_fr_limmed 0xdead,0xbeef,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
cmqaddhus fr10,fr12,fr14,cc1,0
test_fr_limmed 0xbeef,0xdead,fr14
test_fr_limmed 0x2345,0x6789,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
set_fr_iimmed 0x0002,0x0001,fr12
set_fr_iimmed 0x0001,0x0002,fr13
cmqaddhus fr10,fr12,fr14,cc5,0
test_fr_limmed 0x8000,0x7fff,fr14
test_fr_limmed 0xffff,0xffff,fr15
test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0002,0x0001,fr10
set_fr_iimmed 0x0001,0x0001,fr11
set_fr_iimmed 0xfffe,0xfffe,fr12
set_fr_iimmed 0x8000,0x8000,fr13
cmqaddhus.p fr10,fr10,fr14,cc5,0
cmqaddhus fr12,fr12,fr16,cc5,0
test_fr_limmed 0x0004,0x0002,fr14
test_fr_limmed 0x0002,0x0002,fr15
test_fr_limmed 0xffff,0xffff,fr16
test_fr_limmed 0xffff,0xffff,fr17
test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_fr_iimmed 0x1111,0x1111,fr14
set_fr_iimmed 0x2222,0x2222,fr15
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
cmqaddhus fr10,fr12,fr14,cc0,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
cmqaddhus fr10,fr12,fr14,cc0,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
set_fr_iimmed 0x0002,0x0001,fr12
set_fr_iimmed 0x0001,0x0002,fr13
cmqaddhus fr10,fr12,fr14,cc4,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x3333,0x3333,fr16
set_fr_iimmed 0x4444,0x4444,fr17
set_spr_immed 0,msr0
set_fr_iimmed 0x0002,0x0001,fr10
set_fr_iimmed 0x0001,0x0001,fr11
set_fr_iimmed 0xfffe,0xfffe,fr12
set_fr_iimmed 0x8000,0x8000,fr13
cmqaddhus.p fr10,fr10,fr14,cc4,0
cmqaddhus fr12,fr12,fr16,cc4,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_fr_limmed 0x3333,0x3333,fr16
test_fr_limmed 0x4444,0x4444,fr17
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1111,0x1111,fr14
set_fr_iimmed 0x2222,0x2222,fr15
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
cmqaddhus fr10,fr12,fr14,cc1,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
cmqaddhus fr10,fr12,fr14,cc1,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
set_fr_iimmed 0x0002,0x0001,fr12
set_fr_iimmed 0x0001,0x0002,fr13
cmqaddhus fr10,fr12,fr14,cc5,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x3333,0x3333,fr16
set_fr_iimmed 0x4444,0x4444,fr17
set_spr_immed 0,msr0
set_fr_iimmed 0x0002,0x0001,fr10
set_fr_iimmed 0x0001,0x0001,fr11
set_fr_iimmed 0xfffe,0xfffe,fr12
set_fr_iimmed 0x8000,0x8000,fr13
cmqaddhus.p fr10,fr10,fr14,cc5,1
cmqaddhus fr12,fr12,fr16,cc5,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_fr_limmed 0x3333,0x3333,fr16
test_fr_limmed 0x4444,0x4444,fr17
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1111,0x1111,fr14
set_fr_iimmed 0x2222,0x2222,fr15
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
cmqaddhus fr10,fr12,fr14,cc2,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
cmqaddhus fr10,fr12,fr14,cc2,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
set_fr_iimmed 0x0002,0x0001,fr12
set_fr_iimmed 0x0001,0x0002,fr13
cmqaddhus fr10,fr12,fr14,cc6,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x3333,0x3333,fr16
set_fr_iimmed 0x4444,0x4444,fr17
set_spr_immed 0,msr0
set_fr_iimmed 0x0002,0x0001,fr10
set_fr_iimmed 0x0001,0x0001,fr11
set_fr_iimmed 0xfffe,0xfffe,fr12
set_fr_iimmed 0x8000,0x8000,fr13
cmqaddhus.p fr10,fr10,fr14,cc6,0
cmqaddhus fr12,fr12,fr16,cc6,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_fr_limmed 0x3333,0x3333,fr16
test_fr_limmed 0x4444,0x4444,fr17
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1111,0x1111,fr14
set_fr_iimmed 0x2222,0x2222,fr15
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0xdead,0x0000,fr11
set_fr_iimmed 0x0000,0x0000,fr12
set_fr_iimmed 0x0000,0xbeef,fr13
cmqaddhus fr10,fr12,fr14,cc3,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0x1234,0x5678,fr11
set_fr_iimmed 0xbeef,0x0000,fr12
set_fr_iimmed 0x1111,0x1111,fr13
cmqaddhus fr10,fr12,fr14,cc3,0
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
set_fr_iimmed 0x0002,0x0001,fr12
set_fr_iimmed 0x0001,0x0002,fr13
cmqaddhus fr10,fr12,fr14,cc7,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x3333,0x3333,fr16
set_fr_iimmed 0x4444,0x4444,fr17
set_spr_immed 0,msr0
set_fr_iimmed 0x0002,0x0001,fr10
set_fr_iimmed 0x0001,0x0001,fr11
set_fr_iimmed 0xfffe,0xfffe,fr12
set_fr_iimmed 0x8000,0x8000,fr13
cmqaddhus.p fr10,fr10,fr14,cc7,0
cmqaddhus fr12,fr12,fr16,cc7,1
test_fr_limmed 0x1111,0x1111,fr14
test_fr_limmed 0x2222,0x2222,fr15
test_fr_limmed 0x3333,0x3333,fr16
test_fr_limmed 0x4444,0x4444,fr17
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
pass
/cmmachs.cgs
0,0 → 1,1545
# frv testcase for cmmachs $GRi,$GRj,$ACCk,$CCi,$cond
# mach: all
 
.include "../testutils.inc"
 
start
 
.global cmmachs
cmmachs:
set_spr_immed 0x1b1b,cccr
 
; Positive operands
set_spr_immed 0x0,msr0
set_accg_immed 0x0,accg0
set_acc_immed 0x0,acc0
set_accg_immed 0x0,accg1
set_acc_immed 0x0,acc1
set_fr_iimmed 2,3,fr7 ; multiply small numbers
set_fr_iimmed 3,2,fr8
cmmachs fr7,fr8,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
 
set_fr_iimmed 0,1,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
cmmachs fr7,fr8,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
 
set_fr_iimmed 2,1,fr7 ; multiply by 1
set_fr_iimmed 1,2,fr8
cmmachs fr7,fr8,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 8,acc0
test_accg_immed 0,accg1
test_acc_immed 8,acc1
 
set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr8
cmmachs fr7,fr8,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0,0x8006,acc0
test_accg_immed 0,accg1
test_acc_limmed 0,0x8006,acc1
 
set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
set_fr_iimmed 2,0x4000,fr8
cmmachs fr7,fr8,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0001,0x0006,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0001,0x0006,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x4000,0x0007,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x4000,0x0007,acc1
 
; Mixed operands
set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers
set_fr_iimmed 0xfffd,2,fr8
cmmachs fr7,fr8,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x4000,0x0001,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x4000,0x0001,acc1
 
set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1
set_fr_iimmed 1,0xfffe,fr8
cmmachs fr7,fr8,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0xffff,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0xffff,acc1
 
set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0
set_fr_iimmed 0,0xfffe,fr8
cmmachs fr7,fr8,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0xffff,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0xffff,acc1
 
set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result
set_fr_iimmed 0xfffe,0x2001,fr8
cmmachs fr7,fr8,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0xbffd,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0xbffd,acc1
 
set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result
set_fr_iimmed 0xfffe,0x4000,fr8
cmmachs fr7,fr8,acc0,cc4,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0x3ffd,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0x3ffd,acc1
 
set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result
set_fr_iimmed 0x8000,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc4,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xbffd,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xbffd,acc1
 
; Negative operands
set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers
set_fr_iimmed 0xfffd,0xfffe,fr8
cmmachs fr7,fr8,acc0,cc4,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xc003,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xc003,acc1
 
set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1
set_fr_iimmed 0xfffe,0xffff,fr8
cmmachs fr7,fr8,acc0,cc4,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xc005,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xc005,acc1
 
set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result
set_fr_iimmed 0x8001,0x8001,fr8
cmmachs fr7,fr8,acc0,cc4,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0x3ffec006,acc0
test_accg_immed 0,accg1
test_acc_immed 0x3ffec006,acc1
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr8
cmmachs fr7,fr8,acc0,cc4,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0x7ffec006,acc0
test_accg_immed 0,accg1
test_acc_immed 0x7ffec006,acc1
 
set_accg_immed 0x7f,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0x7f,accg1
set_acc_immed 0xffffffff,acc1
set_fr_iimmed 1,1,fr7
set_fr_iimmed 1,1,fr8
cmmachs fr7,fr8,acc0,cc4,1
;;;;;;;;;;;;
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x7f,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xffff,0xffff,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc4,1
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x7f,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xffff,0xffff,acc1
 
set_accg_immed -128,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed -128,accg1
set_acc_immed 0,acc1
set_fr_iimmed 0xffff,0,fr7
set_fr_iimmed 1,0xffff,fr8
cmmachs fr7,fr8,acc0,cc4,1
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x80,accg0
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x0000,0x8000,fr7 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc4,1
test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x80,accg0
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
 
; Positive operands
set_spr_immed 0x0,msr0
set_accg_immed 0x0,accg0 ; saturation
set_acc_immed 0x0,acc0
set_accg_immed 0x0,accg1
set_acc_immed 0x0,acc1
set_fr_iimmed 2,3,fr7 ; multiply small numbers
set_fr_iimmed 3,2,fr8
cmmachs fr7,fr8,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
 
set_fr_iimmed 0,1,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
cmmachs fr7,fr8,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
 
set_fr_iimmed 2,1,fr7 ; multiply by 1
set_fr_iimmed 1,2,fr8
cmmachs fr7,fr8,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 8,acc0
test_accg_immed 0,accg1
test_acc_immed 8,acc1
 
set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr8
cmmachs fr7,fr8,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0,0x8006,acc0
test_accg_immed 0,accg1
test_acc_limmed 0,0x8006,acc1
 
set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
set_fr_iimmed 2,0x4000,fr8
cmmachs fr7,fr8,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0001,0x0006,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0001,0x0006,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x4000,0x0007,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x4000,0x0007,acc1
 
; Mixed operands
set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers
set_fr_iimmed 0xfffd,2,fr8
cmmachs fr7,fr8,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x4000,0x0001,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x4000,0x0001,acc1
 
set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1
set_fr_iimmed 1,0xfffe,fr8
cmmachs fr7,fr8,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0xffff,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0xffff,acc1
 
set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0
set_fr_iimmed 0,0xfffe,fr8
cmmachs fr7,fr8,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0xffff,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0xffff,acc1
 
set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result
set_fr_iimmed 0xfffe,0x2001,fr8
cmmachs fr7,fr8,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0xbffd,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0xbffd,acc1
 
set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result
set_fr_iimmed 0xfffe,0x4000,fr8
cmmachs fr7,fr8,acc0,cc5,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0x3ffd,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0x3ffd,acc1
 
set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result
set_fr_iimmed 0x8000,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc5,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xbffd,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xbffd,acc1
 
; Negative operands
set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers
set_fr_iimmed 0xfffd,0xfffe,fr8
cmmachs fr7,fr8,acc0,cc5,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xc003,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xc003,acc1
 
set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1
set_fr_iimmed 0xfffe,0xffff,fr8
cmmachs fr7,fr8,acc0,cc5,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xc005,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xc005,acc1
 
set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result
set_fr_iimmed 0x8001,0x8001,fr8
cmmachs fr7,fr8,acc0,cc5,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0x3ffec006,acc0
test_accg_immed 0,accg1
test_acc_immed 0x3ffec006,acc1
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr8
cmmachs fr7,fr8,acc0,cc5,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0x7ffec006,acc0
test_accg_immed 0,accg1
test_acc_immed 0x7ffec006,acc1
 
set_accg_immed 0x7f,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0x7f,accg1
set_acc_immed 0xffffffff,acc1
set_fr_iimmed 1,1,fr7
set_fr_iimmed 1,1,fr8
cmmachs fr7,fr8,acc0,cc5,0
test_accg_immed 0x7f,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xffff,0xffff,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc5,0
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x7f,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xffff,0xffff,acc1
 
set_accg_immed 0x80,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed 0x80,accg1
set_acc_immed 0,acc1
set_fr_iimmed 0xffff,0,fr7
set_fr_iimmed 1,0xffff,fr8
cmmachs fr7,fr8,acc0,cc5,0
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x80,accg0
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x0000,0x8000,fr7 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc5,0
test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x80,accg0
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
 
; Positive operands
set_spr_immed 0x0,msr0
set_accg_immed 0x0,accg0
set_acc_immed 0x0,acc0
set_accg_immed 0x0,accg1
set_acc_immed 0x0,acc1
set_fr_iimmed 2,3,fr7 ; multiply small numbers
set_fr_iimmed 3,2,fr8
cmmachs fr7,fr8,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0,1,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
cmmachs fr7,fr8,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 2,1,fr7 ; multiply by 1
set_fr_iimmed 1,2,fr8
cmmachs fr7,fr8,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr8
cmmachs fr7,fr8,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
set_fr_iimmed 2,0x4000,fr8
cmmachs fr7,fr8,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
; Mixed operands
set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers
set_fr_iimmed 0xfffd,2,fr8
cmmachs fr7,fr8,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1
set_fr_iimmed 1,0xfffe,fr8
cmmachs fr7,fr8,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0
set_fr_iimmed 0,0xfffe,fr8
cmmachs fr7,fr8,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result
set_fr_iimmed 0xfffe,0x2001,fr8
cmmachs fr7,fr8,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result
set_fr_iimmed 0xfffe,0x4000,fr8
cmmachs fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result
set_fr_iimmed 0x8000,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
; Negative operands
set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers
set_fr_iimmed 0xfffd,0xfffe,fr8
cmmachs fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1
set_fr_iimmed 0xfffe,0xffff,fr8
cmmachs fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result
set_fr_iimmed 0x8001,0x8001,fr8
cmmachs fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr8
cmmachs fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_accg_immed 0x7f,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0x7f,accg1
set_acc_immed 0xffffffff,acc1
set_fr_iimmed 1,1,fr7
set_fr_iimmed 1,1,fr8
cmmachs fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0x7f,accg1
test_acc_immed 0xffffffff,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0x7f,accg1
test_acc_immed 0xffffffff,acc1
 
set_accg_immed 0x80,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed 0x80,accg1
set_acc_immed 0,acc1
set_fr_iimmed 0xffff,0,fr7
set_fr_iimmed 1,0xffff,fr8
cmmachs fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x80,accg0 ; saturation
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x0000,0x8000,fr7 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x80,accg0 ; saturation
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
 
; Positive operands
set_spr_immed 0x0,msr0
set_accg_immed 0x0,accg0
set_acc_immed 0x0,acc0
set_accg_immed 0x0,accg1
set_acc_immed 0x0,acc1
set_fr_iimmed 2,3,fr7 ; multiply small numbers
set_fr_iimmed 3,2,fr8
cmmachs fr7,fr8,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0,1,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
cmmachs fr7,fr8,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 2,1,fr7 ; multiply by 1
set_fr_iimmed 1,2,fr8
cmmachs fr7,fr8,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr8
cmmachs fr7,fr8,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
set_fr_iimmed 2,0x4000,fr8
cmmachs fr7,fr8,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
; Mixed operands
set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers
set_fr_iimmed 0xfffd,2,fr8
cmmachs fr7,fr8,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1
set_fr_iimmed 1,0xfffe,fr8
cmmachs fr7,fr8,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0
set_fr_iimmed 0,0xfffe,fr8
cmmachs fr7,fr8,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result
set_fr_iimmed 0xfffe,0x2001,fr8
cmmachs fr7,fr8,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result
set_fr_iimmed 0xfffe,0x4000,fr8
cmmachs fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result
set_fr_iimmed 0x8000,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
; Negative operands
set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers
set_fr_iimmed 0xfffd,0xfffe,fr8
cmmachs fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1
set_fr_iimmed 0xfffe,0xffff,fr8
cmmachs fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result
set_fr_iimmed 0x8001,0x8001,fr8
cmmachs fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr8
cmmachs fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_accg_immed 0x7f,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0x7f,accg1
set_acc_immed 0xffffffff,acc1
set_fr_iimmed 1,1,fr7
set_fr_iimmed 1,1,fr8
cmmachs fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0x7f,accg1
test_acc_immed 0xffffffff,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0x7f,accg1
test_acc_immed 0xffffffff,acc1
 
set_accg_immed 0x80,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed 0x80,accg1
set_acc_immed 0,acc1
set_fr_iimmed 0xffff,0,fr7
set_fr_iimmed 1,0xffff,fr8
cmmachs fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x80,accg0 ; saturation
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x0000,0x8000,fr7 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x80,accg0 ; saturation
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
 
; Positive operands
set_spr_immed 0x0,msr0
set_accg_immed 0x0,accg0
set_acc_immed 0x0,acc0
set_accg_immed 0x0,accg1
set_acc_immed 0x0,acc1
set_fr_iimmed 2,3,fr7 ; multiply small numbers
set_fr_iimmed 3,2,fr8
cmmachs fr7,fr8,acc0,cc2,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0,1,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
cmmachs fr7,fr8,acc0,cc2,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 2,1,fr7 ; multiply by 1
set_fr_iimmed 1,2,fr8
cmmachs fr7,fr8,acc0,cc2,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr8
cmmachs fr7,fr8,acc0,cc2,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
set_fr_iimmed 2,0x4000,fr8
cmmachs fr7,fr8,acc0,cc2,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc2,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
; Mixed operands
set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers
set_fr_iimmed 0xfffd,2,fr8
cmmachs fr7,fr8,acc0,cc2,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1
set_fr_iimmed 1,0xfffe,fr8
cmmachs fr7,fr8,acc0,cc2,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0
set_fr_iimmed 0,0xfffe,fr8
cmmachs fr7,fr8,acc0,cc2,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result
set_fr_iimmed 0xfffe,0x2001,fr8
cmmachs fr7,fr8,acc0,cc2,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result
set_fr_iimmed 0xfffe,0x4000,fr8
cmmachs fr7,fr8,acc0,cc6,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result
set_fr_iimmed 0x8000,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc6,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
; Negative operands
set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers
set_fr_iimmed 0xfffd,0xfffe,fr8
cmmachs fr7,fr8,acc0,cc6,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1
set_fr_iimmed 0xfffe,0xffff,fr8
cmmachs fr7,fr8,acc0,cc6,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result
set_fr_iimmed 0x8001,0x8001,fr8
cmmachs fr7,fr8,acc0,cc6,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr8
cmmachs fr7,fr8,acc0,cc6,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_accg_immed 0x7f,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0x7f,accg1
set_acc_immed 0xffffffff,acc1
set_fr_iimmed 1,1,fr7
set_fr_iimmed 1,1,fr8
cmmachs fr7,fr8,acc0,cc6,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0x7f,accg1
test_acc_immed 0xffffffff,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc6,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0x7f,accg1
test_acc_immed 0xffffffff,acc1
 
set_accg_immed 0x80,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed 0x80,accg1
set_acc_immed 0,acc1
set_fr_iimmed 0xffff,0,fr7
set_fr_iimmed 1,0xffff,fr8
cmmachs fr7,fr8,acc0,cc6,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x80,accg0 ; saturation
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x0000,0x8000,fr7 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc6,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x80,accg0 ; saturation
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
;
; Positive operands
set_spr_immed 0x0,msr0
set_accg_immed 0x0,accg0
set_acc_immed 0x0,acc0
set_accg_immed 0x0,accg1
set_acc_immed 0x0,acc1
set_fr_iimmed 2,3,fr7 ; multiply small numbers
set_fr_iimmed 3,2,fr8
cmmachs fr7,fr8,acc0,cc3,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0,1,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
cmmachs fr7,fr8,acc0,cc3,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 2,1,fr7 ; multiply by 1
set_fr_iimmed 1,2,fr8
cmmachs fr7,fr8,acc0,cc3,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr8
cmmachs fr7,fr8,acc0,cc3,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
set_fr_iimmed 2,0x4000,fr8
cmmachs fr7,fr8,acc0,cc3,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc3,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
; Mixed operands
set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers
set_fr_iimmed 0xfffd,2,fr8
cmmachs fr7,fr8,acc0,cc3,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1
set_fr_iimmed 1,0xfffe,fr8
cmmachs fr7,fr8,acc0,cc3,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0
set_fr_iimmed 0,0xfffe,fr8
cmmachs fr7,fr8,acc0,cc3,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result
set_fr_iimmed 0xfffe,0x2001,fr8
cmmachs fr7,fr8,acc0,cc3,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result
set_fr_iimmed 0xfffe,0x4000,fr8
cmmachs fr7,fr8,acc0,cc7,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result
set_fr_iimmed 0x8000,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc7,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
; Negative operands
set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers
set_fr_iimmed 0xfffd,0xfffe,fr8
cmmachs fr7,fr8,acc0,cc7,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1
set_fr_iimmed 0xfffe,0xffff,fr8
cmmachs fr7,fr8,acc0,cc7,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result
set_fr_iimmed 0x8001,0x8001,fr8
cmmachs fr7,fr8,acc0,cc7,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr8
cmmachs fr7,fr8,acc0,cc7,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_accg_immed 0x7f,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0x7f,accg1
set_acc_immed 0xffffffff,acc1
set_fr_iimmed 1,1,fr7
set_fr_iimmed 1,1,fr8
cmmachs fr7,fr8,acc0,cc7,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0x7f,accg1
test_acc_immed 0xffffffff,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc7,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0x7f,accg1
test_acc_immed 0xffffffff,acc1
 
set_accg_immed 0x80,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed 0x80,accg1
set_acc_immed 0,acc1
set_fr_iimmed 0xffff,0,fr7
set_fr_iimmed 1,0xffff,fr8
cmmachs fr7,fr8,acc0,cc7,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x80,accg0 ; saturation
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x0000,0x8000,fr7 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachs fr7,fr8,acc0,cc7,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x80,accg0 ; saturation
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
 
pass
/cmmachu.cgs
0,0 → 1,858
# frv testcase for cmmachu $GRi,$GRj,$GRk,$CCi,$cond
# mach: all
 
.include "../testutils.inc"
 
start
 
.global cmmachu
cmmachu:
set_spr_immed 0x1b1b,cccr
 
set_spr_immed 0,msr0
set_accg_immed 0,accg0
set_acc_immed 0,acc0
set_accg_immed 0,accg1
set_acc_immed 0,acc1
set_fr_iimmed 3,2,fr7 ; multiply small numbers
set_fr_iimmed 2,3,fr8
cmmachu fr7,fr8,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 2,1,fr8
cmmachu fr7,fr8,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 8,acc0
test_accg_immed 0,accg1
test_acc_immed 8,acc1
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
cmmachu fr7,fr8,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 8,acc0
test_accg_immed 0,accg1
test_acc_immed 8,acc1
 
set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr8
cmmachu fr7,fr8,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8006,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x8006,acc1
 
set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
set_fr_iimmed 2,0x4000,fr8
cmmachu fr7,fr8,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0001,0x0006,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0001,0x0006,acc1
 
set_fr_iimmed 0x8000,2,fr7 ; 17 bit result
set_fr_iimmed 2,0x8000,fr8
cmmachu fr7,fr8,acc0,cc4,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0x00020006,acc0
test_accg_immed 0,accg1
test_acc_immed 0x00020006,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachu fr7,fr8,acc0,cc4,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0x40010007,acc0
test_accg_immed 0,accg1
test_acc_immed 0x40010007,acc1
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr8
cmmachu fr7,fr8,acc0,cc4,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x8001,0x0007,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x8001,0x0007,acc1
 
set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmmachu fr7,fr8,acc0,cc4,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 1,accg0
test_acc_limmed 0x7fff,0x0008,acc0
test_accg_immed 1,accg1
test_acc_limmed 0x7fff,0x0008,acc1
 
set_accg_immed 0xff,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xffffffff,acc1
set_fr_iimmed 1,1,fr7
set_fr_iimmed 1,1,fr8
cmmachu fr7,fr8,acc0,cc4,1
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xffff,acc1
 
set_fr_iimmed 0xffff,0x0000,fr7
set_fr_iimmed 0xffff,0xffff,fr8
cmmachu fr7,fr8,acc0,cc4,1
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xffff,acc1
 
set_spr_immed 0,msr0
set_accg_immed 0,accg0
set_acc_immed 0,acc0
set_accg_immed 0,accg1
set_acc_immed 0,acc1
set_fr_iimmed 3,2,fr7 ; multiply small numbers
set_fr_iimmed 2,3,fr8
cmmachu fr7,fr8,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 2,1,fr8
cmmachu fr7,fr8,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 8,acc0
test_accg_immed 0,accg1
test_acc_immed 8,acc1
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
cmmachu fr7,fr8,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 8,acc0
test_accg_immed 0,accg1
test_acc_immed 8,acc1
 
set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr8
cmmachu fr7,fr8,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8006,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x8006,acc1
 
set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
set_fr_iimmed 2,0x4000,fr8
cmmachu fr7,fr8,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0001,0x0006,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0001,0x0006,acc1
 
set_fr_iimmed 0x8000,2,fr7 ; 17 bit result
set_fr_iimmed 2,0x8000,fr8
cmmachu fr7,fr8,acc0,cc5,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0x00020006,acc0
test_accg_immed 0,accg1
test_acc_immed 0x00020006,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachu fr7,fr8,acc0,cc5,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0x40010007,acc0
test_accg_immed 0,accg1
test_acc_immed 0x40010007,acc1
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr8
cmmachu fr7,fr8,acc0,cc5,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x8001,0x0007,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x8001,0x0007,acc1
 
set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmmachu fr7,fr8,acc0,cc5,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 1,accg0
test_acc_limmed 0x7fff,0x0008,acc0
test_accg_immed 1,accg1
test_acc_limmed 0x7fff,0x0008,acc1
 
set_accg_immed 0xff,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xffffffff,acc1
set_fr_iimmed 1,1,fr7
set_fr_iimmed 1,1,fr8
cmmachu fr7,fr8,acc0,cc5,0
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xffff,acc1
 
set_fr_iimmed 0xffff,0x0000,fr7
set_fr_iimmed 0xffff,0xffff,fr8
cmmachu fr7,fr8,acc0,cc5,0
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xffff,acc1
 
set_spr_immed 0,msr0
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_accg_immed 0x00000022,accg1
set_acc_immed 0x22222222,acc1
set_fr_iimmed 3,2,fr7 ; multiply small numbers
set_fr_iimmed 2,3,fr8
cmmachu fr7,fr8,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 2,1,fr8
cmmachu fr7,fr8,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
cmmachu fr7,fr8,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr8
cmmachu fr7,fr8,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
set_fr_iimmed 2,0x4000,fr8
cmmachu fr7,fr8,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x8000,2,fr7 ; 17 bit result
set_fr_iimmed 2,0x8000,fr8
cmmachu fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachu fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr8
cmmachu fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmmachu fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_accg_immed 0xff,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xffffffff,acc1
set_fr_iimmed 1,1,fr7
set_fr_iimmed 1,1,fr8
cmmachu fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0xff,accg1
test_acc_immed 0xffffffff,acc1
 
set_fr_iimmed 0xffff,0x0000,fr7
set_fr_iimmed 0xffff,0xffff,fr8
cmmachu fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0xff,accg1
test_acc_immed 0xffffffff,acc1
 
set_spr_immed 0,msr0
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_accg_immed 0x00000022,accg1
set_acc_immed 0x22222222,acc1
set_fr_iimmed 3,2,fr7 ; multiply small numbers
set_fr_iimmed 2,3,fr8
cmmachu fr7,fr8,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 2,1,fr8
cmmachu fr7,fr8,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
cmmachu fr7,fr8,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr8
cmmachu fr7,fr8,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
set_fr_iimmed 2,0x4000,fr8
cmmachu fr7,fr8,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x8000,2,fr7 ; 17 bit result
set_fr_iimmed 2,0x8000,fr8
cmmachu fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachu fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr8
cmmachu fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmmachu fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_accg_immed 0xff,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xffffffff,acc1
set_fr_iimmed 1,1,fr7
set_fr_iimmed 1,1,fr8
cmmachu fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0xff,accg1
test_acc_immed 0xffffffff,acc1
 
set_fr_iimmed 0xffff,0x0000,fr7
set_fr_iimmed 0xffff,0xffff,fr8
cmmachu fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0xff,accg1
test_acc_immed 0xffffffff,acc1
 
set_spr_immed 0,msr0
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_accg_immed 0x00000022,accg1
set_acc_immed 0x22222222,acc1
set_fr_iimmed 3,2,fr7 ; multiply small numbers
set_fr_iimmed 2,3,fr8
cmmachu fr7,fr8,acc0,cc2,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 2,1,fr8
cmmachu fr7,fr8,acc0,cc2,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
cmmachu fr7,fr8,acc0,cc2,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr8
cmmachu fr7,fr8,acc0,cc2,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
set_fr_iimmed 2,0x4000,fr8
cmmachu fr7,fr8,acc0,cc2,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x8000,2,fr7 ; 17 bit result
set_fr_iimmed 2,0x8000,fr8
cmmachu fr7,fr8,acc0,cc6,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachu fr7,fr8,acc0,cc6,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr8
cmmachu fr7,fr8,acc0,cc6,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmmachu fr7,fr8,acc0,cc6,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_accg_immed 0xff,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xffffffff,acc1
set_fr_iimmed 1,1,fr7
set_fr_iimmed 1,1,fr8
cmmachu fr7,fr8,acc0,cc6,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0xff,accg1
test_acc_immed 0xffffffff,acc1
 
set_fr_iimmed 0xffff,0x0000,fr7
set_fr_iimmed 0xffff,0xffff,fr8
cmmachu fr7,fr8,acc0,cc6,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0xff,accg1
test_acc_immed 0xffffffff,acc1
;
set_spr_immed 0,msr0
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_accg_immed 0x00000022,accg1
set_acc_immed 0x22222222,acc1
set_fr_iimmed 3,2,fr7 ; multiply small numbers
set_fr_iimmed 2,3,fr8
cmmachu fr7,fr8,acc0,cc3,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 2,1,fr8
cmmachu fr7,fr8,acc0,cc3,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
cmmachu fr7,fr8,acc0,cc3,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr8
cmmachu fr7,fr8,acc0,cc3,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
set_fr_iimmed 2,0x4000,fr8
cmmachu fr7,fr8,acc0,cc3,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x8000,2,fr7 ; 17 bit result
set_fr_iimmed 2,0x8000,fr8
cmmachu fr7,fr8,acc0,cc7,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmmachu fr7,fr8,acc0,cc7,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr8
cmmachu fr7,fr8,acc0,cc7,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmmachu fr7,fr8,acc0,cc7,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
 
set_accg_immed 0xff,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xffffffff,acc1
set_fr_iimmed 1,1,fr7
set_fr_iimmed 1,1,fr8
cmmachu fr7,fr8,acc0,cc7,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0xff,accg1
test_acc_immed 0xffffffff,acc1
 
set_fr_iimmed 0xffff,0x0000,fr7
set_fr_iimmed 0xffff,0xffff,fr8
cmmachu fr7,fr8,acc0,cc7,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0xff,accg1
test_acc_immed 0xffffffff,acc1
 
pass
/mabshs.cgs
0,0 → 1,64
# frv testcase for mabshs $FRj,$FRk
# mach: all
 
.include "../testutils.inc"
 
start
 
.global mabshs
mabshs:
set_fr_iimmed 0x0000,0x0000,fr10
mabshs fr10,fr11
test_fr_limmed 0x0000,0x0000,fr11
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0001,0xffff,fr10
mabshs fr10,fr11
test_fr_limmed 0x0001,0x0001,fr11
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7fff,0x8001,fr10
mabshs fr10,fr11
test_fr_limmed 0x7fff,0x7fff,fr11
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x7fff,0x8000,fr10
mabshs fr10,fr11
test_fr_limmed 0x7fff,0x7fff,fr11
test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8000,0x7fff,fr10
mabshs fr10,fr11
test_fr_limmed 0x7fff,0x7fff,fr11
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x7fff,0x8000,fr10
set_fr_iimmed 0x8000,0x7fff,fr11
mabshs.p fr10,fr12
mabshs fr11,fr13
test_fr_limmed 0x7fff,0x7fff,fr12
test_fr_limmed 0x7fff,0x7fff,fr13
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
pass
/udivi.cgs
0,0 → 1,49
# frv testcase for udivi $GRi,$s12,$GRk
# mach: all
 
.include "../testutils.inc"
 
start
 
.global udivi
udivi:
; simple division 12 / 3
set_gr_immed 0x0000000c,gr3
udivi gr3,3,gr3
test_gr_immed 0x00000004,gr3
 
; random example
set_gr_limmed 0xfedc,0xba98,gr3
udivi gr3,0x7ff,gr3
test_gr_limmed 0x001f,0xdf93,gr3
 
; random example
set_gr_limmed 0xffff,0xffff,gr3
udivi gr3,-2048,gr3
test_gr_immed 1,gr3
 
; set up exception handler
set_psr_et 1
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x170,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
set_spr_immed 128,lcr
set_gr_immed 0,gr15
 
; divide by zero
set_spr_addr ok1,lr
set_gr_addr e1,gr17
e1: udivi gr1,0,gr2 ; divide by zero
test_gr_immed 1,gr15
 
pass
 
ok1: ; exception handler for divide by zero
test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set
test_spr_gr epcr0,gr17 ; return address set
test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set
inc_gr_immed 1,gr15
rett 0
fail
/allinsn.exp
0,0 → 1,19
# FRV simulator testsuite.
 
if [istarget frv*-*] {
# load support procs (none yet)
# load_lib cgen.exp
# all machines
set all_machs "fr550"
set cpu_option -mcpu
 
# The .cgs suffix is for "cgen .s".
foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] {
# If we're only testing specific files and this isn't one of them,
# skip it.
if ![runtest_file_p $runtests $src] {
continue
}
run_sim_test $src $all_machs
}
}
/cmcpxru.cgs
0,0 → 1,528
# frv testcase for cmcpxru $GRi,$GRj,$GRk,$CCi,$cond
# mach: all
 
.include "../testutils.inc"
 
start
 
.global cmcpxru
cmcpxru:
set_spr_immed 0x1b1b,cccr
 
set_fr_iimmed 4,2,fr7 ; multiply small numbers
set_fr_iimmed 5,3,fr8
cmcpxru fr7,fr8,acc0,cc0,1
test_accg_immed 0,accg0
test_acc_immed 14,acc0
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 3,1,fr8
cmcpxru fr7,fr8,acc0,cc0,1
test_accg_immed 0,accg0
test_acc_immed 1,acc0
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
cmcpxru fr7,fr8,acc0,cc0,1
test_accg_immed 0,accg0
test_acc_immed 0,acc0
 
set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
set_fr_iimmed 2,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc0,1
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x7ffd,acc0
 
set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
set_fr_iimmed 4,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc0,1
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0xffff,acc0
 
set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
set_fr_iimmed 4,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc0,1
test_accg_immed 0,accg0
test_acc_immed 0x0001ffff,acc0
 
set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmcpxru fr7,fr8,acc0,cc4,1
test_accg_immed 0,accg0
test_acc_immed 0x3fff0001,acc0
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x0000,fr8
cmcpxru fr7,fr8,acc0,cc4,1
test_accg_immed 0,accg0
test_acc_limmed 0x4000,0x0000,acc0
 
set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxru fr7,fr8,acc0,cc4,1
test_accg_immed 0,accg0
test_acc_limmed 0xfffe,0x0001,acc0
 
set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
set_fr_iimmed 0xffff,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc4,1
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
 
set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxru fr7,fr8,acc0,cc4,1
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
 
set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxru fr7,fr8,acc0,cc4,1
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
 
set_fr_iimmed 4,2,fr7 ; multiply small numbers
set_fr_iimmed 5,3,fr8
cmcpxru fr7,fr8,acc0,cc1,0
test_accg_immed 0,accg0
test_acc_immed 14,acc0
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 3,1,fr8
cmcpxru fr7,fr8,acc0,cc1,0
test_accg_immed 0,accg0
test_acc_immed 1,acc0
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
cmcpxru fr7,fr8,acc0,cc1,0
test_accg_immed 0,accg0
test_acc_immed 0,acc0
 
set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
set_fr_iimmed 2,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc1,0
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x7ffd,acc0
 
set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
set_fr_iimmed 4,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc1,0
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0xffff,acc0
 
set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
set_fr_iimmed 4,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc1,0
test_accg_immed 0,accg0
test_acc_immed 0x0001ffff,acc0
 
set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmcpxru fr7,fr8,acc0,cc5,0
test_accg_immed 0,accg0
test_acc_immed 0x3fff0001,acc0
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x0000,fr8
cmcpxru fr7,fr8,acc0,cc5,0
test_accg_immed 0,accg0
test_acc_limmed 0x4000,0x0000,acc0
 
set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxru fr7,fr8,acc0,cc5,0
test_accg_immed 0,accg0
test_acc_limmed 0xfffe,0x0001,acc0
 
set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
set_fr_iimmed 0xffff,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc5,0
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
 
set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxru fr7,fr8,acc0,cc5,0
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
 
set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxru fr7,fr8,acc0,cc5,0
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
 
set_spr_immed 0,msr0
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_fr_iimmed 4,2,fr7 ; multiply small numbers
set_fr_iimmed 5,3,fr8
cmcpxru fr7,fr8,acc0,cc0,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 3,1,fr8
cmcpxru fr7,fr8,acc0,cc0,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
cmcpxru fr7,fr8,acc0,cc0,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
set_fr_iimmed 2,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc0,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
set_fr_iimmed 4,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc0,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
set_fr_iimmed 4,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc0,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmcpxru fr7,fr8,acc0,cc4,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x0000,fr8
cmcpxru fr7,fr8,acc0,cc4,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxru fr7,fr8,acc0,cc4,0
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
set_fr_iimmed 0xffff,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxru fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxru fr7,fr8,acc0,cc4,0
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_spr_immed 0,msr0
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_fr_iimmed 4,2,fr7 ; multiply small numbers
set_fr_iimmed 5,3,fr8
cmcpxru fr7,fr8,acc0,cc1,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 3,1,fr8
cmcpxru fr7,fr8,acc0,cc1,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
cmcpxru fr7,fr8,acc0,cc1,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
set_fr_iimmed 2,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc1,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
set_fr_iimmed 4,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc1,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
set_fr_iimmed 4,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc1,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmcpxru fr7,fr8,acc0,cc5,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x0000,fr8
cmcpxru fr7,fr8,acc0,cc5,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxru fr7,fr8,acc0,cc5,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
set_fr_iimmed 0xffff,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxru fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxru fr7,fr8,acc0,cc5,1
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_spr_immed 0,msr0
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_fr_iimmed 4,2,fr7 ; multiply small numbers
set_fr_iimmed 5,3,fr8
cmcpxru fr7,fr8,acc0,cc2,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 3,1,fr8
cmcpxru fr7,fr8,acc0,cc2,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
cmcpxru fr7,fr8,acc0,cc2,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
set_fr_iimmed 2,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc2,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
set_fr_iimmed 4,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc2,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
set_fr_iimmed 4,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc2,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmcpxru fr7,fr8,acc0,cc6,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x0000,fr8
cmcpxru fr7,fr8,acc0,cc6,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxru fr7,fr8,acc0,cc6,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
set_fr_iimmed 0xffff,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc6,1
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxru fr7,fr8,acc0,cc6,1
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxru fr7,fr8,acc0,cc6,1
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
;
set_spr_immed 0,msr0
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_fr_iimmed 4,2,fr7 ; multiply small numbers
set_fr_iimmed 5,3,fr8
cmcpxru fr7,fr8,acc0,cc3,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 3,1,fr8
cmcpxru fr7,fr8,acc0,cc3,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
cmcpxru fr7,fr8,acc0,cc3,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result
set_fr_iimmed 2,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc3,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x4000,1,fr7 ; 16 bit result
set_fr_iimmed 4,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc3,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x8000,1,fr7 ; 17 bit result
set_fr_iimmed 4,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc3,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
cmcpxru fr7,fr8,acc0,cc7,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x0000,fr8
cmcpxru fr7,fr8,acc0,cc7,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxru fr7,fr8,acc0,cc7,1
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x0000,0x0001,fr7 ; saturation
set_fr_iimmed 0xffff,0x0001,fr8
cmcpxru fr7,fr8,acc0,cc7,1
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0x0000,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxru fr7,fr8,acc0,cc7,1
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation
set_fr_iimmed 0xffff,0xffff,fr8
cmcpxru fr7,fr8,acc0,cc7,1
test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
 
pass
/mqxmachs.cgs
0,0 → 1,211
# frv testcase for mqxmachs $GRi,$GRj,$ACCk
# mach: all
 
.include "../testutils.inc"
 
start
 
.global mqxmachs
mqxmachs:
; Positive operands
set_fr_iimmed 2,3,fr8 ; multiply small numbers
set_fr_iimmed 3,2,fr10
set_fr_iimmed 0,1,fr9 ; multiply by 0
set_fr_iimmed 2,0,fr11
mqxmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
test_accg_immed 0,accg2
test_acc_immed 6,acc2
test_accg_immed 0,accg3
test_acc_immed 6,acc3
 
set_fr_iimmed 2,1,fr8 ; multiply by 1
set_fr_iimmed 1,2,fr10
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr11
mqxmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg2
test_acc_immed 8,acc2
test_accg_immed 0,accg3
test_acc_immed 8,acc3
test_accg_immed 0,accg0
test_acc_limmed 0,0x7ffe,acc0
test_accg_immed 0,accg1
test_acc_limmed 0,0x7ffe,acc1
 
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
set_fr_iimmed 2,0x4000,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr11
mqxmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg2
test_acc_limmed 0x0000,0x8008,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x0000,0x8008,acc3
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0x7fff,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0x7fff,acc1
 
; Mixed operands
set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 0xfffd,2,fr10
set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
set_fr_iimmed 1,0xfffe,fr11
mqxmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg2
test_acc_limmed 0x0000,0x8002,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x0000,0x8002,acc3
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0x7ffd,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0x7ffd,acc1
 
set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
set_fr_iimmed 0,0xfffe,fr10
set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
set_fr_iimmed 0xfffe,0x2001,fr11
mqxmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg2
test_acc_limmed 0x0000,0x8002,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x0000,0x8002,acc3
test_accg_immed 0,accg0
test_acc_limmed 0x3fff,0x3ffb,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x3fff,0x3ffb,acc1
 
set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
set_fr_iimmed 0xfffe,0x4000,fr10
set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
set_fr_iimmed 0x8000,0x7fff,fr11
mqxmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg2
test_acc_limmed 0x0000,0x0002,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x0000,0x0002,acc3
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xbffb,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xbffb,acc1
 
; Negative operands
set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 0xfffd,0xfffe,fr10
set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
set_fr_iimmed 0xfffe,0xffff,fr11
mqxmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg2
test_acc_limmed 0x0000,0x0008,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x0000,0x0008,acc3
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xbffd,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xbffd,acc1
 
set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr11
mqxmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg2
test_acc_immed 0x3fff0009,acc2
test_accg_immed 0,accg3
test_acc_immed 0x3fff0009,acc3
test_accg_immed 0,accg0
test_acc_immed 0x3fffbffd,acc0
test_accg_immed 0,accg1
test_acc_immed 0x3fffbffd,acc1
 
set_accg_immed 0x7f,accg2 ; saturation
set_acc_immed 0xffffffff,acc2
set_accg_immed 0x7f,accg3
set_acc_immed 0xffffffff,acc3
set_accg_immed 0x7f,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0x7f,accg1
set_acc_immed 0xffffffff,acc1
set_fr_iimmed 1,1,fr8
set_fr_iimmed 1,1,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
mqxmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x7f,accg2
test_acc_limmed 0xffff,0xffff,acc2
test_accg_immed 0x7f,accg3
test_acc_limmed 0xffff,0xffff,acc3
test_accg_immed 0x7f,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xffff,0xffff,acc1
 
set_accg_immed 0x80,accg2 ; saturation
set_acc_immed 0,acc2
set_accg_immed 0x80,accg3
set_acc_immed 0,acc3
set_accg_immed 0x80,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed 0x80,accg1
set_acc_immed 0,acc1
set_fr_iimmed 0xffff,0,fr8
set_fr_iimmed 1,0xffff,fr10
set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
mqxmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x80,accg2
test_acc_immed 0,acc2
test_accg_immed 0x80,accg3
test_acc_immed 0,acc3
test_accg_immed 0x80,accg0
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
 
pass
 
 
/dcpl.cgs
0,0 → 1,65
# FRV testcase for dcpl GRi,GRj,lock
# mach: all
 
.include "../testutils.inc"
 
start
 
.global dcpl
dcpl:
or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode
 
; preload and lock all the lines in set 0 of the data cache
set_gr_immed 0x70000,gr10
dcpl gr10,gr0,1
set_mem_immed 0x11111111,gr10
test_mem_immed 0x11111111,gr10
 
inc_gr_immed 0x2000,gr10
set_gr_immed 1,gr11
dcpl gr10,gr11,1
set_mem_immed 0x22222222,gr10
test_mem_immed 0x22222222,gr10
 
inc_gr_immed 0x2000,gr10
set_gr_immed 63,gr11
dcpl gr10,gr11,1
set_mem_immed 0x33333333,gr10
test_mem_immed 0x33333333,gr10
 
inc_gr_immed 0x2000,gr10
set_gr_immed 64,gr11
dcpl gr10,gr11,1
set_mem_immed 0x44444444,gr10
test_mem_immed 0x44444444,gr10
 
; Now write to another address which should be in the same set
; the write should go through to memory, since all the lines in the
; set are locked
inc_gr_immed 0x2000,gr10
set_mem_immed 0xdeadbeef,gr10
test_mem_immed 0xdeadbeef,gr10
 
; Invalidate the data cache. Only the last value stored should have made
; it through to memory
set_gr_immed 0x70000,gr10
invalidate_data_cache gr10
test_mem_immed 0,gr10
 
inc_gr_immed 0x2000,gr10
invalidate_data_cache gr10
test_mem_immed 0,gr10
 
inc_gr_immed 0x2000,gr10
invalidate_data_cache gr10
test_mem_immed 0,gr10
 
inc_gr_immed 0x2000,gr10
invalidate_data_cache gr10
test_mem_immed 0,gr10
 
inc_gr_immed 0x2000,gr10
invalidate_data_cache gr10
test_mem_immed 0xdeadbeef,gr10
 
pass
/maddhss.cgs
0,0 → 1,97
# frv testcase for maddhss $FRi,$FRj,$FRj
# mach: all
 
.include "../testutils.inc"
 
start
 
.global maddhss
maddhss:
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
maddhss fr10,fr11,fr12
test_fr_limmed 0x0000,0x0000,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0x0000,fr10
set_fr_iimmed 0x0000,0xbeef,fr11
maddhss fr10,fr11,fr12
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
maddhss fr10,fr11,fr12
test_fr_limmed 0xbeef,0xdead,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
maddhss fr10,fr11,fr12
test_fr_limmed 0x2345,0x6789,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0xffff,0xffff,fr11
maddhss fr10,fr11,fr12
test_fr_limmed 0x1233,0x5677,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
maddhss fr10,fr11,fr12
test_fr_limmed 0x7fff,0x7fff,fr12
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0xffff,0xfffe,fr11
maddhss fr10,fr11,fr12
test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
test_fr_limmed 0x8000,0x8000,fr12
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
maddhss fr10,fr11,fr12
test_fr_limmed 0x8000,0x8000,fr12
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x7fff,0x7fff,fr11
maddhss.p fr10,fr10,fr12
maddhss fr11,fr11,fr13
test_fr_limmed 0x0002,0x0002,fr12
test_fr_limmed 0x7fff,0x7fff,fr13
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
pass
/maddhus.cgs
0,0 → 1,86
# frv testcase for maddhus $FRi,$FRj,$FRj
# mach: all
 
.include "../testutils.inc"
 
start
 
.global maddhus
maddhus:
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
maddhus fr10,fr11,fr12
test_fr_limmed 0x0000,0x0000,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0x0000,fr10
set_fr_iimmed 0x0000,0xbeef,fr11
maddhus fr10,fr11,fr12
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
maddhus fr10,fr11,fr12
test_fr_limmed 0xbeef,0xdead,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
maddhus fr10,fr11,fr12
test_fr_limmed 0x2345,0x6789,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
maddhus fr10,fr11,fr12
test_fr_limmed 0x8000,0x7fff,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xfffe,0xfffe,fr10
set_fr_iimmed 0x0001,0x0002,fr11
maddhus fr10,fr11,fr12
test_fr_limmed 0xffff,0xffff,fr12
test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0002,0x0001,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
maddhus fr10,fr11,fr12
test_fr_limmed 0xffff,0xffff,fr12
test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x8000,0x8000,fr11
maddhus.p fr10,fr10,fr12
maddhus fr11,fr11,fr13
test_fr_limmed 0x0002,0x0002,fr12
test_fr_limmed 0xffff,0xffff,fr13
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
pass
/cmaddhss.cgs
0,0 → 1,547
# frv testcase for cmaddhss $FRi,$FRj,$FRj,$CCi,$cond
# mach: all
 
.include "../testutils.inc"
 
start
 
.global maddhss
maddhss:
set_spr_immed 0x1b1b,cccr
 
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmaddhss fr10,fr11,fr12,cc0,1
test_fr_limmed 0x0000,0x0000,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0x0000,fr10
set_fr_iimmed 0x0000,0xbeef,fr11
cmaddhss fr10,fr11,fr12,cc0,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
cmaddhss fr10,fr11,fr12,cc0,1
test_fr_limmed 0xbeef,0xdead,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmaddhss fr10,fr11,fr12,cc0,1
test_fr_limmed 0x2345,0x6789,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0xffff,0xffff,fr11
cmaddhss fr10,fr11,fr12,cc0,1
test_fr_limmed 0x1233,0x5677,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmaddhss fr10,fr11,fr12,cc4,1
test_fr_limmed 0x7fff,0x7fff,fr12
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0xffff,0xfffe,fr11
cmaddhss fr10,fr11,fr12,cc4,1
test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
test_fr_limmed 0x8000,0x8000,fr12
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
cmaddhss fr10,fr11,fr12,cc4,1
test_fr_limmed 0x8000,0x8000,fr12
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x7fff,0x7fff,fr11
cmaddhss.p fr10,fr10,fr12,cc4,1
cmaddhss fr11,fr11,fr13,cc4,1
test_fr_limmed 0x0002,0x0002,fr12
test_fr_limmed 0x7fff,0x7fff,fr13
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmaddhss fr10,fr11,fr12,cc1,0
test_fr_limmed 0x0000,0x0000,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0x0000,fr10
set_fr_iimmed 0x0000,0xbeef,fr11
cmaddhss fr10,fr11,fr12,cc1,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
cmaddhss fr10,fr11,fr12,cc1,0
test_fr_limmed 0xbeef,0xdead,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmaddhss fr10,fr11,fr12,cc1,0
test_fr_limmed 0x2345,0x6789,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0xffff,0xffff,fr11
cmaddhss fr10,fr11,fr12,cc1,0
test_fr_limmed 0x1233,0x5677,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmaddhss fr10,fr11,fr12,cc5,0
test_fr_limmed 0x7fff,0x7fff,fr12
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0xffff,0xfffe,fr11
cmaddhss fr10,fr11,fr12,cc5,0
test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
test_fr_limmed 0x8000,0x8000,fr12
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
cmaddhss fr10,fr11,fr12,cc5,0
test_fr_limmed 0x8000,0x8000,fr12
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x7fff,0x7fff,fr11
cmaddhss.p fr10,fr10,fr12,cc5,0
cmaddhss fr11,fr11,fr13,cc5,0
test_fr_limmed 0x0002,0x0002,fr12
test_fr_limmed 0x7fff,0x7fff,fr13
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_fr_iimmed 0xdead,0xbeef,fr12
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmaddhss fr10,fr11,fr12,cc0,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0x0000,fr10
set_fr_iimmed 0x0000,0xbeef,fr11
cmaddhss fr10,fr11,fr12,cc0,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
cmaddhss fr10,fr11,fr12,cc0,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmaddhss fr10,fr11,fr12,cc0,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0xffff,0xffff,fr11
cmaddhss fr10,fr11,fr12,cc0,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmaddhss fr10,fr11,fr12,cc4,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0xffff,0xfffe,fr11
cmaddhss fr10,fr11,fr12,cc4,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
cmaddhss fr10,fr11,fr12,cc4,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr13
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x7fff,0x7fff,fr11
cmaddhss.p fr10,fr10,fr12,cc4,0
cmaddhss fr11,fr11,fr13,cc4,0
test_fr_limmed 0xdead,0xbeef,fr12
test_fr_limmed 0xbeef,0xdead,fr13
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0xbeef,fr12
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmaddhss fr10,fr11,fr12,cc1,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0x0000,fr10
set_fr_iimmed 0x0000,0xbeef,fr11
cmaddhss fr10,fr11,fr12,cc1,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
cmaddhss fr10,fr11,fr12,cc1,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmaddhss fr10,fr11,fr12,cc1,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0xffff,0xffff,fr11
cmaddhss fr10,fr11,fr12,cc1,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmaddhss fr10,fr11,fr12,cc5,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0xffff,0xfffe,fr11
cmaddhss fr10,fr11,fr12,cc5,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
cmaddhss fr10,fr11,fr12,cc5,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr13
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x7fff,0x7fff,fr11
cmaddhss.p fr10,fr10,fr12,cc5,1
cmaddhss fr11,fr11,fr13,cc5,1
test_fr_limmed 0xdead,0xbeef,fr12
test_fr_limmed 0xbeef,0xdead,fr13
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0xbeef,fr12
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmaddhss fr10,fr11,fr12,cc2,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0x0000,fr10
set_fr_iimmed 0x0000,0xbeef,fr11
cmaddhss fr10,fr11,fr12,cc2,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
cmaddhss fr10,fr11,fr12,cc2,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmaddhss fr10,fr11,fr12,cc2,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0xffff,0xffff,fr11
cmaddhss fr10,fr11,fr12,cc2,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmaddhss fr10,fr11,fr12,cc6,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0xffff,0xfffe,fr11
cmaddhss fr10,fr11,fr12,cc6,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
cmaddhss fr10,fr11,fr12,cc6,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr13
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x7fff,0x7fff,fr11
cmaddhss.p fr10,fr10,fr12,cc6,1
cmaddhss fr11,fr11,fr13,cc6,0
test_fr_limmed 0xdead,0xbeef,fr12
test_fr_limmed 0xbeef,0xdead,fr13
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
;
set_fr_iimmed 0xdead,0xbeef,fr12
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmaddhss fr10,fr11,fr12,cc3,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0x0000,fr10
set_fr_iimmed 0x0000,0xbeef,fr11
cmaddhss fr10,fr11,fr12,cc3,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
cmaddhss fr10,fr11,fr12,cc3,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmaddhss fr10,fr11,fr12,cc3,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0xffff,0xffff,fr11
cmaddhss fr10,fr11,fr12,cc3,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmaddhss fr10,fr11,fr12,cc7,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0xffff,0xfffe,fr11
cmaddhss fr10,fr11,fr12,cc7,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
cmaddhss fr10,fr11,fr12,cc7,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr13
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x7fff,0x7fff,fr11
cmaddhss.p fr10,fr10,fr12,cc7,1
cmaddhss fr11,fr11,fr13,cc7,0
test_fr_limmed 0xdead,0xbeef,fr12
test_fr_limmed 0xbeef,0xdead,fr13
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
pass
/cmaddhus.cgs
0,0 → 1,481
# frv testcase for cmaddhus $FRi,$FRj,$FRj,$CCi,$cond
# mach: all
 
.include "../testutils.inc"
 
start
 
.global cmaddhus
cmaddhus:
set_spr_immed 0x1b1b,cccr
 
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmaddhus fr10,fr11,fr12,cc0,1
test_fr_limmed 0x0000,0x0000,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0x0000,fr10
set_fr_iimmed 0x0000,0xbeef,fr11
cmaddhus fr10,fr11,fr12,cc0,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
cmaddhus fr10,fr11,fr12,cc0,1
test_fr_limmed 0xbeef,0xdead,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmaddhus fr10,fr11,fr12,cc0,1
test_fr_limmed 0x2345,0x6789,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmaddhus fr10,fr11,fr12,cc4,1
test_fr_limmed 0x8000,0x7fff,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xfffe,0xfffe,fr10
set_fr_iimmed 0x0001,0x0002,fr11
cmaddhus fr10,fr11,fr12,cc4,1
test_fr_limmed 0xffff,0xffff,fr12
test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0002,0x0001,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
cmaddhus fr10,fr11,fr12,cc4,1
test_fr_limmed 0xffff,0xffff,fr12
test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x8000,0x8000,fr11
cmaddhus.p fr10,fr10,fr12,cc4,1
cmaddhus fr11,fr11,fr13,cc4,1
test_fr_limmed 0x0002,0x0002,fr12
test_fr_limmed 0xffff,0xffff,fr13
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmaddhus fr10,fr11,fr12,cc1,0
test_fr_limmed 0x0000,0x0000,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0x0000,fr10
set_fr_iimmed 0x0000,0xbeef,fr11
cmaddhus fr10,fr11,fr12,cc1,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
cmaddhus fr10,fr11,fr12,cc1,0
test_fr_limmed 0xbeef,0xdead,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmaddhus fr10,fr11,fr12,cc1,0
test_fr_limmed 0x2345,0x6789,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmaddhus fr10,fr11,fr12,cc5,0
test_fr_limmed 0x8000,0x7fff,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xfffe,0xfffe,fr10
set_fr_iimmed 0x0001,0x0002,fr11
cmaddhus fr10,fr11,fr12,cc5,0
test_fr_limmed 0xffff,0xffff,fr12
test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0002,0x0001,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
cmaddhus fr10,fr11,fr12,cc5,0
test_fr_limmed 0xffff,0xffff,fr12
test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x8000,0x8000,fr11
cmaddhus.p fr10,fr10,fr12,cc5,0
cmaddhus fr11,fr11,fr13,cc5,0
test_fr_limmed 0x0002,0x0002,fr12
test_fr_limmed 0xffff,0xffff,fr13
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf set
test_spr_bits 1,0,1,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
 
set_fr_iimmed 0xdead,0xbeef,fr12
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmaddhus fr10,fr11,fr12,cc0,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0x0000,fr10
set_fr_iimmed 0x0000,0xdead,fr11
cmaddhus fr10,fr11,fr12,cc0,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
cmaddhus fr10,fr11,fr12,cc0,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmaddhus fr10,fr11,fr12,cc0,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmaddhus fr10,fr11,fr12,cc4,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xfffe,0xfffe,fr10
set_fr_iimmed 0x0001,0x0002,fr11
cmaddhus fr10,fr11,fr12,cc4,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0002,0x0001,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
cmaddhus fr10,fr11,fr12,cc4,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr13
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x8000,0x8000,fr11
cmaddhus.p fr10,fr10,fr12,cc4,0
cmaddhus fr11,fr11,fr13,cc4,0
test_fr_limmed 0xdead,0xbeef,fr12
test_fr_limmed 0xbeef,0xdead,fr13
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0xbeef,fr12
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmaddhus fr10,fr11,fr12,cc1,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0x0000,fr10
set_fr_iimmed 0x0000,0xdead,fr11
cmaddhus fr10,fr11,fr12,cc1,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
cmaddhus fr10,fr11,fr12,cc1,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmaddhus fr10,fr11,fr12,cc1,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmaddhus fr10,fr11,fr12,cc5,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xfffe,0xfffe,fr10
set_fr_iimmed 0x0001,0x0002,fr11
cmaddhus fr10,fr11,fr12,cc5,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0002,0x0001,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
cmaddhus fr10,fr11,fr12,cc5,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr13
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x8000,0x8000,fr11
cmaddhus.p fr10,fr10,fr12,cc5,1
cmaddhus fr11,fr11,fr13,cc5,1
test_fr_limmed 0xdead,0xbeef,fr12
test_fr_limmed 0xbeef,0xdead,fr13
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0xbeef,fr12
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmaddhus fr10,fr11,fr12,cc2,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0x0000,fr10
set_fr_iimmed 0x0000,0xdead,fr11
cmaddhus fr10,fr11,fr12,cc2,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
cmaddhus fr10,fr11,fr12,cc2,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmaddhus fr10,fr11,fr12,cc2,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmaddhus fr10,fr11,fr12,cc6,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xfffe,0xfffe,fr10
set_fr_iimmed 0x0001,0x0002,fr11
cmaddhus fr10,fr11,fr12,cc6,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0002,0x0001,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
cmaddhus fr10,fr11,fr12,cc6,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr13
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x8000,0x8000,fr11
cmaddhus.p fr10,fr10,fr12,cc6,0
cmaddhus fr11,fr11,fr13,cc6,1
test_fr_limmed 0xdead,0xbeef,fr12
test_fr_limmed 0xbeef,0xdead,fr13
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xdead,0xbeef,fr12
set_spr_immed 0,msr0
set_fr_iimmed 0x0000,0x0000,fr10
set_fr_iimmed 0x0000,0x0000,fr11
cmaddhus fr10,fr11,fr12,cc3,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0x0000,fr10
set_fr_iimmed 0x0000,0xdead,fr11
cmaddhus fr10,fr11,fr12,cc3,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x0000,0xdead,fr10
set_fr_iimmed 0xbeef,0x0000,fr11
cmaddhus fr10,fr11,fr12,cc3,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x1234,0x5678,fr10
set_fr_iimmed 0x1111,0x1111,fr11
cmaddhus fr10,fr11,fr12,cc3,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0x7ffe,0x7ffe,fr10
set_fr_iimmed 0x0002,0x0001,fr11
cmaddhus fr10,fr11,fr12,cc7,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xfffe,0xfffe,fr10
set_fr_iimmed 0x0001,0x0002,fr11
cmaddhus fr10,fr11,fr12,cc7,0
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_spr_immed 0,msr0
set_fr_iimmed 0x0002,0x0001,fr10
set_fr_iimmed 0xfffe,0xfffe,fr11
cmaddhus fr10,fr11,fr12,cc7,1
test_fr_limmed 0xdead,0xbeef,fr12
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
set_fr_iimmed 0xbeef,0xdead,fr13
set_spr_immed 0,msr0
set_fr_iimmed 0x0001,0x0001,fr10
set_fr_iimmed 0x8000,0x8000,fr11
cmaddhus.p fr10,fr10,fr12,cc7,0
cmaddhus fr11,fr11,fr13,cc7,1
test_fr_limmed 0xdead,0xbeef,fr12
test_fr_limmed 0xbeef,0xdead,fr13
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
 
pass
/mqmachs.cgs
0,0 → 1,211
# frv testcase for mqmachs $GRi,$GRj,$ACCk
# mach: all
 
.include "../testutils.inc"
 
start
 
.global mqmachs
mqmachs:
; Positive operands
set_fr_iimmed 2,3,fr8 ; multiply small numbers
set_fr_iimmed 3,2,fr10
set_fr_iimmed 0,1,fr9 ; multiply by 0
set_fr_iimmed 2,0,fr11
mqmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
test_accg_immed 0,accg2
test_acc_immed 0,acc2
test_accg_immed 0,accg3
test_acc_immed 0,acc3
 
set_fr_iimmed 2,1,fr8 ; multiply by 1
set_fr_iimmed 1,2,fr10
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr11
mqmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 8,acc0
test_accg_immed 0,accg1
test_acc_immed 8,acc1
test_accg_immed 0,accg2
test_acc_limmed 0,0x7ffe,acc2
test_accg_immed 0,accg3
test_acc_limmed 0,0x7ffe,acc3
 
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
set_fr_iimmed 2,0x4000,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr11
mqmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8008,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x8008,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x3fff,0x7fff,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x3fff,0x7fff,acc3
 
; Mixed operands
set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 0xfffd,2,fr10
set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
set_fr_iimmed 1,0xfffe,fr11
mqmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8002,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x8002,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x3fff,0x7ffd,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x3fff,0x7ffd,acc3
 
set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
set_fr_iimmed 0,0xfffe,fr10
set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
set_fr_iimmed 0xfffe,0x2001,fr11
mqmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8002,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x8002,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x3fff,0x3ffb,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x3fff,0x3ffb,acc3
 
set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
set_fr_iimmed 0xfffe,0x4000,fr10
set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
set_fr_iimmed 0x8000,0x7fff,fr11
mqmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x0002,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x0002,acc1
test_accg_immed 0xff,accg2
test_acc_limmed 0xffff,0xbffb,acc2
test_accg_immed 0xff,accg3
test_acc_limmed 0xffff,0xbffb,acc3
 
; Negative operands
set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 0xfffd,0xfffe,fr10
set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
set_fr_iimmed 0xfffe,0xffff,fr11
mqmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x0008,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x0008,acc1
test_accg_immed 0xff,accg2
test_acc_limmed 0xffff,0xbffd,acc2
test_accg_immed 0xff,accg3
test_acc_limmed 0xffff,0xbffd,acc3
 
set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr11
mqmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0x3fff0009,acc0
test_accg_immed 0,accg1
test_acc_immed 0x3fff0009,acc1
test_accg_immed 0,accg2
test_acc_immed 0x3fffbffd,acc2
test_accg_immed 0,accg3
test_acc_immed 0x3fffbffd,acc3
 
set_accg_immed 0x7f,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0x7f,accg1
set_acc_immed 0xffffffff,acc1
set_accg_immed 0x7f,accg2 ; saturation
set_acc_immed 0xffffffff,acc2
set_accg_immed 0x7f,accg3
set_acc_immed 0xffffffff,acc3
set_fr_iimmed 1,1,fr8
set_fr_iimmed 1,1,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
mqmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x7f,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xffff,0xffff,acc1
test_accg_immed 0x7f,accg2
test_acc_limmed 0xffff,0xffff,acc2
test_accg_immed 0x7f,accg3
test_acc_limmed 0xffff,0xffff,acc3
 
set_accg_immed 0x80,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed 0x80,accg1
set_acc_immed 0,acc1
set_accg_immed 0x80,accg2 ; saturation
set_acc_immed 0,acc2
set_accg_immed 0x80,accg3
set_acc_immed 0,acc3
set_fr_iimmed 0xffff,0,fr8
set_fr_iimmed 1,0xffff,fr10
set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
mqmachs fr8,fr10,acc0
test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x80,accg0
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
test_accg_immed 0x80,accg2
test_acc_immed 0,acc2
test_accg_immed 0x80,accg3
test_acc_immed 0,acc3
 
pass
 
 
/mmrdhs.cgs
0,0 → 1,263
# frv testcase for mmrdhs $GRi,$GRj,$ACCk
# mach: all
 
.include "../testutils.inc"
 
start
 
.global mmrdhs
mmrdhs:
; Positive operands
set_fr_iimmed 2,3,fr7 ; multiply small numbers
set_fr_iimmed 3,2,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_immed -6,acc0
test_accg_immed 0xff,accg1
test_acc_immed -6,acc1
 
set_fr_iimmed 0,1,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_immed -6,acc0
test_accg_immed 0xff,accg1
test_acc_immed -6,acc1
 
set_fr_iimmed 2,1,fr7 ; multiply by 1
set_fr_iimmed 1,2,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_immed -8,acc0
test_accg_immed 0xff,accg1
test_acc_immed -8,acc1
 
set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0x7ffa,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0x7ffa,acc1
 
set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
set_fr_iimmed 2,0x4000,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_limmed 0xfffe,0xfffa,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xfffe,0xfffa,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_limmed 0xbfff,0xfff9,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xbfff,0xfff9,acc1
 
; Mixed operands
set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers
set_fr_iimmed 0xfffd,2,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_limmed 0xbfff,0xffff,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xbfff,0xffff,acc1
 
set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1
set_fr_iimmed 1,0xfffe,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_limmed 0xc000,0x0001,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xc000,0x0001,acc1
 
set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0
set_fr_iimmed 0,0xfffe,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_limmed 0xc000,0x0001,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xc000,0x0001,acc1
 
set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result
set_fr_iimmed 0xfffe,0x2001,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_limmed 0xc000,0x4003,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xc000,0x4003,acc1
 
set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result
set_fr_iimmed 0xfffe,0x4000,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_limmed 0xc000,0xc003,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xc000,0xc003,acc1
 
set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result
set_fr_iimmed 0x8000,0x7fff,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x4003,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x4003,acc1
 
; Negative operands
set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers
set_fr_iimmed 0xfffd,0xfffe,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x3ffd,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x3ffd,acc1
 
set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1
set_fr_iimmed 0xfffe,0xffff,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x3ffb,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x3ffb,acc1
 
set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result
set_fr_iimmed 0x8001,0x8001,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_immed 0xc0013ffa,acc0
test_accg_immed 0xff,accg1
test_acc_immed 0xc0013ffa,acc1
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0
test_acc_immed 0x80013ffa,acc0
test_accg_immed 0xff,accg1
test_acc_immed 0x80013ffa,acc1
 
set_accg_immed 0x7f,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0x7f,accg1
set_acc_immed 0xffffffff,acc1
set_fr_iimmed 0xffff,1,fr7
set_fr_iimmed 1,0xffff,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x7f,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xffff,0xffff,acc1
 
set_fr_iimmed 0x8000,0x0000,fr7 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x7f,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xffff,0xffff,acc1
 
set_accg_immed 0x80,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed 0x80,accg1
set_acc_immed 0,acc1
set_fr_iimmed 0,1,fr7
set_fr_iimmed 1,1,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x80,accg0
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr8
mmrdhs fr7,fr8,acc0
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x80,accg0
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
 
pass
 
 
/mqmachu.cgs
0,0 → 1,144
# frv testcase for mqmachu $GRi,$GRj,$GRk
# mach: all
 
.include "../testutils.inc"
 
start
 
.global mqmachu
mqmachu:
set_fr_iimmed 3,2,fr8 ; multiply small numbers
set_fr_iimmed 2,3,fr10
set_fr_iimmed 1,2,fr9 ; multiply by 1
set_fr_iimmed 2,1,fr11
mqmachu fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
test_accg_immed 0,accg2
test_acc_immed 2,acc2
test_accg_immed 0,accg3
test_acc_immed 2,acc3
 
set_fr_iimmed 0,2,fr8 ; multiply by 0
set_fr_iimmed 2,0,fr10
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr11
mqmachu fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x0000,0x8000,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x0000,0x8000,acc3
 
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
set_fr_iimmed 2,0x4000,fr10
set_fr_iimmed 0x8000,2,fr9 ; 17 bit result
set_fr_iimmed 2,0x8000,fr11
mqmachu fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8006,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x8006,acc1
test_accg_immed 0,accg2
test_acc_immed 0x00018000,acc2
test_accg_immed 0,accg3
test_acc_immed 0x00018000,acc3
 
set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr10
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr11
mqmachu fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0x3fff8007,acc0
test_accg_immed 0,accg1
test_acc_immed 0x3fff8007,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x4001,0x8000,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x4001,0x8000,acc3
 
set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr10
set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr11
mqmachu fr8,fr10,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 1,accg0
test_acc_limmed 0x3ffd,0x8008,acc0
test_accg_immed 1,accg1
test_acc_limmed 0x3ffd,0x8008,acc1
test_accg_immed 1,accg2
test_acc_limmed 0x3fff,0x8001,acc2
test_accg_immed 1,accg3
test_acc_limmed 0x3fff,0x8001,acc3
 
set_accg_immed 0xff,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xffffffff,acc1
set_accg_immed 0xff,accg2 ; saturation
set_acc_immed 0xffffffff,acc2
set_accg_immed 0xff,accg3
set_acc_immed 0xffffffff,acc3
set_fr_iimmed 1,1,fr8
set_fr_iimmed 1,1,fr10
set_fr_iimmed 1,1,fr9
set_fr_iimmed 1,1,fr11
mqmachu fr8,fr10,acc0
test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xffff,acc1
test_accg_immed 0xff,accg2
test_acc_limmed 0xffff,0xffff,acc2
test_accg_immed 0xff,accg3
test_acc_limmed 0xffff,0xffff,acc3
 
set_fr_iimmed 0xffff,0x0000,fr8
set_fr_iimmed 0xffff,0xffff,fr10
set_fr_iimmed 0x0000,0xffff,fr9
set_fr_iimmed 0xffff,0xffff,fr11
mqmachu fr8,fr10,acc0
test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xffff,acc1
test_accg_immed 0xff,accg2
test_acc_limmed 0xffff,0xffff,acc2
test_accg_immed 0xff,accg3
test_acc_limmed 0xffff,0xffff,acc3
 
pass
/mmrdhu.cgs
0,0 → 1,151
# frv testcase for mmrdhu $GRi,$GRj,$GRk
# mach: all
 
.include "../testutils.inc"
 
start
 
.global mmrdhu
mmrdhu:
set_accg_immed 0x80,accg0
set_acc_immed 0,acc0
set_accg_immed 0x80,accg1
set_acc_immed 0,acc1
 
set_fr_iimmed 3,2,fr7 ; multiply small numbers
set_fr_iimmed 2,3,fr8
mmrdhu fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0
test_acc_immed 0xfffffffa,acc0
test_accg_immed 0x7f,accg1
test_acc_immed 0xfffffffa,acc1
 
set_fr_iimmed 1,2,fr7 ; multiply by 1
set_fr_iimmed 2,1,fr8
mmrdhu fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0
test_acc_immed 0xfffffff8,acc0
test_accg_immed 0x7f,accg1
test_acc_immed 0xfffffff8,acc1
 
set_fr_iimmed 0,2,fr7 ; multiply by 0
set_fr_iimmed 2,0,fr8
mmrdhu fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0
test_acc_immed 0xfffffff8,acc0
test_accg_immed 0x7f,accg1
test_acc_immed 0xfffffff8,acc1
 
set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr8
mmrdhu fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0
test_acc_limmed 0xffff,0x7ffa,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xffff,0x7ffa,acc1
 
set_fr_iimmed 0x4000,2,fr7 ; 16 bit result
set_fr_iimmed 2,0x4000,fr8
mmrdhu fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0
test_acc_limmed 0xfffe,0xfffa,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xfffe,0xfffa,acc1
 
set_fr_iimmed 0x8000,2,fr7 ; 17 bit result
set_fr_iimmed 2,0x8000,fr8
mmrdhu fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0
test_acc_limmed 0xfffd,0xfffa,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xfffd,0xfffa,acc1
 
set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr8
mmrdhu fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0
test_acc_limmed 0xbffe,0xfff9,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xbffe,0xfff9,acc1
 
set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr8
mmrdhu fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0
test_acc_limmed 0x7ffe,0xfff9,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0x7ffe,0xfff9,acc1
 
set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr8
mmrdhu fr7,fr8,acc0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7e,accg0
test_acc_limmed 0x8000,0xfff8,acc0
test_accg_immed 0x7e,accg1
test_acc_limmed 0x8000,0xfff8,acc1
 
set_accg_immed 0,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed 0,accg1
set_acc_immed 0,acc1
set_fr_iimmed 1,1,fr7
set_fr_iimmed 1,1,fr8
mmrdhu fr7,fr8,acc0
test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
set_fr_iimmed 0x0000,0xffff,fr7
set_fr_iimmed 0xffff,0xffff,fr8
mmrdhu fr7,fr8,acc0
test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0,accg0
test_acc_immed 0,acc0
test_accg_immed 0,accg1
test_acc_immed 0,acc1
 
pass
/cmqmachs.cgs
0,0 → 1,1262
# frv testcase for cmqmachs $GRi,$GRj,$ACCk,$CCi,$cond
# mach: all
 
.include "../testutils.inc"
 
start
 
.global cmqmachs
cmqmachs:
set_spr_immed 0x1b1b,cccr
 
; Positive operands
set_spr_immed 0,msr0
set_accg_immed 0,accg0
set_acc_immed 0,acc0
set_accg_immed 0,accg1
set_acc_immed 0,acc1
set_accg_immed 0,accg2
set_acc_immed 0,acc2
set_accg_immed 0,accg3
set_acc_immed 0,acc3
set_fr_iimmed 2,3,fr8 ; multiply small numbers
set_fr_iimmed 3,2,fr10
set_fr_iimmed 0,1,fr9 ; multiply by 0
set_fr_iimmed 2,0,fr11
cmqmachs fr8,fr10,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
test_accg_immed 0,accg2
test_acc_immed 0,acc2
test_accg_immed 0,accg3
test_acc_immed 0,acc3
 
set_fr_iimmed 2,1,fr8 ; multiply by 1
set_fr_iimmed 1,2,fr10
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr11
cmqmachs fr8,fr10,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 8,acc0
test_accg_immed 0,accg1
test_acc_immed 8,acc1
test_accg_immed 0,accg2
test_acc_limmed 0,0x7ffe,acc2
test_accg_immed 0,accg3
test_acc_limmed 0,0x7ffe,acc3
 
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
set_fr_iimmed 2,0x4000,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8008,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x8008,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x3fff,0x7fff,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x3fff,0x7fff,acc3
 
; Mixed operands
set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 0xfffd,2,fr10
set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
set_fr_iimmed 1,0xfffe,fr11
cmqmachs fr8,fr10,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8002,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x8002,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x3fff,0x7ffd,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x3fff,0x7ffd,acc3
 
set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
set_fr_iimmed 0,0xfffe,fr10
set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
set_fr_iimmed 0xfffe,0x2001,fr11
cmqmachs fr8,fr10,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8002,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x8002,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x3fff,0x3ffb,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x3fff,0x3ffb,acc3
 
set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
set_fr_iimmed 0xfffe,0x4000,fr10
set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
set_fr_iimmed 0x8000,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc4,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x0002,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x0002,acc1
test_accg_immed 0xff,accg2
test_acc_limmed 0xffff,0xbffb,acc2
test_accg_immed 0xff,accg3
test_acc_limmed 0xffff,0xbffb,acc3
 
; Negative operands
set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 0xfffd,0xfffe,fr10
set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
set_fr_iimmed 0xfffe,0xffff,fr11
cmqmachs fr8,fr10,acc0,cc4,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x0008,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x0008,acc1
test_accg_immed 0xff,accg2
test_acc_limmed 0xffff,0xbffd,acc2
test_accg_immed 0xff,accg3
test_acc_limmed 0xffff,0xbffd,acc3
 
set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr11
cmqmachs fr8,fr10,acc0,cc4,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0x3fff0009,acc0
test_accg_immed 0,accg1
test_acc_immed 0x3fff0009,acc1
test_accg_immed 0,accg2
test_acc_immed 0x3fffbffd,acc2
test_accg_immed 0,accg3
test_acc_immed 0x3fffbffd,acc3
 
set_accg_immed 0x7f,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0x7f,accg1
set_acc_immed 0xffffffff,acc1
set_accg_immed 0x7f,accg2 ; saturation
set_acc_immed 0xffffffff,acc2
set_accg_immed 0x7f,accg3
set_acc_immed 0xffffffff,acc3
set_fr_iimmed 1,1,fr8
set_fr_iimmed 1,1,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc4,1
test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x7f,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xffff,0xffff,acc1
test_accg_immed 0x7f,accg2
test_acc_limmed 0xffff,0xffff,acc2
test_accg_immed 0x7f,accg3
test_acc_limmed 0xffff,0xffff,acc3
 
set_accg_immed 0x80,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed 0x80,accg1
set_acc_immed 0,acc1
set_accg_immed 0x80,accg2 ; saturation
set_acc_immed 0,acc2
set_accg_immed 0x80,accg3
set_acc_immed 0,acc3
set_fr_iimmed 0xffff,0,fr8
set_fr_iimmed 1,0xffff,fr10
set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc4,1
test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x80,accg0
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
test_accg_immed 0x80,accg2
test_acc_immed 0,acc2
test_accg_immed 0x80,accg3
test_acc_immed 0,acc3
 
; Positive operands
set_spr_immed 0,msr0
set_accg_immed 0,accg0
set_acc_immed 0,acc0
set_accg_immed 0,accg1
set_acc_immed 0,acc1
set_accg_immed 0,accg2
set_acc_immed 0,acc2
set_accg_immed 0,accg3
set_acc_immed 0,acc3
set_fr_iimmed 2,3,fr8 ; multiply small numbers
set_fr_iimmed 3,2,fr10
set_fr_iimmed 0,1,fr9 ; multiply by 0
set_fr_iimmed 2,0,fr11
cmqmachs fr8,fr10,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
test_accg_immed 0,accg2
test_acc_immed 0,acc2
test_accg_immed 0,accg3
test_acc_immed 0,acc3
 
set_fr_iimmed 2,1,fr8 ; multiply by 1
set_fr_iimmed 1,2,fr10
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr11
cmqmachs fr8,fr10,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 8,acc0
test_accg_immed 0,accg1
test_acc_immed 8,acc1
test_accg_immed 0,accg2
test_acc_limmed 0,0x7ffe,acc2
test_accg_immed 0,accg3
test_acc_limmed 0,0x7ffe,acc3
 
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
set_fr_iimmed 2,0x4000,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8008,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x8008,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x3fff,0x7fff,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x3fff,0x7fff,acc3
 
; Mixed operands
set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 0xfffd,2,fr10
set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
set_fr_iimmed 1,0xfffe,fr11
cmqmachs fr8,fr10,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8002,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x8002,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x3fff,0x7ffd,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x3fff,0x7ffd,acc3
 
set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
set_fr_iimmed 0,0xfffe,fr10
set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
set_fr_iimmed 0xfffe,0x2001,fr11
cmqmachs fr8,fr10,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8002,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x8002,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x3fff,0x3ffb,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x3fff,0x3ffb,acc3
 
set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
set_fr_iimmed 0xfffe,0x4000,fr10
set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
set_fr_iimmed 0x8000,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc5,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x0002,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x0002,acc1
test_accg_immed 0xff,accg2
test_acc_limmed 0xffff,0xbffb,acc2
test_accg_immed 0xff,accg3
test_acc_limmed 0xffff,0xbffb,acc3
 
; Negative operands
set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 0xfffd,0xfffe,fr10
set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
set_fr_iimmed 0xfffe,0xffff,fr11
cmqmachs fr8,fr10,acc0,cc5,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x0008,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x0008,acc1
test_accg_immed 0xff,accg2
test_acc_limmed 0xffff,0xbffd,acc2
test_accg_immed 0xff,accg3
test_acc_limmed 0xffff,0xbffd,acc3
 
set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr11
cmqmachs fr8,fr10,acc0,cc5,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0x3fff0009,acc0
test_accg_immed 0,accg1
test_acc_immed 0x3fff0009,acc1
test_accg_immed 0,accg2
test_acc_immed 0x3fffbffd,acc2
test_accg_immed 0,accg3
test_acc_immed 0x3fffbffd,acc3
 
set_accg_immed 0x7f,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0x7f,accg1
set_acc_immed 0xffffffff,acc1
set_accg_immed 0x7f,accg2 ; saturation
set_acc_immed 0xffffffff,acc2
set_accg_immed 0x7f,accg3
set_acc_immed 0xffffffff,acc3
set_fr_iimmed 1,1,fr8
set_fr_iimmed 1,1,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc5,0
test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x7f,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0x7f,accg1
test_acc_limmed 0xffff,0xffff,acc1
test_accg_immed 0x7f,accg2
test_acc_limmed 0xffff,0xffff,acc2
test_accg_immed 0x7f,accg3
test_acc_limmed 0xffff,0xffff,acc3
 
set_accg_immed 0x80,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed 0x80,accg1
set_acc_immed 0,acc1
set_accg_immed 0x80,accg2 ; saturation
set_acc_immed 0,acc2
set_accg_immed 0x80,accg3
set_acc_immed 0,acc3
set_fr_iimmed 0xffff,0,fr8
set_fr_iimmed 1,0xffff,fr10
set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc5,0
test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0x80,accg0
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
test_accg_immed 0x80,accg2
test_acc_immed 0,acc2
test_accg_immed 0x80,accg3
test_acc_immed 0,acc3
 
; Positive operands
set_spr_immed 0,msr0
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_accg_immed 0x00000022,accg1
set_acc_immed 0x22222222,acc1
set_accg_immed 0x00000033,accg2
set_acc_immed 0x33333333,acc2
set_accg_immed 0x00000044,accg3
set_acc_immed 0x44444444,acc3
set_fr_iimmed 2,3,fr8 ; multiply small numbers
set_fr_iimmed 3,2,fr10
set_fr_iimmed 0,1,fr9 ; multiply by 0
set_fr_iimmed 2,0,fr11
cmqmachs fr8,fr10,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 2,1,fr8 ; multiply by 1
set_fr_iimmed 1,2,fr10
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr11
cmqmachs fr8,fr10,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
set_fr_iimmed 2,0x4000,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
; Mixed operands
set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 0xfffd,2,fr10
set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
set_fr_iimmed 1,0xfffe,fr11
cmqmachs fr8,fr10,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
set_fr_iimmed 0,0xfffe,fr10
set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
set_fr_iimmed 0xfffe,0x2001,fr11
cmqmachs fr8,fr10,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
set_fr_iimmed 0xfffe,0x4000,fr10
set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
set_fr_iimmed 0x8000,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
; Negative operands
set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 0xfffd,0xfffe,fr10
set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
set_fr_iimmed 0xfffe,0xffff,fr11
cmqmachs fr8,fr10,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr11
cmqmachs fr8,fr10,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_accg_immed 0x7f,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0x7f,accg1
set_acc_immed 0xffffffff,acc1
set_accg_immed 0x7f,accg2 ; saturation
set_acc_immed 0xffffffff,acc2
set_accg_immed 0x7f,accg3
set_acc_immed 0xffffffff,acc3
set_fr_iimmed 1,1,fr8
set_fr_iimmed 1,1,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0x7f,accg1
test_acc_immed 0xffffffff,acc1
test_accg_immed 0x7f,accg2 ; saturation
test_acc_immed 0xffffffff,acc2
test_accg_immed 0x7f,accg3
test_acc_immed 0xffffffff,acc3
 
set_accg_immed 0x80,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed 0x80,accg1
set_acc_immed 0,acc1
set_accg_immed 0x80,accg2 ; saturation
set_acc_immed 0,acc2
set_accg_immed 0x80,accg3
set_acc_immed 0,acc3
set_fr_iimmed 0xffff,0,fr8
set_fr_iimmed 1,0xffff,fr10
set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x80,accg0 ; saturation
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
test_accg_immed 0x80,accg2 ; saturation
test_acc_immed 0,acc2
test_accg_immed 0x80,accg3
test_acc_immed 0,acc3
 
; Positive operands
set_spr_immed 0,msr0
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_accg_immed 0x00000022,accg1
set_acc_immed 0x22222222,acc1
set_accg_immed 0x00000033,accg2
set_acc_immed 0x33333333,acc2
set_accg_immed 0x00000044,accg3
set_acc_immed 0x44444444,acc3
set_fr_iimmed 2,3,fr8 ; multiply small numbers
set_fr_iimmed 3,2,fr10
set_fr_iimmed 0,1,fr9 ; multiply by 0
set_fr_iimmed 2,0,fr11
cmqmachs fr8,fr10,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 2,1,fr8 ; multiply by 1
set_fr_iimmed 1,2,fr10
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr11
cmqmachs fr8,fr10,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
set_fr_iimmed 2,0x4000,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
; Mixed operands
set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 0xfffd,2,fr10
set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
set_fr_iimmed 1,0xfffe,fr11
cmqmachs fr8,fr10,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
set_fr_iimmed 0,0xfffe,fr10
set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
set_fr_iimmed 0xfffe,0x2001,fr11
cmqmachs fr8,fr10,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
set_fr_iimmed 0xfffe,0x4000,fr10
set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
set_fr_iimmed 0x8000,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
; Negative operands
set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 0xfffd,0xfffe,fr10
set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
set_fr_iimmed 0xfffe,0xffff,fr11
cmqmachs fr8,fr10,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr11
cmqmachs fr8,fr10,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_accg_immed 0x7f,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0x7f,accg1
set_acc_immed 0xffffffff,acc1
set_accg_immed 0x7f,accg2 ; saturation
set_acc_immed 0xffffffff,acc2
set_accg_immed 0x7f,accg3
set_acc_immed 0xffffffff,acc3
set_fr_iimmed 1,1,fr8
set_fr_iimmed 1,1,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0x7f,accg1
test_acc_immed 0xffffffff,acc1
test_accg_immed 0x7f,accg2 ; saturation
test_acc_immed 0xffffffff,acc2
test_accg_immed 0x7f,accg3
test_acc_immed 0xffffffff,acc3
 
set_accg_immed 0x80,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed 0x80,accg1
set_acc_immed 0,acc1
set_accg_immed 0x80,accg2 ; saturation
set_acc_immed 0,acc2
set_accg_immed 0x80,accg3
set_acc_immed 0,acc3
set_fr_iimmed 0xffff,0,fr8
set_fr_iimmed 1,0xffff,fr10
set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x80,accg0 ; saturation
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
test_accg_immed 0x80,accg2 ; saturation
test_acc_immed 0,acc2
test_accg_immed 0x80,accg3
test_acc_immed 0,acc3
 
; Positive operands
set_spr_immed 0,msr0
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_accg_immed 0x00000022,accg1
set_acc_immed 0x22222222,acc1
set_accg_immed 0x00000033,accg2
set_acc_immed 0x33333333,acc2
set_accg_immed 0x00000044,accg3
set_acc_immed 0x44444444,acc3
set_fr_iimmed 2,3,fr8 ; multiply small numbers
set_fr_iimmed 3,2,fr10
set_fr_iimmed 0,1,fr9 ; multiply by 0
set_fr_iimmed 2,0,fr11
cmqmachs fr8,fr10,acc0,cc2,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 2,1,fr8 ; multiply by 1
set_fr_iimmed 1,2,fr10
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr11
cmqmachs fr8,fr10,acc0,cc2,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
set_fr_iimmed 2,0x4000,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc2,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
; Mixed operands
set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 0xfffd,2,fr10
set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
set_fr_iimmed 1,0xfffe,fr11
cmqmachs fr8,fr10,acc0,cc2,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
set_fr_iimmed 0,0xfffe,fr10
set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
set_fr_iimmed 0xfffe,0x2001,fr11
cmqmachs fr8,fr10,acc0,cc2,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
set_fr_iimmed 0xfffe,0x4000,fr10
set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
set_fr_iimmed 0x8000,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc6,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
; Negative operands
set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 0xfffd,0xfffe,fr10
set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
set_fr_iimmed 0xfffe,0xffff,fr11
cmqmachs fr8,fr10,acc0,cc6,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr11
cmqmachs fr8,fr10,acc0,cc6,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_accg_immed 0x7f,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0x7f,accg1
set_acc_immed 0xffffffff,acc1
set_accg_immed 0x7f,accg2 ; saturation
set_acc_immed 0xffffffff,acc2
set_accg_immed 0x7f,accg3
set_acc_immed 0xffffffff,acc3
set_fr_iimmed 1,1,fr8
set_fr_iimmed 1,1,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc6,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0x7f,accg1
test_acc_immed 0xffffffff,acc1
test_accg_immed 0x7f,accg2 ; saturation
test_acc_immed 0xffffffff,acc2
test_accg_immed 0x7f,accg3
test_acc_immed 0xffffffff,acc3
 
set_accg_immed 0x80,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed 0x80,accg1
set_acc_immed 0,acc1
set_accg_immed 0x80,accg2 ; saturation
set_acc_immed 0,acc2
set_accg_immed 0x80,accg3
set_acc_immed 0,acc3
set_fr_iimmed 0xffff,0,fr8
set_fr_iimmed 1,0xffff,fr10
set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc6,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x80,accg0 ; saturation
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
test_accg_immed 0x80,accg2 ; saturation
test_acc_immed 0,acc2
test_accg_immed 0x80,accg3
test_acc_immed 0,acc3
;
; Positive operands
set_spr_immed 0,msr0
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_accg_immed 0x00000022,accg1
set_acc_immed 0x22222222,acc1
set_accg_immed 0x00000033,accg2
set_acc_immed 0x33333333,acc2
set_accg_immed 0x00000044,accg3
set_acc_immed 0x44444444,acc3
set_fr_iimmed 2,3,fr8 ; multiply small numbers
set_fr_iimmed 3,2,fr10
set_fr_iimmed 0,1,fr9 ; multiply by 0
set_fr_iimmed 2,0,fr11
cmqmachs fr8,fr10,acc0,cc3,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 2,1,fr8 ; multiply by 1
set_fr_iimmed 1,2,fr10
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr11
cmqmachs fr8,fr10,acc0,cc3,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
set_fr_iimmed 2,0x4000,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc3,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
; Mixed operands
set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 0xfffd,2,fr10
set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
set_fr_iimmed 1,0xfffe,fr11
cmqmachs fr8,fr10,acc0,cc3,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
set_fr_iimmed 0,0xfffe,fr10
set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
set_fr_iimmed 0xfffe,0x2001,fr11
cmqmachs fr8,fr10,acc0,cc3,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
set_fr_iimmed 0xfffe,0x4000,fr10
set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
set_fr_iimmed 0x8000,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc7,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
; Negative operands
set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
set_fr_iimmed 0xfffd,0xfffe,fr10
set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
set_fr_iimmed 0xfffe,0xffff,fr11
cmqmachs fr8,fr10,acc0,cc7,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
set_fr_iimmed 0x8001,0x8001,fr10
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr11
cmqmachs fr8,fr10,acc0,cc7,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_accg_immed 0x7f,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0x7f,accg1
set_acc_immed 0xffffffff,acc1
set_accg_immed 0x7f,accg2 ; saturation
set_acc_immed 0xffffffff,acc2
set_accg_immed 0x7f,accg3
set_acc_immed 0xffffffff,acc3
set_fr_iimmed 1,1,fr8
set_fr_iimmed 1,1,fr10
set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc7,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x7f,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0x7f,accg1
test_acc_immed 0xffffffff,acc1
test_accg_immed 0x7f,accg2 ; saturation
test_acc_immed 0xffffffff,acc2
test_accg_immed 0x7f,accg3
test_acc_immed 0xffffffff,acc3
 
set_accg_immed 0x80,accg0 ; saturation
set_acc_immed 0,acc0
set_accg_immed 0x80,accg1
set_acc_immed 0,acc1
set_accg_immed 0x80,accg2 ; saturation
set_acc_immed 0,acc2
set_accg_immed 0x80,accg3
set_acc_immed 0,acc3
set_fr_iimmed 0xffff,0,fr8
set_fr_iimmed 1,0xffff,fr10
set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
set_fr_iimmed 0x7fff,0x7fff,fr11
cmqmachs fr8,fr10,acc0,cc7,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x80,accg0 ; saturation
test_acc_immed 0,acc0
test_accg_immed 0x80,accg1
test_acc_immed 0,acc1
test_accg_immed 0x80,accg2 ; saturation
test_acc_immed 0,acc2
test_accg_immed 0x80,accg3
test_acc_immed 0,acc3
 
pass
 
 
/cmqmachu.cgs
0,0 → 1,870
# frv testcase for cmqmachu $GRi,$GRj,$GRk,$CCi,$cond
# mach: all
 
.include "../testutils.inc"
 
start
 
.global cmqmachu
cmqmachu:
set_spr_immed 0x1b1b,cccr
 
set_spr_immed 0,msr0
set_accg_immed 0,accg0
set_acc_immed 0,acc0
set_accg_immed 0,accg1
set_acc_immed 0,acc1
set_accg_immed 0,accg2
set_acc_immed 0,acc2
set_accg_immed 0,accg3
set_acc_immed 0,acc3
set_fr_iimmed 3,2,fr8 ; multiply small numbers
set_fr_iimmed 2,3,fr10
set_fr_iimmed 1,2,fr9 ; multiply by 1
set_fr_iimmed 2,1,fr11
cmqmachu fr8,fr10,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
test_accg_immed 0,accg2
test_acc_immed 2,acc2
test_accg_immed 0,accg3
test_acc_immed 2,acc3
 
set_fr_iimmed 0,2,fr8 ; multiply by 0
set_fr_iimmed 2,0,fr10
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr11
cmqmachu fr8,fr10,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x0000,0x8000,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x0000,0x8000,acc3
 
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
set_fr_iimmed 2,0x4000,fr10
set_fr_iimmed 0x8000,2,fr9 ; 17 bit result
set_fr_iimmed 2,0x8000,fr11
cmqmachu fr8,fr10,acc0,cc0,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8006,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x8006,acc1
test_accg_immed 0,accg2
test_acc_immed 0x00018000,acc2
test_accg_immed 0,accg3
test_acc_immed 0x00018000,acc3
 
set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr10
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr11
cmqmachu fr8,fr10,acc0,cc4,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0x3fff8007,acc0
test_accg_immed 0,accg1
test_acc_immed 0x3fff8007,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x4001,0x8000,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x4001,0x8000,acc3
 
set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr10
set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr11
cmqmachu fr8,fr10,acc0,cc4,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 1,accg0
test_acc_limmed 0x3ffd,0x8008,acc0
test_accg_immed 1,accg1
test_acc_limmed 0x3ffd,0x8008,acc1
test_accg_immed 1,accg2
test_acc_limmed 0x3fff,0x8001,acc2
test_accg_immed 1,accg3
test_acc_limmed 0x3fff,0x8001,acc3
 
set_accg_immed 0xff,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xffffffff,acc1
set_accg_immed 0xff,accg2 ; saturation
set_acc_immed 0xffffffff,acc2
set_accg_immed 0xff,accg3
set_acc_immed 0xffffffff,acc3
set_fr_iimmed 1,1,fr8
set_fr_iimmed 1,1,fr10
set_fr_iimmed 1,1,fr9
set_fr_iimmed 1,1,fr11
cmqmachu fr8,fr10,acc0,cc4,1
test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xffff,acc1
test_accg_immed 0xff,accg2
test_acc_limmed 0xffff,0xffff,acc2
test_accg_immed 0xff,accg3
test_acc_limmed 0xffff,0xffff,acc3
 
set_fr_iimmed 0xffff,0x0000,fr8
set_fr_iimmed 0xffff,0xffff,fr10
set_fr_iimmed 0x0000,0xffff,fr9
set_fr_iimmed 0xffff,0xffff,fr11
cmqmachu fr8,fr10,acc0,cc4,1
test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xffff,acc1
test_accg_immed 0xff,accg2
test_acc_limmed 0xffff,0xffff,acc2
test_accg_immed 0xff,accg3
test_acc_limmed 0xffff,0xffff,acc3
 
set_spr_immed 0,msr0
set_accg_immed 0,accg0
set_acc_immed 0,acc0
set_accg_immed 0,accg1
set_acc_immed 0,acc1
set_accg_immed 0,accg2
set_acc_immed 0,acc2
set_accg_immed 0,accg3
set_acc_immed 0,acc3
set_fr_iimmed 3,2,fr8 ; multiply small numbers
set_fr_iimmed 2,3,fr10
set_fr_iimmed 1,2,fr9 ; multiply by 1
set_fr_iimmed 2,1,fr11
cmqmachu fr8,fr10,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
test_accg_immed 0,accg2
test_acc_immed 2,acc2
test_accg_immed 0,accg3
test_acc_immed 2,acc3
 
set_fr_iimmed 0,2,fr8 ; multiply by 0
set_fr_iimmed 2,0,fr10
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr11
cmqmachu fr8,fr10,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 6,acc0
test_accg_immed 0,accg1
test_acc_immed 6,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x0000,0x8000,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x0000,0x8000,acc3
 
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
set_fr_iimmed 2,0x4000,fr10
set_fr_iimmed 0x8000,2,fr9 ; 17 bit result
set_fr_iimmed 2,0x8000,fr11
cmqmachu fr8,fr10,acc0,cc1,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_limmed 0x0000,0x8006,acc0
test_accg_immed 0,accg1
test_acc_limmed 0x0000,0x8006,acc1
test_accg_immed 0,accg2
test_acc_immed 0x00018000,acc2
test_accg_immed 0,accg3
test_acc_immed 0x00018000,acc3
 
set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr10
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr11
cmqmachu fr8,fr10,acc0,cc5,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0,accg0
test_acc_immed 0x3fff8007,acc0
test_accg_immed 0,accg1
test_acc_immed 0x3fff8007,acc1
test_accg_immed 0,accg2
test_acc_limmed 0x4001,0x8000,acc2
test_accg_immed 0,accg3
test_acc_limmed 0x4001,0x8000,acc3
 
set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr10
set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr11
cmqmachu fr8,fr10,acc0,cc5,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 1,accg0
test_acc_limmed 0x3ffd,0x8008,acc0
test_accg_immed 1,accg1
test_acc_limmed 0x3ffd,0x8008,acc1
test_accg_immed 1,accg2
test_acc_limmed 0x3fff,0x8001,acc2
test_accg_immed 1,accg3
test_acc_limmed 0x3fff,0x8001,acc3
 
set_accg_immed 0xff,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xffffffff,acc1
set_accg_immed 0xff,accg2 ; saturation
set_acc_immed 0xffffffff,acc2
set_accg_immed 0xff,accg3
set_acc_immed 0xffffffff,acc3
set_fr_iimmed 1,1,fr8
set_fr_iimmed 1,1,fr10
set_fr_iimmed 1,1,fr9
set_fr_iimmed 1,1,fr11
cmqmachu fr8,fr10,acc0,cc5,0
test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xffff,acc1
test_accg_immed 0xff,accg2
test_acc_limmed 0xffff,0xffff,acc2
test_accg_immed 0xff,accg3
test_acc_limmed 0xffff,0xffff,acc3
 
set_fr_iimmed 0xffff,0x0000,fr8
set_fr_iimmed 0xffff,0xffff,fr10
set_fr_iimmed 0x0000,0xffff,fr9
set_fr_iimmed 0xffff,0xffff,fr11
cmqmachu fr8,fr10,acc0,cc5,0
test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
test_accg_immed 0xff,accg0
test_acc_limmed 0xffff,0xffff,acc0
test_accg_immed 0xff,accg1
test_acc_limmed 0xffff,0xffff,acc1
test_accg_immed 0xff,accg2
test_acc_limmed 0xffff,0xffff,acc2
test_accg_immed 0xff,accg3
test_acc_limmed 0xffff,0xffff,acc3
 
set_spr_immed 0,msr0
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_accg_immed 0x00000022,accg1
set_acc_immed 0x22222222,acc1
set_accg_immed 0x00000033,accg2
set_acc_immed 0x33333333,acc2
set_accg_immed 0x00000044,accg3
set_acc_immed 0x44444444,acc3
set_fr_iimmed 3,2,fr8 ; multiply small numbers
set_fr_iimmed 2,3,fr10
set_fr_iimmed 1,2,fr9 ; multiply by 1
set_fr_iimmed 2,1,fr11
cmqmachu fr8,fr10,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0,2,fr8 ; multiply by 0
set_fr_iimmed 2,0,fr10
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr11
cmqmachu fr8,fr10,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
set_fr_iimmed 2,0x4000,fr10
set_fr_iimmed 0x8000,2,fr9 ; 17 bit result
set_fr_iimmed 2,0x8000,fr11
cmqmachu fr8,fr10,acc0,cc0,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr10
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr11
cmqmachu fr8,fr10,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr10
set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr11
cmqmachu fr8,fr10,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_accg_immed 0xff,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xffffffff,acc1
set_accg_immed 0xff,accg2 ; saturation
set_acc_immed 0xffffffff,acc2
set_accg_immed 0xff,accg3
set_acc_immed 0xffffffff,acc3
set_fr_iimmed 1,1,fr8
set_fr_iimmed 1,1,fr10
set_fr_iimmed 1,1,fr9
set_fr_iimmed 1,1,fr11
cmqmachu fr8,fr10,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0xff,accg1
test_acc_immed 0xffffffff,acc1
test_accg_immed 0xff,accg2 ; saturation
test_acc_immed 0xffffffff,acc2
test_accg_immed 0xff,accg3
test_acc_immed 0xffffffff,acc3
 
set_fr_iimmed 0xffff,0x0000,fr8
set_fr_iimmed 0xffff,0xffff,fr10
set_fr_iimmed 0x0000,0xffff,fr9
set_fr_iimmed 0xffff,0xffff,fr11
cmqmachu fr8,fr10,acc0,cc4,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0xff,accg1
test_acc_immed 0xffffffff,acc1
test_accg_immed 0xff,accg2 ; saturation
test_acc_immed 0xffffffff,acc2
test_accg_immed 0xff,accg3
test_acc_immed 0xffffffff,acc3
 
set_spr_immed 0,msr0
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_accg_immed 0x00000022,accg1
set_acc_immed 0x22222222,acc1
set_accg_immed 0x00000033,accg2
set_acc_immed 0x33333333,acc2
set_accg_immed 0x00000044,accg3
set_acc_immed 0x44444444,acc3
set_fr_iimmed 3,2,fr8 ; multiply small numbers
set_fr_iimmed 2,3,fr10
set_fr_iimmed 1,2,fr9 ; multiply by 1
set_fr_iimmed 2,1,fr11
cmqmachu fr8,fr10,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0,2,fr8 ; multiply by 0
set_fr_iimmed 2,0,fr10
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr11
cmqmachu fr8,fr10,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
set_fr_iimmed 2,0x4000,fr10
set_fr_iimmed 0x8000,2,fr9 ; 17 bit result
set_fr_iimmed 2,0x8000,fr11
cmqmachu fr8,fr10,acc0,cc1,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr10
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr11
cmqmachu fr8,fr10,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr10
set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr11
cmqmachu fr8,fr10,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_accg_immed 0xff,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xffffffff,acc1
set_accg_immed 0xff,accg2 ; saturation
set_acc_immed 0xffffffff,acc2
set_accg_immed 0xff,accg3
set_acc_immed 0xffffffff,acc3
set_fr_iimmed 1,1,fr8
set_fr_iimmed 1,1,fr10
set_fr_iimmed 1,1,fr9
set_fr_iimmed 1,1,fr11
cmqmachu fr8,fr10,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0xff,accg1
test_acc_immed 0xffffffff,acc1
test_accg_immed 0xff,accg2 ; saturation
test_acc_immed 0xffffffff,acc2
test_accg_immed 0xff,accg3
test_acc_immed 0xffffffff,acc3
 
set_fr_iimmed 0xffff,0x0000,fr8
set_fr_iimmed 0xffff,0xffff,fr10
set_fr_iimmed 0x0000,0xffff,fr9
set_fr_iimmed 0xffff,0xffff,fr11
cmqmachu fr8,fr10,acc0,cc5,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0xff,accg1
test_acc_immed 0xffffffff,acc1
test_accg_immed 0xff,accg2 ; saturation
test_acc_immed 0xffffffff,acc2
test_accg_immed 0xff,accg3
test_acc_immed 0xffffffff,acc3
 
set_spr_immed 0,msr0
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_accg_immed 0x00000022,accg1
set_acc_immed 0x22222222,acc1
set_accg_immed 0x00000033,accg2
set_acc_immed 0x33333333,acc2
set_accg_immed 0x00000044,accg3
set_acc_immed 0x44444444,acc3
set_fr_iimmed 3,2,fr8 ; multiply small numbers
set_fr_iimmed 2,3,fr10
set_fr_iimmed 1,2,fr9 ; multiply by 1
set_fr_iimmed 2,1,fr11
cmqmachu fr8,fr10,acc0,cc2,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0,2,fr8 ; multiply by 0
set_fr_iimmed 2,0,fr10
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr11
cmqmachu fr8,fr10,acc0,cc2,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
set_fr_iimmed 2,0x4000,fr10
set_fr_iimmed 0x8000,2,fr9 ; 17 bit result
set_fr_iimmed 2,0x8000,fr11
cmqmachu fr8,fr10,acc0,cc2,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr10
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr11
cmqmachu fr8,fr10,acc0,cc6,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr10
set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr11
cmqmachu fr8,fr10,acc0,cc6,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_accg_immed 0xff,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xffffffff,acc1
set_accg_immed 0xff,accg2 ; saturation
set_acc_immed 0xffffffff,acc2
set_accg_immed 0xff,accg3
set_acc_immed 0xffffffff,acc3
set_fr_iimmed 1,1,fr8
set_fr_iimmed 1,1,fr10
set_fr_iimmed 1,1,fr9
set_fr_iimmed 1,1,fr11
cmqmachu fr8,fr10,acc0,cc6,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0xff,accg1
test_acc_immed 0xffffffff,acc1
test_accg_immed 0xff,accg2 ; saturation
test_acc_immed 0xffffffff,acc2
test_accg_immed 0xff,accg3
test_acc_immed 0xffffffff,acc3
 
set_fr_iimmed 0xffff,0x0000,fr8
set_fr_iimmed 0xffff,0xffff,fr10
set_fr_iimmed 0x0000,0xffff,fr9
set_fr_iimmed 0xffff,0xffff,fr11
cmqmachu fr8,fr10,acc0,cc6,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0xff,accg1
test_acc_immed 0xffffffff,acc1
test_accg_immed 0xff,accg2 ; saturation
test_acc_immed 0xffffffff,acc2
test_accg_immed 0xff,accg3
test_acc_immed 0xffffffff,acc3
;
set_spr_immed 0,msr0
set_accg_immed 0x00000011,accg0
set_acc_immed 0x11111111,acc0
set_accg_immed 0x00000022,accg1
set_acc_immed 0x22222222,acc1
set_accg_immed 0x00000033,accg2
set_acc_immed 0x33333333,acc2
set_accg_immed 0x00000044,accg3
set_acc_immed 0x44444444,acc3
set_fr_iimmed 3,2,fr8 ; multiply small numbers
set_fr_iimmed 2,3,fr10
set_fr_iimmed 1,2,fr9 ; multiply by 1
set_fr_iimmed 2,1,fr11
cmqmachu fr8,fr10,acc0,cc3,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0,2,fr8 ; multiply by 0
set_fr_iimmed 2,0,fr10
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
set_fr_iimmed 2,0x3fff,fr11
cmqmachu fr8,fr10,acc0,cc3,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
set_fr_iimmed 2,0x4000,fr10
set_fr_iimmed 0x8000,2,fr9 ; 17 bit result
set_fr_iimmed 2,0x8000,fr11
cmqmachu fr8,fr10,acc0,cc3,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result
set_fr_iimmed 0x7fff,0x7fff,fr10
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
set_fr_iimmed 0x8000,0x8000,fr11
cmqmachu fr8,fr10,acc0,cc7,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr10
set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result
set_fr_iimmed 0xffff,0xffff,fr11
cmqmachu fr8,fr10,acc0,cc7,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0x00000011,accg0
test_acc_immed 0x11111111,acc0
test_accg_immed 0x00000022,accg1
test_acc_immed 0x22222222,acc1
test_accg_immed 0x00000033,accg2
test_acc_immed 0x33333333,acc2
test_accg_immed 0x00000044,accg3
test_acc_immed 0x44444444,acc3
 
set_accg_immed 0xff,accg0 ; saturation
set_acc_immed 0xffffffff,acc0
set_accg_immed 0xff,accg1
set_acc_immed 0xffffffff,acc1
set_accg_immed 0xff,accg2 ; saturation
set_acc_immed 0xffffffff,acc2
set_accg_immed 0xff,accg3
set_acc_immed 0xffffffff,acc3
set_fr_iimmed 1,1,fr8
set_fr_iimmed 1,1,fr10
set_fr_iimmed 1,1,fr9
set_fr_iimmed 1,1,fr11
cmqmachu fr8,fr10,acc0,cc7,0
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0xff,accg1
test_acc_immed 0xffffffff,acc1
test_accg_immed 0xff,accg2 ; saturation
test_acc_immed 0xffffffff,acc2
test_accg_immed 0xff,accg3
test_acc_immed 0xffffffff,acc3
 
set_fr_iimmed 0xffff,0x0000,fr8
set_fr_iimmed 0xffff,0xffff,fr10
set_fr_iimmed 0x0000,0xffff,fr9
set_fr_iimmed 0xffff,0xffff,fr11
cmqmachu fr8,fr10,acc0,cc7,1
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
test_accg_immed 0xff,accg0 ; saturation
test_acc_immed 0xffffffff,acc0
test_accg_immed 0xff,accg1
test_acc_immed 0xffffffff,acc1
test_accg_immed 0xff,accg2 ; saturation
test_acc_immed 0xffffffff,acc2
test_accg_immed 0xff,accg3
test_acc_immed 0xffffffff,acc3
 
pass

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