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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

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  • This comparison shows the changes necessary to convert path 
    /openrisc/tags/gdb/gdb-6.8/gdb-6.8.openrisc-2.1/sim/testsuite/sim/frv/interrupts
    from Rev 24 to Rev 33
    ↔ Reverse comparison
  •

Rev 24 → Rev 33

/shadow_regs.cgs
0,0 → 1,205
# FRV testcase for handling of shadow registers SR0-SR4
# mach: frv
 
.include "testutils.inc"
 
start
 
.global tra
tra:
test_spr_bits 0x800,11,1,psr ; PSR.ESR set
test_spr_bits 0x4,2,1,psr ; PSR.S set
 
; Set up exception handler for later
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr7
inc_gr_immed 2112,gr7 ; address of exception handler
set_bctrlr_0_0 gr7 ; bctrlr 0,0
set_spr_immed 128,lcr
set_psr_et 1
 
set_gr_immed 0x11111111,gr4 ; SGR4-7
set_gr_immed 0x22222222,gr5
set_gr_immed 0x33333333,gr6
set_gr_immed 0x44444444,gr7
set_spr_immed 0x55555555,sr0 ; UGR4-7
set_spr_immed 0x66666666,sr1
set_spr_immed 0x77777777,sr2
set_spr_immed 0x88888888,sr3
 
and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR
test_gr_immed 0x11111111,gr4 ; SGR4-7
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
test_spr_immed 0x11111111,sr0 ; SGR4-7
test_spr_immed 0x22222222,sr1
test_spr_immed 0x33333333,sr2
test_spr_immed 0x44444444,sr3
 
set_spr_immed 0x55555555,sr0 ; SGR4-7
set_spr_immed 0x66666666,sr1
set_spr_immed 0x77777777,sr2
set_spr_immed 0x88888888,sr3
test_gr_immed 0x55555555,gr4 ; SGR4-7
test_gr_immed 0x66666666,gr5
test_gr_immed 0x77777777,gr6
test_gr_immed 0x88888888,gr7
test_spr_immed 0x55555555,sr0 ; SGR4-7
test_spr_immed 0x66666666,sr1
test_spr_immed 0x77777777,sr2
test_spr_immed 0x88888888,sr3
 
set_gr_immed 0x11111111,gr4 ; SGR4-7
set_gr_immed 0x22222222,gr5
set_gr_immed 0x33333333,gr6
set_gr_immed 0x44444444,gr7
test_gr_immed 0x11111111,gr4 ; SGR4-7
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
test_spr_immed 0x11111111,sr0 ; SGR4-7
test_spr_immed 0x22222222,sr1
test_spr_immed 0x33333333,sr2
test_spr_immed 0x44444444,sr3
 
or_spr_immed 0x00000800,psr ; turn on PSR.ESR
test_gr_immed 0x11111111,gr4 ; SGR4-7 -- SR0-3 (UGR4-7) are undefined
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
 
set_spr_immed 0x55555555,sr0 ; UGR4-7
set_spr_immed 0x66666666,sr1
set_spr_immed 0x77777777,sr2
set_spr_immed 0x88888888,sr3
test_gr_immed 0x11111111,gr4 ; SGR4-7
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
test_spr_immed 0x55555555,sr0 ; UGR4-7
test_spr_immed 0x66666666,sr1
test_spr_immed 0x77777777,sr2
test_spr_immed 0x88888888,sr3
 
and_spr_immed 0xfffffffb,psr ; turn off PSR.S
test_spr_immed 0x11111111,sr0 ; SGR4-7
test_spr_immed 0x22222222,sr1
test_spr_immed 0x33333333,sr2
test_spr_immed 0x44444444,sr3
test_gr_immed 0x55555555,gr4 ; UGR4-7
test_gr_immed 0x66666666,gr5
test_gr_immed 0x77777777,gr6
test_gr_immed 0x88888888,gr7
 
; need to generate a trap to return to supervisor mode
set_spr_addr ok0,lr
tira gr0,4 ; should branch to tbr + (128 + 4)*16
 
test_spr_bits 0x800,11,0,psr ; PSR.ESR clear
test_spr_bits 0x4,2,0,psr ; PSR.S clear
test_gr_immed 0x11111111,gr4 ; SGR4-7
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
test_spr_immed 0x11111111,sr0 ; SGR4-7
test_spr_immed 0x22222222,sr1
test_spr_immed 0x33333333,sr2
test_spr_immed 0x44444444,sr3
 
set_gr_immed 0x55555555,gr4 ; SGR4-7
set_gr_immed 0x66666666,gr5
set_gr_immed 0x77777777,gr6
set_gr_immed 0x88888888,gr7
test_gr_immed 0x55555555,gr4 ; SGR4-7
test_gr_immed 0x66666666,gr5
test_gr_immed 0x77777777,gr6
test_gr_immed 0x88888888,gr7
test_spr_immed 0x55555555,sr0 ; SGR4-7
test_spr_immed 0x66666666,sr1
test_spr_immed 0x77777777,sr2
test_spr_immed 0x88888888,sr3
 
set_gr_immed 0x11111111,gr4 ; SGR4-7
set_gr_immed 0x22222222,gr5
set_gr_immed 0x33333333,gr6
set_gr_immed 0x44444444,gr7
test_gr_immed 0x11111111,gr4 ; SGR4-7
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
test_spr_immed 0x11111111,sr0 ; SGR4-7
test_spr_immed 0x22222222,sr1
test_spr_immed 0x33333333,sr2
test_spr_immed 0x44444444,sr3
 
; need to generate a trap to return to supervisor mode
set_spr_addr ok1,lr
tira gr0,4 ; should branch to tbr + (128 + 4)*16
 
pass
 
ok0: ; exception handler should branch here the first time
test_spr_bits 0x800,11,1,psr ; PSR.ESR set
test_spr_bits 0x4,2,1,psr ; PSR.S set
test_gr_immed 0x11111111,gr4 ; SGR4-7
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
test_spr_immed 0x55555555,sr0 ; UGR4-7
test_spr_immed 0x66666666,sr1
test_spr_immed 0x77777777,sr2
test_spr_immed 0x88888888,sr3
 
and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR
test_gr_immed 0x11111111,gr4 ; SGR4-7
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
test_spr_immed 0x11111111,sr0 ; SGR4-7
test_spr_immed 0x22222222,sr1
test_spr_immed 0x33333333,sr2
test_spr_immed 0x44444444,sr3
rett 0
fail
 
ok1: ; exception handler should branch here the second time
test_spr_bits 0x800,11,0,psr ; PSR.ESR clear
test_spr_bits 0x4,2,1,psr ; PSR.S set
 
test_gr_immed 0x11111111,gr4 ; SGR4-7
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
test_spr_immed 0x11111111,sr0 ; SGR4-7
test_spr_immed 0x22222222,sr1
test_spr_immed 0x33333333,sr2
test_spr_immed 0x44444444,sr3
 
set_spr_immed 0x55555555,sr0 ; SGR4-7
set_spr_immed 0x66666666,sr1
set_spr_immed 0x77777777,sr2
set_spr_immed 0x88888888,sr3
test_gr_immed 0x55555555,gr4 ; SGR4-7
test_gr_immed 0x66666666,gr5
test_gr_immed 0x77777777,gr6
test_gr_immed 0x88888888,gr7
test_spr_immed 0x55555555,sr0 ; SGR4-7
test_spr_immed 0x66666666,sr1
test_spr_immed 0x77777777,sr2
test_spr_immed 0x88888888,sr3
 
set_gr_immed 0x11111111,gr4 ; SGR4-7
set_gr_immed 0x22222222,gr5
set_gr_immed 0x33333333,gr6
set_gr_immed 0x44444444,gr7
test_gr_immed 0x11111111,gr4 ; SGR4-7
test_gr_immed 0x22222222,gr5
test_gr_immed 0x33333333,gr6
test_gr_immed 0x44444444,gr7
test_spr_immed 0x11111111,sr0 ; SGR4-7
test_spr_immed 0x22222222,sr1
test_spr_immed 0x33333333,sr2
test_spr_immed 0x44444444,sr3
rett 0
fail
/illinsn.cgs
0,0 → 1,38
# FRV testcase
# mach: fr500 fr550 fr400
 
.include "testutils.inc"
 
start
 
.global tra
tra:
and_spr_immed 0x3fffffff,hsr0 ; no caches enabled
 
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr7
inc_gr_immed 0x070,gr7 ; address of exception handler
set_bctrlr_0_0 gr7
inc_gr_immed 0x790,gr7 ; address of exception handler
set_bctrlr_0_0 gr7
set_spr_immed 128,lcr
set_psr_et 1
set_spr_addr ok0,lr
 
set_gr_addr ill1,gr7
set_mem_immed 0x81f80000,gr7 ; unknown opcode: 7E
ill1: tira gr0,0 ; should be overridden
ill2: nop ; also illegal, but prev has priority
bad0: fail
 
; check interrupt
ok0: test_spr_addr ill1,pcsr
test_spr_immed 1,esfr1 ; esr0 active
test_spr_bits 0x3f,0,0xb,esr0
movsg psr,gr28
srli gr28,28,gr28
subicc gr28,0x3,gr0,icc3 ; is fr550?
beq icc3,0,no_epcr
test_spr_addr ill1,epcr0
no_epcr:
pass
/timer.cgs
0,0 → 1,31
# frv testcase to generate timer interrupt for st $GRk,@($GRi,$GRj)
# mach: fr500 fr550 fr400
# sim: --timer 200,14
.include "testutils.inc"
 
start
 
.global align
align:
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x2e0,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
set_spr_immed 0x7fffffff,lcr
set_spr_addr ok1,lr
and_spr_immed 0xffffff87,psr ; enable external interrupts
or_spr_immed 0x00000069,psr ; enable external interrupts
 
set_gr_immed 10,gr16
set_gr_immed 0,gr15
 
again: cmp gr15,gr16,icc0
blt icc0,0,again
pass
 
; exception handler
ok1:
inc_gr_immed 1,gr15
rett 0
fail
/reset.cgs
0,0 → 1,81
# frv testcase to generate reset interrupts
# mach: fr500 fr550 fr400
# sim: --memory-region 0xff000000,64
 
.include "testutils.inc"
 
start
 
.global reset
reset:
and_spr_immed 0xfffffffb,psr ; turn off PSR.S
set_gr_immed 0xfeff0500,gr10 ; address of reset register
set_spr_immed 0x7fffffff,lcr
set_bctrlr_0_0 gr0
 
; Can't recover from hardware interrupt with enough state intact to verify it
; set_spr_addr ok1,lr
; set_mem_immed 0x3,gr10 ; cause hardware reset
; dcf @(gr10,gr0) ; Wait for store to happen
; fail
;
;ok1: ; reset should branch to reset address which should then branch here
; test_mem_immed 0x00000200,gr10
; set_spr_addr ok2,lr
; set_mem_immed 0x2,gr10 ; cause hardware reset
; dcf @(gr10,gr0) ; Wait for store to happen
; fail
;
ok2: ; reset should branch to reset address which should then branch here
; test_mem_immed 0x00000200,gr10
set_spr_addr ok3,lr
set_mem_immed 0x1,gr10 ; cause software reset
dcf @(gr10,gr0) ; Wait for store to happen
fail
ok3: ; reset should branch to reset address which should then branch here
test_mem_immed 0x00000100,gr10
test_spr_bits 0x4,2,1,psr ; psr.s is set
test_spr_bits 0x2,1,0,psr ; psr.ps not set
set_spr_addr bad,lr
set_mem_immed 0x0,gr10 ; no reset
test_mem_immed 0x0,gr10
 
; now retest with HSR0.SA set
set_mem_immed 0,gr0
set_gr_addr 0xff000000,gr11
set_bctrlr_0_0 gr11
or_spr_immed 0x00001000,hsr0 ; set HSR0.SA
 
; Can't recover from hardware interrupt with enough state intact to verify it
; set_spr_addr ok4,lr
; dcf @(gr10,gr0) ; Wait for store to happen
; set_mem_immed 0x3,gr10 ; cause hardware reset
; fail
;
;ok4: ; reset should branch to reset address which should then branch here
; test_mem_immed 0x00000200,gr10
; set_spr_addr ok5,lr
; set_mem_immed 0x2,gr10 ; cause hardware reset
; dcf @(gr10,gr0) ; Wait for store to happen
; fail
;
ok5: ; reset should branch to reset address which should then branch here
; test_mem_immed 0x00000200,gr10
set_spr_addr ok6,lr
set_mem_immed 0x1,gr10 ; cause software reset
dcf @(gr10,gr0) ; Wait for store to happen
fail
ok6: ; reset should branch to reset address which should then branch here
test_mem_immed 0x00000100,gr10
test_spr_bits 0x4,2,1,psr ; psr.s is set
test_spr_bits 0x2,1,1,psr ; psr.ps is set
set_spr_addr bad,lr
set_mem_immed 0x0,gr10 ; no reset
test_mem_immed 0x0,gr10
 
pass
 
bad: ; Should never get here
fail
/fp_exception-fr550.cgs
0,0 → 1,185
# frv testcase to generate fp_exception
# mach: fr550
.include "testutils.inc"
 
float_constants
start
load_float_constants
 
.global align
align:
; clear the packing bit if the insn at 'pack:'. We can't simply use
; '.p' because the assembler will catch the error.
set_gr_mem pack,gr10
and_gr_immed 0x7fffffff,gr10
set_mem_gr gr10,pack
set_gr_addr pack,gr10
flush_data_cache gr10
 
; Make the the source register number odd at badst. We can't simply
; code an odd register number because the assembler will catch the
; error.
set_gr_mem badst,gr10
or_gr_immed 0x02000000,gr10
set_mem_gr gr10,badst
set_gr_addr badst,gr10
flush_data_cache gr10
 
; Make the the dest register number odd at badld. We can't simply
; code an odd register number because the assembler will catch the
; error.
set_gr_mem badld,gr10
or_gr_immed 0x02000000,gr10
set_mem_gr gr10,badld
set_gr_addr badld,gr10
flush_data_cache gr10
 
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x070,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
inc_gr_immed 0x060,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
set_spr_immed 128,lcr
set_spr_addr ok1,lr
set_psr_et 1
inc_gr_immed -4,sp ; for alignment
 
set_gr_immed 0,gr20 ; PC increment
set_gr_immed 0,gr15
 
set_spr_addr ok3,lr
set_gr_immed 4,gr20 ; PC increment
badst: stdfi fr0,@(sp,0) ; misaligned reg -- slot I0
test_gr_immed 1,gr15
 
set_spr_addr ok4,lr
set_gr_immed 8,gr20 ; PC increment
nop.p
badld: lddfi @(sp,0),fr8 ; misaligned reg -- slot I1
test_gr_immed 2,gr15
 
set_spr_addr ok5,lr
set_gr_immed 20,gr20 ; PC increment
fnegs.p fr9,fr9
fnegs.p fr9,fr10
fnegs.p fr9,fr11
pack: fnegs fr10,fr12
fnegs fr10,fr13 ; packing violation
test_gr_immed 3,gr15
 
set_spr_addr ok1,lr
set_gr_immed 4,gr20 ; PC increment
bad: .word 0x83e502c4 ; fmadds fr16,fr4,fr1 (unimplemented)
test_gr_immed 4,gr15
 
and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception
set_fr_iimmed 0x7f7f,0xffff,fr0
set_fr_iimmed 0x0000,0x0000,fr1
fdivs fr0,fr1,fr2 ; div/0 -- no exception
test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set
test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set
test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear
 
set_spr_addr ok2,lr
set_gr_immed 0,gr20 ; PC increment
or_spr_immed 0x04000000,fsr0 ; enable div/0 fp_exception
set_fr_iimmed 0xdead,0xbeef,fr2
div0: fdivs fr0,fr1,fr2 ; fp_exception - div/0
test_fr_iimmed 0xdeadbeef,fr2 ; fr2 not updated
test_gr_immed 5,gr15
 
and_spr_immed 0xfdffffff,fsr0 ; disable inexact fp_exception
fsqrts fr32,fr2 ; inexact -- no exception
test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set
test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is set
test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear
 
set_fr_fr fr2,fr3 ; sqrt 2
set_fr_iimmed 0xdead,0xbeef,fr2
set_spr_addr ok6,lr
or_spr_immed 0x02000000,fsr0 ; enable inexact fp_exception
inxt1: fsqrts fr32,fr2 ; fp_exception - inexact
test_gr_immed 6,gr15 ; handler called
test_fr_fr fr2,fr3 ; fr2 updated
 
set_fr_iimmed 0xdead,0xbeef,fr2
set_spr_addr ok7,lr
inxt2: fsqrts fr32,fr2 ; fp_exception - inexact again
test_gr_immed 7,gr15 ; handler called
test_fr_fr fr2,fr3 ; fr2 updated
 
pass
 
; exception handler 1 -- illegal_instruction: bad insn
ok1:
test_spr_immed 1,esfr1 ; esr0 active
test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set
test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set
bra ret
 
; exception handler 2 - fp_exception: divide by 0
ok2:
test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear
test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set
test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set
 
test_spr_immed 4,esfr1 ; esr2 active
test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set
test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set
test_spr_addr div0,epcr2 ; epcr2 is set
bra ret
 
; exception handler 3 - illegal_instruction: register exception
ok3:
test_spr_immed 1,esfr1 ; esr0 active
test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set
test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set
bra ret
 
; exception handler 4 - illegal_instruction: register exception
ok4:
test_spr_immed 1,esfr1 ; esr0 active
test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set
test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set
bra ret
 
; exception handler 5 - illegal_instruction: sequence violation
ok5:
test_spr_immed 1,esfr1 ; esr0 active
test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set
test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set
bra ret
 
; exception handler 6 - fp_exception: inexact
ok6:
test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear
test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set
test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set
 
test_spr_immed 4,esfr1 ; esr2 active
test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set
test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set
test_spr_addr inxt1,epcr2 ; epcr2 is set
bra ret
 
; exception handler 7 - fp_exception: inexact again
ok7:
test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear
test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set
test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set
 
test_spr_immed 4,esfr1 ; esr2 active
test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set
test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set
test_spr_addr inxt2,epcr2 ; epcr2 is set
bra ret
 
ret:
inc_gr_immed 1,gr15
movsg pcsr,gr60
add gr60,gr20,gr60
movgs gr60,pcsr
rett 0
fail
 
/compound-fr550.cgs
0,0 → 1,54
# frv testcase to generate compound exception
# mach: fr550
.include "testutils.inc"
 
start
 
.global align
align:
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x200,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
set_spr_immed 128,lcr
set_spr_addr ok1,lr
or_spr_immed 0x04000000,fsr0 ; enabled div/0 fp_exception
set_psr_et 1
 
set_gr_immed 0,gr15
set_fr_iimmed 0x7f7f,0xffff,fr0
set_fr_iimmed 0x0000,0x0000,fr1
 
and_spr_immed 0xfffffffe,isr ; enable mem_address_not_aligned
set_gr_addr dividef,gr16
set_gr_addr dividei,gr17
set_gr_immed 0xdeadbeef,gr8
inc_gr_immed 2,sp ; misalign
store: sti.p gr8,@(sp,0) ; misaligned - no exception
dividef:fdivs.p fr0,fr1,fr2 ; fp_exception
dividei:sdiv gr1,gr0,gr1 ; division exception
test_gr_immed 1,gr15
 
pass
 
; exception handler
ok1:
; check fp_exception
test_spr_immed 0x5,esfr1 ; esr2 and esr0 are active
test_spr_gr epcr2,gr16
test_spr_bits 0x0001,0,0x1,esr2 ; esr2 is valid
test_spr_bits 0x003e,1,0xd,esr2 ; esr2.ec is set
test_spr_bits 0x0800,11,0x0,esr2 ; esr2.eav is clear
 
; check on fp_exception
test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear
test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set
test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear
 
; check interrupt on dividei
test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set
 
inc_gr_immed 1,gr15
rett 0
fail
/fp_exception.cgs
0,0 → 1,209
# frv testcase to generate fp_exception
# mach: fr500
.include "testutils.inc"
 
float_constants
start
load_float_constants
 
.global align
align:
; clear the packing bit if the insn at 'pack:'. We can't simply use
; '.p' because the assembler will catch the error.
set_gr_mem pack,gr10
and_gr_immed 0x7fffffff,gr10
set_mem_gr gr10,pack
set_gr_addr pack,gr10
flush_data_cache gr10
 
; Make the the source register number odd at badst. We can't simply
; code an odd register number because the assembler will catch the
; error.
set_gr_mem badst,gr10
or_gr_immed 0x02000000,gr10
set_mem_gr gr10,badst
set_gr_addr badst,gr10
flush_data_cache gr10
 
; Make the the dest register number odd at ld. We can't simply
; code an odd register number because the assembler will catch the
; error.
set_gr_mem badld,gr10
or_gr_immed 0x02000000,gr10
set_mem_gr gr10,badld
set_gr_addr badld,gr10
flush_data_cache gr10
 
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x070,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
inc_gr_immed 0x060,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
set_spr_immed 128,lcr
set_spr_addr ok1,lr
set_psr_et 1
inc_gr_immed -4,sp ; for alignment
 
set_gr_immed 0,gr20 ; PC increment
set_gr_immed 0,gr15
 
set_spr_addr ok3,lr
badst: stdfi fr0,@(sp,0) ; misaligned reg -- slot I0
test_gr_immed 1,gr15
 
set_spr_addr ok4,lr
nop.p
badld: lddfi @(sp,0),fr8 ; misaligned reg -- slot I1
test_gr_immed 2,gr15
 
set_spr_addr ok5,lr
fnegs.p fr9,fr9
pack: fnegs fr10,fr10
fnegs fr10,fr11 ; packing violation
test_gr_immed 3,gr15
 
set_spr_addr ok1,lr
set_gr_immed 4,gr20 ; PC increment
bad: .word 0x83e502c4 ; fmadds fr16,fr4,fr1 (unimplemented)
test_gr_immed 4,gr15
 
and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception
set_fr_iimmed 0x7f7f,0xffff,fr0
set_fr_iimmed 0x0000,0x0000,fr1
fdivs fr0,fr1,fr2 ; div/0 -- no exception
test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is still set
test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set
test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear
and_spr_immed 0xffefffff,fsr0 ; Clear fsr0.qne
 
set_spr_addr ok2,lr
set_gr_immed 0,gr20 ; PC increment
or_spr_immed 0x04000000,fsr0 ; enable div/0 fp_exception
set_fr_iimmed 0xdead,0xbeef,fr2
fdivs fr0,fr1,fr2 ; fp_exception - div/0
test_fr_iimmed 0xdeadbeef,fr2 ; fr2 not updated
test_gr_immed 5,gr15
 
and_spr_immed 0xfdffffff,fsr0 ; disable inexact fp_exception
fsqrts fr32,fr2 ; inexact -- no exception
test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is still set
test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is set
test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear
 
set_fr_fr fr2,fr3 ; sqrt 2
set_fr_iimmed 0xdead,0xbeef,fr2
set_spr_addr ok6,lr
or_spr_immed 0x02000000,fsr0 ; enable inexact fp_exception
fsqrts fr32,fr2 ; fp_exception - inexact
test_gr_immed 6,gr15 ; handler called
test_fr_fr fr2,fr3 ; fr2 updated
 
set_fr_iimmed 0xdead,0xbeef,fr2
set_spr_addr ok7,lr
fsqrts fr32,fr2 ; fp_exception - inexact again
test_gr_immed 7,gr15 ; handler called
test_fr_fr fr2,fr3 ; fr2 updated
 
pass
 
; exception handler 1 -- bad insn
ok1:
test_spr_immed 1,esfr1 ; esr0 active
test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set
test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set
test_spr_addr bad,epcr0
bra ret
 
; exception handler 2 - fp_exception: divide by 0
ok2:
test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set
test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set
test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set
 
test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set
test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set
test_spr_bits 0x380,7,0x1,fqst2 ; fq2.ftt is set
test_spr_bits 0x7e,1,0x4,fqst2 ; fq2.cexc is set
test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set
test_spr_immed 0x85e40241,fqop2 ; fq2.opc
bra ret
 
; exception handler 3 - fp_exception: register exception
ok3:
test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set
test_spr_bits 0xe0000,17,0x6,fsr0 ; fsr0.ftt is set
test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear
 
test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set
test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set
test_spr_bits 0x380,7,0x6,fqst2 ; fq2.ftt is set
test_spr_bits 0x7e,1,0x0,fqst2 ; fq2.cexc is set
test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set
test_spr_immed 0x83581000,fqop2 ; fq2.opc
bra ret
 
; exception handler 4 - fp_exception: another register exception
ok4:
test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set
test_spr_bits 0xe0000,17,0x6,fsr0 ; fsr0.ftt is set
test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is still clear
 
test_spr_bits 0x80000000,31,0x0,fqst3 ; fq3.miv is set
test_spr_bits 0x18000,15,0x0,fqst3 ; fq3.sie is set
test_spr_bits 0x380,7,0x6,fqst3 ; fq3.ftt is set
test_spr_bits 0x7e,1,0x0,fqst3 ; fq3.cexc is set
test_spr_bits 0x1,0,0x1,fqst3 ; fq3.valid is set
test_spr_immed 0x92ec1000,fqop3 ; fq3.opc
bra ret
 
; exception handler 5 - fp_exception: sequence violation
ok5:
test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set
test_spr_bits 0xe0000,17,0x4,fsr0 ; fsr0.ftt is set
test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is still clear
 
test_spr_bits 0x80000000,31,0x0,fqst3 ; fq3.miv is set
test_spr_bits 0x18000,15,0x0,fqst3 ; fq3.sie is set
test_spr_bits 0x380,7,0x4,fqst3 ; fq3.ftt is set
test_spr_bits 0x7e,1,0x0,fqst3 ; fq3.cexc is set
test_spr_bits 0x1,0,0x1,fqst3 ; fq3.valid is set
test_spr_immed 0x97e400ca,fqop3 ; fq3.opc
bra ret
 
; exception handler 6 - fp_exception: inexact
ok6:
test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set
test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set
test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set
 
test_spr_bits 0x80000000,31,0x0,fqst0 ; fq0.miv is set
test_spr_bits 0x18000,15,0x0,fqst0 ; fq0.sie is set
test_spr_bits 0x380,7,0x1,fqst0 ; fq0.ftt is set
test_spr_bits 0x7e,1,0x2,fqst0 ; fq0.cexc is set
test_spr_bits 0x1,0,0x1,fqst0 ; fq0.valid is set
test_spr_immed 0x85e40160,fqop0 ; fq0.opc
bra ret
 
; exception handler 7 - fp_exception: inexact again
ok7:
test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set
test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set
test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set
 
test_spr_bits 0x80000000,31,0x0,fqst1 ; fq1.miv is set
test_spr_bits 0x18000,15,0x0,fqst1 ; fq1.sie is set
test_spr_bits 0x380,7,0x1,fqst1 ; fq1.ftt is set
test_spr_bits 0x7e,1,0x2,fqst1 ; fq1.cexc is set
test_spr_bits 0x1,0,0x1,fqst1 ; fq1.valid is set
test_spr_immed 0x85e40160,fqop1 ; fq1.opc
bra ret
 
ret:
inc_gr_immed 1,gr15
movsg pcsr,gr60
add gr60,gr20,gr60
movgs gr60,pcsr
rett 0
fail
 
/compound.cgs
0,0 → 1,66
# frv testcase to generate compound exception
# mach: fr500 frv
.include "testutils.inc"
 
start
 
.global align
align:
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x200,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
set_spr_immed 128,lcr
set_spr_addr ok1,lr
or_spr_immed 0x04000000,fsr0 ; enabled div/0 fp_exception
set_psr_et 1
 
set_gr_immed 0,gr15
set_fr_iimmed 0x7f7f,0xffff,fr0
set_fr_iimmed 0x0000,0x0000,fr1
 
and_spr_immed 0xfffffffe,isr ; enable mem_address_not_aligned
set_gr_addr store,gr16
set_gr_addr dividei,gr17
set_gr_immed 0xdeadbeef,gr8
inc_gr_immed 2,sp ; misalign
store: sti.p gr8,@(sp,0) ; misaligned write
dividef:fdivs.p fr0,fr1,fr2 ; fp_exception
dividei:sdiv gr1,gr0,gr1 ; division exception
test_gr_immed 1,gr15
 
pass
 
; exception handler
ok1:
; check interrupt on store
test_spr_immed 0x102,esfr1 ; esr8 and esr1 are active
test_spr_gr epcr8,gr16
test_spr_bits 0x0001,0,0x1,esr8 ; esr8 is valid
test_spr_bits 0x003e,1,0xb,esr8 ; esr8.ec is set
test_spr_bits 0x0800,11,0x1,esr8 ; esr8.eav is set
test_spr_gr ear8,sp
test_spr_bits 0x01000,12,0x1,esr8 ; esr8.edv is set
test_spr_bits 0x1e000,13,0x3,esr8 ; esr8.edn is 3
test_spr_gr edr3,gr8 ; edr3 is set
 
; check on fp_exception
test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set
test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set
test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear
 
test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set
test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set
test_spr_bits 0x380,7,0x1,fqst2 ; fq2.ftt is set
test_spr_bits 0x7e,1,0x4,fqst2 ; fq2.cexc is set
test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set
test_spr_immed 0x05e40241,fqop2 ; fq2.opc
 
; check interrupt on dividei
test_spr_gr epcr1,gr17
test_spr_bits 0x0001,0,0x1,esr1 ; esr1 is valid
test_spr_bits 0x003e,1,0x13,esr1 ; esr1.ec is set
 
inc_gr_immed 1,gr15
rett 0
fail
/regalign.cgs
0,0 → 1,130
# frv testcase to generate interrupts for bad register alignment
# mach: frv
.include "testutils.inc"
 
start
 
.global align
align:
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x080,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
inc_gr_immed 0x050,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
set_spr_immed 128,lcr
set_spr_addr ok1,lr
set_psr_et 1
 
; Make the the register number odd at bad[1-4], bad9 and bada.
; We can't simply code an odd register number because the assembler
; will catch the error.
set_gr_mem bad1,gr10
or_gr_immed 0x02000000,gr10
set_mem_gr gr10,bad1
set_gr_addr bad1,gr10
flush_data_cache gr10
set_gr_mem bad2,gr10
or_gr_immed 0x02000000,gr10
set_mem_gr gr10,bad2
set_gr_addr bad2,gr10
flush_data_cache gr10
set_gr_mem bad3,gr10
or_gr_immed 0x02000000,gr10
set_mem_gr gr10,bad3
set_gr_addr bad3,gr10
flush_data_cache gr10
set_gr_mem bad4,gr10
or_gr_immed 0x02000000,gr10
set_mem_gr gr10,bad4
set_gr_addr bad4,gr10
flush_data_cache gr10
set_gr_mem bad9,gr10
or_gr_immed 0x02000000,gr10
set_mem_gr gr10,bad9
set_gr_addr bad9,gr10
flush_data_cache gr10
set_gr_mem bada,gr10
or_gr_immed 0x02000000,gr10
set_mem_gr gr10,bada
set_gr_addr bada,gr10
flush_data_cache gr10
 
set_gr_immed 4,gr20 ; PC increment
set_gr_immed 0,gr15
inc_gr_immed -12,sp ; for memory alignment
 
set_gr_addr bad1,gr17
bad1: stdi gr0,@(sp,0) ; misaligned reg
test_gr_immed 1,gr15
 
set_gr_addr bad2,gr17
bad2: lddi @(sp,0),gr8 ; misaligned reg
test_gr_immed 2,gr15
 
set_gr_addr bad3,gr17
bad3: stdc cpr0,@(sp,gr0) ; misaligned reg
test_gr_immed 3,gr15
 
set_gr_addr bad4,gr17
bad4: lddc @(sp,gr0),cpr8 ; misaligned reg
test_gr_immed 4,gr15
 
set_gr_addr bad5,gr17
bad5: stqi gr2,@(sp,0) ; misaligned reg
test_gr_immed 5,gr15
 
set_gr_addr bad6,gr17
bad6: ldqi @(sp,0),gr10 ; misaligned reg
test_gr_immed 6,gr15
 
set_gr_addr bad7,gr17
bad7: stqc cpr2,@(sp,gr0) ; misaligned reg
test_gr_immed 7,gr15
 
set_gr_addr bad8,gr17
bad8: ldqc @(sp,gr0),cpr10 ; misaligned reg
test_gr_immed 8,gr15
 
set_gr_immed 0,gr20 ; PC increment
set_gr_addr bad9,gr17
bad9: stdfi fr0,@(sp,0) ; misaligned reg
test_gr_immed 9,gr15
 
set_gr_addr bada,gr17
bada: lddfi @(sp,0),fr8 ; misaligned reg
test_gr_immed 10,gr15
 
set_gr_addr badb,gr17
badb: stqfi fr2,@(sp,0) ; misaligned reg
test_gr_immed 11,gr15
 
set_gr_addr badc,gr17
badc: ldqfi @(sp,0),fr10 ; misaligned reg
test_gr_immed 12,gr15
 
pass
 
; exception handler
ok1:
cmpi gr20,0,icc0
beq icc0,0,float
 
; check register_exception
test_spr_immed 0x1,esfr1 ; esr0 is active
test_spr_gr epcr0,gr17
test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
test_spr_bits 0x003e,1,0xc,esr0 ; esr0.ec is set
test_spr_bits 0x00c0,6,0x1,esr0 ; esr0.rec is set
test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set
movsg pcsr,gr60
add gr60,gr20,gr60
movgs gr60,pcsr
bra ret
float:
; check fp_exception
test_spr_immed 0,esfr1 ; no esr's active
ret:
inc_gr_immed 1,gr15
rett 0
fail
/mp_exception.cgs
0,0 → 1,289
# frv testcase for mp_exception
# mach: fr500 fr550 frv
# xerror:
 
# This program no longer assembles because the assembler
# now detects the unaligned registers. For this reason
# this test is now marked as "xerror" and prints the
# expected message "fail"
 
.include "testutils.inc"
 
start
 
.global mp_exception
mpx:
.if 1
fail
.else
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mcmpsh fr10,fr11,fcc1 ; mp_exception: cr-not-aligned
test_spr_bits 0x7000,12,3,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf is set
 
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mcmpsh.p fr10,fr11,fcc0 ; no exception
mcmpsh fr10,fr11,fcc2 ; no exception
test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
 
mmulhs.p fr10,fr11,acc3 ; no exception
mmulhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned
test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
 
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mmulhu fr10,fr11,acc0 ; no exception
test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
 
set_spr_immed 0,msr0
set_spr_immed 0,msr1
mmulxhs.p fr10,fr11,acc3 ; no exception
mmulxhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned
test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
 
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mmulxhu fr10,fr11,acc0 ; no exception
test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
 
set_spr_immed 0,msr0
set_spr_immed 0,msr1
mmachs.p fr10,fr11,acc3 ; no exception
mmachs fr10,fr11,acc1 ; mp_exception: acc-not-aligned
test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
 
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mmachu fr10,fr11,acc0 ; no exception
test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
 
set_spr_immed 0,msr0
set_spr_immed 0,msr1
mqaddhss.p fr10,fr12,fr17 ; mp_exception: register-not-aligned
mqaddhss fr10,fr12,fr14 ; no exception
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
 
set_spr_immed 0,msr0
set_spr_immed 0,msr1
mqaddhss.p fr10,fr12,fr14 ; no exception
mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
 
set_spr_immed 0,msr0
set_spr_immed 0,msr1
mqaddhss.p fr19,fr12,fr14 ; mp_exception: register-not-aligned
mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
 
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqaddhss fr10,fr12,fr14 ; no exception
test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
 
set_spr_immed 0,msr0
set_spr_immed 0,msr1
mqmulhs.p fr10,fr11,acc3 ; no exception
mqmulhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned
test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
 
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqmulhu fr10,fr11,acc0 ; mp_exception: register_not_aligned
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
 
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqmulhu fr10,fr12,acc0 ; no exception
test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
 
set_spr_immed 0,msr0
set_spr_immed 0,msr1
mqmulxhs.p fr10,fr11,acc3 ; no exception
mqmulxhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned
test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
 
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqmulxhu fr10,fr11,acc0 ; mp_exception: register-not-aligned
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
 
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqmulxhu fr10,fr12,acc0 ; no exception
test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
 
set_spr_immed 0,msr0
set_spr_immed 0,msr1
mqmachs.p fr10,fr12,acc3 ; no exception
mqmachs fr10,fr12,acc2 ; mp_exception: acc-not-aligned
test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
 
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned
mqmachu fr10,fr12,acc0 ; no exception
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
 
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqmachu.p fr10,fr12,acc0 ; no exception
mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
 
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned
mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
 
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqmachu fr10,fr12,acc0 ; no exception
test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
 
set_spr_immed 0,msr0
set_spr_immed 0,msr1
mqcpxrs.p fr10,fr12,acc0 ; no exception
mqcpxrs fr10,fr12,acc1 ; mp_exception: acc-not-aligned
test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
 
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned
mqcpxru fr10,fr12,acc0 ; no exception
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
 
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqcpxru.p fr10,fr12,acc0 ; no exception
mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
 
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned
mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned
test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
 
or_spr_immed 2,msr0 ; Set msr0.ovf
or_spr_immed 2,msr1 ; Set msr1.ovf
and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
mqcpxru fr10,fr12,acc0 ; no exception
test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
 
pass
.endif
/privileged_instruction.cgs
0,0 → 1,54
# frv testcase to generate privileged_instruction interrupt
# mach: frv
 
.include "testutils.inc"
 
start
 
.global dsr
dsr:
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x060,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
set_spr_immed 128,lcr
set_psr_et 1
and_spr_immed 0xfffffffb,psr ; clear psr.s
 
set_spr_addr handler,lr
set_gr_immed 0,gr16
 
set_gr_addr bad1,gr17
bad1: rett 0 ; cause interrupt
test_gr_immed 1,gr16
set_gr_addr bad2,gr17
bad2: rei 0 ; cause interrupt
test_gr_immed 2,gr16
set_gr_addr bad3,gr17
bad3: witlb gr0,@(gr0,gr0) ; cause interrupt
test_gr_immed 3,gr16
set_gr_addr bad4,gr17
bad4: wdtlb gr0,@(gr0,gr0) ; cause interrupt
test_gr_immed 4,gr16
set_gr_addr bad5,gr17
bad5: itlbi @(gr0,gr0) ; cause interrupt
test_gr_immed 5,gr16
set_gr_addr bad6,gr17
bad6: dtlbi @(gr0,gr0) ; cause interrupt
test_gr_immed 6,gr16
 
pass
handler:
; check interrupts
test_spr_immed 0x1,esfr1 ; esr0 is active
test_spr_gr epcr0,gr17
test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
test_spr_bits 0x003e,1,0x4,esr0 ; esr0.ec is set
test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set
 
addi gr16,1,gr16
movsg pcsr,gr8
addi gr8,4,gr8
movgs gr8,pcsr
rett 0
fail
/data_store_error-fr550.cgs
0,0 → 1,53
# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj)
# mach: fr550
# sim(fr550): --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0010
.include "testutils.inc"
 
start
 
.global dsr
dsr:
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x140,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
set_spr_immed 128,lcr
set_psr_et 1
 
set_spr_addr ok0,lr
set_gr_immed 0,gr16
 
set_gr_immed 0xdeadbeef,gr15
set_gr_addr 0xfeff0600,gr17
bad1: sti gr15,@(gr17,0) ; no interrupt
test_gr_immed 0,gr16
 
set_gr_immed 0xbeefdead,gr15
set_gr_addr 0xfeff7ffc,gr17
bad2: sti gr15,@(gr17,0) ; no interrupt
test_gr_immed 0,gr16
 
set_gr_immed 0xbeefbeef,gr15
set_gr_addr 0xfe800000,gr17
bad3: sti gr15,@(gr17,0) ; cause interrupt
test_gr_immed 1,gr16
 
set_gr_immed 0xdeaddead,gr15
set_gr_addr 0xfefefffc,gr17
bad4: sti gr15,@(gr17,0) ; cause interrupt
test_gr_immed 2,gr16
 
sti gr0,@(sp,0) ; no interrupt
test_gr_immed 2,gr16
 
pass
ok0:
; check interrupts
test_spr_immed 0x4000,esfr1 ; esr14 is active
test_spr_bits 0x0001,0,0x1,esr14 ; esr14 is valid
test_spr_bits 0x003e,1,0x0,esr14 ; esr14.ec is set
test_spr_bits 0x0800,11,0x0,esr14 ; esr14.eav is not set
 
addi gr16,1,gr16
rett 0
fail
/data_store_error.cgs
0,0 → 1,53
# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj)
# mach: fr500
# sim(fr500): --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0010
.include "testutils.inc"
 
start
 
.global dsr
dsr:
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x140,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
set_spr_immed 128,lcr
set_psr_et 1
 
set_spr_addr ok0,lr
set_gr_immed 0,gr16
 
set_gr_immed 0xdeadbeef,gr15
set_gr_addr 0xfeff0600,gr17
bad1: sti gr15,@(gr17,0) ; cause interrupt
test_gr_immed 1,gr16
 
set_gr_immed 0xbeefdead,gr15
set_gr_addr 0xfeff7ffc,gr17
bad2: sti gr15,@(gr17,0) ; cause interrupt
test_gr_immed 2,gr16
 
set_gr_immed 0xbeefbeef,gr15
set_gr_addr 0xfe800000,gr17
bad3: sti gr15,@(gr17,0) ; cause interrupt
test_gr_immed 3,gr16
 
set_gr_immed 0xdeaddead,gr15
set_gr_addr 0xfefefffc,gr17
bad4: sti gr15,@(gr17,0) ; cause interrupt
test_gr_immed 4,gr16
 
sti gr0,@(sp,0) ; no interrupt
test_gr_immed 4,gr16
 
pass
ok0:
; check interrupts
test_spr_immed 0x4000,esfr1 ; esr14 is active
test_spr_bits 0x0001,0,0x1,esr14 ; esr14 is valid
test_spr_bits 0x003e,1,0x0,esr14 ; esr14.ec is set
test_spr_bits 0x0800,11,0x0,esr14 ; esr14.eav is not set
 
addi gr16,1,gr16
rett 0
fail
/Ipipe-fr400.cgs
0,0 → 1,35
# frv testcase
# mach: fr400
 
.include "testutils.inc"
 
start
 
.global Ipipe
Ipipe:
; Clear the packing bit of the insn at 'pack:'. We can't
; simply use '.p' because the assembler will catch the error.
set_gr_mem pack,gr10
and_gr_immed 0x7fffffff,gr10
set_mem_gr gr10,pack
set_gr_addr pack,gr10
flush_data_cache gr10
 
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr7
inc_gr_immed 0x070,gr7 ; address of exception handler
set_bctrlr_0_0 gr7
set_spr_immed 128,lcr
set_spr_addr ok0,lr
set_psr_et 1
 
bundle: add.p gr1,gr1,gr1
pack: add gr2,gr2,gr2
bad: add gr3,gr3,gr3
fail
ok0:
test_spr_immed 1,esfr1
test_spr_bits 0x3f,0,0xb,esr0
test_spr_addr bundle,epcr0
 
pass
/badalign-fr550.cgs
0,0 → 1,42
# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj)
# mach: fr550
.include "testutils.inc"
 
start
 
.global align
align:
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x100,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
set_spr_immed 128,lcr
set_psr_et 1
set_gr_immed 0xdeadbeef,gr17
set_gr_immed 0,gr15
inc_gr_immed 2,sp ; out of alignment
 
test_spr_bits 1,0,0,isr ; ISR.EMAM always clear (not used)
sti gr17,@(sp,0) ; no exception
sti gr17,@(sp,4) ; no exception
ldi @(sp,0),gr18 ; stored at unaligned address
test_gr_immed 0xdeadbeef,gr18
ldi @(sp,0),gr19 ; no exception
test_gr_immed 0xdeadbeef,gr19
 
and_spr_immed 0xfffffffe,isr ; turn off ISR.EMAM
sti gr17,@(sp,0) ; misaligned -- no exception
test_gr_immed 0,gr15
 
set_gr_gr sp,gr20
set_gr_immed 1,gr21
set_gr_immed 0x10101010,gr10
nop.p
ldu @(sp,gr21),gr10 ; misaligned read no exception
test_gr_immed 0,gr15 ; handler was not called
test_gr_immed 0xadbeefde,gr10 ; gr10 updated
test_gr_immed 1,gr21 ; gr21 not updated
inc_gr_immed 1,gr20
test_gr_gr gr20,sp ; sp updated
 
pass
/insn_access_error-fr550.cgs
0,0 → 1,44
# frv testcase to generate insn_access_error interrupt
# mach: fr550
# sim: --memory-region 0xfe800000,0x7f0500 --memory-region 0xfeff0540,0xfb00
.include "testutils.inc"
 
start
 
.global dsr
dsr:
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x020,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
set_spr_immed 128,lcr
set_psr_et 1
 
set_spr_addr handler,lr
set_gr_immed 0,gr16
 
set_gr_addr ok0,gr8
set_gr_addr 0xfe800000,gr17
jmpl @(gr17,gr0) ; cause interrupt
ok0:
test_gr_immed 1,gr16
 
set_gr_addr ok1,gr8
set_gr_addr 0xfefffffc,gr17
jmpl @(gr17,gr0) ; cause interrupt
ok1:
test_gr_immed 2,gr16
 
pass
handler:
; check interrupts
test_spr_immed 0x1,esfr1 ; esr0 is active
; test_spr_gr epcr0,gr17 ; epcr0 is not used
test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
test_spr_bits 0x003e,1,0x2,esr0 ; esr0.ec is set
test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set
 
addi gr16,1,gr16
movgs gr8,pcsr
rett 0
fail
/Ipipe-fr500.cgs
0,0 → 1,35
# frv testcase
# mach: fr500
 
.include "testutils.inc"
 
start
 
.global Ipipe
Ipipe:
; Clear the packing bit of the insn at 'pack:'. We can't
; simply use '.p' because the assembler will catch the error.
set_gr_mem pack,gr10
and_gr_immed 0x7fffffff,gr10
set_mem_gr gr10,pack
set_gr_addr pack,gr10
flush_data_cache gr10
 
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr7
inc_gr_immed 0x070,gr7 ; address of exception handler
set_bctrlr_0_0 gr7
set_spr_immed 128,lcr
set_spr_addr ok0,lr
set_psr_et 1
 
add.p gr1,gr1,gr1
pack: add gr2,gr2,gr2
bad: add gr3,gr3,gr3
fail
ok0:
test_spr_immed 1,esfr1
test_spr_bits 0x3f,0,0xb,esr0
test_spr_addr bad,epcr0
 
pass
/insn_access_error.cgs
0,0 → 1,56
# frv testcase to generate insn_access_error interrupt
# mach: fr500 fr400
# sim: --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0040
.include "testutils.inc"
 
start
 
.global dsr
dsr:
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x020,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
set_spr_immed 128,lcr
set_psr_et 1
 
set_spr_addr handler,lr
set_gr_immed 0,gr16
 
set_gr_addr ok0,gr8
set_gr_addr 0xfeff0600,gr17
jmpl @(gr17,gr0) ; cause interrupt
ok0:
test_gr_immed 1,gr16
 
set_gr_addr ok1,gr8
set_gr_addr 0xfeff7ffc,gr17
jmpl @(gr17,gr0) ; cause interrupt
ok1:
test_gr_immed 2,gr16
 
set_gr_addr ok2,gr8
set_gr_addr 0xfe800000,gr17
jmpl @(gr17,gr0) ; cause interrupt
ok2:
test_gr_immed 3,gr16
 
set_gr_addr ok3,gr8
set_gr_addr 0xfefefffc,gr17
jmpl @(gr17,gr0) ; cause interrupt
ok3:
test_gr_immed 4,gr16
 
pass
handler:
; check interrupts
test_spr_immed 0x1,esfr1 ; esr0 is active
test_spr_gr epcr0,gr17
test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
test_spr_bits 0x003e,1,0x2,esr0 ; esr0.ec is set
test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set
 
addi gr16,1,gr16
movgs gr8,pcsr
rett 0
fail
/badalign.cgs
0,0 → 1,73
# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj)
# mach: fr500 frv
.include "testutils.inc"
 
start
 
.global align
align:
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x100,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
set_spr_immed 128,lcr
set_spr_addr ok1,lr
set_psr_et 1
set_gr_immed 0xdeadbeef,gr17
set_gr_immed 0,gr15
inc_gr_immed 2,sp ; out of alignment
 
test_spr_bits 1,0,1,isr ; mem_address_not_aligned is masked
sti gr17,@(sp,0) ; no exception
ldi @(sp,-2),gr18 ; stored at aligned address
test_gr_immed 0xdeadbeef,gr18
ldi @(sp,0),gr19 ; no exception
test_gr_immed 0xdeadbeef,gr19
 
and_spr_immed 0xfffffffe,isr ; turn off ISR.EMAM
set_gr_addr bad1,gr16
bad1: sti gr17,@(sp,0) ; misaligned write in slot I1
test_gr_immed 1,gr15
 
set_gr_addr bad3,gr16
set_gr_gr sp,gr20
set_gr_immed 1,gr21
set_gr_immed 0x10101010,gr10
bad2: nop.p
bad3: ldu @(sp,gr21),gr10 ; misaligned read in slot I2
test_gr_immed 2,gr15 ; handler was called
test_gr_immed 0x10101010,gr10 ; gr10 not updated
test_gr_immed 1,gr21 ; gr21 not updated
inc_gr_immed 1,gr20
test_gr_gr gr20,sp ; sp updated
 
pass
 
; exception handler
ok1:
cmpi gr15,0,icc0
bne icc0,0,load
; handle interrupt on store
test_spr_immed 0x100,esfr1 ; esr8 is active
test_spr_gr epcr8,gr16
test_spr_bits 0x0001,0,0x1,esr8 ; esr8 is valid
test_spr_bits 0x003e,1,0xb,esr8 ; esr8.ec is set
test_spr_bits 0x0800,11,0x1,esr8 ; esr8.eav is set
test_spr_gr ear8,sp
test_spr_bits 0x01000,12,0x1,esr8 ; esr8.edv is set
test_spr_bits 0x1e000,13,0x3,esr8 ; esr8.edn is 3
test_spr_gr edr3,gr17 ; edr3 is set
bra ret
load:
; handle interrupt on load
test_spr_immed 0x200,esfr1 ; esr9 is active
test_spr_gr epcr9,gr16
test_spr_bits 0x0001,0,0x1,esr9 ; esr9 is valid
test_spr_bits 0x003e,1,0xb,esr9 ; esr9.ec is set
test_spr_bits 0x0800,11,0x1,esr9 ; esr9.eav is set
test_spr_gr ear9,sp
test_spr_bits 0x1000,12,0x0,esr9 ; esr9.edv is not set
ret:
inc_gr_immed 1,gr15
rett 0
fail

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