URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/tags/gdb/gdb-6.8/gdb-6.8.openrisc-2.1/sim/v850
- from Rev 24 to Rev 33
- ↔ Reverse comparison
Rev 24 → Rev 33
/sim-main.h
0,0 → 1,390
#ifndef SIM_MAIN_H |
#define SIM_MAIN_H |
|
/* General config options */ |
|
#define WITH_CORE |
#define WITH_MODULO_MEMORY 1 |
#define WITH_WATCHPOINTS 1 |
|
|
/* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */ |
|
#define WITH_TARGET_WORD_MSB 31 |
|
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#include "sim-basics.h" |
#include "sim-signal.h" |
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typedef address_word sim_cia; |
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#include "sim-base.h" |
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#include "simops.h" |
#include "bfd.h" |
|
|
typedef signed8 int8; |
typedef unsigned8 uint8; |
typedef signed16 int16; |
typedef unsigned16 uint16; |
typedef signed32 int32; |
typedef unsigned32 uint32; |
typedef unsigned32 reg_t; |
|
|
/* The current state of the processor; registers, memory, etc. */ |
|
typedef struct _v850_regs { |
reg_t regs[32]; /* general-purpose registers */ |
reg_t sregs[32]; /* system registers, including psw */ |
reg_t pc; |
int dummy_mem; /* where invalid accesses go */ |
} v850_regs; |
|
struct _sim_cpu |
{ |
/* ... simulator specific members ... */ |
v850_regs reg; |
reg_t psw_mask; /* only allow non-reserved bits to be set */ |
sim_event *pending_nmi; |
/* ... base type ... */ |
sim_cpu_base base; |
}; |
|
#define CIA_GET(CPU) ((CPU)->reg.pc + 0) |
#define CIA_SET(CPU,VAL) ((CPU)->reg.pc = (VAL)) |
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struct sim_state { |
sim_cpu cpu[MAX_NR_PROCESSORS]; |
#if (WITH_SMP) |
#define STATE_CPU(sd,n) (&(sd)->cpu[n]) |
#else |
#define STATE_CPU(sd,n) (&(sd)->cpu[0]) |
#endif |
#if 0 |
SIM_ADDR rom_size; |
SIM_ADDR low_end; |
SIM_ADDR high_start; |
SIM_ADDR high_base; |
void *mem; |
#endif |
sim_state_base base; |
}; |
|
/* For compatibility, until all functions converted to passing |
SIM_DESC as an argument */ |
extern SIM_DESC simulator; |
|
|
#define V850_ROM_SIZE 0x8000 |
#define V850_LOW_END 0x200000 |
#define V850_HIGH_START 0xffe000 |
|
|
/* Because we are still using the old semantic table, provide compat |
macro's that store the instruction where the old simops expects |
it. */ |
|
extern uint32 OP[4]; |
#if 0 |
OP[0] = inst & 0x1f; /* RRRRR -> reg1 */ |
OP[1] = (inst >> 11) & 0x1f; /* rrrrr -> reg2 */ |
OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */ |
OP[3] = inst; |
#endif |
|
#define SAVE_1 \ |
PC = cia; \ |
OP[0] = instruction_0 & 0x1f; \ |
OP[1] = (instruction_0 >> 11) & 0x1f; \ |
OP[2] = 0; \ |
OP[3] = instruction_0 |
|
#define COMPAT_1(CALL) \ |
SAVE_1; \ |
PC += (CALL); \ |
nia = PC |
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#define SAVE_2 \ |
PC = cia; \ |
OP[0] = instruction_0 & 0x1f; \ |
OP[1] = (instruction_0 >> 11) & 0x1f; \ |
OP[2] = instruction_1; \ |
OP[3] = (instruction_1 << 16) | instruction_0 |
|
#define COMPAT_2(CALL) \ |
SAVE_2; \ |
PC += (CALL); \ |
nia = PC |
|
|
/* new */ |
#define GR ((CPU)->reg.regs) |
#define SR ((CPU)->reg.sregs) |
|
/* old */ |
#define State (STATE_CPU (simulator, 0)->reg) |
#define PC (State.pc) |
#define SP (State.regs[3]) |
#define EP (State.regs[30]) |
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#define EIPC (State.sregs[0]) |
#define EIPSW (State.sregs[1]) |
#define FEPC (State.sregs[2]) |
#define FEPSW (State.sregs[3]) |
#define ECR (State.sregs[4]) |
#define PSW (State.sregs[5]) |
#define CTPC (SR[16]) |
#define CTPSW (SR[17]) |
#define DBPC (State.sregs[18]) |
#define DBPSW (State.sregs[19]) |
#define CTBP (State.sregs[20]) |
|
#define PSW_US BIT32 (8) |
#define PSW_NP 0x80 |
#define PSW_EP 0x40 |
#define PSW_ID 0x20 |
#define PSW_SAT 0x10 |
#define PSW_CY 0x8 |
#define PSW_OV 0x4 |
#define PSW_S 0x2 |
#define PSW_Z 0x1 |
|
#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4) |
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/* sign-extend a 4-bit number */ |
#define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8) |
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/* sign-extend a 5-bit number */ |
#define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10) |
|
/* sign-extend a 9-bit number */ |
#define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100) |
|
/* sign-extend a 22-bit number */ |
#define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000) |
|
/* sign extend a 40 bit number */ |
#define SEXT40(x) ((((x) & UNSIGNED64 (0xffffffffff)) \ |
^ (~UNSIGNED64 (0x7fffffffff))) \ |
+ UNSIGNED64 (0x8000000000)) |
|
/* sign extend a 44 bit number */ |
#define SEXT44(x) ((((x) & UNSIGNED64 (0xfffffffffff)) \ |
^ (~ UNSIGNED64 (0x7ffffffffff))) \ |
+ UNSIGNED64 (0x80000000000)) |
|
/* sign extend a 60 bit number */ |
#define SEXT60(x) ((((x) & UNSIGNED64 (0xfffffffffffffff)) \ |
^ (~ UNSIGNED64 (0x7ffffffffffffff))) \ |
+ UNSIGNED64 (0x800000000000000)) |
|
/* No sign extension */ |
#define NOP(x) (x) |
|
#define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i)) |
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#define RLW(x) load_mem (x, 4) |
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/* Function declarations. */ |
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#define IMEM16(EA) \ |
sim_core_read_aligned_2 (CPU, PC, exec_map, (EA)) |
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#define IMEM16_IMMED(EA,N) \ |
sim_core_read_aligned_2 (STATE_CPU (sd, 0), \ |
PC, exec_map, (EA) + (N) * 2) |
|
#define load_mem(ADDR,LEN) \ |
sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \ |
PC, read_map, (ADDR)) |
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#define store_mem(ADDR,LEN,DATA) \ |
sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \ |
PC, write_map, (ADDR), (DATA)) |
|
|
/* compare cccc field against PSW */ |
int condition_met (unsigned code); |
|
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/* Debug/tracing calls */ |
|
enum op_types |
{ |
OP_UNKNOWN, |
OP_NONE, |
OP_TRAP, |
OP_REG, |
OP_REG_REG, |
OP_REG_REG_CMP, |
OP_REG_REG_MOVE, |
OP_IMM_REG, |
OP_IMM_REG_CMP, |
OP_IMM_REG_MOVE, |
OP_COND_BR, |
OP_LOAD16, |
OP_STORE16, |
OP_LOAD32, |
OP_STORE32, |
OP_JUMP, |
OP_IMM_REG_REG, |
OP_UIMM_REG_REG, |
OP_IMM16_REG_REG, |
OP_UIMM16_REG_REG, |
OP_BIT, |
OP_EX1, |
OP_EX2, |
OP_LDSR, |
OP_STSR, |
OP_BIT_CHANGE, |
OP_REG_REG_REG, |
OP_REG_REG3, |
OP_IMM_REG_REG_REG, |
OP_PUSHPOP1, |
OP_PUSHPOP2, |
OP_PUSHPOP3, |
}; |
|
#ifdef DEBUG |
void trace_input PARAMS ((char *name, enum op_types type, int size)); |
void trace_output PARAMS ((enum op_types result)); |
void trace_result PARAMS ((int has_result, unsigned32 result)); |
|
extern int trace_num_values; |
extern unsigned32 trace_values[]; |
extern unsigned32 trace_pc; |
extern const char *trace_name; |
extern int trace_module; |
|
#define TRACE_BRANCH0() \ |
do { \ |
if (TRACE_BRANCH_P (CPU)) { \ |
trace_module = TRACE_BRANCH_IDX; \ |
trace_pc = cia; \ |
trace_name = itable[MY_INDEX].name; \ |
trace_num_values = 0; \ |
trace_result (1, (nia)); \ |
} \ |
} while (0) |
|
#define TRACE_BRANCH1(IN1) \ |
do { \ |
if (TRACE_BRANCH_P (CPU)) { \ |
trace_module = TRACE_BRANCH_IDX; \ |
trace_pc = cia; \ |
trace_name = itable[MY_INDEX].name; \ |
trace_values[0] = (IN1); \ |
trace_num_values = 1; \ |
trace_result (1, (nia)); \ |
} \ |
} while (0) |
|
#define TRACE_BRANCH2(IN1, IN2) \ |
do { \ |
if (TRACE_BRANCH_P (CPU)) { \ |
trace_module = TRACE_BRANCH_IDX; \ |
trace_pc = cia; \ |
trace_name = itable[MY_INDEX].name; \ |
trace_values[0] = (IN1); \ |
trace_values[1] = (IN2); \ |
trace_num_values = 2; \ |
trace_result (1, (nia)); \ |
} \ |
} while (0) |
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#define TRACE_BRANCH3(IN1, IN2, IN3) \ |
do { \ |
if (TRACE_BRANCH_P (CPU)) { \ |
trace_module = TRACE_BRANCH_IDX; \ |
trace_pc = cia; \ |
trace_name = itable[MY_INDEX].name; \ |
trace_values[0] = (IN1); \ |
trace_values[1] = (IN2); \ |
trace_values[2] = (IN3); \ |
trace_num_values = 3; \ |
trace_result (1, (nia)); \ |
} \ |
} while (0) |
|
#define TRACE_LD(ADDR,RESULT) \ |
do { \ |
if (TRACE_MEMORY_P (CPU)) { \ |
trace_module = TRACE_MEMORY_IDX; \ |
trace_pc = cia; \ |
trace_name = itable[MY_INDEX].name; \ |
trace_values[0] = (ADDR); \ |
trace_num_values = 1; \ |
trace_result (1, (RESULT)); \ |
} \ |
} while (0) |
|
#define TRACE_LD_NAME(NAME, ADDR,RESULT) \ |
do { \ |
if (TRACE_MEMORY_P (CPU)) { \ |
trace_module = TRACE_MEMORY_IDX; \ |
trace_pc = cia; \ |
trace_name = (NAME); \ |
trace_values[0] = (ADDR); \ |
trace_num_values = 1; \ |
trace_result (1, (RESULT)); \ |
} \ |
} while (0) |
|
#define TRACE_ST(ADDR,RESULT) \ |
do { \ |
if (TRACE_MEMORY_P (CPU)) { \ |
trace_module = TRACE_MEMORY_IDX; \ |
trace_pc = cia; \ |
trace_name = itable[MY_INDEX].name; \ |
trace_values[0] = (ADDR); \ |
trace_num_values = 1; \ |
trace_result (1, (RESULT)); \ |
} \ |
} while (0) |
|
#else |
#define trace_input(NAME, IN1, IN2) |
#define trace_output(RESULT) |
#define trace_result(HAS_RESULT, RESULT) |
|
#define TRACE_ALU_INPUT0() |
#define TRACE_ALU_INPUT1(IN0) |
#define TRACE_ALU_INPUT2(IN0, IN1) |
#define TRACE_ALU_INPUT2(IN0, IN1) |
#define TRACE_ALU_INPUT2(IN0, IN1 INS2) |
#define TRACE_ALU_RESULT(RESULT) |
|
#define TRACE_BRANCH0() |
#define TRACE_BRANCH1(IN1) |
#define TRACE_BRANCH2(IN1, IN2) |
#define TRACE_BRANCH2(IN1, IN2, IN3) |
|
#define TRACE_LD(ADDR,RESULT) |
#define TRACE_ST(ADDR,RESULT) |
|
#endif |
|
#define GPR_SET(N, VAL) (State.regs[(N)] = (VAL)) |
#define GPR_CLEAR(N) (State.regs[(N)] = 0) |
|
extern void divun ( unsigned int N, |
unsigned long int als, |
unsigned long int sfi, |
unsigned32 /*unsigned long int*/ * quotient_ptr, |
unsigned32 /*unsigned long int*/ * remainder_ptr, |
int *overflow_ptr |
); |
extern void divn ( unsigned int N, |
unsigned long int als, |
unsigned long int sfi, |
signed32 /*signed long int*/ * quotient_ptr, |
signed32 /*signed long int*/ * remainder_ptr, |
int *overflow_ptr |
); |
extern int type1_regs[]; |
extern int type2_regs[]; |
extern int type3_regs[]; |
|
#endif |
sim-main.h
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: simops.h
===================================================================
--- simops.h (nonexistent)
+++ simops.h (revision 33)
@@ -0,0 +1,78 @@
+#ifndef SIMOPS_H
+#define SIMOPS_H
+int OP_380 (void);
+int OP_480 (void);
+int OP_501 (void);
+int OP_700 (void);
+int OP_720 (void);
+int OP_10720 (void);
+int OP_740 (void);
+int OP_760 (void);
+int OP_10760 (void);
+int OP_1C0 (void);
+int OP_240 (void);
+int OP_600 (void);
+int OP_1A0 (void);
+int OP_180 (void);
+int OP_E0 (void);
+int OP_2E0 (void);
+int OP_6E0 (void);
+int OP_1E0 (void);
+int OP_260 (void);
+int OP_7E0 (void);
+int OP_C0 (void);
+int OP_220 (void);
+int OP_A0 (void);
+int OP_660 (void);
+int OP_80 (void);
+int OP_160 (void);
+int OP_200 (void);
+int OP_640 (void);
+int OP_2A0 (void);
+int OP_A007E0 (void);
+int OP_2C0 (void);
+int OP_C007E0 (void);
+int OP_280 (void);
+int OP_8007E0 (void);
+int OP_100 (void);
+int OP_680 (void);
+int OP_140 (void);
+int OP_6C0 (void);
+int OP_120 (void);
+int OP_6A0 (void);
+int OP_20 (void);
+int OP_7C0 (void);
+int OP_47C0 (void);
+int OP_87C0 (void);
+int OP_C7C0 (void);
+int OP_16007E0 (void);
+int OP_16087E0 (void);
+int OP_12007E0 (void);
+int OP_10007E0 (void);
+int OP_E607E0 (void);
+int OP_22207E0 (void);
+int OP_E407E0 (void);
+int OP_E207E0 (void);
+int OP_E007E0 (void);
+int OP_20007E0 (void);
+int OP_1C207E0 (void);
+int OP_1C007E0 (void);
+int OP_18207E0 (void);
+int OP_18007E0 (void);
+int OP_2C207E0 (void);
+int OP_2C007E0 (void);
+int OP_28207E0 (void);
+int OP_28007E0 (void);
+int OP_24207E0 (void);
+int OP_24007E0 (void);
+int OP_107E0 (void);
+int OP_10780 (void);
+int OP_1B0780 (void);
+int OP_130780 (void);
+int OP_B0780 (void);
+int OP_30780 (void);
+int OP_22007E0 (void);
+int OP_307F0 (void);
+int OP_107F0 (void);
+int OP_307E0 (void);
+#endif
simops.h
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: v850_sim.h
===================================================================
--- v850_sim.h (nonexistent)
+++ v850_sim.h (revision 33)
@@ -0,0 +1,8 @@
+struct simops
+{
+ unsigned long opcode;
+ unsigned long mask;
+ int (* func) PARAMS ((void));
+ int numops;
+ int operands[12];
+};
v850_sim.h
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: interp.c
===================================================================
--- interp.c (nonexistent)
+++ interp.c (revision 33)
@@ -0,0 +1,350 @@
+#include "sim-main.h"
+#include "sim-options.h"
+#include "v850_sim.h"
+#include "sim-assert.h"
+#include "itable.h"
+
+#ifdef HAVE_STDLIB_H
+#include
+#endif
+
+#ifdef HAVE_STRING_H
+#include
+#else
+#ifdef HAVE_STRINGS_H
+#include
+#endif
+#endif
+
+#include "bfd.h"
+
+#ifndef INLINE
+#ifdef __GNUC__
+#define INLINE inline
+#else
+#define INLINE
+#endif
+#endif
+
+static const char * get_insn_name (sim_cpu *, int);
+
+/* For compatibility */
+SIM_DESC simulator;
+
+
+
+/* v850 interrupt model */
+
+enum interrupt_type
+{
+ int_reset,
+ int_nmi,
+ int_intov1,
+ int_intp10,
+ int_intp11,
+ int_intp12,
+ int_intp13,
+ int_intcm4,
+ num_int_types
+};
+
+char *interrupt_names[] = {
+ "reset",
+ "nmi",
+ "intov1",
+ "intp10",
+ "intp11",
+ "intp12",
+ "intp13",
+ "intcm4",
+ NULL
+};
+
+static void
+do_interrupt (sd, data)
+ SIM_DESC sd;
+ void *data;
+{
+ char **interrupt_name = (char**)data;
+ enum interrupt_type inttype;
+ inttype = (interrupt_name - STATE_WATCHPOINTS (sd)->interrupt_names);
+
+ /* For a hardware reset, drop everything and jump to the start
+ address */
+ if (inttype == int_reset)
+ {
+ PC = 0;
+ PSW = 0x20;
+ ECR = 0;
+ sim_engine_restart (sd, NULL, NULL, NULL_CIA);
+ }
+
+ /* Deliver an NMI when allowed */
+ if (inttype == int_nmi)
+ {
+ if (PSW & PSW_NP)
+ {
+ /* We're already working on an NMI, so this one must wait
+ around until the previous one is done. The processor
+ ignores subsequent NMIs, so we don't need to count them.
+ Just keep re-scheduling a single NMI until it manages to
+ be delivered */
+ if (STATE_CPU (sd, 0)->pending_nmi != NULL)
+ sim_events_deschedule (sd, STATE_CPU (sd, 0)->pending_nmi);
+ STATE_CPU (sd, 0)->pending_nmi =
+ sim_events_schedule (sd, 1, do_interrupt, data);
+ return;
+ }
+ else
+ {
+ /* NMI can be delivered. Do not deschedule pending_nmi as
+ that, if still in the event queue, is a second NMI that
+ needs to be delivered later. */
+ FEPC = PC;
+ FEPSW = PSW;
+ /* Set the FECC part of the ECR. */
+ ECR &= 0x0000ffff;
+ ECR |= 0x10;
+ PSW |= PSW_NP;
+ PSW &= ~PSW_EP;
+ PSW |= PSW_ID;
+ PC = 0x10;
+ sim_engine_restart (sd, NULL, NULL, NULL_CIA);
+ }
+ }
+
+ /* deliver maskable interrupt when allowed */
+ if (inttype > int_nmi && inttype < num_int_types)
+ {
+ if ((PSW & PSW_NP) || (PSW & PSW_ID))
+ {
+ /* Can't deliver this interrupt, reschedule it for later */
+ sim_events_schedule (sd, 1, do_interrupt, data);
+ return;
+ }
+ else
+ {
+ /* save context */
+ EIPC = PC;
+ EIPSW = PSW;
+ /* Disable further interrupts. */
+ PSW |= PSW_ID;
+ /* Indicate that we're doing interrupt not exception processing. */
+ PSW &= ~PSW_EP;
+ /* Clear the EICC part of the ECR, will set below. */
+ ECR &= 0xffff0000;
+ switch (inttype)
+ {
+ case int_intov1:
+ PC = 0x80;
+ ECR |= 0x80;
+ break;
+ case int_intp10:
+ PC = 0x90;
+ ECR |= 0x90;
+ break;
+ case int_intp11:
+ PC = 0xa0;
+ ECR |= 0xa0;
+ break;
+ case int_intp12:
+ PC = 0xb0;
+ ECR |= 0xb0;
+ break;
+ case int_intp13:
+ PC = 0xc0;
+ ECR |= 0xc0;
+ break;
+ case int_intcm4:
+ PC = 0xd0;
+ ECR |= 0xd0;
+ break;
+ default:
+ /* Should never be possible. */
+ sim_engine_abort (sd, NULL, NULL_CIA,
+ "do_interrupt - internal error - bad switch");
+ break;
+ }
+ }
+ sim_engine_restart (sd, NULL, NULL, NULL_CIA);
+ }
+
+ /* some other interrupt? */
+ sim_engine_abort (sd, NULL, NULL_CIA,
+ "do_interrupt - internal error - interrupt %d unknown",
+ inttype);
+}
+
+/* Return name of an insn, used by insn profiling. */
+
+static const char *
+get_insn_name (sim_cpu *cpu, int i)
+{
+ return itable[i].name;
+}
+
+/* These default values correspond to expected usage for the chip. */
+
+uint32 OP[4];
+
+
+SIM_DESC
+sim_open (kind, cb, abfd, argv)
+ SIM_OPEN_KIND kind;
+ host_callback *cb;
+ struct bfd *abfd;
+ char **argv;
+{
+ SIM_DESC sd = sim_state_alloc (kind, cb);
+ int mach;
+
+ SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
+
+ /* for compatibility */
+ simulator = sd;
+
+ /* FIXME: should be better way of setting up interrupts */
+ STATE_WATCHPOINTS (sd)->pc = &(PC);
+ STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
+ STATE_WATCHPOINTS (sd)->interrupt_handler = do_interrupt;
+ STATE_WATCHPOINTS (sd)->interrupt_names = interrupt_names;
+
+ /* Initialize the mechanism for doing insn profiling. */
+ CPU_INSN_NAME (STATE_CPU (sd, 0)) = get_insn_name;
+ CPU_MAX_INSNS (STATE_CPU (sd, 0)) = nr_itable_entries;
+
+ if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
+ return 0;
+
+ /* Allocate core managed memory */
+
+ /* "Mirror" the ROM addresses below 1MB. */
+ sim_do_commandf (sd, "memory region 0,0x100000,0x%lx", V850_ROM_SIZE);
+ /* Chunk of ram adjacent to rom */
+ sim_do_commandf (sd, "memory region 0x100000,0x%lx", V850_LOW_END-0x100000);
+ /* peripheral I/O region - mirror 1K across 4k (0x1000) */
+ sim_do_command (sd, "memory region 0xfff000,0x1000,1024");
+ /* similarly if in the internal RAM region */
+ sim_do_command (sd, "memory region 0xffe000,0x1000,1024");
+
+ /* getopt will print the error message so we just have to exit if this fails.
+ FIXME: Hmmm... in the case of gdb we need getopt to call
+ print_filtered. */
+ if (sim_parse_args (sd, argv) != SIM_RC_OK)
+ {
+ /* Uninstall the modules to avoid memory leaks,
+ file descriptor leaks, etc. */
+ sim_module_uninstall (sd);
+ return 0;
+ }
+
+ /* check for/establish the a reference program image */
+ if (sim_analyze_program (sd,
+ (STATE_PROG_ARGV (sd) != NULL
+ ? *STATE_PROG_ARGV (sd)
+ : NULL),
+ abfd) != SIM_RC_OK)
+ {
+ sim_module_uninstall (sd);
+ return 0;
+ }
+
+ /* establish any remaining configuration options */
+ if (sim_config (sd) != SIM_RC_OK)
+ {
+ sim_module_uninstall (sd);
+ return 0;
+ }
+
+ if (sim_post_argv_init (sd) != SIM_RC_OK)
+ {
+ /* Uninstall the modules to avoid memory leaks,
+ file descriptor leaks, etc. */
+ sim_module_uninstall (sd);
+ return 0;
+ }
+
+
+ /* determine the machine type */
+ if (STATE_ARCHITECTURE (sd) != NULL
+ && STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850)
+ mach = STATE_ARCHITECTURE (sd)->mach;
+ else
+ mach = bfd_mach_v850; /* default */
+
+ /* set machine specific configuration */
+ switch (mach)
+ {
+ case bfd_mach_v850:
+ case bfd_mach_v850e:
+ case bfd_mach_v850e1:
+ STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT
+ | PSW_CY | PSW_OV | PSW_S | PSW_Z);
+ break;
+ }
+
+ return sd;
+}
+
+
+void
+sim_close (sd, quitting)
+ SIM_DESC sd;
+ int quitting;
+{
+ sim_module_uninstall (sd);
+}
+
+SIM_RC
+sim_create_inferior (sd, prog_bfd, argv, env)
+ SIM_DESC sd;
+ struct bfd *prog_bfd;
+ char **argv;
+ char **env;
+{
+ memset (&State, 0, sizeof (State));
+ if (prog_bfd != NULL)
+ PC = bfd_get_start_address (prog_bfd);
+ return SIM_RC_OK;
+}
+
+int
+sim_fetch_register (sd, rn, memory, length)
+ SIM_DESC sd;
+ int rn;
+ unsigned char *memory;
+ int length;
+{
+ *(unsigned32*)memory = H2T_4 (State.regs[rn]);
+ return -1;
+}
+
+int
+sim_store_register (sd, rn, memory, length)
+ SIM_DESC sd;
+ int rn;
+ unsigned char *memory;
+ int length;
+{
+ State.regs[rn] = T2H_4 (*(unsigned32*)memory);
+ return -1;
+}
+
+void
+sim_do_command (sd, cmd)
+ SIM_DESC sd;
+ char *cmd;
+{
+ char *mm_cmd = "memory-map";
+ char *int_cmd = "interrupt";
+
+ if (sim_args_command (sd, cmd) != SIM_RC_OK)
+ {
+ if (strncmp (cmd, mm_cmd, strlen (mm_cmd) == 0))
+ sim_io_eprintf (sd, "`memory-map' command replaced by `sim memory'\n");
+ else if (strncmp (cmd, int_cmd, strlen (int_cmd)) == 0)
+ sim_io_eprintf (sd, "`interrupt' command replaced by `sim watch'\n");
+ else
+ sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
+ }
+}
interp.c
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: configure.ac
===================================================================
--- configure.ac (nonexistent)
+++ configure.ac (revision 33)
@@ -0,0 +1,22 @@
+dnl Process this file with autoconf to produce a configure script.
+AC_PREREQ(2.59)dnl
+AC_INIT(Makefile.in)
+AC_CONFIG_HEADER(config.h:config.in)
+
+sinclude(../common/aclocal.m4)
+
+# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around
+# it by inlining the macro's contents.
+sinclude(../common/common.m4)
+
+SIM_AC_OPTION_ENDIAN(LITTLE_ENDIAN)
+SIM_AC_OPTION_ALIGNMENT(,NONSTRICT_ALIGNMENT)
+SIM_AC_OPTION_HOSTENDIAN
+SIM_AC_OPTION_WARNINGS
+SIM_AC_OPTION_RESERVED_BITS
+SIM_AC_OPTION_BITSIZE(32,31)
+
+AC_CHECK_FUNCS(time chmod utime fork execve execv chown)
+AC_CHECK_HEADERS(unistd.h stdlib.h string.h strings.h utime.h time.h)
+
+SIM_AC_OUTPUT
configure.ac
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: v850.igen
===================================================================
--- v850.igen (nonexistent)
+++ v850.igen (revision 33)
@@ -0,0 +1,1205 @@
+:option:::insn-bit-size:16
+:option:::hi-bit-nr:15
+
+
+:option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
+:option:::format-names:XI,XII,XIII
+:option:::format-names:XIV,XV
+:option:::format-names:Z
+
+
+:model:::v850:v850:
+
+:option:::multi-sim:true
+:model:::v850e:v850e:
+:option:::multi-sim:true
+:model:::v850e1:v850e1:
+
+// Cache macros
+
+:cache:::unsigned:reg1:RRRRR:(RRRRR)
+:cache:::unsigned:reg2:rrrrr:(rrrrr)
+:cache:::unsigned:reg3:wwwww:(wwwww)
+
+:cache:::unsigned:disp4:dddd:(dddd)
+:cache:::unsigned:disp5:dddd:(dddd << 1)
+:cache:::unsigned:disp7:ddddddd:ddddddd
+:cache:::unsigned:disp8:ddddddd:(ddddddd << 1)
+:cache:::unsigned:disp8:dddddd:(dddddd << 2)
+:cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
+:cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
+:cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
+:cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)
+
+:cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
+:cache:::unsigned:imm6:iiiiii:iiiiii
+:cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
+:cache:::unsigned:imm5:iiii:(32 - (iiii << 1))
+:cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
+:cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
+:cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
+:cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
+
+:cache:::unsigned:vector:iiiii:iiiii
+
+:cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
+:cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
+
+:cache:::unsigned:bit3:bbb:bbb
+
+
+// What do we do with an illegal instruction?
+:internal::::illegal:
+{
+ sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
+ (unsigned long) cia);
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+}
+
+
+
+// Add
+
+rrrrr,001110,RRRRR:I:::add
+"add r, r"
+{
+ COMPAT_1 (OP_1C0 ());
+}
+
+rrrrr,010010,iiiii:II:::add
+"add ,r"
+{
+ COMPAT_1 (OP_240 ());
+}
+
+
+
+// ADDI
+rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
+"addi , r, r"
+{
+ COMPAT_2 (OP_600 ());
+}
+
+
+
+// AND
+rrrrr,001010,RRRRR:I:::and
+"and r, r"
+{
+ COMPAT_1 (OP_140 ());
+}
+
+
+
+// ANDI
+rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
+"andi , r, r"
+{
+ COMPAT_2 (OP_6C0 ());
+}
+
+
+
+// Map condition code to a string
+:%s::::cccc:int cccc
+{
+ switch (cccc)
+ {
+ case 0xf: return "gt";
+ case 0xe: return "ge";
+ case 0x6: return "lt";
+
+ case 0x7: return "le";
+
+ case 0xb: return "h";
+ case 0x9: return "nl";
+ case 0x1: return "l";
+
+ case 0x3: return "nh";
+
+ case 0x2: return "e";
+
+ case 0xa: return "ne";
+
+ case 0x0: return "v";
+ case 0x8: return "nv";
+ case 0x4: return "n";
+ case 0xc: return "p";
+ /* case 0x1: return "c"; */
+ /* case 0x9: return "nc"; */
+ /* case 0x2: return "z"; */
+ /* case 0xa: return "nz"; */
+ case 0x5: return "r"; /* always */
+ case 0xd: return "sa";
+ }
+ return "(null)";
+}
+
+
+// Bcond
+ddddd,1011,ddd,cccc:III:::Bcond
+"b%s "
+{
+ int cond;
+ if ((ddddd == 0x00) && (ddd == 0x00) && (cccc == 0x05)) {
+ // Special case - treat "br *" like illegal instruction
+ sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
+ } else {
+ cond = condition_met (cccc);
+ if (cond)
+ nia = cia + disp9;
+ TRACE_BRANCH1 (cond);
+ }
+}
+
+
+
+// BSH
+rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
+*v850e
+*v850e1
+"bsh r, r"
+{
+ unsigned32 value;
+ TRACE_ALU_INPUT1 (GR[reg2]);
+
+ value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
+ | MOVED32 (GR[reg2], 31, 24, 23, 16)
+ | MOVED32 (GR[reg2], 7, 0, 15, 8)
+ | MOVED32 (GR[reg2], 15, 8, 7, 0));
+
+ GR[reg3] = value;
+ PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
+ if ((value & 0xffff) == 0) PSW |= PSW_Z;
+ if (value & 0x80000000) PSW |= PSW_S;
+ if (((value & 0xff) == 0) || ((value & 0xff00) == 0)) PSW |= PSW_CY;
+
+ TRACE_ALU_RESULT (GR[reg3]);
+}
+
+// BSW
+rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
+*v850e
+*v850e1
+"bsw r, r"
+{
+#define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
+ unsigned32 value;
+ TRACE_ALU_INPUT1 (GR[reg2]);
+
+ value = GR[reg2];
+ value >>= 24;
+ value |= (GR[reg2] << 24);
+ value |= ((GR[reg2] << 8) & 0x00ff0000);
+ value |= ((GR[reg2] >> 8) & 0x0000ff00);
+ GR[reg3] = value;
+
+ PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
+
+ if (value == 0) PSW |= PSW_Z;
+ if (value & 0x80000000) PSW |= PSW_S;
+ if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
+
+ TRACE_ALU_RESULT (GR[reg3]);
+}
+
+// CALLT
+0000001000,iiiiii:II:::callt
+*v850e
+*v850e1
+"callt "
+{
+ unsigned32 adr;
+ unsigned32 off;
+ CTPC = cia + 2;
+ CTPSW = PSW;
+ adr = (CTBP & ~1) + (imm6 << 1);
+ off = load_mem (adr, 2) & ~1; /* Force alignment */
+ nia = (CTBP & ~1) + off;
+ TRACE_BRANCH3 (adr, CTBP, off);
+}
+
+
+// CLR1
+10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
+"clr1 , [r]"
+{
+ COMPAT_2 (OP_87C0 ());
+}
+
+rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
+*v850e
+*v850e1
+"clr1 r, [r]"
+{
+ COMPAT_2 (OP_E407E0 ());
+}
+
+
+// CTRET
+0000011111100000 + 0000000101000100:X:::ctret
+*v850e
+*v850e1
+"ctret"
+{
+ nia = (CTPC & ~1);
+ PSW = (CTPSW & (CPU)->psw_mask);
+ TRACE_BRANCH1 (PSW);
+}
+
+// CMOV
+rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
+*v850e
+*v850e1
+"cmov %s, r, r, r"
+{
+ int cond = condition_met (cccc);
+ TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
+ GR[reg3] = cond ? GR[reg1] : GR[reg2];
+ TRACE_ALU_RESULT (GR[reg3]);
+}
+
+rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
+*v850e
+*v850e1
+"cmov %s, , r, r"
+{
+ int cond = condition_met (cccc);
+ TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]);
+ GR[reg3] = cond ? imm5 : GR[reg2];
+ TRACE_ALU_RESULT (GR[reg3]);
+}
+
+// CMP
+rrrrr,001111,RRRRR:I:::cmp
+"cmp r, r"
+{
+ COMPAT_1 (OP_1E0 ());
+}
+
+rrrrr,010011,iiiii:II:::cmp
+"cmp , r"
+{
+ COMPAT_1 (OP_260 ());
+}
+
+
+
+// DI
+0000011111100000 + 0000000101100000:X:::di
+"di"
+{
+ COMPAT_2 (OP_16007E0 ());
+}
+
+
+
+// DISPOSE
+// 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
+// "dispose , "
+0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
+*v850e
+*v850e1
+"dispose , ":RRRRR == 0
+"dispose , , [reg1]"
+{
+ int i;
+ SAVE_2;
+
+ trace_input ("dispose", OP_PUSHPOP1, 0);
+
+ SP += (OP[3] & 0x3e) << 1;
+
+ /* Load the registers with lower number registers being retrieved
+ from higher addresses. */
+ for (i = 12; i--;)
+ if ((OP[3] & (1 << type1_regs[ i ])))
+ {
+ State.regs[ 20 + i ] = load_mem (SP, 4);
+ SP += 4;
+ }
+
+ if ((OP[3] & 0x1f0000) != 0)
+ {
+ nia = State.regs[ (OP[3] >> 16) & 0x1f];
+ }
+
+ trace_output (OP_PUSHPOP1);
+}
+
+
+// DIV
+rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
+*v850e
+*v850e1
+"div r, r, r"
+{
+ COMPAT_2 (OP_2C007E0 ());
+}
+
+
+// DIVH
+rrrrr!0,000010,RRRRR!0:I:::divh
+"divh r, r"
+{
+ unsigned32 ov, s, z;
+ signed long int op0, op1, result;
+
+ trace_input ("divh", OP_REG_REG, 0);
+
+ PC = cia;
+ OP[0] = instruction_0 & 0x1f;
+ OP[1] = (instruction_0 >> 11) & 0x1f;
+
+ /* Compute the result. */
+ op0 = EXTEND16 (State.regs[OP[0]]);
+ op1 = State.regs[OP[1]];
+
+ if (op0 == -1 && op1 == 0x80000000)
+ {
+ PSW &= ~PSW_Z;
+ PSW |= PSW_OV | PSW_S;
+ State.regs[OP[1]] = 0x80000000;
+ }
+ else if (op0 == 0)
+ {
+ PSW |= PSW_OV;
+ }
+ else
+ {
+ result = (signed32) op1 / op0;
+ ov = 0;
+
+ /* Compute the condition codes. */
+ z = (result == 0);
+ s = (result & 0x80000000);
+
+ /* Store the result and condition codes. */
+ State.regs[OP[1]] = result;
+ PSW &= ~(PSW_Z | PSW_S | PSW_OV);
+ PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0));
+ }
+
+ trace_output (OP_REG_REG);
+
+ PC += 2;
+ nia = PC;
+}
+
+rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
+*v850e
+*v850e1
+"divh r, r, r"
+{
+ COMPAT_2 (OP_28007E0 ());
+}
+
+
+// DIVHU
+rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
+*v850e
+*v850e1
+"divhu r, r, r"
+{
+ COMPAT_2 (OP_28207E0 ());
+}
+
+
+// DIVU
+rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
+*v850e
+*v850e1
+"divu r, r, r"
+{
+ COMPAT_2 (OP_2C207E0 ());
+}
+
+
+// EI
+1000011111100000 + 0000000101100000:X:::ei
+"ei"
+{
+ COMPAT_2 (OP_16087E0 ());
+}
+
+
+
+// HALT
+0000011111100000 + 0000000100100000:X:::halt
+"halt"
+{
+ COMPAT_2 (OP_12007E0 ());
+}
+
+
+
+// HSW
+rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
+*v850e
+*v850e1
+"hsw r, r"
+{
+ unsigned32 value;
+ TRACE_ALU_INPUT1 (GR[reg2]);
+
+ value = GR[reg2];
+ value >>= 16;
+ value |= (GR[reg2] << 16);
+
+ GR[reg3] = value;
+
+ PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
+
+ if (value == 0) PSW |= PSW_Z;
+ if (value & 0x80000000) PSW |= PSW_S;
+ if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
+
+ TRACE_ALU_RESULT (GR[reg3]);
+}
+
+
+
+// JARL
+rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
+"jarl , r"
+{
+ GR[reg2] = nia;
+ nia = cia + disp22;
+ TRACE_BRANCH1 (GR[reg2]);
+}
+
+
+
+// JMP
+00000000011,RRRRR:I:::jmp
+"jmp [r]"
+{
+ nia = GR[reg1] & ~1;
+ TRACE_BRANCH0 ();
+}
+
+
+
+// JR
+0000011110,dddddd + ddddddddddddddd,0:V:::jr
+"jr "
+{
+ nia = cia + disp22;
+ TRACE_BRANCH0 ();
+}
+
+
+
+// LD
+rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
+"ld.b [r], r"
+{
+ COMPAT_2 (OP_700 ());
+}
+
+rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
+"ld.h [r], r"
+{
+ COMPAT_2 (OP_720 ());
+}
+
+rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
+"ld.w [r], r"
+{
+ COMPAT_2 (OP_10720 ());
+}
+
+rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
+*v850e
+*v850e1
+"ld.bu [r], r"
+{
+ COMPAT_2 (OP_10780 ());
+}
+
+rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
+*v850e
+*v850e1
+"ld.hu [r], r"
+{
+ COMPAT_2 (OP_107E0 ());
+}
+
+
+// LDSR
+regID,111111,RRRRR + 0000000000100000:IX:::ldsr
+"ldsr r, s"
+{
+ TRACE_ALU_INPUT1 (GR[reg1]);
+
+ if (&PSW == &SR[regID])
+ PSW = (GR[reg1] & (CPU)->psw_mask);
+ else
+ SR[regID] = GR[reg1];
+
+ TRACE_ALU_RESULT (SR[regID]);
+}
+
+
+
+// MOV
+rrrrr!0,000000,RRRRR:I:::mov
+"mov r, r"
+{
+ TRACE_ALU_INPUT0 ();
+ GR[reg2] = GR[reg1];
+ TRACE_ALU_RESULT (GR[reg2]);
+}
+
+
+rrrrr!0,010000,iiiii:II:::mov
+"mov , r"
+{
+ COMPAT_1 (OP_200 ());
+}
+
+00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
+*v850e
+*v850e1
+"mov , r"
+{
+ SAVE_2;
+ trace_input ("mov", OP_IMM_REG, 4);
+ State.regs[ OP[0] ] = load_mem (PC + 2, 4);
+ trace_output (OP_IMM_REG);
+}
+
+
+
+// MOVEA
+rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
+"movea , r, r"
+{
+ TRACE_ALU_INPUT2 (GR[reg1], simm16);
+ GR[reg2] = GR[reg1] + simm16;
+ TRACE_ALU_RESULT (GR[reg2]);
+}
+
+
+
+// MOVHI
+rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
+"movhi , r, r"
+{
+ COMPAT_2 (OP_640 ());
+}
+
+
+
+// MUL
+rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
+*v850e
+*v850e1
+"mul r, r, r"
+{
+ COMPAT_2 (OP_22007E0 ());
+}
+
+rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
+*v850e
+*v850e1
+"mul , r, r"
+{
+ COMPAT_2 (OP_24007E0 ());
+}
+
+
+// MULH
+rrrrr!0,000111,RRRRR:I:::mulh
+"mulh r, r"
+{
+ COMPAT_1 (OP_E0 ());
+}
+
+rrrrr!0,010111,iiiii:II:::mulh
+"mulh , r"
+{
+ COMPAT_1 (OP_2E0 ());
+}
+
+
+
+// MULHI
+rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
+"mulhi , r, r"
+{
+ COMPAT_2 (OP_6E0 ());
+}
+
+
+
+// MULU
+rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
+*v850e
+*v850e1
+"mulu r, r, r"
+{
+ COMPAT_2 (OP_22207E0 ());
+}
+
+rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
+*v850e
+*v850e1
+"mulu , r, r"
+{
+ COMPAT_2 (OP_24207E0 ());
+}
+
+
+
+// NOP
+0000000000000000:I:::nop
+"nop"
+{
+ /* do nothing, trace nothing */
+}
+
+
+
+// NOT
+rrrrr,000001,RRRRR:I:::not
+"not r, r"
+{
+ COMPAT_1 (OP_20 ());
+}
+
+
+
+// NOT1
+01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
+"not1 , [r]"
+{
+ COMPAT_2 (OP_47C0 ());
+}
+
+rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
+*v850e
+*v850e1
+"not1 r, r"
+{
+ COMPAT_2 (OP_E207E0 ());
+}
+
+
+
+// OR
+rrrrr,001000,RRRRR:I:::or
+"or r, r"
+{
+ COMPAT_1 (OP_100 ());
+}
+
+
+
+// ORI
+rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
+"ori , r, r"
+{
+ COMPAT_2 (OP_680 ());
+}
+
+
+
+// PREPARE
+0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
+*v850e
+*v850e1
+"prepare , "
+{
+ int i;
+ SAVE_2;
+
+ trace_input ("prepare", OP_PUSHPOP1, 0);
+
+ /* Store the registers with lower number registers being placed at
+ higher addresses. */
+ for (i = 0; i < 12; i++)
+ if ((OP[3] & (1 << type1_regs[ i ])))
+ {
+ SP -= 4;
+ store_mem (SP, 4, State.regs[ 20 + i ]);
+ }
+
+ SP -= (OP[3] & 0x3e) << 1;
+
+ trace_output (OP_PUSHPOP1);
+}
+
+
+0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
+*v850e
+*v850e1
+"prepare , , sp"
+{
+ COMPAT_2 (OP_30780 ());
+}
+
+0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
+*v850e
+*v850e1
+"prepare , , "
+{
+ COMPAT_2 (OP_B0780 ());
+}
+
+0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
+*v850e
+*v850e1
+"prepare , , "
+{
+ COMPAT_2 (OP_130780 ());
+}
+
+0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
+*v850e
+*v850e1
+"prepare , , "
+{
+ COMPAT_2 (OP_1B0780 ());
+}
+
+
+
+// RETI
+0000011111100000 + 0000000101000000:X:::reti
+"reti"
+{
+ if ((PSW & PSW_EP))
+ {
+ nia = (EIPC & ~1);
+ PSW = EIPSW;
+ }
+ else if ((PSW & PSW_NP))
+ {
+ nia = (FEPC & ~1);
+ PSW = FEPSW;
+ }
+ else
+ {
+ nia = (EIPC & ~1);
+ PSW = EIPSW;
+ }
+ TRACE_BRANCH1 (PSW);
+}
+
+
+
+// SAR
+rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
+"sar r, r"
+{
+ COMPAT_2 (OP_A007E0 ());
+}
+
+rrrrr,010101,iiiii:II:::sar
+"sar , r"
+{
+ COMPAT_1 (OP_2A0 ());
+}
+
+
+
+// SASF
+rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
+*v850e
+*v850e1
+"sasf %s, r"
+{
+ COMPAT_2 (OP_20007E0 ());
+}
+
+
+
+
+// SATADD
+rrrrr!0,000110,RRRRR:I:::satadd
+"satadd r, r"
+{
+ COMPAT_1 (OP_C0 ());
+}
+
+rrrrr!0,010001,iiiii:II:::satadd
+"satadd , r"
+{
+ COMPAT_1 (OP_220 ());
+}
+
+
+
+// SATSUB
+rrrrr!0,000101,RRRRR:I:::satsub
+"satsub r, r"
+{
+ COMPAT_1 (OP_A0 ());
+}
+
+
+
+// SATSUBI
+rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
+"satsubi , r, r"
+{
+ COMPAT_2 (OP_660 ());
+}
+
+
+
+// SATSUBR
+rrrrr!0,000100,RRRRR:I:::satsubr
+"satsubr r, r"
+{
+ COMPAT_1 (OP_80 ());
+}
+
+
+
+// SETF
+rrrrr,1111110,cccc + 0000000000000000:IX:::setf
+"setf %s, r"
+{
+ COMPAT_2 (OP_7E0 ());
+}
+
+
+
+// SET1
+00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
+"set1 , [r]"
+{
+ COMPAT_2 (OP_7C0 ());
+}
+
+rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
+*v850e
+*v850e1
+"set1 r, [r]"
+{
+ COMPAT_2 (OP_E007E0 ());
+}
+
+
+
+// SHL
+rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
+"shl r, r"
+{
+ COMPAT_2 (OP_C007E0 ());
+}
+
+rrrrr,010110,iiiii:II:::shl
+"shl , r"
+{
+ COMPAT_1 (OP_2C0 ());
+}
+
+
+
+// SHR
+rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
+"shr r, r"
+{
+ COMPAT_2 (OP_8007E0 ());
+}
+
+rrrrr,010100,iiiii:II:::shr
+"shr , r"
+{
+ COMPAT_1 (OP_280 ());
+}
+
+
+
+// SLD
+rrrrr,0110,ddddddd:IV:::sld.b
+"sld.bu [ep], r":(PSW & PSW_US)
+"sld.b [ep], r"
+{
+ unsigned32 addr = EP + disp7;
+ unsigned32 result = load_mem (addr, 1);
+ if (PSW & PSW_US)
+ {
+ GR[reg2] = result;
+ TRACE_LD_NAME ("sld.bu", addr, result);
+ }
+ else
+ {
+ result = EXTEND8 (result);
+ GR[reg2] = result;
+ TRACE_LD (addr, result);
+ }
+}
+
+rrrrr,1000,ddddddd:IV:::sld.h
+"sld.hu [ep], r":(PSW & PSW_US)
+"sld.h [ep], r"
+{
+ unsigned32 addr = EP + disp8;
+ unsigned32 result = load_mem (addr, 2);
+ if (PSW & PSW_US)
+ {
+ GR[reg2] = result;
+ TRACE_LD_NAME ("sld.hu", addr, result);
+ }
+ else
+ {
+ result = EXTEND16 (result);
+ GR[reg2] = result;
+ TRACE_LD (addr, result);
+ }
+}
+
+rrrrr,1010,dddddd,0:IV:::sld.w
+"sld.w [ep], r"
+{
+ unsigned32 addr = EP + disp8;
+ unsigned32 result = load_mem (addr, 4);
+ GR[reg2] = result;
+ TRACE_LD (addr, result);
+}
+
+rrrrr!0,0000110,dddd:IV:::sld.bu
+*v850e
+*v850e1
+"sld.b [ep], r":(PSW & PSW_US)
+"sld.bu [ep], r"
+{
+ unsigned32 addr = EP + disp4;
+ unsigned32 result = load_mem (addr, 1);
+ if (PSW & PSW_US)
+ {
+ result = EXTEND8 (result);
+ GR[reg2] = result;
+ TRACE_LD_NAME ("sld.b", addr, result);
+ }
+ else
+ {
+ GR[reg2] = result;
+ TRACE_LD (addr, result);
+ }
+}
+
+rrrrr!0,0000111,dddd:IV:::sld.hu
+*v850e
+*v850e1
+"sld.h [ep], r":(PSW & PSW_US)
+"sld.hu [ep], r"
+{
+ unsigned32 addr = EP + disp5;
+ unsigned32 result = load_mem (addr, 2);
+ if (PSW & PSW_US)
+ {
+ result = EXTEND16 (result);
+ GR[reg2] = result;
+ TRACE_LD_NAME ("sld.h", addr, result);
+ }
+ else
+ {
+ GR[reg2] = result;
+ TRACE_LD (addr, result);
+ }
+}
+
+// SST
+rrrrr,0111,ddddddd:IV:::sst.b
+"sst.b r, [ep]"
+{
+ COMPAT_1 (OP_380 ());
+}
+
+rrrrr,1001,ddddddd:IV:::sst.h
+"sst.h r, [ep]"
+{
+ COMPAT_1 (OP_480 ());
+}
+
+rrrrr,1010,dddddd,1:IV:::sst.w
+"sst.w r, [ep]"
+{
+ COMPAT_1 (OP_501 ());
+}
+
+// ST
+rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
+"st.b r, [r]"
+{
+ COMPAT_2 (OP_740 ());
+}
+
+rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
+"st.h r, [r]"
+{
+ COMPAT_2 (OP_760 ());
+}
+
+rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
+"st.w r, [r]"
+{
+ COMPAT_2 (OP_10760 ());
+}
+
+// STSR
+rrrrr,111111,regID + 0000000001000000:IX:::stsr
+"stsr s, r"
+{
+ TRACE_ALU_INPUT1 (SR[regID]);
+ GR[reg2] = SR[regID];
+ TRACE_ALU_RESULT (GR[reg2]);
+}
+
+// SUB
+rrrrr,001101,RRRRR:I:::sub
+"sub r, r"
+{
+ COMPAT_1 (OP_1A0 ());
+}
+
+// SUBR
+rrrrr,001100,RRRRR:I:::subr
+"subr r, r"
+{
+ COMPAT_1 (OP_180 ());
+}
+
+// SWITCH
+00000000010,RRRRR:I:::switch
+*v850e
+*v850e1
+"switch r"
+{
+ unsigned long adr;
+ SAVE_1;
+ trace_input ("switch", OP_REG, 0);
+ adr = (cia + 2) + (State.regs[ reg1 ] << 1);
+ nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
+ trace_output (OP_REG);
+}
+
+// SXB
+00000000101,RRRRR:I:::sxb
+*v850e
+*v850e1
+"sxb r"
+{
+ TRACE_ALU_INPUT1 (GR[reg1]);
+ GR[reg1] = EXTEND8 (GR[reg1]);
+ TRACE_ALU_RESULT (GR[reg1]);
+}
+
+// SXH
+00000000111,RRRRR:I:::sxh
+*v850e
+*v850e1
+"sxh r"
+{
+ TRACE_ALU_INPUT1 (GR[reg1]);
+ GR[reg1] = EXTEND16 (GR[reg1]);
+ TRACE_ALU_RESULT (GR[reg1]);
+}
+
+// TRAP
+00000111111,iiiii + 0000000100000000:X:::trap
+"trap "
+{
+ COMPAT_2 (OP_10007E0 ());
+}
+
+// TST
+rrrrr,001011,RRRRR:I:::tst
+"tst r, r"
+{
+ COMPAT_1 (OP_160 ());
+}
+
+// TST1
+11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
+"tst1 , [r]"
+{
+ COMPAT_2 (OP_C7C0 ());
+}
+
+rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
+*v850e
+*v850e1
+"tst1 r, [r]"
+{
+ COMPAT_2 (OP_E607E0 ());
+}
+
+// XOR
+rrrrr,001001,RRRRR:I:::xor
+"xor r, r"
+{
+ COMPAT_1 (OP_120 ());
+}
+
+// XORI
+rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
+"xori , r, r"
+{
+ COMPAT_2 (OP_6A0 ());
+}
+
+// ZXB
+00000000100,RRRRR:I:::zxb
+*v850e
+*v850e1
+"zxb r"
+{
+ TRACE_ALU_INPUT1 (GR[reg1]);
+ GR[reg1] = GR[reg1] & 0xff;
+ TRACE_ALU_RESULT (GR[reg1]);
+}
+
+// ZXH
+00000000110,RRRRR:I:::zxh
+*v850e
+*v850e1
+"zxh r"
+{
+ TRACE_ALU_INPUT1 (GR[reg1]);
+ GR[reg1] = GR[reg1] & 0xffff;
+ TRACE_ALU_RESULT (GR[reg1]);
+}
+
+// Right field must be zero so that it doesn't clash with DIVH
+// Left field must be non-zero so that it doesn't clash with SWITCH
+11111,000010,00000:I:::break
+*v850
+*v850e
+{
+ sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
+}
+
+11111,000010,00000:I:::dbtrap
+*v850e1
+"dbtrap"
+{
+ DBPC = cia + 2;
+ DBPSW = PSW;
+ PSW = PSW | (PSW_NP | PSW_EP | PSW_ID);
+ PC = 0x00000060;
+ nia = 0x00000060;
+ TRACE_BRANCH0 ();
+}
+
+// New breakpoint: 0x7E0 0x7E0
+00000,111111,00000 + 00000,11111,100000:X:::ilgop
+{
+ sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
+}
+
+// Return from debug trap: 0x146007e0
+0000011111100000 + 0000000101000110:X:::dbret
+*v850e1
+"dbret"
+{
+ nia = DBPC;
+ PSW = DBPSW;
+ TRACE_BRANCH1 (PSW);
+}
Index: v850-dc
===================================================================
--- v850-dc (nonexistent)
+++ v850-dc (revision 33)
@@ -0,0 +1,29 @@
+# most instructions
+# ------ options ------ : Fst : Lst : ff : fl : fe : word : --- fmt --- : model ...
+# { : mask : value : word }
+
+# Top level - create a very big switch statement.
+
+ padded-switch,combine : 15 : 5 : : : : 0 : :
+
+
+# for opcode 60,124
+
+ switch,combine : 4 : 0 : : : : 1 : V,VII :
+ switch,combine : 4 : 0 : : : : 1 : V,XIII : v850e
+ switch,combine : 4 : 0 : : : : 1 : V,XIII : v850e1
+
+
+# for opcode 63, 127, 1087 et.al.
+
+ switch,combine : 9 : 5 : : : : 1 : :
+ switch,combine : 4 : 0 : : : : 1 : :
+
+
+# for opcode 40 et.al.
+
+ switch,combine : 4 : 0 : : : : 0 : III,IV :
+
+# for opcode 66 - divh/break
+
+ switch,combine : 4 : 0 : : : : 0 : I :
Index: ChangeLog
===================================================================
--- ChangeLog (nonexistent)
+++ ChangeLog (revision 33)
@@ -0,0 +1,1254 @@
+2008-02-05 DJ Delorie
+
+ * simops.c (OP_1C007E0): Compensate for 64 bit hosts.
+ (OP_18007E0): Likewise.
+ (OP_2C007E0): Likewise.
+ (OP_28007E0): Likewise.
+ * v850.igen (divh): Likewise.
+
+ * simops.c (OP_C0): Correct saturation logic.
+ (OP_220): Likewise.
+ (OP_A0): Likewise.
+ (OP_660): Likewise.
+ (OP_80): Likewise.
+
+ * simops.c (OP_2A0): If the shift count is zero, clear the
+ carry.
+ (OP_A007E0): Likewise.
+ (OP_2C0): Likewise.
+ (OP_C007E0): Likewise.
+ (OP_280): Likewise.
+ (OP_8007E0): Likewise.
+
+ * simops.c (OP_2C207E0): Correct PSW flags for special divu
+ conditions.
+ (OP_2C007E0): Likewise, for div.
+ (OP_28207E0): Likewise, for divhu.
+ (OP_28007E0): Likewise, for divh. Also, sign-extend the correct
+ operand.
+ * v850.igen (divh): Likewise, for 2-op divh.
+
+ * v850.igen (bsh): Fix carry logic.
+
+2007-02-20 Daniel Jacobowitz
+
+ * Makefile.in (interp.o): Uncomment and update.
+
+2006-12-21 Hans-Peter Nilsson
+
+ * acconfig.h: Remove.
+ * config.in: Regenerate.
+
+2006-06-13 Richard Earnshaw
+
+ * configure: Regenerated.
+
+2006-06-05 Daniel Jacobowitz
+
+ * configure: Regenerated.
+
+2006-05-31 Daniel Jacobowitz
+
+ * configure: Regenerated.
+
+2005-03-23 Mark Kettenis
+
+ * configure: Regenerate.
+
+2005-01-14 Andrew Cagney
+
+ * configure.ac: Sinclude aclocal.m4 before common.m4. Add
+ explicit call to AC_CONFIG_HEADER.
+ * configure: Regenerate.
+
+2005-01-12 Andrew Cagney
+
+ * configure.ac: Update to use ../common/common.m4.
+ * configure: Re-generate.
+
+2005-01-11 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+2005-01-07 Andrew Cagney
+
+ * configure.ac: Rename configure.in, require autoconf 2.59.
+ * configure: Re-generate.
+
+2004-12-08 Hans-Peter Nilsson
+
+ * configure: Regenerate for ../common/aclocal.m4 update.
+
+2004-01-18 Mark Kettenis
+
+ * simops.c: Include .
+
+2003-09-05 Andrew Cagney
+ Nick Clifton
+
+ * interp.c (sim_open): Accept bfd_mach_v850e1.
+ * v850-dc: Add entry for v850e1.
+ * v850.igen: Add support for v850e1.
+ Add code for DBTRAP and DBRET instructions.
+ (dbtrap): Create a separate v850e1 specific instruction.
+ Only generate a trap if the target is not the v850e1.
+ Otherwise treat it as a special kind of branch.
+ (break): Mark as v850/v850e specific.
+
+2003-05-16 Ian Lance Taylor
+
+ * Makefile.in (SHELL): Make sure this is defined.
+ (tmp-igen): Use $(SHELL) whenever we invoke move-if-change.
+
+2003-04-06 Nick Clifton
+
+ * simops.c (OP_40): Delete. Move code to...
+ * v850-igen.c (): ...Here. Sign extend the first operand.
+ * simops.h (OP_40): Remove prototype.
+
+2003-02-27 Andrew Cagney
+
+ * interp.c (sim_open, sim_create_inferior): Rename _bfd to bfd.
+
+2002-11-30 Andrew Cagney
+
+ * simops.c: Use int, 1, 0 instead of boolean, true and false.
+ * sim-main.h: Ditto.
+
+2002-09-27 Jim Wilson
+
+ * simops.c (OP_E6077E0): And op1 with 7 after reading register, not
+ before.
+ (BIT_CHANGE_OP): Likewise.
+
+2002-09-26 Jim Wilson
+
+ * simops (OP_10007E0): Don't subtract 4 from PC.
+
+2002-09-19 Nick Clifton
+
+ * interp.c (sim_open): Remove reference to v850ea.
+ (sim_create_inferior): Likewise.
+ * v850-dc: Likewise.
+ * v850.igen: Remove all references to v850ea, including v850ea
+ specific instructions.
+
+2002-08-29 Nick Clifton
+
+ From 2001-08-23 Catherine Moore