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Subversion Repositories openrisc_2011-10-31
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- This comparison shows the changes necessary to convert path
/openrisc/tags/gnu-src/gcc-4.5.1/gcc-4.5.1-or32-1.0rc2/gcc/config/mmix
- from Rev 282 to Rev 384
- ↔ Reverse comparison
Rev 282 → Rev 384
/crti.asm
0,0 → 1,116
/* Copyright (C) 2001, 2002 Free Software Foundation, Inc. |
Contributed by Hans-Peter Nilsson <hp@bitrange.com> |
|
This file is free software; you can redistribute it and/or modify it |
under the terms of the GNU General Public License as published by the |
Free Software Foundation; either version 3, or (at your option) any |
later version. |
|
This file is distributed in the hope that it will be useful, but |
WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
General Public License for more details. |
|
Under Section 7 of GPL version 3, you are granted additional |
permissions described in the GCC Runtime Library Exception, version |
3.1, as published by the Free Software Foundation. |
|
You should have received a copy of the GNU General Public License and |
a copy of the GCC Runtime Library Exception along with this program; |
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see |
<http://www.gnu.org/licenses/>. */ |
|
% This is the crt0 equivalent for mmix-knuth-mmixware, for setting up |
% things for compiler-generated assembly-code and for setting up things |
% between where the simulator calls and main, and shutting things down on |
% the way back. There's an actual crt0.o elsewhere, but that's a dummy. |
|
% This file and the GCC output are supposed to be *reasonably* |
% mmixal-compatible to enable people to re-use output with Knuth's mmixal. |
% However, forward references are used more freely: we are using the |
% binutils tools. Users of mmixal beware; you will sometimes have to |
% re-order things or use temporary variables. |
|
% Users of mmixal will want to set up 8H and 9H to be .text and .data |
% respectively, so the compiler can switch between them pretending they're |
% segments. |
|
% This little treasure is here so the 32 lowest address bits of user data |
% will not be zero. Because of truncation, that would cause testcase |
% gcc.c-torture/execute/980701-1.c to incorrectly fail. |
|
.data ! mmixal:= 8H LOC Data_Segment |
.p2align 3 |
LOC @+(8-@)@7 |
OCTA 2009 |
|
.text ! mmixal:= 9H LOC 8B; LOC #100 |
.global Main |
|
% The __Stack_start symbol is provided by the link script. |
stackpp OCTA __Stack_start |
|
% "Main" is the magic symbol the simulator jumps to. We want to go |
% on to "main". |
% We need to set rG explicitly to avoid hard-to-debug situations. |
Main SETL $255,32 |
PUT rG,$255 |
|
% Initialize the stack pointer. It is supposedly made a global |
% zero-initialized (allowed to change) register in crtn.asm; we use the |
% explicit number. |
GETA $255,stackpp |
LDOU $254,$255,0 |
|
% Make sure we get more than one mem, to simplify counting cycles. |
LDBU $255,$1,0 |
LDBU $255,$1,1 |
|
PUSHJ $2,_init |
|
#ifdef __MMIX_ABI_GNU__ |
% Copy argc and argv from their initial position to argument registers |
% where necessary. |
SET $231,$0 |
SET $232,$1 |
#else |
% For the mmixware ABI, we need to move arguments. The return value will |
% appear in $0. |
SET $2,$1 |
SET $1,$0 |
#endif |
|
PUSHJ $0,main |
JMP exit |
|
% Provide the first part of _init and _fini. Save the return address on the |
% register stack. We eventually ignore the return address of these |
% PUSHJ:s, so it doesn't matter that whether .init and .fini code calls |
% functions or where they store rJ. We shouldn't get there, so die |
% (TRAP Halt) if that happens. |
|
.section .init,"ax",@progbits |
.global _init |
_init: |
GET $0,:rJ |
PUSHJ $1,0F |
SETL $255,255 |
TRAP 0,0,0 |
0H IS @ |
|
% Register _fini to be executed as the last atexit function. |
#ifdef __MMIX_ABI_GNU__ |
GETA $231,_fini |
#else |
GETA $1,_fini |
#endif |
PUSHJ $0,atexit |
|
.section .fini,"ax",@progbits |
.global _fini |
_fini: |
GET $0,:rJ |
PUSHJ $1,0F |
SETL $255,255 |
TRAP 0,0,0 |
0H IS @ |
/mmix.h
0,0 → 1,958
/* Definitions of target machine for GNU compiler, for MMIX. |
Copyright (C) 2000, 2001, 2002, 2004, 2005, 2007, 2008, 2009 |
Free Software Foundation, Inc. |
Contributed by Hans-Peter Nilsson (hp@bitrange.com) |
|
This file is part of GCC. |
|
GCC is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 3, or (at your option) |
any later version. |
|
GCC is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with GCC; see the file COPYING3. If not see |
<http://www.gnu.org/licenses/>. */ |
|
#ifndef GCC_MMIX_H |
#define GCC_MMIX_H |
|
/* First, some local helper macros. Note that the "default" value of |
FIXED_REGISTERS, CALL_USED_REGISTERS, REG_ALLOC_ORDER and |
REG_CLASS_CONTENTS depend on these values. */ |
#define MMIX_RESERVED_GNU_ARG_0_REGNUM 231 |
#define MMIX_FIRST_ARG_REGNUM \ |
(TARGET_ABI_GNU ? MMIX_RESERVED_GNU_ARG_0_REGNUM : 16) |
#define MMIX_FIRST_INCOMING_ARG_REGNUM \ |
(TARGET_ABI_GNU ? MMIX_RESERVED_GNU_ARG_0_REGNUM : 0) |
#define MMIX_MAX_ARGS_IN_REGS 16 |
|
/* FIXME: This one isn't fully implemented yet. Return values larger than |
one register are passed by reference in MMIX_STRUCT_VALUE_REGNUM by the |
caller, except for return values of type "complex". */ |
#define MMIX_MAX_REGS_FOR_VALUE 16 |
#define MMIX_RETURN_VALUE_REGNUM \ |
(TARGET_ABI_GNU ? MMIX_RESERVED_GNU_ARG_0_REGNUM : 15) |
#define MMIX_OUTGOING_RETURN_VALUE_REGNUM \ |
(TARGET_ABI_GNU ? MMIX_RESERVED_GNU_ARG_0_REGNUM : 0) |
#define MMIX_STRUCT_VALUE_REGNUM 251 |
#define MMIX_STATIC_CHAIN_REGNUM 252 |
#define MMIX_FRAME_POINTER_REGNUM 253 |
#define MMIX_STACK_POINTER_REGNUM 254 |
#define MMIX_LAST_GENERAL_REGISTER 255 |
#define MMIX_INCOMING_RETURN_ADDRESS_REGNUM MMIX_rJ_REGNUM |
#define MMIX_HIMULT_REGNUM 258 |
#define MMIX_REMAINDER_REGNUM MMIX_rR_REGNUM |
#define MMIX_ARG_POINTER_REGNUM 261 |
#define MMIX_rO_REGNUM 262 |
#define MMIX_LAST_STACK_REGISTER_REGNUM 31 |
|
/* Four registers; "ideally, these registers should be call-clobbered", so |
just grab a bunch of the common clobbered registers. FIXME: Last |
registers of return-value should be used, with an error if there's a |
return-value (that collides in size). */ |
#define MMIX_EH_RETURN_DATA_REGNO_START (MMIX_STRUCT_VALUE_REGNUM - 4) |
|
/* Try to keep the definitions from running away on their own. */ |
#if (MMIX_EH_RETURN_DATA_REGNO_START \ |
!= MMIX_RESERVED_GNU_ARG_0_REGNUM + MMIX_MAX_ARGS_IN_REGS) |
#error MMIX register definition inconsistency |
#endif |
|
#if (MMIX_MAX_REGS_FOR_VALUE + MMIX_MAX_ARGS_IN_REGS > 32) |
#error MMIX parameters and return values bad, more than 32 registers |
#endif |
|
/* This chosen as "a call-clobbered hard register that is otherwise |
untouched by the epilogue". */ |
#define MMIX_EH_RETURN_STACKADJ_REGNUM MMIX_STATIC_CHAIN_REGNUM |
|
#ifdef REG_OK_STRICT |
# define MMIX_REG_OK_STRICT 1 |
#else |
# define MMIX_REG_OK_STRICT 0 |
#endif |
|
#define MMIX_FUNCTION_ARG_SIZE(MODE, TYPE) \ |
((MODE) != BLKmode ? GET_MODE_SIZE (MODE) : int_size_in_bytes (TYPE)) |
|
/* Per-function machine data. This is normally an opaque type just |
defined and used in the tm.c file, but we need to see the definition in |
mmix.md too. */ |
struct GTY(()) machine_function |
{ |
int has_landing_pad; |
int highest_saved_stack_register; |
int in_prologue; |
}; |
|
/* For these target macros, there is no generic documentation here. You |
should read `Using and Porting GCC' for that. Only comments specific |
to the MMIX target are here. |
|
There are however references to the specific texinfo node (comments |
with "Node:"), so there should be little or nothing amiss. Probably |
the opposite, since we don't have to care about old littering and |
soon outdated generic comments. */ |
|
/* Node: Driver */ |
|
/* User symbols are in the same name-space as built-in symbols, but we |
don't need the built-in symbols, so remove those and instead apply |
stricter operand checking. Don't warn when expanding insns. */ |
#define ASM_SPEC "-no-predefined-syms -x" |
|
/* Pass on -mset-program-start=N and -mset-data-start=M to the linker. |
Provide default program start 0x100 unless -mno-set-program-start. |
Don't do this if linking relocatably, with -r. For a final link, |
produce mmo, unless ELF is requested or when linking relocatably. */ |
#define LINK_SPEC \ |
"%{mset-program-start=*:--defsym __.MMIX.start..text=%*}\ |
%{mset-data-start=*:--defsym __.MMIX.start..data=%*}\ |
%{!mset-program-start=*:\ |
%{!mno-set-program-start:\ |
%{!r:--defsym __.MMIX.start..text=0x100}}}\ |
%{!melf:%{!r:-m mmo}}%{melf|r:-m elf64mmix}" |
|
/* FIXME: There's no provision for profiling here. */ |
#define STARTFILE_SPEC \ |
"crti%O%s crtbegin%O%s" |
|
#define ENDFILE_SPEC "crtend%O%s crtn%O%s" |
|
/* Node: Run-time Target */ |
|
/* Define __LONG_MAX__, since we're advised not to change glimits.h. */ |
#define TARGET_CPU_CPP_BUILTINS() \ |
do \ |
{ \ |
builtin_define ("__mmix__"); \ |
builtin_define ("__MMIX__"); \ |
if (TARGET_ABI_GNU) \ |
builtin_define ("__MMIX_ABI_GNU__"); \ |
else \ |
builtin_define ("__MMIX_ABI_MMIXWARE__"); \ |
} \ |
while (0) |
|
extern int target_flags; |
|
#define TARGET_DEFAULT \ |
(MASK_BRANCH_PREDICT | MASK_BASE_ADDRESSES | MASK_USE_RETURN_INSN) |
|
/* Unfortunately, this must not reference anything in "mmix.c". */ |
#define TARGET_VERSION \ |
fprintf (stderr, " (MMIX)") |
|
#define OVERRIDE_OPTIONS mmix_override_options () |
|
#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ |
do \ |
{ \ |
if (LEVEL >= 1) \ |
flag_regmove = TRUE; \ |
\ |
if (SIZE || LEVEL > 1) \ |
{ \ |
flag_omit_frame_pointer = TRUE; \ |
} \ |
} \ |
while (0) |
|
/* This one will have to wait a little bit; right now we can't debug |
neither with or without a frame-pointer. */ |
/* #define CAN_DEBUG_WITHOUT_FP */ |
|
|
/* Node: Per-Function Data */ |
#define INIT_EXPANDERS mmix_init_expanders () |
|
|
/* Node: Storage Layout */ |
/* I see no bit-field instructions. Anyway, the common order is from low |
to high, as the power of two, hence little-endian. */ |
#define BITS_BIG_ENDIAN 0 |
#define BYTES_BIG_ENDIAN 1 |
#define WORDS_BIG_ENDIAN 1 |
#define FLOAT_WORDS_BIG_ENDIAN 1 |
#define UNITS_PER_WORD 8 |
|
/* We need to align everything to 64 bits that can affect the alignment |
of other types. Since address N is interpreted in MMIX as (N modulo |
access_size), we must align. */ |
#define PARM_BOUNDARY 64 |
#define STACK_BOUNDARY 64 |
#define FUNCTION_BOUNDARY 32 |
#define BIGGEST_ALIGNMENT 64 |
|
/* This one is only used in the ADA front end. */ |
#define MINIMUM_ATOMIC_ALIGNMENT 8 |
|
/* Copied from elfos.h. */ |
#define MAX_OFILE_ALIGNMENT (32768 * 8) |
|
#define DATA_ALIGNMENT(TYPE, BASIC_ALIGN) \ |
mmix_data_alignment (TYPE, BASIC_ALIGN) |
|
#define CONSTANT_ALIGNMENT(CONSTANT, BASIC_ALIGN) \ |
mmix_constant_alignment (CONSTANT, BASIC_ALIGN) |
|
#define LOCAL_ALIGNMENT(TYPE, BASIC_ALIGN) \ |
mmix_local_alignment (TYPE, BASIC_ALIGN) |
|
/* Following other ports, this seems to most commonly be the word-size, |
so let's do that here too. */ |
#define EMPTY_FIELD_BOUNDARY 64 |
|
/* We chose to have this low solely for similarity with the alpha. It has |
nothing to do with passing the tests dg/c99-scope-2 and |
execute/align-1.c. Nothing. Though the tests seem wrong. Padding of |
the structure is automatically added to get alignment when needed if we |
set this to just byte-boundary. */ |
#define STRUCTURE_SIZE_BOUNDARY 8 |
|
/* The lower bits are ignored. */ |
#define STRICT_ALIGNMENT 1 |
|
|
/* Node: Type Layout */ |
|
/* It might seem more natural to have 64-bit ints on a 64-bit machine, |
but then an occasional MMIX programmer needs to know how to put a lot |
of __attribute__ stuff to get to the 8, 16 and 32-bit modes rather |
than the "intuitive" char, short and int types. */ |
#define INT_TYPE_SIZE 32 |
#define SHORT_TYPE_SIZE 16 |
#define LONG_LONG_TYPE_SIZE 64 |
|
#define FLOAT_TYPE_SIZE 32 |
#define DOUBLE_TYPE_SIZE 64 |
#define LONG_DOUBLE_TYPE_SIZE 64 |
|
#define DEFAULT_SIGNED_CHAR 1 |
|
|
/* Node: Register Basics */ |
/* We tell GCC about all 256 general registers, and we also include |
rD, rE, rH, rJ, rR and rO (in that order) so we can describe what insns |
clobber them. We use a faked register for the argument pointer. It is |
always eliminated towards the frame-pointer or the stack-pointer, never |
output in assembly. Any fixed register would do for this, like $255, |
but future debugging is easier when using a separate register. It |
counts as a global register for pseudorandom reasons. */ |
#define FIRST_PSEUDO_REGISTER 263 |
|
/* We treat general registers with no assigned purpose as fixed. The |
stack pointer, $254, is also fixed. Register $255 is referred to as a |
temporary register in the MMIX papers, and used as such in mmixal, so |
it should not be used as a stack pointer. We set it to fixed, and use |
it "manually" at times of despair. */ |
#define FIXED_REGISTERS \ |
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, \ |
1, 1, 0, 0, 0, 1, 1 \ |
} |
|
/* General registers are fixed and therefore "historically" marked |
call-used. (FIXME: This has changed). Registers $15..$31 are |
call-clobbered; we'll put arguments in $16 and up, and we need $15 for |
the MMIX register-stack "hole". */ |
#define CALL_USED_REGISTERS \ |
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, \ |
1, 1, 1, 1, 1, 1, 1 \ |
} |
|
#define CONDITIONAL_REGISTER_USAGE mmix_conditional_register_usage () |
|
#define INCOMING_REGNO(OUT) mmix_opposite_regno (OUT, 0) |
|
#define OUTGOING_REGNO(IN) mmix_opposite_regno (IN, 1) |
|
/* Defining LOCAL_REGNO is necessary in presence of prologue/epilogue, |
else GCC will be confused that those registers aren't saved and |
restored. */ |
#define LOCAL_REGNO(REGNO) mmix_local_regno (REGNO) |
|
/* Node: Allocation Order */ |
|
/* We should allocate registers from 0 to 31 by increasing number, because |
I think that's what people expect. Beyond that, just use |
call-clobbered global registers first, then call-clobbered special |
registers. Last, the fixed registers. */ |
#define MMIX_MMIXWARE_ABI_REG_ALLOC_ORDER \ |
{ 0, 1, 2, 3, 4, 5, 6, 7, \ |
8, 9, 10, 11, 12, 13, 14, 15, \ |
16, 17, 18, 19, 20, 21, 22, 23, \ |
24, 25, 26, 27, 28, 29, 30, 31, \ |
\ |
252, 251, 250, 249, 248, 247, \ |
\ |
253, \ |
\ |
258, 260, 259, \ |
\ |
32, 33, 34, 35, 36, 37, 38, 39, \ |
40, 41, 42, 43, 44, 45, 46, 47, \ |
48, 49, 50, 51, 52, 53, 54, 55, \ |
56, 57, 58, 59, 60, 61, 62, 63, \ |
64, 65, 66, 67, 68, 69, 70, 71, \ |
72, 73, 74, 75, 76, 77, 78, 79, \ |
80, 81, 82, 83, 84, 85, 86, 87, \ |
88, 89, 90, 91, 92, 93, 94, 95, \ |
96, 97, 98, 99, 100, 101, 102, 103, \ |
104, 105, 106, 107, 108, 109, 110, 111, \ |
112, 113, 114, 115, 116, 117, 118, 119, \ |
120, 121, 122, 123, 124, 125, 126, 127, \ |
128, 129, 130, 131, 132, 133, 134, 135, \ |
136, 137, 138, 139, 140, 141, 142, 143, \ |
144, 145, 146, 147, 148, 149, 150, 151, \ |
152, 153, 154, 155, 156, 157, 158, 159, \ |
160, 161, 162, 163, 164, 165, 166, 167, \ |
168, 169, 170, 171, 172, 173, 174, 175, \ |
176, 177, 178, 179, 180, 181, 182, 183, \ |
184, 185, 186, 187, 188, 189, 190, 191, \ |
192, 193, 194, 195, 196, 197, 198, 199, \ |
200, 201, 202, 203, 204, 205, 206, 207, \ |
208, 209, 210, 211, 212, 213, 214, 215, \ |
216, 217, 218, 219, 220, 221, 222, 223, \ |
224, 225, 226, 227, 228, 229, 230, 231, \ |
232, 233, 234, 235, 236, 237, 238, 239, \ |
240, 241, 242, 243, 244, 245, 246, \ |
\ |
254, 255, 256, 257, 261, 262 \ |
} |
|
/* As a convenience, we put this nearby, for ease of comparison. |
First, call-clobbered registers in reverse order of assignment as |
parameters (also the top ones; not because they're parameters, but |
for continuity). |
|
Second, saved registers that go on the register-stack. |
|
Third, special registers rH, rR and rJ. They should not normally be |
allocated, but since they're call-clobbered, it is cheaper to use one |
of them than using a call-saved register for a call-clobbered use, |
assuming it is referenced a very limited number of times. Other global |
and fixed registers come next; they are never allocated. */ |
#define MMIX_GNU_ABI_REG_ALLOC_ORDER \ |
{ 252, 251, 250, 249, 248, 247, 246, \ |
245, 244, 243, 242, 241, 240, 239, 238, \ |
237, 236, 235, 234, 233, 232, 231, \ |
\ |
0, 1, 2, 3, 4, 5, 6, 7, \ |
8, 9, 10, 11, 12, 13, 14, 15, \ |
16, 17, 18, 19, 20, 21, 22, 23, \ |
24, 25, 26, 27, 28, 29, 30, 31, \ |
\ |
253, \ |
\ |
258, 260, 259, \ |
\ |
32, 33, 34, 35, 36, 37, 38, 39, \ |
40, 41, 42, 43, 44, 45, 46, 47, \ |
48, 49, 50, 51, 52, 53, 54, 55, \ |
56, 57, 58, 59, 60, 61, 62, 63, \ |
64, 65, 66, 67, 68, 69, 70, 71, \ |
72, 73, 74, 75, 76, 77, 78, 79, \ |
80, 81, 82, 83, 84, 85, 86, 87, \ |
88, 89, 90, 91, 92, 93, 94, 95, \ |
96, 97, 98, 99, 100, 101, 102, 103, \ |
104, 105, 106, 107, 108, 109, 110, 111, \ |
112, 113, 114, 115, 116, 117, 118, 119, \ |
120, 121, 122, 123, 124, 125, 126, 127, \ |
128, 129, 130, 131, 132, 133, 134, 135, \ |
136, 137, 138, 139, 140, 141, 142, 143, \ |
144, 145, 146, 147, 148, 149, 150, 151, \ |
152, 153, 154, 155, 156, 157, 158, 159, \ |
160, 161, 162, 163, 164, 165, 166, 167, \ |
168, 169, 170, 171, 172, 173, 174, 175, \ |
176, 177, 178, 179, 180, 181, 182, 183, \ |
184, 185, 186, 187, 188, 189, 190, 191, \ |
192, 193, 194, 195, 196, 197, 198, 199, \ |
200, 201, 202, 203, 204, 205, 206, 207, \ |
208, 209, 210, 211, 212, 213, 214, 215, \ |
216, 217, 218, 219, 220, 221, 222, 223, \ |
224, 225, 226, 227, 228, 229, 230, \ |
\ |
254, 255, 256, 257, 261, 262 \ |
} |
|
/* The default one. */ |
#define REG_ALLOC_ORDER MMIX_MMIXWARE_ABI_REG_ALLOC_ORDER |
|
/* Node: Values in Registers */ |
|
#define HARD_REGNO_NREGS(REGNO, MODE) \ |
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \ |
/ UNITS_PER_WORD) |
|
#define HARD_REGNO_MODE_OK(REGNO, MODE) 1 |
|
/* Note that no register can really be accessed in single-float mode, so |
we *can* say 1 here. FIXME: Will TRT happen for single-float, or do |
we have to punt to libgcc1.asm? */ |
#define MODES_TIEABLE_P(MODE1, MODE2) 1 |
|
|
/* Node: Leaf Functions */ |
/* (empty) */ |
|
|
/* Node: Register Classes */ |
|
enum reg_class |
{ |
NO_REGS, GENERAL_REGS, REMAINDER_REG, HIMULT_REG, |
SYSTEM_REGS, ALL_REGS, LIM_REG_CLASSES |
}; |
|
#define N_REG_CLASSES (int) LIM_REG_CLASSES |
|
#define REG_CLASS_NAMES \ |
{"NO_REGS", "GENERAL_REGS", "REMAINDER_REG", "HIMULT_REG", \ |
"SYSTEM_REGS", "ALL_REGS"} |
|
/* Note that the contents of each item is always 32 bits. */ |
#define REG_CLASS_CONTENTS \ |
{{0, 0, 0, 0, 0, 0, 0, 0, 0}, \ |
{~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, 0x20}, \ |
{0, 0, 0, 0, 0, 0, 0, 0, 0x10}, \ |
{0, 0, 0, 0, 0, 0, 0, 0, 4}, \ |
{0, 0, 0, 0, 0, 0, 0, 0, 0x7f}, \ |
{~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, 0x7f}} |
|
#define REGNO_REG_CLASS(REGNO) \ |
((REGNO) <= MMIX_LAST_GENERAL_REGISTER \ |
|| (REGNO) == MMIX_ARG_POINTER_REGNUM \ |
? GENERAL_REGS \ |
: (REGNO) == MMIX_REMAINDER_REGNUM ? REMAINDER_REG \ |
: (REGNO) == MMIX_HIMULT_REGNUM ? HIMULT_REG : SYSTEM_REGS) |
|
#define BASE_REG_CLASS GENERAL_REGS |
|
#define INDEX_REG_CLASS GENERAL_REGS |
|
#define REG_CLASS_FROM_LETTER(CHAR) \ |
((CHAR) == 'x' ? SYSTEM_REGS \ |
: (CHAR) == 'y' ? REMAINDER_REG \ |
: (CHAR) == 'z' ? HIMULT_REG : NO_REGS) |
|
#define REGNO_OK_FOR_BASE_P(REGNO) \ |
((REGNO) <= MMIX_LAST_GENERAL_REGISTER \ |
|| (REGNO) == MMIX_ARG_POINTER_REGNUM \ |
|| (reg_renumber[REGNO] > 0 \ |
&& reg_renumber[REGNO] <= MMIX_LAST_GENERAL_REGISTER)) |
|
#define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P (REGNO) |
|
#define PREFERRED_RELOAD_CLASS(X, CLASS) \ |
mmix_preferred_reload_class (X, CLASS) |
|
#define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \ |
mmix_preferred_output_reload_class (X, CLASS) |
|
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
mmix_secondary_reload_class (CLASS, MODE, X, 1) |
|
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
mmix_secondary_reload_class (CLASS, MODE, X, 0) |
|
#define CLASS_MAX_NREGS(CLASS, MODE) HARD_REGNO_NREGS (CLASS, MODE) |
|
#define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
mmix_const_ok_for_letter_p (VALUE, C) |
|
#define EXTRA_CONSTRAINT(VALUE, C) \ |
mmix_extra_constraint (VALUE, C, MMIX_REG_OK_STRICT) |
|
/* Do we need anything serious here? Yes, any FLOT constant. */ |
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ |
mmix_const_double_ok_for_letter_p (VALUE, C) |
|
|
/* Node: Frame Layout */ |
|
#define STACK_GROWS_DOWNWARD |
#define FRAME_GROWS_DOWNWARD 1 |
|
#define STARTING_FRAME_OFFSET \ |
mmix_starting_frame_offset () |
|
#define FIRST_PARM_OFFSET(FUNDECL) 0 |
|
#define DYNAMIC_CHAIN_ADDRESS(FRAMEADDR) \ |
mmix_dynamic_chain_address (FRAMEADDR) |
|
/* FIXME: It seems RETURN_ADDR_OFFSET is undocumented. */ |
|
#define SETUP_FRAME_ADDRESSES() \ |
mmix_setup_frame_addresses () |
|
#define RETURN_ADDR_RTX(COUNT, FRAME) \ |
mmix_return_addr_rtx (COUNT, FRAME) |
|
/* It's in rJ before we store it somewhere. */ |
#define INCOMING_RETURN_ADDR_RTX \ |
gen_rtx_REG (Pmode, MMIX_INCOMING_RETURN_ADDRESS_REGNUM) |
|
/* FIXME: This does not seem properly documented or cross-indexed. |
Nowhere except in the code does it say it *has* to be in the range |
0..255, or else it will be truncated. That goes for the default too. */ |
#define DWARF_FRAME_RETURN_COLUMN \ |
DWARF_FRAME_REGNUM (MMIX_INCOMING_RETURN_ADDRESS_REGNUM) |
|
/* No return address is stored there. */ |
#define INCOMING_FRAME_SP_OFFSET 0 |
|
/* Node: Stack Checking */ |
/* (empty) */ |
|
|
/* Node: Exception Handling */ |
|
#define EH_RETURN_DATA_REGNO(N) \ |
mmix_eh_return_data_regno (N) |
|
#define EH_RETURN_STACKADJ_RTX \ |
mmix_eh_return_stackadj_rtx () |
|
#define EH_RETURN_HANDLER_RTX \ |
mmix_eh_return_handler_rtx () |
|
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
mmix_asm_preferred_eh_data_format (CODE, GLOBAL) |
|
/* Node: Frame Registers */ |
#define STACK_POINTER_REGNUM MMIX_STACK_POINTER_REGNUM |
|
/* Perhaps we can use HARD_FRAME_POINTER_REGNUM and decide later on |
what register we want to use. */ |
#define FRAME_POINTER_REGNUM MMIX_FRAME_POINTER_REGNUM |
#define ARG_POINTER_REGNUM MMIX_ARG_POINTER_REGNUM |
|
#define STATIC_CHAIN_REGNUM MMIX_STATIC_CHAIN_REGNUM |
|
|
/* Node: Elimination */ |
|
/* The frame-pointer is stored in a location that either counts to the |
offset of incoming parameters, or that counts to the offset of the |
frame, so we can't use a single offset. We therefore eliminate those |
two separately. */ |
#define ELIMINABLE_REGS \ |
{{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ |
{ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ |
{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} |
|
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
(OFFSET) = mmix_initial_elimination_offset (FROM, TO) |
|
|
/* Node: Stack Arguments */ |
|
#define ACCUMULATE_OUTGOING_ARGS 1 |
|
#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACKSIZE) 0 |
|
|
/* Node: Register Arguments */ |
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
mmix_function_arg (&(CUM), MODE, TYPE, NAMED, 0) |
|
#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ |
mmix_function_arg (&(CUM), MODE, TYPE, NAMED, 1) |
|
typedef struct { int regs; int lib; } CUMULATIVE_ARGS; |
|
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
((CUM).regs = 0, (CUM).lib = ((LIBNAME) != 0)) |
|
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
((CUM).regs \ |
= ((targetm.calls.must_pass_in_stack (MODE, TYPE)) \ |
|| (MMIX_FUNCTION_ARG_SIZE (MODE, TYPE) > 8 \ |
&& !TARGET_LIBFUNC && !(CUM).lib)) \ |
? (MMIX_MAX_ARGS_IN_REGS) + 1 \ |
: (CUM).regs + (7 + (MMIX_FUNCTION_ARG_SIZE (MODE, TYPE))) / 8) |
|
#define FUNCTION_ARG_REGNO_P(REGNO) \ |
mmix_function_arg_regno_p (REGNO, 0) |
|
|
/* Node: Register Arguments */ |
|
#define FUNCTION_VALUE(VALTYPE, FUNC) \ |
gen_rtx_REG (TYPE_MODE (VALTYPE), MMIX_RETURN_VALUE_REGNUM) |
|
/* This needs to take care of the register hole for complex return values. */ |
#define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ |
mmix_function_outgoing_value (VALTYPE, FUNC) |
|
#define LIBCALL_VALUE(MODE) \ |
gen_rtx_REG (MODE, MMIX_RETURN_VALUE_REGNUM) |
|
#define FUNCTION_VALUE_REGNO_P(REGNO) \ |
mmix_function_value_regno_p (REGNO) |
|
|
/* Node: Caller Saves */ |
/* (empty) */ |
|
|
/* Node: Function Entry */ |
|
/* See mmix.c for TARGET_ASM_FUNCTION_PROLOGUE and |
TARGET_ASM_FUNCTION_EPILOGUE. */ |
|
/* We need to say that the epilogue uses the return address, so the |
initial-value machinery restores it. FIXME: Some targets |
conditionalize on "reload_completed &&". Investigate difference. |
FIXME: Not needed if nonlocal_goto_stack_level. */ |
#define EPILOGUE_USES(REGNO) \ |
((REGNO) == MMIX_INCOMING_RETURN_ADDRESS_REGNUM) |
|
/* Node: Profiling */ |
#define FUNCTION_PROFILER(FILE, LABELNO) \ |
mmix_function_profiler (FILE, LABELNO) |
|
/* Node: Trampolines */ |
|
#define TRAMPOLINE_SIZE (4*UNITS_PER_WORD) |
#define TRAMPOLINE_ALIGNMENT BITS_PER_WORD |
|
/* Node: Addressing Modes */ |
|
#define CONSTANT_ADDRESS_P(X) \ |
mmix_constant_address_p (X) |
|
#define MAX_REGS_PER_ADDRESS 2 |
|
#ifndef REG_OK_STRICT |
# define REG_OK_FOR_BASE_P(X) \ |
(REGNO (X) <= MMIX_LAST_GENERAL_REGISTER \ |
|| REGNO (X) == MMIX_ARG_POINTER_REGNUM \ |
|| REGNO (X) >= FIRST_PSEUDO_REGISTER) |
#else |
# define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) |
#endif /* REG_OK_STRICT */ |
|
#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X) |
|
#define LEGITIMATE_CONSTANT_P(X) \ |
mmix_legitimate_constant_p (X) |
|
|
/* Node: Condition Code */ |
|
#define SELECT_CC_MODE(OP, X, Y) \ |
mmix_select_cc_mode (OP, X, Y) |
|
/* A definition of CANONICALIZE_COMPARISON that changed LE and GT |
comparisons with -1 to LT and GE respectively, and LT, LTU, GE or GEU |
comparisons with 256 to 255 and LE, LEU, GT and GTU has been |
ineffective; the code path for performing the changes did not trig for |
neither the GCC testsuite nor ghostscript-6.52 nor Knuth's mmix.tar.gz |
itself (core GCC functionality supposedly handling it) with sources |
from 2002-06-06. */ |
|
#define REVERSIBLE_CC_MODE(MODE) \ |
mmix_reversible_cc_mode (MODE) |
|
|
/* Node: Costs */ |
|
/* The special registers can only move to and from general regs, and we |
need to check that their constraints match, so say 3 for them. */ |
/* WARNING: gcc-2.7.2.2 i686-pc-linux-gnulibc1 (as shipped with RH 4.2) |
miscompiles reload1.c:reload_cse_simplify_set; a call to |
reload_cse_regno_equal_p is missing when checking if a substitution of |
a register setting is valid if this is defined to just the expression |
in mmix_register_move_cost. |
|
Symptom: a (all?) register setting is optimized away for e.g. |
"char *p1(char *p) { return p+1; }" and the value of register zero ($0) |
is returned. |
|
We can workaround by making this a function call - unknown if this |
causes dire speed effects. */ |
#define REGISTER_MOVE_COST(MODE, FROM, TO) \ |
mmix_register_move_cost (MODE, FROM, TO) |
|
#define SLOW_BYTE_ACCESS 0 |
|
|
/* Node: Sections */ |
|
/* This must be a constant string, since it's used in crtstuff.c. */ |
#define TEXT_SECTION_ASM_OP \ |
"\t.text ! mmixal:= 9H LOC 8B" |
|
/* FIXME: Not documented. */ |
#define DATA_SECTION_ASM_OP \ |
mmix_data_section_asm_op () |
|
#define READONLY_DATA_SECTION_ASM_OP "\t.section\t.rodata" |
|
/* Node: PIC */ |
/* (empty) */ |
|
|
/* Node: File Framework */ |
|
/* While any other punctuation character but ";" would do, we prefer "%" |
or "!"; "!" is an unary operator and so will not be mistakenly included |
in correctly formed expressions. The hash character adds mass; catches |
the eye. We can't have it as a comment char by itself, since it's a |
hex-number prefix. */ |
#define ASM_COMMENT_START "!#" |
|
/* These aren't currently functional. We just keep them as markers. */ |
#define ASM_APP_ON "%APP\n" |
#define ASM_APP_OFF "%NO_APP\n" |
|
#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \ |
mmix_asm_output_source_filename (STREAM, NAME) |
|
#define OUTPUT_QUOTED_STRING(STREAM, STRING) \ |
mmix_output_quoted_string (STREAM, STRING, strlen (STRING)) |
|
#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section |
|
/* Node: Data Output */ |
|
#define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \ |
mmix_asm_output_ascii (STREAM, PTR, LEN) |
|
/* Node: Uninitialized Data */ |
|
#define ASM_OUTPUT_ALIGNED_COMMON(ST, N, S, A) \ |
mmix_asm_output_aligned_common (ST, N, S, A) |
|
#define ASM_OUTPUT_ALIGNED_LOCAL(ST, N, S, A) \ |
mmix_asm_output_aligned_local (ST, N, S, A) |
|
|
/* Node: Label Output */ |
|
#define ASM_OUTPUT_LABEL(STREAM, NAME) \ |
mmix_asm_output_label (STREAM, NAME) |
|
#define ASM_OUTPUT_INTERNAL_LABEL(STREAM, NAME) \ |
mmix_asm_output_internal_label (STREAM, NAME) |
|
#define ASM_DECLARE_REGISTER_GLOBAL(STREAM, DECL, REGNO, NAME) \ |
mmix_asm_declare_register_global (STREAM, DECL, REGNO, NAME) |
|
#define GLOBAL_ASM_OP "\t.global " |
|
#define ASM_WEAKEN_LABEL(STREAM, NAME) \ |
mmix_asm_weaken_label (STREAM, NAME) |
|
#define MAKE_DECL_ONE_ONLY(DECL) \ |
mmix_make_decl_one_only (DECL) |
|
#define ASM_OUTPUT_LABELREF(STREAM, NAME) \ |
mmix_asm_output_labelref (STREAM, NAME) |
|
/* We insert a ":" to disambiguate against user symbols like L5. */ |
#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ |
sprintf (LABEL, "*%s:%ld", PREFIX, (long)(NUM)) |
|
/* Insert "::"; these are rarer than internal labels. FIXME: Make sure no |
":" is seen in the object file; we don't really want that mmixal |
feature visible there. We don't want the default, which uses a dot; |
that'd be incompatible with mmixal. */ |
#define ASM_PN_FORMAT "%s::%lu" |
|
#define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \ |
mmix_asm_output_def (STREAM, NAME, VALUE) |
|
/* Node: Macros for Initialization */ |
/* We're compiling to ELF and linking to MMO; fundamental ELF features |
that GCC depend on are there. */ |
|
/* These must be constant strings, since they're used in crtstuff.c. */ |
#define INIT_SECTION_ASM_OP "\t.section .init,\"ax\" ! mmixal-incompatible" |
|
#define FINI_SECTION_ASM_OP "\t.section .fini,\"ax\" ! mmixal-incompatible" |
|
#define OBJECT_FORMAT_ELF |
|
|
/* Node: Instruction Output */ |
|
/* The non-$ register names must be prefixed with ":", since they're |
affected by PREFIX. We provide the non-colon names as additional |
names. */ |
#define REGISTER_NAMES \ |
{"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \ |
"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ |
"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ |
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", \ |
"$32", "$33", "$34", "$35", "$36", "$37", "$38", "$39", \ |
"$40", "$41", "$42", "$43", "$44", "$45", "$46", "$47", \ |
"$48", "$49", "$50", "$51", "$52", "$53", "$54", "$55", \ |
"$56", "$57", "$58", "$59", "$60", "$61", "$62", "$63", \ |
"$64", "$65", "$66", "$67", "$68", "$69", "$70", "$71", \ |
"$72", "$73", "$74", "$75", "$76", "$77", "$78", "$79", \ |
"$80", "$81", "$82", "$83", "$84", "$85", "$86", "$87", \ |
"$88", "$89", "$90", "$91", "$92", "$93", "$94", "$95", \ |
"$96", "$97", "$98", "$99", "$100", "$101", "$102", "$103", \ |
"$104", "$105", "$106", "$107", "$108", "$109", "$110", "$111", \ |
"$112", "$113", "$114", "$115", "$116", "$117", "$118", "$119", \ |
"$120", "$121", "$122", "$123", "$124", "$125", "$126", "$127", \ |
"$128", "$129", "$130", "$131", "$132", "$133", "$134", "$135", \ |
"$136", "$137", "$138", "$139", "$140", "$141", "$142", "$143", \ |
"$144", "$145", "$146", "$147", "$148", "$149", "$150", "$151", \ |
"$152", "$153", "$154", "$155", "$156", "$157", "$158", "$159", \ |
"$160", "$161", "$162", "$163", "$164", "$165", "$166", "$167", \ |
"$168", "$169", "$170", "$171", "$172", "$173", "$174", "$175", \ |
"$176", "$177", "$178", "$179", "$180", "$181", "$182", "$183", \ |
"$184", "$185", "$186", "$187", "$188", "$189", "$190", "$191", \ |
"$192", "$193", "$194", "$195", "$196", "$197", "$198", "$199", \ |
"$200", "$201", "$202", "$203", "$204", "$205", "$206", "$207", \ |
"$208", "$209", "$210", "$211", "$212", "$213", "$214", "$215", \ |
"$216", "$217", "$218", "$219", "$220", "$221", "$222", "$223", \ |
"$224", "$225", "$226", "$227", "$228", "$229", "$230", "$231", \ |
"$232", "$233", "$234", "$235", "$236", "$237", "$238", "$239", \ |
"$240", "$241", "$242", "$243", "$244", "$245", "$246", "$247", \ |
"$248", "$249", "$250", "$251", "$252", "$253", "$254", "$255", \ |
":rD", ":rE", ":rH", ":rJ", ":rR", "ap_!BAD!", ":rO"} |
|
#define ADDITIONAL_REGISTER_NAMES \ |
{{"sp", 254}, {":sp", 254}, {"rD", 256}, {"rE", 257}, \ |
{"rH", 258}, {"rJ", MMIX_rJ_REGNUM}, {"rO", MMIX_rO_REGNUM}} |
|
#define PRINT_OPERAND(STREAM, X, CODE) \ |
mmix_print_operand (STREAM, X, CODE) |
|
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
mmix_print_operand_punct_valid_p (CODE) |
|
#define PRINT_OPERAND_ADDRESS(STREAM, X) \ |
mmix_print_operand_address (STREAM, X) |
|
#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ |
mmix_asm_output_reg_push (STREAM, REGNO) |
|
#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ |
mmix_asm_output_reg_pop (STREAM, REGNO) |
|
|
/* Node: Dispatch Tables */ |
|
/* We define both types, since SImode is the better, but DImode the only |
possible for mmixal so that's the one actually used. */ |
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ |
mmix_asm_output_addr_diff_elt (STREAM, BODY, VALUE, REL) |
|
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ |
mmix_asm_output_addr_vec_elt (STREAM, VALUE) |
|
|
/* Node: Exception Region Output */ |
/* (empty) */ |
|
/* Node: Alignment Output */ |
|
#define ASM_OUTPUT_SKIP(STREAM, NBYTES) \ |
mmix_asm_output_skip (STREAM, NBYTES) |
|
#define ASM_OUTPUT_ALIGN(STREAM, POWER) \ |
mmix_asm_output_align (STREAM, POWER) |
|
|
/* Node: All Debuggers */ |
|
#define DBX_REGISTER_NUMBER(REGNO) \ |
mmix_dbx_register_number (REGNO) |
|
|
/* Node: DBX Options */ |
/* (empty) */ |
/* Node: DBX Hooks */ |
/* (empty) */ |
/* Node: File Names and DBX */ |
/* (empty) */ |
|
|
/* Node: SDB and DWARF */ |
#define DWARF2_DEBUGGING_INFO 1 |
#define DWARF2_ASM_LINE_DEBUG_INFO 1 |
|
/* Node: Misc */ |
|
/* There's no way to get a PC-relative offset into tables for SImode, so |
for the moment we have absolute entries in DImode. |
When we're going ELF, these should be SImode and 1. */ |
#define CASE_VECTOR_MODE DImode |
#define CASE_VECTOR_PC_RELATIVE 0 |
|
#define WORD_REGISTER_OPERATIONS |
|
/* We have a choice, which makes this yet another parameter to tweak. The |
gut feeling is currently that SIGN_EXTEND wins; "int" is more frequent |
than "unsigned int", and we have signed characters. FIXME: measure. */ |
#define LOAD_EXTEND_OP(MODE) (TARGET_ZERO_EXTEND ? ZERO_EXTEND : SIGN_EXTEND) |
|
#define MOVE_MAX 8 |
|
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 |
|
/* ??? MMIX allows a choice of STORE_FLAG_VALUE. Revisit later, |
we don't have scc expanders yet. */ |
|
#define Pmode DImode |
|
#define FUNCTION_MODE QImode |
|
#define NO_IMPLICIT_EXTERN_C |
|
#define HANDLE_SYSV_PRAGMA 1 |
|
/* These are checked. */ |
#define DOLLARS_IN_IDENTIFIERS 0 |
#define NO_DOLLAR_IN_LABEL |
#define NO_DOT_IN_LABEL |
|
#endif /* GCC_MMIX_H */ |
/* |
* Local variables: |
* eval: (c-set-style "gnu") |
* indent-tabs-mode: t |
* End: |
*/ |
mmix.h
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: predicates.md
===================================================================
--- predicates.md (nonexistent)
+++ predicates.md (revision 384)
@@ -0,0 +1,155 @@
+;; Operand and operator predicates for the GCC MMIX port.
+;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;;
mmix-protos.h
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: crtn.asm
===================================================================
--- crtn.asm (nonexistent)
+++ crtn.asm (revision 384)
@@ -0,0 +1,87 @@
+/* Copyright (C) 2001, 2002, 2009 Free Software Foundation, Inc.
+ Contributed by Hans-Peter Nilsson
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 3, or (at your option) any
+later version.
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+General Public License for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ due to
+;; changes in loop optimization. The file machmode.def says they're of
+;; size 4 QI. Valid bit-patterns correspond to integers -1, 0 and 1, so
+;; we treat them as signed entities; see mmix-modes.def. The following
+;; expanders should cover all MODE_CC modes, and expand for this pattern.
+(define_insn "*movcc_expanded"
+ [(set (match_operand 0 "nonimmediate_operand" "=r,x,r,r,m")
+ (match_operand 1 "nonimmediate_operand" "r,r,x,m,r"))]
+ "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_CC
+ && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_CC"
+ "@
+ SET %0,%1
+ PUT %0,%1
+ GET %0,%1
+ LDT %0,%1
+ STT %1,%0")
+
+(define_expand "movcc"
+ [(set (match_operand:CC 0 "nonimmediate_operand" "")
+ (match_operand:CC 1 "nonimmediate_operand" ""))]
+ ""
+ "")
+
+(define_expand "movcc_uns"
+ [(set (match_operand:CC_UNS 0 "nonimmediate_operand" "")
+ (match_operand:CC_UNS 1 "nonimmediate_operand" ""))]
+ ""
+ "")
+
+(define_expand "movcc_fp"
+ [(set (match_operand:CC_FP 0 "nonimmediate_operand" "")
+ (match_operand:CC_FP 1 "nonimmediate_operand" ""))]
+ ""
+ "")
+
+(define_expand "movcc_fpeq"
+ [(set (match_operand:CC_FPEQ 0 "nonimmediate_operand" "")
+ (match_operand:CC_FPEQ 1 "nonimmediate_operand" ""))]
+ ""
+ "")
+
+(define_expand "movcc_fun"
+ [(set (match_operand:CC_FUN 0 "nonimmediate_operand" "")
+ (match_operand:CC_FUN 1 "nonimmediate_operand" ""))]
+ ""
+ "")
+
+(define_insn "adddi3"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r")
+ (plus:DI
+ (match_operand:DI 1 "register_operand" "%r,r,0")
+ (match_operand:DI 2 "mmix_reg_or_constant_operand" "rI,K,LS")))]
+ ""
+ "@
+ ADDU %0,%1,%2
+ SUBU %0,%1,%n2
+ %i2 %0,%v2")
+
+(define_insn "adddf3"
+ [(set (match_operand:DF 0 "register_operand" "=r")
+ (plus:DF (match_operand:DF 1 "register_operand" "%r")
+ (match_operand:DF 2 "register_operand" "r")))]
+ ""
+ "FADD %0,%1,%2")
+
+;; Insn canonicalization *should* have removed the need for an integer
+;; in operand 2.
+(define_insn "subdi3"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (minus:DI (match_operand:DI 1 "mmix_reg_or_8bit_operand" "r,I")
+ (match_operand:DI 2 "register_operand" "r,r")))]
+ ""
+ "@
+ SUBU %0,%1,%2
+ NEGU %0,%1,%2")
+
+(define_insn "subdf3"
+ [(set (match_operand:DF 0 "register_operand" "=r")
+ (minus:DF (match_operand:DF 1 "register_operand" "r")
+ (match_operand:DF 2 "register_operand" "r")))]
+ ""
+ "FSUB %0,%1,%2")
+
+;; FIXME: Should we define_expand and match 2, 4, 8 (etc) with shift (or
+;; %{something}2ADDU %0,%1,0)? Hopefully GCC should still handle it, so
+;; we don't have to taint the machine description. If results are bad
+;; enough, we may have to do it anyway.
+(define_insn "muldi3"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (mult:DI (match_operand:DI 1 "register_operand" "%r,r")
+ (match_operand:DI 2 "mmix_reg_or_8bit_operand" "O,rI")))
+ (clobber (match_scratch:DI 3 "=X,z"))]
+ ""
+ "@
+ %m2ADDU %0,%1,%1
+ MULU %0,%1,%2")
+
+(define_insn "muldf3"
+ [(set (match_operand:DF 0 "register_operand" "=r")
+ (mult:DF (match_operand:DF 1 "register_operand" "r")
+ (match_operand:DF 2 "register_operand" "r")))]
+ ""
+ "FMUL %0,%1,%2")
+
+(define_insn "divdf3"
+ [(set (match_operand:DF 0 "register_operand" "=r")
+ (div:DF (match_operand:DF 1 "register_operand" "r")
+ (match_operand:DF 2 "register_operand" "r")))]
+ ""
+ "FDIV %0,%1,%2")
+
+;; FIXME: Is "frem" doing the right operation for moddf3?
+(define_insn "moddf3"
+ [(set (match_operand:DF 0 "register_operand" "=r")
+ (mod:DF (match_operand:DF 1 "register_operand" "r")
+ (match_operand:DF 2 "register_operand" "r")))]
+ ""
+ "FREM %0,%1,%2")
+
+;; FIXME: Should we define_expand for smin, smax, umin, umax using a
+;; nifty conditional sequence?
+
+;; FIXME: The cuter andn combinations don't get here, presumably because
+;; they ended up in the constant pool. Check: still?
+(define_insn "anddi3"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (and:DI
+ (match_operand:DI 1 "register_operand" "%r,0")
+ (match_operand:DI 2 "mmix_reg_or_constant_operand" "rI,NT")))]
+ ""
+ "@
+ AND %0,%1,%2
+ %A2 %0,%V2")
+
+(define_insn "iordi3"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (ior:DI (match_operand:DI 1 "register_operand" "%r,0")
+ (match_operand:DI 2 "mmix_reg_or_constant_operand" "rH,LS")))]
+ ""
+ "@
+ OR %0,%1,%2
+ %o2 %0,%v2")
+
+(define_insn "xordi3"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (xor:DI (match_operand:DI 1 "register_operand" "%r")
+ (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))]
+ ""
+ "XOR %0,%1,%2")
+
+;; FIXME: When TImode works for other reasons (like cross-compiling from
+;; a 32-bit host), add back umulditi3 and umuldi3_highpart here.
+
+;; FIXME: Check what's really reasonable for the mod part.
+
+;; One day we might persuade GCC to expand divisions with constants the
+;; way MMIX does; giving the remainder the sign of the divisor. But even
+;; then, it might be good to have an option to divide the way "everybody
+;; else" does. Perhaps then, this option can be on by default. However,
+;; it's not likely to happen because major (C, C++, Fortran) language
+;; standards in effect at 2002-04-29 reportedly demand that the sign of
+;; the remainder must follow the sign of the dividend.
+
+(define_insn "divmoddi4"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (div:DI (match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))
+ (set (match_operand:DI 3 "register_operand" "=y")
+ (mod:DI (match_dup 1) (match_dup 2)))]
+ ;; Do the library stuff later.
+ "TARGET_KNUTH_DIVISION"
+ "DIV %0,%1,%2")
+
+(define_insn "udivmoddi4"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (udiv:DI (match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))
+ (set (match_operand:DI 3 "register_operand" "=y")
+ (umod:DI (match_dup 1) (match_dup 2)))]
+ ""
+ "DIVU %0,%1,%2")
+
+(define_expand "divdi3"
+ [(parallel
+ [(set (match_operand:DI 0 "register_operand" "=&r")
+ (div:DI (match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "register_operand" "r")))
+ (clobber (scratch:DI))
+ (clobber (scratch:DI))
+ (clobber (reg:DI MMIX_rR_REGNUM))])]
+ "! TARGET_KNUTH_DIVISION"
+ "")
+
+;; The %2-is-%1-case is there just to make sure things don't fail. Could
+;; presumably happen with optimizations off; no evidence.
+(define_insn "*divdi3_nonknuth"
+ [(set (match_operand:DI 0 "register_operand" "=&r,&r")
+ (div:DI (match_operand:DI 1 "register_operand" "r,r")
+ (match_operand:DI 2 "register_operand" "1,r")))
+ (clobber (match_scratch:DI 3 "=1,1"))
+ (clobber (match_scratch:DI 4 "=2,2"))
+ (clobber (reg:DI MMIX_rR_REGNUM))]
+ "! TARGET_KNUTH_DIVISION"
+ "@
+ SETL %0,1
+ XOR $255,%1,%2\;NEGU %0,0,%2\;CSN %2,%2,%0\;NEGU %0,0,%1\;CSN %1,%1,%0\;\
+DIVU %0,%1,%2\;NEGU %1,0,%0\;CSN %0,$255,%1")
+
+(define_expand "moddi3"
+ [(parallel
+ [(set (match_operand:DI 0 "register_operand" "=&r")
+ (mod:DI (match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "register_operand" "r")))
+ (clobber (scratch:DI))
+ (clobber (scratch:DI))
+ (clobber (reg:DI MMIX_rR_REGNUM))])]
+ "! TARGET_KNUTH_DIVISION"
+ "")
+
+;; The %2-is-%1-case is there just to make sure things don't fail. Could
+;; presumably happen with optimizations off; no evidence.
+(define_insn "*moddi3_nonknuth"
+ [(set (match_operand:DI 0 "register_operand" "=&r,&r")
+ (mod:DI (match_operand:DI 1 "register_operand" "r,r")
+ (match_operand:DI 2 "register_operand" "1,r")))
+ (clobber (match_scratch:DI 3 "=1,1"))
+ (clobber (match_scratch:DI 4 "=2,2"))
+ (clobber (reg:DI MMIX_rR_REGNUM))]
+ "! TARGET_KNUTH_DIVISION"
+ "@
+ SETL %0,0
+ NEGU %0,0,%2\;CSN %2,%2,%0\;NEGU $255,0,%1\;CSN %1,%1,$255\;\
+DIVU %1,%1,%2\;GET %0,:rR\;NEGU %2,0,%0\;CSNN %0,$255,%2")
+
+(define_insn "ashldi3"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (ashift:DI
+ (match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))]
+ ""
+ "SLU %0,%1,%2")
+
+(define_insn "ashrdi3"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (ashiftrt:DI
+ (match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))]
+ ""
+ "SR %0,%1,%2")
+
+(define_insn "lshrdi3"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (lshiftrt:DI
+ (match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))]
+ ""
+ "SRU %0,%1,%2")
+
+(define_insn "negdi2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (neg:DI (match_operand:DI 1 "register_operand" "r")))]
+ ""
+ "NEGU %0,0,%1")
+
+(define_expand "negdf2"
+ [(parallel [(set (match_operand:DF 0 "register_operand" "=r")
+ (neg:DF (match_operand:DF 1 "register_operand" "r")))
+ (use (match_dup 2))])]
+ ""
+{
+ /* Emit bit-flipping sequence to be IEEE-safe wrt. -+0. */
+ operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
+})
+
+(define_insn "*expanded_negdf2"
+ [(set (match_operand:DF 0 "register_operand" "=r")
+ (neg:DF (match_operand:DF 1 "register_operand" "r")))
+ (use (match_operand:DI 2 "register_operand" "r"))]
+ ""
+ "XOR %0,%1,%2")
+
+;; FIXME: define_expand for absdi2?
+
+(define_insn "absdf2"
+ [(set (match_operand:DF 0 "register_operand" "=r")
+ (abs:DF (match_operand:DF 1 "register_operand" "0")))]
+ ""
+ "ANDNH %0,#8000")
+
+(define_insn "sqrtdf2"
+ [(set (match_operand:DF 0 "register_operand" "=r")
+ (sqrt:DF (match_operand:DF 1 "register_operand" "r")))]
+ ""
+ "FSQRT %0,%1")
+
+;; FIXME: define_expand for ffssi2? (not ffsdi2 since int is SImode).
+
+(define_insn "one_cmpldi2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (not:DI (match_operand:DI 1 "register_operand" "r")))]
+ ""
+ "NOR %0,%1,0")
+
+;; When the user-patterns expand, the resulting insns will match the
+;; patterns below.
+
+;; We can fold the signed-compare where the register value is
+;; already equal to (compare:CCTYPE (reg) (const_int 0)).
+;; We can't do that at all for floating-point, due to NaN, +0.0
+;; and -0.0, and we can only do it for the non/zero test of
+;; unsigned, so that has to be done another way.
+;; FIXME: Perhaps a peep2 changing CCcode to a new code, that
+;; gets folded here.
+(define_insn "*cmpdi_folded"
+ [(set (match_operand:CC 0 "register_operand" "=r")
+ (compare:CC
+ (match_operand:DI 1 "register_operand" "r")
+ (const_int 0)))]
+ ;; FIXME: Can we test equivalence any other way?
+ ;; FIXME: Can we fold any other way?
+ "REG_P (operands[0]) && REG_P (operands[1])
+ && REGNO (operands[1]) == REGNO (operands[0])"
+ "%% folded: cmp %0,%1,0")
+
+(define_insn "*cmps"
+ [(set (match_operand:CC 0 "register_operand" "=r")
+ (compare:CC
+ (match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))]
+ ""
+ "CMP %0,%1,%2")
+
+(define_insn "*cmpu"
+ [(set (match_operand:CC_UNS 0 "register_operand" "=r")
+ (compare:CC_UNS
+ (match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI")))]
+ ""
+ "CMPU %0,%1,%2")
+
+(define_insn "*fcmp"
+ [(set (match_operand:CC_FP 0 "register_operand" "=r")
+ (compare:CC_FP
+ (match_operand:DF 1 "register_operand" "r")
+ (match_operand:DF 2 "register_operand" "r")))]
+ ""
+ "FCMP%e0 %0,%1,%2")
+
+;; FIXME: for -mieee, add fsub %0,%1,%1\;fsub %0,%2,%2 before to
+;; make signalling compliant.
+(define_insn "*feql"
+ [(set (match_operand:CC_FPEQ 0 "register_operand" "=r")
+ (compare:CC_FPEQ
+ (match_operand:DF 1 "register_operand" "r")
+ (match_operand:DF 2 "register_operand" "r")))]
+ ""
+ "FEQL%e0 %0,%1,%2")
+
+(define_insn "*fun"
+ [(set (match_operand:CC_FUN 0 "register_operand" "=r")
+ (compare:CC_FUN
+ (match_operand:DF 1 "register_operand" "r")
+ (match_operand:DF 2 "register_operand" "r")))]
+ ""
+ "FUN%e0 %0,%1,%2")
+
+;; In order to get correct rounding, we have to use SFLOT and SFLOTU for
+;; conversion. They do not convert to SFmode; they convert to DFmode,
+;; with rounding as of SFmode. They are not usable as is, but we pretend
+;; we have a single instruction but emit two.
+
+;; Note that this will (somewhat unexpectedly) create an inexact
+;; exception if rounding is necessary - has to be masked off in crt0?
+(define_expand "floatdisf2"
+ [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "=rm")
+ (float:SF
+ (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI")))
+ ;; Let's use a DI scratch, since SF don't generally get into
+ ;; registers. Dunno what's best; it's really a DF, but that
+ ;; doesn't logically follow from operands in the pattern.
+ (clobber (match_scratch:DI 2 "=&r"))])]
+ ""
+ "
+{
+ if (GET_CODE (operands[0]) != MEM)
+ {
+ rtx stack_slot;
+
+ /* FIXME: This stack-slot remains even at -O3. There must be a
+ better way. */
+ stack_slot
+ = validize_mem (assign_stack_temp (SFmode,
+ GET_MODE_SIZE (SFmode), 0));
+ emit_insn (gen_floatdisf2 (stack_slot, operands[1]));
+ emit_move_insn (operands[0], stack_slot);
+ DONE;
+ }
+}")
+
+(define_insn "*floatdisf2_real"
+ [(set (match_operand:SF 0 "memory_operand" "=m")
+ (float:SF
+ (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI")))
+ (clobber (match_scratch:DI 2 "=&r"))]
+ ""
+ "SFLOT %2,%1\;STSF %2,%0")
+
+(define_expand "floatunsdisf2"
+ [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "=rm")
+ (unsigned_float:SF
+ (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI")))
+ ;; Let's use a DI scratch, since SF don't generally get into
+ ;; registers. Dunno what's best; it's really a DF, but that
+ ;; doesn't logically follow from operands in the pattern.
+ (clobber (scratch:DI))])]
+ ""
+ "
+{
+ if (GET_CODE (operands[0]) != MEM)
+ {
+ rtx stack_slot;
+
+ /* FIXME: This stack-slot remains even at -O3. Must be a better
+ way. */
+ stack_slot
+ = validize_mem (assign_stack_temp (SFmode,
+ GET_MODE_SIZE (SFmode), 0));
+ emit_insn (gen_floatunsdisf2 (stack_slot, operands[1]));
+ emit_move_insn (operands[0], stack_slot);
+ DONE;
+ }
+}")
+
+(define_insn "*floatunsdisf2_real"
+ [(set (match_operand:SF 0 "memory_operand" "=m")
+ (unsigned_float:SF
+ (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI")))
+ (clobber (match_scratch:DI 2 "=&r"))]
+ ""
+ "SFLOTU %2,%1\;STSF %2,%0")
+
+;; Note that this will (somewhat unexpectedly) create an inexact
+;; exception if rounding is necessary - has to be masked off in crt0?
+(define_insn "floatdidf2"
+ [(set (match_operand:DF 0 "register_operand" "=r")
+ (float:DF
+ (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI")))]
+ ""
+ "FLOT %0,%1")
+
+(define_insn "floatunsdidf2"
+ [(set (match_operand:DF 0 "register_operand" "=r")
+ (unsigned_float:DF
+ (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI")))]
+ ""
+ "FLOTU %0,%1")
+
+(define_insn "ftruncdf2"
+ [(set (match_operand:DF 0 "register_operand" "=r")
+ (fix:DF (match_operand:DF 1 "register_operand" "r")))]
+ ""
+ ;; ROUND_OFF
+ "FINT %0,1,%1")
+
+;; Note that this will (somewhat unexpectedly) create an inexact
+;; exception if rounding is necessary - has to be masked off in crt0?
+(define_insn "fix_truncdfdi2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "r"))))]
+ ""
+ ;; ROUND_OFF
+ "FIX %0,1,%1")
+
+(define_insn "fixuns_truncdfdi2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unsigned_fix:DI
+ (fix:DF (match_operand:DF 1 "register_operand" "r"))))]
+ ""
+ ;; ROUND_OFF
+ "FIXU %0,1,%1")
+
+;; It doesn't seem like it's possible to have memory_operand as a
+;; predicate here (testcase: libgcc2 floathisf). FIXME: Shouldn't it be
+;; possible to do that? Bug in GCC? Anyway, this used to be a simple
+;; pattern with a memory_operand predicate, but was split up with a
+;; define_expand with the old pattern as "anonymous".
+;; FIXME: Perhaps with SECONDARY_MEMORY_NEEDED?
+(define_expand "truncdfsf2"
+ [(set (match_operand:SF 0 "memory_operand" "")
+ (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
+ ""
+ "
+{
+ if (GET_CODE (operands[0]) != MEM)
+ {
+ /* FIXME: There should be a way to say: 'put this in operands[0]
+ but *after* the expanded insn'. */
+ rtx stack_slot;
+
+ /* There is no sane destination but a register here, if it wasn't
+ already MEM. (It's too hard to get fatal_insn to work here.) */
+ if (! REG_P (operands[0]))
+ internal_error (\"MMIX Internal: Bad truncdfsf2 expansion\");
+
+ /* FIXME: This stack-slot remains even at -O3. Must be a better
+ way. */
+ stack_slot
+ = validize_mem (assign_stack_temp (SFmode,
+ GET_MODE_SIZE (SFmode), 0));
+ emit_insn (gen_truncdfsf2 (stack_slot, operands[1]));
+ emit_move_insn (operands[0], stack_slot);
+ DONE;
+ }
+}")
+
+(define_insn "*truncdfsf2_real"
+ [(set (match_operand:SF 0 "memory_operand" "=m")
+ (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
+ ""
+ "STSF %1,%0")
+
+;; Same comment as for truncdfsf2.
+(define_expand "extendsfdf2"
+ [(set (match_operand:DF 0 "register_operand" "=r")
+ (float_extend:DF (match_operand:SF 1 "memory_operand" "m")))]
+ ""
+ "
+{
+ if (GET_CODE (operands[1]) != MEM)
+ {
+ rtx stack_slot;
+
+ /* There is no sane destination but a register here, if it wasn't
+ already MEM. (It's too hard to get fatal_insn to work here.) */
+ if (! REG_P (operands[0]))
+ internal_error (\"MMIX Internal: Bad extendsfdf2 expansion\");
+
+ /* FIXME: This stack-slot remains even at -O3. There must be a
+ better way. */
+ stack_slot
+ = validize_mem (assign_stack_temp (SFmode,
+ GET_MODE_SIZE (SFmode), 0));
+ emit_move_insn (stack_slot, operands[1]);
+ emit_insn (gen_extendsfdf2 (operands[0], stack_slot));
+ DONE;
+ }
+}")
+
+(define_insn "*extendsfdf2_real"
+ [(set (match_operand:DF 0 "register_operand" "=r")
+ (float_extend:DF (match_operand:SF 1 "memory_operand" "m")))]
+ ""
+ "LDSF %0,%1")
+
+;; Neither sign-extend nor zero-extend are necessary; gcc knows how to
+;; synthesize using shifts or and, except with a memory source and not
+;; completely optimal. FIXME: Actually, other bugs surface when those
+;; patterns are defined; fix later.
+
+;; There are no sane values with the bit-patterns of (int) 0..255 except
+;; 0 to use in movdfcc.
+
+(define_expand "movdfcc"
+ [(set (match_dup 4) (match_dup 5))
+ (set (match_operand:DF 0 "register_operand" "")
+ (if_then_else:DF
+ (match_operand 1 "comparison_operator" "")
+ (match_operand:DF 2 "mmix_reg_or_0_operand" "")
+ (match_operand:DF 3 "mmix_reg_or_0_operand" "")))]
+ ""
+ "
+{
+ enum rtx_code code = GET_CODE (operands[1]);
+ if (code == LE || code == GE)
+ FAIL;
+
+ operands[4] = mmix_gen_compare_reg (code, XEXP (operands[1], 0),
+ XEXP (operands[1], 1));
+ operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
+ XEXP (operands[1], 0),
+ XEXP (operands[1], 1));
+ operands[1] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
+}")
+
+(define_expand "movdicc"
+ [(set (match_dup 4) (match_dup 5))
+ (set (match_operand:DI 0 "register_operand" "")
+ (if_then_else:DI
+ (match_operand 1 "comparison_operator" "")
+ (match_operand:DI 2 "mmix_reg_or_8bit_operand" "")
+ (match_operand:DI 3 "mmix_reg_or_8bit_operand" "")))]
+ ""
+ "
+{
+ enum rtx_code code = GET_CODE (operands[1]);
+ if (code == LE || code == GE)
+ FAIL;
+
+ operands[4] = mmix_gen_compare_reg (code, XEXP (operands[1], 0),
+ XEXP (operands[1], 1));
+ operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
+ XEXP (operands[1], 0),
+ XEXP (operands[1], 1));
+ operands[1] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
+}")
+
+;; FIXME: Is this the right way to do "folding" of CCmode -> DImode?
+(define_insn "*movdicc_real_foldable"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
+ (if_then_else:DI
+ (match_operator 2 "mmix_foldable_comparison_operator"
+ [(match_operand:DI 3 "register_operand" "r,r,r,r")
+ (const_int 0)])
+ (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI,0 ,rI,GM")
+ (match_operand:DI 4 "mmix_reg_or_8bit_operand" "0 ,rI,GM,rI")))]
+ ""
+ "@
+ CS%d2 %0,%3,%1
+ CS%D2 %0,%3,%4
+ ZS%d2 %0,%3,%1
+ ZS%D2 %0,%3,%4")
+
+(define_insn "*movdicc_real_reversible"
+ [(set
+ (match_operand:DI 0 "register_operand" "=r ,r ,r ,r")
+ (if_then_else:DI
+ (match_operator
+ 2 "mmix_comparison_operator"
+ [(match_operand 3 "mmix_reg_cc_operand" "r ,r ,r ,r")
+ (const_int 0)])
+ (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI,0 ,rI,GM")
+ (match_operand:DI 4 "mmix_reg_or_8bit_operand" "0 ,rI,GM,rI")))]
+ "REVERSIBLE_CC_MODE (GET_MODE (operands[3]))"
+ "@
+ CS%d2 %0,%3,%1
+ CS%D2 %0,%3,%4
+ ZS%d2 %0,%3,%1
+ ZS%D2 %0,%3,%4")
+
+(define_insn "*movdicc_real_nonreversible"
+ [(set
+ (match_operand:DI 0 "register_operand" "=r ,r")
+ (if_then_else:DI
+ (match_operator
+ 2 "mmix_comparison_operator"
+ [(match_operand 3 "mmix_reg_cc_operand" "r ,r")
+ (const_int 0)])
+ (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI,rI")
+ (match_operand:DI 4 "mmix_reg_or_0_operand" "0 ,GM")))]
+ "!REVERSIBLE_CC_MODE (GET_MODE (operands[3]))"
+ "@
+ CS%d2 %0,%3,%1
+ ZS%d2 %0,%3,%1")
+
+(define_insn "*movdfcc_real_foldable"
+ [(set
+ (match_operand:DF 0 "register_operand" "=r ,r ,r ,r")
+ (if_then_else:DF
+ (match_operator
+ 2 "mmix_foldable_comparison_operator"
+ [(match_operand:DI 3 "register_operand" "r ,r ,r ,r")
+ (const_int 0)])
+ (match_operand:DF 1 "mmix_reg_or_0_operand" "rGM,0 ,rGM,GM")
+ (match_operand:DF 4 "mmix_reg_or_0_operand" "0 ,rGM,GM ,rGM")))]
+ ""
+ "@
+ CS%d2 %0,%3,%1
+ CS%D2 %0,%3,%4
+ ZS%d2 %0,%3,%1
+ ZS%D2 %0,%3,%4")
+
+(define_insn "*movdfcc_real_reversible"
+ [(set
+ (match_operand:DF 0 "register_operand" "=r ,r ,r ,r")
+ (if_then_else:DF
+ (match_operator
+ 2 "mmix_comparison_operator"
+ [(match_operand 3 "mmix_reg_cc_operand" "r ,r ,r ,r")
+ (const_int 0)])
+ (match_operand:DF 1 "mmix_reg_or_0_operand" "rGM,0 ,rGM,GM")
+ (match_operand:DF 4 "mmix_reg_or_0_operand" "0 ,rGM,GM ,rGM")))]
+ "REVERSIBLE_CC_MODE (GET_MODE (operands[3]))"
+ "@
+ CS%d2 %0,%3,%1
+ CS%D2 %0,%3,%4
+ ZS%d2 %0,%3,%1
+ ZS%D2 %0,%3,%4")
+
+(define_insn "*movdfcc_real_nonreversible"
+ [(set
+ (match_operand:DF 0 "register_operand" "=r ,r")
+ (if_then_else:DF
+ (match_operator
+ 2 "mmix_comparison_operator"
+ [(match_operand 3 "mmix_reg_cc_operand" "r ,r")
+ (const_int 0)])
+ (match_operand:DF 1 "mmix_reg_or_0_operand" "rGM,rGM")
+ (match_operand:DF 4 "mmix_reg_or_0_operand" "0 ,GM")))]
+ "!REVERSIBLE_CC_MODE (GET_MODE (operands[3]))"
+ "@
+ CS%d2 %0,%3,%1
+ ZS%d2 %0,%3,%1")
+
+;; FIXME: scc insns will probably help, I just skip them
+;; right now. Revisit.
+
+(define_expand "cbranchdi4"
+ [(set (match_dup 4)
+ (match_op_dup 5
+ [(match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "mmix_reg_or_8bit_operand" "")]))
+ (set (pc)
+ (if_then_else
+ (match_operator 0 "ordered_comparison_operator"
+ [(match_dup 4)
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ ""
+ "
+{
+ operands[4] = mmix_gen_compare_reg (GET_CODE (operands[0]),
+ operands[1], operands[2]);
+ operands[5] = gen_rtx_fmt_ee (COMPARE,
+ GET_MODE (operands[4]),
+ operands[1], operands[2]);
+}")
+
+(define_expand "cbranchdf4"
+ [(set (match_dup 4)
+ (match_op_dup 5
+ [(match_operand:DF 1 "register_operand" "")
+ (match_operand:DF 2 "register_operand" "")]))
+ (set (pc)
+ (if_then_else
+ (match_operator 0 "float_comparison_operator"
+ [(match_dup 4)
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ ""
+ "
+{
+ /* The head comment of optabs.c:can_compare_p says we're required to
+ implement this, so we have to clean up the mess here. */
+ if (GET_CODE (operands[0]) == LE || GET_CODE (operands[0]) == GE)
+ {
+ enum rtx_code ltgt_code = GET_CODE (operands[0]) == LE ? LT : GT;
+ emit_cmp_and_jump_insns (operands[1], operands[2], ltgt_code, NULL_RTX,
+ DFmode, 0, operands[3]);
+ emit_cmp_and_jump_insns (operands[1], operands[2], EQ, NULL_RTX,
+ DFmode, 0, operands[3]);
+ DONE;
+ }
+
+ operands[4] = mmix_gen_compare_reg (GET_CODE (operands[0]),
+ operands[1], operands[2]);
+ operands[5] = gen_rtx_fmt_ee (COMPARE,
+ GET_MODE (operands[4]),
+ operands[1], operands[2]);
+}")
+
+
+;; FIXME: we can emit an unordered-or-*not*-equal compare in one insn, but
+;; there's no RTL code for it. Maybe revisit in future.
+
+;; FIXME: Odd/Even matchers?
+(define_insn "*bCC_foldable"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "mmix_foldable_comparison_operator"
+ [(match_operand:DI 2 "register_operand" "r")
+ (const_int 0)])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ ""
+ "%+B%d1 %2,%0")
+
+(define_insn "*bCC"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "mmix_comparison_operator"
+ [(match_operand 2 "mmix_reg_cc_operand" "r")
+ (const_int 0)])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ ""
+ "%+B%d1 %2,%0")
+
+(define_insn "*bCC_inverted_foldable"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "mmix_foldable_comparison_operator"
+ [(match_operand:DI 2 "register_operand" "r")
+ (const_int 0)])
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+;; REVERSIBLE_CC_MODE is checked by mmix_foldable_comparison_operator.
+ ""
+ "%+B%D1 %2,%0")
+
+(define_insn "*bCC_inverted"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "mmix_comparison_operator"
+ [(match_operand 2 "mmix_reg_cc_operand" "r")
+ (const_int 0)])
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ "REVERSIBLE_CC_MODE (GET_MODE (operands[2]))"
+ "%+B%D1 %2,%0")
+
+(define_expand "call"
+ [(parallel [(call (match_operand:QI 0 "memory_operand" "")
+ (match_operand 1 "general_operand" ""))
+ (use (match_operand 2 "general_operand" ""))
+ (clobber (match_dup 4))])
+ (set (match_dup 4) (match_dup 3))]
+ ""
+ "
+{
+ /* The caller checks that the operand is generally valid as an
+ address, but at -O0 nothing makes sure that it's also a valid
+ call address for a *call*; a mmix_symbolic_or_address_operand.
+ Force into a register if it isn't. */
+ if (!mmix_symbolic_or_address_operand (XEXP (operands[0], 0),
+ GET_MODE (XEXP (operands[0], 0))))
+ operands[0]
+ = replace_equiv_address (operands[0],
+ force_reg (Pmode, XEXP (operands[0], 0)));
+
+ /* Since the epilogue 'uses' the return address, and it is clobbered
+ in the call, and we set it back after every call (all but one setting
+ will be optimized away), integrity is maintained. */
+ operands[3]
+ = mmix_get_hard_reg_initial_val (Pmode,
+ MMIX_INCOMING_RETURN_ADDRESS_REGNUM);
+
+ /* FIXME: There's a bug in gcc which causes NULL to be passed as
+ operand[2] when we get out of registers, which later confuses gcc.
+ Work around it by replacing it with const_int 0. Possibly documentation
+ error too. */
+ if (operands[2] == NULL_RTX)
+ operands[2] = const0_rtx;
+
+ operands[4] = gen_rtx_REG (DImode, MMIX_INCOMING_RETURN_ADDRESS_REGNUM);
+}")
+
+(define_expand "call_value"
+ [(parallel [(set (match_operand 0 "" "")
+ (call (match_operand:QI 1 "memory_operand" "")
+ (match_operand 2 "general_operand" "")))
+ (use (match_operand 3 "general_operand" ""))
+ (clobber (match_dup 5))])
+ (set (match_dup 5) (match_dup 4))]
+ ""
+ "
+{
+ /* The caller checks that the operand is generally valid as an
+ address, but at -O0 nothing makes sure that it's also a valid
+ call address for a *call*; a mmix_symbolic_or_address_operand.
+ Force into a register if it isn't. */
+ if (!mmix_symbolic_or_address_operand (XEXP (operands[1], 0),
+ GET_MODE (XEXP (operands[1], 0))))
+ operands[1]
+ = replace_equiv_address (operands[1],
+ force_reg (Pmode, XEXP (operands[1], 0)));
+
+ /* Since the epilogue 'uses' the return address, and it is clobbered
+ in the call, and we set it back after every call (all but one setting
+ will be optimized away), integrity is maintained. */
+ operands[4]
+ = mmix_get_hard_reg_initial_val (Pmode,
+ MMIX_INCOMING_RETURN_ADDRESS_REGNUM);
+
+ /* FIXME: See 'call'. */
+ if (operands[3] == NULL_RTX)
+ operands[3] = const0_rtx;
+
+ /* FIXME: Documentation bug: operands[3] (operands[2] for 'call') is the
+ *next* argument register, not the number of arguments in registers.
+ (There used to be code here where that mattered.) */
+
+ operands[5] = gen_rtx_REG (DImode, MMIX_INCOMING_RETURN_ADDRESS_REGNUM);
+}")
+
+;; Don't use 'p' here. A 'p' must stand first in constraints, or reload
+;; messes up, not registering the address for reload. Several C++
+;; testcases, including g++.brendan/crash40.C. FIXME: This is arguably a
+;; bug in gcc. Note line ~2612 in reload.c, that does things on the
+;; condition <> and the comment on
+;; ~3017 that says:
+;; << case 'p':
+;; /* All necessary reloads for an address_operand
+;; were handled in find_reloads_address. */>>
+;; Sorry, I have not dug deeper. If symbolic addresses are used
+;; rarely compared to addresses in registers, disparaging the
+;; first ("p") alternative by adding ? in the first operand
+;; might do the trick. We define 'U' as a synonym to 'p', but without the
+;; caveats (and very small advantages) of 'p'.
+(define_insn "*call_real"
+ [(call (mem:QI
+ (match_operand:DI 0 "mmix_symbolic_or_address_operand" "s,rU"))
+ (match_operand 1 "" ""))
+ (use (match_operand 2 "" ""))
+ (clobber (reg:DI MMIX_rJ_REGNUM))]
+ ""
+ "@
+ PUSHJ $%p2,%0
+ PUSHGO $%p2,%a0")
+
+(define_insn "*call_value_real"
+ [(set (match_operand 0 "register_operand" "=r,r")
+ (call (mem:QI
+ (match_operand:DI 1 "mmix_symbolic_or_address_operand" "s,rU"))
+ (match_operand 2 "" "")))
+ (use (match_operand 3 "" ""))
+ (clobber (reg:DI MMIX_rJ_REGNUM))]
+ ""
+ "@
+ PUSHJ $%p3,%1
+ PUSHGO $%p3,%a1")
+
+;; I hope untyped_call and untyped_return are not needed for MMIX.
+;; Users of Objective-C will notice.
+
+; Generated by GCC.
+(define_expand "return"
+ [(return)]
+ "mmix_use_simple_return ()"
+ "")
+
+; Generated by the epilogue expander.
+(define_insn "*expanded_return"
+ [(return)]
+ ""
+ "POP %.,0")
+
+(define_expand "prologue"
+ [(const_int 0)]
+ ""
+ "mmix_expand_prologue (); DONE;")
+
+; Note that the (return) from the expander itself is always the last insn
+; in the epilogue.
+(define_expand "epilogue"
+ [(return)]
+ ""
+ "mmix_expand_epilogue ();")
+
+(define_insn "nop"
+ [(const_int 0)]
+ ""
+ "SWYM 0,0,0")
+
+(define_insn "jump"
+ [(set (pc) (label_ref (match_operand 0 "" "")))]
+ ""
+ "JMP %0")
+
+(define_insn "indirect_jump"
+ [(set (pc) (match_operand 0 "address_operand" "p"))]
+ ""
+ "GO $255,%a0")
+
+;; FIXME: This is just a jump, and should be expanded to one.
+(define_insn "tablejump"
+ [(set (pc) (match_operand:DI 0 "address_operand" "p"))
+ (use (label_ref (match_operand 1 "" "")))]
+ ""
+ "GO $255,%a0")
+
+;; The only peculiar thing is that the register stack has to be unwound at
+;; nonlocal_goto_receiver. At each function that has a nonlocal label, we
+;; save at function entry the location of the "alpha" register stack
+;; pointer, rO, in a stack slot known to that function (right below where
+;; the frame-pointer would be located).
+;; In the nonlocal goto receiver, we unwind the register stack by a series
+;; of "pop 0,0" until rO equals the saved value. (If it goes lower, we
+;; should die with a trap.)
+(define_expand "nonlocal_goto_receiver"
+ [(parallel [(unspec_volatile [(const_int 0)] 1)
+ (clobber (scratch:DI))
+ (clobber (reg:DI MMIX_rJ_REGNUM))])
+ (set (reg:DI MMIX_rJ_REGNUM) (match_dup 0))]
+ ""
+ "
+{
+ operands[0]
+ = mmix_get_hard_reg_initial_val (Pmode,
+ MMIX_INCOMING_RETURN_ADDRESS_REGNUM);
+
+ /* Mark this function as containing a landing-pad. */
+ cfun->machine->has_landing_pad = 1;
+}")
+
+;; GCC can insist on using saved registers to keep the slot address in
+;; "across" the exception, or (perhaps) to use saved registers in the
+;; address and re-use them after the register stack unwind, so it's best
+;; to form the address ourselves.
+(define_insn "*nonlocal_goto_receiver_expanded"
+ [(unspec_volatile [(const_int 0)] 1)
+ (clobber (match_scratch:DI 0 "=&r"))
+ (clobber (reg:DI MMIX_rJ_REGNUM))]
+ ""
+{
+ rtx temp_reg = operands[0];
+ rtx my_operands[2];
+ HOST_WIDEST_INT offs;
+ const char *my_template
+ = "GETA $255,0f\;PUT rJ,$255\;LDOU $255,%a0\n\
+0:\;GET %1,rO\;CMPU %1,%1,$255\;BNP %1,1f\;POP 0,0\n1:";
+
+ my_operands[1] = temp_reg;
+
+ /* If we have a frame-pointer (hence unknown stack-pointer offset),
+ just use the frame-pointer and the known offset. */
+ if (frame_pointer_needed)
+ {
+ my_operands[0] = GEN_INT (-MMIX_fp_rO_OFFSET);
+
+ output_asm_insn ("NEGU %1,0,%0", my_operands);
+ my_operands[0] = gen_rtx_PLUS (Pmode, frame_pointer_rtx, temp_reg);
+ }
+ else
+ {
+ /* We know the fp-based offset, so "eliminate" it to be sp-based. */
+ offs
+ = (mmix_initial_elimination_offset (MMIX_FRAME_POINTER_REGNUM,
+ MMIX_STACK_POINTER_REGNUM)
+ + MMIX_fp_rO_OFFSET);
+
+ if (offs >= 0 && offs <= 255)
+ my_operands[0]
+ = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offs));
+ else
+ {
+ mmix_output_register_setting (asm_out_file, REGNO (temp_reg),
+ offs, 1);
+ my_operands[0] = gen_rtx_PLUS (Pmode, stack_pointer_rtx, temp_reg);
+ }
+ }
+
+ output_asm_insn (my_template, my_operands);
+ return "";
+})
+
+(define_insn "*Naddu"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "const_int_operand" "n"))
+ (match_operand:DI 3 "mmix_reg_or_8bit_operand" "rI")))]
+ "GET_CODE (operands[2]) == CONST_INT
+ && (INTVAL (operands[2]) == 2
+ || INTVAL (operands[2]) == 4
+ || INTVAL (operands[2]) == 8
+ || INTVAL (operands[2]) == 16)"
+ "%2ADDU %0,%1,%3")
+
+(define_insn "*andn"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (and:DI
+ (not:DI (match_operand:DI 1 "mmix_reg_or_8bit_operand" "rI"))
+ (match_operand:DI 2 "register_operand" "r")))]
+ ""
+ "ANDN %0,%2,%1")
+
+(define_insn "*nand"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (ior:DI
+ (not:DI (match_operand:DI 1 "register_operand" "%r"))
+ (not:DI (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI"))))]
+ ""
+ "NAND %0,%1,%2")
+
+(define_insn "*nor"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (and:DI
+ (not:DI (match_operand:DI 1 "register_operand" "%r"))
+ (not:DI (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI"))))]
+ ""
+ "NOR %0,%1,%2")
+
+(define_insn "*nxor"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (not:DI
+ (xor:DI (match_operand:DI 1 "register_operand" "%r")
+ (match_operand:DI 2 "mmix_reg_or_8bit_operand" "rI"))))]
+ ""
+ "NXOR %0,%1,%2")
+
+(define_insn "sync_icache"
+ [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")
+ (match_operand:DI 1 "const_int_operand" "I")] 0)]
+ ""
+ "SYNCID %1,%0")
+
+;; Local Variables:
+;; mode: lisp
+;; indent-tabs-mode: t
+;; End:
Index: mmix.c
===================================================================
--- mmix.c (nonexistent)
+++ mmix.c (revision 384)
@@ -0,0 +1,2745 @@
+/* Definitions of target machine for GNU compiler, for MMIX.
+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+ Free Software Foundation, Inc.
+ Contributed by Hans-Peter Nilsson (hp@bitrange.com)
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+
+ syntax is used (which works for aligned data too). We actually
+ *must* do that, since we say we don't have simple aligned
+ pseudos, causing this function to be called. We just try and
+ keep as much compatibility as possible with mmixal syntax for
+ normal cases (i.e. without GNU extensions and C only). */
+ case 1:
+ if (GET_CODE (x) != CONST_INT)
+ {
+ aligned_p = 0;
+ break;
+ }
+ fputs ("\tBYTE\t", asm_out_file);
+ mmix_print_operand (asm_out_file, x, 'B');
+ fputc ('\n', asm_out_file);
+ return true;
+
+ case 2:
+ if (GET_CODE (x) != CONST_INT)
+ {
+ aligned_p = 0;
+ break;
+ }
+ fputs ("\tWYDE\t", asm_out_file);
+ mmix_print_operand (asm_out_file, x, 'W');
+ fputc ('\n', asm_out_file);
+ return true;
+
+ case 4:
+ if (GET_CODE (x) != CONST_INT)
+ {
+ aligned_p = 0;
+ break;
+ }
+ fputs ("\tTETRA\t", asm_out_file);
+ mmix_print_operand (asm_out_file, x, 'L');
+ fputc ('\n', asm_out_file);
+ return true;
+
+ case 8:
+ /* We don't get here anymore for CONST_DOUBLE, because DImode
+ isn't expressed as CONST_DOUBLE, and DFmode is handled
+ elsewhere. */
+ gcc_assert (GET_CODE (x) != CONST_DOUBLE);
+ assemble_integer_with_op ("\tOCTA\t", x);
+ return true;
+ }
+ return default_assemble_integer (x, size, aligned_p);
+}
+
+/* ASM_OUTPUT_ASCII. */
+
+void
+mmix_asm_output_ascii (FILE *stream, const char *string, int length)
+{
+ while (length > 0)
+ {
+ int chunk_size = length > 60 ? 60 : length;
+ fprintf (stream, "\tBYTE ");
+ mmix_output_quoted_string (stream, string, chunk_size);
+ string += chunk_size;
+ length -= chunk_size;
+ fprintf (stream, "\n");
+ }
+}
+
+/* ASM_OUTPUT_ALIGNED_COMMON. */
+
+void
+mmix_asm_output_aligned_common (FILE *stream,
+ const char *name,
+ int size,
+ int align)
+{
+ /* This is mostly the elfos.h one. There doesn't seem to be a way to
+ express this in a mmixal-compatible way. */
+ fprintf (stream, "\t.comm\t");
+ assemble_name (stream, name);
+ fprintf (stream, ",%u,%u ! mmixal-incompatible COMMON\n",
+ size, align / BITS_PER_UNIT);
+}
+
+/* ASM_OUTPUT_ALIGNED_LOCAL. */
+
+void
+mmix_asm_output_aligned_local (FILE *stream,
+ const char *name,
+ int size,
+ int align)
+{
+ switch_to_section (data_section);
+
+ ASM_OUTPUT_ALIGN (stream, exact_log2 (align/BITS_PER_UNIT));
+ assemble_name (stream, name);
+ fprintf (stream, "\tLOC @+%d\n", size);
+}
+
+/* ASM_OUTPUT_LABEL. */
+
+void
+mmix_asm_output_label (FILE *stream, const char *name)
+{
+ assemble_name (stream, name);
+ fprintf (stream, "\tIS @\n");
+}
+
+/* ASM_OUTPUT_INTERNAL_LABEL. */
+
+void
+mmix_asm_output_internal_label (FILE *stream, const char *name)
+{
+ assemble_name_raw (stream, name);
+ fprintf (stream, "\tIS @\n");
+}
+
+/* ASM_DECLARE_REGISTER_GLOBAL. */
+
+void
+mmix_asm_declare_register_global (FILE *stream ATTRIBUTE_UNUSED,
+ tree decl ATTRIBUTE_UNUSED,
+ int regno ATTRIBUTE_UNUSED,
+ const char *name ATTRIBUTE_UNUSED)
+{
+ /* Nothing to do here, but there *will* be, therefore the framework is
+ here. */
+}
+
+/* ASM_WEAKEN_LABEL. */
+
+void
+mmix_asm_weaken_label (FILE *stream ATTRIBUTE_UNUSED,
+ const char *name ATTRIBUTE_UNUSED)
+{
+ fprintf (stream, "\t.weak ");
+ assemble_name (stream, name);
+ fprintf (stream, " ! mmixal-incompatible\n");
+}
+
+/* MAKE_DECL_ONE_ONLY. */
+
+void
+mmix_make_decl_one_only (tree decl)
+{
+ DECL_WEAK (decl) = 1;
+}
+
+/* ASM_OUTPUT_LABELREF.
+ Strip GCC's '*' and our own '@'. No order is assumed. */
+
+void
+mmix_asm_output_labelref (FILE *stream, const char *name)
+{
+ int is_extern = 1;
+
+ for (; (*name == '@' || *name == '*'); name++)
+ if (*name == '@')
+ is_extern = 0;
+
+ asm_fprintf (stream, "%s%U%s",
+ is_extern && TARGET_TOPLEVEL_SYMBOLS ? ":" : "",
+ name);
+}
+
+/* ASM_OUTPUT_DEF. */
+
+void
+mmix_asm_output_def (FILE *stream, const char *name, const char *value)
+{
+ assemble_name (stream, name);
+ fprintf (stream, "\tIS ");
+ assemble_name (stream, value);
+ fputc ('\n', stream);
+}
+
+/* PRINT_OPERAND. */
+
+void
+mmix_print_operand (FILE *stream, rtx x, int code)
+{
+ /* When we add support for different codes later, we can, when needed,
+ drop through to the main handler with a modified operand. */
+ rtx modified_x = x;
+ int regno = x != NULL_RTX && REG_P (x) ? REGNO (x) : 0;
+
+ switch (code)
+ {
+ /* Unrelated codes are in alphabetic order. */
+
+ case '+':
+ /* For conditional branches, output "P" for a probable branch. */
+ if (TARGET_BRANCH_PREDICT)
+ {
+ x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
+ if (x && INTVAL (XEXP (x, 0)) > REG_BR_PROB_BASE / 2)
+ putc ('P', stream);
+ }
+ return;
+
+ case '.':
+ /* For the %d in POP %d,0. */
+ fprintf (stream, "%d", MMIX_POP_ARGUMENT ());
+ return;
+
+ case 'B':
+ if (GET_CODE (x) != CONST_INT)
+ fatal_insn ("MMIX Internal: Expected a CONST_INT, not this", x);
+ fprintf (stream, "%d", (int) (INTVAL (x) & 0xff));
+ return;
+
+ case 'H':
+ /* Highpart. Must be general register, and not the last one, as
+ that one cannot be part of a consecutive register pair. */
+ if (regno > MMIX_LAST_GENERAL_REGISTER - 1)
+ internal_error ("MMIX Internal: Bad register: %d", regno);
+
+ /* This is big-endian, so the high-part is the first one. */
+ fprintf (stream, "%s", reg_names[MMIX_OUTPUT_REGNO (regno)]);
+ return;
+
+ case 'L':
+ /* Lowpart. Must be CONST_INT or general register, and not the last
+ one, as that one cannot be part of a consecutive register pair. */
+ if (GET_CODE (x) == CONST_INT)
+ {
+ fprintf (stream, "#%lx",
+ (unsigned long) (INTVAL (x)
+ & ((unsigned int) 0x7fffffff * 2 + 1)));
+ return;
+ }
+
+ if (GET_CODE (x) == SYMBOL_REF)
+ {
+ output_addr_const (stream, x);
+ return;
+ }
+
+ if (regno > MMIX_LAST_GENERAL_REGISTER - 1)
+ internal_error ("MMIX Internal: Bad register: %d", regno);
+
+ /* This is big-endian, so the low-part is + 1. */
+ fprintf (stream, "%s", reg_names[MMIX_OUTPUT_REGNO (regno) + 1]);
+ return;
+
+ /* Can't use 'a' because that's a generic modifier for address
+ output. */
+ case 'A':
+ mmix_output_shiftvalue_op_from_str (stream, "ANDN",
+ ~(unsigned HOST_WIDEST_INT)
+ mmix_intval (x));
+ return;
+
+ case 'i':
+ mmix_output_shiftvalue_op_from_str (stream, "INC",
+ (unsigned HOST_WIDEST_INT)
+ mmix_intval (x));
+ return;
+
+ case 'o':
+ mmix_output_shiftvalue_op_from_str (stream, "OR",
+ (unsigned HOST_WIDEST_INT)
+ mmix_intval (x));
+ return;
+
+ case 's':
+ mmix_output_shiftvalue_op_from_str (stream, "SET",
+ (unsigned HOST_WIDEST_INT)
+ mmix_intval (x));
+ return;
+
+ case 'd':
+ case 'D':
+ mmix_output_condition (stream, x, (code == 'D'));
+ return;
+
+ case 'e':
+ /* Output an extra "e" to make fcmpe, fune. */
+ if (TARGET_FCMP_EPSILON)
+ fprintf (stream, "e");
+ return;
+
+ case 'm':
+ /* Output the number minus 1. */
+ if (GET_CODE (x) != CONST_INT)
+ {
+ fatal_insn ("MMIX Internal: Bad value for 'm', not a CONST_INT",
+ x);
+ }
+ fprintf (stream, HOST_WIDEST_INT_PRINT_DEC,
+ (HOST_WIDEST_INT) (mmix_intval (x) - 1));
+ return;
+
+ case 'p':
+ /* Store the number of registers we want to save. This was setup
+ by the prologue. The actual operand contains the number of
+ registers to pass, but we don't use it currently. Anyway, we
+ need to output the number of saved registers here. */
+ fprintf (stream, "%d",
+ cfun->machine->highest_saved_stack_register + 1);
+ return;
+
+ case 'r':
+ /* Store the register to output a constant to. */
+ if (! REG_P (x))
+ fatal_insn ("MMIX Internal: Expected a register, not this", x);
+ mmix_output_destination_register = MMIX_OUTPUT_REGNO (regno);
+ return;
+
+ case 'I':
+ /* Output the constant. Note that we use this for floats as well. */
+ if (GET_CODE (x) != CONST_INT
+ && (GET_CODE (x) != CONST_DOUBLE
+ || (GET_MODE (x) != VOIDmode && GET_MODE (x) != DFmode
+ && GET_MODE (x) != SFmode)))
+ fatal_insn ("MMIX Internal: Expected a constant, not this", x);
+ mmix_output_register_setting (stream,
+ mmix_output_destination_register,
+ mmix_intval (x), 0);
+ return;
+
+ case 'U':
+ /* An U for unsigned, if TARGET_ZERO_EXTEND. Ignore the operand. */
+ if (TARGET_ZERO_EXTEND)
+ putc ('U', stream);
+ return;
+
+ case 'v':
+ mmix_output_shifted_value (stream, (HOST_WIDEST_INT) mmix_intval (x));
+ return;
+
+ case 'V':
+ mmix_output_shifted_value (stream, (HOST_WIDEST_INT) ~mmix_intval (x));
+ return;
+
+ case 'W':
+ if (GET_CODE (x) != CONST_INT)
+ fatal_insn ("MMIX Internal: Expected a CONST_INT, not this", x);
+ fprintf (stream, "#%x", (int) (INTVAL (x) & 0xffff));
+ return;
+
+ case 0:
+ /* Nothing to do. */
+ break;
+
+ default:
+ /* Presumably there's a missing case above if we get here. */
+ internal_error ("MMIX Internal: Missing %qc case in mmix_print_operand", code);
+ }
+
+ switch (GET_CODE (modified_x))
+ {
+ case REG:
+ regno = REGNO (modified_x);
+ if (regno >= FIRST_PSEUDO_REGISTER)
+ internal_error ("MMIX Internal: Bad register: %d", regno);
+ fprintf (stream, "%s", reg_names[MMIX_OUTPUT_REGNO (regno)]);
+ return;
+
+ case MEM:
+ output_address (XEXP (modified_x, 0));
+ return;
+
+ case CONST_INT:
+ /* For -2147483648, mmixal complains that the constant does not fit
+ in 4 bytes, so let's output it as hex. Take care to handle hosts
+ where HOST_WIDE_INT is longer than an int.
+
+ Print small constants +-255 using decimal. */
+
+ if (INTVAL (modified_x) > -256 && INTVAL (modified_x) < 256)
+ fprintf (stream, "%d", (int) (INTVAL (modified_x)));
+ else
+ fprintf (stream, "#%x",
+ (int) (INTVAL (modified_x)) & (unsigned int) ~0);
+ return;
+
+ case CONST_DOUBLE:
+ /* Do somewhat as CONST_INT. */
+ mmix_output_octa (stream, mmix_intval (modified_x), 0);
+ return;
+
+ case CONST:
+ output_addr_const (stream, modified_x);
+ return;
+
+ default:
+ /* No need to test for all strange things. Let output_addr_const do
+ it for us. */
+ if (CONSTANT_P (modified_x)
+ /* Strangely enough, this is not included in CONSTANT_P.
+ FIXME: Ask/check about sanity here. */
+ || GET_CODE (modified_x) == CODE_LABEL)
+ {
+ output_addr_const (stream, modified_x);
+ return;
+ }
+
+ /* We need the original here. */
+ fatal_insn ("MMIX Internal: Cannot decode this operand", x);
+ }
+}
+
+/* PRINT_OPERAND_PUNCT_VALID_P. */
+
+int
+mmix_print_operand_punct_valid_p (int code ATTRIBUTE_UNUSED)
+{
+ /* A '+' is used for branch prediction, similar to other ports. */
+ return code == '+'
+ /* A '.' is used for the %d in the POP %d,0 return insn. */
+ || code == '.';
+}
+
+/* PRINT_OPERAND_ADDRESS. */
+
+void
+mmix_print_operand_address (FILE *stream, rtx x)
+{
+ if (REG_P (x))
+ {
+ /* I find the generated assembly code harder to read without
+ the ",0". */
+ fprintf (stream, "%s,0", reg_names[MMIX_OUTPUT_REGNO (REGNO (x))]);
+ return;
+ }
+ else if (GET_CODE (x) == PLUS)
+ {
+ rtx x1 = XEXP (x, 0);
+ rtx x2 = XEXP (x, 1);
+
+ if (REG_P (x1))
+ {
+ fprintf (stream, "%s,", reg_names[MMIX_OUTPUT_REGNO (REGNO (x1))]);
+
+ if (REG_P (x2))
+ {
+ fprintf (stream, "%s",
+ reg_names[MMIX_OUTPUT_REGNO (REGNO (x2))]);
+ return;
+ }
+ else if (GET_CODE (x2) == CONST_INT
+ && CONST_OK_FOR_LETTER_P (INTVAL (x2), 'I'))
+ {
+ output_addr_const (stream, x2);
+ return;
+ }
+ }
+ }
+
+ if (TARGET_BASE_ADDRESSES && mmix_legitimate_constant_p (x))
+ {
+ output_addr_const (stream, x);
+ return;
+ }
+
+ fatal_insn ("MMIX Internal: This is not a recognized address", x);
+}
+
+/* ASM_OUTPUT_REG_PUSH. */
+
+void
+mmix_asm_output_reg_push (FILE *stream, int regno)
+{
+ fprintf (stream, "\tSUBU %s,%s,8\n\tSTOU %s,%s,0\n",
+ reg_names[MMIX_STACK_POINTER_REGNUM],
+ reg_names[MMIX_STACK_POINTER_REGNUM],
+ reg_names[MMIX_OUTPUT_REGNO (regno)],
+ reg_names[MMIX_STACK_POINTER_REGNUM]);
+}
+
+/* ASM_OUTPUT_REG_POP. */
+
+void
+mmix_asm_output_reg_pop (FILE *stream, int regno)
+{
+ fprintf (stream, "\tLDOU %s,%s,0\n\tINCL %s,8\n",
+ reg_names[MMIX_OUTPUT_REGNO (regno)],
+ reg_names[MMIX_STACK_POINTER_REGNUM],
+ reg_names[MMIX_STACK_POINTER_REGNUM]);
+}
+
+/* ASM_OUTPUT_ADDR_DIFF_ELT. */
+
+void
+mmix_asm_output_addr_diff_elt (FILE *stream,
+ rtx body ATTRIBUTE_UNUSED,
+ int value,
+ int rel)
+{
+ fprintf (stream, "\tTETRA L%d-L%d\n", value, rel);
+}
+
+/* ASM_OUTPUT_ADDR_VEC_ELT. */
+
+void
+mmix_asm_output_addr_vec_elt (FILE *stream, int value)
+{
+ fprintf (stream, "\tOCTA L:%d\n", value);
+}
+
+/* ASM_OUTPUT_SKIP. */
+
+void
+mmix_asm_output_skip (FILE *stream, int nbytes)
+{
+ fprintf (stream, "\tLOC @+%d\n", nbytes);
+}
+
+/* ASM_OUTPUT_ALIGN. */
+
+void
+mmix_asm_output_align (FILE *stream, int power)
+{
+ /* We need to record the needed alignment of this section in the object,
+ so we have to output an alignment directive. Use a .p2align (not
+ .align) so people will never have to wonder about whether the
+ argument is in number of bytes or the log2 thereof. We do it in
+ addition to the LOC directive, so nothing needs tweaking when
+ copy-pasting assembly into mmixal. */
+ fprintf (stream, "\t.p2align %d\n", power);
+ fprintf (stream, "\tLOC @+(%d-@)&%d\n", 1 << power, (1 << power) - 1);
+}
+
+/* DBX_REGISTER_NUMBER. */
+
+int
+mmix_dbx_register_number (int regno)
+{
+ /* Adjust the register number to the one it will be output as, dammit.
+ It'd be nice if we could check the assumption that we're filling a
+ gap, but every register between the last saved register and parameter
+ registers might be a valid parameter register. */
+ regno = MMIX_OUTPUT_REGNO (regno);
+
+ /* We need to renumber registers to get the number of the return address
+ register in the range 0..255. It is also space-saving if registers
+ mentioned in the call-frame information (which uses this function by
+ defaulting DWARF_FRAME_REGNUM to DBX_REGISTER_NUMBER) are numbered
+ 0 .. 63. So map 224 .. 256+15 -> 0 .. 47 and 0 .. 223 -> 48..223+48. */
+ return regno >= 224 ? (regno - 224) : (regno + 48);
+}
+
+/* End of target macro support functions.
+
+ Now the MMIX port's own functions. First the exported ones. */
+
+/* Wrapper for get_hard_reg_initial_val since integrate.h isn't included
+ from insn-emit.c. */
+
+rtx
+mmix_get_hard_reg_initial_val (enum machine_mode mode, int regno)
+{
+ return get_hard_reg_initial_val (mode, regno);
+}
+
+/* Nonzero when the function epilogue is simple enough that a single
+ "POP %d,0" should be used even within the function. */
+
+int
+mmix_use_simple_return (void)
+{
+ int regno;
+
+ int stack_space_to_allocate
+ = (crtl->outgoing_args_size
+ + crtl->args.pretend_args_size
+ + get_frame_size () + 7) & ~7;
+
+ if (!TARGET_USE_RETURN_INSN || !reload_completed)
+ return 0;
+
+ for (regno = 255;
+ regno >= MMIX_FIRST_GLOBAL_REGNUM;
+ regno--)
+ /* Note that we assume that the frame-pointer-register is one of these
+ registers, in which case we don't count it here. */
+ if ((((regno != MMIX_FRAME_POINTER_REGNUM || !frame_pointer_needed)
+ && df_regs_ever_live_p (regno) && !call_used_regs[regno]))
+ || IS_MMIX_EH_RETURN_DATA_REG (regno))
+ return 0;
+
+ if (frame_pointer_needed)
+ stack_space_to_allocate += 8;
+
+ if (MMIX_CFUN_HAS_LANDING_PAD)
+ stack_space_to_allocate += 16;
+ else if (MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS)
+ stack_space_to_allocate += 8;
+
+ return stack_space_to_allocate == 0;
+}
+
+
+/* Expands the function prologue into RTX. */
+
+void
+mmix_expand_prologue (void)
+{
+ HOST_WIDE_INT locals_size = get_frame_size ();
+ int regno;
+ HOST_WIDE_INT stack_space_to_allocate
+ = (crtl->outgoing_args_size
+ + crtl->args.pretend_args_size
+ + locals_size + 7) & ~7;
+ HOST_WIDE_INT offset = -8;
+
+ /* Add room needed to save global non-register-stack registers. */
+ for (regno = 255;
+ regno >= MMIX_FIRST_GLOBAL_REGNUM;
+ regno--)
+ /* Note that we assume that the frame-pointer-register is one of these
+ registers, in which case we don't count it here. */
+ if ((((regno != MMIX_FRAME_POINTER_REGNUM || !frame_pointer_needed)
+ && df_regs_ever_live_p (regno) && !call_used_regs[regno]))
+ || IS_MMIX_EH_RETURN_DATA_REG (regno))
+ stack_space_to_allocate += 8;
+
+ /* If we do have a frame-pointer, add room for it. */
+ if (frame_pointer_needed)
+ stack_space_to_allocate += 8;
+
+ /* If we have a non-local label, we need to be able to unwind to it, so
+ store the current register stack pointer. Also store the return
+ address if we do that. */
+ if (MMIX_CFUN_HAS_LANDING_PAD)
+ stack_space_to_allocate += 16;
+ else if (MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS)
+ /* If we do have a saved return-address slot, add room for it. */
+ stack_space_to_allocate += 8;
+
+ /* Make sure we don't get an unaligned stack. */
+ if ((stack_space_to_allocate % 8) != 0)
+ internal_error ("stack frame not a multiple of 8 bytes: %wd",
+ stack_space_to_allocate);
+
+ if (crtl->args.pretend_args_size)
+ {
+ int mmix_first_vararg_reg
+ = (MMIX_FIRST_INCOMING_ARG_REGNUM
+ + (MMIX_MAX_ARGS_IN_REGS
+ - crtl->args.pretend_args_size / 8));
+
+ for (regno
+ = MMIX_FIRST_INCOMING_ARG_REGNUM + MMIX_MAX_ARGS_IN_REGS - 1;
+ regno >= mmix_first_vararg_reg;
+ regno--)
+ {
+ if (offset < 0)
+ {
+ HOST_WIDE_INT stack_chunk
+ = stack_space_to_allocate > (256 - 8)
+ ? (256 - 8) : stack_space_to_allocate;
+
+ mmix_emit_sp_add (-stack_chunk);
+ offset += stack_chunk;
+ stack_space_to_allocate -= stack_chunk;
+ }
+
+ /* These registers aren't actually saved (as in "will be
+ restored"), so don't tell DWARF2 they're saved. */
+ emit_move_insn (gen_rtx_MEM (DImode,
+ plus_constant (stack_pointer_rtx,
+ offset)),
+ gen_rtx_REG (DImode, regno));
+ offset -= 8;
+ }
+ }
+
+ /* Store the frame-pointer. */
+
+ if (frame_pointer_needed)
+ {
+ rtx insn;
+
+ if (offset < 0)
+ {
+ /* Get 8 less than otherwise, since we need to reach offset + 8. */
+ HOST_WIDE_INT stack_chunk
+ = stack_space_to_allocate > (256 - 8 - 8)
+ ? (256 - 8 - 8) : stack_space_to_allocate;
+
+ mmix_emit_sp_add (-stack_chunk);
+
+ offset += stack_chunk;
+ stack_space_to_allocate -= stack_chunk;
+ }
+
+ insn = emit_move_insn (gen_rtx_MEM (DImode,
+ plus_constant (stack_pointer_rtx,
+ offset)),
+ hard_frame_pointer_rtx);
+ RTX_FRAME_RELATED_P (insn) = 1;
+ insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
+ stack_pointer_rtx,
+ GEN_INT (offset + 8)));
+ RTX_FRAME_RELATED_P (insn) = 1;
+ offset -= 8;
+ }
+
+ if (MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS)
+ {
+ rtx tmpreg, retreg;
+ rtx insn;
+
+ /* Store the return-address, if one is needed on the stack. We
+ usually store it in a register when needed, but that doesn't work
+ with -fexceptions. */
+
+ if (offset < 0)
+ {
+ /* Get 8 less than otherwise, since we need to reach offset + 8. */
+ HOST_WIDE_INT stack_chunk
+ = stack_space_to_allocate > (256 - 8 - 8)
+ ? (256 - 8 - 8) : stack_space_to_allocate;
+
+ mmix_emit_sp_add (-stack_chunk);
+
+ offset += stack_chunk;
+ stack_space_to_allocate -= stack_chunk;
+ }
+
+ tmpreg = gen_rtx_REG (DImode, 255);
+ retreg = gen_rtx_REG (DImode, MMIX_rJ_REGNUM);
+
+ /* Dwarf2 code is confused by the use of a temporary register for
+ storing the return address, so we have to express it as a note,
+ which we attach to the actual store insn. */
+ emit_move_insn (tmpreg, retreg);
+
+ insn = emit_move_insn (gen_rtx_MEM (DImode,
+ plus_constant (stack_pointer_rtx,
+ offset)),
+ tmpreg);
+ RTX_FRAME_RELATED_P (insn) = 1;
+ REG_NOTES (insn)
+ = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
+ gen_rtx_SET (VOIDmode,
+ gen_rtx_MEM (DImode,
+ plus_constant (stack_pointer_rtx,
+ offset)),
+ retreg),
+ REG_NOTES (insn));
+
+ offset -= 8;
+ }
+ else if (MMIX_CFUN_HAS_LANDING_PAD)
+ offset -= 8;
+
+ if (MMIX_CFUN_HAS_LANDING_PAD)
+ {
+ /* Store the register defining the numbering of local registers, so
+ we know how long to unwind the register stack. */
+
+ if (offset < 0)
+ {
+ /* Get 8 less than otherwise, since we need to reach offset + 8. */
+ HOST_WIDE_INT stack_chunk
+ = stack_space_to_allocate > (256 - 8 - 8)
+ ? (256 - 8 - 8) : stack_space_to_allocate;
+
+ mmix_emit_sp_add (-stack_chunk);
+
+ offset += stack_chunk;
+ stack_space_to_allocate -= stack_chunk;
+ }
+
+ /* We don't tell dwarf2 about this one; we just have it to unwind
+ the register stack at landing pads. FIXME: It's a kludge because
+ we can't describe the effect of the PUSHJ and PUSHGO insns on the
+ register stack at the moment. Best thing would be to handle it
+ like stack-pointer offsets. Better: some hook into dwarf2out.c
+ to produce DW_CFA_expression:s that specify the increment of rO,
+ and unwind it at eh_return (preferred) or at the landing pad.
+ Then saves to $0..$G-1 could be specified through that register. */
+
+ emit_move_insn (gen_rtx_REG (DImode, 255),
+ gen_rtx_REG (DImode,
+ MMIX_rO_REGNUM));
+ emit_move_insn (gen_rtx_MEM (DImode,
+ plus_constant (stack_pointer_rtx, offset)),
+ gen_rtx_REG (DImode, 255));
+ offset -= 8;
+ }
+
+ /* After the return-address and the frame-pointer, we have the local
+ variables. They're the ones that may have an "unaligned" size. */
+ offset -= (locals_size + 7) & ~7;
+
+ /* Now store all registers that are global, i.e. not saved by the
+ register file machinery.
+
+ It is assumed that the frame-pointer is one of these registers, so it
+ is explicitly excluded in the count. */
+
+ for (regno = 255;
+ regno >= MMIX_FIRST_GLOBAL_REGNUM;
+ regno--)
+ if (((regno != MMIX_FRAME_POINTER_REGNUM || !frame_pointer_needed)
+ && df_regs_ever_live_p (regno) && ! call_used_regs[regno])
+ || IS_MMIX_EH_RETURN_DATA_REG (regno))
+ {
+ rtx insn;
+
+ if (offset < 0)
+ {
+ HOST_WIDE_INT stack_chunk
+ = (stack_space_to_allocate > (256 - offset - 8)
+ ? (256 - offset - 8) : stack_space_to_allocate);
+
+ mmix_emit_sp_add (-stack_chunk);
+ offset += stack_chunk;
+ stack_space_to_allocate -= stack_chunk;
+ }
+
+ insn = emit_move_insn (gen_rtx_MEM (DImode,
+ plus_constant (stack_pointer_rtx,
+ offset)),
+ gen_rtx_REG (DImode, regno));
+ RTX_FRAME_RELATED_P (insn) = 1;
+ offset -= 8;
+ }
+
+ /* Finally, allocate room for outgoing args and local vars if room
+ wasn't allocated above. */
+ if (stack_space_to_allocate)
+ mmix_emit_sp_add (-stack_space_to_allocate);
+}
+
+/* Expands the function epilogue into RTX. */
+
+void
+mmix_expand_epilogue (void)
+{
+ HOST_WIDE_INT locals_size = get_frame_size ();
+ int regno;
+ HOST_WIDE_INT stack_space_to_deallocate
+ = (crtl->outgoing_args_size
+ + crtl->args.pretend_args_size
+ + locals_size + 7) & ~7;
+
+ /* The first address to access is beyond the outgoing_args area. */
+ HOST_WIDE_INT offset = crtl->outgoing_args_size;
+
+ /* Add the space for global non-register-stack registers.
+ It is assumed that the frame-pointer register can be one of these
+ registers, in which case it is excluded from the count when needed. */
+ for (regno = 255;
+ regno >= MMIX_FIRST_GLOBAL_REGNUM;
+ regno--)
+ if (((regno != MMIX_FRAME_POINTER_REGNUM || !frame_pointer_needed)
+ && df_regs_ever_live_p (regno) && !call_used_regs[regno])
+ || IS_MMIX_EH_RETURN_DATA_REG (regno))
+ stack_space_to_deallocate += 8;
+
+ /* Add in the space for register stack-pointer. If so, always add room
+ for the saved PC. */
+ if (MMIX_CFUN_HAS_LANDING_PAD)
+ stack_space_to_deallocate += 16;
+ else if (MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS)
+ /* If we have a saved return-address slot, add it in. */
+ stack_space_to_deallocate += 8;
+
+ /* Add in the frame-pointer. */
+ if (frame_pointer_needed)
+ stack_space_to_deallocate += 8;
+
+ /* Make sure we don't get an unaligned stack. */
+ if ((stack_space_to_deallocate % 8) != 0)
+ internal_error ("stack frame not a multiple of octabyte: %wd",
+ stack_space_to_deallocate);
+
+ /* We will add back small offsets to the stack pointer as we go.
+ First, we restore all registers that are global, i.e. not saved by
+ the register file machinery. */
+
+ for (regno = MMIX_FIRST_GLOBAL_REGNUM;
+ regno <= 255;
+ regno++)
+ if (((regno != MMIX_FRAME_POINTER_REGNUM || !frame_pointer_needed)
+ && df_regs_ever_live_p (regno) && !call_used_regs[regno])
+ || IS_MMIX_EH_RETURN_DATA_REG (regno))
+ {
+ if (offset > 255)
+ {
+ mmix_emit_sp_add (offset);
+ stack_space_to_deallocate -= offset;
+ offset = 0;
+ }
+
+ emit_move_insn (gen_rtx_REG (DImode, regno),
+ gen_rtx_MEM (DImode,
+ plus_constant (stack_pointer_rtx,
+ offset)));
+ offset += 8;
+ }
+
+ /* Here is where the local variables were. As in the prologue, they
+ might be of an unaligned size. */
+ offset += (locals_size + 7) & ~7;
+
+ /* The saved register stack pointer is just below the frame-pointer
+ register. We don't need to restore it "manually"; the POP
+ instruction does that. */
+ if (MMIX_CFUN_HAS_LANDING_PAD)
+ offset += 16;
+ else if (MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS)
+ /* The return-address slot is just below the frame-pointer register.
+ We don't need to restore it because we don't really use it. */
+ offset += 8;
+
+ /* Get back the old frame-pointer-value. */
+ if (frame_pointer_needed)
+ {
+ if (offset > 255)
+ {
+ mmix_emit_sp_add (offset);
+
+ stack_space_to_deallocate -= offset;
+ offset = 0;
+ }
+
+ emit_move_insn (hard_frame_pointer_rtx,
+ gen_rtx_MEM (DImode,
+ plus_constant (stack_pointer_rtx,
+ offset)));
+ offset += 8;
+ }
+
+ /* We do not need to restore pretended incoming args, just add back
+ offset to sp. */
+ if (stack_space_to_deallocate != 0)
+ mmix_emit_sp_add (stack_space_to_deallocate);
+
+ if (crtl->calls_eh_return)
+ /* Adjust the (normal) stack-pointer to that of the receiver.
+ FIXME: It would be nice if we could also adjust the register stack
+ here, but we need to express it through DWARF 2 too. */
+ emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
+ gen_rtx_REG (DImode,
+ MMIX_EH_RETURN_STACKADJ_REGNUM)));
+}
+
+/* Output an optimal sequence for setting a register to a specific
+ constant. Used in an alternative for const_ints in movdi, and when
+ using large stack-frame offsets.
+
+ Use do_begin_end to say if a line-starting TAB and newline before the
+ first insn and after the last insn is wanted. */
+
+void
+mmix_output_register_setting (FILE *stream,
+ int regno,
+ HOST_WIDEST_INT value,
+ int do_begin_end)
+{
+ if (do_begin_end)
+ fprintf (stream, "\t");
+
+ if (mmix_shiftable_wyde_value ((unsigned HOST_WIDEST_INT) value))
+ {
+ /* First, the one-insn cases. */
+ mmix_output_shiftvalue_op_from_str (stream, "SET",
+ (unsigned HOST_WIDEST_INT)
+ value);
+ fprintf (stream, " %s,", reg_names[regno]);
+ mmix_output_shifted_value (stream, (unsigned HOST_WIDEST_INT) value);
+ }
+ else if (mmix_shiftable_wyde_value (-(unsigned HOST_WIDEST_INT) value))
+ {
+ /* We do this to get a bit more legible assembly code. The next
+ alternative is mostly redundant with this. */
+
+ mmix_output_shiftvalue_op_from_str (stream, "SET",
+ -(unsigned HOST_WIDEST_INT)
+ value);
+ fprintf (stream, " %s,", reg_names[regno]);
+ mmix_output_shifted_value (stream, -(unsigned HOST_WIDEST_INT) value);
+ fprintf (stream, "\n\tNEGU %s,0,%s", reg_names[regno],
+ reg_names[regno]);
+ }
+ else if (mmix_shiftable_wyde_value (~(unsigned HOST_WIDEST_INT) value))
+ {
+ /* Slightly more expensive, the two-insn cases. */
+
+ /* FIXME: We could of course also test if 0..255-N or ~(N | 1..255)
+ is shiftable, or any other one-insn transformation of the value.
+ FIXME: Check first if the value is "shiftable" by two loading
+ with two insns, since it makes more readable assembly code (if
+ anyone else cares). */
+
+ mmix_output_shiftvalue_op_from_str (stream, "SET",
+ ~(unsigned HOST_WIDEST_INT)
+ value);
+ fprintf (stream, " %s,", reg_names[regno]);
+ mmix_output_shifted_value (stream, ~(unsigned HOST_WIDEST_INT) value);
+ fprintf (stream, "\n\tNOR %s,%s,0", reg_names[regno],
+ reg_names[regno]);
+ }
+ else
+ {
+ /* The generic case. 2..4 insns. */
+ static const char *const higher_parts[] = {"L", "ML", "MH", "H"};
+ const char *op = "SET";
+ const char *line_begin = "";
+ int insns = 0;
+ int i;
+ HOST_WIDEST_INT tmpvalue = value;
+
+ /* Compute the number of insns needed to output this constant. */
+ for (i = 0; i < 4 && tmpvalue != 0; i++)
+ {
+ if (tmpvalue & 65535)
+ insns++;
+ tmpvalue >>= 16;
+ }
+ if (TARGET_BASE_ADDRESSES && insns == 3)
+ {
+ /* The number three is based on a static observation on
+ ghostscript-6.52. Two and four are excluded because there
+ are too many such constants, and each unique constant (maybe
+ offset by 1..255) were used few times compared to other uses,
+ e.g. addresses.
+
+ We use base-plus-offset addressing to force it into a global
+ register; we just use a "LDA reg,VALUE", which will cause the
+ assembler and linker to DTRT (for constants as well as
+ addresses). */
+ fprintf (stream, "LDA %s,", reg_names[regno]);
+ mmix_output_octa (stream, value, 0);
+ }
+ else
+ {
+ /* Output pertinent parts of the 4-wyde sequence.
+ Still more to do if we want this to be optimal, but hey...
+ Note that the zero case has been handled above. */
+ for (i = 0; i < 4 && value != 0; i++)
+ {
+ if (value & 65535)
+ {
+ fprintf (stream, "%s%s%s %s,#%x", line_begin, op,
+ higher_parts[i], reg_names[regno],
+ (int) (value & 65535));
+ /* The first one sets the rest of the bits to 0, the next
+ ones add set bits. */
+ op = "INC";
+ line_begin = "\n\t";
+ }
+
+ value >>= 16;
+ }
+ }
+ }
+
+ if (do_begin_end)
+ fprintf (stream, "\n");
+}
+
+/* Return 1 if value is 0..65535*2**(16*N) for N=0..3.
+ else return 0. */
+
+int
+mmix_shiftable_wyde_value (unsigned HOST_WIDEST_INT value)
+{
+ /* Shift by 16 bits per group, stop when we've found two groups with
+ nonzero bits. */
+ int i;
+ int has_candidate = 0;
+
+ for (i = 0; i < 4; i++)
+ {
+ if (value & 65535)
+ {
+ if (has_candidate)
+ return 0;
+ else
+ has_candidate = 1;
+ }
+
+ value >>= 16;
+ }
+
+ return 1;
+}
+
+/* X and Y are two things to compare using CODE. Return the rtx for
+ the cc-reg in the proper mode. */
+
+rtx
+mmix_gen_compare_reg (RTX_CODE code, rtx x, rtx y)
+{
+ enum machine_mode ccmode = SELECT_CC_MODE (code, x, y);
+ return gen_reg_rtx (ccmode);
+}
+
+/* Local (static) helper functions. */
+
+static void
+mmix_emit_sp_add (HOST_WIDE_INT offset)
+{
+ rtx insn;
+
+ if (offset < 0)
+ {
+ /* Negative stack-pointer adjustments are allocations and appear in
+ the prologue only. We mark them as frame-related so unwind and
+ debug info is properly emitted for them. */
+ if (offset > -255)
+ insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
+ stack_pointer_rtx,
+ GEN_INT (offset)));
+ else
+ {
+ rtx tmpr = gen_rtx_REG (DImode, 255);
+ RTX_FRAME_RELATED_P (emit_move_insn (tmpr, GEN_INT (offset))) = 1;
+ insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
+ stack_pointer_rtx, tmpr));
+ }
+ RTX_FRAME_RELATED_P (insn) = 1;
+ }
+ else
+ {
+ /* Positive adjustments are in the epilogue only. Don't mark them
+ as "frame-related" for unwind info. */
+ if (CONST_OK_FOR_LETTER_P (offset, 'L'))
+ emit_insn (gen_adddi3 (stack_pointer_rtx,
+ stack_pointer_rtx,
+ GEN_INT (offset)));
+ else
+ {
+ rtx tmpr = gen_rtx_REG (DImode, 255);
+ emit_move_insn (tmpr, GEN_INT (offset));
+ insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
+ stack_pointer_rtx, tmpr));
+ }
+ }
+}
+
+/* Print operator suitable for doing something with a shiftable
+ wyde. The type of operator is passed as an asm output modifier. */
+
+static void
+mmix_output_shiftvalue_op_from_str (FILE *stream,
+ const char *mainop,
+ HOST_WIDEST_INT value)
+{
+ static const char *const op_part[] = {"L", "ML", "MH", "H"};
+ int i;
+
+ if (! mmix_shiftable_wyde_value (value))
+ {
+ char s[sizeof ("0xffffffffffffffff")];
+ sprintf (s, HOST_WIDEST_INT_PRINT_HEX, value);
+ internal_error ("MMIX Internal: %s is not a shiftable int", s);
+ }
+
+ for (i = 0; i < 4; i++)
+ {
+ /* We know we're through when we find one-bits in the low
+ 16 bits. */
+ if (value & 0xffff)
+ {
+ fprintf (stream, "%s%s", mainop, op_part[i]);
+ return;
+ }
+ value >>= 16;
+ }
+
+ /* No bits set? Then it must have been zero. */
+ fprintf (stream, "%sL", mainop);
+}
+
+/* Print a 64-bit value, optionally prefixed by assembly pseudo. */
+
+static void
+mmix_output_octa (FILE *stream, HOST_WIDEST_INT value, int do_begin_end)
+{
+ /* Snipped from final.c:output_addr_const. We need to avoid the
+ presumed universal "0x" prefix. We can do it by replacing "0x" with
+ "#0" here; we must avoid a space in the operands and no, the zero
+ won't cause the number to be assumed in octal format. */
+ char hex_format[sizeof (HOST_WIDEST_INT_PRINT_HEX)];
+
+ if (do_begin_end)
+ fprintf (stream, "\tOCTA ");
+
+ strcpy (hex_format, HOST_WIDEST_INT_PRINT_HEX);
+ hex_format[0] = '#';
+ hex_format[1] = '0';
+
+ /* Provide a few alternative output formats depending on the number, to
+ improve legibility of assembler output. */
+ if ((value < (HOST_WIDEST_INT) 0 && value > (HOST_WIDEST_INT) -10000)
+ || (value >= (HOST_WIDEST_INT) 0 && value <= (HOST_WIDEST_INT) 16384))
+ fprintf (stream, "%d", (int) value);
+ else if (value > (HOST_WIDEST_INT) 0
+ && value < ((HOST_WIDEST_INT) 1 << 31) * 2)
+ fprintf (stream, "#%x", (unsigned int) value);
+ else
+ fprintf (stream, hex_format, value);
+
+ if (do_begin_end)
+ fprintf (stream, "\n");
+}
+
+/* Print the presumed shiftable wyde argument shifted into place (to
+ be output with an operand). */
+
+static void
+mmix_output_shifted_value (FILE *stream, HOST_WIDEST_INT value)
+{
+ int i;
+
+ if (! mmix_shiftable_wyde_value (value))
+ {
+ char s[16+2+1];
+ sprintf (s, HOST_WIDEST_INT_PRINT_HEX, value);
+ internal_error ("MMIX Internal: %s is not a shiftable int", s);
+ }
+
+ for (i = 0; i < 4; i++)
+ {
+ /* We know we're through when we find one-bits in the low 16 bits. */
+ if (value & 0xffff)
+ {
+ fprintf (stream, "#%x", (int) (value & 0xffff));
+ return;
+ }
+
+ value >>= 16;
+ }
+
+ /* No bits set? Then it must have been zero. */
+ fprintf (stream, "0");
+}
+
+/* Output an MMIX condition name corresponding to an operator
+ and operands:
+ (comparison_operator [(comparison_operator ...) (const_int 0)])
+ which means we have to look at *two* operators.
+
+ The argument "reversed" refers to reversal of the condition (not the
+ same as swapping the arguments). */
+
+static void
+mmix_output_condition (FILE *stream, rtx x, int reversed)
+{
+ struct cc_conv
+ {
+ RTX_CODE cc;
+
+ /* The normal output cc-code. */
+ const char *const normal;
+
+ /* The reversed cc-code, or NULL if invalid. */
+ const char *const reversed;
+ };
+
+ struct cc_type_conv
+ {
+ enum machine_mode cc_mode;
+
+ /* Terminated with {UNKNOWN, NULL, NULL} */
+ const struct cc_conv *const convs;
+ };
+
+#undef CCEND
+#define CCEND {UNKNOWN, NULL, NULL}
+
+ static const struct cc_conv cc_fun_convs[]
+ = {{ORDERED, "Z", "P"},
+ {UNORDERED, "P", "Z"},
+ CCEND};
+ static const struct cc_conv cc_fp_convs[]
+ = {{GT, "P", NULL},
+ {LT, "N", NULL},
+ CCEND};
+ static const struct cc_conv cc_fpeq_convs[]
+ = {{NE, "Z", "P"},
+ {EQ, "P", "Z"},
+ CCEND};
+ static const struct cc_conv cc_uns_convs[]
+ = {{GEU, "NN", "N"},
+ {GTU, "P", "NP"},
+ {LEU, "NP", "P"},
+ {LTU, "N", "NN"},
+ CCEND};
+ static const struct cc_conv cc_signed_convs[]
+ = {{NE, "NZ", "Z"},
+ {EQ, "Z", "NZ"},
+ {GE, "NN", "N"},
+ {GT, "P", "NP"},
+ {LE, "NP", "P"},
+ {LT, "N", "NN"},
+ CCEND};
+ static const struct cc_conv cc_di_convs[]
+ = {{NE, "NZ", "Z"},
+ {EQ, "Z", "NZ"},
+ {GE, "NN", "N"},
+ {GT, "P", "NP"},
+ {LE, "NP", "P"},
+ {LT, "N", "NN"},
+ {GTU, "NZ", "Z"},
+ {LEU, "Z", "NZ"},
+ CCEND};
+#undef CCEND
+
+ static const struct cc_type_conv cc_convs[]
+ = {{CC_FUNmode, cc_fun_convs},
+ {CC_FPmode, cc_fp_convs},
+ {CC_FPEQmode, cc_fpeq_convs},
+ {CC_UNSmode, cc_uns_convs},
+ {CCmode, cc_signed_convs},
+ {DImode, cc_di_convs}};
+
+ size_t i;
+ int j;
+
+ enum machine_mode mode = GET_MODE (XEXP (x, 0));
+ RTX_CODE cc = GET_CODE (x);
+
+ for (i = 0; i < ARRAY_SIZE (cc_convs); i++)
+ {
+ if (mode == cc_convs[i].cc_mode)
+ {
+ for (j = 0; cc_convs[i].convs[j].cc != UNKNOWN; j++)
+ if (cc == cc_convs[i].convs[j].cc)
+ {
+ const char *mmix_cc
+ = (reversed ? cc_convs[i].convs[j].reversed
+ : cc_convs[i].convs[j].normal);
+
+ if (mmix_cc == NULL)
+ fatal_insn ("MMIX Internal: Trying to output invalidly\
+ reversed condition:", x);
+
+ fprintf (stream, "%s", mmix_cc);
+ return;
+ }
+
+ fatal_insn ("MMIX Internal: What's the CC of this?", x);
+ }
+ }
+
+ fatal_insn ("MMIX Internal: What is the CC of this?", x);
+}
+
+/* Return the bit-value for a const_int or const_double. */
+
+static HOST_WIDEST_INT
+mmix_intval (rtx x)
+{
+ unsigned HOST_WIDEST_INT retval;
+
+ if (GET_CODE (x) == CONST_INT)
+ return INTVAL (x);
+
+ /* We make a little song and dance because converting to long long in
+ gcc-2.7.2 is broken. I still want people to be able to use it for
+ cross-compilation to MMIX. */
+ if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == VOIDmode)
+ {
+ if (sizeof (HOST_WIDE_INT) < sizeof (HOST_WIDEST_INT))
+ {
+ retval = (unsigned) CONST_DOUBLE_LOW (x) / 2;
+ retval *= 2;
+ retval |= CONST_DOUBLE_LOW (x) & 1;
+
+ retval |=
+ (unsigned HOST_WIDEST_INT) CONST_DOUBLE_HIGH (x)
+ << (HOST_BITS_PER_LONG);
+ }
+ else
+ retval = CONST_DOUBLE_HIGH (x);
+
+ return retval;
+ }
+
+ if (GET_CODE (x) == CONST_DOUBLE)
+ {
+ REAL_VALUE_TYPE value;
+
+ /* FIXME: This macro is not in the manual but should be. */
+ REAL_VALUE_FROM_CONST_DOUBLE (value, x);
+
+ if (GET_MODE (x) == DFmode)
+ {
+ long bits[2];
+
+ REAL_VALUE_TO_TARGET_DOUBLE (value, bits);
+
+ /* The double cast is necessary to avoid getting the long
+ sign-extended to unsigned long long(!) when they're of
+ different size (usually 32-bit hosts). */
+ return
+ ((unsigned HOST_WIDEST_INT) (unsigned long) bits[0]
+ << (unsigned HOST_WIDEST_INT) 32U)
+ | (unsigned HOST_WIDEST_INT) (unsigned long) bits[1];
+ }
+ else if (GET_MODE (x) == SFmode)
+ {
+ long bits;
+ REAL_VALUE_TO_TARGET_SINGLE (value, bits);
+
+ return (unsigned long) bits;
+ }
+ }
+
+ fatal_insn ("MMIX Internal: This is not a constant:", x);
+}
+
+/* Worker function for TARGET_PROMOTE_FUNCTION_MODE. */
+
+enum machine_mode
+mmix_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
+ enum machine_mode mode,
+ int *punsignedp ATTRIBUTE_UNUSED,
+ const_tree fntype ATTRIBUTE_UNUSED,
+ int for_return)
+{
+ /* Apparently not doing TRT if int < register-size. FIXME: Perhaps
+ FUNCTION_VALUE and LIBCALL_VALUE needs tweaking as some ports say. */
+ if (for_return == 1)
+ return mode;
+
+ /* Promotion of modes currently generates slow code, extending before
+ operation, so we do it only for arguments. */
+ if (GET_MODE_CLASS (mode) == MODE_INT
+ && GET_MODE_SIZE (mode) < 8)
+ return DImode;
+ else
+ return mode;
+}
+/* Worker function for TARGET_STRUCT_VALUE_RTX. */
+
+static rtx
+mmix_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
+ int incoming ATTRIBUTE_UNUSED)
+{
+ return gen_rtx_REG (Pmode, MMIX_STRUCT_VALUE_REGNUM);
+}
+
+/* Worker function for TARGET_FRAME_POINTER_REQUIRED.
+
+ FIXME: Is this requirement built-in? Anyway, we should try to get rid
+ of it; we can deduce the value. */
+
+bool
+mmix_frame_pointer_required (void)
+{
+ return (cfun->has_nonlocal_label);
+}
+
+/*
+ * Local variables:
+ * eval: (c-set-style "gnu")
+ * indent-tabs-mode: t
+ * End:
+ */
mmix.c
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: mmix.opt
===================================================================
--- mmix.opt (nonexistent)
+++ mmix.opt (revision 384)
@@ -0,0 +1,99 @@
+; Options for the MMIX port of the compiler.
+
+; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
+;
+; This file is part of GCC.
+;
+; GCC is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License as published by the Free
+; Software Foundation; either version 3, or (at your option) any later
+; version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+; for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING3. If not see
+;