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Subversion Repositories openrisc_2011-10-31
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- This comparison shows the changes necessary to convert path
/openrisc/tags/gnu-src/gdb-6.8/pre-binutils-2.20.1-sync/include/opcode
- from Rev 157 to Rev 223
- ↔ Reverse comparison
Rev 157 → Rev 223
/i386.h
0,0 → 1,115
/* opcode/i386.h -- Intel 80386 opcode macros |
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
Free Software Foundation, Inc. |
|
This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. |
|
This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. |
|
This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
|
/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived |
ix86 Unix assemblers, generate floating point instructions with |
reversed source and destination registers in certain cases. |
Unfortunately, gcc and possibly many other programs use this |
reversed syntax, so we're stuck with it. |
|
eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but |
`fsub %st,%st(3)' results in st(3) = st - st(3), rather than |
the expected st(3) = st(3) - st |
|
This happens with all the non-commutative arithmetic floating point |
operations with two register operands, where the source register is |
%st, and destination register is %st(i). |
|
The affected opcode map is dceX, dcfX, deeX, defX. */ |
|
#ifndef SYSV386_COMPAT |
/* Set non-zero for broken, compatible instructions. Set to zero for |
non-broken opcodes at your peril. gcc generates SystemV/386 |
compatible instructions. */ |
#define SYSV386_COMPAT 1 |
#endif |
#ifndef OLDGCC_COMPAT |
/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could |
generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands |
reversed. */ |
#define OLDGCC_COMPAT SYSV386_COMPAT |
#endif |
|
#define MOV_AX_DISP32 0xa0 |
#define POP_SEG_SHORT 0x07 |
#define JUMP_PC_RELATIVE 0xeb |
#define INT_OPCODE 0xcd |
#define INT3_OPCODE 0xcc |
/* The opcode for the fwait instruction, which disassembler treats as a |
prefix when it can. */ |
#define FWAIT_OPCODE 0x9b |
#define ADDR_PREFIX_OPCODE 0x67 |
#define DATA_PREFIX_OPCODE 0x66 |
#define LOCK_PREFIX_OPCODE 0xf0 |
#define CS_PREFIX_OPCODE 0x2e |
#define DS_PREFIX_OPCODE 0x3e |
#define ES_PREFIX_OPCODE 0x26 |
#define FS_PREFIX_OPCODE 0x64 |
#define GS_PREFIX_OPCODE 0x65 |
#define SS_PREFIX_OPCODE 0x36 |
#define REPNE_PREFIX_OPCODE 0xf2 |
#define REPE_PREFIX_OPCODE 0xf3 |
|
#define TWO_BYTE_OPCODE_ESCAPE 0x0f |
#define NOP_OPCODE (char) 0x90 |
|
/* register numbers */ |
#define EBP_REG_NUM 5 |
#define ESP_REG_NUM 4 |
|
/* modrm_byte.regmem for twobyte escape */ |
#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM |
/* index_base_byte.index for no index register addressing */ |
#define NO_INDEX_REGISTER ESP_REG_NUM |
/* index_base_byte.base for no base register addressing */ |
#define NO_BASE_REGISTER EBP_REG_NUM |
#define NO_BASE_REGISTER_16 6 |
|
/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ |
#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ |
#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) |
|
/* x86-64 extension prefix. */ |
#define REX_OPCODE 0x40 |
|
/* Indicates 64 bit operand size. */ |
#define REX_W 8 |
/* High extension to reg field of modrm byte. */ |
#define REX_R 4 |
/* High extension to SIB index field. */ |
#define REX_X 2 |
/* High extension to base field of modrm or SIB, or reg field of opcode. */ |
#define REX_B 1 |
|
/* max operands per insn */ |
#define MAX_OPERANDS 4 |
|
/* max immediates per insn (lcall, ljmp, insertq, extrq) */ |
#define MAX_IMMEDIATE_OPERANDS 2 |
|
/* max memory refs per insn (string ops) */ |
#define MAX_MEMORY_OPERANDS 2 |
|
/* max size of insn mnemonics. */ |
#define MAX_MNEM_SIZE 16 |
|
/* max size of register name in insn mnemonics. */ |
#define MAX_REG_NAME_SIZE 8 |
i386.h
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: ChangeLog-9103
===================================================================
--- ChangeLog-9103 (nonexistent)
+++ ChangeLog-9103 (revision 223)
@@ -0,0 +1,3121 @@
+2005-04-13 H.J. Lu
+
+ 2003-11-18 Maciej W. Rozycki
+ * mips.h: Define new enum members, M_LCA_AB and M_DLCA_AB.
+
+ 2003-04-04 Svein E. Seldal
+ * tic4x.h: Namespace cleanup. Replace s/c4x/tic4x
+
+ 2002-11-16 Klee Dienes
+ * m88k.h (INSTAB): Remove 'next' field.
+ (instruction): Remove definition; replace with extern declaration
+ and mark as const.
+
+ 2002-08-28 Michael Hayes
+ * tic4x.h: New file.
+
+ 2002-07-25 Richard Sandiford
+ * mips.h (CPU_R2000): Remove.
+
+2003-10-21 Peter Barada
+ Bernardo Innocenti
+
+ * m68k.h: Add MCFv4/MCF5528x support.
+
+2003-10-19 Hans-Peter Nilsson
+
+ * mmix.h (JMP_INSN_BYTE): Define.
+
+2003-09-30 Chris Demetriou
+
+ * mips.h: Document +E, +F, +G, +H, and +I operand types.
+ Update documentation of I, +B and +C operand types.
+ (INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
+ (M_DEXT, M_DINS): New enum values.
+
+2003-09-04 Nick Clifton
+
+ * v850.h (PROCESSOR_V850E1): Define.
+
+2003-08-19 Alan Modra
+
+ * ppc.h (PPC_OPCODE_440): Define. Formatting. Use hex for other
+ PPC_OPCODE_* defines.
+
+2003-08-16 Jason Eckhardt
+
+ * i860.h (fmov.ds): Expand as famov.ds.
+ (fmov.sd): Expand as famov.sd.
+ (pfmov.ds): Expand as pfamov.ds.
+
+2003-08-07 Michael Meissner
+
+ * cgen.h: Remove PARAM macro usage in all prototypes.
+ (CGEN_EXTRACT_INFO): Use void * instead of PTR.
+ (cgen_print_fn): Ditto.
+ (CGEN_HW_ENTRY): Ditto.
+ (CGEN_MAYBE_MULTI_IFLD): Ditto.
+ (struct cgen_insn): Ditto.
+ (CGEN_CPU_TABLE): Ditto.
+
+2003-08-07 Alan Modra
+
+ * alpha.h: Remove PARAMS macro.
+ * arc.h: Likewise.
+ * d10v.h: Likewise.
+ * d30v.h: Likewise.
+ * i370.h: Likewise.
+ * or32.h: Likewise.
+ * pj.h: Likewise.
+ * ppc.h: Likewise.
+ * sparc.h: Likewise.
+ * tic80.h: Likewise.
+ * v850.h: Likewise.
+
+2003-07-18 Michael Snyder
+
+ * include/opcode/h8sx.h (DO_MOVA1, DO_MOVA2): Reformatting.
+
+2003-07-15 Richard Sandiford
+
+ * mips.h (CPU_RM7000): New macro.
+ (OPCODE_IS_MEMBER): Match CPU_RM7000 against 4650 insns.
+
+2003-07-09 Alexandre Oliva
+
+ 2000-04-01 Alexandre Oliva
+ * mn10300.h (AM33_2): Renamed from AM33.
+ 2000-03-31 Alexandre Oliva
+ * mn10300.h (AM332, FMT_D3): Defined.
+ (MN10300_OPERAND_FSREG, MN10300_OPERAND_FDREG): Likewise.
+ (MN10300_OPERAND_FPCR): Likewise.
+
+2003-07-01 Martin Schwidefsky
+
+ * s390.h (s390_opcode_cpu_val): Add enum for cpu type z990.
+
+2003-06-25 Richard Sandiford
+
+ * h8300.h (IMM2_NS, IMM8_NS, IMM16_NS): Remove.
+ (IMM8U, IMM8U_NS): Define.
+ (h8_opcodes): Use IMM8U_NS for mov.[wl] #xx:8,@yy.
+
+2003-06-25 Richard Sandiford
+
+ * h8300.h (h8_opcodes): Fix the mov.l @(dd:32,ERs),ERd and
+ mov.l ERs,@(dd:32,ERd) entries.
+
+2003-06-23 H.J. Lu
+
+ * i386.h (i386_optab): Support Intel Precott New Instructions.
+
+2003-06-10 Gary Hade
+
+ * ppc.h (PPC_OPERAND_DQ): Define.
+
+2003-06-10 Richard Sandiford
+
+ * h8300.h (IMM4_NS, IMM8_NS): New.
+ (h8_opcodes): Replace IMM4 with IMM4_NS in mov.b and mov.w entries.
+ Likewise IMM8 for mov.w and mov.l. Likewise IMM16U for mov.l.
+
+2003-06-03 Michael Snyder
+
+ * h8300.h (enum h8_model): Add AV_H8S to distinguish from H8H.
+ (ldc): Split ccr ops from exr ops (which are only available
+ on H8S or H8SX).
+ (stc): Ditto.
+ (andc, orc, xorc): Ditto.
+ (ldmac, stmac, clrmac, mac): Change access to AV_H8S.
+
+2003-06-03 Michael Snyder
+ and Bernd Schmidt
+ and Alexandre Oliva
+ * h8300.h: Add support for h8300sx instruction set.
+
+2003-05-23 Jason Eckhardt
+
+ * i860.h (expand_type): Add XP_ONLY.
+ (scyc.b): New XP instruction.
+ (ldio.l): Likewise.
+ (ldio.s): Likewise.
+ (ldio.b): Likewise.
+ (ldint.l): Likewise.
+ (ldint.s): Likewise.
+ (ldint.b): Likewise.
+ (stio.l): Likewise.
+ (stio.s): Likewise.
+ (stio.b): Likewise.
+ (pfld.q): Likewise.
+
+2003-05-20 Jason Eckhardt
+
+ * i860.h (flush): Set lower 3 bits properly and use 'L'
+ for the immediate operand type instead of 'i'.
+
+2003-05-20 Jason Eckhardt
+
+ * i860.h (fzchks): Both S and R bits must be set.
+ (pfzchks): Likewise.
+ (faddp): Likewise.
+ (pfaddp): Likewise.
+ (fix.ss): Remove (invalid instruction).
+ (pfix.ss): Likewise.
+ (ftrunc.ss): Likewise.
+ (pftrunc.ss): Likewise.
+
+2003-05-18 Jason Eckhardt
+
+ * i860.h (form, pform): Add missing .dd suffix.
+
+2003-05-13 Stephane Carrez
+
+ * m68hc11.h (M68HC12_BANK_VIRT): Define to 0x010000
+
+2003-04-07 Michael Snyder
+
+ * h8300.h (ldc/stc): Fix up src/dst swaps.
+
+2003-04-09 J. Grant
+
+ * mips.h: Correct comment typo.
+
+2003-03-21 Martin Schwidefsky
+
+ * s390.h (s390_opcode_arch_val): Rename to s390_opcode_mode_val.
+ (S390_OPCODE_ESAME): Rename to S390_OPCODE_ZARCH.
+ (s390_opcode): Remove architecture. Add modes and min_cpu.
+
+2003-03-17 D.Venkatasubramanian
+
+ * h8300.h (O_SYS_CMDLINE): New pseudo opcode for command line
+ processing.
+
+2003-02-21 Noida D.Venkatasubramanian
+
+ * h8300.h (ldmac, stmac): Replace MACREG with MS32 and MD32.
+
+2003-01-23 Alan Modra
+
+ * m68hc11.h (cpu6812s): Define.
+
+2003-01-07 Chris Demetriou
+
+ * mips.h: Fix missing space in comment.
+ (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, INSN_ISA5)
+ (INSN_ISA32, INSN_ISA32R2, INSN_ISA64): Shift values right
+ by four bits.
+
+2003-01-02 Chris Demetriou
+
+ * mips.h: Update copyright years to include 2002 (which had
+ been missed previously) and 2003. Make comments about "+A",
+ "+B", and "+C" operand types more descriptive.
+
+2002-12-31 Chris Demetriou
+
+ * mips.h: Note that the "+D" operand type name is now used.
+
+2002-12-30 Chris Demetriou
+
+ * mips.h: Document "+" as the start of two-character operand
+ type names, and add new "K", "+A", "+B", and "+C" operand types.
+ (OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
+ (OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
+ defines.
+
+2002-12-24 Dmitry Diky
+
+ * msp430.h: New file. Defines msp430 opcodes.
+
+2002-12-30 D.Venkatasubramanian
+
+ * h8300.h: Added some more pseudo opcodes for system call
+ processing.
+
+2002-12-19 Chris Demetriou
+
+ * mips.h (OP_OP_COP0, OP_OP_COP1, OP_OP_COP2, OP_OP_COP3)
+ (OP_OP_LWC1, OP_OP_LWC2, OP_OP_LWC3, OP_OP_LDC1, OP_OP_LDC2)
+ (OP_OP_LDC3, OP_OP_SWC1, OP_OP_SWC2, OP_OP_SWC3, OP_OP_SDC1)
+ (OP_OP_SDC2, OP_OP_SDC3): Define.
+
+2002-12-16 Alan Modra
+
+ * hppa.h (completer_chars): #if 0 out.
+
+ * ns32k.h (struct ns32k_opcode): Constify "name", "operands" and
+ "default_args".
+ (struct not_wot): Constify "args".
+ (struct not): Constify "name".
+ (numopcodes): Delete.
+ (endop): Delete.
+
+2002-12-13 Alan Modra
+
+ * pj.h (pj_opc_info_t): Add union.
+
+2002-12-04 David Mosberger
+
+ * ia64.h: Fix copyright message.
+ (IA64_OPND_AR_CSD): New operand kind.
+
+2002-12-03 Richard Henderson
+
+ * ia64.h (enum ia64_opnd): Add IA64_OPND_LDXMOV.
+
+2002-12-03 Alan Modra
+
+ * cgen.h (struct cgen_maybe_multi_ifield): Add "const PTR p" to union.
+ Constify "leaf" and "multi".
+
+2002-11-19 Klee Dienes
+
+ * h8300.h (h8_opcode): Remove 'noperands', 'idx', and 'size'
+ fields.
+ (h8_opcodes). Modify initializer and initializer macros to no
+ longer initialize the removed fields.
+
+2002-11-19 Svein E. Seldal
+
+ * tic4x.h (c4x_insts): Fixed LDHI constraint
+
+2002-11-18 Klee Dienes
+
+ * h8300.h (h8_opcode): Remove 'length' field.
+ (h8_opcodes): Mark as 'const' (both the declaration and
+ definition). Modify initializer and initializer macros to no
+ longer initialize the length field.
+
+2002-11-18 Klee Dienes
+
+ * arc.h (arc_ext_opcodes): Declare as extern.
+ (arc_ext_operands): Declare as extern.
+ * i860.h (i860_opcodes): Declare as const.
+
+2002-11-18 Svein E. Seldal
+
+ * tic4x.h: File reordering. Added enhanced opcodes.
+
+2002-11-16 Svein E. Seldal
+
+ * tic4x.h: Major rewrite of entire file. Define instruction
+ classes, and put each instruction into a class.
+
+2002-11-11 Svein E. Seldal
+
+ * tic4x.h: Added new opcodes and corrected some bugs. Add support
+ for new DSP types.
+
+2002-10-14 Alan Modra
+
+ * cgen.h: Test __BFD_H_SEEN__ rather than BFD_VERSION_DATE.
+
+2002-09-30 Gavin Romig-Koch
+ Ken Raeburn
+ Aldy Hernandez
+ Eric Christopher
+ Richard Sandiford
+
+ * mips.h: Update comment for new opcodes.
+ (OP_MASK_VECBYTE, OP_SH_VECBYTE): New.
+ (OP_MASK_VECALIGN, OP_SH_VECALIGN): New.
+ (INSN_4111, INSN_4120, INSN_5400, INSN_5500): New.
+ (CPU_VR4120, CPU_VR5400, CPU_VR5500): New.
+ (OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags.
+ Don't match CPU_R4111 with INSN_4100.
+
+2002-08-19 Elena Zannoni
+
+ From matthew green
+
+ * ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500
+ instructions.
+ (PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR,
+ PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the
+ e500x2 Integer select, branch locking, performance monitor,
+ cache locking and machine check APUs, respectively.
+ (PPC_OPCODE_EFS): New opcode type for efs* instructions.
+ (PPC_OPCODE_CLASSIC): New opcode type for Classic PowerPC instructions.
+
+2002-08-13 Stephane Carrez
+
+ * m68hc11.h (M6812_OP_PAGE): Define to identify call operand.
+ (M68HC12_BANK_VIRT, M68HC12_BANK_MASK, M68HC12_BANK_BASE,
+ M68HC12_BANK_SHIFT, M68HC12_BANK_PAGE_MASK): Define for 68HC12
+ memory banks.
+ (M6811_OC1M5, M6811_OC1M4, M6811_MODF): Fix value.
+
+2002-07-09 Thiemo Seufer
+
+ * mips.h (INSN_MIPS16): New define.
+
+2002-07-08 Alan Modra
+
+ * i386.h: Remove IgnoreSize from movsx and movzx.
+
+2002-06-08 Alan Modra
+
+ * a29k.h: Replace CONST with const.
+ (CONST): Don't define.
+ * convex.h: Replace CONST with const.
+ (CONST): Don't define.
+ * dlx.h: Replace CONST with const.
+ * or32.h (CONST): Don't define.
+
+2002-05-30 Chris G. Demetriou
+
+ * mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
+ (MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
+ (MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
+ (INSN_MDMX): New constants, for MDMX support.
+ (opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
+
+2002-05-28 Kuang Hwa Lin
+
+ * dlx.h: New file.
+
+2002-05-25 Alan Modra
+
+ * ia64.h: Use #include "" instead of <> for local header files.
+ * sparc.h: Likewise.
+
+2002-05-22 Thiemo Seufer
+
+ * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
+2002-05-17 Andrey Volkov
+
+ * h8300.h: Corrected defs of all control regs
+ and eepmov instr.
+
+2002-04-11 Alan Modra
+
+ * i386.h: Add intel mode cmpsd and movsd.
+ Put them before SSE2 insns, so that rep prefix works.
+
+2002-03-15 Chris G. Demetriou
+
+ * mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D
+ instructions.
+ (OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks
+ may be passed along with the ISA bitmask.
+
+2002-03-05 Paul Koning
+
+ * pdp11.h: Add format codes for float instruction formats.
+
+2002-02-25 Alan Modra
+
+ * ppc.h (PPC_OPCODE_POWER4, PPC_OPCODE_NOPOWER4): Define.
+
+Mon Feb 18 17:31:48 CET 2002 Jan Hubicka
+
+ * i386.h (push,pop): Fix Reg64 to WordReg to allow 16bit operands.
+
+Mon Feb 11 12:53:19 CET 2002 Jan Hubicka
+
+ * i386.h (push,pop): Allow 16bit operands in 64bit mode.
+ (xchg): Fix.
+ (in, out): Disable 64bit operands.
+ (call, jmp): Avoid REX prefixes.
+ (jcxz): Prohibit in 64bit mode
+ (jrcxz, loop): Add 64bit variants.
+ (movq): Fix patterns.
+ (movmskps, pextrw, pinstrw): Add 64bit variants.
+
+2002-01-31 Ivan Guzvinec
+
+ * or32.h: New file.
+
+2002-01-22 Graydon Hoare
+
+ * cgen.h (CGEN_MAYBE_MULTI_IFLD): New structure.
+ (CGEN_OPERAND): Add CGEN_MAYBE_MULTI_IFLD field.
+
+2002-01-21 Thomas Klausner
+
+ * h8300.h: Comment typo fix.
+
+2002-01-03 matthew green
+
+ * ppc.h (PPC_OPCODE_BOOKE): BookE is not Motorola specific.
+ (PPC_OPCODE_BOOKE64): Likewise.
+
+Mon Dec 31 16:45:41 2001 Jeffrey A Law (law@cygnus.com)
+
+ * hppa.h (call, ret): Move to end of table.
+ (addb, addib): PA2.0 variants should have been PA2.0W.
+ (ldw, ldh, ldb, stw, sth, stb, stwa): Reorder to keep disassembler
+ happy.
+ (fldw, fldd, fstw, fstd, bb): Likewise.
+ (short loads/stores): Tweak format specifier slightly to keep
+ disassembler happy.
+ (indexed loads/stores): Likewise.
+ (absolute loads/stores): Likewise.
+
+2001-12-04 Alexandre Oliva
+
+ * d10v.h (OPERAND_NOSP): New macro.
+
+2001-11-29 Alexandre Oliva
+
+ * d10v.h (OPERAND_SP): New macro.
+
+2001-11-15 Alan Modra
+
+ * ppc.h (struct powerpc_operand ): Add dialect param.
+
+2001-11-11 Timothy Wall
+
+ * tic54x.h: Revise opcode layout; don't really need a separate
+ structure for parallel opcodes.
+
+2001-11-13 Zack Weinberg
+ Alan Modra
+
+ * i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to
+ accept WordReg.
+
+2001-11-04 Chris Demetriou
+
+ * mips.h (OPCODE_IS_MEMBER): Remove extra space.
+
+2001-10-30 Hans-Peter Nilsson
+
+ * mmix.h: New file.
+
+2001-10-18 Chris Demetriou
+
+ * mips.h (OPCODE_IS_MEMBER): Add a no-op term to the end
+ of the expression, to make source code merging easier.
+
+2001-10-17 Chris Demetriou
+
+ * mips.h: Sort coprocessor instruction argument characters
+ in comment, add a few more words of description for "H".
+
+2001-10-17 Chris Demetriou
+
+ * mips.h (INSN_SB1): New cpu-specific instruction bit.
+ (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1
+ if cpu is CPU_SB1.
+
+2001-10-17 matthew green
+
+ * ppc.h (PPC_OPCODE_BOOKE64): Fix typo.
+
+2001-10-12 matthew green
+
+ * ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_BOOKE64, PPC_OPCODE_403): New
+ opcode flags for BookE 32-bit, BookE 64-bit and PowerPC 403
+ instructions, respectively.
+
+2001-09-27 Nick Clifton
+
+ * v850.h: Remove spurious comment.
+
+2001-09-21 Nick Clifton
+
+ * h8300.h: Fix compile time warning messages
+
+2001-09-04 Richard Henderson
+
+ * alpha.h (struct alpha_operand): Pack elements into bitfields.
+
+2001-08-31 Eric Christopher
+
+ * mips.h: Remove CPU_MIPS32_4K.
+
+2001-08-27 Torbjorn Granlund
+
+ * ppc.h (PPC_OPERAND_DS): Define.
+
+2001-08-25 Andreas Jaeger
+
+ * d30v.h: Fix declaration of reg_name_cnt.
+
+ * d10v.h: Fix declaration of d10v_reg_name_cnt.
+
+ * arc.h: Add prototypes from opcodes/arc-opc.c.
+
+2001-08-16 Thiemo Seufer
+
+ * mips.h (INSN_10000): Define.
+ (OPCODE_IS_MEMBER): Check for INSN_10000.
+
+2001-08-10 Alan Modra
+
+ * ppc.h: Revert 2001-08-08.
+
+2001-08-10 Richard Sandiford
+
+ * mips.h (INSN_GP32): Remove.
+ (OPCODE_IS_MEMBER): Remove gp32 parameter.
+ (M_MOVE): New macro identifier.
+
+2001-08-08 Alan Modra
+
+ 1999-10-25 Torbjorn Granlund
+ * ppc.h (struct powerpc_operand): New field `reloc'.
+
+2001-08-01 Aldy Hernandez
+
+ * mips.h (INSN_ISA_MASK): Nuke bits 12-15.
+
+2001-07-12 Jeff Johnston
+
+ * cgen.h (CGEN_INSN): Add regex support.
+ (build_insn_regex): Declare.
+
+2001-07-11 Frank Ch. Eigler
+
+ * cgen.h (CGEN_MACH): Add insn_chunk_bitsize field.
+ (cgen_cpu_desc): Ditto.
+
+2001-07-07 Ben Elliston
+
+ * m88k.h: Clean up and reformat. Remove unused code.
+
+2001-06-14 Geoffrey Keating
+
+ * cgen.h (cgen_keyword): Add nonalpha_chars field.
+
+2001-05-23 Thiemo Seufer
+
+ * mips.h (CPU_R12000): Define.
+
+2001-05-23 John Healy
+
+ * cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48.
+
+2001-05-15 Thiemo Seufer
+
+ * mips.h (INSN_ISA_MASK): Define.
+
+2001-05-12 Alan Modra
+
+ * i386.h (i386_optab): Second operand of cvtps2dq is an xmm reg,
+ not an mmx reg. Swap xmm/mmx regs on both movdq2q and movq2dq,
+ and use InvMem as these insns must have register operands.
+
+2001-05-04 Alan Modra
+
+ * i386.h (i386_optab): Move InvMem to first operand of pmovmskb
+ and pextrw to swap reg/rm assignments.
+
+2001-04-05 Hans-Peter Nilsson
+
+ * cris.h (enum cris_insn_version_usage): Correct comment for
+ cris_ver_v3p.
+
+2001-03-24 Alan Modra
+
+ * i386.h (i386_optab): Correct entry for "movntdq". Add "punpcklqdq".
+ Add InvMem to first operand of "maskmovdqu".
+
+2001-03-22 Hans-Peter Nilsson
+
+ * cris.h (ADD_PC_INCR_OPCODE): New macro.
+
+2001-03-21 Kazu Hirata
+
+ * h8300.h: Fix formatting.
+
+2001-03-22 Alan Modra
+
+ * i386.h (i386_optab): Add paddq, psubq.
+
+2001-03-19 Alan Modra
+
+ * i386.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Define.
+
+2001-02-28 Igor Shevlyakov
+
+ * m68k.h: new defines for Coldfire V4. Update mcf to know
+ about mcf5407.
+
+2001-02-18 lars brinkhoff
+
+ * pdp11.h: New file.
+
+2001-02-12 Jan Hubicka
+
+ * i386.h (i386_optab): SSE integer converison instructions have
+ 64bit versions on x86-64.
+
+2001-02-10 Nick Clifton
+
+ * mips.h: Remove extraneous whitespace. Formating change to allow
+ for future contribution.
+
+2001-02-09 Martin Schwidefsky
+
+ * s390.h: New file.
+
+2001-02-02 Patrick Macdonald
+
+ * cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short.
+ (CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES.
+ (CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS.
+
+2001-01-24 Karsten Keil
+
+ * i386.h (i386_optab): Fix swapgs
+
+2001-01-14 Alan Modra
+
+ * hppa.h: Describe new '<' and '>' operand types, and tidy
+ existing comments.
+ (pa_opcodes): Add entries for missing wide mode ldi,ldo,ldw,stw.
+ Remove duplicate "ldw j(s,b),x". Sort some entries.
+
+2001-01-13 Jan Hubicka
+
+ * i386.h (i386_optab): Fix pusha and ret templates.
+
+2001-01-11 Peter Targett
+
+ * arc.h (ARC_MACH_5, ARC_MACH_6, ARC_MACH_7, ARC_MACH_8): New
+ definitions for masking cpu type.
+ (arc_ext_operand_value) New structure for storing extended
+ operands.
+ (ARC_OPERAND_*) Flags for operand values.
+
+2001-01-10 Jan Hubicka
+
+ * i386.h (pinsrw): Add.
+ (pshufw): Remove.
+ (cvttpd2dq): Fix operands.
+ (cvttps2dq): Likewise.
+ (movq2q): Rename to movdq2q.
+
+2001-01-10 Richard Schaal
+
+ * i386.h: Correct movnti instruction.
+
+2001-01-09 Jeff Johnston
+
+ * cgen.h (CGEN_SYNTAX_CHAR_TYPE): New typedef based on max number
+ of operands (unsigned char or unsigned short).
+ (CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE.
+ (CGEN_SYNTAX_CHAR): Changed to cast to unsigned char.
+
+2001-01-05 Jan Hubicka
+
+ * i386.h (i386_optab): Make [sml]fence template to use immext field.
+
+2001-01-03 Jan Hubicka
+
+ * i386.h (i386_optab): Fix 64bit pushf template; Add instructions
+ introduced by Pentium4
+
+2000-12-30 Jan Hubicka
+
+ * i386.h (i386_optab): Add "rex*" instructions;
+ add swapgs; disable jmp/call far direct instructions for
+ 64bit mode; add syscall and sysret; disable registers for 0xc6
+ template. Add 'q' suffixes to extendable instructions, disable
+ obsolete instructions, add new sign/zero extension ones.
+ (i386_regtab): Add extended registers.
+ (*Suf): Add No_qSuf.
+ (q_Suf, wlq_Suf, bwlq_Suf): New.
+
+2000-12-20 Jan Hubicka
+
+ * i386.h (i386_optab): Replace "Imm" with "EncImm".
+ (i386_regtab): Add flags field.
+
+2000-12-12 Nick Clifton
+
+ * mips.h: Fix formatting.
+
+2000-12-01 Chris Demetriou
+
+ mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete.
+ (OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old
+ OP_*_SYSCALL definitions.
+ (OP_SH_CODE19, OP_MASK_CODE19): Define, for use as
+ 19 bit wait codes.
+ (MIPS operand specifier comments): Remove 'm', add 'U' and
+ 'J', and update the meaning of 'B' so that it's more general.
+
+ * mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4,
+ INSN_ISA5): Renumber, redefine to mean the ISA at which the
+ instruction was added.
+ (INSN_ISA32): New constant.
+ (INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32):
+ Renumber to avoid new and/or renumbered INSN_* constants.
+ (INSN_MIPS32): Delete.
+ (ISA_UNKNOWN): New constant to indicate unknown ISA.
+ (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5,
+ ISA_MIPS32): New constants, defined to be the mask of INSN_*
+ constants available at that ISA level.
+ (CPU_UNKNOWN): New constant to indicate unknown CPU.
+ (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter,
+ define it with a unique value.
+ (OPCODE_IS_MEMBER): Update for new ISA membership-related
+ constant meanings.
+
+ * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New
+ definitions.
+
+ * mips.h (CPU_SB1): New constant.
+
+2000-10-20 Jakub Jelinek
+
+ * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
+ Note that '3' is used for siam operand.
+
+2000-09-22 Jim Wilson
+
+ * ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP.
+
+2000-09-13 Anders Norlander
+
+ * mips.h: Use defines instead of hard-coded processor numbers.
+ (CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010,
+ CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650,
+ CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K,
+ CPU_4KC, CPU_4KM, CPU_4KP): Define..
+ (OPCODE_IS_MEMBER): Use new defines.
+ (OP_MASK_SEL, OP_SH_SEL): Define.
+ (OP_MASK_CODE20, OP_SH_CODE20): Define.
+ Add 'P' to used characters.
+ Use 'H' for coprocessor select field.
+ Use 'm' for 20 bit breakpoint code.
+ Document new arg characters and add to used characters.
+ (INSN_MIPS32): New define for MIPS32 extensions.
+ (OPCODE_IS_MEMBER): Recognize MIPS32 instructions.
+
+2000-09-05 Alan Modra
+
+ * hppa.h: Mention cz completer.
+
+2000-08-16 Jim Wilson
+
+ * ia64.h (IA64_OPCODE_POSTINC): New.
+
+2000-08-15 H.J. Lu
+
+ * i386.h: Swap the Intel syntax "movsx"/"movzx" due to the
+ IgnoreSize change.
+
+2000-08-08 Jason Eckhardt
+
+ * i860.h: Small formatting adjustments.
+
+2000-07-29 Marek Michalkiewicz
+
+ * avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros.
+ Move related opcodes closer to each other.
+ Minor changes in comments, list undefined opcodes.
+
+2000-07-26 Dave Brolley
+
+ * cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned.
+
+2000-07-22 Jason Eckhardt
+
+ * i860.h (btne, bte, bla): Changed these opcodes
+ to use sbroff ('r') instead of split16 ('s').
+ (J, K, L, M): New operand types for 16-bit aligned fields.
+ (ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to
+ use I, J, K, L, M instead of just I.
+ (T, U): New operand types for split 16-bit aligned fields.
+ (st.x): Changed these opcodes to use S, T, U instead of just S.
+ (andh, andnoth, orh, xorh): Deleted 3-register forms as they do not
+ exist on the i860.
+ (pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860.
+ (pfeq.ss, pfeq.dd): New opcodes.
+ (st.s): Fixed incorrect mask bits.
+ (fmlow): Fixed incorrect mask bits.
+ (fzchkl, pfzchkl): Fixed incorrect mask bits.
+ (faddz, pfaddz): Fixed incorrect mask bits.
+ (form, pform): Fixed incorrect mask bits.
+ (pfld.l): Fixed incorrect mask bits.
+ (fst.q): Fixed incorrect mask bits.
+ (all floating point opcodes): Fixed incorrect mask bits for
+ handling of dual bit.
+
+2000-07-20 Hans-Peter Nilsson
+
+ cris.h: New file.
+
+2000-06-26 Marek Michalkiewicz
+
+ * avr.h (AVR_ISA_WRAP): Remove, now assumed if not AVR_ISA_MEGA.
+ (AVR_ISA_ESPM): Remove, because ESPM removed in databook update.
+ (AVR_ISA_85xx): Remove, all uses changed back to AVR_ISA_2xxx.
+ (AVR_ISA_M83): Define for ATmega83, ATmega85.
+ (espm): Remove, because ESPM removed in databook update.
+ (eicall, eijmp): Move to the end of opcode table.
+
+2000-06-18 Stephane Carrez
+
+ * m68hc11.h: New file for support of Motorola 68hc11.
+
+Fri Jun 9 21:51:50 2000 Denis Chertykov
+
+ * avr.h: clr,lsl,rol, ... moved after add,adc, ...
+
+Wed Jun 7 21:39:54 2000 Denis Chertykov
+
+ * avr.h: New file with AVR opcodes.
+
+Wed Apr 12 17:11:20 2000 Donald Lindsay
+
+ * d10v.h: added ALONE attribute for d10v_opcode.exec_type.
+
+2000-05-23 Maciej W. Rozycki
+
+ * i386.h: Allow d suffix on iret, and add DefaultSize modifier.
+
+2000-05-17 Maciej W. Rozycki
+
+ * i386.h: Use sl_FP, not sl_Suf for fild.
+
+2000-05-16 Frank Ch. Eigler
+
+ * cgen.h (CGEN_MAX_SYNTAX_BYTES): Increase to 32. Check that
+ it exceeds CGEN_ACTUAL_MAX_SYNTAX_BYTES, if set.
+ (CGEN_MAX_IFMT_OPERANDS): Increase to 16. Check that it exceeds
+ CGEN_ACTUAL_MAX_IFMT_OPERANDS, if set.
+
+2000-05-13 Alan Modra ,
+
+ * i386.h (i386_optab): Cpu686 for sysenter,sysexit,fxsave,fxrestore.
+
+2000-05-13 Alan Modra ,
+ Alexander Sokolov
+
+ * i386.h (i386_optab): Add cpu_flags for all instructions.
+
+2000-05-13 Alan Modra
+
+ From Gavin Romig-Koch
+ * i386.h (wld_Suf): Define. Use on pushf, popf, pusha, popa.
+
+2000-05-04 Timothy Wall
+
+ * tic54x.h: New.
+
+2000-05-03 J.T. Conklin
+
+ * ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit.
+ (PPC_OPERAND_VR): New operand flag for vector registers.
+
+2000-05-01 Kazu Hirata
+
+ * h8300.h (EOP): Add missing initializer.
+
+Fri Apr 21 15:03:37 2000 Jason Eckhardt
+
+ * hppa.h (pa_opcodes): New opcodes for PA2.0 wide mode
+ forms of ld/st{b,h,w,d} and fld/fst{w,d} (16-bit displacements).
+ New operand types l,y,&,fe,fE,fx added to support above forms.
+ (pa_opcodes): Replaced usage of 'x' as source/target for
+ floating point double-word loads/stores with 'fx'.
+
+Fri Apr 21 13:20:53 2000 Richard Henderson
+ David Mosberger
+ Timothy Wall
+ Jim Wilson
+
+ * ia64.h: New file.
+
+2000-03-27 Nick Clifton
+
+ * d30v.h (SHORT_A1): Fix value.
+ (SHORT_AR): Renumber so that it is at the end of the list of short
+ instructions, not the end of the list of long instructions.
+
+2000-03-26 Alan Modra
+
+ * i386.h: (UNIXWARE_COMPAT): Rename to SYSV386_COMPAT as the
+ problem isn't really specific to Unixware.
+ (OLDGCC_COMPAT): Define.
+ (i386_optab): If !OLDGCC_COMPAT, don't handle fsubp etc. with
+ destination %st(0).
+ Fix lots of comments.
+
+2000-03-02 J"orn Rennecke
+
+ * d30v.h:
+ (SHORT_B2r, SHORT_B3, SHORT_B3r, SHORT_B3b, SHORT_B3br): Updated.
+ (SHORT_D1r, SHORT_D2, SHORT_D2r, SHORT_D2Br, SHORT_U): Updated.
+ (SHORT_F, SHORT_AF, SHORT_T, SHORT_A5, SHORT_CMP, SHORT_CMPU): Updated.
+ (SHORT_A1, SHORT_AA, SHORT_RA, SHORT_MODINC, SHORT_MODDEC): Updated.
+ (SHORT_C1, SHORT_C2, SHORT_UF, SHORT_A2, SHORT_NONE, LONG): Updated.
+ (LONG_U, LONG_Ur, LONG_CMP, LONG_M, LONG_M2, LONG_2, LONG_2r): Updated.
+ (LONG_2b, LONG_2br, LONG_D, LONG_Dr, LONG_Dbr): Updated.
+
+2000-02-25 Alan Modra
+
+ * i386.h (fild, fistp): Change intel d_Suf form to fildd and
+ fistpd without suffix.
+
+2000-02-24 Nick Clifton
+
+ * cgen.h (cgen_cpu_desc): Rename field 'flags' to
+ 'signed_overflow_ok_p'.
+ Delete prototypes for cgen_set_flags() and cgen_get_flags().
+
+2000-02-24 Andrew Haley
+
+ * cgen.h (CGEN_INSN_MACH_HAS_P): New macro.
+ (CGEN_CPU_TABLE): flags: new field.
+ Add prototypes for new functions.
+
+2000-02-24 Alan Modra
+
+ * i386.h: Add some more UNIXWARE_COMPAT comments.
+
+2000-02-23 Linas Vepstas
+
+ * i370.h: New file.
+
+2000-02-22 Chandra Chavva
+
+ * d30v.h (FLAG_NOT_WITH_ADDSUBppp): Redefined as operation
+ cannot be combined in parallel with ADD/SUBppp.
+
+2000-02-22 Andrew Haley
+
+ * mips.h: (OPCODE_IS_MEMBER): Add comment.
+
+1999-12-30 Andrew Haley
+
+ * mips.h (OPCODE_IS_MEMBER): Add gp32 arg, which determines
+ whether synthetic opcodes (e.g. move) generate 32-bit or 64-bit
+ insns.
+
+2000-01-15 Alan Modra
+
+ * i386.h: Qualify intel mode far call and jmp with x_Suf.
+
+1999-12-27 Alan Modra
+
+ * i386.h: Add JumpAbsolute qualifier to all non-intel mode
+ indirect jumps and calls. Add FF/3 call for intel mode.
+
+Wed Dec 1 03:05:25 1999 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300.h: Add new operand types. Add new instruction formats.
+
+Wed Nov 24 20:28:58 1999 Jeffrey A Law (law@cygnus.com)
+
+ * hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb"
+ instruction.
+
+1999-11-18 Gavin Romig-Koch
+
+ * mips.h (INSN_ISA5): New.
+
+1999-11-01 Gavin Romig-Koch
+
+ * mips.h (OPCODE_IS_MEMBER): New.
+
+1999-10-29 Nick Clifton
+
+ * d30v.h (SHORT_AR): Define.
+
+1999-10-18 Michael Meissner
+
+ * alpha.h (alpha_num_opcodes): Convert to unsigned.
+ (alpha_num_operands): Ditto.
+
+Sun Oct 10 01:46:56 1999 Jerry Quinn
+
+ * hppa.h (pa_opcodes): Add load and store cache control to
+ instructions. Add ordered access load and store.
+
+ * hppa.h (pa_opcode): Add new entries for addb and addib.
+
+ * hppa.h (pa_opcodes): Fix cmpb and cmpib entries.
+
+ * hppa.h (pa_opcodes): Add entries for cmpb and cmpib.
+
+Thu Oct 7 00:12:25 MDT 1999 Diego Novillo
+
+ * d10v.h: Add flag RESTRICTED_NUM3 for imm3 operands.
+
+Thu Sep 23 07:08:38 1999 Jerry Quinn
+
+ * hppa.h (pa_opcodes): Add "call" and "ret". Clean up "b", "bve"
+ and "be" using completer prefixes.
+
+ * hppa.h (pa_opcodes): Add initializers to silence compiler.
+
+ * hppa.h: Update comments about character usage.
+
+Mon Sep 20 03:55:31 1999 Jeffrey A Law (law@cygnus.com)
+
+ * hppa.h (pa_opcodes): Fix minor thinkos introduced while cleaning
+ up the new fstw & bve instructions.
+
+Sun Sep 19 10:40:59 1999 Jeffrey A Law (law@cygnus.com)
+
+ * hppa.h (pa_opcodes): Add remaining PA2.0 integer load/store
+ instructions.
+
+ * hppa.h (pa_opcodes): Add remaining PA2.0 FP load/store instructions.
+
+ * hppa.h (pa_opcodes): Add long offset double word load/store
+ instructions.
+
+ * hppa.h (pa_opcodes): Add FLAG_STRICT variants of FP loads and
+ stores.
+
+ * hppa.h (pa_opcodes): Handle PA2.0 fcnv, fcmp and ftest insns.
+
+ * hppa.h (pa_opcodes): Finish support for PA2.0 "b" instructions.
+
+ * hppa.h (pa_opcodes): Handle PA2.0 "bve" instructions.
+
+ * hppa.h (pa_opcodes): Add new syntax "be" instructions.
+
+ * hppa.h (pa_opcodes): Note use of 'M' and 'L'.
+
+ * hppa.h (pa_opcodes): Add support for "b,l".
+
+ * hppa.h (pa_opcodes): Add support for "b,gate".
+
+Sat Sep 18 11:41:16 1999 Jeffrey A Law (law@cygnus.com)
+
+ * hppa.h (pa_opcodes): Use 'fX' for first register operand
+ in xmpyu.
+
+ * hppa.h (pa_opcodes): Fix mask for probe and probei.
+
+ * hppa.h (pa_opcodes): Fix mask for depwi.
+
+Tue Sep 7 13:44:25 1999 Jeffrey A Law (law@cygnus.com)
+
+ * hppa.h (pa_opcodes): Add "addil" variant which has the %r1 as
+ an explicit output argument.
+
+Mon Sep 6 04:41:42 1999 Jeffrey A Law (law@cygnus.com)
+
+ * hppa.h: Add strict variants of PA1.0/PA1.1 loads and stores.
+ Add a few PA2.0 loads and store variants.
+
+1999-09-04 Steve Chamberlain
+
+ * pj.h: New file.
+
+1999-08-29 Alan Modra
+
+ * i386.h (i386_regtab): Move %st to top of table, and split off
+ other fp reg entries.
+ (i386_float_regtab): To here.
+
+Sat Aug 28 00:25:25 1999 Jerry Quinn
+
+ * hppa.h (pa_opcodes): Replace 'f' by 'v'. Prefix float register args
+ by 'f'.
+
+ * hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi.
+ Add supporting args.
+
+ * hppa.h: Document new completers and args.
+ * hppa.h (pa_opcodes): Add 64 bit patterns and pa2.0 syntax for uxor,
+ uaddcm, dcor, addi, add, sub, subi, shladd, rfi, and probe. Add pa2.0
+ extensions for ssm, rsm, pdtlb, pitlb. Add performance instructions
+ pmenb and pmdis.
+
+ * hppa.h (pa_opcodes): Add pa2.0 instructions hadd, hshl,
+ hshr, hsub, mixh, mixw, permh.
+
+ * hppa.h (pa_opcodes): Change completers in instructions to
+ use 'c' prefix.
+
+ * hppa.h (pa_opcodes): Add popbts, new forms of bb, havg,
+ hshladd, hshradd, shrpd, and shrpw instructions. Update arg comments.
+
+ * hppa.h (pa_opcodes): Change fmpyfadd, fmpynfadd, fneg,
+ fnegabs to use 'I' instead of 'F'.
+
+1999-08-21 Alan Modra
+
+ * i386.h: Add AMD athlon instructions, pfnacc, pfpnacc, pswapd.
+ Document pf2iw and pi2fw as athlon insns. Remove pswapw.
+ Alphabetically sort PIII insns.
+
+Wed Aug 18 18:14:40 1999 Doug Evans
+
+ * cgen.h (CGEN_INSN_MACH_HAS_P): New macro.
+
+Fri Aug 6 09:46:35 1999 Jerry Quinn
+
+ * hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and,
+ and andcm. Add 32 and 64 bit version of cmpclr, cmpiclr.
+
+ * hppa.h: Document 64 bit condition completers.
+
+Thu Aug 5 16:56:07 1999 Jerry Quinn
+
+ * hppa.h (pa_opcodes): Change condition args to use '?' prefix.
+
+1999-08-04 Alan Modra
+
+ * i386.h (i386_optab): Add DefaultSize modifier to all insns
+ that implicitly modify %esp. #undef d_Suf, x_suf, sld_suf,
+ sldx_suf, bwld_Suf, d_FP, x_FP, sld_FP, sldx_FP at end of table.
+
+Wed Jul 28 02:04:24 1999 Jerry Quinn
+ Jeff Law
+
+ * hppa.h (pa_opcodes): Add "pushnom" and "pushbts".
+
+ * hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT.
+
+ * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd,
+ and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'.
+
+1999-07-13 Alan Modra
+
+ * i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw insns.
+
+Thu Jul 1 00:17:24 1999 Jeffrey A Law (law@cygnus.com)
+
+ * hppa.h (struct pa_opcode): Add new field "flags".
+ (FLAGS_STRICT): Define.
+
+Fri Jun 25 04:22:04 1999 Jerry Quinn
+ Jeff Law
+
+ * hppa.h (pa_opcodes): Add pa2.0 clrbts instruction.
+
+ * hppa.h (pa_opcodes): Add entries for mfia and mtsarcm instructions.
+
+1999-06-23 Alan Modra
+
+ * i386.h: Allow `l' suffix on bswap. Allow `w' suffix on arpl,
+ lldt, lmsw, ltr, str, verr, verw. Add FP flag to fcmov*. Add FP
+ flag to fcomi and friends.
+
+Fri May 28 15:26:11 1999 Jeffrey A Law (law@cygnus.com)
+
+ * hppa.h (pa_opcodes): Move integer arithmetic instructions after
+ integer logical instructions.
+
+1999-05-28 Linus Nordberg
+
+ * m68k.h: Document new formats `E', `G', `H' and new places `N',
+ `n', `o'.
+
+ * m68k.h: Define mcf5206e, mcf5307, mcf. Document new format `u'
+ and new places `m', `M', `h'.
+
+Thu May 27 04:13:54 1999 Joel Sherrill (joel@OARcorp.com
+
+ * hppa.h (pa_opcodes): Add several processor specific system
+ instructions.
+
+Wed May 26 16:57:44 1999 Jeffrey A Law (law@cygnus.com)
+
+ * hppa.h (pa_opcodes): Add second entry for "comb", "comib",
+ "addb", and "addib" to be used by the disassembler.
+
+1999-05-12 Alan Modra
+
+ * i386.h (ReverseModrm): Remove all occurences.
+ (InvMem): Add to control/debug/test mov insns, movhlps, movlhps,
+ movmskps, pextrw, pmovmskb, maskmovq.
+ Change NoSuf to FP on all MMX, XMM and AMD insns as these all
+ ignore the data size prefix.
+
+ * i386.h (i386_optab, i386_regtab): Add support for PIII SIMD.
+ Mostly stolen from Doug Ledford
+
+Sat May 8 23:27:35 1999 Richard Henderson
+
+ * ppc.h (PPC_OPCODE_64_BRIDGE): New.
+
+1999-04-14 Doug Evans
+
+ * cgen.h (CGEN_ATTR): Delete member num_nonbools.
+ (CGEN_ATTR_TYPE): Update.
+ (CGEN_ATTR_MASK): Number booleans starting at 0.
+ (CGEN_ATTR_VALUE): Update.
+ (CGEN_INSN_ATTR): Update.
+
+Mon Apr 12 23:43:27 1999 Jeffrey A Law (law@cygnus.com)
+
+ * hppa.h (fmpyfadd, fmpynfadd, fneg, fnegabs): New PA2.0
+ instructions.
+
+Tue Mar 23 11:24:38 1999 Jeffrey A Law (law@cygnus.com)
+
+ * hppa.h (bb, bvb): Tweak opcode/mask.
+
+
+1999-03-22 Doug Evans
+
+ * cgen.h (CGEN_ISA,CGEN_MACH): New typedefs.
+ (struct cgen_cpu_desc): Rename member mach to machs. New member isas.
+ New members word_bitsize,default_insn_bitsize,base_insn-bitsize,
+ min_insn_bitsize,max_insn_bitsize,isa_table,mach_table,rebuild_tables.
+ Delete member max_insn_size.
+ (enum cgen_cpu_open_arg): New enum.
+ (cpu_open): Update prototype.
+ (cpu_open_1): Declare.
+ (cgen_set_cpu): Delete.
+
+1999-03-11 Doug Evans
+
+ * cgen.h (CGEN_HW_TABLE): Delete `num_init_entries' member.
+ (CGEN_OPERAND_NIL): New macro.
+ (CGEN_OPERAND): New member `type'.
+ (@arch@_cgen_operand_table): Delete decl.
+ (CGEN_OPERAND_INDEX,CGEN_OPERAND_TYPE,CGEN_OPERAND_ENTRY): Delete.
+ (CGEN_OPERAND_TABLE): New struct.
+ (cgen_operand_lookup_by_name,cgen_operand_lookup_by_num): Declare.
+ (CGEN_OPINST): Pointer to operand table entry replaced with enum.
+ (CGEN_CPU_TABLE): New member `isa'. Change member `operand_table',
+ now a CGEN_OPERAND_TABLE. Add CGEN_CPU_DESC arg to
+ {get,set}_{int,vma}_operand.
+ (@arch@_cgen_cpu_open): New arg `isa'.
+ (cgen_set_cpu): Ditto.
+
+Fri Feb 26 02:36:45 1999 Richard Henderson
+
+ * i386.h: Fill in cmov and fcmov alternates. Add fcomi short forms.
+
+1999-02-25 Doug Evans
+
+ * cgen.h (enum cgen_asm_type): Add CGEN_ASM_NONE.
+ (CGEN_HW_ENTRY): Delete member `next'. Change type of `type' to
+ enum cgen_hw_type.
+ (CGEN_HW_TABLE): New struct.
+ (hw_table): Delete declaration.
+ (CGEN_OPERAND): Change member hw to hw_type, change type from pointer
+ to table entry to enum.
+ (CGEN_OPINST): Ditto.
+ (CGEN_CPU_TABLE): Change member hw_list to hw_table.
+
+Sat Feb 13 14:13:44 1999 Richard Henderson
+
+ * alpha.h (AXP_OPCODE_EV6): New.
+ (AXP_OPCODE_NOPAL): Include it.
+
+1999-02-09 Doug Evans
+
+ * cgen.h (CGEN_CPU_DESC): Renamed from CGEN_OPCODE_DESC.
+ All uses updated. New members int_insn_p, max_insn_size,
+ parse_operand,insert_operand,extract_operand,print_operand,
+ sizeof_fields,set_fields_bitsize,get_int_operand,set_int_operand,
+ get_vma_operand,set_vma_operand,parse_handlers,insert_handlers,
+ extract_handlers,print_handlers.
+ (CGEN_ATTR): Change type of num_nonbools to unsigned int.
+ (CGEN_ATTR_BOOL_OFFSET): New macro.
+ (CGEN_ATTR_MASK): Subtract it to compute bit number.
+ (CGEN_ATTR_VALUE): Redo bool/nonbool attr calculation.
+ (cgen_opcode_handler): Renamed from cgen_base.
+ (CGEN_HW_ATTR_VALUE): Renamed from CGEN_HW_ATTR, all uses updated.
+ (CGEN_OPERAND_ATTR_VALUE): Renamed from CGEN_OPERAND_ATTR,
+ all uses updated.
+ (CGEN_OPERAND_INDEX): Rewrite to use table entry, not global.
+ (enum cgen_opinst_type): Renamed from cgen_operand_instance_type.
+ (CGEN_IFLD_ATTR_VALUE): Renamed from CGEN_IFLD_ATTR, all uses updated.
+ (CGEN_OPCODE,CGEN_IBASE): New types.
+ (CGEN_INSN): Rewrite.
+ (CGEN_{ASM,DIS}_HASH*): Delete.
+ (init_opcode_table,init_ibld_table): Declare.
+ (CGEN_INSN_ATTR): New type.
+
+Mon Feb 1 21:09:14 1999 Catherine Moore
+
+ * i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf): Define.
+ (x_FP, d_FP, dls_FP, sldx_FP): Define.
+ Change *Suf definitions to include x and d suffixes.
+ (movsx): Use w_Suf and b_Suf.
+ (movzx): Likewise.
+ (movs): Use bwld_Suf.
+ (fld): Change ordering. Use sld_FP.
+ (fild): Add Intel Syntax equivalent of fildq.
+ (fst): Use sld_FP.
+ (fist): Use sld_FP.
+ (fstp): Use sld_FP. Add x_FP version.
+ (fistp): LLongMem version for Intel Syntax.
+ (fcom, fcomp): Use sld_FP.
+ (fadd, fiadd, fsub): Use sld_FP.
+ (fsubr): Use sld_FP.
+ (fmul, fimul, fdvi, fidiv, fdivr): Use sld_FP.
+
+1999-01-27 Doug Evans
+
+ * cgen.h (enum cgen_mode): Add CGEN_MODE_TARGET_MAX, CGEN_MODE_INT,
+ CGEN_MODE_UINT.
+
+1999-01-16 Jeffrey A Law (law@cygnus.com)
+
+ * hppa.h (bv): Fix mask.
+
+1999-01-05 Doug Evans
+
+ * cgen.h (CGEN_ATTR_VALUE_TYPE): New typedef.
+ (CGEN_ATTR): Use it.
+ (CGEN_ATTR_TYPE,CGEN_ATTR_ENTRY): Ditto.
+ (CGEN_ATTR_TABLE): New member dfault.
+
+1998-12-30 Gavin Romig-Koch
+
+ * mips.h (MIPS16_INSN_BRANCH): New.
+
+Wed Dec 9 10:38:48 1998 David Taylor
+
+ The following is part of a change made by Edith Epstein
+ as part of a project to merge in
+ changes by HP; HP did not create ChangeLog entries.
+
+ * hppa.h (completer_chars): list of chars to not put a space
+ after.
+
+Sun Dec 6 13:21:34 1998 Ian Lance Taylor
+
+ * i386.h (i386_optab): Permit w suffix on processor control and
+ status word instructions.
+
+1998-11-30 Doug Evans
+
+ * cgen.h (struct cgen_hw_entry): Delete const on attrs member.
+ (struct cgen_keyword_entry): Ditto.
+ (struct cgen_operand): Ditto.
+ (CGEN_IFLD): New typedef, with associated access macros.
+ (CGEN_IFMT): New typedef, with associated access macros.
+ (CGEN_IFMT): Renamed from CGEN_FORMAT. New member `iflds'.
+ (CGEN_IVALUE): New typedef.
+ (struct cgen_insn): Delete const on syntax,attrs members.
+ `format' now points to format data. Type of `value' is now
+ CGEN_IVALUE.
+ (struct cgen_opcode_table): New member ifld_table.
+
+1998-11-18 Doug Evans
+
+ * cgen.h (cgen_extract_fn): Update type of `base_insn' arg.
+ (CGEN_OPERAND_INSTANCE): New member `attrs'.
+ (CGEN_OPERAND_INSTANCE_{ATTRS,ATTR}): New macros.
+ (cgen_dis_lookup_insn): Update type of `base_insn' arg.
+ (cgen_opcode_table): Update type of dis_hash fn.
+ (extract_operand): Update type of `insn_value' arg.
+
+Thu Oct 29 11:38:36 1998 Doug Evans
+
+ * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Delete.
+
+Tue Oct 27 08:57:59 1998 Gavin Romig-Koch
+
+ * mips.h (INSN_MULT): Added.
+
+Tue Oct 20 11:31:34 1998 Alan Modra
+
+ * i386.h (MAX_MNEM_SIZE): Rename from MAX_OPCODE_SIZE.
+
+Mon Oct 19 12:50:00 1998 Doug Evans
+
+ * cgen.h (CGEN_INSN_INT): New typedef.
+ (CGEN_INT_INSN_P): Renamed from CGEN_INT_INSN.
+ (CGEN_INSN_BYTES): Renamed from cgen_insn_t.
+ (CGEN_INSN_BYTES_PTR): New typedef.
+ (CGEN_EXTRACT_INFO): New typedef.
+ (cgen_insert_fn,cgen_extract_fn): Update.
+ (cgen_opcode_table): New member `insn_endian'.
+ (assemble_insn,lookup_insn,lookup_get_insn_operands): Update.
+ (insert_operand,extract_operand): Update.
+ (cgen_get_insn_value,cgen_put_insn_value): Add prototypes.
+
+Fri Oct 9 13:38:13 1998 Doug Evans
+
+ * cgen.h (CGEN_ATTR_BOOLS): New macro.
+ (struct CGEN_HW_ENTRY): New member `attrs'.
+ (CGEN_HW_ATTR): New macro.
+ (struct CGEN_OPERAND_INSTANCE): New member `name'.
+ (CGEN_INSN_INVALID_P): New macro.
+
+Mon Oct 5 00:21:07 1998 Jeffrey A Law (law@cygnus.com)
+
+ * hppa.h: Add "fid".
+
+Sun Oct 4 21:00:00 1998 Alan Modra
+
+ From Robert Andrew Dale
+ * i386.h (i386_optab): Add AMD 3DNow! instructions.
+ (AMD_3DNOW_OPCODE): Define.
+
+Tue Sep 22 17:53:47 1998 Nick Clifton
+
+ * d30v.h (EITHER_BUT_PREFER_MU): Define.
+
+Mon Aug 10 14:09:38 1998 Doug Evans
+
+ * cgen.h (cgen_insn): #if 0 out element `cdx'.
+
+Mon Aug 3 12:21:57 1998 Doug Evans
+
+ Move all global state data into opcode table struct, and treat
+ opcode table as something that is "opened/closed".
+ * cgen.h (CGEN_OPCODE_DESC): New type.
+ (all fns): New first arg of opcode table descriptor.
+ (cgen_set_parse_operand_fn): Add prototype.
+ (cgen_current_machine,cgen_current_endian): Delete.
+ (CGEN_OPCODE_TABLE): New members mach,endian,operand_table,
+ parse_operand_fn,asm_hash_table,asm_hash_table_entries,
+ dis_hash_table,dis_hash_table_entries.
+ (opcode_open,opcode_close): Add prototypes.
+
+ * cgen.h (cgen_insn): New element `cdx'.
+
+Thu Jul 30 21:44:25 1998 Frank Ch. Eigler
+
+ * d30v.h (FLAG_LKR): New flag for "left-kills-right" instructions.
+
+Tue Jul 28 10:59:07 1998 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300.h: Add "no_match_operands" field for instructions.
+ (MN10300_MAX_OPERANDS): Define.
+
+Fri Jul 24 11:44:24 1998 Doug Evans
+
+ * cgen.h (cgen_macro_insn_count): Declare.
+
+Tue Jul 21 13:12:13 1998 Doug Evans
+
+ * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Define.
+ (cgen_insert_fn,cgen_extract_fn): New arg `pc'.
+ (get_operand,put_operand): Replaced with get_{int,vma}_operand,
+ set_{int,vma}_operand.
+
+Fri Jun 26 11:09:06 1998 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300.h: Add "machine" field for instructions.
+ (MN103, AM30): Define machine types.
+
+Fri Jun 19 16:09:09 1998 Alan Modra
+
+ * i386.h: Use FP, not sl_Suf, for fxsave and fxrstor.
+
+1998-06-18 Ulrich Drepper
+
+ * i386.h: Add support for fxsave, fxrstor, sysenter and sysexit.
+
+Sat Jun 13 11:31:35 1998 Alan Modra
+
+ * i386.h (i386_optab): Add general form of aad and aam. Add ud2a
+ and ud2b.
+ (i386_regtab): Allow cr0..7, db0..7, dr0..7, tr0..7, not just
+ those that happen to be implemented on pentiums.
+
+Tue Jun 9 12:16:01 1998 Alan Modra