URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
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- This comparison shows the changes necessary to convert path
/openrisc/tags/gnu-src/gdb-6.8/pre-binutils-2.20.1-sync/sim/testsuite/sim/arm/iwmmxt
- from Rev 157 to Rev 223
- ↔ Reverse comparison
Rev 157 → Rev 223
/wshufh.cgs
0,0 → 1,35
# Intel(r) Wireless MMX(tm) technology testcase for WSHUFH |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wshufh |
wshufh: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wshufh wr1, wr0, #0x1b |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0xdef09abc |
test_h_gr r3, 0x56781234 |
|
pass |
/wpack.cgs
0,0 → 1,173
# Intel(r) Wireless MMX(tm) technology testcase for WPACK |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wpack |
wpack: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Halfword, Unsigned Saturation, Packing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wpackhus wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x0000ffff |
test_h_gr r5, 0x0000ffff |
|
# Test Halfword, Signed Saturation, Packing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wpackhss wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x80807f7f |
test_h_gr r5, 0x00007f7f |
|
# Test Word, Unsigned Saturation, Packing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wpackwus wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x0000ffff |
test_h_gr r5, 0x0000ffff |
|
# Test Word, Signed Saturation, Packing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wpackwss wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x80007fff |
test_h_gr r5, 0x00007fff |
|
# Test Double Word, Unsigned Saturation, Packing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wpackdus wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x00000000 |
test_h_gr r5, 0x11111111 |
|
# Test Double Word, Signed Saturation, Packing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wpackdss wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x80000000 |
test_h_gr r5, 0x11111111 |
|
pass |
/wzero.cgs
0,0 → 1,29
# Intel(r) Wireless MMX(tm) technology testcase for WZERO |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wzero |
wzero: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
|
tmcrr wr0, r0, r1 |
|
wzero wr0 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x00000000 |
test_h_gr r1, 0x00000000 |
|
pass |
/wor.cgs
0,0 → 1,41
# Intel(r) Wireless MMX(tm) technology testcase for WOR |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wor |
wor: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wor wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x13355779 |
test_h_gr r5, 0x9abcdef0 |
|
pass |
/wandn.cgs
0,0 → 1,41
# Intel(r) Wireless MMX(tm) technology testcase for WANDN |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wandn |
wandn: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wandn wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x02244668 |
test_h_gr r5, 0x9abcdef0 |
|
pass |
/wmin.cgs
0,0 → 1,173
# Intel(r) Wireless MMX(tm) technology testcase for WMIN |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wmin |
wmin: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned Byte Minimum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wminub wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x11111111 |
test_h_gr r5, 0x11111100 |
|
# Test Signed Byte Minimum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wminsb wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x11111111 |
test_h_gr r5, 0x9abcde00 |
|
# Test Unsigned Halfword Minimum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wminuh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x11111111 |
test_h_gr r5, 0x11111111 |
|
# Test Signed Halfword Minimum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wminsh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x11111111 |
test_h_gr r5, 0x9abcde00 |
|
# Test Unsigned Word Minimum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wminuw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x11111111 |
test_h_gr r5, 0x11111111 |
|
# Test Signed Word Minimum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wminsw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x11111111 |
test_h_gr r5, 0x9abcde00 |
|
pass |
/tmiaxy.cgs
0,0 → 1,89
# Intel(r) Wireless MMX(tm) technology testcase for TMIAxy |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global tmiaXY |
tmiaXY: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Bottom Bottom Multilply Accumulate |
|
mvi_h_gr r0, 0x11223344 |
mvi_h_gr r1, 0x55667788 |
mvi_h_gr r2, 0x12345678 |
mvi_h_gr r3, 0x9abcdef0 |
|
tmcrr wr0, r0, r1 |
|
tmiaBB wr0, r2, r3 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x05f753c4 |
test_h_gr r1, 0x55667788 |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
# Test Bottom Top Multilply Accumulate |
|
mvi_h_gr r0, 0x11223344 |
mvi_h_gr r1, 0x55667788 |
mvi_h_gr r2, 0x12345678 |
mvi_h_gr r3, 0x9abcdef0 |
|
tmcrr wr0, r0, r1 |
|
tmiaBT wr0, r2, r3 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0xeeede364 |
test_h_gr r1, 0x55667787 |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
# Test Top Bottom Multilply Accumulate |
|
mvi_h_gr r0, 0x11223344 |
mvi_h_gr r1, 0x55667788 |
mvi_h_gr r2, 0x12345678 |
mvi_h_gr r3, 0x9abcdef0 |
|
tmcrr wr0, r0, r1 |
|
tmiaTB wr0, r2, r3 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x0ec85c04 |
test_h_gr r1, 0x55667788 |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
# Test Top Top Multilply Accumulate |
|
mvi_h_gr r0, 0x11223344 |
mvi_h_gr r1, 0x55667788 |
mvi_h_gr r2, 0x12345678 |
mvi_h_gr r3, 0x9abcdef0 |
|
tmcrr wr0, r0, r1 |
|
tmiaTT wr0, r2, r3 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x09eed974 |
test_h_gr r1, 0x55667788 |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
pass |
/wmax.cgs
0,0 → 1,173
# Intel(r) Wireless MMX(tm) technology testcase for WMAX |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wmax |
wmax: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned Byte Maximum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmaxub wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x12345678 |
test_h_gr r5, 0x9abcde11 |
|
# Test Signed Byte Maximum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmaxsb wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x12345678 |
test_h_gr r5, 0x11111111 |
|
# Test Unsigned Halfword Maximum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmaxuh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x12345678 |
test_h_gr r5, 0x9abcde00 |
|
# Test Signed Halfword Maximum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmaxsh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x12345678 |
test_h_gr r5, 0x11111111 |
|
# Test Unsigned Word Maximum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmaxuw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x12345678 |
test_h_gr r5, 0x9abcde00 |
|
# Test Signed Word Maximum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmaxsw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x12345678 |
test_h_gr r5, 0x11111111 |
|
pass |
/tbcst.cgs
0,0 → 1,65
# Intel(r) Wireless MMX(tm) technology testcase for TBCST |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global tbcst |
tbcst: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Byte Wide Broadcast |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
tbcstb wr0, r2 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0xffffffff |
test_h_gr r1, 0xffffffff |
test_h_gr r2, 0x111111ff |
|
# Test Half Word Wide Broadcast |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
tbcsth wr0, r2 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x11ff11ff |
test_h_gr r1, 0x11ff11ff |
test_h_gr r2, 0x111111ff |
|
# Test Word Wide Broadcast |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
tbcstw wr0, r2 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x111111ff |
test_h_gr r1, 0x111111ff |
test_h_gr r2, 0x111111ff |
|
pass |
/wadd.cgs
0,0 → 1,251
# Intel(r) Wireless MMX(tm) technology testcase for WADD |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wadd |
wadd: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test UnSaturated Byte Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waddb wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456789 |
test_h_gr r5, 0xabcdef11 |
|
# Test Unsigned Saturated Byte Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waddbus wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456789 |
test_h_gr r5, 0xabcdef11 |
|
# Test Signed Saturated Byte Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waddbss wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x2345677f |
test_h_gr r5, 0xabcdef11 |
|
# Test UnSaturated Halfword Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waddh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456789 |
test_h_gr r5, 0xabcdef11 |
|
# Test Unsigned Saturated Halfword Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waddhus wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456789 |
test_h_gr r5, 0xabcdef11 |
|
# Test Signed Saturated Halfword Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waddhss wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456789 |
test_h_gr r5, 0xabcdef11 |
|
# Test UnSaturated Word Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waddw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456789 |
test_h_gr r5, 0xabcdef11 |
|
# Test Unsigned Saturated Word Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waddwus wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456789 |
test_h_gr r5, 0xabcdef11 |
|
# Test Signed Saturated Word Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waddwss wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456789 |
test_h_gr r5, 0xabcdef11 |
|
pass |
/wsub.cgs
0,0 → 1,251
# Intel(r) Wireless MMX(tm) technology testcase for WSUB |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wsub |
wsub: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsaturated Byte subtraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsubb wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x89abcdef |
|
# Test Unsigned saturated Byte subtraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsubbus wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x89abcd00 |
|
# Test Signed saturated Byte subtraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsubbss wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x89abcdef |
|
# Test Unsaturated Halfword subtraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsubh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x89abccef |
|
# Test Unsigned saturated Halfword subtraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsubhus wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x89abccef |
|
# Test Signed saturated Halfword subtraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsubhss wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x89abccef |
|
# Test Unsaturated Word subtraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsubw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x89abccef |
|
# Test Unsigned saturated Word subtraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsubwus wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x89abccef |
|
# Test Signed saturated Word subtraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsubwss wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x89abccef |
|
pass |
/wmul.cgs
0,0 → 1,121
# Intel(r) Wireless MMX(tm) technology testcase for WMUL |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wmul |
wmul: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned, Most Significant Multiply |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmulum wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x013605c3 |
test_h_gr r5, 0x14a11db9 |
|
# Test Unsigned, Least Significant Multiply |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmulul wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0xa974b5f8 |
test_h_gr r5, 0x84f87be0 |
|
# Test Signed, Most Significant Multiply |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmulsm wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x013605c3 |
test_h_gr r5, 0xf27ffb97 |
|
# Test Signed, Least Significant Multiply |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmulsl wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0xa974b5f8 |
test_h_gr r5, 0x84f87be0 |
|
pass |
/wunpckeh.cgs
0,0 → 1,137
# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKEH |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wunpckeh |
wunpckeh: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned Byte Unpacking |
|
mvi_h_gr r0, 0x12345687 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckehub wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345687 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x00de00f0 |
test_h_gr r3, 0x009a00bc |
|
# Test Signed Byte Unpacking |
|
mvi_h_gr r0, 0x12345687 |
mvi_h_gr r1, 0x7abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckehsb wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345687 |
test_h_gr r1, 0x7abcdef0 |
test_h_gr r2, 0xffdefff0 |
test_h_gr r3, 0x007affbc |
|
# Test Unsigned Halfword Unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckehuh wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x0000def0 |
test_h_gr r3, 0x00009abc |
|
# Test Signed Halfword Unpacking |
|
mvi_h_gr r0, 0x12348678 |
mvi_h_gr r1, 0x7abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckehsh wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12348678 |
test_h_gr r1, 0x7abcdef0 |
test_h_gr r2, 0xffffdef0 |
test_h_gr r3, 0x00007abc |
|
# Test Unsigned Word Unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckehuw wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x9abcdef0 |
test_h_gr r3, 0x00000000 |
|
# Test Signed Word Unpacking |
|
mvi_h_gr r0, 0x82345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckehsw wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x82345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x9abcdef0 |
test_h_gr r3, 0xffffffff |
|
pass |
/wmov.cgs
0,0 → 1,35
# Intel(r) Wireless MMX(tm) technology testcase for WMOV |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wmov |
wmov: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wmov wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
pass |
/wunpckel.cgs
0,0 → 1,137
# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKEL |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wunpckel |
wunpckel: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned Byte Unpacking |
|
mvi_h_gr r0, 0x12345687 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckelub wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345687 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x00560087 |
test_h_gr r3, 0x00120034 |
|
# Test Signed Byte Unpacking |
|
mvi_h_gr r0, 0x12345687 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckelsb wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345687 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x0056ff87 |
test_h_gr r3, 0x00120034 |
|
# Test Unsigned Halfword Unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckeluh wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x00005678 |
test_h_gr r3, 0x00001234 |
|
# Test Signed Halfword Unpacking |
|
mvi_h_gr r0, 0x12348678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckelsh wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12348678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0xffff8678 |
test_h_gr r3, 0x00001234 |
|
# Test Unsigned Word Unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckeluw wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x00000000 |
|
# Test Signed Word Unpacking |
|
mvi_h_gr r0, 0x82345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckelsw wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x82345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x82345678 |
test_h_gr r3, 0xffffffff |
|
pass |
/wunpckih.cgs
0,0 → 1,95
# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKIH |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wunpckih |
wunpckih: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Byte unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wunpckihb wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x00de00f0 |
test_h_gr r5, 0x009a00bc |
|
# Test Halfword unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wunpckihh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x0000def0 |
test_h_gr r5, 0x00009abc |
|
# Test Word unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wunpckihw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x9abcdef0 |
test_h_gr r5, 0x00000000 |
|
pass |
/wand.cgs
0,0 → 1,41
# Intel(r) Wireless MMX(tm) technology testcase for WAND |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wand |
wand: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wand wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x10101010 |
test_h_gr r5, 0x00000000 |
|
pass |
/wror.cgs
0,0 → 1,167
# Intel(r) Wireless MMX(tm) technology testcase for WROR |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wror |
wror: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Halfword wide rotate right by register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wrorh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x091a2b3c |
test_h_gr r5, 0x4d5e6f78 |
|
# Test Halfword wide rotate right by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr0, r2 |
tmcrr wr1, r2, r3 |
|
wrorhg wr1, wr0, wcgr0 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr0 |
tmrrc r3, r4, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x091a2b3c |
test_h_gr r4, 0x4d5e6f78 |
|
# Test Word wide rotate right by register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wrorw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x2b3c091a |
test_h_gr r5, 0x6f784d5e |
|
# Test Word wide rotate right by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr0, r2 |
tmcrr wr1, r2, r3 |
|
wrorwg wr1, wr0, wcgr0 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr0 |
tmrrc r3, r4, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x2b3c091a |
test_h_gr r4, 0x6f784d5e |
|
# Test Double Word wide rotate right by register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wrord wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x6f78091a |
test_h_gr r5, 0x2b3c4d5e |
|
# Test Double Word wide rotate right by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr0, r2 |
tmcrr wr1, r2, r3 |
|
wrordg wr1, wr0, wcgr0 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr0 |
tmrrc r3, r4, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x6f78091a |
test_h_gr r4, 0x2b3c4d5e |
|
pass |
/tmia.cgs
0,0 → 1,35
# Intel(r) Wireless MMX(tm) technology testcase for TMIA |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global tmia |
tmia: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Multilply Accumulate |
|
mvi_h_gr r0, 0x11223344 |
mvi_h_gr r1, 0x55667788 |
mvi_h_gr r2, 0x12345678 |
mvi_h_gr r3, 0x9abcdef0 |
|
tmcrr wr0, r0, r1 |
|
tmia wr0, r2, r3 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x354f53c4 |
test_h_gr r1, 0x4e330b5e |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
pass |
/wunpckil.cgs
0,0 → 1,95
# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKIL |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wunpckil |
wunpckil: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Byte unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wunpckilb wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x11561178 |
test_h_gr r5, 0x11121134 |
|
# Test Halfword unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wunpckilh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x11115678 |
test_h_gr r5, 0x11111234 |
|
# Test Word unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wunpckilw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x12345678 |
test_h_gr r5, 0x11111111 |
|
pass |
/wxor.cgs
0,0 → 1,41
# Intel(r) Wireless MMX(tm) technology testcase for WXOR |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wxor |
wxor: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wxor wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x03254769 |
test_h_gr r5, 0x9abcdef0 |
|
pass |
/tmovmsk.cgs
0,0 → 1,65
# Intel(r) Wireless MMX(tm) technology testcase for TMOVMSK |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global tmovmsk |
tmovmsk: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Byte Wide Mask Transfer |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
|
tmcrr wr0, r0, r1 |
|
tmovmskb r2, wr0 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x000000f0 |
|
# Test Half Word Wide Mask Transfer |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
|
tmcrr wr0, r0, r1 |
|
tmovmskh r2, wr0 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x0000000c |
|
# Test Word Wide Mask Transfer |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
|
tmcrr wr0, r0, r1 |
|
tmovmskw r2, wr0 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x00000002 |
|
pass |
/iwmmxt.exp
0,0 → 1,28
# Intel(r) Wireless MMX(tm) technology simulator testsuite. |
|
if { [istarget xscale*-*-*] } { |
# load support procs (none yet) |
# load_lib cgen.exp |
|
# all machines |
set all_machs "xscale" |
|
if [is_remote host] { |
remote_download host $srcdir/$subdir/testutils.inc |
} |
|
# The .cgs suffix is for "cgen .s". |
foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { |
# If we're only testing specific files and this isn't one of them, |
# skip it. |
if ![runtest_file_p $runtests $src] { |
continue |
} |
|
run_sim_test $src $all_machs |
} |
|
if [is_remote host] { |
remote_file host delete testutils.inc |
} |
} |
/wsra.cgs
0,0 → 1,167
# Intel(r) Wireless MMX(tm) technology testcase for WSRA |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wsra |
wsra: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Halfword Arithmetic Shift Right |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsrah wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01230567 |
test_h_gr r5, 0xf9abfdef |
|
# Test Halfword Arithmetic Shift Right by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr1, r2 |
tmcrr wr1, r3, r4 |
|
wsrahg wr1, wr0, wcgr1 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr1 |
tmrrc r3, r4, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x01230567 |
test_h_gr r4, 0xf9abfdef |
|
# Test Word Arithmetic Shift Right |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsraw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0xf9abcdef |
|
# Test Word Arithmetic Shift Right by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr2, r2 |
tmcrr wr1, r3, r4 |
|
wsrawg wr1, wr0, wcgr2 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr2 |
tmrrc r3, r4, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x01234567 |
test_h_gr r4, 0xf9abcdef |
|
# Test Double Word Arithmetic Shift Right |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdefc |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsrad wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdefc |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0xc1234567 |
test_h_gr r5, 0xf9abcdef |
|
# Test Double Word Arithmetic Shift Right by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdefc |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr3, r2 |
tmcrr wr1, r3, r4 |
|
wsradg wr1, wr0, wcgr3 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr3 |
tmrrc r3, r4, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdefc |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0xc1234567 |
test_h_gr r4, 0xf9abcdef |
|
pass |
/wacc.cgs
0,0 → 1,77
# Intel(r) Wireless MMX(tm) technology testcase for WACC |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wacc |
wacc: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned Byte Wide Accumulation |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
waccb wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x00000438 |
test_h_gr r3, 0x00000000 |
|
# Test Unsigned Half Word Wide Accumulation |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wacch wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x0001e258 |
test_h_gr r3, 0x00000000 |
|
# Test Unsigned Word Wide Accumulation |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
waccw wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0xacf13568 |
test_h_gr r3, 0x00000000 |
|
pass |
/wsll.cgs
0,0 → 1,167
# Intel(r) Wireless MMX(tm) technology testcase for WSLL |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wsll |
wsll: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Halfword Logical Shift Left |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsllh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23406780 |
test_h_gr r5, 0xabc0ef00 |
|
# Test Halfword Aritc Shift Left by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr1, r2 |
tmcrr wr1, r3, r4 |
|
wsllhg wr1, wr0, wcgr1 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr1 |
tmrrc r3, r4, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x23406780 |
test_h_gr r4, 0xabc0ef00 |
|
# Test Word Logical Shift Left |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsllw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456780 |
test_h_gr r5, 0xabcdef00 |
|
# Test Word Logical Shift Left by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr2, r2 |
tmcrr wr1, r3, r4 |
|
wsllwg wr1, wr0, wcgr2 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr2 |
tmrrc r3, r4, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x23456780 |
test_h_gr r4, 0xabcdef00 |
|
# Test Double Word Logical Shift Left |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdefc |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wslld wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdefc |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456780 |
test_h_gr r5, 0xabcdefc1 |
|
# Test Double Word Logical Shift Left by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdefc |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr3, r2 |
tmcrr wr1, r3, r4 |
|
wslldg wr1, wr0, wcgr3 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr3 |
tmrrc r3, r4, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdefc |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x23456780 |
test_h_gr r4, 0xabcdefc1 |
|
pass |
/tmiaph.cgs
0,0 → 1,35
# Intel(r) Wireless MMX(tm) technology testcase for TMIAPH |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global tmiaph |
tmiaph: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Multilply Accumulate |
|
mvi_h_gr r0, 0x11223344 |
mvi_h_gr r1, 0x55667788 |
mvi_h_gr r2, 0x12345678 |
mvi_h_gr r3, 0x9abcdef0 |
|
tmcrr wr0, r0, r1 |
|
tmiaph wr0, r2, r3 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0xfec3f9f4 |
test_h_gr r1, 0x55667787 |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
pass |
/textrm.cgs
0,0 → 1,113
# Intel(r) Wireless MMX(tm) technology testcase for TEXTRM |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global textrm |
textrm: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned Byte Wide Extraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
textrmub r2, wr0, #3 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x00000012 |
|
# Test Signed Byte Wide Extraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
textrmsb r2, wr0, #4 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0xfffffff0 |
|
# Test Unsigned Half Word Wide Extraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
textrmuh r2, wr0, #3 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x00009abc |
|
# Test Signed Half Word Wide Extraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
textrmsh r2, wr0, #1 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x00001234 |
|
# Test Unsigned Word Wide Extraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
textrmuw r2, wr0, #0 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x12345678 |
|
# Test Signed Word Wide Extraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
textrmsw r2, wr0, #1 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x9abcdef0 |
|
pass |
/wavg2.cgs
0,0 → 1,121
# Intel(r) Wireless MMX(tm) technology testcase for WAVG2 |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wavg2 |
wavg2: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Byte Wide Averaging |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wavg2b wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x11223344 |
test_h_gr r5, 0x5e6f8089 |
|
# Test Byte Wide Averaging with Rounding |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wavg2br wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x12233445 |
test_h_gr r5, 0x5e6f8089 |
|
# Test Half Word Wide Averaging |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wavg2h wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x11a233c4 |
test_h_gr r5, 0x5e6f8089 |
|
# Test Half Word Wide Averaging with Rounding |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wavg2hr wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x11a333c5 |
test_h_gr r5, 0x5e6f8089 |
|
pass |
/wmac.cgs
0,0 → 1,121
# Intel(r) Wireless MMX(tm) technology testcase for WMAC |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wmac |
wmac: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned, Multiply Accumulate, Non-zeroing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0x33333333 |
mvi_h_gr r5, 0x44444444 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmacu wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x6c889377 |
test_h_gr r5, 0x44444444 |
|
# Test Unsigned, Multiply Accumulate, Zeroing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0x33333333 |
mvi_h_gr r5, 0x44444444 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmacuz wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x39556044 |
test_h_gr r5, 0x00000000 |
|
# Test Signed, Multiply Accumulate, Non-zeroing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0x33333333 |
mvi_h_gr r5, 0x44444444 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmacs wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x28449377 |
test_h_gr r5, 0x44444444 |
|
# Test Signed, Multiply Accumulate, Zeroing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0x33333333 |
mvi_h_gr r5, 0x44444444 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmacsz wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0xf5116044 |
test_h_gr r5, 0xffffffff |
|
pass |
/wsrl.cgs
0,0 → 1,167
# Intel(r) Wireless MMX(tm) technology testcase for WSRL |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wsrl |
wsrl: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Halfword Logical Shift Right |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsrlh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01230567 |
test_h_gr r5, 0x09ab0def |
|
# Test Halfword Logical Shift Right by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr1, r2 |
tmcrr wr1, r3, r4 |
|
wsrlhg wr1, wr0, wcgr1 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr1 |
tmrrc r3, r4, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x01230567 |
test_h_gr r4, 0x09ab0def |
|
# Test Word Logical Shift Right |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsrlw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x09abcdef |
|
# Test Word Logical Shift Right by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr2, r2 |
tmcrr wr1, r3, r4 |
|
wsrlwg wr1, wr0, wcgr2 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr2 |
tmrrc r3, r4, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x01234567 |
test_h_gr r4, 0x09abcdef |
|
# Test Double Word Logical Shift Right |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdefc |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsrld wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdefc |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0xc1234567 |
test_h_gr r5, 0x09abcdef |
|
# Test Double Word Logical Shift Right by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdefc |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr3, r2 |
tmcrr wr1, r3, r4 |
|
wsrldg wr1, wr0, wcgr3 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr3 |
tmrrc r3, r4, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdefc |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0xc1234567 |
test_h_gr r4, 0x09abcdef |
|
pass |
/waligni.cgs
0,0 → 1,43
# Intel(r) Wireless MMX(tm) technology testcase for WALIGNI |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global waligni |
waligni: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test 2 byte align |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waligni wr2, wr0, wr1, #2 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0xdef01234 |
test_h_gr r5, 0x11119abc |
|
pass |
/wmadd.cgs
0,0 → 1,69
# Intel(r) Wireless MMX(tm) technology testcase for WMADD |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wmadd |
wmadd: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned, Multiply Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmaddu wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x06fa5f6c |
test_h_gr r5, 0x325b00d8 |
|
# Test Signed, Multiply Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmadds wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x06fa5f6c |
test_h_gr r5, 0xee1700d8 |
|
pass |
/wcmpeq.cgs
0,0 → 1,95
# Intel(r) Wireless MMX(tm) technology testcase for WCMPEQ |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wcmpeq |
wcmpeq: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Byte Wide Compare Equal To |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x9abcde00 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wcmpeqb wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x9abcde00 |
test_h_gr r4, 0x00000000 |
test_h_gr r5, 0xffffffff |
|
# Test Half Word Wide Compare Equal To |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x9abcde00 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wcmpeqh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x9abcde00 |
test_h_gr r4, 0x00000000 |
test_h_gr r5, 0xffffffff |
|
# Test Word Wide Compare Equal To |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x9abcde00 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wcmpeqw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x9abcde00 |
test_h_gr r4, 0x00000000 |
test_h_gr r5, 0xffffffff |
|
pass |
/testutils.inc
0,0 → 1,118
# r0-r3 are used as tmps, consider them call clobbered by these macros. |
# This uses the angel rom monitor calls. |
# ??? How do we use the \@ facility of .macros ??? |
# @ is the comment char! |
|
.macro mvi_h_gr reg, val |
ldr \reg,[pc] |
b . + 8 |
.word \val |
.endm |
|
.macro mvaddr_h_gr reg, addr |
ldr \reg,[pc] |
b . + 8 |
.word \addr |
.endm |
|
.macro start |
.data |
failmsg: |
.asciz "fail\n" |
passmsg: |
.asciz "pass\n" |
.text |
|
do_pass: |
ldr r1, passmsg_addr |
mov r0, #4 |
swi #0x123456 |
exit 0 |
passmsg_addr: |
.word passmsg |
|
do_fail: |
ldr r1, failmsg_addr |
mov r0, #4 |
swi #0x123456 |
exit 1 |
failmsg_addr: |
.word failmsg |
|
.global _start |
_start: |
.endm |
|
# *** Other macros know pass/fail are 4 bytes in size! Yuck. |
|
.macro pass |
b do_pass |
.endm |
|
.macro fail |
b do_fail |
.endm |
|
.macro exit rc |
# ??? This works with the ARMulator but maybe not others. |
#mov r0, #\rc |
#swi #1 |
# This seems to be portable (though it ignores rc). |
mov r0,#0x18 |
mvi_h_gr r1, 0x20026 |
swi #0x123456 |
# If that returns, punt with a sigill. |
stc 0,cr0,[r0] |
.endm |
|
# Other macros know this only clobbers r0. |
# WARNING: It also clobbers the condition codes (FIXME). |
.macro test_h_gr reg, val |
mvaddr_h_gr r0, \val |
cmp \reg, r0 |
beq . + 8 |
fail |
.endm |
|
.macro mvi_h_cnvz c, n, v, z |
mov r0, #0 |
.if \c |
orr r0, r0, #0x20000000 |
.endif |
.if \n |
orr r0, r0, #0x80000000 |
.endif |
.if \v |
orr r0, r0, #0x10000000 |
.endif |
.if \z |
orr r0, r0, #0x40000000 |
.endif |
mrs r1, cpsr |
bic r1, r1, #0xf0000000 |
orr r1, r1, r0 |
msr cpsr, r1 |
# ??? nops needed |
.endm |
|
# ??? Preserve condition codes? |
.macro test_h_cnvz c, n, v, z |
mov r0, #0 |
.if \c |
orr r0, r0, #0x20000000 |
.endif |
.if \n |
orr r0, r0, #0x80000000 |
.endif |
.if \v |
orr r0, r0, #0x10000000 |
.endif |
.if \z |
orr r0, r0, #0x40000000 |
.endif |
mrs r1, cpsr |
and r1, r1, #0xf0000000 |
cmp r0, r1 |
beq . + 8 |
fail |
.endm |
/wsad.cgs
0,0 → 1,121
# Intel(r) Wireless MMX(tm) technology testcase for WSAD |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wsad |
wsad: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Byte wide absolute accumulation |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0x22222222 |
mvi_h_gr r5, 0x22222222 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsadb wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x2222258e |
test_h_gr r5, 0x00000000 |
|
# Test Byte wide absolute accumulation with zeroing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0x22222222 |
mvi_h_gr r5, 0x22222222 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsadbz wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x0000036c |
test_h_gr r5, 0x00000000 |
|
# Test Halfword wide absolute accumulation |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0x22222222 |
mvi_h_gr r5, 0x22222222 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsadh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x22239e14 |
test_h_gr r5, 0x00000000 |
|
# Test Halfword wide absolute accumulation with zeroing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0x22222222 |
mvi_h_gr r5, 0x22222222 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsadhz wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x00017bf2 |
test_h_gr r5, 0x00000000 |
|
pass |
/tinsr.cgs
0,0 → 1,65
# Intel(r) Wireless MMX(tm) technology testcase for TINSR |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global tinsr |
tinsr: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Byte Wide Insertion |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
tinsrb wr0, r2, #3 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0xff345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x111111ff |
|
# Test Half Word Wide Insertion |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
tinsrh wr0, r2, #2 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abc11ff |
test_h_gr r2, 0x111111ff |
|
# Test Word Wide Insertion |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
tinsrw wr0, r2, #1 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x111111ff |
test_h_gr r2, 0x111111ff |
|
pass |
/wcmpgt.cgs
0,0 → 1,173
# Intel(r) Wireless MMX(tm) technology testcase for WCMPGT |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wcmpgt |
wcmpgt: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned Byte Wide Compare Greater Than |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wcmpgtub wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0xffffffff |
test_h_gr r5, 0xffffff00 |
|
# Test Signed Byte Wide Compare Greater Than |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wcmpgtsb wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0xffffffff |
test_h_gr r5, 0x00000000 |
|
# Test Unsigned Half Word Wide Compare Greater Than |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wcmpgtuh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0xffffffff |
test_h_gr r5, 0xffffffff |
|
# Test Signed Half Word Wide Compare Greater Than |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wcmpgtsh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0xffffffff |
test_h_gr r5, 0x00000000 |
|
# Test Unsigned Word Wide Compare Greater Than |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wcmpgtuw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0xffffffff |
test_h_gr r5, 0xffffffff |
|
# Test Signed Word Wide Compare Greater Than |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wcmpgtsw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0xffffffff |
test_h_gr r5, 0x00000000 |
|
pass |
/walignr.cgs
0,0 → 1,137
# Intel(r) Wireless MMX(tm) technology testcase for WALIGNR |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global walignr |
walignr: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test 0 byte align |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
mvi_h_gr r6, 3 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
tmcr wcgr0, r6 |
|
walignr0 wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
tmrc r6, wcgr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0xbcdef012 |
test_h_gr r5, 0x1111119a |
test_h_gr r6, 3 |
|
# Test 1 byte align |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
mvi_h_gr r6, 4 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
tmcr wcgr1, r6 |
|
walignr1 wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
tmrc r6, wcgr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x9abcdef0 |
test_h_gr r5, 0x11111111 |
test_h_gr r6, 4 |
|
# Test 2 byte align |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
mvi_h_gr r6, 2 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
tmcr wcgr2, r6 |
|
walignr2 wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
tmrc r6, wcgr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0xdef01234 |
test_h_gr r5, 0x11119abc |
test_h_gr r6, 2 |
|
# Test 3 byte align |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
mvi_h_gr r6, 5 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
tmcr wcgr3, r6 |
|
walignr3 wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
tmrc r6, wcgr3 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x119abcde |
test_h_gr r5, 0x00111111 |
test_h_gr r6, 5 |
|
pass |