URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/tags/gnu-src/gdb-6.8/pre-binutils-2.20.1-sync/sim/testsuite/sim/arm
- from Rev 157 to Rev 223
- ↔ Reverse comparison
Rev 157 → Rev 223
/thumb/sbc.cgs
0,0 → 1,12
# arm testcase for sbc $rd,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global alu_sbc |
alu_sbc: |
sbc r0,r0 |
|
pass |
/thumb/tst.cgs
0,0 → 1,12
# arm testcase for tst $rd,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global alu_tst |
alu_tst: |
tst r0,r0 |
|
pass |
/thumb/bpl.cgs
0,0 → 1,12
# arm testcase for bpl $soffset8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global bpl |
bpl: |
bpl footext |
|
pass |
/thumb/bls.cgs
0,0 → 1,12
# arm testcase for bls $soffset8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global bls |
bls: |
bls footext |
|
pass |
/thumb/lda-sp.cgs
0,0 → 1,12
# arm testcase for add ${bit10-rd},sp,$word8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global lda_sp |
lda_sp: |
add r0,sp,0 |
|
pass |
/thumb/blt.cgs
0,0 → 1,12
# arm testcase for blt $soffset8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global blt |
blt: |
blt footext |
|
pass |
/thumb/ldr-pc.cgs
0,0 → 1,12
# arm testcase for ldr ${bit10-rd},[pc,#$word8] |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr_pc |
ldr_pc: |
ldr r0,[pc,#0] |
|
pass |
/thumb/ldr.cgs
0,0 → 1,12
# arm testcase for ldr $rd,[$rb,$ro] |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr |
ldr: |
ldr r0,[r0,r0] |
|
pass |
/thumb/str-imm.cgs
0,0 → 1,12
# arm testcase for str $rd,[$rb,#${offset5-7}] |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global str_imm |
str_imm: |
str r0,[r0,#0] |
|
pass |
/thumb/allthumb.exp
0,0 → 1,21
# ARM simulator testsuite. |
|
if { [istarget arm*-*-*] |
|| [istarget thumb*-*-*] } { |
# load support procs (none yet) |
# load_lib cgen.exp |
|
# all machines |
set all_machs "arm7tdmi" |
|
# The .cgs suffix is for "cgen .s". |
foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { |
# If we're only testing specific files and this isn't one of them, |
# skip it. |
if ![runtest_file_p $runtests $src] { |
continue |
} |
|
run_sim_test $src $all_machs |
} |
} |
/thumb/strb-imm.cgs
0,0 → 1,12
# arm testcase for strb $rd,[$rb,#$offset5] |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strb_imm |
strb_imm: |
strb r0,[r0,#0] |
|
pass |
/thumb/cmp-hd-rs.cgs
0,0 → 1,12
# arm testcase for cmp $hd,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global cmp_hd_rs |
cmp_hd_rs: |
cmp r8,r0 |
|
pass |
/thumb/bic.cgs
0,0 → 1,12
# arm testcase for bic $rd,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global alu_bic |
alu_bic: |
bic r0,r0 |
|
pass |
/thumb/strh-imm.cgs
0,0 → 1,12
# arm testcase for strh $rd,[$rb,#${offset5-6}] |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strh_imm |
strh_imm: |
strh r0,[r0,#0] |
|
pass |
/thumb/lda-pc.cgs
0,0 → 1,12
# arm testcase for add ${bit10-rd},pc,$word8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global lda_pc |
lda_pc: |
add r0,pc,0 |
|
pass |
/thumb/mvn.cgs
0,0 → 1,12
# arm testcase for mvn $rd,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global alu_mvn |
alu_mvn: |
mvn r0,r0 |
|
pass |
/thumb/orr.cgs
0,0 → 1,12
# arm testcase for orr $rd,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global alu_orr |
alu_orr: |
orr r0,r0 |
|
pass |
/thumb/mov-hd-hs.cgs
0,0 → 1,12
# arm testcase for mov $hd,$hs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global mov_hd_hs |
mov_hd_hs: |
mov r8,r8 |
|
pass |
/thumb/subi.cgs
0,0 → 1,12
# arm testcase for sub $rd,$rs,#$offset3 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global subi |
subi: |
sub r0,r0,#0 |
|
pass |
/thumb/add-hd-rs.cgs
0,0 → 1,12
# arm testcase for add $hd,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global add_hd_rs |
add_hd_rs: |
add r8,r0 |
|
pass |
/thumb/ldr-sprel.cgs
0,0 → 1,12
# arm testcase for ldr ${bit10-rd},[sp,#$word8] |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr_sprel |
ldr_sprel: |
ldr r0,[sp,#0] |
|
pass |
/thumb/beq.cgs
0,0 → 1,12
# arm testcase for beq $soffset8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global beq |
beq: |
beq footext |
|
pass |
/thumb/bmi.cgs
0,0 → 1,12
# arm testcase for bmi $soffset8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global bmi |
bmi: |
bmi footext |
|
pass |
/thumb/neg.cgs
0,0 → 1,12
# arm testcase for neg $rd,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global alu_neg |
alu_neg: |
neg r0,r0 |
|
pass |
/thumb/mov-rd-hs.cgs
0,0 → 1,12
# arm testcase for mov $rd,$hs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global mov_rd_hs |
mov_rd_hs: |
mov r0,r8 |
|
pass |
/thumb/push.cgs
0,0 → 1,12
# arm testcase for push {$rlist} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global push |
push: |
push {0} |
|
pass |
/thumb/b.cgs
0,0 → 1,12
# arm testcase for b $offset11 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global b |
b: |
b footext |
|
pass |
/thumb/ldrb.cgs
0,0 → 1,12
# arm testcase for ldrb $rd,[$rb,$ro] |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrb |
ldrb: |
ldrb r0,[r0,r0] |
|
pass |
/thumb/eor.cgs
0,0 → 1,12
# arm testcase for eor $rd,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global alu_eor |
alu_eor: |
eor r0,r0 |
|
pass |
/thumb/asr.cgs
0,0 → 1,14
# arm testcase for asr $rd,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global alu_asr |
alu_asr: |
asr r0,r0 |
|
# FIXME: Also asr $rd,$rs,#$offset5 |
|
pass |
/thumb/ldmia.cgs
0,0 → 1,12
# arm testcase for ldmia $rb!,{$rlist} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldmia |
ldmia: |
ldmia r0!,{0} |
|
pass |
/thumb/adc.cgs
0,0 → 1,12
# arm testcase for adc $rd,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global alu_adc |
alu_adc: |
adc r0,r0 |
|
pass |
/thumb/add.cgs
0,0 → 1,12
# arm testcase for add $rd,$rs,$rn |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global add |
add: |
add r0,r0,r0 |
|
pass |
/thumb/addi8.cgs
0,0 → 1,12
# arm testcase for add ${bit10-rd},#$offset8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global addi8 |
addi8: |
add r0,#0 |
|
pass |
/thumb/ldrh.cgs
0,0 → 1,12
# arm testcase for ldrh $rd,[$rb,$ro] |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrh |
ldrh: |
ldrh r0,[r0,r0] |
|
pass |
/thumb/subi8.cgs
0,0 → 1,12
# arm testcase for sub ${bit10-rd},#$offset8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global subi8 |
subi8: |
sub r0,#0 |
|
pass |
/thumb/str-sprel.cgs
0,0 → 1,12
# arm testcase for str ${bit10-rd},[sp,#$word8] |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global str_sprel |
str_sprel: |
str r0,[sp,#0] |
|
pass |
/thumb/bx-rs.cgs
0,0 → 1,12
# arm testcase for bx $rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global bx_rs |
bx_rs: |
bx r0 |
|
pass |
/thumb/addi.cgs
0,0 → 1,12
# arm testcase for add $rd,$rs,#$offset3 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global addi |
addi: |
add r0,r0,#0 |
|
pass |
/thumb/ldr-imm.cgs
0,0 → 1,12
# arm testcase for ldr $rd,[$rb,#${offset5-7}] |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr_imm |
ldr_imm: |
ldr r0,[r0,#0] |
|
pass |
/thumb/mov.cgs
0,0 → 1,12
# arm testcase for mov ${bit10-rd},#$offset8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global mov |
mov: |
mov r0,#0 |
|
pass |
/thumb/swi.cgs
0,0 → 1,12
# arm testcase for swi $value8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global swi |
swi: |
swi 0 |
|
pass |
/thumb/bne.cgs
0,0 → 1,12
# arm testcase for bne $soffset8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global bne |
bne: |
bne footext |
|
pass |
/thumb/add-sp.cgs
0,0 → 1,12
# arm testcase for add sp,#$sword7 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global add_sp |
add_sp: |
add sp,#0 |
|
pass |
/thumb/bvc.cgs
0,0 → 1,12
# arm testcase for bvc $soffset8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global bvc |
bvc: |
bvc footext |
|
pass |
/thumb/stmia.cgs
0,0 → 1,12
# arm testcase for stmia $rb!,{$rlist} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global stmia |
stmia: |
stmia r0!,{0} |
|
pass |
/thumb/cmp-hd-hs.cgs
0,0 → 1,12
# arm testcase for cmp $hd,$hs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global cmp_hd_hs |
cmp_hd_hs: |
cmp r8,r8 |
|
pass |
/thumb/ldsb.cgs
0,0 → 1,12
# arm testcase for ldsb $rd,[$rb,$ro] |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldsb |
ldsb: |
ldsb r0,[r0,r0] |
|
pass |
/thumb/bcc.cgs
0,0 → 1,12
# arm testcase for bcc $soffset8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global bcc |
bcc: |
bcc footext |
|
pass |
/thumb/add-hd-hs.cgs
0,0 → 1,12
# arm testcase for add $hd,$hs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global add_hd_hs |
add_hd_hs: |
add r8,r8 |
|
pass |
/thumb/bvs.cgs
0,0 → 1,12
# arm testcase for bvs $soffset8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global bvs |
bvs: |
bvs footext |
|
pass |
/thumb/cmp-rd-hs.cgs
0,0 → 1,12
# arm testcase for cmp $rd,$hs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global cmp_rd_hs |
cmp_rd_hs: |
cmp r0,r8 |
|
pass |
/thumb/ldsh.cgs
0,0 → 1,12
# arm testcase for ldsh $rd,[$rb,$ro] |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldsh |
ldsh: |
ldsh r0,[r0,r0] |
|
pass |
/thumb/bl-hi.cgs
0,0 → 1,12
# arm testcase for bl-hi ${lbwl-hi} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global bl_hi |
bl_hi: |
bl-hi 0 |
|
pass |
/thumb/bge.cgs
0,0 → 1,12
# arm testcase for bge $soffset8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global bge |
bge: |
bge footext |
|
pass |
/thumb/pop-pc.cgs
0,0 → 1,12
# arm testcase for pop {${rlist-pc}} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global pop_pc |
pop_pc: |
pop {0} |
|
pass |
/thumb/add-rd-hs.cgs
0,0 → 1,12
# arm testcase for add $rd,$hs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global add_rd_hs |
add_rd_hs: |
add r0,r8 |
|
pass |
/thumb/ldrb-imm.cgs
0,0 → 1,12
# arm testcase for ldrb $rd,[$rb,#$offset5] |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrb_imm |
ldrb_imm: |
ldrb r0,[r0,#0] |
|
pass |
/thumb/bl-lo.cgs
0,0 → 1,12
# arm testcase for bl-lo ${lbwl-lo} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global bl_lo |
bl_lo: |
bl-lo 0 |
|
pass |
/thumb/bcs.cgs
0,0 → 1,12
# arm testcase for bcs $soffset8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global bcs |
bcs: |
bcs footext |
|
pass |
/thumb/str.cgs
0,0 → 1,12
# arm testcase for str $rd,[$rb,$ro] |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global str |
str: |
str r0,[r0,r0] |
|
pass |
/thumb/sub-sp.cgs
0,0 → 1,12
# arm testcase for add sp,#-$sword7 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global sub_sp |
sub_sp: |
add sp,#-0 |
|
pass |
/thumb/ldrh-imm.cgs
0,0 → 1,12
# arm testcase for ldrh $rd,[$rb,#${offset5-6}] |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrh_imm |
ldrh_imm: |
ldrh r0,[r0,#0] |
|
pass |
/thumb/strb.cgs
0,0 → 1,12
# arm testcase for strb $rd,[$rb,$ro] |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strb |
strb: |
strb r0,[r0,r0] |
|
pass |
/thumb/mov-hd-rs.cgs
0,0 → 1,12
# arm testcase for mov $hd,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global mov_hd_rs |
mov_hd_rs: |
mov r8,r0 |
|
pass |
/thumb/bgt.cgs
0,0 → 1,12
# arm testcase for bgt $soffset8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global bgt |
bgt: |
bgt footext |
|
pass |
/thumb/cmn.cgs
0,0 → 1,12
# arm testcase for cmn $rd,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global alu_cmn |
alu_cmn: |
cmn r0,r0 |
|
pass |
/thumb/cmp.cgs
0,0 → 1,14
# arm testcase for cmp ${bit10-rd},#$offset8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global cmp |
cmp: |
cmp r0,#0 |
|
# FIXME: Also: cmp $rd,$rs |
|
pass |
/thumb/strh.cgs
0,0 → 1,12
# arm testcase for strh $rd,[$rb,$ro] |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strh |
strh: |
strh r0,[r0,r0] |
|
pass |
/thumb/bx-hs.cgs
0,0 → 1,12
# arm testcase for bx $hs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global bx_hs |
bx_hs: |
bx r8 |
|
pass |
/thumb/sub.cgs
0,0 → 1,12
# arm testcase for sub $rd,$rs,$rn |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global sub |
sub: |
sub r0,r0,r0 |
|
pass |
/thumb/push-lr.cgs
0,0 → 1,12
# arm testcase for push {${rlist-lr}} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global push_lr |
push_lr: |
push {0} |
|
pass |
/thumb/lsl.cgs
0,0 → 1,14
# arm testcase for lsl $rd,$rs,#$offset5 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global lsl |
lsl: |
lsl r0,r0,#0 |
|
# FIXME: Also lsl $rd,$rs |
|
pass |
/thumb/mul.cgs
0,0 → 1,12
# arm testcase for mul $rd,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global alu_mul |
alu_mul: |
mul r0,r0 |
|
pass |
/thumb/testutils.inc
0,0 → 1,91
# FIXME: wip, copied from ../testutils.inc |
# r0-r3 are used as tmps, consider them call clobbered by these macros. |
# This uses the angel rom monitor calls. |
# ??? How do we use the \@ facility of .macros ??? |
# @ is the comment char! |
|
.macro a_mvi_h_gr reg, val |
ldr \reg,[pc] |
b . + 8 |
.word \val |
.endm |
|
.macro mvaddr_h_gr reg, addr |
ldr \reg,[pc] |
b . + 8 |
.word \val |
.endm |
|
.macro start |
.data |
failmsg: |
.asciz "fail\n" |
passmsg: |
.asciz "pass\n" |
.text |
|
do_pass: |
ldr r1, passmsg_addr |
mov r0, #4 |
swi #0x123456 |
exit 0 |
passmsg_addr: |
.word passmsg |
|
do_fail: |
ldr r1, failmsg_addr |
mov r0, #4 |
swi #0x123456 |
exit 1 |
failmsg_addr: |
.word failmsg |
|
.global _start |
_start: |
.endm |
|
# *** Other macros know pass/fail are 4 bytes in size! Yuck. |
|
.macro pass |
b do_pass |
.endm |
|
.macro fail |
b do_fail |
.endm |
|
.macro exit rc |
mov r1, #\rc |
mov r0, #0x2a @ decimal 42 |
swi #1 |
# If that returns, punt with a sigill. |
stc 0,cr0,[r0] |
.endm |
|
# Other macros know this only clobbers r0. |
.macro test_h_gr reg, val |
mvaddr_h_gr r0, \val |
cmp \reg, r0 |
beq . + 8 |
fail |
.endm |
|
.macro mvi_h_cc c, n, v, z |
ldi8 r0, 0 |
ldi8 r1, 1 |
.if xxx |
cmp r0, r1 |
.else |
cmp r1, r0 |
.endif |
.endm |
|
.macro test_h_cc c, n, v, z |
.if xxx |
bc . + 8 |
fail |
.else |
bnc . + 8 |
fail |
.endif |
.endm |
/thumb/pop.cgs
0,0 → 1,12
# arm testcase for pop {$rlist} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global pop |
pop: |
pop {0} |
|
pass |
/thumb/lsr.cgs
0,0 → 1,14
# arm testcase for lsr $rd,$rs,#$offset5 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global lsr |
lsr: |
lsr r0,r0,#0 |
|
# FIXME: Also lsr $rd,$rs |
|
pass |
/thumb/and.cgs
0,0 → 1,12
# arm testcase for and $rd,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global alu_and |
alu_and: |
and r0,r0 |
|
pass |
/thumb/bhi.cgs
0,0 → 1,12
# arm testcase for bhi $soffset8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global bhi |
bhi: |
bhi footext |
|
pass |
/thumb/ble.cgs
0,0 → 1,12
# arm testcase for ble $soffset8 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ble |
ble: |
ble footext |
|
pass |
/thumb/ror.cgs
0,0 → 1,12
# arm testcase for ror $rd,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global alu_ror |
alu_ror: |
ror r0,r0 |
|
pass |
/ldrsb.cgs
0,0 → 1,132
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsb_post_dec_imm_offset |
ldrsb_post_dec_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsb_post_dec_reg_offset |
ldrsb_post_dec_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsb_post_inc_imm_offset |
ldrsb_post_inc_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsb_post_inc_reg_offset |
ldrsb_post_inc_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsb_pre_dec_imm_offset |
ldrsb_pre_dec_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsb_pre_dec_reg_offset |
ldrsb_pre_dec_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsb_pre_dec_wb_imm_offset |
ldrsb_pre_dec_wb_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsb_pre_dec_wb_reg_offset |
ldrsb_pre_dec_wb_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsb_pre_inc_imm_offset |
ldrsb_pre_inc_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsb_pre_inc_reg_offset |
ldrsb_pre_inc_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsb_pre_inc_wb_imm_offset |
ldrsb_pre_inc_wb_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsb_pre_inc_wb_reg_offset |
ldrsb_pre_inc_wb_reg_offset: |
|
pass |
/sbc.cgs
0,0 → 1,36
# arm testcase for sbc$cond${set-cc?} $rd,$rn,$imm12 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global sbc_imm |
sbc_imm: |
sbc00 pc,pc,0 |
|
pass |
# arm testcase for sbc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global sbc_reg_imm_shift |
sbc_reg_imm_shift: |
sbc00 pc,pc,pc,lsl 0 |
|
pass |
# arm testcase for sbc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global sbc_reg_reg_shift |
sbc_reg_reg_shift: |
sbc00 pc,pc,pc,lsl pc |
|
pass |
/mla.cgs
0,0 → 1,12
# arm testcase for mla$cond${set-cc?} ${mul-rd},$rm,$rs,${mul-rn} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global mla |
mla: |
mla00 pc,pc,pc,pc |
|
pass |
/swp.cgs
0,0 → 1,12
# arm testcase for swp$cond $rd,$rm,[$rn] |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global swp |
swp: |
swp0 pc,pc,[pc] |
|
pass |
/tst.cgs
0,0 → 1,36
# arm testcase for tst${cond}${set-cc?} $rn,$imm12 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global tst_imm |
tst_imm: |
tst00 pc,0 |
|
pass |
# arm testcase for tst$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global tst_reg_imm_shift |
tst_reg_imm_shift: |
tst00 pc,pc,pc,lsl 0 |
|
pass |
# arm testcase for tst$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global tst_reg_reg_shift |
tst_reg_reg_shift: |
tst00 pc,pc,pc,lsl pc |
|
pass |
/ldrsh.cgs
0,0 → 1,132
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsh_post_dec_imm_offset |
ldrsh_post_dec_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsh_post_dec_reg_offset |
ldrsh_post_dec_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsh_post_inc_imm_offset |
ldrsh_post_inc_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsh_post_inc_reg_offset |
ldrsh_post_inc_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsh_pre_dec_imm_offset |
ldrsh_pre_dec_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsh_pre_dec_reg_offset |
ldrsh_pre_dec_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsh_pre_dec_wb_imm_offset |
ldrsh_pre_dec_wb_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsh_pre_dec_wb_reg_offset |
ldrsh_pre_dec_wb_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsh_pre_inc_imm_offset |
ldrsh_pre_inc_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsh_pre_inc_reg_offset |
ldrsh_pre_inc_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsh_pre_inc_wb_imm_offset |
ldrsh_pre_inc_wb_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrsh_pre_inc_wb_reg_offset |
ldrsh_pre_inc_wb_reg_offset: |
|
pass |
/ldm.cgs
0,0 → 1,89
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldmda_wb |
ldmda_wb: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldmda |
ldmda: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldmdb_wb |
ldmdb_wb: |
|
pass |
# arm testcase for ldm$cond .. |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldmdb |
ldmdb: |
ldm0 .. |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldmia_wb |
ldmia_wb: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldmia |
ldmia: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldmib_wb |
ldmib_wb: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldmib |
ldmib: |
|
pass |
/ldr.cgs
0,0 → 1,192
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr_post_dec_imm_offset |
ldr_post_dec_imm_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for ldr${cond}t $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr_post_dec_nonpriv_imm_offset |
ldr_post_dec_nonpriv_imm_offset: |
ldr0t pc,??? |
|
pass |
# arm testcase for ldr${cond}t $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr_post_dec_nonpriv_reg_offset |
ldr_post_dec_nonpriv_reg_offset: |
ldr0t pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr_post_dec_reg_offset |
ldr_post_dec_reg_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr_post_inc_imm_offset |
ldr_post_inc_imm_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for ldr${cond}t $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr_post_inc_nonpriv_imm_offset |
ldr_post_inc_nonpriv_imm_offset: |
ldr0t pc,??? |
|
pass |
# arm testcase for ldr${cond}t $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr_post_inc_nonpriv_reg_offset |
ldr_post_inc_nonpriv_reg_offset: |
ldr0t pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr_post_inc_reg_offset |
ldr_post_inc_reg_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr_pre_dec_imm_offset |
ldr_pre_dec_imm_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr_pre_dec_reg_offset |
ldr_pre_dec_reg_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr_pre_dec_wb_imm_offset |
ldr_pre_dec_wb_imm_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr_pre_dec_wb_reg_offset |
ldr_pre_dec_wb_reg_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr_pre_inc_imm_offset |
ldr_pre_inc_imm_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr_pre_inc_reg_offset |
ldr_pre_inc_reg_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr_pre_inc_wb_imm_offset |
ldr_pre_inc_wb_imm_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldr_pre_inc_wb_reg_offset |
ldr_pre_inc_wb_reg_offset: |
ldr0 pc,??? |
|
pass |
/smull.cgs
0,0 → 1,12
# arm testcase for smull$cond${set-cc?} $rdlo,$rdhi,$rm,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global smull |
smull: |
smull00 pc,pc,pc,pc |
|
pass |
/bic.cgs
0,0 → 1,43
# arm testcase for bic |
# mach: all |
|
# ??? Unfinished, more tests needed. |
|
.include "testutils.inc" |
|
start |
|
# bic$cond${set-cc?} $rd,$rn,$imm12 |
|
.global bic_imm |
bic_imm: |
mvi_h_gr r4,1 |
mvi_h_cnvz 0,0,0,0 |
bic r5,r4,#0 |
test_h_cnvz 0,0,0,0 |
test_h_gr r5,1 |
|
# bic$cond${set-cc?} $rd,$rn,$rm,${operbic2-shifttype} ${operbic2-shiftimm} |
|
.global bic_reg_imm_shift |
bic_reg_imm_shift: |
mvi_h_gr r4,7 |
mvi_h_gr r5,1 |
mvi_h_cnvz 0,0,0,0 |
bic r6,r4,r5,lsl #1 |
test_h_cnvz 0,0,0,0 |
test_h_gr r6,5 |
|
# bic$cond${set-cc?} $rd,$rn,$rm,${operbic2-shifttype} ${operbic2-shiftreg} |
|
.global bic_reg_reg_shift |
bic_reg_reg_shift: |
mvi_h_gr r4,7 |
mvi_h_gr r5,1 |
mvi_h_gr r6,1 |
mvi_h_cnvz 0,0,0,0 |
bic r7,r4,r5,lsl r6 |
test_h_cnvz 0,0,0,0 |
test_h_gr r7,5 |
|
pass |
/bl.cgs
0,0 → 1,21
# arm testcase for bl$cond $offset24 |
# mach: all |
|
.include "testutils.inc" |
|
start |
|
.global bl |
bl: |
mvi_h_gr r14,0 |
bl bl2 |
bl1: |
fail |
bl2: |
mvaddr_h_gr r4,bl1 |
cmp r14,r4 |
beq bl3 |
fail |
bl3: |
|
pass |
/umull.cgs
0,0 → 1,12
# arm testcase for umull$cond${set-cc?} $rdlo,$rdhi,$rm,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global umull |
umull: |
umull00 pc,pc,pc,pc |
|
pass |
/mvn.cgs
0,0 → 1,36
# arm testcase for mvn$cond${set-cc?} $rd,$imm12 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global mvn_imm |
mvn_imm: |
mvn00 pc,0 |
|
pass |
# arm testcase for mvn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global mvn_reg_imm_shift |
mvn_reg_imm_shift: |
mvn00 pc,pc,pc,lsl 0 |
|
pass |
# arm testcase for mvn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global mvn_reg_reg_shift |
mvn_reg_reg_shift: |
mvn00 pc,pc,pc,lsl pc |
|
pass |
/misaligned1.ms
0,0 → 1,61
# Test LDR instructions with offsets misaligned by 1 byte. |
# mach(): all |
|
.macro invalid |
# This is "undefined" but it's not properly decoded yet. |
.word 0x07ffffff |
# This is stc which isn't recognized yet. |
stc 0,cr0,[r0] |
.endm |
|
.global _start |
_start: |
# Run some simple insns to confirm the engine is at least working. |
nop |
|
# Skip over output text. |
bl do_test |
|
pass: |
.asciz "pass\n" |
.p2align 2 |
|
do_test: |
mov r4, r14 |
bl continue |
word1: |
.word 0x5555 |
continue: |
ldr r6, [r14, #1] |
ldr r7, word2 |
cmp r6, r7 |
# Failed. |
bne done |
|
output_next: |
# Output a character (in arm mode). |
mov r0,#3 |
mov r1,r4 |
swi #0x123456 |
|
# Load next character, see if done. |
add r4,r4,#1 |
sub r3,r3,r3 |
ldrb r5,[r4,r3] |
teq r5,#0 |
bne output_next |
|
done: |
mov r0,#0x18 |
ldr r1,exit_code |
swi #0x123456 |
|
# If that fails, try to die with an invalid insn. |
invalid |
|
exit_code: |
.word 0x20026 |
.word 0xFFFFFFFF |
word2: |
.word 0x55000055 |
.word 0xFFFFFFFF |
/mrs.cgs
0,0 → 1,24
# arm testcase for mrs$cond $rd,cpsr |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global mrs_c |
mrs_c: |
mrs0 pc,cpsr |
|
pass |
# arm testcase for mrs$cond $rd,spsr |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global mrs_s |
mrs_s: |
mrs0 pc,spsr |
|
pass |
/misaligned3.ms
0,0 → 1,62
# Test LDR instructions with offsets misaligned by 3 bytes. |
# mach(): all |
|
.macro invalid |
# This is "undefined" but it's not properly decoded yet. |
.word 0x07ffffff |
# This is stc which isn't recognized yet. |
stc 0,cr0,[r0] |
.endm |
|
.global _start |
_start: |
# Run some simple insns to confirm the engine is at least working. |
nop |
|
# Skip over output text. |
bl do_test |
|
pass: |
.asciz "pass\n" |
.p2align 2 |
|
do_test: |
mov r4, r14 |
bl continue |
word1: |
.word 0x5555 |
continue: |
ldr r6, [r14, #3] |
ldr r7, word2 |
cmp r6, r7 |
# Failed. |
bne done |
|
output_next: |
# Output a character (in arm mode). |
mov r0,#3 |
mov r1,r4 |
swi #0x123456 |
|
# Load next character, see if done. |
add r4,r4,#1 |
sub r3,r3,r3 |
ldrb r5,[r4,r3] |
teq r5,#0 |
bne output_next |
|
done: |
mov r0,#0x18 |
ldr r1,exit_code |
swi #0x123456 |
|
# If that fails, try to die with an invalid insn. |
invalid |
|
exit_code: |
.word 0x20026 |
|
.word 0xFFFFFFFF |
word2: |
.word 0x555500 |
.word 0xFFFFFFFF |
/orr.cgs
0,0 → 1,36
# arm testcase for orr$cond${set-cc?} $rd,$rn,$imm12 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global orr_imm |
orr_imm: |
orr00 pc,pc,0 |
|
pass |
# arm testcase for orr$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global orr_reg_imm_shift |
orr_reg_imm_shift: |
orr00 pc,pc,pc,lsl 0 |
|
pass |
# arm testcase for orr$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global orr_reg_reg_shift |
orr_reg_reg_shift: |
orr00 pc,pc,pc,lsl pc |
|
pass |
/stm.cgs
0,0 → 1,88
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global stmda_wb |
stmda_wb: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global stmda |
stmda: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global stmdb_wb |
stmdb_wb: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global stmdb |
stmdb: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global stmia_wb |
stmia_wb: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global stmia |
stmia: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global stmib_wb |
stmib_wb: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global stmib |
stmib: |
|
pass |
/xscale/blx.cgs
0,0 → 1,31
# arm testcase for bl$cond $offset24 |
# mach: all |
|
.include "testutils.inc" |
|
start |
|
.arm |
blx thumb |
|
.thumb |
.thumb_func |
thumb: |
nop |
blx next |
blx PASS |
nop |
nop |
|
.section text1, "ax" |
.arm |
next: |
add r0, r1, r0 |
bx lr |
|
FAIL: |
fail |
PASS: |
pass |
|
|
/xscale/mia.cgs
0,0 → 1,35
# XSCALE testcase for MIA |
# mach: xscale |
# as: -mcpu=xscale |
|
.include "testutils.inc" |
|
start |
|
.global mia |
mia: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Multilply Accumulate |
|
mvi_h_gr r0, 0x11223344 |
mvi_h_gr r1, 0x55667788 |
mvi_h_gr r2, 0x12345678 |
mvi_h_gr r3, 0x9abcdef0 |
|
mar acc0, r0, r1 |
|
mia acc0, r2, r3 |
|
mra r0, r1, acc0 |
|
test_h_gr r0, 0x354f53c4 |
test_h_gr r1, 0x4e330b5e |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
pass |
/xscale/miaxy.cgs
0,0 → 1,89
# XSCALE testcase for MIAxy |
# mach: xscale |
# as: -mcpu=xscale |
|
.include "testutils.inc" |
|
start |
|
.global miaXY |
miaXY: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Bottom Bottom Multilply Accumulate |
|
mvi_h_gr r0, 0x11223344 |
mvi_h_gr r1, 0x55667788 |
mvi_h_gr r2, 0x12345678 |
mvi_h_gr r3, 0x9abcdef0 |
|
mar acc0, r0, r1 |
|
miaBB acc0, r2, r3 |
|
mra r0, r1, acc0 |
|
test_h_gr r0, 0x05f753c4 |
test_h_gr r1, 0x55667788 |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
# Test Bottom Top Multilply Accumulate |
|
mvi_h_gr r0, 0x11223344 |
mvi_h_gr r1, 0x55667788 |
mvi_h_gr r2, 0x12345678 |
mvi_h_gr r3, 0x9abcdef0 |
|
mar acc0, r0, r1 |
|
miaBT acc0, r2, r3 |
|
mra r0, r1, acc0 |
|
test_h_gr r0, 0xeeede364 |
test_h_gr r1, 0x55667787 |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
# Test Top Bottom Multilply Accumulate |
|
mvi_h_gr r0, 0x11223344 |
mvi_h_gr r1, 0x55667788 |
mvi_h_gr r2, 0x12345678 |
mvi_h_gr r3, 0x9abcdef0 |
|
mar acc0, r0, r1 |
|
miaTB acc0, r2, r3 |
|
mra r0, r1, acc0 |
|
test_h_gr r0, 0x0ec85c04 |
test_h_gr r1, 0x55667788 |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
# Test Top Top Multilply Accumulate |
|
mvi_h_gr r0, 0x11223344 |
mvi_h_gr r1, 0x55667788 |
mvi_h_gr r2, 0x12345678 |
mvi_h_gr r3, 0x9abcdef0 |
|
mar acc0, r0, r1 |
|
miaTT acc0, r2, r3 |
|
mra r0, r1, acc0 |
|
test_h_gr r0, 0x09eed974 |
test_h_gr r1, 0x55667788 |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
pass |
/xscale/testutils.inc
0,0 → 1,118
# r0-r3 are used as tmps, consider them call clobbered by these macros. |
# This uses the angel rom monitor calls. |
# ??? How do we use the \@ facility of .macros ??? |
# @ is the comment char! |
|
.macro mvi_h_gr reg, val |
ldr \reg,[pc] |
b . + 8 |
.word \val |
.endm |
|
.macro mvaddr_h_gr reg, addr |
ldr \reg,[pc] |
b . + 8 |
.word \addr |
.endm |
|
.macro start |
.data |
failmsg: |
.asciz "fail\n" |
passmsg: |
.asciz "pass\n" |
.text |
|
do_pass: |
ldr r1, passmsg_addr |
mov r0, #4 |
swi #0x123456 |
exit 0 |
passmsg_addr: |
.word passmsg |
|
do_fail: |
ldr r1, failmsg_addr |
mov r0, #4 |
swi #0x123456 |
exit 1 |
failmsg_addr: |
.word failmsg |
|
.global _start |
_start: |
.endm |
|
# *** Other macros know pass/fail are 4 bytes in size! Yuck. |
|
.macro pass |
b do_pass |
.endm |
|
.macro fail |
b do_fail |
.endm |
|
.macro exit rc |
# ??? This works with the ARMulator but maybe not others. |
#mov r0, #\rc |
#swi #1 |
# This seems to be portable (though it ignores rc). |
mov r0,#0x18 |
mvi_h_gr r1, 0x20026 |
swi #0x123456 |
# If that returns, punt with a sigill. |
stc 0,cr0,[r0] |
.endm |
|
# Other macros know this only clobbers r0. |
# WARNING: It also clobbers the condition codes (FIXME). |
.macro test_h_gr reg, val |
mvaddr_h_gr r0, \val |
cmp \reg, r0 |
beq . + 8 |
fail |
.endm |
|
.macro mvi_h_cnvz c, n, v, z |
mov r0, #0 |
.if \c |
orr r0, r0, #0x20000000 |
.endif |
.if \n |
orr r0, r0, #0x80000000 |
.endif |
.if \v |
orr r0, r0, #0x10000000 |
.endif |
.if \z |
orr r0, r0, #0x40000000 |
.endif |
mrs r1, cpsr |
bic r1, r1, #0xf0000000 |
orr r1, r1, r0 |
msr cpsr, r1 |
# ??? nops needed |
.endm |
|
# ??? Preserve condition codes? |
.macro test_h_cnvz c, n, v, z |
mov r0, #0 |
.if \c |
orr r0, r0, #0x20000000 |
.endif |
.if \n |
orr r0, r0, #0x80000000 |
.endif |
.if \v |
orr r0, r0, #0x10000000 |
.endif |
.if \z |
orr r0, r0, #0x40000000 |
.endif |
mrs r1, cpsr |
and r1, r1, #0xf0000000 |
cmp r0, r1 |
beq . + 8 |
fail |
.endm |
/xscale/miaph.cgs
0,0 → 1,35
# XSCALE testcase for MIAPH |
# mach: xscale |
# as: -mcpu=xscale |
|
.include "testutils.inc" |
|
start |
|
.global miaph |
miaph: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Multilply Accumulate |
|
mvi_h_gr r0, 0x11223344 |
mvi_h_gr r1, 0x55667788 |
mvi_h_gr r2, 0x12345678 |
mvi_h_gr r3, 0x9abcdef0 |
|
mar acc0, r0, r1 |
|
miaph acc0, r2, r3 |
|
mra r0, r1, acc0 |
|
test_h_gr r0, 0xfec3f9f4 |
test_h_gr r1, 0x55667787 |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
pass |
/xscale/mra.cgs
0,0 → 1,30
# XScale testcase for MAR and MRA |
# mach: xscale |
# as: -mcpu=xscale |
|
.include "testutils.inc" |
|
start |
|
.global mar_mra |
mar_mra: |
mvi_h_gr r2,0 |
mvi_h_gr r3,0 |
mvi_h_gr r4,0x0000EFA0 |
mvi_h_gr r5,0xA0A0A0A0 |
|
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
mar acc0, r5, r4 |
mra r2, r3, acc0 |
|
test_h_gr r2,0xA0A0A0A0 |
test_h_gr r3,0x0000EFA0 |
test_h_gr r4,0x0000EFA0 |
test_h_gr r5,0xA0A0A0A0 |
|
pass |
/xscale/xscale.exp
0,0 → 1,28
# XSCALE simulator testsuite. |
|
if { [istarget xscale*-*-*] } { |
# load support procs (none yet) |
# load_lib cgen.exp |
|
# all machines |
set all_machs "xscale" |
|
if [is_remote host] { |
remote_download host $srcdir/$subdir/testutils.inc |
} |
|
# The .cgs suffix is for "cgen .s". |
foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { |
# If we're only testing specific files and this isn't one of them, |
# skip it. |
if ![runtest_file_p $runtests $src] { |
continue |
} |
|
run_sim_test $src $all_machs |
} |
|
if [is_remote host] { |
remote_file host delete testutils.inc |
} |
} |
/hello.ms
0,0 → 1,91
# output(): Hello, world.\n |
# mach(): all |
|
# Emit hello world while switching back and forth between arm/thumb. |
# ??? Unfinished |
|
.macro invalid |
# This is "undefined" but it's not properly decoded yet. |
.word 0x07ffffff |
# This is stc which isn't recognized yet. |
stc 0,cr0,[r0] |
.endm |
|
.global _start |
_start: |
# Run some simple insns to confirm the engine is at least working. |
nop |
|
# Skip over output text. |
|
bl skip_output |
|
hello_text: |
.asciz "Hello, world.\n" |
|
.p2align 2 |
skip_output: |
|
# Prime loop. |
|
mov r4, r14 |
|
output_next: |
|
# Switch arm->thumb to output next chacter. |
# At this point r4 must point to the next character to output. |
|
adr r0, into_thumb + 1 |
bx r0 |
|
into_thumb: |
.thumb |
|
# Output a character. |
|
mov r0,#3 @ writec angel call |
mov r1,r4 |
swi 0xab @ ??? Confirm number. |
|
# Switch thumb->arm. |
|
adr r5, back_to_arm |
bx r5 |
|
.p2align 2 |
back_to_arm: |
.arm |
|
# Load next character, see if done. |
|
add r4,r4,#1 |
sub r3,r3,r3 |
ldrb r5,[r4,r3] |
teq r5,#0 |
beq done |
|
# Output a character (in arm mode). |
|
mov r0,#3 |
mov r1,r4 |
swi #0x123456 |
|
# Load next character, see if done. |
|
add r4,r4,#1 |
sub r3,r3,r3 |
ldrb r5,[r4,r3] |
teq r5,#0 |
bne output_next |
|
done: |
mov r0,#0x18 |
ldr r1,exit_code |
swi #0x123456 |
|
# If that fails, try to die with an invalid insn. |
|
invalid |
|
exit_code: |
.word 0x20026 |
/str.cgs
0,0 → 1,192
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global str_post_dec_imm_offset |
str_post_dec_imm_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for ldr${cond}t $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global str_post_dec_nonpriv_imm_offset |
str_post_dec_nonpriv_imm_offset: |
ldr0t pc,??? |
|
pass |
# arm testcase for str${cond}t $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global str_post_dec_nonpriv_reg_offset |
str_post_dec_nonpriv_reg_offset: |
str0t pc,??? |
|
pass |
# arm testcase for str${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global str_post_dec_reg_offset |
str_post_dec_reg_offset: |
str0 pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global str_post_inc_imm_offset |
str_post_inc_imm_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for ldr${cond}t $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global str_post_inc_nonpriv_imm_offset |
str_post_inc_nonpriv_imm_offset: |
ldr0t pc,??? |
|
pass |
# arm testcase for str${cond}t $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global str_post_inc_nonpriv_reg_offset |
str_post_inc_nonpriv_reg_offset: |
str0t pc,??? |
|
pass |
# arm testcase for str${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global str_post_inc_reg_offset |
str_post_inc_reg_offset: |
str0 pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global str_pre_dec_imm_offset |
str_pre_dec_imm_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for str${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global str_pre_dec_reg_offset |
str_pre_dec_reg_offset: |
str0 pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global str_pre_dec_wb_imm_offset |
str_pre_dec_wb_imm_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for str${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global str_pre_dec_wb_reg_offset |
str_pre_dec_wb_reg_offset: |
str0 pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global str_pre_inc_imm_offset |
str_pre_inc_imm_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for str${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global str_pre_inc_reg_offset |
str_pre_inc_reg_offset: |
str0 pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global str_pre_inc_wb_imm_offset |
str_pre_inc_wb_imm_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for str${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global str_pre_inc_wb_reg_offset |
str_pre_inc_wb_reg_offset: |
str0 pc,??? |
|
pass |
/smlal.cgs
0,0 → 1,12
# arm testcase for smlal$cond${set-cc?} $rdlo,$rdhi,$rm,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global smlal |
smlal: |
smlal00 pc,pc,pc,pc |
|
pass |
/bx.cgs
0,0 → 1,12
# arm testcase for bx$cond $rn |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global bx |
bx: |
bx0 pc |
|
pass |
/umlal.cgs
0,0 → 1,12
# arm testcase for umlal$cond${set-cc?} $rdlo,$rdhi,$rm,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global umlal |
umlal: |
umlal00 pc,pc,pc,pc |
|
pass |
/strb.cgs
0,0 → 1,192
# arm testcase for ldr${cond}b $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strb_post_dec_imm_offset |
strb_post_dec_imm_offset: |
ldr0b pc,??? |
|
pass |
# arm testcase for ldr${cond}t $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strb_post_dec_nonpriv_imm_offset |
strb_post_dec_nonpriv_imm_offset: |
ldr0t pc,??? |
|
pass |
# arm testcase for str${cond}t $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strb_post_dec_nonpriv_reg_offset |
strb_post_dec_nonpriv_reg_offset: |
str0t pc,??? |
|
pass |
# arm testcase for str${cond}b $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strb_post_dec_reg_offset |
strb_post_dec_reg_offset: |
str0b pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strb_post_inc_imm_offset |
strb_post_inc_imm_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for ldr${cond}t $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strb_post_inc_nonpriv_imm_offset |
strb_post_inc_nonpriv_imm_offset: |
ldr0t pc,??? |
|
pass |
# arm testcase for str${cond}t $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strb_post_inc_nonpriv_reg_offset |
strb_post_inc_nonpriv_reg_offset: |
str0t pc,??? |
|
pass |
# arm testcase for str${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strb_post_inc_reg_offset |
strb_post_inc_reg_offset: |
str0 pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strb_pre_dec_imm_offset |
strb_pre_dec_imm_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for str${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strb_pre_dec_reg_offset |
strb_pre_dec_reg_offset: |
str0 pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strb_pre_dec_wb_imm_offset |
strb_pre_dec_wb_imm_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for str${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strb_pre_dec_wb_reg_offset |
strb_pre_dec_wb_reg_offset: |
str0 pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strb_pre_inc_imm_offset |
strb_pre_inc_imm_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for str${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strb_pre_inc_reg_offset |
strb_pre_inc_reg_offset: |
str0 pc,??? |
|
pass |
# arm testcase for ldr${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strb_pre_inc_wb_imm_offset |
strb_pre_inc_wb_imm_offset: |
ldr0 pc,??? |
|
pass |
# arm testcase for str${cond} $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strb_pre_inc_wb_reg_offset |
strb_pre_inc_wb_reg_offset: |
str0 pc,??? |
|
pass |
/iwmmxt/wshufh.cgs
0,0 → 1,35
# Intel(r) Wireless MMX(tm) technology testcase for WSHUFH |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wshufh |
wshufh: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wshufh wr1, wr0, #0x1b |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0xdef09abc |
test_h_gr r3, 0x56781234 |
|
pass |
/iwmmxt/wpack.cgs
0,0 → 1,173
# Intel(r) Wireless MMX(tm) technology testcase for WPACK |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wpack |
wpack: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Halfword, Unsigned Saturation, Packing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wpackhus wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x0000ffff |
test_h_gr r5, 0x0000ffff |
|
# Test Halfword, Signed Saturation, Packing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wpackhss wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x80807f7f |
test_h_gr r5, 0x00007f7f |
|
# Test Word, Unsigned Saturation, Packing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wpackwus wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x0000ffff |
test_h_gr r5, 0x0000ffff |
|
# Test Word, Signed Saturation, Packing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wpackwss wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x80007fff |
test_h_gr r5, 0x00007fff |
|
# Test Double Word, Unsigned Saturation, Packing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wpackdus wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x00000000 |
test_h_gr r5, 0x11111111 |
|
# Test Double Word, Signed Saturation, Packing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wpackdss wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x80000000 |
test_h_gr r5, 0x11111111 |
|
pass |
/iwmmxt/wzero.cgs
0,0 → 1,29
# Intel(r) Wireless MMX(tm) technology testcase for WZERO |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wzero |
wzero: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
|
tmcrr wr0, r0, r1 |
|
wzero wr0 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x00000000 |
test_h_gr r1, 0x00000000 |
|
pass |
/iwmmxt/wor.cgs
0,0 → 1,41
# Intel(r) Wireless MMX(tm) technology testcase for WOR |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wor |
wor: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wor wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x13355779 |
test_h_gr r5, 0x9abcdef0 |
|
pass |
/iwmmxt/wandn.cgs
0,0 → 1,41
# Intel(r) Wireless MMX(tm) technology testcase for WANDN |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wandn |
wandn: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wandn wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x02244668 |
test_h_gr r5, 0x9abcdef0 |
|
pass |
/iwmmxt/wmin.cgs
0,0 → 1,173
# Intel(r) Wireless MMX(tm) technology testcase for WMIN |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wmin |
wmin: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned Byte Minimum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wminub wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x11111111 |
test_h_gr r5, 0x11111100 |
|
# Test Signed Byte Minimum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wminsb wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x11111111 |
test_h_gr r5, 0x9abcde00 |
|
# Test Unsigned Halfword Minimum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wminuh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x11111111 |
test_h_gr r5, 0x11111111 |
|
# Test Signed Halfword Minimum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wminsh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x11111111 |
test_h_gr r5, 0x9abcde00 |
|
# Test Unsigned Word Minimum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wminuw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x11111111 |
test_h_gr r5, 0x11111111 |
|
# Test Signed Word Minimum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wminsw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x11111111 |
test_h_gr r5, 0x9abcde00 |
|
pass |
/iwmmxt/tmiaxy.cgs
0,0 → 1,89
# Intel(r) Wireless MMX(tm) technology testcase for TMIAxy |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global tmiaXY |
tmiaXY: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Bottom Bottom Multilply Accumulate |
|
mvi_h_gr r0, 0x11223344 |
mvi_h_gr r1, 0x55667788 |
mvi_h_gr r2, 0x12345678 |
mvi_h_gr r3, 0x9abcdef0 |
|
tmcrr wr0, r0, r1 |
|
tmiaBB wr0, r2, r3 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x05f753c4 |
test_h_gr r1, 0x55667788 |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
# Test Bottom Top Multilply Accumulate |
|
mvi_h_gr r0, 0x11223344 |
mvi_h_gr r1, 0x55667788 |
mvi_h_gr r2, 0x12345678 |
mvi_h_gr r3, 0x9abcdef0 |
|
tmcrr wr0, r0, r1 |
|
tmiaBT wr0, r2, r3 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0xeeede364 |
test_h_gr r1, 0x55667787 |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
# Test Top Bottom Multilply Accumulate |
|
mvi_h_gr r0, 0x11223344 |
mvi_h_gr r1, 0x55667788 |
mvi_h_gr r2, 0x12345678 |
mvi_h_gr r3, 0x9abcdef0 |
|
tmcrr wr0, r0, r1 |
|
tmiaTB wr0, r2, r3 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x0ec85c04 |
test_h_gr r1, 0x55667788 |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
# Test Top Top Multilply Accumulate |
|
mvi_h_gr r0, 0x11223344 |
mvi_h_gr r1, 0x55667788 |
mvi_h_gr r2, 0x12345678 |
mvi_h_gr r3, 0x9abcdef0 |
|
tmcrr wr0, r0, r1 |
|
tmiaTT wr0, r2, r3 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x09eed974 |
test_h_gr r1, 0x55667788 |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
pass |
/iwmmxt/wmax.cgs
0,0 → 1,173
# Intel(r) Wireless MMX(tm) technology testcase for WMAX |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wmax |
wmax: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned Byte Maximum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmaxub wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x12345678 |
test_h_gr r5, 0x9abcde11 |
|
# Test Signed Byte Maximum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmaxsb wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x12345678 |
test_h_gr r5, 0x11111111 |
|
# Test Unsigned Halfword Maximum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmaxuh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x12345678 |
test_h_gr r5, 0x9abcde00 |
|
# Test Signed Halfword Maximum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmaxsh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x12345678 |
test_h_gr r5, 0x11111111 |
|
# Test Unsigned Word Maximum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmaxuw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x12345678 |
test_h_gr r5, 0x9abcde00 |
|
# Test Signed Word Maximum |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmaxsw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x12345678 |
test_h_gr r5, 0x11111111 |
|
pass |
/iwmmxt/tbcst.cgs
0,0 → 1,65
# Intel(r) Wireless MMX(tm) technology testcase for TBCST |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global tbcst |
tbcst: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Byte Wide Broadcast |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
tbcstb wr0, r2 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0xffffffff |
test_h_gr r1, 0xffffffff |
test_h_gr r2, 0x111111ff |
|
# Test Half Word Wide Broadcast |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
tbcsth wr0, r2 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x11ff11ff |
test_h_gr r1, 0x11ff11ff |
test_h_gr r2, 0x111111ff |
|
# Test Word Wide Broadcast |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
tbcstw wr0, r2 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x111111ff |
test_h_gr r1, 0x111111ff |
test_h_gr r2, 0x111111ff |
|
pass |
/iwmmxt/wadd.cgs
0,0 → 1,251
# Intel(r) Wireless MMX(tm) technology testcase for WADD |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wadd |
wadd: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test UnSaturated Byte Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waddb wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456789 |
test_h_gr r5, 0xabcdef11 |
|
# Test Unsigned Saturated Byte Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waddbus wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456789 |
test_h_gr r5, 0xabcdef11 |
|
# Test Signed Saturated Byte Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waddbss wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x2345677f |
test_h_gr r5, 0xabcdef11 |
|
# Test UnSaturated Halfword Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waddh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456789 |
test_h_gr r5, 0xabcdef11 |
|
# Test Unsigned Saturated Halfword Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waddhus wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456789 |
test_h_gr r5, 0xabcdef11 |
|
# Test Signed Saturated Halfword Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waddhss wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456789 |
test_h_gr r5, 0xabcdef11 |
|
# Test UnSaturated Word Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waddw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456789 |
test_h_gr r5, 0xabcdef11 |
|
# Test Unsigned Saturated Word Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waddwus wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456789 |
test_h_gr r5, 0xabcdef11 |
|
# Test Signed Saturated Word Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waddwss wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456789 |
test_h_gr r5, 0xabcdef11 |
|
pass |
/iwmmxt/wsub.cgs
0,0 → 1,251
# Intel(r) Wireless MMX(tm) technology testcase for WSUB |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wsub |
wsub: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsaturated Byte subtraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsubb wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x89abcdef |
|
# Test Unsigned saturated Byte subtraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsubbus wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x89abcd00 |
|
# Test Signed saturated Byte subtraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsubbss wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x89abcdef |
|
# Test Unsaturated Halfword subtraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsubh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x89abccef |
|
# Test Unsigned saturated Halfword subtraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsubhus wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x89abccef |
|
# Test Signed saturated Halfword subtraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsubhss wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x89abccef |
|
# Test Unsaturated Word subtraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsubw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x89abccef |
|
# Test Unsigned saturated Word subtraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsubwus wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x89abccef |
|
# Test Signed saturated Word subtraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsubwss wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x89abccef |
|
pass |
/iwmmxt/wmul.cgs
0,0 → 1,121
# Intel(r) Wireless MMX(tm) technology testcase for WMUL |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wmul |
wmul: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned, Most Significant Multiply |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmulum wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x013605c3 |
test_h_gr r5, 0x14a11db9 |
|
# Test Unsigned, Least Significant Multiply |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmulul wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0xa974b5f8 |
test_h_gr r5, 0x84f87be0 |
|
# Test Signed, Most Significant Multiply |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmulsm wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x013605c3 |
test_h_gr r5, 0xf27ffb97 |
|
# Test Signed, Least Significant Multiply |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmulsl wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0xa974b5f8 |
test_h_gr r5, 0x84f87be0 |
|
pass |
/iwmmxt/wunpckeh.cgs
0,0 → 1,137
# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKEH |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wunpckeh |
wunpckeh: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned Byte Unpacking |
|
mvi_h_gr r0, 0x12345687 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckehub wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345687 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x00de00f0 |
test_h_gr r3, 0x009a00bc |
|
# Test Signed Byte Unpacking |
|
mvi_h_gr r0, 0x12345687 |
mvi_h_gr r1, 0x7abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckehsb wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345687 |
test_h_gr r1, 0x7abcdef0 |
test_h_gr r2, 0xffdefff0 |
test_h_gr r3, 0x007affbc |
|
# Test Unsigned Halfword Unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckehuh wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x0000def0 |
test_h_gr r3, 0x00009abc |
|
# Test Signed Halfword Unpacking |
|
mvi_h_gr r0, 0x12348678 |
mvi_h_gr r1, 0x7abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckehsh wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12348678 |
test_h_gr r1, 0x7abcdef0 |
test_h_gr r2, 0xffffdef0 |
test_h_gr r3, 0x00007abc |
|
# Test Unsigned Word Unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckehuw wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x9abcdef0 |
test_h_gr r3, 0x00000000 |
|
# Test Signed Word Unpacking |
|
mvi_h_gr r0, 0x82345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckehsw wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x82345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x9abcdef0 |
test_h_gr r3, 0xffffffff |
|
pass |
/iwmmxt/wmov.cgs
0,0 → 1,35
# Intel(r) Wireless MMX(tm) technology testcase for WMOV |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wmov |
wmov: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wmov wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
pass |
/iwmmxt/wunpckel.cgs
0,0 → 1,137
# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKEL |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wunpckel |
wunpckel: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned Byte Unpacking |
|
mvi_h_gr r0, 0x12345687 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckelub wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345687 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x00560087 |
test_h_gr r3, 0x00120034 |
|
# Test Signed Byte Unpacking |
|
mvi_h_gr r0, 0x12345687 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckelsb wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345687 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x0056ff87 |
test_h_gr r3, 0x00120034 |
|
# Test Unsigned Halfword Unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckeluh wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x00005678 |
test_h_gr r3, 0x00001234 |
|
# Test Signed Halfword Unpacking |
|
mvi_h_gr r0, 0x12348678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckelsh wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12348678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0xffff8678 |
test_h_gr r3, 0x00001234 |
|
# Test Unsigned Word Unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckeluw wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x00000000 |
|
# Test Signed Word Unpacking |
|
mvi_h_gr r0, 0x82345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wunpckelsw wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x82345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x82345678 |
test_h_gr r3, 0xffffffff |
|
pass |
/iwmmxt/wunpckih.cgs
0,0 → 1,95
# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKIH |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wunpckih |
wunpckih: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Byte unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wunpckihb wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x00de00f0 |
test_h_gr r5, 0x009a00bc |
|
# Test Halfword unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wunpckihh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x0000def0 |
test_h_gr r5, 0x00009abc |
|
# Test Word unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wunpckihw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x9abcdef0 |
test_h_gr r5, 0x00000000 |
|
pass |
/iwmmxt/wand.cgs
0,0 → 1,41
# Intel(r) Wireless MMX(tm) technology testcase for WAND |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wand |
wand: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wand wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x10101010 |
test_h_gr r5, 0x00000000 |
|
pass |
/iwmmxt/wror.cgs
0,0 → 1,167
# Intel(r) Wireless MMX(tm) technology testcase for WROR |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wror |
wror: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Halfword wide rotate right by register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wrorh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x091a2b3c |
test_h_gr r5, 0x4d5e6f78 |
|
# Test Halfword wide rotate right by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr0, r2 |
tmcrr wr1, r2, r3 |
|
wrorhg wr1, wr0, wcgr0 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr0 |
tmrrc r3, r4, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x091a2b3c |
test_h_gr r4, 0x4d5e6f78 |
|
# Test Word wide rotate right by register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wrorw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x2b3c091a |
test_h_gr r5, 0x6f784d5e |
|
# Test Word wide rotate right by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr0, r2 |
tmcrr wr1, r2, r3 |
|
wrorwg wr1, wr0, wcgr0 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr0 |
tmrrc r3, r4, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x2b3c091a |
test_h_gr r4, 0x6f784d5e |
|
# Test Double Word wide rotate right by register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wrord wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x6f78091a |
test_h_gr r5, 0x2b3c4d5e |
|
# Test Double Word wide rotate right by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr0, r2 |
tmcrr wr1, r2, r3 |
|
wrordg wr1, wr0, wcgr0 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr0 |
tmrrc r3, r4, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x6f78091a |
test_h_gr r4, 0x2b3c4d5e |
|
pass |
/iwmmxt/tmia.cgs
0,0 → 1,35
# Intel(r) Wireless MMX(tm) technology testcase for TMIA |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global tmia |
tmia: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Multilply Accumulate |
|
mvi_h_gr r0, 0x11223344 |
mvi_h_gr r1, 0x55667788 |
mvi_h_gr r2, 0x12345678 |
mvi_h_gr r3, 0x9abcdef0 |
|
tmcrr wr0, r0, r1 |
|
tmia wr0, r2, r3 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x354f53c4 |
test_h_gr r1, 0x4e330b5e |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
pass |
/iwmmxt/wunpckil.cgs
0,0 → 1,95
# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKIL |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wunpckil |
wunpckil: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Byte unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wunpckilb wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x11561178 |
test_h_gr r5, 0x11121134 |
|
# Test Halfword unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wunpckilh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x11115678 |
test_h_gr r5, 0x11111234 |
|
# Test Word unpacking |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wunpckilw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x12345678 |
test_h_gr r5, 0x11111111 |
|
pass |
/iwmmxt/wxor.cgs
0,0 → 1,41
# Intel(r) Wireless MMX(tm) technology testcase for WXOR |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wxor |
wxor: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wxor wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x03254769 |
test_h_gr r5, 0x9abcdef0 |
|
pass |
/iwmmxt/tmovmsk.cgs
0,0 → 1,65
# Intel(r) Wireless MMX(tm) technology testcase for TMOVMSK |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global tmovmsk |
tmovmsk: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Byte Wide Mask Transfer |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
|
tmcrr wr0, r0, r1 |
|
tmovmskb r2, wr0 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x000000f0 |
|
# Test Half Word Wide Mask Transfer |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
|
tmcrr wr0, r0, r1 |
|
tmovmskh r2, wr0 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x0000000c |
|
# Test Word Wide Mask Transfer |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
|
tmcrr wr0, r0, r1 |
|
tmovmskw r2, wr0 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x00000002 |
|
pass |
/iwmmxt/iwmmxt.exp
0,0 → 1,28
# Intel(r) Wireless MMX(tm) technology simulator testsuite. |
|
if { [istarget xscale*-*-*] } { |
# load support procs (none yet) |
# load_lib cgen.exp |
|
# all machines |
set all_machs "xscale" |
|
if [is_remote host] { |
remote_download host $srcdir/$subdir/testutils.inc |
} |
|
# The .cgs suffix is for "cgen .s". |
foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { |
# If we're only testing specific files and this isn't one of them, |
# skip it. |
if ![runtest_file_p $runtests $src] { |
continue |
} |
|
run_sim_test $src $all_machs |
} |
|
if [is_remote host] { |
remote_file host delete testutils.inc |
} |
} |
/iwmmxt/wsra.cgs
0,0 → 1,167
# Intel(r) Wireless MMX(tm) technology testcase for WSRA |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wsra |
wsra: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Halfword Arithmetic Shift Right |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsrah wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01230567 |
test_h_gr r5, 0xf9abfdef |
|
# Test Halfword Arithmetic Shift Right by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr1, r2 |
tmcrr wr1, r3, r4 |
|
wsrahg wr1, wr0, wcgr1 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr1 |
tmrrc r3, r4, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x01230567 |
test_h_gr r4, 0xf9abfdef |
|
# Test Word Arithmetic Shift Right |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsraw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0xf9abcdef |
|
# Test Word Arithmetic Shift Right by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr2, r2 |
tmcrr wr1, r3, r4 |
|
wsrawg wr1, wr0, wcgr2 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr2 |
tmrrc r3, r4, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x01234567 |
test_h_gr r4, 0xf9abcdef |
|
# Test Double Word Arithmetic Shift Right |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdefc |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsrad wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdefc |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0xc1234567 |
test_h_gr r5, 0xf9abcdef |
|
# Test Double Word Arithmetic Shift Right by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdefc |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr3, r2 |
tmcrr wr1, r3, r4 |
|
wsradg wr1, wr0, wcgr3 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr3 |
tmrrc r3, r4, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdefc |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0xc1234567 |
test_h_gr r4, 0xf9abcdef |
|
pass |
/iwmmxt/wacc.cgs
0,0 → 1,77
# Intel(r) Wireless MMX(tm) technology testcase for WACC |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wacc |
wacc: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned Byte Wide Accumulation |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
waccb wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x00000438 |
test_h_gr r3, 0x00000000 |
|
# Test Unsigned Half Word Wide Accumulation |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
wacch wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x0001e258 |
test_h_gr r3, 0x00000000 |
|
# Test Unsigned Word Wide Accumulation |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0 |
mvi_h_gr r3, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
|
waccw wr1, wr0 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0xacf13568 |
test_h_gr r3, 0x00000000 |
|
pass |
/iwmmxt/wsll.cgs
0,0 → 1,167
# Intel(r) Wireless MMX(tm) technology testcase for WSLL |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wsll |
wsll: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Halfword Logical Shift Left |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsllh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23406780 |
test_h_gr r5, 0xabc0ef00 |
|
# Test Halfword Aritc Shift Left by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr1, r2 |
tmcrr wr1, r3, r4 |
|
wsllhg wr1, wr0, wcgr1 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr1 |
tmrrc r3, r4, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x23406780 |
test_h_gr r4, 0xabc0ef00 |
|
# Test Word Logical Shift Left |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsllw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456780 |
test_h_gr r5, 0xabcdef00 |
|
# Test Word Logical Shift Left by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr2, r2 |
tmcrr wr1, r3, r4 |
|
wsllwg wr1, wr0, wcgr2 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr2 |
tmrrc r3, r4, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x23456780 |
test_h_gr r4, 0xabcdef00 |
|
# Test Double Word Logical Shift Left |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdefc |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wslld wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdefc |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x23456780 |
test_h_gr r5, 0xabcdefc1 |
|
# Test Double Word Logical Shift Left by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdefc |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr3, r2 |
tmcrr wr1, r3, r4 |
|
wslldg wr1, wr0, wcgr3 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr3 |
tmrrc r3, r4, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdefc |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x23456780 |
test_h_gr r4, 0xabcdefc1 |
|
pass |
/iwmmxt/tmiaph.cgs
0,0 → 1,35
# Intel(r) Wireless MMX(tm) technology testcase for TMIAPH |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global tmiaph |
tmiaph: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Multilply Accumulate |
|
mvi_h_gr r0, 0x11223344 |
mvi_h_gr r1, 0x55667788 |
mvi_h_gr r2, 0x12345678 |
mvi_h_gr r3, 0x9abcdef0 |
|
tmcrr wr0, r0, r1 |
|
tmiaph wr0, r2, r3 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0xfec3f9f4 |
test_h_gr r1, 0x55667787 |
test_h_gr r2, 0x12345678 |
test_h_gr r3, 0x9abcdef0 |
|
pass |
/iwmmxt/textrm.cgs
0,0 → 1,113
# Intel(r) Wireless MMX(tm) technology testcase for TEXTRM |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global textrm |
textrm: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned Byte Wide Extraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
textrmub r2, wr0, #3 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x00000012 |
|
# Test Signed Byte Wide Extraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
textrmsb r2, wr0, #4 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0xfffffff0 |
|
# Test Unsigned Half Word Wide Extraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
textrmuh r2, wr0, #3 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x00009abc |
|
# Test Signed Half Word Wide Extraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
textrmsh r2, wr0, #1 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x00001234 |
|
# Test Unsigned Word Wide Extraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
textrmuw r2, wr0, #0 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x12345678 |
|
# Test Signed Word Wide Extraction |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
textrmsw r2, wr0, #1 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x9abcdef0 |
|
pass |
/iwmmxt/wavg2.cgs
0,0 → 1,121
# Intel(r) Wireless MMX(tm) technology testcase for WAVG2 |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wavg2 |
wavg2: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Byte Wide Averaging |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wavg2b wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x11223344 |
test_h_gr r5, 0x5e6f8089 |
|
# Test Byte Wide Averaging with Rounding |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wavg2br wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x12233445 |
test_h_gr r5, 0x5e6f8089 |
|
# Test Half Word Wide Averaging |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wavg2h wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x11a233c4 |
test_h_gr r5, 0x5e6f8089 |
|
# Test Half Word Wide Averaging with Rounding |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wavg2hr wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x11a333c5 |
test_h_gr r5, 0x5e6f8089 |
|
pass |
/iwmmxt/wmac.cgs
0,0 → 1,121
# Intel(r) Wireless MMX(tm) technology testcase for WMAC |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wmac |
wmac: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned, Multiply Accumulate, Non-zeroing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0x33333333 |
mvi_h_gr r5, 0x44444444 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmacu wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x6c889377 |
test_h_gr r5, 0x44444444 |
|
# Test Unsigned, Multiply Accumulate, Zeroing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0x33333333 |
mvi_h_gr r5, 0x44444444 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmacuz wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x39556044 |
test_h_gr r5, 0x00000000 |
|
# Test Signed, Multiply Accumulate, Non-zeroing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0x33333333 |
mvi_h_gr r5, 0x44444444 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmacs wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x28449377 |
test_h_gr r5, 0x44444444 |
|
# Test Signed, Multiply Accumulate, Zeroing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0x33333333 |
mvi_h_gr r5, 0x44444444 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmacsz wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0xf5116044 |
test_h_gr r5, 0xffffffff |
|
pass |
/iwmmxt/wsrl.cgs
0,0 → 1,167
# Intel(r) Wireless MMX(tm) technology testcase for WSRL |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wsrl |
wsrl: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Halfword Logical Shift Right |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsrlh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01230567 |
test_h_gr r5, 0x09ab0def |
|
# Test Halfword Logical Shift Right by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr1, r2 |
tmcrr wr1, r3, r4 |
|
wsrlhg wr1, wr0, wcgr1 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr1 |
tmrrc r3, r4, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x01230567 |
test_h_gr r4, 0x09ab0def |
|
# Test Word Logical Shift Right |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsrlw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0x01234567 |
test_h_gr r5, 0x09abcdef |
|
# Test Word Logical Shift Right by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr2, r2 |
tmcrr wr1, r3, r4 |
|
wsrlwg wr1, wr0, wcgr2 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr2 |
tmrrc r3, r4, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x01234567 |
test_h_gr r4, 0x09abcdef |
|
# Test Double Word Logical Shift Right |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdefc |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0x11111111 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsrld wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdefc |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0x11111111 |
test_h_gr r4, 0xc1234567 |
test_h_gr r5, 0x09abcdef |
|
# Test Double Word Logical Shift Right by CG register |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdefc |
mvi_h_gr r2, 0x11111104 |
mvi_h_gr r3, 0 |
mvi_h_gr r4, 0 |
|
tmcrr wr0, r0, r1 |
tmcr wcgr3, r2 |
tmcrr wr1, r3, r4 |
|
wsrldg wr1, wr0, wcgr3 |
|
tmrrc r0, r1, wr0 |
tmrc r2, wcgr3 |
tmrrc r3, r4, wr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdefc |
test_h_gr r2, 0x11111104 |
test_h_gr r3, 0xc1234567 |
test_h_gr r4, 0x09abcdef |
|
pass |
/iwmmxt/waligni.cgs
0,0 → 1,43
# Intel(r) Wireless MMX(tm) technology testcase for WALIGNI |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global waligni |
waligni: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test 2 byte align |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
waligni wr2, wr0, wr1, #2 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0xdef01234 |
test_h_gr r5, 0x11119abc |
|
pass |
/iwmmxt/wmadd.cgs
0,0 → 1,69
# Intel(r) Wireless MMX(tm) technology testcase for WMADD |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wmadd |
wmadd: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned, Multiply Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmaddu wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x06fa5f6c |
test_h_gr r5, 0x325b00d8 |
|
# Test Signed, Multiply Addition |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wmadds wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x06fa5f6c |
test_h_gr r5, 0xee1700d8 |
|
pass |
/iwmmxt/wcmpeq.cgs
0,0 → 1,95
# Intel(r) Wireless MMX(tm) technology testcase for WCMPEQ |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wcmpeq |
wcmpeq: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Byte Wide Compare Equal To |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x9abcde00 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wcmpeqb wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x9abcde00 |
test_h_gr r4, 0x00000000 |
test_h_gr r5, 0xffffffff |
|
# Test Half Word Wide Compare Equal To |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x9abcde00 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wcmpeqh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x9abcde00 |
test_h_gr r4, 0x00000000 |
test_h_gr r5, 0xffffffff |
|
# Test Word Wide Compare Equal To |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x9abcde00 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wcmpeqw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x9abcde00 |
test_h_gr r4, 0x00000000 |
test_h_gr r5, 0xffffffff |
|
pass |
/iwmmxt/testutils.inc
0,0 → 1,118
# r0-r3 are used as tmps, consider them call clobbered by these macros. |
# This uses the angel rom monitor calls. |
# ??? How do we use the \@ facility of .macros ??? |
# @ is the comment char! |
|
.macro mvi_h_gr reg, val |
ldr \reg,[pc] |
b . + 8 |
.word \val |
.endm |
|
.macro mvaddr_h_gr reg, addr |
ldr \reg,[pc] |
b . + 8 |
.word \addr |
.endm |
|
.macro start |
.data |
failmsg: |
.asciz "fail\n" |
passmsg: |
.asciz "pass\n" |
.text |
|
do_pass: |
ldr r1, passmsg_addr |
mov r0, #4 |
swi #0x123456 |
exit 0 |
passmsg_addr: |
.word passmsg |
|
do_fail: |
ldr r1, failmsg_addr |
mov r0, #4 |
swi #0x123456 |
exit 1 |
failmsg_addr: |
.word failmsg |
|
.global _start |
_start: |
.endm |
|
# *** Other macros know pass/fail are 4 bytes in size! Yuck. |
|
.macro pass |
b do_pass |
.endm |
|
.macro fail |
b do_fail |
.endm |
|
.macro exit rc |
# ??? This works with the ARMulator but maybe not others. |
#mov r0, #\rc |
#swi #1 |
# This seems to be portable (though it ignores rc). |
mov r0,#0x18 |
mvi_h_gr r1, 0x20026 |
swi #0x123456 |
# If that returns, punt with a sigill. |
stc 0,cr0,[r0] |
.endm |
|
# Other macros know this only clobbers r0. |
# WARNING: It also clobbers the condition codes (FIXME). |
.macro test_h_gr reg, val |
mvaddr_h_gr r0, \val |
cmp \reg, r0 |
beq . + 8 |
fail |
.endm |
|
.macro mvi_h_cnvz c, n, v, z |
mov r0, #0 |
.if \c |
orr r0, r0, #0x20000000 |
.endif |
.if \n |
orr r0, r0, #0x80000000 |
.endif |
.if \v |
orr r0, r0, #0x10000000 |
.endif |
.if \z |
orr r0, r0, #0x40000000 |
.endif |
mrs r1, cpsr |
bic r1, r1, #0xf0000000 |
orr r1, r1, r0 |
msr cpsr, r1 |
# ??? nops needed |
.endm |
|
# ??? Preserve condition codes? |
.macro test_h_cnvz c, n, v, z |
mov r0, #0 |
.if \c |
orr r0, r0, #0x20000000 |
.endif |
.if \n |
orr r0, r0, #0x80000000 |
.endif |
.if \v |
orr r0, r0, #0x10000000 |
.endif |
.if \z |
orr r0, r0, #0x40000000 |
.endif |
mrs r1, cpsr |
and r1, r1, #0xf0000000 |
cmp r0, r1 |
beq . + 8 |
fail |
.endm |
/iwmmxt/wsad.cgs
0,0 → 1,121
# Intel(r) Wireless MMX(tm) technology testcase for WSAD |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wsad |
wsad: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Byte wide absolute accumulation |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0x22222222 |
mvi_h_gr r5, 0x22222222 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsadb wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x2222258e |
test_h_gr r5, 0x00000000 |
|
# Test Byte wide absolute accumulation with zeroing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0x22222222 |
mvi_h_gr r5, 0x22222222 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsadbz wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x0000036c |
test_h_gr r5, 0x00000000 |
|
# Test Halfword wide absolute accumulation |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0x22222222 |
mvi_h_gr r5, 0x22222222 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsadh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x22239e14 |
test_h_gr r5, 0x00000000 |
|
# Test Halfword wide absolute accumulation with zeroing |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0x22222222 |
mvi_h_gr r5, 0x22222222 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wsadhz wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0x00017bf2 |
test_h_gr r5, 0x00000000 |
|
pass |
/iwmmxt/tinsr.cgs
0,0 → 1,65
# Intel(r) Wireless MMX(tm) technology testcase for TINSR |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global tinsr |
tinsr: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Byte Wide Insertion |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
tinsrb wr0, r2, #3 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0xff345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x111111ff |
|
# Test Half Word Wide Insertion |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
tinsrh wr0, r2, #2 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abc11ff |
test_h_gr r2, 0x111111ff |
|
# Test Word Wide Insertion |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x111111ff |
|
tmcrr wr0, r0, r1 |
|
tinsrw wr0, r2, #1 |
|
tmrrc r0, r1, wr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x111111ff |
test_h_gr r2, 0x111111ff |
|
pass |
/iwmmxt/wcmpgt.cgs
0,0 → 1,173
# Intel(r) Wireless MMX(tm) technology testcase for WCMPGT |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global wcmpgt |
wcmpgt: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test Unsigned Byte Wide Compare Greater Than |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wcmpgtub wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0xffffffff |
test_h_gr r5, 0xffffff00 |
|
# Test Signed Byte Wide Compare Greater Than |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wcmpgtsb wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0xffffffff |
test_h_gr r5, 0x00000000 |
|
# Test Unsigned Half Word Wide Compare Greater Than |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wcmpgtuh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0xffffffff |
test_h_gr r5, 0xffffffff |
|
# Test Signed Half Word Wide Compare Greater Than |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wcmpgtsh wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0xffffffff |
test_h_gr r5, 0x00000000 |
|
# Test Unsigned Word Wide Compare Greater Than |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wcmpgtuw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0xffffffff |
test_h_gr r5, 0xffffffff |
|
# Test Signed Word Wide Compare Greater Than |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcde00 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x22222222 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
|
wcmpgtsw wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcde00 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x22222222 |
test_h_gr r4, 0xffffffff |
test_h_gr r5, 0x00000000 |
|
pass |
/iwmmxt/walignr.cgs
0,0 → 1,137
# Intel(r) Wireless MMX(tm) technology testcase for WALIGNR |
# mach: xscale |
# as: -mcpu=xscale+iwmmxt |
|
.include "testutils.inc" |
|
start |
|
.global walignr |
walignr: |
# Enable access to CoProcessors 0 & 1 before |
# we attempt these instructions. |
|
mvi_h_gr r1, 3 |
mcr p15, 0, r1, cr15, cr1, 0 |
|
# Test 0 byte align |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
mvi_h_gr r6, 3 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
tmcr wcgr0, r6 |
|
walignr0 wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
tmrc r6, wcgr0 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0xbcdef012 |
test_h_gr r5, 0x1111119a |
test_h_gr r6, 3 |
|
# Test 1 byte align |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
mvi_h_gr r6, 4 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
tmcr wcgr1, r6 |
|
walignr1 wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
tmrc r6, wcgr1 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x9abcdef0 |
test_h_gr r5, 0x11111111 |
test_h_gr r6, 4 |
|
# Test 2 byte align |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
mvi_h_gr r6, 2 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
tmcr wcgr2, r6 |
|
walignr2 wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
tmrc r6, wcgr2 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0xdef01234 |
test_h_gr r5, 0x11119abc |
test_h_gr r6, 2 |
|
# Test 3 byte align |
|
mvi_h_gr r0, 0x12345678 |
mvi_h_gr r1, 0x9abcdef0 |
mvi_h_gr r2, 0x11111111 |
mvi_h_gr r3, 0x00000000 |
mvi_h_gr r4, 0 |
mvi_h_gr r5, 0 |
mvi_h_gr r6, 5 |
|
tmcrr wr0, r0, r1 |
tmcrr wr1, r2, r3 |
tmcrr wr2, r4, r5 |
tmcr wcgr3, r6 |
|
walignr3 wr2, wr0, wr1 |
|
tmrrc r0, r1, wr0 |
tmrrc r2, r3, wr1 |
tmrrc r4, r5, wr2 |
tmrc r6, wcgr3 |
|
test_h_gr r0, 0x12345678 |
test_h_gr r1, 0x9abcdef0 |
test_h_gr r2, 0x11111111 |
test_h_gr r3, 0x00000000 |
test_h_gr r4, 0x119abcde |
test_h_gr r5, 0x00111111 |
test_h_gr r6, 5 |
|
pass |
/swpb.cgs
0,0 → 1,12
# arm testcase for swpb${cond}b $rd,$rm,[$rn] |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global swpb |
swpb: |
swpb0b pc,pc,[pc] |
|
pass |
/misc.exp
0,0 → 1,20
# Miscellaneous ARM simulator testcases |
|
if { [istarget arm*-*-*] || [istarget thumb*-*-*] || [istarget xscale*-*-*] } { |
# load support procs |
# load_lib cgen.exp |
|
# all machines |
set all_machs "arm7tdmi" |
|
# The .ms suffix is for "miscellaneous .s". |
foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { |
# If we're only testing specific files and this isn't one of them, |
# skip it. |
if ![runtest_file_p $runtests $src] { |
continue |
} |
|
run_sim_test $src $all_machs |
} |
} |
/cmn.cgs
0,0 → 1,36
# arm testcase for cmn${cond}${set-cc?} $rn,$imm12 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global cmn_imm |
cmn_imm: |
cmn00 pc,0 |
|
pass |
# arm testcase for cmn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global cmn_reg_imm_shift |
cmn_reg_imm_shift: |
cmn00 pc,pc,pc,lsl 0 |
|
pass |
# arm testcase for cmn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global cmn_reg_reg_shift |
cmn_reg_reg_shift: |
cmn00 pc,pc,pc,lsl pc |
|
pass |
/cmp.cgs
0,0 → 1,36
# arm testcase for cmp${cond}${set-cc?} $rn,$imm12 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global cmp_imm |
cmp_imm: |
cmp00 pc,0 |
|
pass |
# arm testcase for cmp$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global cmp_reg_imm_shift |
cmp_reg_imm_shift: |
cmp00 pc,pc,pc,lsl 0 |
|
pass |
# arm testcase for cmp$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global cmp_reg_reg_shift |
cmp_reg_reg_shift: |
cmp00 pc,pc,pc,lsl pc |
|
pass |
/allinsn.exp
0,0 → 1,28
# ARM simulator testsuite. |
|
if { [istarget arm*-*-*] || [istarget xscale*-*-*] } { |
# load support procs (none yet) |
# load_lib cgen.exp |
|
# all machines |
set all_machs "xscale" |
|
if [is_remote host] { |
remote_download host $srcdir/$subdir/testutils.inc |
} |
|
# The .cgs suffix is for "cgen .s". |
foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { |
# If we're only testing specific files and this isn't one of them, |
# skip it. |
if ![runtest_file_p $runtests $src] { |
continue |
} |
|
run_sim_test $src $all_machs |
} |
|
if [is_remote host] { |
remote_file host delete testutils.inc |
} |
} |
/strh.cgs
0,0 → 1,132
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strh_post_dec_imm_offset |
strh_post_dec_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strh_post_dec_reg_offset |
strh_post_dec_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strh_post_inc_imm_offset |
strh_post_inc_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strh_post_inc_reg_offset |
strh_post_inc_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strh_pre_dec_imm_offset |
strh_pre_dec_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strh_pre_dec_reg_offset |
strh_pre_dec_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strh_pre_dec_wb_imm_offset |
strh_pre_dec_wb_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strh_pre_dec_wb_reg_offset |
strh_pre_dec_wb_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strh_pre_inc_imm_offset |
strh_pre_inc_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strh_pre_inc_reg_offset |
strh_pre_inc_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strh_pre_inc_wb_imm_offset |
strh_pre_inc_wb_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global strh_pre_inc_wb_reg_offset |
strh_pre_inc_wb_reg_offset: |
|
pass |
/b.cgs
0,0 → 1,261
# arm testcase for b$cond $offset24 |
# mach: all |
|
# ??? Still need to test edge cases. |
|
.include "testutils.inc" |
|
start |
|
.global b |
b: |
|
# b foo |
|
b balways1 |
fail |
balways1: |
|
# beq foo |
|
mvi_h_gr r4,4 |
mvi_h_gr r5,4 |
cmp r4,r5 |
beq beq1 |
fail |
beq1: |
mvi_h_gr r5,5 |
cmp r4,r5 |
beq beq2 |
b beq3 |
beq2: |
fail |
beq3: |
|
# bne foo |
|
mvi_h_gr r4,4 |
mvi_h_gr r5,5 |
cmp r4,r5 |
bne bne1 |
fail |
bne1: |
mvi_h_gr r5,4 |
cmp r4,r5 |
bne bne2 |
b bne3 |
bne2: |
fail |
bne3: |
|
# bcs foo |
|
mvi_h_cnvz 1,0,0,0 |
bcs bcs1 |
fail |
bcs1: |
mvi_h_cnvz 0,0,0,0 |
bcs bcs2 |
b bcs3 |
bcs2: |
fail |
bcs3: |
|
# bcc foo |
|
mvi_h_cnvz 0,0,0,0 |
bcc bcc1 |
fail |
bcc1: |
mvi_h_cnvz 1,0,0,0 |
bcc bcc2 |
b bcc3 |
bcc2: |
fail |
bcc3: |
|
# bmi foo |
|
mvi_h_cnvz 0,1,0,0 |
bmi bmi1 |
fail |
bmi1: |
mvi_h_cnvz 0,0,0,0 |
bmi bmi2 |
b bmi3 |
bmi2: |
fail |
bmi3: |
|
# bpl foo |
|
mvi_h_cnvz 0,0,0,0 |
bpl bpl1 |
fail |
bpl1: |
mvi_h_cnvz 0,1,0,0 |
bpl bpl2 |
b bpl3 |
bpl2: |
fail |
bpl3: |
|
# bvs foo |
|
mvi_h_cnvz 0,0,1,0 |
bvs bvs1 |
fail |
bvs1: |
mvi_h_cnvz 0,0,0,0 |
bvs bvs2 |
b bvs3 |
bvs2: |
fail |
bvs3: |
|
# bvc foo |
|
mvi_h_cnvz 0,0,0,0 |
bvc bvc1 |
fail |
bvc1: |
mvi_h_cnvz 0,0,1,0 |
bvc bvc2 |
b bvc3 |
bvc2: |
fail |
bvc3: |
|
# bhi foo |
|
mvi_h_gr r4,5 |
mvi_h_gr r5,4 |
cmp r4,r5 |
bhi bhi1 |
fail |
bhi1: |
mvi_h_gr r5,5 |
cmp r4,r5 |
bhi bhi2 |
b bhi3 |
bhi2: |
fail |
bhi3: |
mvi_h_gr r5,6 |
cmp r4,r5 |
bhi bhi4 |
b bhi5 |
bhi4: |
fail |
bhi5: |
|
# bls foo |
|
mvi_h_gr r4,4 |
mvi_h_gr r5,5 |
cmp r4,r5 |
bls bls1 |
fail |
bls1: |
mvi_h_gr r5,4 |
cmp r4,r5 |
bls bls2 |
fail |
bls2: |
mvi_h_gr r5,3 |
cmp r4,r5 |
bls bls3 |
b bls4 |
bls3: |
fail |
bls4: |
|
# bge foo |
|
mvi_h_gr r4,4 |
mvi_h_gr r5,4 |
cmp r4,r5 |
bge bge1 |
fail |
bge1: |
mvi_h_gr r5,3 |
cmp r4,r5 |
bge bge2 |
fail |
bge2: |
mvi_h_gr r5,5 |
cmp r4,r5 |
bge bge3 |
b bge4 |
bge3: |
fail |
bge4: |
|
# blt foo |
|
mvi_h_gr r4,4 |
mvi_h_gr r5,5 |
cmp r4,r5 |
blt blt1 |
fail |
blt1: |
mvi_h_gr r5,4 |
cmp r4,r5 |
blt blt2 |
b blt3 |
blt2: |
fail |
blt3: |
mvi_h_gr r5,3 |
cmp r4,r5 |
blt blt4 |
b blt5 |
blt4: |
fail |
blt5: |
|
# bgt foo |
|
mvi_h_gr r4,4 |
mvi_h_gr r5,3 |
cmp r4,r5 |
bgt bgt1 |
fail |
bgt1: |
mvi_h_gr r5,4 |
cmp r4,r5 |
bgt bgt2 |
b bgt3 |
bgt2: |
fail |
bgt3: |
mvi_h_gr r5,5 |
cmp r4,r5 |
bgt bgt4 |
b bgt5 |
bgt4: |
fail |
bgt5: |
|
# ble foo |
|
mvi_h_gr r4,4 |
mvi_h_gr r5,4 |
cmp r4,r5 |
ble ble1 |
fail |
ble1: |
mvi_h_gr r5,5 |
cmp r4,r5 |
ble ble2 |
fail |
ble2: |
mvi_h_gr r5,3 |
cmp r4,r5 |
ble ble3 |
b ble4 |
ble3: |
fail |
ble4: |
|
pass |
/ldrb.cgs
0,0 → 1,192
# arm testcase for ldr${cond}b $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrb_post_dec_imm_offset |
ldrb_post_dec_imm_offset: |
ldr0b pc,??? |
|
pass |
# arm testcase for ldr${cond}bt $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrb_post_dec_nonpriv_imm_offset |
ldrb_post_dec_nonpriv_imm_offset: |
ldr0bt pc,??? |
|
pass |
# arm testcase for ldr${cond}bt $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrb_post_dec_nonpriv_reg_offset |
ldrb_post_dec_nonpriv_reg_offset: |
ldr0bt pc,??? |
|
pass |
# arm testcase for ldr${cond}b $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrb_post_dec_reg_offset |
ldrb_post_dec_reg_offset: |
ldr0b pc,??? |
|
pass |
# arm testcase for ldr${cond}b $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrb_post_inc_imm_offset |
ldrb_post_inc_imm_offset: |
ldr0b pc,??? |
|
pass |
# arm testcase for ldr${cond}bt $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrb_post_inc_nonpriv_imm_offset |
ldrb_post_inc_nonpriv_imm_offset: |
ldr0bt pc,??? |
|
pass |
# arm testcase for ldr${cond}bt $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrb_post_inc_nonpriv_reg_offset |
ldrb_post_inc_nonpriv_reg_offset: |
ldr0bt pc,??? |
|
pass |
# arm testcase for ldr${cond}b $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrb_post_inc_reg_offset |
ldrb_post_inc_reg_offset: |
ldr0b pc,??? |
|
pass |
# arm testcase for ldr${cond}b $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrb_pre_dec_imm_offset |
ldrb_pre_dec_imm_offset: |
ldr0b pc,??? |
|
pass |
# arm testcase for ldr${cond}b $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrb_pre_dec_reg_offset |
ldrb_pre_dec_reg_offset: |
ldr0b pc,??? |
|
pass |
# arm testcase for ldr${cond}b $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrb_pre_dec_wb_imm_offset |
ldrb_pre_dec_wb_imm_offset: |
ldr0b pc,??? |
|
pass |
# arm testcase for ldr${cond}b $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrb_pre_dec_wb_reg_offset |
ldrb_pre_dec_wb_reg_offset: |
ldr0b pc,??? |
|
pass |
# arm testcase for ldr${cond}b $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrb_pre_inc_imm_offset |
ldrb_pre_inc_imm_offset: |
ldr0b pc,??? |
|
pass |
# arm testcase for ldr${cond}b $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrb_pre_inc_reg_offset |
ldrb_pre_inc_reg_offset: |
ldr0b pc,??? |
|
pass |
# arm testcase for ldr${cond}b $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrb_pre_inc_wb_imm_offset |
ldrb_pre_inc_wb_imm_offset: |
ldr0b pc,??? |
|
pass |
# arm testcase for ldr${cond}b $rd,??? |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrb_pre_inc_wb_reg_offset |
ldrb_pre_inc_wb_reg_offset: |
ldr0b pc,??? |
|
pass |
/eor.cgs
0,0 → 1,36
# arm testcase for eor$cond${set-cc?} $rd,$rn,$imm12 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global eor_imm |
eor_imm: |
eor00 pc,pc,0 |
|
pass |
# arm testcase for eor$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global eor_reg_imm_shift |
eor_reg_imm_shift: |
eor00 pc,pc,pc,lsl 0 |
|
pass |
# arm testcase for eor$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global eor_reg_reg_shift |
eor_reg_reg_shift: |
eor00 pc,pc,pc,lsl pc |
|
pass |
/rsb.cgs
0,0 → 1,36
# arm testcase for rsb$cond${set-cc?} $rd,$rn,$imm12 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global rsb_imm |
rsb_imm: |
rsb00 pc,pc,0 |
|
pass |
# arm testcase for rsb$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global rsb_reg_imm_shift |
rsb_reg_imm_shift: |
rsb00 pc,pc,pc,lsl 0 |
|
pass |
# arm testcase for rsb$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global rsb_reg_reg_shift |
rsb_reg_reg_shift: |
rsb00 pc,pc,pc,lsl pc |
|
pass |
/rsc.cgs
0,0 → 1,36
# arm testcase for rsc$cond${set-cc?} $rd,$rn,$imm12 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global rsc_imm |
rsc_imm: |
rsc00 pc,pc,0 |
|
pass |
# arm testcase for rsc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global rsc_reg_imm_shift |
rsc_reg_imm_shift: |
rsc00 pc,pc,pc,lsl 0 |
|
pass |
# arm testcase for rsc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global rsc_reg_reg_shift |
rsc_reg_reg_shift: |
rsc00 pc,pc,pc,lsl pc |
|
pass |
/adc.cgs
0,0 → 1,43
# arm testcase for adc |
# mach: all |
|
# ??? Unfinished, more tests needed. |
|
.include "testutils.inc" |
|
start |
|
# adc$cond${set-cc?} $rd,$rn,$imm12 |
|
.global adc_imm |
adc_imm: |
mvi_h_gr r4,1 |
mvi_h_cnvz 0,0,0,0 |
adc r5,r4,#1 |
test_h_cnvz 0,0,0,0 |
test_h_gr r5,2 |
|
# adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} |
|
.global adc_reg_imm_shift |
adc_reg_imm_shift: |
mvi_h_gr r4,1 |
mvi_h_gr r5,1 |
mvi_h_cnvz 0,0,0,0 |
adc r6,r4,r5,lsl #2 |
test_h_cnvz 0,0,0,0 |
test_h_gr r6,5 |
|
# adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} |
|
.global adc_reg_reg_shift |
adc_reg_reg_shift: |
mvi_h_gr r4,1 |
mvi_h_gr r5,1 |
mvi_h_gr r6,2 |
mvi_h_cnvz 0,0,0,0 |
adc r7,r4,r5,lsl r6 |
test_h_cnvz 0,0,0,0 |
test_h_gr r7,5 |
|
pass |
/add.cgs
0,0 → 1,43
# arm testcase for add |
# mach: all |
|
# ??? Unfinished, more tests needed. |
|
.include "testutils.inc" |
|
start |
|
# add$cond${set-cc?} $rd,$rn,$imm12 |
|
.global add_imm |
add_imm: |
mvi_h_gr r4,1 |
mvi_h_cnvz 0,0,0,0 |
add r5,r4,#1 |
test_h_cnvz 0,0,0,0 |
test_h_gr r5,2 |
|
# add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} |
|
.global add_reg_imm_shift |
add_reg_imm_shift: |
mvi_h_gr r4,1 |
mvi_h_gr r5,1 |
mvi_h_cnvz 0,0,0,0 |
add r6,r4,r5,lsl #2 |
test_h_cnvz 0,0,0,0 |
test_h_gr r6,5 |
|
# add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} |
|
.global add_reg_reg_shift |
add_reg_reg_shift: |
mvi_h_gr r4,1 |
mvi_h_gr r5,1 |
mvi_h_gr r6,2 |
mvi_h_cnvz 0,0,0,0 |
add r7,r4,r5,lsl r6 |
test_h_cnvz 0,0,0,0 |
test_h_gr r7,5 |
|
pass |
/ldrh.cgs
0,0 → 1,132
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrh_post_dec_imm_offset |
ldrh_post_dec_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrh_post_dec_reg_offset |
ldrh_post_dec_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrh_post_inc_imm_offset |
ldrh_post_inc_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrh_post_inc_reg_offset |
ldrh_post_inc_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrh_pre_dec_imm_offset |
ldrh_pre_dec_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrh_pre_dec_reg_offset |
ldrh_pre_dec_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrh_pre_dec_wb_imm_offset |
ldrh_pre_dec_wb_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrh_pre_dec_wb_reg_offset |
ldrh_pre_dec_wb_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrh_pre_inc_imm_offset |
ldrh_pre_inc_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrh_pre_inc_reg_offset |
ldrh_pre_inc_reg_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrh_pre_inc_wb_imm_offset |
ldrh_pre_inc_wb_imm_offset: |
|
pass |
# arm testcase for FIXME |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global ldrh_pre_inc_wb_reg_offset |
ldrh_pre_inc_wb_reg_offset: |
|
pass |
/sub.cgs
0,0 → 1,36
# arm testcase for sub$cond${set-cc?} $rd,$rn,$imm12 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global sub_imm |
sub_imm: |
sub00 pc,pc,0 |
|
pass |
# arm testcase for sub$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global sub_reg_imm_shift |
sub_reg_imm_shift: |
sub00 pc,pc,pc,lsl 0 |
|
pass |
# arm testcase for sub$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global sub_reg_reg_shift |
sub_reg_reg_shift: |
sub00 pc,pc,pc,lsl pc |
|
pass |
/teq.cgs
0,0 → 1,36
# arm testcase for teq${cond}${set-cc?} $rn,$imm12 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global teq_imm |
teq_imm: |
teq00 pc,0 |
|
pass |
# arm testcase for teq$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global teq_reg_imm_shift |
teq_reg_imm_shift: |
teq00 pc,pc,pc,lsl 0 |
|
pass |
# arm testcase for teq$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global teq_reg_reg_shift |
teq_reg_reg_shift: |
teq00 pc,pc,pc,lsl pc |
|
pass |
/mul.cgs
0,0 → 1,12
# arm testcase for mul$cond${set-cc?} ${mul-rd},$rm,$rs |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global mul |
mul: |
mul00 pc,pc,pc |
|
pass |
/testutils.inc
0,0 → 1,118
# r0-r3 are used as tmps, consider them call clobbered by these macros. |
# This uses the angel rom monitor calls. |
# ??? How do we use the \@ facility of .macros ??? |
# @ is the comment char! |
|
.macro mvi_h_gr reg, val |
ldr \reg,[pc] |
b . + 8 |
.word \val |
.endm |
|
.macro mvaddr_h_gr reg, addr |
ldr \reg,[pc] |
b . + 8 |
.word \addr |
.endm |
|
.macro start |
.data |
failmsg: |
.asciz "fail\n" |
passmsg: |
.asciz "pass\n" |
.text |
|
do_pass: |
ldr r1, passmsg_addr |
mov r0, #4 |
swi #0x123456 |
exit 0 |
passmsg_addr: |
.word passmsg |
|
do_fail: |
ldr r1, failmsg_addr |
mov r0, #4 |
swi #0x123456 |
exit 1 |
failmsg_addr: |
.word failmsg |
|
.global _start |
_start: |
.endm |
|
# *** Other macros know pass/fail are 4 bytes in size! Yuck. |
|
.macro pass |
b do_pass |
.endm |
|
.macro fail |
b do_fail |
.endm |
|
.macro exit rc |
# ??? This works with the ARMulator but maybe not others. |
#mov r0, #\rc |
#swi #1 |
# This seems to be portable (though it ignores rc). |
mov r0,#0x18 |
mvi_h_gr r1, 0x20026 |
swi #0x123456 |
# If that returns, punt with a sigill. |
stc 0,cr0,[r0] |
.endm |
|
# Other macros know this only clobbers r0. |
# WARNING: It also clobbers the condition codes (FIXME). |
.macro test_h_gr reg, val |
mvaddr_h_gr r0, \val |
cmp \reg, r0 |
beq . + 8 |
fail |
.endm |
|
.macro mvi_h_cnvz c, n, v, z |
mov r0, #0 |
.if \c |
orr r0, r0, #0x20000000 |
.endif |
.if \n |
orr r0, r0, #0x80000000 |
.endif |
.if \v |
orr r0, r0, #0x10000000 |
.endif |
.if \z |
orr r0, r0, #0x40000000 |
.endif |
mrs r1, cpsr |
bic r1, r1, #0xf0000000 |
orr r1, r1, r0 |
msr cpsr, r1 |
# ??? nops needed |
.endm |
|
# ??? Preserve condition codes? |
.macro test_h_cnvz c, n, v, z |
mov r0, #0 |
.if \c |
orr r0, r0, #0x20000000 |
.endif |
.if \n |
orr r0, r0, #0x80000000 |
.endif |
.if \v |
orr r0, r0, #0x10000000 |
.endif |
.if \z |
orr r0, r0, #0x40000000 |
.endif |
mrs r1, cpsr |
and r1, r1, #0xf0000000 |
cmp r0, r1 |
beq . + 8 |
fail |
.endm |
/msr.cgs
0,0 → 1,24
# arm testcase for msr$cond cpsr,$rm |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global msr_c |
msr_c: |
msr0 cpsr,pc |
|
pass |
# arm testcase for msr$cond spsr,$rm |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global msr_s |
msr_s: |
msr0 spsr,pc |
|
pass |
/mov.cgs
0,0 → 1,36
# arm testcase for mov$cond${set-cc?} $rd,$imm12 |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global mov_imm |
mov_imm: |
mov00 pc,0 |
|
pass |
# arm testcase for mov$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global mov_reg_imm_shift |
mov_reg_imm_shift: |
mov00 pc,pc,pc,lsl 0 |
|
pass |
# arm testcase for mov$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global mov_reg_reg_shift |
mov_reg_reg_shift: |
mov00 pc,pc,pc,lsl pc |
|
pass |
/misaligned2.ms
0,0 → 1,60
# Test LDR instructions with offsets misaligned by 2 bytes. |
# mach(): all |
|
.macro invalid |
# This is "undefined" but it's not properly decoded yet. |
.word 0x07ffffff |
# This is stc which isn't recognized yet. |
stc 0,cr0,[r0] |
.endm |
|
.global _start |
_start: |
# Run some simple insns to confirm the engine is at least working. |
nop |
|
# Skip over output text. |
bl do_test |
|
pass: |
.asciz "pass\n" |
.p2align 2 |
|
do_test: |
mov r4, r14 |
bl continue |
word1: |
.word 0x5555 |
continue: |
ldr r6, [r14, #2] |
ldr r7, word2 |
cmp r6, r7 |
# Failed. |
bne done |
|
output_next: |
# Output a character (in arm mode). |
mov r0,#3 |
mov r1,r4 |
swi #0x123456 |
|
# Load next character, see if done. |
add r4,r4,#1 |
sub r3,r3,r3 |
ldrb r5,[r4,r3] |
teq r5,#0 |
bne output_next |
|
done: |
mov r0,#0x18 |
ldr r1,exit_code |
swi #0x123456 |
|
# If that fails, try to die with an invalid insn. |
invalid |
|
exit_code: |
.word 0x20026 |
|
word2: |
.word 0x55550000 |
/and.cgs
0,0 → 1,43
# arm testcase for and |
# mach: all |
|
# ??? Unfinished, more tests needed. |
|
.include "testutils.inc" |
|
start |
|
# and$cond${set-cc?} $rd,$rn,$imm12 |
|
.global and_imm |
and_imm: |
mvi_h_gr r4,1 |
mvi_h_cnvz 0,0,0,0 |
and r5,r4,#1 |
test_h_cnvz 0,0,0,0 |
test_h_gr r5,1 |
|
# and$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm} |
|
.global and_reg_imm_shift |
and_reg_imm_shift: |
mvi_h_gr r4,1 |
mvi_h_gr r5,1 |
mvi_h_cnvz 0,0,0,0 |
and r6,r4,r5,lsl #1 |
test_h_cnvz 0,0,0,0 |
test_h_gr r6,0 |
|
# and$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg} |
|
.global and_reg_reg_shift |
and_reg_reg_shift: |
mvi_h_gr r4,1 |
mvi_h_gr r5,1 |
mvi_h_gr r6,1 |
mvi_h_cnvz 0,0,0,0 |
and r7,r4,r5,lsl r6 |
test_h_cnvz 0,0,0,0 |
test_h_gr r7,0 |
|
pass |
/swi.cgs
0,0 → 1,12
# arm testcase for swi$cond ${swi-comment} |
# mach: unfinished |
|
.include "testutils.inc" |
|
start |
|
.global swi |
swi: |
swi0 0 |
|
pass |