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/openrisc/tags/gnu-src/newlib-1.18.0/newlib-1.18.0-or32-1.0rc1/newlib/libc/sys/a29khif/sys
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/fpsymbol.h

0,0 → 1,2970

fpsymbol.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: proreg.h =================================================================== --- proreg.h (nonexistent) +++ proreg.h (revision 345) @@ -0,0 +1,60 @@ +; @(#)proreg.h 1.3 90/10/14 20:56:11, AMD +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright 1989, 1990 Advanced Micro Devices, Inc. +; +; This software is the property of Advanced Micro Devices, Inc (AMD) which +; specifically grants the user the right to modify, use and distribute this +; software provided this notice is not removed or altered. All other rights +; are reserved by AMD. +; +; AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS +; SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL +; DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR +; USE OF THIS SOFTWARE. +; +; So that all may benefit from your experience, please report any problems +; or suggestions about this software to the 29K Technical Support Center at +; 800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131 in the UK, or +; 0031-11-1129 in Japan, toll free. The direct dial number is 512-462-4118. +; +; Advanced Micro Devices, Inc. +; 29K Support Products +; Mail Stop 573 +; 5900 E. Ben White Blvd. +; Austin, TX 78741 +; 800-292-9263 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; +; proreg.h +; + ; 16 function value return regs + .reg v0, gr96 + .reg v1, gr97 + .reg v2, gr98 + .reg v3, gr99 + .reg v4, gr100 + .reg v5, gr101 + .reg v6, gr102 + .reg v7, gr103 + .reg v8, gr104 + .reg v9, gr105 + .reg v10, gr106 + .reg v11, gr107 + .reg v12, gr108 + .reg v13, gr109 + .reg v14, gr110 + .reg v15, gr111 +; + .reg rsp, gr1 ; Register Stack Pointer + .reg ret, gr96 ; First word of return value + .reg rp0, gr112 ; Reserved for Programmer, #0 + .reg rp1, gr113 ; Reserved for Programmer, #1 + .reg rp2, gr114 ; Reserved for Programmer, #2 + .reg rp3, gr115 ; Reserved for Programmer, #3 + .reg tav, gr121 ; Temporary, Argument for Trap Handlers + .reg tpc, gr122 ; Temporary, Return PC for Trap Handlers + .reg lrp, gr123 ; Large Return Pointer + .reg slp, gr124 ; Static Link Pointer + .reg msp, gr125 ; Memory Stack Pointer + .reg rab, gr126 ; Register Allocate Bound + .reg rfb, gr127 ; Register Free Bound

proreg.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: intrinsi.h =================================================================== --- intrinsi.h (nonexistent) +++ intrinsi.h (revision 345) @@ -0,0 +1,457 @@ +; @(#)intrinsi.h 1.4 90/10/14 20:56:06, Copyright 1988, 1989, 1990 AMD +; start of file intrinsi.h +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright 1990 Advanced Micro Devices, Inc. +; +; This software is the property of Advanced Micro Devices, Inc (AMD) which +; specifically grants the user the right to modify, use and distribute this +; software provided this notice is not removed or altered. All other rights +; are reserved by AMD. +; +; AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS +; SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL +; DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR +; USE OF THIS SOFTWARE. +; +; So that all may benefit from your experience, please report any problems +; or suggestions about this software to the 29K Technical Support Center at +; 800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131 in the UK, or +; 0031-11-1129 in Japan, toll free. The direct dial number is 512-462-4118. +; +; Advanced Micro Devices, Inc. +; 29K Support Products +; Mail Stop 573 +; 5900 E. Ben White Blvd. +; Austin, TX 78741 +; 800-292-9263 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; +; + .title "QTC Intrinsics Header file" +; +; Floating point library package for AMD 29000 family +; +; Copyright 1988 Advanced Micro Devices, Inc. +; +; All rights reserved +; +; Developed for AMD by Quantitative Technology Corporation +; 8700 SW Creekside Place Suite D +; Beaverton OR 97005 +; (503) 626-3081 +; +; Version information : +; +; Revision 1.6 89/06/29 16:08:51 jimh +; Fixed two bugs regarding compatiblility with the fpsymbol file. The +; definitions of ROUND_TO_PLUS/MINUS_INFINITY were reversed. Set_Rounding +; _Mode was fixed to set the local copy (29000 resident) of rounding mode +; in 29027 mode. +; +; +; Revision 1.5 89/04/17 11:20:49 jim +; replaced emfsr and emtsr macro calls with mfsr and mtsr instructions. +; +; Revision 1.4 89/02/24 15:18:04 jimh +; Added the definitions of FP_ENV_MODE_1_DEFAULT, FP_ENV_MODE_2_DEFAULT, +; FP_FLAGS_DEFAULT. +; Added macro clear_Flags. +; Changed the operation of set_Invalid_Op_flag, set_Reserved_Op_flag. +; +; Revision 1.3 89/02/01 18:30:12 jimh +; Changed the way set_Rounding_Mode, extract_Rounding_Mode, set_Invalid_Op_flag +; and set_Reserved_Op_flag are done. Changed save_FP_regs. +; +; Revision 1.2 89/01/31 10:01:54 jimh +; Updated to the new standard. This includes moving in register +; definitions, changing old symbols to reflect those in fpsymbol.h, +; and changing the include file to smartmac.h. +; +; + .include "../traps/fpenv.h" ; RPD 8/21/89 + .include "sys/smartmac.h" + + .equ DOUBLE_EXP_WIDTH, 11 + .equ DOUBLE_EXTENDED_WIDTH, 56 + + .equ SIGNED, 0 + .equ UNSIGNED, 1 + + .equ ROUND_TO_NEAREST, 0 + .equ ROUND_TO_MINUS_INFINITY, 1 + .equ ROUND_TO_PLUS_INFINITY, 2 + .equ ROUND_TO_ZERO, 3 + .equ ROUNDING_MODE_POSITION, 14 + + .equ FORMAT_INTEGER, 0 + .equ FORMAT_SINGLE, 1 + .equ FORMAT_DOUBLE, 2 + + .equ DOUBLE_MSB_MASK,0x00080000 +; +; The following are definitions used in the smart macro package, defining +; the 29000 shadow registers for the floating-point register file, and +; some temporary registers used during the library routines +; + .reg FP0, gr96 + .reg FP1, gr98 + .reg FP2, gr100 + .reg FP3, gr102 + .reg FP4, gr104 + .reg FP5, gr106 + .reg FP6, gr108 + .reg FP7, gr110 +; +; GR60 through GR6F are used to return the value of a function +; + .reg rtn0, gr96 + .reg rtn1, gr97 + .reg rtn2, gr98 + .reg rtn3, gr99 + .reg rtn4, gr100 + .reg rtn5, gr101 + .reg rtn6, gr102 + .reg rtn7, gr103 + .reg rtn8, gr104 + .reg rtn9, gr105 + .reg rtn10, gr106 + .reg rtn11, gr107 + .reg rtn12, gr108 + .reg rtn13, gr109 + .reg rtn14, gr110 + .reg rtn15, gr111 +; +; GR74..GR78 (116-120) - temporaries +; + .reg t0, gr116 + .reg t1, gr117 + .reg t2, gr118 + .reg t3, gr119 + .reg t4, gr120 +; +; FP_ENV_MODE_1 and FP_ENV_MODE_2 are based on 64-bit 29027 Mode register, +; and thus the fpsymbol.h CP_ constants may be used directly. +; +; FP_ENV_MODE_1 (Bits 0-31) +; +; 0-3 - floating-point format select, always 0 +; 4 - Saturate enable +; 5 - IEEE Affine/Projective mode (ignored by traps code) +; 6 - IEEE Trap enable +; 7 - IEEE Sudden underflow / FP Environment Fast Float Select +; 8-10 - ignored +; 11 - Integer multiplication signed/unsigned select +; 12-13 - Integer multiplication format adjust +; 14-16 - Rounding mode select +; 17-19 - ignored +; 20 - Pipeline mode select +; 21 - ignored +; 22 - Invalid operation mask bit +; 23 - Reserved operand mask bit +; 24 - Overflow mask bit +; 25 - Underflow mask bit +; 26 - Inexact result mask bit +; 27 - Zero mask bit +; 28-31 - ignored +; +; FP_ENV_MODE_2 (Bits 32-63) [Hardware configuration register, rarely modified] +; +; 32-35 - Pipeline timer count +; 36-39 - Timer count for multiply-accumulate operation +; 40-43 - Timer count for save state transaction request +; 44-63 - ignored +; +; FP_ENV_MODE_1 definitions +; + .set FP_ENV_MODE_1_DEFAULT, CP_PFF_EQ_IEEE + .set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_AFF_EQ_IEEE + .set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_AFFINE_MODE + .set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_IEEE_TRAPS_DISABLED + .set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_IEEE_GRADUAL_UFLOW_MODE + .set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_UNSIGNED_INT_MPY_MODE + .set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_MF_EQ_LSBS + .set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_RMS_EQ_NEAREST + .set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_FLOWTHROUGH_MODE + .set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_INVALID_OP_EXCP_MASK + .set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_RESERVED_OP_EXCP_MASK + .set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_OVERFLOW_EXCP_MASK + .set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_UNDERFLOW_EXCP_MASK + .set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_INEXACT_EXCP_MASK + .set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_ZERO_EXCP_MASK +; +; FP_ENV_MODE_2 definitions +; + .set FP_ENV_MODE_2_DEFAULT, CP_PLTC_EQ_6 + .set FP_ENV_MODE_2_DEFAULT,FP_ENV_MODE_2_DEFAULT|CP_MATC_EQ_9 + .set FP_ENV_MODE_2_DEFAULT,FP_ENV_MODE_2_DEFAULT|CP_MVTC_EQ_3 + .set FP_ENV_MODE_2_DEFAULT,FP_ENV_MODE_2_DEFAULT|CP_NORMAL_DRDY_MODE + .set FP_ENV_MODE_2_DEFAULT,FP_ENV_MODE_2_DEFAULT|CP_HALT_ON_ERROR_DISABLED + .set FP_ENV_MODE_2_DEFAULT,FP_ENV_MODE_2_DEFAULT|CP_EXCP_DISABLED +; +; FP_FLAGS_DEFAULT definitions +; + .equ FP_FLAGS_DEFAULT, 0x00000000 ; No flags set +; +; The following macros are used by transcendentals to access the environment. +; +; MACRO NAME: clear_Flags +; +; FUNCTION: to clear the flags on entry to a transcendental routine. +; +; INPUT PARAMETERS: reg - temporary working register +; reg2 - temporary working register +; + .macro clear_Flags,reg,reg2 + .endm +; +; MACRO NAME: set_Invalid_Op_flag +; +; FUNCTION: to set the Invalid operation flag in the floating-point status +; register +; +; INPUT PARAMETERS: reg - temporary working register +; reg2 - 2nd temporary working register +; + .macro set_Invalid_Op_flag,reg,reg2 + .endm + +; +; MACRO NAME: set_Reserved_Op_flag +; +; FUNCTION: to set the Reserved Op flag in the floating-point status register +; +; INPUT PARAMETERS: reg - temporary working register +; reg2 - 2nd temporary working register +; + .macro set_Reserved_Op_flag,reg,reg2 + .endm + +; +; MACRO NAME: extract_Rounding_Mode +; +; FUNCTION: to extract the Rounding Mode portion of the floating-point +; invironment mode register, shift the value to the range of +; 0-7, and leave it in a register +; +; INPUT PARAMETERS: reg - destination for the mode +; + .macro extract_Rounding_Mode,reg + .ifdef _29027_MODE + .extern __29027Mode + const reg,__29027Mode + consth reg,__29027Mode + load 0,0,reg,reg + srl reg,reg,CP_RMS_POSITION + and reg,reg,CP_RMS_MASK >> CP_RMS_POSITION + .else + mfsr reg,FPE + and reg,reg,FPE_FPRND_MASK + srl reg,reg,FPE_FPRND_POSITION + .endif + .endm + +; +; MACRO NAME: set_Rounding_Mode +; +; FUNCTION: to set the 29027 Rounding Mode to a given value +; +; INPUT PARAMETERS: reg - working register +; reg2 - second working register +; rounding_mode - value of the rounding mode +; 0 - round to nearest +; 1 - round to minus infinity +; 2 - round to plus infinity +; 3 - round to zero +; +; NOTES: rounding_mode value is not checked +; 29027 Mode register is NOT written by this macro +; + .macro set_Rounding_Mode,reg,reg2,mode + .ifdef _29027_MODE + .extern __29027Mode + const reg2,__29027Mode + consth reg2,__29027Mode + load 0,0,reg,reg2 + const reg2,CP_RMS_MASK + consth reg2,CP_RMS_MASK + andn reg,reg,reg2 + const reg2,mode + sll reg2,reg2,CP_RMS_POSITION + or reg,reg,reg2 + const reg2,__29027Mode + consth reg2,__29027Mode + store 0,0,reg,reg2 + add reg2,reg2,4 + load 0,0,reg2,reg2 + cp_write_mode reg2,reg + .else + mfsr reg,FPE + andn reg,reg,FPE_FPRND_MASK + const reg2,mode + sll reg2,reg2,FPE_FPRND_POSITION + or reg,reg,reg2 + mtsr FPE,reg + .endif + .endm +; +; +; NOTE: The 29027 is the floating point coprocessor for the 29000. +; It contains 8 floating point registers FP0 to FP7. Three of +; these, FP0, FP1, and FP2, are currently designated as scratch, +; that is, they will not be preserved across calls. The other +; five contain values that must be saved whenever they are used +; in code, and restored before the exit of the routine. The 29027 +; registers are tagged with a single bit indicating the precision +; of the current value. When numbers are read into the 29027, +; they are always stored in double precision, so that single +; precision values are converted on input. Only the MOVE instruction +; fails to do this automatic widening. If the result from calculations +; in the 29027 ALU (determined by the result precision bit in the +; instruction word) is to be single precision and the result saved in +; an FP reg, the result precision bit from the instruction gets copied +; into the precision bit for the register. If a single precision +; SNaN is saved from the 29027, it will be converted to a double +; precision QNaN. Along the way it will cause an unmasked exception +; when read off the chip and cause changes to the status register. +; So the preservation routine will need to modify the mode register to +; mask off the exceptions, save the state of the status register before +; saving the FP regs, and restore the status and mode registers to their +; original settings when the save is complete. +; +; REFERENCE: The instructions to drive the Am29027 are described in the +; Am29027 manual beginning on page 17. Table 4 describes the +; operation codes and table 3 the multiplexer codes. Communication +; with the 29000 is described on pages 11 and 12 of the Am29027 +; manual and chapters 6 and 8 of the Am29000 User's Manual +; +; MACRO NAME: save_FP_regs +; +; FUNCTION: to save the AMD 29027 floating point register values in the +; 29000 general purpose registers +; +; INPUT PARAMETERS: fp_register, one of the 29027 registers FP3 - FP7 +; +; REGISTER USAGE: the following registers are used in save_FP_regs +; +; rtn0 this register is used in setting the mode and status registers +; rtn1 this register is used in setting the mode and status registers +; rtn6 this register is used to store the MSW when FP3 is saved +; rtn7 this register is used to store the LSW when FP3 is saved +; rtn8 this register is used to store the MSW when FP4 is saved +; rtn9 this register is used to store the LSW when FP4 is saved +; + + .macro save_FP_regs,fp_register + .ifdef _29027_MODE + ; + ; For 29027 mode, expand the macro into 29027 code to preserve FP register + ; + .ifeqs "@fp_register@","FP3" + const rtn6,__29027Mode ; Load the address of FP mode + consth rtn6,__29027Mode + load 0,0,rtn0,rtn6 ; Load MSW of FP mode into rtn0 + add rtn6,rtn6,4 ; Increment rtn6 + 4 + load 0,0,rtn1,rtn6 ; Load LSW of FP mode into rtn1 + const rtn6,CP_RESERVED_OP_EXCP_MASK ; Load mask to disable exception + consth rtn6,CP_RESERVED_OP_EXCP_MASK + or rtn0,rtn0,rtn6 ; OR in disable of exception mask + cp_write_mode rtn1, rtn0 ; Reset mode w/exception disabled + cp_read_status rtn0 ; Read status and save in rtn1 + const rtn6,CP_PASS_P | CP_P_EQ_RF3 ; Instruction is PASS_P from RF3 + consth rtn6,CP_PASS_P | CP_P_EQ_RF3 + ; Load & execute the instruction + ; + store 1,CP_WRITE_INST | CP_START,rtn6,rtn6 + load 1,CP_READ_MSBS,rtn6,rtn6 ; Read the MSW to first register + load 1,CP_READ_LSBS,rtn7,rtn7 ; Read the LSW to second register + cp_write_status rtn0 ; Restore the original status + const rtn1,__29027Mode ; Load the address of FP mode + consth rtn1,__29027Mode + load 0,0,rtn0,rtn1 ; Load MSW of FP mode into rtn0 + add rtn1,rtn1,4 ; Increment rtn6 to __29027Mode+4 + load 0,0,rtn1,rtn1 ; Load LSW of FP mode into rtn1 + cp_write_mode rtn1, rtn0 ; Restore the original write mode + .endif + .ifeqs "@fp_register@","FP4" + const rtn8,__29027Mode ; Load the address of FP mode + consth rtn8,__29027Mode + load 0,0,rtn0,rtn8 ; Load MSW of FP mode into rtn0 + add rtn8,rtn8,4 ; Increment rtn6 + 4 + load 0,0,rtn1,rtn8 ; Load LSW of FP mode into rtn1 + const rtn8,CP_RESERVED_OP_EXCP_MASK ; Load mask to disable exception + consth rtn8,CP_RESERVED_OP_EXCP_MASK + or rtn0,rtn0,rtn8 ; OR in disable of exception mask + cp_write_mode rtn1, rtn0 ; Reset mode w/exception disabled + cp_read_status rtn0 ; Read status and save in rtn1 + const rtn8,CP_PASS_P | CP_P_EQ_RF4 ; Instruction is PASS_P from RF4 + consth rtn8,CP_PASS_P | CP_P_EQ_RF4 + ; Load & execute the instruction + ; + store 1,CP_WRITE_INST | CP_START,rtn8,rtn8 + load 1,CP_READ_MSBS,rtn8,rtn8 ; Read the MSW to first register + load 1,CP_READ_LSBS,rtn9,rtn9 ; Read the LSW to second register + cp_write_status rtn0 ; Restore the original status + const rtn1,__29027Mode ; Load the address of FP mode + consth rtn1,__29027Mode + load 0,0,rtn0,rtn1 ; Load MSW of FP mode into rtn0 + add rtn1,rtn1,4 ; Increment rtn6 + 4 + load 0,0,rtn1,rtn1 ; Load LSW of FP mode into rtn1 + cp_write_mode rtn1, rtn0 ; Restore the original write mode + .endif + .else + ; + ; For 29000 mode, do nothing + ; + .endif + .endm +; +; MACRO NAME: restore_FP_regs +; +; FUNCTION: to restore the AMD 29027 floating point register values from the +; 29000 general purpose registers +; +; INPUT PARAMETERS: fp_register, one of the 29027 registers FP3 - FP7 +; +; REGISTER USAGE: the following registers are used in restore_FP_regs +; +; rtn0 this register is used in setting the mode and status registers +; rtn6 the value in this register is stored as the MSW of FP3 +; rtn7 the value in this register is stored as the LSW of FP3 +; rtn8 the value in this register is stored as the MSW of FP4 +; rtn9 the value in this register is stored as the LSW of FP4 +; + .macro restore_FP_regs,fp_register + .ifdef _29027_MODE + ; + ; For 29027 mode, move data from return registers to the correct FP register + ; + .ifeqs "@fp_register@","FP3" + store 1,CP_WRITE_R ,rtn6,rtn7 ; Move the data to the R register + ; Then create the instruction + ; + const rtn0,CP_MOVE_P|CP_D_D|CP_P_EQ_R|CP_DEST_EQ_RF3 + consth rtn0,CP_MOVE_P|CP_D_D|CP_P_EQ_R|CP_DEST_EQ_RF3 + ; + ; Perform the write + ; + store 1,(CP_WRITE_INST | CP_START),rtn0,0 + .endif + .ifeqs "@fp_register@","FP4" + store 1,CP_WRITE_R ,rtn8,rtn9 ; Move the data to the R register + ; Then create the instruction + ; + const rtn0,CP_MOVE_P|CP_D_D|CP_P_EQ_R|CP_DEST_EQ_RF4 + consth rtn0,CP_MOVE_P|CP_D_D|CP_P_EQ_R|CP_DEST_EQ_RF4 + ; + ; Perform the write + ; + store 1,(CP_WRITE_INST | CP_START),rtn0,0 + .endif + .else + ; + ; For 29000 mode, do nothing. + ; + .endif + .endm +; +; end of file intrinsi.h

intrinsi.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: sysmac.h =================================================================== --- sysmac.h (nonexistent) +++ sysmac.h (revision 345) @@ -0,0 +1,165 @@ +; @(#)sysmac.h 1.7 90/10/14 20:56:17, Copyright 1988, 1989, 1990 AMD +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright 1988, 1989, 1990 Advanced Micro Devices, Inc. +; +; This software is the property of Advanced Micro Devices, Inc (AMD) which +; specifically grants the user the right to modify, use and distribute this +; software provided this notice is not removed or altered. All other rights +; are reserved by AMD. +; +; AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS +; SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL +; DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR +; USE OF THIS SOFTWARE. +; +; So that all may benefit from your experience, please report any problems +; or suggestions about this software to the 29K Technical Support Center at +; 800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131 in the UK, or +; 0031-11-1129 in Japan, toll free. The direct dial number is 512-462-4118. +; +; Advanced Micro Devices, Inc. +; 29K Support Products +; Mail Stop 573 +; 5900 E. Ben White Blvd. +; Austin, TX 78741 +; 800-292-9263 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; +; sysmac.h +; + .include "sys/proreg.h" + +; Supported system call function numbers - BSD emulation + + .equ BSD_exit, 1 + .equ BSD_open, 5 + .equ BSD_close, 6 + .equ BSD_remove, 10 + .equ BSD_lseek, 19 + .equ BSD_sbrk, 69 + .equ BSD_readv, 120 + .equ BSD_writev, 121 + .equ BSD_rename, 128 +; Functions above 0x100 are handled by Am29000 code + .equ BSD_alloc, 0x101 + .equ BSD_free, 0x102 + .equ BSD_getpagesize, 0x103 + + .equ BSD_clock, 0x111 + +; Supported system call function numbers - HIF version 2.0 + + .equ HIF_exit, 0x01 + + .equ HIF_open, 0x11 + .equ HIF_close, 0x12 + .equ HIF_read, 0x13 + .equ HIF_write, 0x14 + .equ HIF_lseek, 0x15 + .equ HIF_remove, 0x16 + .equ HIF_rename, 0x17 + .equ HIF_ioctl, 0x18 + .equ HIF_iowait, 0x19 + .equ HIF_iostat, 0x1a + + .equ HIF_tmpnam, 0x21 + + .equ HIF_time, 0x31 + + .equ HIF_getenv, 0x41 + .equ HIF_gettz, 0x43 + + .equ HIF_sysalloc, 0x101 + .equ HIF_alloc, HIF_sysalloc ;Synonym. + .equ HIF_sysfree, 0x102 + .equ HIF_free, HIF_sysfree ;Synonym. + .equ HIF_getpsize, 0x103 + .equ HIF_getpagesize,HIF_getpsize ;Synonym. + .equ HIF_getargs, 0x104 + + .equ HIF_clock, 0x111 + .equ HIF_cycles, 0x112 + + .equ HIF_setvec, 0x121 + .equ HIF_settrap, 0x122 + .equ HIF_setim, 0x123 + + .equ HIF_query, 0x131 + + .equ HIF_signal, 0x141 + .equ HIF_sigdfl, 0x142 + .equ HIF_sigret, 0x143 + .equ HIF_sigrep, 0x144 + .equ HIF_sigskp, 0x145 + .equ HIF_sendsig, 0x146 + +;Maintain compatibility with HIF 1.0 code. + + .equ EPI_exit, HIF_exit + + .equ EPI_open, HIF_open + .equ EPI_close, HIF_close + .equ EPI_read, HIF_read + .equ EPI_write, HIF_write + .equ EPI_lseek, HIF_lseek + .equ EPI_remove, HIF_remove + .equ EPI_rename, HIF_rename + + .equ EPI_tmpnam, HIF_tmpnam + + .equ EPI_time, HIF_time + + .equ EPI_getenv, HIF_getenv + .equ EPI_gettz, HIF_gettz + .equ EPI_alloc, HIF_sysalloc + .equ EPI_free, HIF_sysfree + .equ EPI_getpagesize, HIF_getpsize + .equ EPI_getargs, HIF_getargs + + .equ EPI_clock, HIF_clock + .equ EPI_cycles, HIF_cycles + + .equ EPI_setvec, HIF_setvec + + .equ V_SYSCALL, 69 + +; System call macros +/* Now that source files have been sed'd to avoid these macros, they + are just commented out. -- gnu@cygnus.com Oct 90 + + .ifdef _BSD_OS + .equ V_SYSCALL, 66 + .else + .equ V_SYSCALL, 69 + .endif + + .macro syscall, name + .ifdef _BSD_OS + const tav, SYS_@name + .else + const tav, HIF_@name + .endif + asneq V_SYSCALL, gr1, gr1 + .endm + +; error return +; set errno to the error value in tav. +; return -1 +; + .macro returnerr +;; .extern _errno ; rather have undef'd sym than multiple def's + const tpc, _errno + consth tpc, _errno + store 0, 0, tav, tpc + jmpi lr0 + constn v0, -1 + .endm + +; package the most common case in one macro +; + .macro system, name + syscall name + jmpti tav, lr0 + returnerr + .endm + */

sysmac.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: romdcl.h =================================================================== --- romdcl.h (nonexistent) +++ romdcl.h (revision 345) @@ -0,0 +1,392 @@ +; @(#)romdcl.h 1.4 90/10/14 20:56:12, Copyright 1988, 1989, 1990 AMD +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright 1990 Advanced Micro Devices, Inc. +; +; This software is the property of Advanced Micro Devices, Inc (AMD) which +; specifically grants the user the right to modify, use and distribute this +; software provided this notice is not removed or altered. All other rights +; are reserved by AMD. +; +; AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS +; SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL +; DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR +; USE OF THIS SOFTWARE. +; +; So that all may benefit from your experience, please report any problems +; or suggestions about this software to the 29K Technical Support Center at +; 800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131 in the UK, or +; 0031-11-1129 in Japan, toll free. The direct dial number is 512-462-4118. +; +; Advanced Micro Devices, Inc. +; 29K Support Products +; Mail Stop 573 +; 5900 E. Ben White Blvd. +; Austin, TX 78741 +; 800-292-9263 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + .sbttl "Register, Constant and Macro Declarations - v1.4" + +; Copyright 1988, Advanced Micro Devices +; Written by Gibbons and Associates, Inc. + +;v1.4 JG correct FUNCTION macro - fault in register padding to even + +;----------------------------------------------------------------------- +;Global registers +;----------------------------------------------------------------------- + .reg rsp, gr1 ;local reg. var. stack pointer + + .equ SYS_TEMP, 64 ;system temp registers + + .reg st0, gr64 + .reg st1, gr65 + .reg st2, gr66 + .reg st3, gr67 + .reg st4, gr68 + .reg st5, gr69 + .reg st6, gr70 + .reg st7, gr71 + .reg st8, gr72 + .reg st9, gr73 + .reg st10, gr74 + .reg st11, gr75 + .reg st12, gr76 + .reg st13, gr77 + .reg st14, gr78 + .reg st15, gr79 + + .equ SYS_STAT, 80 ;system static registers + + .reg ss0, gr80 + .reg ss1, gr81 + .reg ss2, gr82 + .reg ss3, gr83 + .reg ss4, gr84 + .reg ss5, gr85 + .reg ss6, gr86 + .reg ss7, gr87 + .reg ss8, gr88 + .reg ss9, gr89 + .reg ss10, gr90 + .reg ss11, gr91 + .reg ss12, gr92 + .reg ss13, gr93 + .reg ss14, gr94 + .reg ss15, gr95 + + .equ RET_VAL, 96 ;return registers + + .reg v0, gr96 + .reg v1, gr97 + .reg v2, gr98 + .reg v3, gr99 + .reg v4, gr100 + .reg v5, gr101 + .reg v6, gr102 + .reg v7, gr103 + .reg v8, gr104 + .reg v9, gr105 + .reg v10, gr106 + .reg v11, gr107 + .reg v12, gr108 + .reg v13, gr109 + .reg v14, gr110 + .reg v15, gr111 + + .equ TEMP_REG, 96 ;temp registers + + .reg t0, gr96 + .reg t1, gr97 + .reg t2, gr98 + .reg t3, gr99 + .reg t4, gr100 + .reg t5, gr101 + .reg t6, gr102 + .reg t7, gr103 + .reg t8, gr104 + .reg t9, gr105 + .reg t10, gr106 + .reg t11, gr107 + .reg t12, gr108 + .reg t13, gr109 + .reg t14, gr110 + .reg t15, gr111 + + .equ RES_REG, 112 ;reserved (for user) + + .reg r0, gr112 + .reg r1, gr113 + .reg r2, gr114 + .reg r3, gr115 + + .equ TEMP_EXT, 116 ;temp extension (and shared) + + .reg x0, gr116 + .reg x1, gr117 + .reg x2, gr118 + .reg x3, gr119 + .reg x4, gr120 + .reg x5, gr121 + .reg x6, gr122 + .reg x7, gr123 + .reg x8, gr124 + +;----------------------------------------------------------------------- +;Global registers with special calling convention uses +;----------------------------------------------------------------------- + + .reg tav, gr121 ;trap handler argument (also x6) + .reg tpc, gr122 ;trap handler return (also x7) + .reg lsrp, gr123 ;large return pointer (also x8) + .reg slp, gr124 ;static link pointer (also x9) + .reg msp, gr125 ;memory stack pointer + .reg rab, gr126 ;register alloc bound + .reg rfb, gr127 ;register frame bound + +;----------------------------------------------------------------------- +;Local compiler registers - output parameters, etc. +; (only valid if frame has been established) +;----------------------------------------------------------------------- + + .reg p15, lr17 ;parameter registers + .reg p14, lr16 + .reg p13, lr15 + .reg p12, lr14 + .reg p11, lr13 + .reg p10, lr12 + .reg p9, lr11 + .reg p8, lr10 + .reg p7, lr9 + .reg p6, lr8 + .reg p5, lr7 + .reg p4, lr6 + .reg p3, lr5 + .reg p2, lr4 + .reg p1, lr3 + .reg p0, lr2 + + +;----------------------------------------------------------------------- +;TLB register count +;----------------------------------------------------------------------- + + .equ TLB_CNT, 128 + + .eject + +;----------------------------------------------------------------------- +;constants for general use +;----------------------------------------------------------------------- + .equ WRD_SIZ, 4 ;word size + .equ TRUE, 0x80000000 ;logical true -- bit 31 + .equ FALSE, 0x00000000 ;logical false -- 0 + .equ CHKPAT_a5, 0xa5a5a5a5 ;check pattern + +;----------------------------------------------------------------------- +;constants for data access control +;----------------------------------------------------------------------- + .equ CE, 0b1 ;coprocessor enable + .equ CD, 0b0 ;coprocessor disable + + .equ AS, 0b1000000 ;set for I/O + .equ PA, 0b0100000 ;set for physical ad + .equ SB, 0b0010000 ;set for set BP + .equ UA, 0b0001000 ;set for user access + + .equ ROM_OPT, 0b100 ;OPT values for acc + .equ DATA_OPT, 0b000 + .equ INST_OPT, 0b000 + + .equ ROM_CTL, (PA + ROM_OPT) ;control field + .equ DATA_CTL, (PA + DATA_OPT) + .equ INST_CTL, (PA + INST_OPT) + .equ IO_CTL, (AS + PA + DATA_OPT) + + + .eject + +;----------------------------------------------------------------------- +;defined vectors +;----------------------------------------------------------------------- + + .equ V_IllegalOp, 0 + .equ V_Unaligned, 1 + .equ V_OutOfRange, 2 + .equ V_NoCoProc, 3 + .equ V_CoProcExcept, 4 + .equ V_ProtViol, 5 + .equ V_InstAccExcept, 6 + .equ V_DataAccExcept, 7 + .equ V_UserInstTLB, 8 + .equ V_UserDataTLB, 9 + .equ V_SupInstTLB, 10 + .equ V_SupDataTLB, 11 + .equ V_InstTLBProt, 12 + .equ V_DataTLBProt, 13 + .equ V_Timer, 14 + .equ V_Trace, 15 + .equ V_INTR0, 16 + .equ V_INTR1, 17 + .equ V_INTR2, 18 + .equ V_INTR3, 19 + .equ V_TRAP0, 20 + .equ V_TRAP1, 21 + + ; 22 - 31 reserved + + .equ V_MULTIPLY, 32 + .equ V_DIVIDE, 33 + .equ V_MULTIPLU, 34 + .equ V_DIVIDU, 35 + .equ V_CONVERT, 36 + + ; 37 - 41 reserved + + .equ V_FEQ, 42 + .equ V_DEQ, 43 + .equ V_FGT, 44 + .equ V_DGT, 45 + .equ V_FGE, 46 + .equ V_DGE, 47 + .equ V_FADD, 48 + .equ V_DADD, 49 + .equ V_FSUB, 50 + .equ V_DSUB, 51 + .equ V_FMUL, 52 + .equ V_DMUL, 53 + .equ V_FDIV, 54 + .equ V_DDIV, 55 + + ; 56 - 63 reserved + + .equ V_SPILL, 64 + .equ V_FILL, 65 + .equ V_BSDCALL, 66 + .equ V_SYSVCALL, 67 + .equ V_BRKPNT, 68 + .equ V_EPI_OS, 69 + + .eject + + .macro R_LEFT,REGVAR + + ;Rotate left + ; + ; Parameters: REGVAR register to rotate + + add REGVAR, REGVAR, REGVAR ;shift left by 1 bit, C = MSB + addc REGVAR, REGVAR, 0 ;add C to LSB + + .endm +;---------------------------------------------------------------------- + + + .macro FUNCTION,NAME,INCNT,LOCCNT,OUTCNT + + ;Introduces a non-leaf routine. + ; + ;This macro defines the standard tag word before the function, + ;then establishes the statement label with the function's name + ;and finally allocates a register stack frame. It may not be used + ;if a memory stack frame is required. + ; + ;Note also that the size of the register stack frame is limited. + ;Neither this nor the lack of a memory frame is considered to be + ;a severe restriction in an assembly language environment. The + ;assembler will report errors if the requested frame is too large + ;for this macro. + ; + ;It may be good practice to allocate an even number of both output + ;registers and local registers. This will help in maintaining + ;double word alignment within these groups. The macro will assure + ;double word alignment of the stack frame as a whole as required + ;for correct linkage. + ; + ; Paramters: NAME the function name + ; INCNT input parameter count + ; LOCCNT local register count + ; OUTCNT output parameter count + + .set ALLOC_CNT, ((2 + OUTCNT + LOCCNT) << 2) + .set PAD_CNT, (ALLOC_CNT & 4) + .set ALLOC_CNT, (ALLOC_CNT + PAD_CNT) + .set REG_PAD, (PAD_CNT >> 2) + .if (INCNT) + .set IN_PRM, (4 + OUTCNT + REG_PAD + LOCCNT + 0x80) + .endif + .if (LOCCNT) + .set LOC_REG, (2 + OUTCNT + REG_PAD + 0x80) + .endif + .if (OUTCNT) + .set OUT_PRM, (2 + 0x80) + .endif + + .word ((2 + OUTCNT + LOCCNT) << 16) +NAME: + sub rsp, rsp, ALLOC_CNT + asgeu V_SPILL, rsp, rab + add lr1, rsp, ((4 + OUTCNT + LOCCNT + REG_PAD + INCNT) << 2) + + .endm +;---------------------------------------------------------------------- + + + .macro LEAF,NAME,INCNT + + ;Introduces a leaf routine + ; + ;This macro defines the standard tag word before the function, + ;then establishes the statement label with the function's name. + ; + ; Paramters: NAME the function name + ; INCNT input parameter count + + .if (INCNT) + .set IN_PRM, (2 + 0x80) + .endif + .set ALLOC_CNT, 0 + + .word 0 +NAME: + + .endm +;---------------------------------------------------------------------- + + + .macro EPILOGUE + + ;De-allocates register stack frame (only and only if necessary). + + .if (ALLOC_CNT) + + add rsp, rsp, ALLOC_CNT + nop + jmpi lr0 + asleu V_FILL, lr1, rfb + + .else + + jmpi lr0 + nop + + .endif + + .set IN_PRM, (1024) ;illegal, to cause err on ref + .set LOC_REG, (1024) ;illegal, to cause err on ref + .set OUT_PRM, (1024) ;illegal, to cause err on ref + .set ALLOC_CNT, (1024) ;illegal, to cause err on ref + + .endm +;---------------------------------------------------------------------- + + +;Initial values for macro set variables to guard against misuse + + .set IN_PRM, (1024) ;illegal, to cause err on ref + .set LOC_REG, (1024) ;illegal, to cause err on ref + .set OUT_PRM, (1024) ;illegal, to cause err on ref + .set ALLOC_CNT, (1024) ;illegal, to cause err on ref + +;...................................................................... +; end of romdcl.h

romdcl.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: macros.h =================================================================== --- macros.h (nonexistent) +++ macros.h (revision 345) @@ -0,0 +1,37 @@ +; @(#)macros.h 1.3 90/10/14 20:56:10, Copyright 1989, 1990 AMD +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright 1989, 1990 Advanced Micro Devices, Inc. +; +; This software is the property of Advanced Micro Devices, Inc (AMD) which +; specifically grants the user the right to modify, use and distribute this +; software provided this notice is not removed or altered. All other rights +; are reserved by AMD. +; +; AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS +; SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL +; DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR +; USE OF THIS SOFTWARE. +; +; So that all may benefit from your experience, please report any problems +; or suggestions about this software to the 29K Technical Support Center at +; 800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131 in the UK, or +; 0031-11-1129 in Japan, toll free. The direct dial number is 512-462-4118. +; +; Advanced Micro Devices, Inc. +; 29K Support Products +; Mail Stop 573 +; 5900 E. Ben White Blvd. +; Austin, TX 78741 +; 800-292-9263 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; +; macros.h +; Short macros of general utility + + .macro mov, dest,src + add dest, src, 0 + .endm + + .macro not, dest,src + nand dest, src, src + .endm

macros.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: cpudef.h =================================================================== --- cpudef.h (nonexistent) +++ cpudef.h (revision 345) @@ -0,0 +1,270 @@ +; @(#)cpudef.h 2.3 90/10/14 20:55:56, Copyright 1989, 1990 AMD +;----------------------------------------------------------------------- +; Useful equates +;----------------------------------------------------------------------- +; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright 1989, 1990 Advanced Micro Devices, Inc. +; +; This software is the property of Advanced Micro Devices, Inc (AMD) which +; specifically grants the user the right to modify, use and distribute this +; software provided this notice is not removed or altered. All other rights +; are reserved by AMD. +; +; AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS +; SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL +; DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR +; USE OF THIS SOFTWARE. +; +; So that all may benefit from your experience, please report any problems +; or suggestions about this software to the 29K Technical Support Center at +; 800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131 in the UK, or +; 0031-11-1129 in Japan, toll free. The direct dial number is 512-462-4118. +; +; Advanced Micro Devices, Inc. +; 29K Support Products +; Mail Stop 573 +; 5900 E. Ben White Blvd. +; Austin, TX 78741 +; 800-292-9263 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + ; Processor status registers OPS (sr1) and CPS (sr2) + .equ CA,0x8000 ; Coprocessor active + .equ IP,0x4000 ; Interrupt pending + .equ TE,0x2000 ; Trace enable + .equ TP,0x1000 ; Trace pending + .equ TU,0x0800 ; Trap unaligned access + .equ FZ,0x0400 ; Freeze + .equ LK,0x0200 ; Lock + .equ RE,0x0100 ; ROM enable + .equ WM,0x0080 ; Wait mode + .equ PD,0x0040 ; No translation for Data + .equ PI,0x0020 ; No translation for Instr + .equ SM,0x0010 ; Supervisor mode + .equ IM,0x000C ; Interrupt mask + .equ IM1,0x0100 ; enable INTR0-1 + .equ IM2,0x1000 ; enable INTR0-2 + .equ IM3,0x1100 ; enable INTR0-3 + .equ DI,0x0002 ; Disable ints + .equ DA,0x0001 ; Disable ints and traps + + ; Configuration register CFG (sr3) + .equ PRL,0xFF000000 ; Processor release level + .equ VF,0x10 ; Vector fetch + .equ RV,0x08 ; ROM Vector area + .equ BO,0x04 ; Byte order + .equ CP,0x02 ; Coprocessor present + .equ CD,0x01 ; BTC disable + + ; Channel control register CHC (sr6) + .equ LS,0x8000 ; Load store + .equ ML,0x4000 ; Multiple operation + .equ ST,0x2000 ; Set + .equ LA,0x1000 ; Lock active + .equ TF,0x0400 ; Transaction faulted + .equ TR,0x03FC ; Target register + .equ NN,0x0002 ; Not needed + .equ CV,0x0001 ; Contents valid + + ; Timer reload register TMR (sr9) + .equ IE,0x01000000 ; timer int enable + .equ IN,0x02000000 ; timer int pending + .equ OV,0x04000000 ; timer Overflow + + ; MMU configuration register MMU (sr13) + .equ PS,0x300 ; Page size + .equ PID,0xFF ; Process identifier + + ; ALU status register ALU (sr132) + .equ DF,0x800 ; Divide flag + .equ V,0x400 ; Overflow + .equ N,0x200 ; Negative + .equ Z,0x100 ; Zero + .equ C,0x080 ; Carry + + ; TLB entry + .equ VTAG,0xFFFF8000 ; Virtual tag + .equ VE,0x4000 ; Valid entry + .equ SR,0x2000 ; Supervisor read + .equ SW,0x1000 ; Supervisor write + .equ SE,0x0800 ; Supervisor execute + .equ UR,0x0400 ; User read + .equ UW,0x0200 ; User write + .equ UE,0x0100 ; User execute + .equ TID,0x00FF ; Task identifier + .equ RPN,0xFFFFFC00 ; Real page number + .equ PGM,0x00C0 ; User programmable + .equ U,0x0002 ; Usage + .equ F,0x0001 ; Flag + +;----------------------------------------------------------------------- +;Global registers +;----------------------------------------------------------------------- + + .reg rsp, gr1 ; local register stack pointer + + ; System-wide statics + .reg s0, gr64 + .reg spillreg, s0 ; pointer to user spill handler + .reg s1, gr65 + .reg fillreg, s1 ; pointer to user fill handler + .reg s2, gr66 + .reg heapptr, s2 ; pointer to heap area + .reg s3, gr67 + .reg s4, gr68 + .reg s5, gr69 + .reg s6, gr70 + .reg s7, gr71 + .reg s8, gr72 + .reg s9, gr73 + .reg s10, gr74 + .reg s11, gr75 + .reg s12, gr76 + .reg s13, gr77 + .reg s14, gr78 + .reg s15, gr79 + + ; Interrupt handler temporaries + .reg i0, gr80 + .reg i1, gr81 + .reg i2, gr82 + .reg i3, gr83 + .reg i4, gr84 + .reg i5, gr85 + .reg i6, gr86 + .reg i7, gr87 + .reg i8, gr88 + .reg i9, gr89 + .reg i10, gr90 + .reg i11, gr91 + .reg i12, gr92 + .reg i13, gr93 + .reg i14, gr94 + .reg i15, gr95 + + ; Subroutine/function temporaries + ; also used for function return values + .reg t0, gr96 + .reg rtn, t0 + .reg t1, gr97 + .reg t2, gr98 + .reg t3, gr99 + .reg t4, gr100 + .reg t5, gr101 + .reg t6, gr102 + .reg t7, gr103 + .reg t8, gr104 + .reg t9, gr105 + .reg t10, gr106 + .reg t11, gr107 + .reg t12, gr108 + .reg t13, gr109 + .reg t14, gr110 + .reg t15, gr111 + + ; User process statics + .reg u0, gr112 + .reg u1, gr113 + .reg u2, gr114 + .reg u3, gr115 + + ; More subroutine/function temporaries + .reg t16, gr116 + .reg t17, gr117 + .reg t18, gr118 + .reg t19, gr119 + .reg t20, gr120 + + ; Older names for the same registers + .reg tmp0, gr116 + .reg tmp1, gr117 + .reg tmp2, gr118 + .reg tmp3, gr119 + .reg tmp4, gr120 + + ; Trap handler temporaries + .reg tav, gr121 ; arg/temp + .reg tpc, gr122 ; rtn/temp + + ; Linkage pointers + .reg lrp, gr123 ; large rtn ptr + .reg slp, gr124 ; static link ptr + .reg msp, gr125 ; memory stack ptr + .reg rab, gr126 ; register allocate bound + .reg rfb, gr127 ; register free bound + +;----------------------------------------------------------------------- +;Local compiler registers +; (only valid if frame has been established) +;----------------------------------------------------------------------- + + .reg p15, lr17 ; outgoing arg 16 + .reg p14, lr16 ; outgoing arg 15 + .reg p13, lr15 ; outgoing arg 14 + .reg p12, lr14 ; outgoing arg 13 + .reg p11, lr13 ; outgoing arg 12 + .reg p10, lr12 ; outgoing arg 11 + .reg p9, lr11 ; outgoing arg 10 + .reg p8, lr10 ; outgoing arg 9 + .reg p7, lr9 ; outgoing arg 8 + .reg p6, lr8 ; outgoing arg 7 + .reg p5, lr7 ; outgoing arg 6 + .reg p4, lr6 ; outgoing arg 5 + .reg p3, lr5 ; outgoing arg 4 + .reg p2, lr4 ; outgoing arg 3 + .reg p1, lr3 ; outgoing arg 2 + .reg p0, lr2 ; outgoing arg 1 + .reg fp, lr1 ; frame pointer + .reg raddr, lr0 ; return address + +;----------------------------------------------------------------------- +; Vectors +;----------------------------------------------------------------------- + + .equ V_ILLEG, 0 ; Illegal opcode + .equ V_ALIGN, 1 ; Unaligned access + .equ V_RANGE, 2 ; Out of range + .equ V_COPRE, 3 ; Coprocessor not present + .equ V_COEXC, 4 ; Coprocessor exception + .equ V_PROT, 5 ; Protection violation + .equ V_INSTR, 6 ; Instruction access exception + .equ V_DATA, 7 ; Data access exception + .equ V_UITLB, 8 ; User-mode instruction TLB miss + .equ V_UDTLB, 9 ; User-mode data TLB miss + .equ V_SITLB, 10 ; Supervisor-mode instr TLB miss + .equ V_SDTLB, 11 ; Supervisor-mode data TLB miss + .equ V_ITLB, 12 ; Instruction TLB violation + .equ V_DTLB, 13 ; Data TLB violation + .equ V_TIMER, 14 ; Timer + .equ V_TRACE, 15 ; Trace + .equ V_INTR0, 16 ; Interrupt 0 + .equ V_INTR1, 17 ; Interrupt 1 + .equ V_INTR2, 18 ; Interrupt 2 + .equ V_INTR3, 19 ; Interrupt 3 + .equ V_TRAP0, 20 ; Trap 0 + .equ V_TRAP1, 21 ; Trap 1 + +;----------------------------------------------------------------------- +;constants for LOAD and STORE operations +;----------------------------------------------------------------------- + +; CE operand values + .equ CE, 0b1 ;coprocessor enable + .equ ME, 0b0 ; memory enable + +; CNTL operand values + .equ IO, 0b1000000 ;set for I/O + .equ PA, 0b0100000 ;force physical addr + .equ SB, 0b0010000 ;set for set BP + .equ UA, 0b0001000 ;force user mode access + .equ ROM, 0b0000100 ;ROM access + .equ HWORD, 0b0000010 ;Half word access + .equ BYTE, 0b0000001 ;Byte access + .equ WORD, 0b0000000 ;Word access + +;----------------------------------------------------------------------- +; stack alignment value +;----------------------------------------------------------------------- + .equ STKALIGN, 8 ; double word align +

cpudef.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: smartmac.h =================================================================== --- smartmac.h (nonexistent) +++ smartmac.h (revision 345) @@ -0,0 +1,1491 @@ +; @(#)smartmac.h 1.2 90/10/14 20:56:14, AMD +; start of smartmac.h file +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright 1988, 1989, 1990 Advanced Micro Devices, Inc. +; +; This software is the property of Advanced Micro Devices, Inc (AMD) which +; specifically grants the user the right to modify, use and distribute this +; software provided this notice is not removed or altered. All other rights +; are reserved by AMD. +; +; AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS +; SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL +; DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR +; USE OF THIS SOFTWARE. +; +; So that all may benefit from your experience, please report any problems +; or suggestions about this software to the 29K Technical Support Center at +; 800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131 in the UK, or +; 0031-11-1129 in Japan, toll free. The direct dial number is 512-462-4118. +; +; Advanced Micro Devices, Inc. +; 29K Support Products +; Mail Stop 573 +; 5900 E. Ben White Blvd. +; Austin, TX 78741 +; 800-292-9263 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; +; + .title "AM29000 Smart Macro Package" +; +; Floating point package for AMD 29000 family +; +; Copyright 1988 Advanced Micro Devices, Inc. +; +; All rights reserved +; +; Developed for AMD by Quantitative Technology Corporation +; 8700 SW Creekside Place Suite D +; Beaverton OR 97005 +; (503) 626-3081 +; +; Version information : +; +; Version 1.0 - 1 June 1988 - Larry Westerman (smart_macros.h) +; +; Revision 1.4 89/02/01 18:26:03 jimh +; Changed to relect the new symbols from Bob Perlman, and the new include file.s +; +; Revision 1.3 89/01/31 10:13:34 jimh +; Updated to use symbols from Bob Perlmans fpsymbol.h file. This is +; an extensive change. +; +; Revision 1.2 89/01/26 09:23:50 jimh +; This version checked in previous to substituting Bob Perlman's floating +; point symbols. +; +; Revision 1.1 89/01/24 13:23:29 jim +; Initial revision +; Replaces smart_macros.h ver 1.11. +; +; +; +; +; NOTES: +; +; This package makes the following assumptions about the use of these +; smart macros: +; +; 1. These macros will be after the entry code for a transcendental +; routine. This entry code will move the original function arguments +; (by value, if the target language is FORTRAN) into the global +; registers t0/t1 and t2/t3 (t0 and t2 for single precision +; routines). +; 2. The sources of all operands will be one register from the +; following list: +; t0 or t2 - the source is one of the original input operands +; rtn0 - the source is rtn0, which should be used as the +; source for all constant values to be sent to the +; AM29027 (when used) +; FP0 - FP7 - the source is one of the fp registers +; 3. The destination of all operations will be a register from the +; following list: +; rtn0 - the destination is the function return value +; FP0 - FP7 - the destination is one of the fp registers +; 4. The additional registers available for temporary use are +; t4, lrp, and slp. +; +; These register definitions are all taken from the file "proregs.a" +; which was supplied by AMD. NOTE that the FP0-FP7 registers, for the +; Am29000 version of the file, overlap with the rtn0-rtn15 registers, so +; that FP0 corresponds to rtn0/rtn1, FP1 to rtn2/rtn3, and so forth. +; + .equ ERROR,0 + .equ NO_ERROR,1 + + .equ DOUBLE_FUNCTION,0 + .equ SINGLE_FUNCTION,1 + + .equ T_OPERATION,0 + .equ Q_OPERATION,1 + + .equ R_SOURCE_29000,0 + .equ R_SOURCE_29027,1 + + .equ S_SOURCE_29000,0 + .equ S_SOURCE_29027,1 + + .equ DESTINATION_29000, 0 + .equ DESTINATION_29027, 1 + +; +; SMART MACRO : mfadd +; +; FUNCTION : single-precision floating point addition +; +; Required arguments : destination - one of possible destinations +; operand1 - one of possible sources +; operand2 - one of possible sources +; + .macro mfadd,destination,operand1,operand2 + + .if $narg!=3 + .err + .print "mfadd: missing parameter(s)" + .exitm + .endif + + .ifdef _29027_MODE + ; + ; For 29027 mode, perform full suite of checking + ; + initialize_previous_instruction + .set CURRENT_INSTRUCTION, CP_S_S | CP_P_PLUS_T + .set OPERATION_TYPE, T_OPERATION + perform_single_operation destination,operand1,operand2 + read_single_result destination + ; + ; Save the instruction for the next macro invocation + ; + .set PREVIOUS_INSTRUCTION, CURRENT_INSTRUCTION + + .else + ; + ; For 29000 mode, simply produce equivalent trap-inducing instruction + ; + fadd destination,operand1,operand2 + + .endif + + .endm ; end of mfadd macro definition + +; +; SMART MACRO : mfsub +; +; FUNCTION : single-precision floating point subtraction +; +; Required arguments : destination - one of possible destinations +; operand1 - one of possible sources +; operand2 - one of possible sources +; + .macro mfsub,destination,operand1,operand2 + + .if $narg!=3 + .err + .print "mfsub: missing parameter(s)" + .exitm + .endif + + .ifdef _29027_MODE + ; + ; For 29027 mode, perform full suite of checking + ; + initialize_previous_instruction + .set CURRENT_INSTRUCTION, CP_S_S | CP_P_MINUS_T + .set OPERATION_TYPE, T_OPERATION + perform_single_operation destination,operand1,operand2 + read_single_result destination + ; + ; Save the instruction for the next macro invocation + ; + .set PREVIOUS_INSTRUCTION, CURRENT_INSTRUCTION + + .else + ; + ; For 29000 mode, simply produce equivalent trap-inducing instruction + ; + fsub destination,operand1,operand2 + + .endif + + .endm ; end of mfsub macro definition + +; +; SMART MACRO : mfmul +; +; FUNCTION : single-precision floating point multiplication +; +; Required arguments : destination - one of possible destinations +; operand1 - one of possible sources +; operand2 - one of possible sources +; + .macro mfmul,destination,operand1,operand2 + + .if $narg!=3 + .err + .print "mfmul: missing parameter(s)" + .exitm + .endif + + .ifdef _29027_MODE + ; + ; For 29027 mode, perform full suite of checking + ; + initialize_previous_instruction + .set CURRENT_INSTRUCTION, CP_S_S | CP_P_TIMES_Q + .set OPERATION_TYPE, Q_OPERATION + perform_single_operation destination,operand1,operand2 + read_single_result destination + ; + ; Save the instruction for the next macro invocation + ; + .set PREVIOUS_INSTRUCTION, CURRENT_INSTRUCTION + + .else + ; + ; For 29000 mode, simply produce equivalent trap-inducing instruction + ; + fmul destination,operand1,operand2 + + .endif + + .endm ; end of mfmul macro definition + +; +; SMART MACRO : mfdiv +; +; FUNCTION : single-precision floating point divide +; +; Required arguments : destination - one of possible destinations +; operand1 - one of possible sources +; operand2 - one of possible sources +; + .macro mfdiv,destination,operand1,operand2 + + .if $narg!=3 + .err + .print "mfdiv: missing parameter(s)" + .exitm + .endif + + ; + ; Generate the trap instruction in all cases + ; + fdiv destination, operand1, operand2 + + .endm ; end of mfdiv macro definition + + +; +; SMART MACRO : mdadd +; +; FUNCTION : double-precision floating point addition +; +; Required arguments : destination - one of possible destinations +; operand1 - one of possible sources +; operand2 - one of possible sources +; + .macro mdadd,destination,operand1,operand2 + + .if $narg!=3 + .err + .print "mdadd: missing parameter(s)" + .exitm + .endif + + .ifdef _29027_MODE + ; + ; For 29027 mode, perform full suite of checking + ; + initialize_previous_instruction + .set CURRENT_INSTRUCTION, CP_D_D | CP_P_PLUS_T + .set OPERATION_TYPE, T_OPERATION + perform_double_operation destination,operand1,operand2 + read_double_result destination + ; + ; Save the instruction for the next macro invocation + ; + .set PREVIOUS_INSTRUCTION, CURRENT_INSTRUCTION + + .else + ; + ; For 29000 mode, simply produce equivalent trap-inducing instruction + ; + dadd destination,operand1,operand2 + + .endif + + .endm ; end of mdadd macro definition + +; +; SMART MACRO : mdsub +; +; FUNCTION : double-precision floating point subtraction +; +; Required arguments : destination - one of possible destinations +; operand1 - one of possible sources +; operand2 - one of possible sources +; + .macro mdsub,destination,operand1,operand2 + + .if $narg!=3 + .err + .print "mdsub: missing parameter(s)" + .exitm + .endif + + .ifdef _29027_MODE + ; + ; For 29027 mode, perform full suite of checking + ; + initialize_previous_instruction + .set CURRENT_INSTRUCTION, CP_D_D | CP_P_MINUS_T + .set OPERATION_TYPE, T_OPERATION + perform_double_operation destination,operand1,operand2 + read_double_result destination + ; + ; Save the instruction for the next macro invocation + ; + .set PREVIOUS_INSTRUCTION, CURRENT_INSTRUCTION + + .else + ; + ; For 29000 mode, simply produce equivalent trap-inducing instruction + ; + dsub destination,operand1,operand2 + + .endif + + .endm ; end of mdsub macro definition + +; +; SMART MACRO : mdmul +; +; FUNCTION : double-precision floating point multiplication +; +; Required arguments : destination - one of possible destinations +; operand1 - one of possible sources +; operand2 - one of possible sources +; + .macro mdmul,destination,operand1,operand2 + + .if $narg!=3 + .err + .print "mdmul: missing parameter(s)" + .exitm + .endif + + .ifdef _29027_MODE + ; + ; For 29027 mode, perform full suite of checking + ; + initialize_previous_instruction + .set CURRENT_INSTRUCTION, CP_D_D | CP_P_TIMES_Q + .set OPERATION_TYPE, Q_OPERATION + perform_double_operation destination,operand1,operand2 + read_double_result destination + ; + ; Save the instruction for the next macro invocation + ; + .set PREVIOUS_INSTRUCTION, CURRENT_INSTRUCTION + + .else + ; + ; For 29000 mode, simply produce equivalent trap-inducing instruction + ; + dmul destination,operand1,operand2 + + .endif + + .endm ; end of mdmul macro definition + +; +; SMART MACRO : mddiv +; +; FUNCTION : double-precision floating point divide +; +; Required arguments : destination - one of possible destinations +; operand1 - one of possible sources +; operand2 - one of possible sources +; + .macro mddiv,destination,operand1,operand2 + + .if $narg!=3 + .err + .print "mddiv: missing parameter(s)" + .exitm + .endif + + ; + ; Generate the trap instruction in all cases + ; + ddiv destination, operand1, operand2 + + .endm ; end of mfdiv macro definition + +; +; SMART MACRO: mconvert +; +; FUNCTION: Floating point/integer conversion +; +; PARAMETERS: destination - one of the possible destinations +; source - one of the possible sources +; sign_flag - one of SIGNED or UNSIGNED +; rounding_mode - one of ROUND_TO_NEAREST, ROUND_TO_PLUS, +; ROUND_TO_MINUS, ROUND_TO_ZERO +; destination_precision - one of FORMAT_INTEGER, FORMAT_DOUBLE, +; or FORMAT_SINGLE +; source_precision - one of FORMAT_INTEGER, FORMAT_DOUBLE, +; or FORMAT_SINGLE +; + .macro mconvert, destination, source, sign_flag, rounding_mode, destination_precision, source_precision + + .if $narg!=6 + .err + .print "mconvert: missing parameter(s)" + .exitm + .endif + + .ifdef _29027_MODE + ; + ; Generate in line 29027 code + ; + initialize_previous_instruction + .if ( destination_precision == FORMAT_INTEGER ) + .set CURRENT_INSTRUCTION, CP_CONVERT_T_TO_INT + select_T_operand source + .if ( source_precision == FORMAT_DOUBLE ) + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_S_D + .else + .if ( source_precision == FORMAT_SINGLE ) + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_S_S + .else + .err + .print "mconvert: invalid source type" + .exitm + .endif + .endif + .else + .if ( destination_precision == FORMAT_DOUBLE ) + .if ( source_precision == FORMAT_SINGLE ) + .set CURRENT_INSTRUCTION, CP_PASS_P | CP_P_EQ_R | CP_D_S + select_P_operand source + .else + .if ( source_precision == FORMAT_INTEGER ) + .set CURRENT_INSTRUCTION, CP_I_CONVERT_T_TO_FLOAT | CP_D_S + select_T_operand source + .else + .err + .print "mconvert: invalid source type" + .exitm + .endif + .endif + .else + .if ( destination_precision == FORMAT_SINGLE ) + .if ( source_precision == FORMAT_DOUBLE ) + .set CURRENT_INSTRUCTION, CP_PASS_P | CP_P_EQ_R | CP_S_D + select_P_operand source + .else + .if ( source_precision == FORMAT_INTEGER ) + .set CURRENT_INSTRUCTION, CP_I_CONVERT_T_TO_FLOAT | CP_S_S + select_T_operand source + .else + .err + .print "mconvert: invalid source type" + .exitm + .endif + .endif + .else + .err + .print "mconvert: invalid destination type " + .exitm + .endif + .endif + .endif + ; + ; Perform the operation, using a 29027 dummy register as the second + ; source operand, to avoid writing any data inappropriately to the + ; 29027 + ; + select_destination destination + .set S_SOURCE, S_SOURCE_29027 + .if ( source_precision == FORMAT_DOUBLE ) + write_and_execute_double_operation source, FP0 + .else + write_and_execute_single_operation source, FP0 + .endif + .if ( destination_precision == FORMAT_DOUBLE ) + read_double_result destination + .else + .if ( destination_precision == FORMAT_SINGLE ) + read_single_result destination + .else + read_integer_result destination + .endif + .endif + .else + ; + ; For 29000 mode (the default) just invoke the trap-inducing instruction + ; + convert destination,source,sign_flag,rounding_mode,destination_precision,source_precision + + .endif + + .endm ; end of mfeq macro definition + +; +; SMART MACRO: mfeq +; +; FUNCTION: Single precision, floating point compare +; +; PARAMETERS: destination - one of the possible destinations +; operand1 - one of the possible sources +; operand2 - one of the possible sources +; + .macro mfeq, destination, operand1, operand2 + + .if $narg!=3 + .err + .print "mfeq: missing parameter(s)" + .exitm + .endif + + .ifdef _29027_MODE + ; + ; Generate in line 29027 code + ; + initialize_previous_instruction + .set CURRENT_INSTRUCTION, CP_S_S | CP_COMPARE_P_AND_T + .set OPERATION_TYPE, T_OPERATION + select_destination destination + ; + ; 29027 registers are not valid destinations for compare operations + ; If the destination is a 29000 register, write the appropriate + ; Boolean value to that register. + ; + .if ( DESTINATION == DESTINATION_29027 ) + .err + .print "29027 destinations invalid for compares - @destination@" + .exitm + .else + perform_single_operation destination, operand1, operand2 + cp_read_flags destination + srl destination, destination, CP_EQUAL_FLAG_POSITION + sll destination, destination, 31 + .endif + + .else + ; + ; For 29000 mode (the default) just invoke the trap-inducing instruction + ; + feq destination,operand1,operand2 + + .endif + + .endm ; end of mfeq macro definition + +; +; SMART MACRO: mfge +; +; FUNCTION: Single precision, floating point compare +; +; PARAMETERS: destination - one of the possible destinations +; operand1 - one of the possible sources +; operand2 - one of the possible sources +; + .macro mfge, destination, operand1, operand2 + + .if $narg!=3 + .err + .print "mfge: missing parameter(s)" + .exitm + .endif + + .ifdef _29027_MODE + ; + ; Generate in line 29027 code + ; + initialize_previous_instruction + .set CURRENT_INSTRUCTION, CP_S_S | CP_COMPARE_P_AND_T + .set OPERATION_TYPE, T_OPERATION + select_destination destination + ; + ; 29027 registers are not valid destinations for compare operations + ; If the destination is a 29000 register, write the appropriate + ; Boolean value to that register. + ; + .if ( DESTINATION == DESTINATION_29027 ) + .err + .print "29027 destinations invalid for compares - @destination@" + .exitm + .else + perform_single_operation destination, operand1, operand2 + cp_read_flags destination + and destination, destination, CP_EQUAL_FLAG | CP_GREATER_THAN_FLAG + cpneq destination, destination, 0x0 + .endif + + .else + ; + ; For 29000 mode (the default) just invoke the trap-inducing instruction + ; + fge destination,operand1,operand2 + + .endif + + .endm ; end of mfge macro definition + +; +; SMART MACRO: mfgt +; +; FUNCTION: Single precision, floating point compare +; +; PARAMETERS: destination - one of the possible destinations +; operand1 - one of the possible sources +; operand2 - one of the possible sources +; + .macro mfgt, destination, operand1, operand2 + + .if $narg!=3 + .err + .print "mfgt: missing parameter(s)" + .exitm + .endif + + .ifdef _29027_MODE + ; + ; Generate in line 29027 code + ; + initialize_previous_instruction + .set CURRENT_INSTRUCTION, CP_S_S | CP_COMPARE_P_AND_T + .set OPERATION_TYPE, T_OPERATION + select_destination destination + ; + ; 29027 registers are not valid destinations for compare operations + ; If the destination is a 29000 register, write the appropriate + ; Boolean value to that register. + ; + .if ( DESTINATION == DESTINATION_29027 ) + .err + .print "29027 destinations invalid for compares - @destination@" + .exitm + .else + perform_single_operation destination, operand1, operand2 + cp_read_flags destination + srl destination, destination, CP_GREATER_THAN_FLAG_POSITION + sll destination, destination, 31 + .endif + + .else + ; + ; For 29000 mode (the default) just invoke the trap-inducing instruction + ; + fgt destination,operand1,operand2 + + .endif + + .endm ; end of mfgt macro definition + +; +; SMART MACRO: mdeq +; +; FUNCTION: Double precision, floating point compare +; +; PARAMETERS: destination - one of the possible destinations +; operand1 - one of the possible sources +; operand2 - one of the possible sources +; + .macro mdeq, destination, operand1, operand2 + + .if $narg!=3 + .err + .print "mdeq: missing parameter(s)" + .exitm + .endif + + + .ifdef _29027_MODE + ; + ; Generate in line 29027 code + ; + initialize_previous_instruction + .set CURRENT_INSTRUCTION, CP_D_D | CP_COMPARE_P_AND_T + .set OPERATION_TYPE, T_OPERATION + select_destination destination + ; + ; 29027 registers are not valid destinations for compare operations + ; If the destination is a 29000 register, write the appropriate + ; Boolean value to that register. + ; + .if ( DESTINATION == DESTINATION_29027 ) + .err + .print "29027 destinations invalid for compare - @destination@" + .exitm + .else + perform_double_operation destination, operand1, operand2 + cp_read_flags destination + srl destination, destination, CP_EQUAL_FLAG_POSITION + sll destination, destination, 31 + .endif + .else + ; + ; For 29000 mode (the default) just invoke the trap-inducing instruction + ; + deq destination,operand1,operand2 + + .endif + + .endm ; end of mdeq macro definition + +; +; SMART MACRO: mdge +; +; FUNCTION: Double precision, floating point compare +; +; PARAMETERS: destination - one of the possible destinations +; operand1 - one of the possible sources +; operand2 - one of the possible sources +; + .macro mdge, destination, operand1, operand2 + + .if $narg!=3 + .err + .print "mdge: missing parameter(s)" + .exitm + .endif + + + .ifdef _29027_MODE + ; + ; Generate in line 29027 code + ; + initialize_previous_instruction + .set CURRENT_INSTRUCTION, CP_D_D | CP_COMPARE_P_AND_T + .set OPERATION_TYPE, T_OPERATION + select_destination destination + ; + ; 29027 registers are not valid destinations for compare operations + ; If the destination is a 29000 register, write the appropriate + ; Boolean value to that register. + ; + .if ( DESTINATION == DESTINATION_29027 ) + .err + .print "29027 destinations invalid for compare - @destination@" + .exitm + .else + perform_double_operation destination, operand1, operand2 + cp_read_flags destination + and destination, destination, CP_EQUAL_FLAG | CP_GREATER_THAN_FLAG + cpneq destination, destination, 0x0 + .endif + .else + ; + ; For 29000 mode (the default) just invoke the trap-inducing instruction + ; + dge destination,operand1,operand2 + + .endif + + .endm ; end of mdge macro definition + +; +; SMART MACRO: mdgt +; +; FUNCTION: Double precision, floating point compare +; +; PARAMETERS: destination - one of the possible destinations +; operand1 - one of the possible sources +; operand2 - one of the possible sources +; + .macro mdgt, destination, operand1, operand2 + + .if $narg!=3 + .err + .print "mdgt: missing parameter(s)" + .exitm + .endif + + + .ifdef _29027_MODE + ; + ; Generate in line 29027 code + ; + initialize_previous_instruction + .set CURRENT_INSTRUCTION, CP_D_D | CP_COMPARE_P_AND_T + .set OPERATION_TYPE, T_OPERATION + select_destination destination + ; + ; 29027 registers are not valid destinations for compare operations + ; If the destination is a 29000 register, write the appropriate + ; Boolean value to that register. + ; + .if ( DESTINATION == DESTINATION_29027 ) + .err + .print "29027 destinations invalid for compare - @destination@" + .exitm + .else + perform_double_operation destination, operand1, operand2 + cp_read_flags destination + srl destination, destination, CP_GREATER_THAN_FLAG_POSITION + sll destination, destination, 31 + .endif + .else + ; + ; For 29000 mode (the default) just invoke the trap-inducing instruction + ; + dgt destination,operand1,operand2 + + .endif + + .endm ; end of mdgt macro definition + +; +; MACRO NAME : perform_double_operation +; +; FUNCTION : After the instruction base is set up, do the appropriate checking +; to send the instruction if necessary, send the double-precision +; operands if necessary, and start the operation +; +; PARAMETERS : destination - one of possible destination operands +; operand1 - one of possible source operands +; operand2 - one of possible source operands +; + .macro perform_double_operation,destination,operand1,operand2 + + .if $narg!=3 + .err + .print "perform_double_operation: missing parameter(s)" + .exitm + .endif + + ; + ; Start defining the instruction + ; + select_destination destination + select_P_operand operand1 + select_S_operand operand2 + + write_and_execute_double_operation operand1, operand2 + + .endm ; End of perform_double_operation macro definition + +; +; MACRO NAME : perform_single_operation +; +; FUNCTION : After the instruction base is set up, do the appropriate checking +; to send the instruction if necessary, send the single-precision +; operands if necessary and start the operation +; +; PARAMETERS : destination - one of possible destination operands +; operand1 - one of possible source operands +; operand2 - one of possible source operands +; + .macro perform_single_operation,destination,operand1,operand2 + + ; + ; Start defining the instruction + ; + select_destination destination + select_P_operand operand1 + select_S_operand operand2 + write_and_execute_single_operation operand1,operand2 + + .endm ; End of perform_single_operation macro definition + +; +; MACRO NAME : write_and_execute_double_operation +; +; FUNCTION : Write the instruction and operands for a double-precision +; operation, and start the operation +; +; PARAMETER : operand1 - first operand of double-precision operation +; operand2 - second operand of operation +; + .macro write_and_execute_double_operation,operand1,operand2 + .if ( ( R_SOURCE == R_SOURCE_29027 ) && ( S_SOURCE == S_SOURCE_29027 ) ) + ; + ; If both sources are within the 29027, write the instruction + ; and start the operation + ; + const t4, CURRENT_INSTRUCTION + consth t4, CURRENT_INSTRUCTION + cp_write_inst t4, START + .else + ; + ; One or both of the sources must be written first, so check the + ; previous instruction + ; + const t4, CURRENT_INSTRUCTION + consth t4, CURRENT_INSTRUCTION + cp_write_inst t4 + .if ( R_SOURCE == R_SOURCE_29000 ) && ( S_SOURCE == S_SOURCE_29027 ) + .ifeqs "@operand1@","t0" + cp_write_r t0, t1, START + .else + .ifeqs "@operand1@","t2" + cp_write_r t2, t3, START + .else + .ifeqs "@operand1@","rtn0" + cp_write_r rtn0, rtn1, START + .else + .err + .print "Invalid source for double operation - @operand1@" + .exitm + .endif + .endif + .endif + .endif + .if ( R_SOURCE == R_SOURCE_29027 ) && ( S_SOURCE == S_SOURCE_29000 ) + .ifeqs "@operand2@","t0" + cp_write_s t0, t1, START + .else + .ifeqs "@operand2@","t2" + cp_write_s t2, t3, START + .else + .ifeqs "@operand2@","rtn0" + cp_write_s rtn0, rtn1, START + .else + .err + .print "Invalid source for double operation - @operand1@" + .exitm + .endif + .endif + .endif + .endif + .if ( R_SOURCE == R_SOURCE_29000 ) && ( S_SOURCE == S_SOURCE_29000 ) + .ifeqs "@operand1@","t0" + cp_write_r t0, t1 + .else + .ifeqs "@operand1@","t2" + cp_write_r t2, t3 + .else + .ifeqs "@operand1@","rtn0" + cp_write_r rtn0, rtn1 + .else + .err + .print "Invalid source for double operation - @operand1@" + .exitm + .endif + .endif + .endif + .ifeqs "@operand2@","t0" + cp_write_s t0, t1, START + .else + .ifeqs "@operand2@","t2" + cp_write_s t2, t3, START + .else + .ifeqs "@operand2@","rtn0" + cp_write_s rtn0, rtn1, START + .else + .err + .print "Invalid source for double operation - @operand1@" + .exitm + .endif + .endif + .endif + .endif + .endif + + .endm ; end of write_and_execute_double_operation macro definition + +; +; MACRO NAME : write_and_execute_single_operation +; +; FUNCTION : If necessary, read the result from the 29027 into a +; register on the 29000 +; +; PARAMETER : operand1 - first source for single-precision operation +; operand2 - second source for operation +; + .macro write_and_execute_single_operation,operand1,operand2 + + .if ( ( R_SOURCE == R_SOURCE_29027 ) && ( S_SOURCE == S_SOURCE_29027 ) ) + ; + ; If both sources are within the 29027, write the instruction + ; and start the operation + ; + const t4, CURRENT_INSTRUCTION + consth t4, CURRENT_INSTRUCTION + cp_write_inst t4, START + .else + ; + ; One or both of the sources must be written first, so check the + ; previous instruction + ; + const t4,CURRENT_INSTRUCTION + consth t4,CURRENT_INSTRUCTION + cp_write_inst t4, START + .if ( R_SOURCE == R_SOURCE_29000 ) && ( S_SOURCE == S_SOURCE_29027 ) + cp_write_r operand1, operand1, START + .endif + .if ( R_SOURCE == R_SOURCE_29027 ) && ( S_SOURCE == S_SOURCE_29000 ) + cp_write_s operand2, operand2, START + .endif + .if ( R_SOURCE == R_SOURCE_29000 ) && ( S_SOURCE == S_SOURCE_29000 ) + cp_write_rs operand1, operand2, START + .endif + .endif + + .endm ; End of write_and_execute_single_operation macro definition + +; +; MACRO NAME : read_double_result +; +; FUNCTION : If necessary, read the result from the 29027 into a +; register on the 29000 +; +; PARAMETER : destination - one of the possible destination registers +; + .macro read_double_result,destination + .if ( DESTINATION == DESTINATION_29000 ) + ; + ; If the destination is not within the 29027 register file, read + ; the result and store it into the correct register in the 29000 + ; + .ifeqs "@destination@","rtn0" + cp_read_dp rtn0, rtn1 + .else + .err + .print "Invalid destination for double result - @destination@" + .exitm + .endif + .endif + + .endm ; End of read_double_result macro definition + +; +; MACRO NAME : read_single_result +; +; FUNCTION : If necessary, read the result from the 29027 into a +; register on the 29000 +; +; PARAMETER : destination +; + .macro read_single_result,destination + + .if ( DESTINATION == DESTINATION_29000 ) + ; + ; If the destination is not within the 29027 register file, read + ; the result and store it into the correct register in the 29000 + ; + .ifeqs "@destination@","rtn0" + cp_read_sp rtn0 + .else + .err + .print "Invalid destination for single result - @destination@" + .exitm + .endif + .endif + + .endm ; End of read_single_result macro definition + +; +; MACRO NAME : read_integer_result +; +; FUNCTION : If necessary, read the result from the 29027 into a +; register on the 29000 +; +; PARAMETER : destination +; + .macro read_integer_result,destination + + .if ( DESTINATION == DESTINATION_29000 ) + ; + ; If the destination is not within the 29027 register file, read + ; the result and store it into the correct register in the 29000 + ; + .ifeqs "@destination@","rtn0" + cp_read_int rtn0 + .else + .err + .print "Invalid destination for single result - @destination@" + .exitm + .endif + .endif + + .endm ; End of read_integer_result macro definition + +; +; MACRO NAME : select_P_operand +; +; FUNCTION : Given an operand, determine if the operand is from the +; register file, and if so, set the appropriate bits in +; the current instruction word. In addition, set the +; variable R_SOURCE to 0 for local register file, or 1 for +; floating-point register file. +; +; PARAMETER : operand1 - one of the possible source operands +; + .macro select_P_operand,operand1 + .ifeqs "@operand1@","t0" + .set R_SOURCE,R_SOURCE_29000 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_P_EQ_R + .exitm + .endif + .ifeqs "@operand1@","t2" + .set R_SOURCE,R_SOURCE_29000 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_P_EQ_R + .exitm + .endif + .ifeqs "@operand1@","rtn0" + .set R_SOURCE,R_SOURCE_29000 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_P_EQ_R + .exitm + .endif + .ifeqs "@operand1@","FP0" + .set R_SOURCE,R_SOURCE_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_P_EQ_RF0 + .exitm + .endif + .ifeqs "@operand1@","FP1" + .set R_SOURCE,R_SOURCE_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_P_EQ_RF1 + .exitm + .endif + .ifeqs "@operand1@","FP2" + .set R_SOURCE,R_SOURCE_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_P_EQ_RF2 + .exitm + .endif + .ifeqs "@operand1@","FP3" + .set R_SOURCE,R_SOURCE_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_P_EQ_RF3 + .exitm + .endif + .ifeqs "@operand1@","FP4" + .set R_SOURCE,R_SOURCE_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_P_EQ_RF4 + .exitm + .endif + .ifeqs "@operand1@","FP5" + .set R_SOURCE,R_SOURCE_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_P_EQ_RF5 + .exitm + .endif + .ifeqs "@operand1@","FP6" + .set R_SOURCE,R_SOURCE_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_P_EQ_RF6 + .exitm + .endif + .ifeqs "@operand1@","FP7" + .set R_SOURCE,R_SOURCE_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_P_EQ_RF7 + .exitm + .endif + .err + .print "@operand1@ - Invalid operand" + + .endm ; end of select_P_operand macro definition + +; +; MACRO NAME : select_S_operand +; +; FUNCTION : Given an operand, determine if the operand is from the +; register file, and if so, set the appropriate bits in +; the current instruction word. In addition, set the +; variable S_SOURCE to S_SOURCE_29000 or S_SOURCE_29027 +; as appropriate +; +; PARAMETER : operand2 - one of the possible source operands +; + .macro select_S_operand,operand2 + .ifeqs "@operand2@","t0" + .set S_SOURCE,S_SOURCE_29000 + .if ( OPERATION_TYPE == T_OPERATION ) + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_S + .else + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_Q_EQ_S + .endif + .exitm + .endif + .ifeqs "@operand2@","t2" + .set S_SOURCE,S_SOURCE_29000 + .if ( OPERATION_TYPE == T_OPERATION ) + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_S + .else + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_Q_EQ_S + .endif + .exitm + .endif + .ifeqs "@operand2@","rtn0" + .set S_SOURCE,S_SOURCE_29000 + .if ( OPERATION_TYPE == T_OPERATION ) + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_S + .else + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_Q_EQ_S + .endif + .exitm + .endif + .ifeqs "@operand2@","FP0" + .set S_SOURCE,S_SOURCE_29027 + .if ( OPERATION_TYPE == T_OPERATION ) + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_RF0 + .else + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_Q_EQ_RF0 + .endif + .exitm + .endif + .ifeqs "@operand2@","FP1" + .set S_SOURCE,S_SOURCE_29027 + .if ( OPERATION_TYPE == T_OPERATION ) + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_RF1 + .else + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_Q_EQ_RF1 + .endif + .exitm + .endif + .ifeqs "@operand2@","FP2" + .set S_SOURCE,S_SOURCE_29027 + .if ( OPERATION_TYPE == T_OPERATION ) + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_RF2 + .else + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_Q_EQ_RF2 + .endif + .exitm + .endif + .ifeqs "@operand2@","FP3" + .set S_SOURCE,S_SOURCE_29027 + .if ( OPERATION_TYPE == T_OPERATION ) + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_RF3 + .else + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_Q_EQ_RF3 + .endif + .exitm + .endif + .ifeqs "@operand2@","FP4" + .set S_SOURCE,S_SOURCE_29027 + .if ( OPERATION_TYPE == T_OPERATION ) + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_RF4 + .else + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_Q_EQ_RF4 + .endif + .exitm + .endif + .ifeqs "@operand2@","FP5" + .set S_SOURCE,S_SOURCE_29027 + .if ( OPERATION_TYPE == T_OPERATION ) + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_RF5 + .else + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_Q_EQ_RF5 + .endif + .exitm + .endif + .ifeqs "@operand2@","FP6" + .set S_SOURCE,S_SOURCE_29027 + .if ( OPERATION_TYPE == T_OPERATION ) + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_RF6 + .else + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_Q_EQ_RF6 + .endif + .exitm + .endif + .ifeqs "@operand2@","FP7" + .set S_SOURCE,S_SOURCE_29027 + .if ( OPERATION_TYPE == T_OPERATION ) + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_RF7 + .else + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_Q_EQ_RF7 + .endif + .exitm + .endif + .err + .print "@operand2@ - Invalid operand" + + .endm ; end of select_S_operand macro definition + +; +; MACRO NAME : select_T_operand +; +; FUNCTION : Given an operand, determine if the operand is from the +; register file, and if so, set the appropriate bits in +; the current instruction word, to read the corresponding +; source into the T operand. In addition, set the +; variable R_SOURCE to 0 for local register file, or 1 for +; floating-point register file. +; +; PARAMETER : operand1 - one of the possible source operands +; + .macro select_T_operand,operand1 + .ifeqs "@operand1@","t0" + .set R_SOURCE,R_SOURCE_29000 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_R + .exitm + .endif + .ifeqs "@operand1@","t2" + .set R_SOURCE,R_SOURCE_29000 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_R + .exitm + .endif + .ifeqs "@operand1@","rtn0" + .set R_SOURCE,R_SOURCE_29000 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_R + .exitm + .endif + .ifeqs "@operand1@","FP0" + .set R_SOURCE,R_SOURCE_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_RF0 + .exitm + .endif + .ifeqs "@operand1@","FP1" + .set R_SOURCE,R_SOURCE_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_RF1 + .exitm + .endif + .ifeqs "@operand1@","FP2" + .set R_SOURCE,R_SOURCE_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_RF2 + .exitm + .endif + .ifeqs "@operand1@","FP3" + .set R_SOURCE,R_SOURCE_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_RF3 + .exitm + .endif + .ifeqs "@operand1@","FP4" + .set R_SOURCE,R_SOURCE_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_RF4 + .exitm + .endif + .ifeqs "@operand1@","FP5" + .set R_SOURCE,R_SOURCE_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_RF5 + .exitm + .endif + .ifeqs "@operand1@","FP6" + .set R_SOURCE,R_SOURCE_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_RF6 + .exitm + .endif + .ifeqs "@operand1@","FP7" + .set R_SOURCE,R_SOURCE_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_T_EQ_RF7 + .exitm + .endif + .err + .print "@operand1@ - Invalid operand" + + .endm ; end of select_T_operand macro definition + +; +; MACRO NAME : select_destination +; +; FUNCTION : Given a destination, determine if the operand is from the +; register file, and if so, set the appropriate bits in +; the current instruction word. In addition, set the +; variable DESTINATION to DESTINATION_29000 or +; DESTINATION_29027 as appropriate +; +; PARAMETER : destination - one of the possible destination operands +; + .macro select_destination,destination + .ifeqs "@destination@","rtn0" + .set DESTINATION,DESTINATION_29000 + .exitm + .endif + .ifeqs "@destination@","FP0" + .set DESTINATION,DESTINATION_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_DEST_EQ_RF0 + .exitm + .endif + .ifeqs "@destination@","FP1" + .set DESTINATION,DESTINATION_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_DEST_EQ_RF1 + .exitm + .endif + .ifeqs "@destination@","FP2" + .set DESTINATION,DESTINATION_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_DEST_EQ_RF2 + .exitm + .endif + .ifeqs "@destination@","FP3" + .set DESTINATION,DESTINATION_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_DEST_EQ_RF3 + .exitm + .endif + .ifeqs "@destination@","FP4" + .set DESTINATION,DESTINATION_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_DEST_EQ_RF4 + .exitm + .endif + .ifeqs "@destination@","FP5" + .set DESTINATION,DESTINATION_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_DEST_EQ_RF5 + .exitm + .endif + .ifeqs "@destination@","FP6" + .set DESTINATION,DESTINATION_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_DEST_EQ_RF6 + .exitm + .endif + .ifeqs "@destination@","FP7" + .set DESTINATION,DESTINATION_29027 + .set CURRENT_INSTRUCTION, CURRENT_INSTRUCTION | CP_DEST_EQ_RF7 + .exitm + .endif + .err + .print "@destination@ - Invalid operand" + + .endm ; end of select_destination macro definition + +; MACRO NAME : initialize_previous_instruction +; +; FUNCTION : Make sure the previous instruction is defined and set to zero +; + .macro initialize_previous_instruction + + .ifndef PREVIOUS_INSTRUCTION + ; + ; Make sure that the previous instruction variable is initialized + ; + .set PREVIOUS_INSTRUCTION,0 + .endif + + .endm ; end of initialize_previous_instruction macro definition + + +; MACRO NAME : prepare_function_parameters +; +; FUNCTION : To place the input parameters into the correct position for +; use by the function body. When the target language is +; FORTRAN, the values of the input arguments are read from the +; supplied addresses and moved to the t0-t3 temporary area. +; When the target language is C or Pascal, the values of the +; input arguments are simply moved to the t0-t3 temporary area. +; + .macro prepare_function_parameters,arg1,arg2 + + .if $narg==0 + .err + .print "Missing function argument(s)" + .exitm + .endif + + .if $narg>2 + .err + .print "Too many function arguments + .exitm + .endif + + .if $narg>=1 + .if $isreg(@arg1) + .ifdef FORTRAN + load 0,0,t0,arg1 + .if ( FUNCTION_TYPE == DOUBLE_FUNCTION ) + add t1,arg1,4 + load 0,0,t1,t1 + .endif + .else + add t0,arg1,0 + .if ( FUNCTION_TYPE == DOUBLE_FUNCTION ) + add t1,%%(&arg1+1),0 + .endif + .endif + .else + .err + .print "Function argument not register - @arg1@" + .endif + .endif + .if $narg==2 + .if $isreg (@arg2) + .ifdef FORTRAN + load 0,0,t2,arg2 + .if ( FUNCTION_TYPE == DOUBLE_FUNCTION ) + add t3,arg2,4 + load 0,0,t3,t3 + .endif + .else + add t2,arg2,0 + .if ( FUNCTION_TYPE == DOUBLE_FUNCTION ) + add t3,%%(&arg2+1),0 + .endif + .endif + .else + .err + .print "Function argument not register - @arg2@" + .endif + .endif + + .endm ; end of prepare_function_parameters macro definition + +; end of smartmac.h file

smartmac.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property

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