URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/tags/or1ksim/or1ksim-0.3.0/build/doc
- from Rev 19 to Rev 21
- ↔ Reverse comparison
Rev 19 → Rev 21
/or1ksim.aux
0,0 → 1,135
@xrdef{Top-title}{Scope of this Document} |
@xrdef{Top-snt}{} |
@xrdef{Top-pg}{1} |
@xrdef{Installation-title}{Installation} |
@xrdef{Installation-snt}{Chapter@tie 1} |
@xrdef{Installation-pg}{2} |
@xrdef{Usage-title}{Usage} |
@xrdef{Usage-snt}{Chapter@tie 2} |
@xrdef{Standalone Simulator-title}{Standalone Simulator} |
@xrdef{Standalone Simulator-snt}{Section@tie 2.1} |
@xrdef{Profiling Utility-title}{Profiling Utility} |
@xrdef{Profiling Utility-snt}{Section@tie 2.2} |
@xrdef{Usage-pg}{3} |
@xrdef{Standalone Simulator-pg}{3} |
@xrdef{Profiling Utility-pg}{3} |
@xrdef{Memory Profiling Utility-title}{Memory Profiling Utility} |
@xrdef{Memory Profiling Utility-snt}{Section@tie 2.3} |
@xrdef{Simulator Library-title}{Simulator Library} |
@xrdef{Simulator Library-snt}{Section@tie 2.4} |
@xrdef{Memory Profiling Utility-pg}{4} |
@xrdef{Simulator Library-pg}{5} |
@xrdef{Configuration-title}{Configuration} |
@xrdef{Configuration-snt}{Chapter@tie 3} |
@xrdef{Configuration File Format-title}{Configuration File Format} |
@xrdef{Configuration File Format-snt}{Section@tie 3.1} |
@xrdef{Configuration File Preprocessing-title}{Configuration File Preprocessing} |
@xrdef{Configuration File Preprocessing-snt}{Section@tie 3.1.1} |
@xrdef{Configuration File Syntax-title}{Configuration File Syntax} |
@xrdef{Configuration File Syntax-snt}{Section@tie 3.1.2} |
@xrdef{Configuration-pg}{7} |
@xrdef{Configuration File Format-pg}{7} |
@xrdef{Configuration File Preprocessing-pg}{7} |
@xrdef{Configuration File Syntax-pg}{7} |
@xrdef{Simulator Configuration-title}{Simulator Configuration} |
@xrdef{Simulator Configuration-snt}{Section@tie 3.2} |
@xrdef{Simulator Behavior-title}{Simulator Behavior} |
@xrdef{Simulator Behavior-snt}{Section@tie 3.2.1} |
@xrdef{Simulator Configuration-pg}{8} |
@xrdef{Simulator Behavior-pg}{8} |
@xrdef{Verification API Configuration-title}{Verification API (VAPI) Configuration} |
@xrdef{Verification API Configuration-snt}{Section@tie 3.2.2} |
@xrdef{Verification API Configuration-pg}{9} |
@xrdef{CUC Configuration-title}{Custom Unit Compiler (CUC) Configuration} |
@xrdef{CUC Configuration-snt}{Section@tie 3.2.3} |
@xrdef{CUC Configuration-pg}{10} |
@xrdef{Core OpenRISC Configuration-title}{Configuring the OpenRISC Architectural Components} |
@xrdef{Core OpenRISC Configuration-snt}{Section@tie 3.3} |
@xrdef{CPU Configuration-title}{CPU Configuration} |
@xrdef{CPU Configuration-snt}{Section@tie 3.3.1} |
@xrdef{Core OpenRISC Configuration-pg}{11} |
@xrdef{CPU Configuration-pg}{11} |
@xrdef{Memory Configuration-title}{Memory Configuration} |
@xrdef{Memory Configuration-snt}{Section@tie 3.3.2} |
@xrdef{Memory Configuration-pg}{12} |
@xrdef{Memory Management Configuration-title}{Memory Management Configuration} |
@xrdef{Memory Management Configuration-snt}{Section@tie 3.3.3} |
@xrdef{Cache Configuration-title}{Cache Configuration} |
@xrdef{Cache Configuration-snt}{Section@tie 3.3.4} |
@xrdef{Memory Management Configuration-pg}{14} |
@xrdef{Interrupt Configuration-title}{Interrupt Configuration} |
@xrdef{Interrupt Configuration-snt}{Section@tie 3.3.5} |
@xrdef{Cache Configuration-pg}{15} |
@xrdef{Interrupt Configuration-pg}{15} |
@xrdef{Power Management Configuration-title}{Power Management Configuration} |
@xrdef{Power Management Configuration-snt}{Section@tie 3.3.6} |
@xrdef{Branch Prediction Configuration-title}{Branch Prediction Configuration} |
@xrdef{Branch Prediction Configuration-snt}{Section@tie 3.3.7} |
@xrdef{Power Management Configuration-pg}{16} |
@xrdef{Branch Prediction Configuration-pg}{16} |
@xrdef{Debug Interface Configuration-title}{Debug Interface Configuration} |
@xrdef{Debug Interface Configuration-snt}{Section@tie 3.3.8} |
@xrdef{Peripheral Configuration-title}{Configuring Memory Mapped Peripherals} |
@xrdef{Peripheral Configuration-snt}{Section@tie 3.4} |
@xrdef{Memory Controller Configuration-title}{Memory Controller Configuration} |
@xrdef{Memory Controller Configuration-snt}{Section@tie 3.4.1} |
@xrdef{Debug Interface Configuration-pg}{17} |
@xrdef{Peripheral Configuration-pg}{17} |
@xrdef{Memory Controller Configuration-pg}{17} |
@xrdef{UART Configuration-title}{UART Configuration} |
@xrdef{UART Configuration-snt}{Section@tie 3.4.2} |
@xrdef{UART Configuration-pg}{18} |
@xrdef{DMA Configuration-title}{DMA Configuration} |
@xrdef{DMA Configuration-snt}{Section@tie 3.4.3} |
@xrdef{DMA Configuration-pg}{19} |
@xrdef{Ethernet Configuration-title}{Ethernet Configuration} |
@xrdef{Ethernet Configuration-snt}{Section@tie 3.4.4} |
@xrdef{Ethernet Configuration-pg}{20} |
@xrdef{GPIO Configuration-title}{GPIO Configuration} |
@xrdef{GPIO Configuration-snt}{Section@tie 3.4.5} |
@xrdef{GPIO Configuration-pg}{21} |
@xrdef{Display Interface Configuration-title}{Display Interface Configuration} |
@xrdef{Display Interface Configuration-snt}{Section@tie 3.4.6} |
@xrdef{Frame Buffer Configuration-title}{Frame Buffer Configuration} |
@xrdef{Frame Buffer Configuration-snt}{Section@tie 3.4.7} |
@xrdef{Display Interface Configuration-pg}{22} |
@xrdef{Frame Buffer Configuration-pg}{22} |
@xrdef{Keyboard Configuration-title}{Keyboard Configuration (PS2)} |
@xrdef{Keyboard Configuration-snt}{Section@tie 3.4.8} |
@xrdef{Disc Interface Configuration-title}{Disc Interface Configuration} |
@xrdef{Disc Interface Configuration-snt}{Section@tie 3.4.9} |
@xrdef{Keyboard Configuration-pg}{23} |
@xrdef{Disc Interface Configuration-pg}{24} |
@xrdef{Generic Peripheral Configuration-title}{Generic Peripheral Configuration} |
@xrdef{Generic Peripheral Configuration-snt}{Section@tie 3.4.10} |
@xrdef{Generic Peripheral Configuration-pg}{25} |
@xrdef{Interactive Command Line-title}{Interactive Command Line} |
@xrdef{Interactive Command Line-snt}{Chapter@tie 4} |
@xrdef{Interactive Command Line-pg}{27} |
@xrdef{Verification API-title}{Verification API (VAPI)} |
@xrdef{Verification API-snt}{Chapter@tie 5} |
@xrdef{Verification API-pg}{30} |
@xrdef{Code Internals-title}{A Guide to @value {OR1KSIM} Internals} |
@xrdef{Code Internals-snt}{Chapter@tie 6} |
@xrdef{Coding Conventions-title}{Coding Conventions for @value {OR1KSIM}} |
@xrdef{Coding Conventions-snt}{Section@tie 6.1} |
@xrdef{Code Internals-pg}{32} |
@xrdef{Coding Conventions-pg}{32} |
@xrdef{Global Data Structures-title}{Global Data Structures} |
@xrdef{Global Data Structures-snt}{Section@tie 6.2} |
@xrdef{Global Data Structures-pg}{33} |
@xrdef{Concepts-title}{Concepts} |
@xrdef{Concepts-snt}{Section@tie 6.3} |
@xrdef{Output Redirection-title}{Concepts} |
@xrdef{Output Redirection-snt}{} |
@xrdef{Internal Debugging-title}{Internal Debugging} |
@xrdef{Internal Debugging-snt}{Section@tie 6.4} |
@xrdef{Concepts-pg}{34} |
@xrdef{Output Redirection-pg}{34} |
@xrdef{Internal Debugging-pg}{34} |
@xrdef{GNU Free Documentation License-title}{GNU Free Documentation License} |
@xrdef{GNU Free Documentation License-snt}{Chapter@tie 7} |
@xrdef{GNU Free Documentation License-pg}{35} |
@xrdef{Index-title}{Index} |
@xrdef{Index-snt}{} |
@xrdef{Index-pg}{42} |
/or1ksim.log
0,0 → 1,268
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Chapter 1 |
[1] Chapter 2 [2] [3] [4] [5] Chapter 3 [6] [7] [8] |
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[9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] |
[24] [25] Chapter 4 [26] [27] [28] Chapter 5 [29] |
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[33] Chapter 7 [34] |
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/or1ksim.cp
0,0 → 1,461
\entry{installing Or1ksim}{2}{installing Or1ksim} |
\entry{--enable-ethphy}{2}{\code {--enable-ethphy}} |
\entry{Ethernet via socket, enabling}{2}{Ethernet via socket, enabling} |
\entry{enabling Ethernet via socket}{2}{enabling Ethernet via socket} |
\entry{running Or1ksim}{3}{running Or1ksim} |
\entry{command line for Or1ksim standalone use}{3}{command line for Or1ksim standalone use} |
\entry{-v}{3}{\code {-v}} |
\entry{--version}{3}{\code {--version}} |
\entry{-h}{3}{\code {-h}} |
\entry{--help}{3}{\code {--help}} |
\entry{-f}{3}{\code {-f}} |
\entry{--file}{3}{\code {--file}} |
\entry{--nosrv}{3}{\code {--nosrv}} |
\entry{--srv}{3}{\code {--srv}} |
\entry{-d}{3}{\code {-d}} |
\entry{--debug-config}{3}{\code {--debug-config}} |
\entry{-i}{3}{\code {-i}} |
\entry{--interactive}{3}{\code {--interactive}} |
\entry{--enable-profile}{3}{\code {--enable-profile}} |
\entry{--enable-mprofile}{3}{\code {--enable-mprofile}} |
\entry{profiling for Or1ksim}{3}{profiling for Or1ksim} |
\entry{instruction profiling for Or1ksim}{3}{instruction profiling for Or1ksim} |
\entry{-v (profiling utility)}{4}{\code {-v} (profiling utility)} |
\entry{--version (profiling utility)}{4}{\code {--version} (profiling utility)} |
\entry{-h (profiling utility)}{4}{\code {-h} (profiling utility)} |
\entry{--help (profiling utility)}{4}{\code {--help} (profiling utility)} |
\entry{-c}{4}{\code {-c}} |
\entry{--cumulative}{4}{\code {--cumulative}} |
\entry{-q}{4}{\code {-q}} |
\entry{--quiet}{4}{\code {--quiet}} |
\entry{-g}{4}{\code {-g}} |
\entry{--generate}{4}{\code {--generate}} |
\entry{memory profiling version of Or1ksim}{4}{memory profiling version of Or1ksim} |
\entry{-v (memory profiling utility)}{4}{\code {-v} (memory profiling utility)} |
\entry{--version (memory profiling utility)}{4}{\code {--version} (memory profiling utility)} |
\entry{-h (memory profiling utility)}{4}{\code {-h} (memory profiling utility)} |
\entry{--help (memory profiling utility)}{4}{\code {--help} (memory profiling utility)} |
\entry{-m}{4}{\code {-m}} |
\entry{--mode}{4}{\code {--mode}} |
\entry{-g}{4}{\code {-g}} |
\entry{--group}{4}{\code {--group}} |
\entry{-f}{4}{\code {-f}} |
\entry{--filename}{4}{\code {--filename}} |
\entry{memory profiling start address}{4}{memory profiling start address} |
\entry{memory profiling end address}{4}{memory profiling end address} |
\entry{library version of Or1ksim}{5}{library version of Or1ksim} |
\entry{or1ksim_init}{5}{\code {or1ksim_init}} |
\entry{or1ksim_run}{5}{\code {or1ksim_run}} |
\entry{or1ksim_reset_duration}{5}{\code {or1ksim_reset_duration}} |
\entry{or1ksim_set_time_point}{5}{\code {or1ksim_set_time_point}} |
\entry{or1ksim_get_time_period}{5}{\code {or1ksim_get_time_period}} |
\entry{or1ksim_is_le}{5}{\code {or1ksim_is_le}} |
\entry{long}{5}{\code {long}} |
\entry{or1ksim_interrupt}{5}{\code {or1ksim_interrupt}} |
\entry{configuring Or1ksim}{7}{configuring Or1ksim} |
\entry{configuration file structure}{7}{configuration file structure} |
\entry{configuring the behavior of Or1ksim}{8}{configuring the behavior of Or1ksim} |
\entry{simulator configuration}{8}{simulator configuration} |
\entry{section sim}{8}{\code {section sim}} |
\entry{verbose (simulator configuration)}{8}{\code {verbose} (simulator configuration)} |
\entry{debug (simulator configuration)}{8}{\code {debug} (simulator configuration)} |
\entry{profile (simulator configuration)}{8}{\code {profile} (simulator configuration)} |
\entry{prof_file (simulator configuration)}{8}{\code {prof_file} (simulator configuration)} |
\entry{prof_fn (simulator configuration - deprecated)}{8}{\code {prof_fn} (simulator configuration - deprecated)} |
\entry{mprofile (simulator configuration)}{8}{\code {mprofile} (simulator configuration)} |
\entry{mprof_file (simulator configuration)}{8}{\code {mprof_file} (simulator configuration)} |
\entry{mprof_fn (simulator configuration - deprecated)}{8}{\code {mprof_fn} (simulator configuration - deprecated)} |
\entry{history (simulator configuration)}{8}{\code {history} (simulator configuration)} |
\entry{exe_log (simulator configuration)}{9}{\code {exe_log} (simulator configuration)} |
\entry{exe_log_type (simulator configuration)}{9}{\code {exe_log_type} (simulator configuration)} |
\entry{exe_log_type=default (simulator configuration)}{9}{\code {exe_log_type=default} (simulator configuration)} |
\entry{exe_log_type=hardware (simulator configuration)}{9}{\code {exe_log_type=hardware} (simulator configuration)} |
\entry{exe_log_type=simple (simulator configuration)}{9}{\code {exe_log_type=simple} (simulator configuration)} |
\entry{exe_log_type=software (simulator configuration)}{9}{\code {exe_log_type=software} (simulator configuration)} |
\entry{exe_log_start (simulator configuration)}{9}{\code {exe_log_start} (simulator configuration)} |
\entry{exe_log_end (simulator configuration)}{9}{\code {exe_log_end} (simulator configuration)} |
\entry{exe_log_marker (simulator configuration)}{9}{\code {exe_log_marker} (simulator configuration)} |
\entry{exe_log_file (simulator configuration)}{9}{\code {exe_log_file} (simulator configuration)} |
\entry{exe_log_fn (simulator configuration - deprecated)}{9}{\code {exe_log_fn} (simulator configuration - deprecated)} |
\entry{clkcycle (simulator configuration)}{9}{\code {clkcycle} (simulator configuration)} |
\entry{configuring the Verification API (VAPI)}{9}{configuring the Verification API (VAPI)} |
\entry{Verification API configuration}{9}{Verification API configuration} |
\entry{VAPI configuration}{9}{VAPI configuration} |
\entry{section vapi}{9}{\code {section vapi}} |
\entry{enabled (verification API configuration)}{10}{\code {enabled} (verification API configuration)} |
\entry{server_port (verification API configuration)}{10}{\code {server_port} (verification API configuration)} |
\entry{TCP/IP port range}{10}{TCP/IP port range} |
\entry{port range for TCP/IP}{10}{port range for TCP/IP} |
\entry{dynamic ports, use of}{10}{dynamic ports, use of} |
\entry{private ports, use of}{10}{private ports, use of} |
\entry{log_enabled (verification API configuration)}{10}{\code {log_enabled} (verification API configuration)} |
\entry{hide_device_id (verification API configuration)}{10}{\code {hide_device_id} (verification API configuration)} |
\entry{vapi_log_file (verification API configuration)}{10}{\code {vapi_log_file} (verification API configuration)} |
\entry{vapi_log_fn (verification API configuration - deprecated)}{10}{\code {vapi_log_fn} (verification API configuration - deprecated)} |
\entry{configuring the Custom Unit Compiler (CUC)}{10}{configuring the Custom Unit Compiler (CUC)} |
\entry{Custom Unit Compiler Configuration}{10}{Custom Unit Compiler Configuration} |
\entry{CUC configuration}{10}{CUC configuration} |
\entry{section cuc}{10}{\code {section cuc}} |
\entry{memory_order (CUC configuration)}{10}{\code {memory_order} (CUC configuration)} |
\entry{memory_order=none (CUC configuration)}{10}{\code {memory_order=none} (CUC configuration)} |
\entry{memory_order=weak (CUC configuration)}{10}{\code {memory_order=weak} (CUC configuration)} |
\entry{memory_order=strong (CUC configuration)}{10}{\code {memory_order=strong} (CUC configuration)} |
\entry{memory_order=exact (CUC configuration)}{10}{\code {memory_order=exact} (CUC configuration)} |
\entry{calling_convention (CUC configuration)}{10}{\code {calling_convention} (CUC configuration)} |
\entry{enable_bursts (CUC configuration)}{10}{\code {enable_bursts} (CUC configuration)} |
\entry{no_multicycle (CUC configuration)}{11}{\code {no_multicycle} (CUC configuration)} |
\entry{timings_file (CUC configuration)}{11}{\code {timings_file} (CUC configuration)} |
\entry{timings_fn (CUC configuration - deprecated)}{11}{\code {timings_fn} (CUC configuration - deprecated)} |
\entry{configuring the CPU}{11}{configuring the CPU} |
\entry{configuring the processor}{11}{configuring the processor} |
\entry{CPU configuration}{11}{CPU configuration} |
\entry{processor configuration}{11}{processor configuration} |
\entry{section cpu}{11}{\code {section cpu}} |
\entry{ver (CPU configuration)}{11}{\code {ver} (CPU configuration)} |
\entry{rev (CPU configuration)}{11}{\code {rev} (CPU configuration)} |
\entry{upr (CPU configuration)}{11}{\code {upr} (CPU configuration)} |
\entry{cfgr (CPU configuration)}{11}{\code {cfgr} (CPU configuration)} |
\entry{sr (CPU configuration)}{11}{\code {sr} (CPU configuration)} |
\entry{superscalar (CPU configuration)}{11}{\code {superscalar} (CPU configuration)} |
\entry{hazards (CPU configuration)}{12}{\code {hazards} (CPU configuration)} |
\entry{dependstats (CPU configuration)}{12}{\code {dependstats} (CPU configuration)} |
\entry{sbuf_len (CPU configuration)}{12}{\code {sbuf_len} (CPU configuration)} |
\entry{configuring memory}{12}{configuring memory} |
\entry{memory configuration}{12}{memory configuration} |
\entry{section memory}{12}{\code {section memory}} |
\entry{type (memory configuration)}{12}{\code {type} (memory configuration)} |
\entry{type=random (memory configuration)}{12}{\code {type=random} (memory configuration)} |
\entry{type=pattern (memory configuration)}{12}{\code {type=pattern} (memory configuration)} |
\entry{type=unknown (memory configuration)}{12}{\code {type=unknown} (memory configuration)} |
\entry{type=zero (memory configuration)}{12}{\code {type=zero} (memory configuration)} |
\entry{random_seed (memory configuration)}{12}{\code {random_seed} (memory configuration)} |
\entry{pattern (memory configuration)}{13}{\code {pattern} (memory configuration)} |
\entry{baseaddr (memory configuration)}{13}{\code {baseaddr} (memory configuration)} |
\entry{size (memory configuration)}{13}{\code {size} (memory configuration)} |
\entry{name (memory configuration)}{13}{\code {name} (memory configuration)} |
\entry{ce (memory configuration)}{13}{\code {ce} (memory configuration)} |
\entry{mc (memory configuration)}{13}{\code {mc} (memory configuration)} |
\entry{delayr (memory configuration)}{13}{\code {delayr} (memory configuration)} |
\entry{delayw (memory configuration)}{14}{\code {delayw} (memory configuration)} |
\entry{log (memory configuration)}{14}{\code {log} (memory configuration)} |
\entry{configuring data & instruction MMUs}{14}{configuring data & instruction MMUs} |
\entry{MMU configuration}{14}{MMU configuration} |
\entry{DMMU configuration}{14}{DMMU configuration} |
\entry{data MMU configuration}{14}{data MMU configuration} |
\entry{IMMU configuration}{14}{IMMU configuration} |
\entry{instruction MMU configuration}{14}{instruction MMU configuration} |
\entry{section dmmu}{14}{\code {section dmmu}} |
\entry{section immu}{14}{\code {section immu}} |
\entry{enabled (MMU configuration)}{14}{\code {enabled} (MMU configuration)} |
\entry{nsets (MMU configuration)}{14}{\code {nsets} (MMU configuration)} |
\entry{nways (MMU configuration)}{14}{\code {nways} (MMU configuration)} |
\entry{pagesize (MMU configuration)}{14}{\code {pagesize} (MMU configuration)} |
\entry{entrysize (MMU configuration)}{14}{\code {entrysize} (MMU configuration)} |
\entry{ustates (MMU configuration)}{14}{\code {ustates} (MMU configuration)} |
\entry{hitdelay (MMU configuration)}{14}{\code {hitdelay} (MMU configuration)} |
\entry{missdelay (MMU configuration)}{14}{\code {missdelay} (MMU configuration)} |
\entry{configuring data & instruction caches}{15}{configuring data & instruction caches} |
\entry{cache configuration}{15}{cache configuration} |
\entry{data cache configuration}{15}{data cache configuration} |
\entry{instruction cache configuration}{15}{instruction cache configuration} |
\entry{section dc}{15}{\code {section dc}} |
\entry{section ic}{15}{\code {section ic}} |
\entry{enabled (cache configuration)}{15}{\code {enabled} (cache configuration)} |
\entry{nsets (cache configuration)}{15}{\code {nsets} (cache configuration)} |
\entry{nways (cache configuration)}{15}{\code {nways} (cache configuration)} |
\entry{blocksize (cache configuration)}{15}{\code {blocksize} (cache configuration)} |
\entry{ustates (cache configuration)}{15}{\code {ustates} (cache configuration)} |
\entry{hitdelay (instruction cache configuration)}{15}{\code {hitdelay} (instruction cache configuration)} |
\entry{missdelay (instruction cache configuration)}{15}{\code {missdelay} (instruction cache configuration)} |
\entry{load_hitdelay (data cache configuration)}{15}{\code {load_hitdelay} (data cache configuration)} |
\entry{load_missdelay (data cache configuration)}{15}{\code {load_missdelay} (data cache configuration)} |
\entry{store_hitdelay (data cache configuration)}{15}{\code {store_hitdelay} (data cache configuration)} |
\entry{store_missdelay (data cache configuration)}{15}{\code {store_missdelay} (data cache configuration)} |
\entry{configuring the interrupt controller}{15}{configuring the interrupt controller} |
\entry{interrupt controller configuration}{15}{interrupt controller configuration} |
\entry{programmable interrupt controller configuration}{15}{programmable interrupt controller configuration} |
\entry{PIC configuration}{15}{PIC configuration} |
\entry{section pic}{15}{\code {section pic}} |
\entry{enabled (interrupt controller)}{16}{\code {enabled} (interrupt controller)} |
\entry{edge_trigger (interrupt controller)}{16}{\code {edge_trigger} (interrupt controller)} |
\entry{configuring power management}{16}{configuring power management} |
\entry{power management configuration}{16}{power management configuration} |
\entry{PMU configuration}{16}{PMU configuration} |
\entry{section pmu}{16}{\code {section pmu}} |
\entry{SDF (power management register)}{16}{SDF (power management register)} |
\entry{slow down factor (power management register)}{16}{slow down factor (power management register)} |
\entry{power management register, SDF}{16}{power management register, SDF} |
\entry{PMR - SDF}{16}{PMR - SDF} |
\entry{DME (power management register)}{16}{DME (power management register)} |
\entry{doze mode (power management register)}{16}{doze mode (power management register)} |
\entry{power management register, DME}{16}{power management register, DME} |
\entry{PMR - DME}{16}{PMR - DME} |
\entry{SME (power management register)}{16}{SME (power management register)} |
\entry{sleep mode (power management register)}{16}{sleep mode (power management register)} |
\entry{power management register, SME}{16}{power management register, SME} |
\entry{PMR - SME}{16}{PMR - SME} |
\entry{DCGE (power management register)}{16}{DCGE (power management register)} |
\entry{dynamic clock gating (power management register)}{16}{dynamic clock gating (power management register)} |
\entry{power management register, DGCE}{16}{power management register, DGCE} |
\entry{PMR - DGCE}{16}{PMR - DGCE} |
\entry{SUME (power management register)}{16}{SUME (power management register)} |
\entry{suspend mode (power management register)}{16}{suspend mode (power management register)} |
\entry{power management register, SUME}{16}{power management register, SUME} |
\entry{PMR - SUME}{16}{PMR - SUME} |
\entry{enabled (power management configuration)}{16}{\code {enabled} (power management configuration)} |
\entry{configuring branch prediction}{16}{configuring branch prediction} |
\entry{branch prediction configuration}{16}{branch prediction configuration} |
\entry{BPB configuration}{16}{BPB configuration} |
\entry{section bpb}{16}{\code {section bpb}} |
\entry{enabled (branch prediction configuration)}{16}{\code {enabled} (branch prediction configuration)} |
\entry{btic (branch prediction configuration)}{16}{\code {btic} (branch prediction configuration)} |
\entry{sbp_bf_fwd (branch prediction configuration)}{16}{\code {sbp_bf_fwd} (branch prediction configuration)} |
\entry{sbp_bnf_fwd (branch prediction configuration)}{16}{\code {sbp_bnf_fwd} (branch prediction configuration)} |
\entry{hitdelay (branch prediction configuration)}{16}{\code {hitdelay} (branch prediction configuration)} |
\entry{missdelay (branch prediction configuration)}{17}{\code {missdelay} (branch prediction configuration)} |
\entry{configuring the debug unit and interface to external debuggers}{17}{configuring the debug unit and interface to external debuggers} |
\entry{debug unit configuration}{17}{debug unit configuration} |
\entry{debug interface configuration}{17}{debug interface configuration} |
\entry{section debug}{17}{\code {section debug}} |
\entry{enabled (debug interface configuration)}{17}{\code {enabled} (debug interface configuration)} |
\entry{gdb_enabled (debug interface configuration)}{17}{\code {gdb_enabled} (debug interface configuration)} |
\entry{server_port (debug interface configuration)}{17}{\code {server_port} (debug interface configuration)} |
\entry{TCP/IP port range for or1ksim service}{17}{TCP/IP port range for \code {or1ksim} service} |
\entry{vapi_id (debug interface configuration)}{17}{\code {vapi_id} (debug interface configuration)} |
\entry{configuring the memory controller}{17}{configuring the memory controller} |
\entry{memory controller configuration}{17}{memory controller configuration} |
\entry{section mc}{17}{\code {section mc}} |
\entry{enabled (memory controller configuration)}{18}{\code {enabled} (memory controller configuration)} |
\entry{baseaddr (memory controller configuration)}{18}{\code {baseaddr} (memory controller configuration)} |
\entry{poc (memory controller configuration)}{18}{\code {poc} (memory controller configuration)} |
\entry{index (memory controller configuration)}{18}{\code {index} (memory controller configuration)} |
\entry{configuring the UART}{18}{configuring the UART} |
\entry{UART configuration}{18}{UART configuration} |
\entry{section uart}{18}{\code {section uart}} |
\entry{enabled (UART configuration)}{18}{\code {enabled} (UART configuration)} |
\entry{baseaddr (UART configuration)}{18}{\code {baseaddr} (UART configuration)} |
\entry{channel (UART configuration)}{18}{\code {channel} (UART configuration)} |
\entry{UART I/O from/to files}{19}{UART I/O from/to files} |
\entry{UART I/O from/to an xterm}{19}{UART I/O from/to an \command {xterm}} |
\entry{UART I/O from/to TCP/IP}{19}{UART I/O from/to TCP/IP} |
\entry{UART I/O from/to open file descriptors}{19}{UART I/O from/to open file descriptors} |
\entry{UART I/O from/to a physical serial port}{19}{UART I/O from/to a physical serial port} |
\entry{irq (UART configuration)}{19}{\code {irq} (UART configuration)} |
\entry{16550 (UART configuration)}{19}{\code {16550} (UART configuration)} |
\entry{jitter (UART configuration)}{19}{\code {jitter} (UART configuration)} |
\entry{vapi_id (UART configuration)}{19}{\code {vapi_id} (UART configuration)} |
\entry{configuring DMA}{19}{configuring DMA} |
\entry{DMA configuration}{19}{DMA configuration} |
\entry{section dma}{19}{\code {section dma}} |
\entry{enabled (DMA configuration)}{20}{\code {enabled} (DMA configuration)} |
\entry{baseaddr (DMA configuration)}{20}{\code {baseaddr} (DMA configuration)} |
\entry{irq (DMA configuration)}{20}{\code {irq} (DMA configuration)} |
\entry{vapi_id (DMA configuration)}{20}{\code {vapi_id} (DMA configuration)} |
\entry{configuring the Ethernet interface}{20}{configuring the Ethernet interface} |
\entry{Ethernet configuration}{20}{Ethernet configuration} |
\entry{section ethernet}{20}{\code {section ethernet}} |
\entry{enabled (Ethernet configuration)}{20}{\code {enabled} (Ethernet configuration)} |
\entry{baseaddr (Ethernet configuration)}{20}{\code {baseaddr} (Ethernet configuration)} |
\entry{dma (Ethernet configuration)}{20}{\code {dma} (Ethernet configuration)} |
\entry{dma (Ethernet configuration)}{20}{\code {dma} (Ethernet configuration)} |
\entry{rtx_type (Ethernet configuration)}{21}{\code {rtx_type} (Ethernet configuration)} |
\entry{rx_channel (Ethernet configuration)}{21}{\code {rx_channel} (Ethernet configuration)} |
\entry{tx_channel (Ethernet configuration)}{21}{\code {tx_channel} (Ethernet configuration)} |
\entry{rxfile (Ethernet configuration)}{21}{\code {rxfile} (Ethernet configuration)} |
\entry{txfile (Ethernet configuration)}{21}{\code {txfile} (Ethernet configuration)} |
\entry{sockif (Ethernet configuration)}{21}{\code {sockif} (Ethernet configuration)} |
\entry{vapi_id (DMA configuration)}{21}{\code {vapi_id} (DMA configuration)} |
\entry{configuring the GPIO}{21}{configuring the GPIO} |
\entry{GPIO configuration}{21}{GPIO configuration} |
\entry{section cpio}{21}{\code {section cpio}} |
\entry{enabled (GPIO configuration)}{21}{\code {enabled} (GPIO configuration)} |
\entry{baseaddr (GPIO configuration)}{21}{\code {baseaddr} (GPIO configuration)} |
\entry{irq (GPIO configuration)}{22}{\code {irq} (GPIO configuration)} |
\entry{vapi_id (GPIO configuration)}{22}{\code {vapi_id} (GPIO configuration)} |
\entry{base_vapi_id (GPIO configuration - deprecated)}{22}{\code {base_vapi_id} (GPIO configuration - deprecated)} |
\entry{configuring the VGA interface}{22}{configuring the VGA interface} |
\entry{display interface configuration}{22}{display interface configuration} |
\entry{VGA configuration}{22}{VGA configuration} |
\entry{section vga}{22}{\code {section vga}} |
\entry{enabled (VGA configuration)}{22}{\code {enabled} (VGA configuration)} |
\entry{baseaddr (VGA configuration)}{22}{\code {baseaddr} (VGA configuration)} |
\entry{irq (VGA configuration)}{22}{\code {irq} (VGA configuration)} |
\entry{refresh_rate (VGA configuration)}{22}{\code {refresh_rate} (VGA configuration)} |
\entry{txfile (VGA configuration)}{22}{\code {txfile} (VGA configuration)} |
\entry{filename (VGA configuration - deprecated)}{22}{\code {filename} (VGA configuration - deprecated)} |
\entry{configuring the frame buffer}{22}{configuring the frame buffer} |
\entry{frame buffer configuration}{22}{frame buffer configuration} |
\entry{section fb}{22}{\code {section fb}} |
\entry{enabled (frame buffer configuration)}{22}{\code {enabled} (frame buffer configuration)} |
\entry{baseaddr (frame buffer configuration)}{23}{\code {baseaddr} (frame buffer configuration)} |
\entry{refresh_rate (frame buffer configuration)}{23}{\code {refresh_rate} (frame buffer configuration)} |
\entry{txfile (frame buffer configuration)}{23}{\code {txfile} (frame buffer configuration)} |
\entry{filename (frame buffer configuration - deprecated)}{23}{\code {filename} (frame buffer configuration - deprecated)} |
\entry{configuring the keyboard interface}{23}{configuring the keyboard interface} |
\entry{configuring the PS2 interface}{23}{configuring the PS2 interface} |
\entry{keyboard configuration}{23}{keyboard configuration} |
\entry{PS2 configuration}{23}{PS2 configuration} |
\entry{section kb}{23}{\code {section kb}} |
\entry{enabled (keyboard configuration)}{23}{\code {enabled} (keyboard configuration)} |
\entry{baseaddr (keyboard configuration)}{23}{\code {baseaddr} (keyboard configuration)} |
\entry{irq (keyboard configuration)}{23}{\code {irq} (keyboard configuration)} |
\entry{file (keyboard configuration)}{23}{\code {file} (keyboard configuration)} |
\entry{configuring the ATA/ATAPI interfaces}{24}{configuring the ATA/ATAPI interfaces} |
\entry{disc interface configuration}{24}{disc interface configuration} |
\entry{ATA/ATAPI configuration}{24}{ATA/ATAPI configuration} |
\entry{section ata}{24}{\code {section ata}} |
\entry{enabled (ATA/ATAPI configuration)}{24}{\code {enabled} (ATA/ATAPI configuration)} |
\entry{baseaddr (ATA/ATAPI configuration)}{24}{\code {baseaddr} (ATA/ATAPI configuration)} |
\entry{irq (ATA/ATAPI configuration)}{24}{\code {irq} (ATA/ATAPI configuration)} |
\entry{dev_id (ATA/ATAPI configuration)}{24}{\code {dev_id} (ATA/ATAPI configuration)} |
\entry{rev (ATA/ATAPI configuration)}{24}{\code {rev} (ATA/ATAPI configuration)} |
\entry{pio_mode0_t1 (ATA/ATAPI configuration)}{24}{\code {pio_mode0_t1} (ATA/ATAPI configuration)} |
\entry{pio_mode0_t2 (ATA/ATAPI configuration)}{24}{\code {pio_mode0_t2} (ATA/ATAPI configuration)} |
\entry{pio_mode0_t4 (ATA/ATAPI configuration)}{24}{\code {pio_mode0_t4} (ATA/ATAPI configuration)} |
\entry{pio_mode0_teoc (ATA/ATAPI configuration)}{24}{\code {pio_mode0_teoc} (ATA/ATAPI configuration)} |
\entry{dma_mode0_tm (ATA/ATAPI configuration)}{24}{\code {dma_mode0_tm} (ATA/ATAPI configuration)} |
\entry{dma_mode0_td (ATA/ATAPI configuration)}{24}{\code {dma_mode0_td} (ATA/ATAPI configuration)} |
\entry{dma_mode0_teoc (ATA/ATAPI configuration)}{24}{\code {dma_mode0_teoc} (ATA/ATAPI configuration)} |
\entry{disc interface device configuration}{25}{disc interface device configuration} |
\entry{ATA/ATAPI device configuration}{25}{ATA/ATAPI device configuration} |
\entry{type (ATA/ATAPI device configuration)}{25}{\code {type} (ATA/ATAPI device configuration)} |
\entry{file (ATA/ATAPI device configuration)}{25}{\code {file} (ATA/ATAPI device configuration)} |
\entry{size (ATA/ATAPI device configuration)}{25}{\code {size} (ATA/ATAPI device configuration)} |
\entry{packet (ATA/ATAPI device configuration)}{25}{\code {packet} (ATA/ATAPI device configuration)} |
\entry{firmware (ATA/ATAPI device configuration)}{25}{\code {firmware} (ATA/ATAPI device configuration)} |
\entry{heads (ATA/ATAPI device configuration)}{25}{\code {heads} (ATA/ATAPI device configuration)} |
\entry{sectors (ATA/ATAPI device configuration)}{25}{\code {sectors} (ATA/ATAPI device configuration)} |
\entry{mwdma (ATA/ATAPI device configuration)}{25}{\code {mwdma} (ATA/ATAPI device configuration)} |
\entry{pio (ATA/ATAPI device configuration)}{25}{\code {pio} (ATA/ATAPI device configuration)} |
\entry{generic peripheral configuration}{25}{generic peripheral configuration} |
\entry{configuration of generic peripherals}{25}{configuration of generic peripherals} |
\entry{section generic}{25}{\code {section generic}} |
\entry{enabled (generic peripheral configuration)}{26}{\code {enabled} (generic peripheral configuration)} |
\entry{baseaddr (generic peripheral configuration)}{26}{\code {baseaddr} (generic peripheral configuration)} |
\entry{size (generic peripheral configuration)}{26}{\code {size} (generic peripheral configuration)} |
\entry{name (generic peripheral configuration)}{26}{\code {name} (generic peripheral configuration)} |
\entry{byte_enabled (generic peripheral configuration)}{26}{\code {byte_enabled} (generic peripheral configuration)} |
\entry{hw_enabled (generic peripheral configuration)}{26}{\code {hw_enabled} (generic peripheral configuration)} |
\entry{word_enabled (generic peripheral configuration)}{26}{\code {word_enabled} (generic peripheral configuration)} |
\entry{q (Interactive CLI)}{27}{\code {q} (Interactive CLI)} |
\entry{quitting (Interactive CLI)}{27}{quitting (Interactive CLI)} |
\entry{r (Interactive CLI)}{27}{\code {r} (Interactive CLI)} |
\entry{displaying registers (Interactive CLI)}{27}{displaying registers (Interactive CLI)} |
\entry{register display (Interactive CLI)}{27}{register display (Interactive CLI)} |
\entry{t (Interactive CLI)}{27}{\code {t} (Interactive CLI)} |
\entry{stepping code (Interactive CLI)}{27}{stepping code (Interactive CLI)} |
\entry{run (Interactive CLI)}{27}{\code {run} (Interactive CLI)} |
\entry{running code (Interactive CLI)}{27}{running code (Interactive CLI)} |
\entry{executing code (Interactive CLI)}{27}{executing code (Interactive CLI)} |
\entry{pr (Interactive CLI)}{27}{\code {pr} (Interactive CLI)} |
\entry{patching registers (Interactive CLI)}{27}{patching registers (Interactive CLI)} |
\entry{register patching (Interactive CLI)}{27}{register patching (Interactive CLI)} |
\entry{dm (Interactive CLI)}{27}{\code {dm} (Interactive CLI)} |
\entry{displaying memory (Interactive CLI)}{27}{displaying memory (Interactive CLI)} |
\entry{memory display (Interactive CLI)}{27}{memory display (Interactive CLI)} |
\entry{dm (Interactive CLI)}{27}{\code {dm} (Interactive CLI)} |
\entry{disassemble (Interactive CLI)}{27}{disassemble (Interactive CLI)} |
\entry{pm (Interactive CLI)}{27}{\code {pm} (Interactive CLI)} |
\entry{patching memory (Interactive CLI)}{27}{patching memory (Interactive CLI)} |
\entry{memory patching (Interactive CLI)}{27}{memory patching (Interactive CLI)} |
\entry{pc (Interactive CLI)}{27}{\code {pc} (Interactive CLI)} |
\entry{patching the program counter (Interactive CLI)}{27}{patching the program counter (Interactive CLI)} |
\entry{program counter patching (Interactive CLI)}{27}{program counter patching (Interactive CLI)} |
\entry{cm (Interactive CLI)}{27}{\code {cm} (Interactive CLI)} |
\entry{copying memory (Interactive CLI)}{27}{copying memory (Interactive CLI)} |
\entry{memory copying (Interactive CLI)}{27}{memory copying (Interactive CLI)} |
\entry{break (Interactive CLI)}{27}{\code {break} (Interactive CLI)} |
\entry{breakpoint set/clear (Interactive CLI)}{27}{breakpoint set/clear (Interactive CLI)} |
\entry{set breakpoint (Interactive CLI)}{27}{set breakpoint (Interactive CLI)} |
\entry{clear breakpoint (Interactive CLI)}{27}{clear breakpoint (Interactive CLI)} |
\entry{toggle breakpoint (Interactive CLI)}{27}{toggle breakpoint (Interactive CLI)} |
\entry{breaks (Interactive CLI)}{27}{\code {breaks} (Interactive CLI)} |
\entry{breakpoint list (Interactive CLI)}{27}{breakpoint list (Interactive CLI)} |
\entry{list breakpoints (Interactive CLI)}{27}{list breakpoints (Interactive CLI)} |
\entry{reset (Interactive CLI)}{27}{\code {reset} (Interactive CLI)} |
\entry{simulator reset (Interactive CLI)}{27}{simulator reset (Interactive CLI)} |
\entry{reset the simulator (Interactive CLI)}{27}{reset the simulator (Interactive CLI)} |
\entry{hist (Interactive CLI)}{27}{\code {hist} (Interactive CLI)} |
\entry{execution history (Interactive CLI)}{27}{execution history (Interactive CLI)} |
\entry{history of execution (Interactive CLI)}{27}{history of execution (Interactive CLI)} |
\entry{stall (Interactive CLI)}{27}{\code {stall} (Interactive CLI)} |
\entry{processor stall (Interactive CLI)}{27}{processor stall (Interactive CLI)} |
\entry{stall the processor (Interactive CLI)}{27}{stall the processor (Interactive CLI)} |
\entry{stats (Interactive CLI)}{28}{\code {stats} (Interactive CLI)} |
\entry{simulator statistics (Interactive CLI)}{28}{simulator statistics (Interactive CLI)} |
\entry{statistics, simulation (Interactive CLI)}{28}{statistics, simulation (Interactive CLI)} |
\entry{info (Interactive CLI)}{28}{\code {info} (Interactive CLI)} |
\entry{simulator configuration info (Interactive CLI)}{28}{simulator configuration info (Interactive CLI)} |
\entry{configuration info (Interactive CLI)}{28}{configuration info (Interactive CLI)} |
\entry{dv (Interactive CLI)}{28}{\code {dv} (Interactive CLI)} |
\entry{Verilog memory dump (Interactive CLI)}{28}{Verilog memory dump (Interactive CLI)} |
\entry{memory dump, Verilog (Interactive CLI)}{28}{memory dump, Verilog (Interactive CLI)} |
\entry{dv (Interactive CLI)}{28}{\code {dv} (Interactive CLI)} |
\entry{hexadecimal memory dump (Interactive CLI)}{28}{hexadecimal memory dump (Interactive CLI)} |
\entry{memory dump, hexadecimal (Interactive CLI)}{28}{memory dump, hexadecimal (Interactive CLI)} |
\entry{setdbch (Interactive CLI)}{28}{\code {setdbch} (Interactive CLI)} |
\entry{debug channel toggle (Interactive CLI)}{28}{debug channel toggle (Interactive CLI)} |
\entry{toggle debug channels (Interactive CLI)}{28}{toggle debug channels (Interactive CLI)} |
\entry{set (Interactive CLI)}{28}{\code {set} (Interactive CLI)} |
\entry{configuration parameter setting (Interactive CLI)}{28}{configuration parameter setting (Interactive CLI)} |
\entry{debug (Interactive CLI)}{28}{\code {debug} (Interactive CLI)} |
\entry{debug mode toggle (Interactive CLI)}{28}{debug mode toggle (Interactive CLI)} |
\entry{toggle debug mode (Interactive CLI)}{28}{toggle debug mode (Interactive CLI)} |
\entry{debug (Interactive CLI)}{29}{\code {debug} (Interactive CLI)} |
\entry{Custom Unit Compiler (Interactive CLI)}{29}{Custom Unit Compiler (Interactive CLI)} |
\entry{help (Interactive CLI)}{29}{\code {help} (Interactive CLI)} |
\entry{Custom Unit Compiler (Interactive CLI)}{29}{Custom Unit Compiler (Interactive CLI)} |
\entry{mprofile (Interactive CLI)}{29}{\code {mprofile} (Interactive CLI)} |
\entry{memory profiling utility (Interactive CLI)}{29}{memory profiling utility (Interactive CLI)} |
\entry{mprofile (Interactive CLI)}{29}{\code {mprofile} (Interactive CLI)} |
\entry{profiling utility (Interactive CLI)}{29}{profiling utility (Interactive CLI)} |
\entry{instruction profiling utility (Interactive CLI)}{29}{instruction profiling utility (Interactive CLI)} |
\entry{Debug Unit verification (VAPI)}{30}{Debug Unit verification (VAPI)} |
\entry{VAPI for Debug Unit}{30}{VAPI for Debug Unit} |
\entry{UART verification (VAPI)}{30}{UART verification (VAPI)} |
\entry{VAPI for UART}{30}{VAPI for UART} |
\entry{0x00 UART VAPI sub-command (UART verification)}{30}{0x00 UART VAPI sub-command (UART verification)} |
\entry{0x01 UART VAPI sub-command (UART verification)}{30}{0x01 UART VAPI sub-command (UART verification)} |
\entry{0x02 UART VAPI sub-command (UART verification)}{30}{0x02 UART VAPI sub-command (UART verification)} |
\entry{0x03 UART VAPI sub-command (UART verification)}{30}{0x03 UART VAPI sub-command (UART verification)} |
\entry{0x04 UART VAPI sub-command (UART verification)}{30}{0x04 UART VAPI sub-command (UART verification)} |
\entry{DMA verification (VAPI)}{30}{DMA verification (VAPI)} |
\entry{VAPI for DMA}{30}{VAPI for DMA} |
\entry{Ethernet verification (VAPI)}{30}{Ethernet verification (VAPI)} |
\entry{VAPI for Ethernet}{30}{VAPI for Ethernet} |
\entry{ETH_VAPI_DATA (Ethernet verification)}{31}{\code {ETH_VAPI_DATA} (Ethernet verification)} |
\entry{ETH_VAPI_CTRL (Ethernet verification)}{31}{\code {ETH_VAPI_CTRL} (Ethernet verification)} |
\entry{GPIO verification (VAPI)}{31}{GPIO verification (VAPI)} |
\entry{VAPI for GPIO}{31}{VAPI for GPIO} |
\entry{GPIO_VAPI_DATA (GPIO verification)}{31}{\code {GPIO_VAPI_DATA} (GPIO verification)} |
\entry{GPIO_VAPI_AUX (GPIO verification)}{31}{\code {GPIO_VAPI_AUX} (GPIO verification)} |
\entry{GPIO_VAPI_CLOCK (GPIO verification)}{31}{\code {GPIO_VAPI_CLOCK} (GPIO verification)} |
\entry{GPIO_VAPI_RGPIO (GPIO verification)}{31}{\code {GPIO_VAPI_RGPIO} (GPIO verification)} |
\entry{GPIO_VAPI_INTE (GPIO verification)}{31}{\code {GPIO_VAPI_INTE} (GPIO verification)} |
\entry{GPIO_VAPI_PTRIG (GPIO verification)}{31}{\code {GPIO_VAPI_PTRIG} (GPIO verification)} |
\entry{GPIO_VAPI_AUX (GPIO verification)}{31}{\code {GPIO_VAPI_AUX} (GPIO verification)} |
\entry{GPIO_VAPI_CTRL (GPIO verification)}{31}{\code {GPIO_VAPI_CTRL} (GPIO verification)} |
\entry{configuration global structure}{33}{configuration global structure} |
\entry{config}{33}{\code {config}} |
\entry{config.sim}{33}{\code {config.sim}} |
\entry{config.vapi}{33}{\code {config.vapi}} |
\entry{config.cuc}{33}{\code {config.cuc}} |
\entry{config.cpu}{33}{\code {config.cpu}} |
\entry{config.dc}{33}{\code {config.dc}} |
\entry{config.pm}{33}{\code {config.pm}} |
\entry{config.pic}{34}{\code {config.pic}} |
\entry{config.bpb}{34}{\code {config.bpb}} |
\entry{config.debug}{34}{\code {config.debug}} |
\entry{configuration dynamic structure}{34}{configuration dynamic structure} |
\entry{sections}{34}{\code {sections}} |
\entry{runtime global structure}{34}{runtime global structure} |
\entry{runtime}{34}{\code {runtime}} |
\entry{runtime.cpu}{34}{\code {runtime.cpu}} |
\entry{runtime.vapi}{34}{\code {runtime.vapi}} |
\entry{runtime.cuc}{34}{\code {runtime.cuc}} |
\entry{output rediretion}{34}{output rediretion} |
\entry{runtime.cpu.fout}{34}{\code {runtime.cpu.fout}} |
\entry{reset hooks}{34}{reset hooks} |
\entry{reg_sim_reset}{34}{\code {reg_sim_reset}} |
\entry{internal debugging}{34}{internal debugging} |
\entry{license for Or1ksim}{35}{license for Or1ksim} |
/or1ksim.tp
--- or1ksim.cps (nonexistent)
+++ or1ksim.cps (revision 21)
@@ -0,0 +1,477 @@
+\initial {-}
+\entry {\code {--cumulative}}{4}
+\entry {\code {--debug-config}}{3}
+\entry {\code {--enable-ethphy}}{2}
+\entry {\code {--enable-mprofile}}{3}
+\entry {\code {--enable-profile}}{3}
+\entry {\code {--file}}{3}
+\entry {\code {--filename}}{4}
+\entry {\code {--generate}}{4}
+\entry {\code {--group}}{4}
+\entry {\code {--help}}{3}
+\entry {\code {--help} (memory profiling utility)}{4}
+\entry {\code {--help} (profiling utility)}{4}
+\entry {\code {--interactive}}{3}
+\entry {\code {--mode}}{4}
+\entry {\code {--nosrv}}{3}
+\entry {\code {--quiet}}{4}
+\entry {\code {--srv}}{3}
+\entry {\code {--version}}{3}
+\entry {\code {--version} (memory profiling utility)}{4}
+\entry {\code {--version} (profiling utility)}{4}
+\entry {\code {-c}}{4}
+\entry {\code {-d}}{3}
+\entry {\code {-f}}{3, 4}
+\entry {\code {-g}}{4}
+\entry {\code {-h}}{3}
+\entry {\code {-h} (memory profiling utility)}{4}
+\entry {\code {-h} (profiling utility)}{4}
+\entry {\code {-i}}{3}
+\entry {\code {-m}}{4}
+\entry {\code {-q}}{4}
+\entry {\code {-v}}{3}
+\entry {\code {-v} (memory profiling utility)}{4}
+\entry {\code {-v} (profiling utility)}{4}
+\initial {0}
+\entry {0x00 UART VAPI sub-command (UART verification)}{30}
+\entry {0x01 UART VAPI sub-command (UART verification)}{30}
+\entry {0x02 UART VAPI sub-command (UART verification)}{30}
+\entry {0x03 UART VAPI sub-command (UART verification)}{30}
+\entry {0x04 UART VAPI sub-command (UART verification)}{30}
+\initial {1}
+\entry {\code {16550} (UART configuration)}{19}
+\initial {A}
+\entry {ATA/ATAPI configuration}{24}
+\entry {ATA/ATAPI device configuration}{25}
+\initial {B}
+\entry {\code {base_vapi_id} (GPIO configuration - deprecated)}{22}
+\entry {\code {baseaddr} (ATA/ATAPI configuration)}{24}
+\entry {\code {baseaddr} (DMA configuration)}{20}
+\entry {\code {baseaddr} (Ethernet configuration)}{20}
+\entry {\code {baseaddr} (frame buffer configuration)}{23}
+\entry {\code {baseaddr} (generic peripheral configuration)}{26}
+\entry {\code {baseaddr} (GPIO configuration)}{21}
+\entry {\code {baseaddr} (keyboard configuration)}{23}
+\entry {\code {baseaddr} (memory configuration)}{13}
+\entry {\code {baseaddr} (memory controller configuration)}{18}
+\entry {\code {baseaddr} (UART configuration)}{18}
+\entry {\code {baseaddr} (VGA configuration)}{22}
+\entry {\code {blocksize} (cache configuration)}{15}
+\entry {BPB configuration}{16}
+\entry {branch prediction configuration}{16}
+\entry {\code {break} (Interactive CLI)}{27}
+\entry {breakpoint list (Interactive CLI)}{27}
+\entry {breakpoint set/clear (Interactive CLI)}{27}
+\entry {\code {breaks} (Interactive CLI)}{27}
+\entry {\code {btic} (branch prediction configuration)}{16}
+\entry {\code {byte_enabled} (generic peripheral configuration)}{26}
+\initial {C}
+\entry {cache configuration}{15}
+\entry {\code {calling_convention} (CUC configuration)}{10}
+\entry {\code {ce} (memory configuration)}{13}
+\entry {\code {cfgr} (CPU configuration)}{11}
+\entry {\code {channel} (UART configuration)}{18}
+\entry {clear breakpoint (Interactive CLI)}{27}
+\entry {\code {clkcycle} (simulator configuration)}{9}
+\entry {\code {cm} (Interactive CLI)}{27}
+\entry {command line for Or1ksim standalone use}{3}
+\entry {\code {config}}{33}
+\entry {\code {config.bpb}}{34}
+\entry {\code {config.cpu}}{33}
+\entry {\code {config.cuc}}{33}
+\entry {\code {config.dc}}{33}
+\entry {\code {config.debug}}{34}
+\entry {\code {config.pic}}{34}
+\entry {\code {config.pm}}{33}
+\entry {\code {config.sim}}{33}
+\entry {\code {config.vapi}}{33}
+\entry {configuration dynamic structure}{34}
+\entry {configuration file structure}{7}
+\entry {configuration global structure}{33}
+\entry {configuration info (Interactive CLI)}{28}
+\entry {configuration of generic peripherals}{25}
+\entry {configuration parameter setting (Interactive CLI)}{28}
+\entry {configuring branch prediction}{16}
+\entry {configuring data & instruction caches}{15}
+\entry {configuring data & instruction MMUs}{14}
+\entry {configuring DMA}{19}
+\entry {configuring memory}{12}
+\entry {configuring Or1ksim}{7}
+\entry {configuring power management}{16}
+\entry {configuring the ATA/ATAPI interfaces}{24}
+\entry {configuring the behavior of Or1ksim}{8}
+\entry {configuring the CPU}{11}
+\entry {configuring the Custom Unit Compiler (CUC)}{10}
+\entry {configuring the debug unit and interface to external debuggers}{17}
+\entry {configuring the Ethernet interface}{20}
+\entry {configuring the frame buffer}{22}
+\entry {configuring the GPIO}{21}
+\entry {configuring the interrupt controller}{15}
+\entry {configuring the keyboard interface}{23}
+\entry {configuring the memory controller}{17}
+\entry {configuring the processor}{11}
+\entry {configuring the PS2 interface}{23}
+\entry {configuring the UART}{18}
+\entry {configuring the Verification API (VAPI)}{9}
+\entry {configuring the VGA interface}{22}
+\entry {copying memory (Interactive CLI)}{27}
+\entry {CPU configuration}{11}
+\entry {CUC configuration}{10}
+\entry {Custom Unit Compiler (Interactive CLI)}{29}
+\entry {Custom Unit Compiler Configuration}{10}
+\initial {D}
+\entry {data cache configuration}{15}
+\entry {data MMU configuration}{14}
+\entry {DCGE (power management register)}{16}
+\entry {\code {debug} (Interactive CLI)}{28, 29}
+\entry {\code {debug} (simulator configuration)}{8}
+\entry {debug channel toggle (Interactive CLI)}{28}
+\entry {debug interface configuration}{17}
+\entry {debug mode toggle (Interactive CLI)}{28}
+\entry {debug unit configuration}{17}
+\entry {Debug Unit verification (VAPI)}{30}
+\entry {\code {delayr} (memory configuration)}{13}
+\entry {\code {delayw} (memory configuration)}{14}
+\entry {\code {dependstats} (CPU configuration)}{12}
+\entry {\code {dev_id} (ATA/ATAPI configuration)}{24}
+\entry {disassemble (Interactive CLI)}{27}
+\entry {disc interface configuration}{24}
+\entry {disc interface device configuration}{25}
+\entry {display interface configuration}{22}
+\entry {displaying memory (Interactive CLI)}{27}
+\entry {displaying registers (Interactive CLI)}{27}
+\entry {\code {dm} (Interactive CLI)}{27}
+\entry {\code {dma} (Ethernet configuration)}{20}
+\entry {DMA configuration}{19}
+\entry {DMA verification (VAPI)}{30}
+\entry {\code {dma_mode0_td} (ATA/ATAPI configuration)}{24}
+\entry {\code {dma_mode0_teoc} (ATA/ATAPI configuration)}{24}
+\entry {\code {dma_mode0_tm} (ATA/ATAPI configuration)}{24}
+\entry {DME (power management register)}{16}
+\entry {DMMU configuration}{14}
+\entry {doze mode (power management register)}{16}
+\entry {\code {dv} (Interactive CLI)}{28}
+\entry {dynamic clock gating (power management register)}{16}
+\entry {dynamic ports, use of}{10}
+\initial {E}
+\entry {\code {edge_trigger} (interrupt controller)}{16}
+\entry {\code {enable_bursts} (CUC configuration)}{10}
+\entry {\code {enabled} (ATA/ATAPI configuration)}{24}
+\entry {\code {enabled} (branch prediction configuration)}{16}
+\entry {\code {enabled} (cache configuration)}{15}
+\entry {\code {enabled} (debug interface configuration)}{17}
+\entry {\code {enabled} (DMA configuration)}{20}
+\entry {\code {enabled} (Ethernet configuration)}{20}
+\entry {\code {enabled} (frame buffer configuration)}{22}
+\entry {\code {enabled} (generic peripheral configuration)}{26}
+\entry {\code {enabled} (GPIO configuration)}{21}
+\entry {\code {enabled} (interrupt controller)}{16}
+\entry {\code {enabled} (keyboard configuration)}{23}
+\entry {\code {enabled} (memory controller configuration)}{18}
+\entry {\code {enabled} (MMU configuration)}{14}
+\entry {\code {enabled} (power management configuration)}{16}
+\entry {\code {enabled} (UART configuration)}{18}
+\entry {\code {enabled} (verification API configuration)}{10}
+\entry {\code {enabled} (VGA configuration)}{22}
+\entry {enabling Ethernet via socket}{2}
+\entry {\code {entrysize} (MMU configuration)}{14}
+\entry {\code {ETH_VAPI_CTRL} (Ethernet verification)}{31}
+\entry {\code {ETH_VAPI_DATA} (Ethernet verification)}{31}
+\entry {Ethernet configuration}{20}
+\entry {Ethernet verification (VAPI)}{30}
+\entry {Ethernet via socket, enabling}{2}
+\entry {\code {exe_log} (simulator configuration)}{9}
+\entry {\code {exe_log_end} (simulator configuration)}{9}
+\entry {\code {exe_log_file} (simulator configuration)}{9}
+\entry {\code {exe_log_fn} (simulator configuration - deprecated)}{9}
+\entry {\code {exe_log_marker} (simulator configuration)}{9}
+\entry {\code {exe_log_start} (simulator configuration)}{9}
+\entry {\code {exe_log_type} (simulator configuration)}{9}
+\entry {\code {exe_log_type=default} (simulator configuration)}{9}
+\entry {\code {exe_log_type=hardware} (simulator configuration)}{9}
+\entry {\code {exe_log_type=simple} (simulator configuration)}{9}
+\entry {\code {exe_log_type=software} (simulator configuration)}{9}
+\entry {executing code (Interactive CLI)}{27}
+\entry {execution history (Interactive CLI)}{27}
+\initial {F}
+\entry {\code {file} (ATA/ATAPI device configuration)}{25}
+\entry {\code {file} (keyboard configuration)}{23}
+\entry {\code {filename} (frame buffer configuration - deprecated)}{23}
+\entry {\code {filename} (VGA configuration - deprecated)}{22}
+\entry {\code {firmware} (ATA/ATAPI device configuration)}{25}
+\entry {frame buffer configuration}{22}
+\initial {G}
+\entry {\code {gdb_enabled} (debug interface configuration)}{17}
+\entry {generic peripheral configuration}{25}
+\entry {GPIO configuration}{21}
+\entry {GPIO verification (VAPI)}{31}
+\entry {\code {GPIO_VAPI_AUX} (GPIO verification)}{31}
+\entry {\code {GPIO_VAPI_CLOCK} (GPIO verification)}{31}
+\entry {\code {GPIO_VAPI_CTRL} (GPIO verification)}{31}
+\entry {\code {GPIO_VAPI_DATA} (GPIO verification)}{31}
+\entry {\code {GPIO_VAPI_INTE} (GPIO verification)}{31}
+\entry {\code {GPIO_VAPI_PTRIG} (GPIO verification)}{31}
+\entry {\code {GPIO_VAPI_RGPIO} (GPIO verification)}{31}
+\initial {H}
+\entry {\code {hazards} (CPU configuration)}{12}
+\entry {\code {heads} (ATA/ATAPI device configuration)}{25}
+\entry {\code {help} (Interactive CLI)}{29}
+\entry {hexadecimal memory dump (Interactive CLI)}{28}
+\entry {\code {hide_device_id} (verification API configuration)}{10}
+\entry {\code {hist} (Interactive CLI)}{27}
+\entry {\code {history} (simulator configuration)}{8}
+\entry {history of execution (Interactive CLI)}{27}
+\entry {\code {hitdelay} (branch prediction configuration)}{16}
+\entry {\code {hitdelay} (instruction cache configuration)}{15}
+\entry {\code {hitdelay} (MMU configuration)}{14}
+\entry {\code {hw_enabled} (generic peripheral configuration)}{26}
+\initial {I}
+\entry {IMMU configuration}{14}
+\entry {\code {index} (memory controller configuration)}{18}
+\entry {\code {info} (Interactive CLI)}{28}
+\entry {installing Or1ksim}{2}
+\entry {instruction cache configuration}{15}
+\entry {instruction MMU configuration}{14}
+\entry {instruction profiling for Or1ksim}{3}
+\entry {instruction profiling utility (Interactive CLI)}{29}
+\entry {internal debugging}{34}
+\entry {interrupt controller configuration}{15}
+\entry {\code {irq} (ATA/ATAPI configuration)}{24}
+\entry {\code {irq} (DMA configuration)}{20}
+\entry {\code {irq} (GPIO configuration)}{22}
+\entry {\code {irq} (keyboard configuration)}{23}
+\entry {\code {irq} (UART configuration)}{19}
+\entry {\code {irq} (VGA configuration)}{22}
+\initial {J}
+\entry {\code {jitter} (UART configuration)}{19}
+\initial {K}
+\entry {keyboard configuration}{23}
+\initial {L}
+\entry {library version of Or1ksim}{5}
+\entry {license for Or1ksim}{35}
+\entry {list breakpoints (Interactive CLI)}{27}
+\entry {\code {load_hitdelay} (data cache configuration)}{15}
+\entry {\code {load_missdelay} (data cache configuration)}{15}
+\entry {\code {log} (memory configuration)}{14}
+\entry {\code {log_enabled} (verification API configuration)}{10}
+\entry {\code {long}}{5}
+\initial {M}
+\entry {\code {mc} (memory configuration)}{13}
+\entry {memory configuration}{12}
+\entry {memory controller configuration}{17}
+\entry {memory copying (Interactive CLI)}{27}
+\entry {memory display (Interactive CLI)}{27}
+\entry {memory dump, hexadecimal (Interactive CLI)}{28}
+\entry {memory dump, Verilog (Interactive CLI)}{28}
+\entry {memory patching (Interactive CLI)}{27}
+\entry {memory profiling end address}{4}
+\entry {memory profiling start address}{4}
+\entry {memory profiling utility (Interactive CLI)}{29}
+\entry {memory profiling version of Or1ksim}{4}
+\entry {\code {memory_order} (CUC configuration)}{10}
+\entry {\code {memory_order=exact} (CUC configuration)}{10}
+\entry {\code {memory_order=none} (CUC configuration)}{10}
+\entry {\code {memory_order=strong} (CUC configuration)}{10}
+\entry {\code {memory_order=weak} (CUC configuration)}{10}
+\entry {\code {missdelay} (branch prediction configuration)}{17}
+\entry {\code {missdelay} (instruction cache configuration)}{15}
+\entry {\code {missdelay} (MMU configuration)}{14}
+\entry {MMU configuration}{14}
+\entry {\code {mprof_file} (simulator configuration)}{8}
+\entry {\code {mprof_fn} (simulator configuration - deprecated)}{8}
+\entry {\code {mprofile} (Interactive CLI)}{29}
+\entry {\code {mprofile} (simulator configuration)}{8}
+\entry {\code {mwdma} (ATA/ATAPI device configuration)}{25}
+\initial {N}
+\entry {\code {name} (generic peripheral configuration)}{26}
+\entry {\code {name} (memory configuration)}{13}
+\entry {\code {no_multicycle} (CUC configuration)}{11}
+\entry {\code {nsets} (cache configuration)}{15}
+\entry {\code {nsets} (MMU configuration)}{14}
+\entry {\code {nways} (cache configuration)}{15}
+\entry {\code {nways} (MMU configuration)}{14}
+\initial {O}
+\entry {\code {or1ksim_get_time_period}}{5}
+\entry {\code {or1ksim_init}}{5}
+\entry {\code {or1ksim_interrupt}}{5}
+\entry {\code {or1ksim_is_le}}{5}
+\entry {\code {or1ksim_reset_duration}}{5}
+\entry {\code {or1ksim_run}}{5}
+\entry {\code {or1ksim_set_time_point}}{5}
+\entry {output rediretion}{34}
+\initial {P}
+\entry {\code {packet} (ATA/ATAPI device configuration)}{25}
+\entry {\code {pagesize} (MMU configuration)}{14}
+\entry {patching memory (Interactive CLI)}{27}
+\entry {patching registers (Interactive CLI)}{27}
+\entry {patching the program counter (Interactive CLI)}{27}
+\entry {\code {pattern} (memory configuration)}{13}
+\entry {\code {pc} (Interactive CLI)}{27}
+\entry {PIC configuration}{15}
+\entry {\code {pio} (ATA/ATAPI device configuration)}{25}
+\entry {\code {pio_mode0_t1} (ATA/ATAPI configuration)}{24}
+\entry {\code {pio_mode0_t2} (ATA/ATAPI configuration)}{24}
+\entry {\code {pio_mode0_t4} (ATA/ATAPI configuration)}{24}
+\entry {\code {pio_mode0_teoc} (ATA/ATAPI configuration)}{24}
+\entry {\code {pm} (Interactive CLI)}{27}
+\entry {PMR - DGCE}{16}
+\entry {PMR - DME}{16}
+\entry {PMR - SDF}{16}
+\entry {PMR - SME}{16}
+\entry {PMR - SUME}{16}
+\entry {PMU configuration}{16}
+\entry {\code {poc} (memory controller configuration)}{18}
+\entry {port range for TCP/IP}{10}
+\entry {power management configuration}{16}
+\entry {power management register, DGCE}{16}
+\entry {power management register, DME}{16}
+\entry {power management register, SDF}{16}
+\entry {power management register, SME}{16}
+\entry {power management register, SUME}{16}
+\entry {\code {pr} (Interactive CLI)}{27}
+\entry {private ports, use of}{10}
+\entry {processor configuration}{11}
+\entry {processor stall (Interactive CLI)}{27}
+\entry {\code {prof_file} (simulator configuration)}{8}
+\entry {\code {prof_fn} (simulator configuration - deprecated)}{8}
+\entry {\code {profile} (simulator configuration)}{8}
+\entry {profiling for Or1ksim}{3}
+\entry {profiling utility (Interactive CLI)}{29}
+\entry {program counter patching (Interactive CLI)}{27}
+\entry {programmable interrupt controller configuration}{15}
+\entry {PS2 configuration}{23}
+\initial {Q}
+\entry {\code {q} (Interactive CLI)}{27}
+\entry {quitting (Interactive CLI)}{27}
+\initial {R}
+\entry {\code {r} (Interactive CLI)}{27}
+\entry {\code {random_seed} (memory configuration)}{12}
+\entry {\code {refresh_rate} (frame buffer configuration)}{23}
+\entry {\code {refresh_rate} (VGA configuration)}{22}
+\entry {\code {reg_sim_reset}}{34}
+\entry {register display (Interactive CLI)}{27}
+\entry {register patching (Interactive CLI)}{27}
+\entry {\code {reset} (Interactive CLI)}{27}
+\entry {reset hooks}{34}
+\entry {reset the simulator (Interactive CLI)}{27}
+\entry {\code {rev} (ATA/ATAPI configuration)}{24}
+\entry {\code {rev} (CPU configuration)}{11}
+\entry {\code {rtx_type} (Ethernet configuration)}{21}
+\entry {\code {run} (Interactive CLI)}{27}
+\entry {running code (Interactive CLI)}{27}
+\entry {running Or1ksim}{3}
+\entry {\code {runtime}}{34}
+\entry {runtime global structure}{34}
+\entry {\code {runtime.cpu}}{34}
+\entry {\code {runtime.cpu.fout}}{34}
+\entry {\code {runtime.cuc}}{34}
+\entry {\code {runtime.vapi}}{34}
+\entry {\code {rx_channel} (Ethernet configuration)}{21}
+\entry {\code {rxfile} (Ethernet configuration)}{21}
+\initial {S}
+\entry {\code {sbp_bf_fwd} (branch prediction configuration)}{16}
+\entry {\code {sbp_bnf_fwd} (branch prediction configuration)}{16}
+\entry {\code {sbuf_len} (CPU configuration)}{12}
+\entry {SDF (power management register)}{16}
+\entry {\code {section ata}}{24}
+\entry {\code {section bpb}}{16}
+\entry {\code {section cpio}}{21}
+\entry {\code {section cpu}}{11}
+\entry {\code {section cuc}}{10}
+\entry {\code {section dc}}{15}
+\entry {\code {section debug}}{17}
+\entry {\code {section dma}}{19}
+\entry {\code {section dmmu}}{14}
+\entry {\code {section ethernet}}{20}
+\entry {\code {section fb}}{22}
+\entry {\code {section generic}}{25}
+\entry {\code {section ic}}{15}
+\entry {\code {section immu}}{14}
+\entry {\code {section kb}}{23}
+\entry {\code {section mc}}{17}
+\entry {\code {section memory}}{12}
+\entry {\code {section pic}}{15}
+\entry {\code {section pmu}}{16}
+\entry {\code {section sim}}{8}
+\entry {\code {section uart}}{18}
+\entry {\code {section vapi}}{9}
+\entry {\code {section vga}}{22}
+\entry {\code {sections}}{34}
+\entry {\code {sectors} (ATA/ATAPI device configuration)}{25}
+\entry {\code {server_port} (debug interface configuration)}{17}
+\entry {\code {server_port} (verification API configuration)}{10}
+\entry {\code {set} (Interactive CLI)}{28}
+\entry {set breakpoint (Interactive CLI)}{27}
+\entry {\code {setdbch} (Interactive CLI)}{28}
+\entry {simulator configuration}{8}
+\entry {simulator configuration info (Interactive CLI)}{28}
+\entry {simulator reset (Interactive CLI)}{27}
+\entry {simulator statistics (Interactive CLI)}{28}
+\entry {\code {size} (ATA/ATAPI device configuration)}{25}
+\entry {\code {size} (generic peripheral configuration)}{26}
+\entry {\code {size} (memory configuration)}{13}
+\entry {sleep mode (power management register)}{16}
+\entry {slow down factor (power management register)}{16}
+\entry {SME (power management register)}{16}
+\entry {\code {sockif} (Ethernet configuration)}{21}
+\entry {\code {sr} (CPU configuration)}{11}
+\entry {\code {stall} (Interactive CLI)}{27}
+\entry {stall the processor (Interactive CLI)}{27}
+\entry {statistics, simulation (Interactive CLI)}{28}
+\entry {\code {stats} (Interactive CLI)}{28}
+\entry {stepping code (Interactive CLI)}{27}
+\entry {\code {store_hitdelay} (data cache configuration)}{15}
+\entry {\code {store_missdelay} (data cache configuration)}{15}
+\entry {SUME (power management register)}{16}
+\entry {\code {superscalar} (CPU configuration)}{11}
+\entry {suspend mode (power management register)}{16}
+\initial {T}
+\entry {\code {t} (Interactive CLI)}{27}
+\entry {TCP/IP port range}{10}
+\entry {TCP/IP port range for \code {or1ksim} service}{17}
+\entry {\code {timings_file} (CUC configuration)}{11}
+\entry {\code {timings_fn} (CUC configuration - deprecated)}{11}
+\entry {toggle breakpoint (Interactive CLI)}{27}
+\entry {toggle debug channels (Interactive CLI)}{28}
+\entry {toggle debug mode (Interactive CLI)}{28}
+\entry {\code {tx_channel} (Ethernet configuration)}{21}
+\entry {\code {txfile} (Ethernet configuration)}{21}
+\entry {\code {txfile} (frame buffer configuration)}{23}
+\entry {\code {txfile} (VGA configuration)}{22}
+\entry {\code {type} (ATA/ATAPI device configuration)}{25}
+\entry {\code {type} (memory configuration)}{12}
+\entry {\code {type=pattern} (memory configuration)}{12}
+\entry {\code {type=random} (memory configuration)}{12}
+\entry {\code {type=unknown} (memory configuration)}{12}
+\entry {\code {type=zero} (memory configuration)}{12}
+\initial {U}
+\entry {UART configuration}{18}
+\entry {UART I/O from/to a physical serial port}{19}
+\entry {UART I/O from/to an \command {xterm}}{19}
+\entry {UART I/O from/to files}{19}
+\entry {UART I/O from/to open file descriptors}{19}
+\entry {UART I/O from/to TCP/IP}{19}
+\entry {UART verification (VAPI)}{30}
+\entry {\code {upr} (CPU configuration)}{11}
+\entry {\code {ustates} (cache configuration)}{15}
+\entry {\code {ustates} (MMU configuration)}{14}
+\initial {V}
+\entry {VAPI configuration}{9}
+\entry {VAPI for Debug Unit}{30}
+\entry {VAPI for DMA}{30}
+\entry {VAPI for Ethernet}{30}
+\entry {VAPI for GPIO}{31}
+\entry {VAPI for UART}{30}
+\entry {\code {vapi_id} (debug interface configuration)}{17}
+\entry {\code {vapi_id} (DMA configuration)}{20, 21}
+\entry {\code {vapi_id} (GPIO configuration)}{22}
+\entry {\code {vapi_id} (UART configuration)}{19}
+\entry {\code {vapi_log_file} (verification API configuration)}{10}
+\entry {\code {vapi_log_fn} (verification API configuration - deprecated)}{10}
+\entry {\code {ver} (CPU configuration)}{11}
+\entry {\code {verbose} (simulator configuration)}{8}
+\entry {Verification API configuration}{9}
+\entry {Verilog memory dump (Interactive CLI)}{28}
+\entry {VGA configuration}{22}
+\initial {W}
+\entry {\code {word_enabled} (generic peripheral configuration)}{26}
/or1ksim.toc
0,0 → 1,45
@unnchapentry{Scope of this Document}{10001}{Top}{1} |
@numchapentry{Installation}{1}{Installation}{2} |
@numchapentry{Usage}{2}{Usage}{3} |
@numsecentry{Standalone Simulator}{2.1}{Standalone Simulator}{3} |
@numsecentry{Profiling Utility}{2.2}{Profiling Utility}{3} |
@numsecentry{Memory Profiling Utility}{2.3}{Memory Profiling Utility}{4} |
@numsecentry{Simulator Library}{2.4}{Simulator Library}{5} |
@numchapentry{Configuration}{3}{Configuration}{7} |
@numsecentry{Configuration File Format}{3.1}{Configuration File Format}{7} |
@numsubsecentry{Configuration File Preprocessing}{3.1.1}{Configuration File Preprocessing}{7} |
@numsubsecentry{Configuration File Syntax}{3.1.2}{Configuration File Syntax}{7} |
@numsecentry{Simulator Configuration}{3.2}{Simulator Configuration}{8} |
@numsubsecentry{Simulator Behavior}{3.2.1}{Simulator Behavior}{8} |
@numsubsecentry{Verification API (VAPI) Configuration}{3.2.2}{Verification API Configuration}{9} |
@numsubsecentry{Custom Unit Compiler (CUC) Configuration}{3.2.3}{CUC Configuration}{10} |
@numsecentry{Configuring the OpenRISC Architectural Components}{3.3}{Core OpenRISC Configuration}{11} |
@numsubsecentry{CPU Configuration}{3.3.1}{CPU Configuration}{11} |
@numsubsecentry{Memory Configuration}{3.3.2}{Memory Configuration}{12} |
@numsubsecentry{Memory Management Configuration}{3.3.3}{Memory Management Configuration}{14} |
@numsubsecentry{Cache Configuration}{3.3.4}{Cache Configuration}{15} |
@numsubsecentry{Interrupt Configuration}{3.3.5}{Interrupt Configuration}{15} |
@numsubsecentry{Power Management Configuration}{3.3.6}{Power Management Configuration}{16} |
@numsubsecentry{Branch Prediction Configuration}{3.3.7}{Branch Prediction Configuration}{16} |
@numsubsecentry{Debug Interface Configuration}{3.3.8}{Debug Interface Configuration}{17} |
@numsecentry{Configuring Memory Mapped Peripherals}{3.4}{Peripheral Configuration}{17} |
@numsubsecentry{Memory Controller Configuration}{3.4.1}{Memory Controller Configuration}{17} |
@numsubsecentry{UART Configuration}{3.4.2}{UART Configuration}{18} |
@numsubsecentry{DMA Configuration}{3.4.3}{DMA Configuration}{19} |
@numsubsecentry{Ethernet Configuration}{3.4.4}{Ethernet Configuration}{20} |
@numsubsecentry{GPIO Configuration}{3.4.5}{GPIO Configuration}{21} |
@numsubsecentry{Display Interface Configuration}{3.4.6}{Display Interface Configuration}{22} |
@numsubsecentry{Frame Buffer Configuration}{3.4.7}{Frame Buffer Configuration}{22} |
@numsubsecentry{Keyboard Configuration (PS2)}{3.4.8}{Keyboard Configuration}{23} |
@numsubsecentry{Disc Interface Configuration}{3.4.9}{Disc Interface Configuration}{24} |
@numsubsubsecentry{ATA/ATAPI Device Configuration}{3.4.9.1}{}{25} |
@numsubsecentry{Generic Peripheral Configuration}{3.4.10}{Generic Peripheral Configuration}{25} |
@numchapentry{Interactive Command Line}{4}{Interactive Command Line}{27} |
@numchapentry{Verification API (VAPI)}{5}{Verification API}{30} |
@numchapentry{A Guide to Or1ksim Internals}{6}{Code Internals}{32} |
@numsecentry{Coding Conventions for Or1ksim}{6.1}{Coding Conventions}{32} |
@numsecentry{Global Data Structures}{6.2}{Global Data Structures}{33} |
@numsecentry{Concepts}{6.3}{Concepts}{34} |
@numsecentry{Internal Debugging}{6.4}{Internal Debugging}{34} |
@numchapentry{GNU Free Documentation License}{7}{GNU Free Documentation License}{35} |
@unnchapentry{Index}{10002}{Index}{42} |
/Makefile
0,0 → 1,633
# Makefile.in generated by automake 1.10.1 from Makefile.am. |
# doc/Makefile. Generated from Makefile.in by configure. |
|
# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. |
# This Makefile.in is free software; the Free Software Foundation |
# gives unlimited permission to copy and/or distribute it, |
# with or without modifications, as long as this notice is preserved. |
|
# This program is distributed in the hope that it will be useful, |
# but WITHOUT ANY WARRANTY, to the extent permitted by law; without |
# even the implied warranty of MERCHANTABILITY or FITNESS FOR A |
# PARTICULAR PURPOSE. |
|
|
|
# Makefile.am -- Documentation automake configuration file |
# |
# Copyright (C) 2008 Embecosm Limited |
# |
# Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
# |
# This file is part of OpenRISC 1000 Architectural Simulator. |
# |
# This program is free software; you can redistribute it and/or modify it |
# under the terms of the GNU General Public License as published by the Free |
# Software Foundation; either version 3 of the License, or (at your option) |
# any later version. |
# |
# This program is distributed in the hope that it will be useful, but WITHOUT |
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
# more details. |
# |
# You should have received a copy of the GNU General Public License along |
# with this program. If not, see <http://www.gnu.org/licenses/>. |
VPATH = ../../doc |
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pkglibdir = $(libdir)/or1ksim |
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install_sh_DATA = $(install_sh) -c -m 644 |
install_sh_PROGRAM = $(install_sh) -c |
install_sh_SCRIPT = $(install_sh) -c |
INSTALL_HEADER = $(INSTALL_DATA) |
transform = $(program_transform_name) |
NORMAL_INSTALL = : |
PRE_INSTALL = : |
POST_INSTALL = : |
NORMAL_UNINSTALL = : |
PRE_UNINSTALL = : |
POST_UNINSTALL = : |
build_triplet = i686-pc-linux-gnu |
host_triplet = i686-pc-linux-gnu |
target_triplet = or32-unknown-uclinux |
subdir = doc |
DIST_COMMON = $(or1ksim_TEXINFOS) $(srcdir)/Makefile.am \ |
$(srcdir)/Makefile.in $(srcdir)/stamp-vti \ |
$(srcdir)/version.texi mdate-sh texinfo.tex |
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abs_srcdir = /home/jeremy/partners/OpenCores/cvstrees/or1k/or1ksim/build/../doc |
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target_cpu = or32 |
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top_builddir = .. |
top_srcdir = ../.. |
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|
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or1ksim_TEXINFOS = config.texi \ |
fdl-1.2.texi \ |
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|
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|
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echo ' cd $(top_srcdir) && $(AUTOMAKE) --gnu doc/Makefile'; \ |
cd $(top_srcdir) && \ |
$(AUTOMAKE) --gnu doc/Makefile |
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|
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if test ! -d $(@:.html=.htp) && test -d $(@:.html=); then \ |
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exit 1; \ |
fi |
$(srcdir)/or1ksim.info: or1ksim.texi $(srcdir)/version.texi $(or1ksim_TEXINFOS) |
or1ksim.dvi: or1ksim.texi $(srcdir)/version.texi $(or1ksim_TEXINFOS) |
or1ksim.pdf: or1ksim.texi $(srcdir)/version.texi $(or1ksim_TEXINFOS) |
or1ksim.html: or1ksim.texi $(srcdir)/version.texi $(or1ksim_TEXINFOS) |
$(srcdir)/version.texi: $(srcdir)/stamp-vti |
$(srcdir)/stamp-vti: or1ksim.texi $(top_srcdir)/configure |
@(dir=.; test -f ./or1ksim.texi || dir=$(srcdir); \ |
set `$(SHELL) $(srcdir)/mdate-sh $$dir/or1ksim.texi`; \ |
echo "@set UPDATED $$1 $$2 $$3"; \ |
echo "@set UPDATED-MONTH $$2 $$3"; \ |
echo "@set EDITION $(VERSION)"; \ |
echo "@set VERSION $(VERSION)") > vti.tmp |
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or1ksim.ps or1ksim.html |
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# Tell versions [3.59,3.63) of GNU make to not export all variables. |
# Otherwise a system limit (for SysV at least) may be exceeded. |
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