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Rev 121 → Rev 135
/Makefile.in
0,0 → 1,418
# Makefile.in generated by automake 1.11.1 from Makefile.am. |
# @configure_input@ |
|
# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, |
# Inc. |
# This Makefile.in is free software; the Free Software Foundation |
# gives unlimited permission to copy and/or distribute it, |
# with or without modifications, as long as this notice is preserved. |
|
# This program is distributed in the hope that it will be useful, |
# but WITHOUT ANY WARRANTY, to the extent permitted by law; without |
# even the implied warranty of MERCHANTABILITY or FITNESS FOR A |
# PARTICULAR PURPOSE. |
|
@SET_MAKE@ |
|
# Makefile.am for libor1ksim DejaGNU tests |
|
# Copyright (C) Marko Mlinar, 2001 |
# Copyright (C) Embecosm Limited, 2010 |
|
# Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
|
# To add new test, edit between marked areas only |
|
# This file is part of OpenRISC 1000 Architectural Simulator. |
|
# This program is free software; you can redistribute it and/or modify it |
# under the terms of the GNU General Public License as published by the Free |
# Software Foundation; either version 3 of the License, or (at your option) |
# any later version. |
|
# This program is distributed in the hope that it will be useful, but WITHOUT |
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
# more details. |
|
# You should have received a copy of the GNU General Public License along |
# with this program. If not, see <http:#www.gnu.org/licenses/>. */ |
|
# ----------------------------------------------------------------------------- |
# This code is commented throughout for use with Doxygen. |
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|
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jtag-select-module.exp \ |
jtag-write-control.exp \ |
jtag-write-command.exp \ |
lib-iftest.exp \ |
upcalls.exp \ |
upcalls.cfg |
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# Tell versions [3.59,3.63) of GNU make to not export all variables. |
# Otherwise a system limit (for SysV at least) may be exceeded. |
.NOEXPORT: |
/jtag-write-command.exp
0,0 → 1,1678
# jtag-command.exp. Tests of the library JTAG WRITE_COMMAND |
|
# Copyright (C) 2010 Embecosm Limited |
|
# Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
|
# This file is part of OpenRISC 1000 Architectural Simulator. |
|
# This program is free software; you can redistribute it and/or modify it |
# under the terms of the GNU General Public License as published by the Free |
# Software Foundation; either version 3 of the License, or (at your option) |
# any later version. |
|
# This program is distributed in the hope that it will be useful, but WITHOUT |
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
# more details. |
|
# You should have received a copy of the GNU General Public License along |
# with this program. If not, see <http:#www.gnu.org/licenses/>. */ |
|
# ----------------------------------------------------------------------------- |
# This code is commented throughout for use with Doxygen. |
# ----------------------------------------------------------------------------- |
|
|
# These are the tests of the high level JTAG WRITE_COMMAND interface. |
|
# NOTE. All these tests return timing information, but we ignore it, since in |
# general it will not be repeatable. |
|
# Test of WRITE_COMMAND for each module (including none). This should raise an |
# error for any module other than WB and CPU0. There are different errors for |
# CPU1 (which can be selected, but for which WRITE_COMMAND is invalid) and all |
# other modules. |
|
# WRITE_COMMAND with no module selection |
run_libsim "JTAG WRITE_COMMAND no module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018f4396f780000000100088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "0" "WRITE_COMMAND" "2" "100000" "4" |
|
# WRITE_COMMAND for Wishbone |
run_libsim "JTAG WRITE_COMMAND module WB" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018f4396f780000000100088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "0" "WRITE_COMMAND" "2" "100000" "4" |
|
# WRITE_COMMAND for CPU0 |
run_libsim "JTAG WRITE_COMMAND module CPU0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001933eb7e580010028000088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "1" "WRITE_COMMAND" "2" "2801" "4" |
|
# WRITE_COMMAND for CPU1 |
run_libsim "JTAG WRITE_COMMAND module CPU1" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000001993c98e69" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018f4396f780000000100088" \ |
"ERROR: JTAG WRITE_COMMAND for CPU1 not supported." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "2" "WRITE_COMMAND" "2" "100000" "4" |
|
# WRITE_COMMAND for invalid module |
run_libsim "JTAG WRITE_COMMAND invalid module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000424d9ea79" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018f4396f780000000100088" \ |
"ERROR: JTAG WRITE_COMMAND with no module selected." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "3" "WRITE_COMMAND" "2" "100000" "4" |
|
# WRITE_COMMAND for valid followed by invalid module |
run_libsim "JTAG WRITE_COMMAND valid then invalid module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000001993c98e69" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000424d9ea79" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018f4396f780000000100088" \ |
"ERROR: JTAG WRITE_COMMAND with no module selected." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "2" "SELECT_MODULE" "3" "WRITE_COMMAND" "2" \ |
"100000" "4" |
|
# WRITE_COMMAND for invalid followed by valid module |
run_libsim "JTAG WRITE_COMMAND invalid then valid module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000424d9ea79" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018f4396f780000000100088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "3" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" \ |
"100000" "4" |
|
# Tests of WRITE_COMMAND access types for WishBone. Check the different access |
# types are accepted/rejected as expected (0, 1, 2, 4, 5 and 6 are OK). |
|
# WRITE_COMMAND to write bytes for WishBone (access type 0) |
run_libsim "JTAG WRITE_COMMAND WB write bytes" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000107557c0580000000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100000" "4" |
|
# WRITE_COMMAND to write half words for WishBone (access type 1) |
run_libsim "JTAG WRITE_COMMAND WB write half words" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000001778a9e180000000100108" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "100000" "4" |
|
# WRITE_COMMAND to write words for WishBone (access type 2) |
run_libsim "JTAG WRITE_COMMAND WB write words" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018f4396f780000000100088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" "100000" "4" |
|
# WRITE_COMMAND to write access type 3 for WishBone. This should fail with an |
# error. |
run_libsim "JTAG WRITE_COMMAND WB write access type 3" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000009f6e431380000000100188" \ |
"ERROR: JTAG WRITE_COMMAND unknown access type 3." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "3" "100000" "4" |
|
# WRITE_COMMAND to read bytes for WishBone (access type 4). All the read |
# accesses use the init version of the loop, so consistent values are set. |
run_libsim "JTAG WRITE_COMMAND WB read bytes" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000982f0f3d80000000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100000" "4" |
|
# WRITE_COMMAND to read half words for WishBone (access type 5) |
run_libsim "JTAG WRITE_COMMAND WB read half words" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018802dad980000000100148" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "100000" "4" |
|
# WRITE_COMMAND to read words for WishBone (access type 6) |
run_libsim "JTAG WRITE_COMMAND WB read words" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000001039e5cf800000001000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" "100000" "4" |
|
# WRITE_COMMAND to read access type 7 for WishBone. This should fail with an |
# error. |
run_libsim "JTAG WRITE_COMMAND WB read access type 7" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000010014302b800000001001c8" \ |
"ERROR: JTAG WRITE_COMMAND unknown access type 7." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "7" "100000" "4" |
|
# Tests of WRITE_COMMAND addresses for WishBone. Check different addresses are |
# all accepted. For all of these we use the simple loop and a byte write. Test |
# the boundaries (address 0 and address 0xffffffff). |
|
# WRITE_COMMAND for WishBone to address 0 |
run_libsim "JTAG WRITE_COMMAND WB write address 0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000517c6ee600000000000008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "0" "1" |
|
# WRITE_COMMAND for WishBone to address ffffffff |
run_libsim "JTAG WRITE_COMMAND WB write address 0xffffffff" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000cd06d25e0001fffffffe08" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "ffffffff" "1" |
|
# Tests of WRITE_COMMAND lengths for WishBone. Check the different lengths are |
# accepted. For all of these we use the simple loop and write. There is no |
# point testing sizes outside the range, since these fail in the test rather |
# than the progrma under test. We use byte reads from the initialized loop |
|
# Test of WRITE_COMMAND for WishBone 1 byte. |
run_libsim "JTAG WRITE_COMMAND WB read length 1" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001aee68a5c00000000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100000" "1" |
|
# Test of WRITE_COMMAND for WishBone 0x10000 bytes. We only match the first |
# few bytes of the shifted strings and data. |
run_libsim "JTAG WRITE_COMMAND WB read length 0x10000" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000d2aaafa3fffe0000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100000" "10000" |
|
# Tests of WRITE_COMMAND with different alignments. Byte access should be |
# aligned on any boundary. Half-word on half-word boundaries and word on word |
# boundaries. In each case we use 4 byte transfers. |
|
# Write bytes, aligned on byte 0 |
run_libsim "JTAG WRITE_COMMAND WB write bytes, byte 0 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000107557c0580000000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100000" "4" |
|
# Write bytes, aligned on byte 1 |
run_libsim "JTAG WRITE_COMMAND WB write bytes, byte 1 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000c53f4b0580010000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100001" "4" |
|
# Write bytes, aligned on byte 2 |
run_libsim "JTAG WRITE_COMMAND WB write bytes, byte 2 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001e660678580008000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100002" "4" |
|
# Write bytes, aligned on byte 3 |
run_libsim "JTAG WRITE_COMMAND WB write bytes, byte 3 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000240a508580018000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100003" "4" |
|
# Write half words, aligned on byte 0 |
run_libsim "JTAG WRITE_COMMAND WB write half words, byte 0 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000001778a9e180000000100108" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "100000" "4" |
|
# Write half words, aligned on byte 1 |
run_libsim "JTAG WRITE_COMMAND WB write half words, byte 1 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001d5129ee180010000100108" \ |
"ERROR: JTAG WishBone 16-bit access must be 2-byte aligned." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "100001" "4" |
|
# Write half words, aligned on byte 2 |
run_libsim "JTAG WRITE_COMMAND WB write half words, byte 2 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000f64db26180008000100108" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "100002" "4" |
|
# Write half words, aligned on byte 3 |
run_libsim "JTAG WRITE_COMMAND WB write half words, byte 3 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000013427856180018000100108" \ |
"ERROR: JTAG WishBone 16-bit access must be 2-byte aligned." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "100003" "4" |
|
# Write words, aligned on byte 0 |
run_libsim "JTAG WRITE_COMMAND WB write words, byte 0 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018f4396f780000000100088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" "100000" "4" |
|
# Write words, aligned on byte 1 |
run_libsim "JTAG WRITE_COMMAND WB write words, byte 1 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000004d29a1f780010000100088" \ |
"ERROR: JTAG WishBone 32-bit access must be 4-byte aligned." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" "100001" "4" |
|
# Write words, aligned on byte 2 |
run_libsim "JTAG WRITE_COMMAND WB write words, byte 2 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000016e768d7780008000100088" \ |
"ERROR: JTAG WishBone 32-bit access must be 4-byte aligned." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" "100002" "4" |
|
# Write words, aligned on byte 3 |
run_libsim "JTAG WRITE_COMMAND WB write words, byte 3 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000ac1cba7780018000100088" \ |
"ERROR: JTAG WishBone 32-bit access must be 4-byte aligned." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" "100003" "4" |
|
# Read bytes, aligned on byte 0 |
run_libsim "JTAG WRITE_COMMAND WB read bytes, byte 0 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000982f0f3d80000000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100000" "4" |
|
# Read bytes, aligned on byte 1 |
run_libsim "JTAG WRITE_COMMAND WB read bytes, byte 1 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000015a45383d80010000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100001" "4" |
|
# Read bytes, aligned on byte 2 |
run_libsim "JTAG WRITE_COMMAND WB read bytes, byte 2 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000791a14bd80008000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100002" "4" |
|
# Read bytes, aligned on byte 3 |
run_libsim "JTAG WRITE_COMMAND WB read bytes, byte 3 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001bb7023bd80018000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100003" "4" |
|
# Read half words, aligned on byte 0 |
run_libsim "JTAG WRITE_COMMAND WB read half words, byte 0 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018802dad980000000100148" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "100000" "4" |
|
# Read half words, aligned on byte 1 |
run_libsim "JTAG WRITE_COMMAND WB read half words, byte 1 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000004a68edd980010000100148" \ |
"ERROR: JTAG WishBone 16-bit access must be 2-byte aligned." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "100001" "4" |
|
# Read half words, aligned on byte 2 |
run_libsim "JTAG WRITE_COMMAND WB read half words, byte 2 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000016937c15980008000100148" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "100002" "4" |
|
# Read half words, aligned on byte 3 |
run_libsim "JTAG WRITE_COMMAND WB read half words, byte 3 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000ab5df65980018000100148" \ |
"ERROR: JTAG WishBone 16-bit access must be 2-byte aligned." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "100003" "4" |
|
# Read words, aligned on byte 0 |
run_libsim "JTAG WRITE_COMMAND WB read words, byte 0 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000001039e5cf800000001000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" "100000" "4" |
|
# Read words, aligned on byte 1 |
run_libsim "JTAG WRITE_COMMAND WB read words, byte 1 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001d253d2cf800100001000c8" \ |
"ERROR: JTAG WishBone 32-bit access must be 4-byte aligned." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" "100001" "4" |
|
# Read words, aligned on byte 2 |
run_libsim "JTAG WRITE_COMMAND WB read words, byte 2 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000f10cfe4f800080001000c8" \ |
"ERROR: JTAG WishBone 32-bit access must be 4-byte aligned." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" "100002" "4" |
|
# Read words, aligned on byte 3 |
run_libsim "JTAG WRITE_COMMAND WB read words, byte 3 aligned" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000013366c94f800180001000c8" \ |
"ERROR: JTAG WishBone 32-bit access must be 4-byte aligned." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" "100003" "4" |
|
# Tests of WRITE_COMMAND for CPU0. Check the different access types are |
# accepted/rejected as expected (2 and 6 are OK). |
|
# WRITE_COMMAND to write bytes for CPU0 (access type 0). This should fail |
# with an error message. |
run_libsim "JTAG WRITE_COMMAND CPU0 write bytes" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000011b285d1780010028000008" \ |
"ERROR: JTAG 8-bit access for SPR not supported." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "0" "2801" "4" |
|
# WRITE_COMMAND to write half words for CPU0 (access type 1). This should fail |
# with an error message. |
run_libsim "JTAG WRITE_COMMAND CPU0 write half words" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000000b0588f380010028000108" \ |
"ERROR: JTAG 16-bit access for SPR not supported." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "1" "2801" "4" |
|
# WRITE_COMMAND to write words for CPU0 (access type 2). |
run_libsim "JTAG WRITE_COMMAND CPU0 write words" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001933eb7e580010028000088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "2" "2801" "4" |
|
# WRITE_COMMAND to write access type 3. This should fail with an error |
# message. |
run_libsim "JTAG WRITE_COMMAND CPU0 access type 3" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000008313620180010028000188" \ |
"ERROR: unknown JTAG SPR access type 3." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "3" "2801" "4" |
|
# WRITE_COMMAND to read bytes for CPU0 (access type 4). This should fail |
# with an error message. |
run_libsim "JTAG WRITE_COMMAND CPU0 read bytes" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000084522e2f80010028000048" \ |
"ERROR: JTAG 8-bit access for SPR not supported." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "4" "2801" "4" |
|
# WRITE_COMMAND to read half words for CPU0 (access type 5). This should fail |
# with an error message. |
run_libsim "JTAG WRITE_COMMAND CPU0 read half words" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001947ffbcb80010028000148" \ |
"ERROR: JTAG 16-bit access for SPR not supported." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "5" "2801" "4" |
|
# WRITE_COMMAND to read words for CPU0 (access type 6) |
run_libsim "JTAG WRITE_COMMAND CPU0 read words" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000000c44c4dd800100280000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "6" "2801" "4" |
|
# WRITE_COMMAND to read access type 7. This should fail with an error message. |
run_libsim "JTAG WRITE_COMMAND CPU0 access type 7" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000011c691139800100280001c8" \ |
"ERROR: unknown JTAG SPR access type 7." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "7" "2801" "4" |
|
# Tests of WRITE_COMMAND addresses for CPU0. Addresses up to 0xffff are |
# OK. Check different addresses are all accepted. For all of these we use the |
# simple loop and a word write. Test the boundaries (addresses 0, 0xffff and |
# 0x10000). Over-size addresses should be truncated with a warning. Remember |
# these are SPR addresses, which are effectively word addresses. |
|
# WRITE_COMMAND for CPU0 to address 0 |
run_libsim "JTAG WRITE_COMMAND CPU0 write address 0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001efa3017580000000000088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "2" "0" "4" |
|
# WRITE_COMMAND for CPU0 to address 0xffff |
run_libsim "JTAG WRITE_COMMAND CPU0 write address 0xffff" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000012e99654d8001fffe000088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "2" "ffff" "4" |
|
# WRITE_COMMAND for CPU0 to address 0x10000. Should be trucated witha |
# warning. |
run_libsim "JTAG WRITE_COMMAND CPU0 write address 0x10000" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000008c6e605180000001000088" \ |
"Warning: truncated JTAG SPR address 0x00010000." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "2" "10000" "4" |
|
# Tests of WRITE_COMMAND lengths for CPU0. Check only length 4 is |
# accepted. For all of these we use the simple loop and write. There is no |
# point in testing values outside the permitted range, since these are |
# rejected in the test code, rather than the target code. Test sizes 3, 4, 5 |
# and 0x10000 bytes. |
|
# Test of WRITE_COMMAND for CPU0 3 bytes. This should fail with an error |
# message. |
run_libsim "JTAG WRITE_COMMAND CPU0 read length 3" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001d735c29c800100280000c8" \ |
"ERROR: JTAG SPR access 0x3 bytes not supported." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "6" "2801" "3" |
|
# Test of WRITE_COMMAND for CPU0 4 bytes. |
run_libsim "JTAG WRITE_COMMAND CPU0 read length 4" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000000c44c4dd800100280000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "6" "2801" "4" |
|
# Test of WRITE_COMMAND for CPU0 5 bytes. This should fail with an error |
# message. |
run_libsim "JTAG WRITE_COMMAND CPU0 read length 5" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000014c51002c400100280000c8" \ |
"ERROR: JTAG SPR access 0x5 bytes not supported." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "6" "2801" "5" |
|
# Test of WRITE_COMMAND for CPU0 0x10000 bytes. This should fail with an error |
# message. |
run_libsim "JTAG WRITE_COMMAND CPU0 read length 0x10000" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000046c16443ffff00280000c8" \ |
"ERROR: JTAG SPR access 0x10000 bytes not supported." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "6" "2801" "10000" |
/jtag-select-module.exp
0,0 → 1,414
# jtag-select-module.exp. Tests of the library JTAG module selection |
|
# Copyright (C) 2010 Embecosm Limited |
|
# Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
|
# This file is part of OpenRISC 1000 Architectural Simulator. |
|
# This program is free software; you can redistribute it and/or modify it |
# under the terms of the GNU General Public License as published by the Free |
# Software Foundation; either version 3 of the License, or (at your option) |
# any later version. |
|
# This program is distributed in the hope that it will be useful, but WITHOUT |
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
# more details. |
|
# You should have received a copy of the GNU General Public License along |
# with this program. If not, see <http:#www.gnu.org/licenses/>. */ |
|
# ----------------------------------------------------------------------------- |
# This code is commented throughout for use with Doxygen. |
# ----------------------------------------------------------------------------- |
|
|
# These tests check all the module selection behavior. Behavior consequential |
# on subsequent commands (WRITE_COMMAND, READ_COMMAND, GO_COMMAND_READ, |
# GO_COMMAND_WRITE, READ_CONTROL and READ_CONTROL) appears in the test file |
# for that command. |
|
# NOTE. All these tests return timing information, but we ignore it, since in |
# general it will not be repeatable. |
|
# Just check if we can reset |
run_libsim "JTAG SELECT_MODULE reset" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" |
|
# Check instruction selection. Just a partial test. Comprehensive testing of |
# this is in jtag-basic.exp |
run_libsim "JTAG SELECT_MODULE EXTEST instr" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x00" \ |
"Warning: JTAG EXTEST shifted" \ |
" shifted out: 0x00" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "0" |
|
run_libsim "JTAG SELECT_MODULE invalid instr" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x0c" \ |
"ERROR: Unknown JTAG instruction 0x3 shifted" \ |
" shifted out: 0x0c" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "3" |
|
run_libsim "JTAG SELECT_MODULE DEBUG instr" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" |
|
# Comprehensive test of selecting all possible modules. Only Wishbone (0), |
# CPU0 (1) and CPU1 (2) should work silently (although CPU1 will prompt |
# warnings if subsequent GO commands are used). All other values will fail by |
# setting the status field on response. |
|
# Wishbone module select (0) |
run_libsim "JTAG SELECT_MODULE SELECT_MODULE WB (0)" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "0" |
|
# CPU0 module select (1) |
run_libsim "JTAG SELECT_MODULE SELECT_MODULE CPU0 (1)" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "1" |
|
# CPU1 module select (2) |
run_libsim "JTAG SELECT_MODULE SELECT_MODULE CPU1 (2)" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000001993c98e69" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "2" |
|
# All remaining modules should fail |
run_libsim "JTAG SELECT_MODULE SELECT_MODULE 3" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000424d9ea79" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "3" |
|
run_libsim "JTAG SELECT_MODULE SELECT_MODULE 4" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000102585a565" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "4" |
|
run_libsim "JTAG SELECT_MODULE SELECT_MODULE 5" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000d9295c175" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "5" |
|
run_libsim "JTAG SELECT_MODULE SELECT_MODULE 6" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000001efe0d976d" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "6" |
|
run_libsim "JTAG SELECT_MODULE SELECT_MODULE 7" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x000000000003491df37d" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "7" |
|
run_libsim "JTAG SELECT_MODULE SELECT_MODULE 8" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x000000000014fea3b0e3" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "8" |
|
run_libsim "JTAG SELECT_MODULE SELECT_MODULE 9" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000949b3d4f3" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "9" |
|
run_libsim "JTAG SELECT_MODULE SELECT_MODULE 10" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000001a252b82eb" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "a" |
|
run_libsim "JTAG SELECT_MODULE SELECT_MODULE 11" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x000000000007923be6fb" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "b" |
|
run_libsim "JTAG SELECT_MODULE SELECT_MODULE 12" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000139367a9e7" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "c" |
|
run_libsim "JTAG SELECT_MODULE SELECT_MODULE 13" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000e2477cdf7" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "d" |
|
run_libsim "JTAG SELECT_MODULE SELECT_MODULE 14" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000001d48ef9bef" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "e" |
|
run_libsim "JTAG SELECT_MODULE SELECT_MODULE 15" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x000000000000ffffffff" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "f" |
/default.cfg
0,0 → 1,183
/* default.cfg -- Or1ksim default configuration script file |
|
Copyright (C) 2001, Marko Mlinar <markom@opencores.org> |
Copyright (C) 2010 Embecosm Limited |
|
Contributor Marko Mlinar <markom@opencores.org> |
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify it |
under the terms of the GNU General Public License as published by the Free |
Software Foundation; either version 3 of the License, or (at your option) |
any later version. |
|
This program is distributed in the hope that it will be useful, but WITHOUT |
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
more details. |
|
You should have received a copy of the GNU General Public License along |
with this program. If not, see <http: www.gnu.org/licenses/>. */ |
|
section memory |
/*random_seed = 12345 |
type = random*/ |
pattern = 0x00 |
type = unknown /* Fastest */ |
|
name = "FLASH" |
ce = 0 |
mc = 0 |
baseaddr = 0xf0000000 |
size = 0x00200000 |
delayr = 10 |
delayw = -1 |
end |
|
section memory |
/*random_seed = 12345 |
type = random*/ |
pattern = 0x00 |
type = unknown /* Fastest */ |
|
name = "RAM" |
ce = 1 |
mc = 0 |
baseaddr = 0x00000000 |
size = 0x00200000 |
delayr = 2 |
delayw = 4 |
end |
|
/* High memory for testing */ |
section memory |
/*random_seed = 12345 |
type = random*/ |
pattern = 0x00 |
type = unknown /* Fastest */ |
|
name = "RAM" |
ce = 2 |
mc = 0 |
baseaddr = 0xffe00000 |
size = 0x00200000 |
delayr = 2 |
delayw = 4 |
end |
|
section immu |
enabled = 1 |
nsets = 64 |
nways = 1 |
ustates = 2 |
pagesize = 8192 |
end |
|
section dmmu |
enabled = 1 |
nsets = 64 |
nways = 1 |
ustates = 2 |
pagesize = 8192 |
end |
|
section ic |
enabled = 1 |
nsets = 256 |
nways = 1 |
ustates = 2 |
blocksize = 16 |
end |
|
section dc |
enabled = 1 |
nsets = 256 |
nways = 1 |
ustates = 2 |
blocksize = 16 |
end |
|
/* Set the CPU to take vectors at 0xf0000000 */ |
section cpu |
ver = 0x12 |
rev = 0x0001 |
/* upr = */ |
sr = 0xc001 |
superscalar = 0 |
hazards = 0 |
dependstats = 0 |
end |
|
section bpb |
enabled = 0 |
btic = 0 |
end |
|
section debug |
/* enabled = 1 |
rsp_enabled = 1 |
rsp_port = 51000*/ |
end |
|
section sim |
debug = 0 |
profile = 0 |
prof_fn = "sim.profile" |
|
exe_log = 0 |
exe_log_type = software |
exe_log_fn = "executed.log" |
end |
|
/* Memory instead of MC. Stops write errors when the startup code tries to |
access a non-existent MC */ |
section memory |
/*random_seed = 12345 |
type = random*/ |
pattern = 0x00 |
type = unknown /* Fastest */ |
|
name = "MC shadow" |
baseaddr = 0x93000000 |
size = 0x00000080 |
delayr = 2 |
delayw = 4 |
end |
|
/* Disabled */ |
section mc |
enabled = 0 |
baseaddr = 0x93000000 |
POC = 0x00000008 /* Power on configuration register */ |
index = 0 |
end |
|
section dma |
baseaddr = 0xB8000000 |
irq = 4 |
end |
|
section ethernet |
enabled = 0 |
baseaddr = 0x92000000 |
irq = 4 |
rtx_type = 0 |
end |
|
section VAPI |
enabled = 0 |
server_port = 9998 |
end |
|
section fb |
enabled = 1 |
baseaddr = 0x97000000 |
refresh_rate = 10000 |
filename = "primary" |
end |
|
section kbd |
enabled = 0 |
end |
/jtag-write-control.exp
0,0 → 1,426
# jtag-write-control.exp. Tests of the library JTAG WRITE_CONTROL command |
|
# Copyright (C) 2010 Embecosm Limited |
|
# Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
|
# This file is part of OpenRISC 1000 Architectural Simulator. |
|
# This program is free software; you can redistribute it and/or modify it |
# under the terms of the GNU General Public License as published by the Free |
# Software Foundation; either version 3 of the License, or (at your option) |
# any later version. |
|
# This program is distributed in the hope that it will be useful, but WITHOUT |
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
# more details. |
|
# You should have received a copy of the GNU General Public License along |
# with this program. If not, see <http:#www.gnu.org/licenses/>. */ |
|
# ----------------------------------------------------------------------------- |
# This code is commented throughout for use with Doxygen. |
# ----------------------------------------------------------------------------- |
|
|
# These tests check all the behavior associated with the JTAG WRITE_CONTROL |
# command. |
|
# NOTE. All these tests return timing information, but we ignore it, since in |
# general it will not be repeatable. |
|
# Tests of the WRITE_CONTROL for writing from different modules. This should |
# work fine for CPU0, but provoke a warning for Wishbone and CPU1 and a |
# different warning for all other modules. Test no module, Wishbone, CPU0, |
# CPU1 and module 6. |
|
# WRITE_CONTROL with no module selected. |
run_libsim "JTAG WRITE_CONTROL no module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_CONTROL." \ |
" shifting in: 0x000000000096dc049200000000000004" \ |
"ERROR: JTAG WRITE_CONTROL with no module selected." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "WRITE_CONTROL" "0" "0" |
|
# WRITE_CONTROL with only WishBone module selected. |
run_libsim "JTAG WRITE_CONTROL WB module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_CONTROL." \ |
" shifting in: 0x000000000096dc049200000000000004" \ |
"ERROR: JTAG WRITE_CONTROL of WishBone not supported." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_CONTROL" "0" "0" |
|
# WRITE_CONTROL with only invalid module selected. |
run_libsim "JTAG WRITE_CONTROL invalid module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000001993c98e69" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_CONTROL." \ |
" shifting in: 0x000000000096dc049200000000000004" \ |
"ERROR: JTAG WRITE_CONTROL of CPU1 not supported." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "2" "WRITE_CONTROL" "0" "0" |
|
# WRITE_CONTROL with invalid module selected after valid module |
run_libsim "JTAG WRITE_CONTROL invalid after valid module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x000000000003491df37d" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_CONTROL." \ |
" shifting in: 0x000000000096dc049200000000000004" \ |
"ERROR: JTAG WRITE_CONTROL with no module selected." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "SELECT_MODULE" "7" "WRITE_CONTROL" "0" "0" |
|
# WRITE_CONTROL with valid module selected after invalid module |
run_libsim "JTAG WRITE_CONTROL valid after invalid module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x000000000003491df37d" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
" shifting in: 0x000000000096dc049200000000000004" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "7" "SELECT_MODULE" "1" "WRITE_CONTROL" "0" "0" |
|
# Verify that writing works correctly from the valid module, CPU0. |
|
# WRITE_CONTROL for CPU0. |
run_libsim "JTAG WRITE_CONTROL CPU0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_CONTROL." \ |
" shifting in: 0x000000000096dc049200000000000004" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_CONTROL" "0" "0" |
|
# Test of setting and clearing the stall bit for CPU0. We can only do this via |
# multiple WRITE_COMMANDs. After stalling we should complete execution on a |
# breakpoint and after clearing complete OK. |
|
# Set the stall bit. |
run_libsim "JTAG WRITE_CONTROL CPU0 set stall" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_CONTROL." \ |
" shifting in: 0x000000000109a677aa00000000000044" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed with breakpoint." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_CONTROL" "0" "1" |
|
# Clear the stall bit. |
run_libsim "JTAG WRITE_CONTROL CPU0 clear stall" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_CONTROL." \ |
" shifting in: 0x000000000096dc049200000000000004" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_CONTROL" "0" "0" |
|
# Set, then clear the stall bit. |
run_libsim "JTAG WRITE_CONTROL CPU0 set then clear stall" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_CONTROL." \ |
" shifting in: 0x000000000109a677aa00000000000044" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed with breakpoint." \ |
"Processing WRITE_CONTROL." \ |
" shifting in: 0x000000000096dc049200000000000004" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "1" "WRITE_CONTROL" "0" "1" "WRITE_CONTROL" "0" "0" |
|
# Clear, then set the stall bit. |
run_libsim "JTAG WRITE_CONTROL CPU0 clear then set stall" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_CONTROL." \ |
" shifting in: 0x000000000096dc049200000000000004" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_CONTROL." \ |
" shifting in: 0x000000000109a677aa00000000000044" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed with breakpoint." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "1" "WRITE_CONTROL" "0" "0" "WRITE_CONTROL" "0" "1" |
|
# Test the reset bit. We can see this works, becaause the PIC puts out a |
# message on reset. |
|
# Set the reset bit. |
run_libsim "JTAG WRITE_CONTROL CPU0 reset" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_CONTROL." \ |
" shifting in: 0x000000000059613d0e00000000000024" \ |
"Resetting PIC." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_CONTROL" "1" "0" |
|
# Verify that reset overrides any simultaneous stall |
run_libsim "JTAG WRITE_CONTROL CPU0 stall and reset" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_CONTROL." \ |
" shifting in: 0x0000000001c61b4e3600000000000064" \ |
"Resetting PIC." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_CONTROL" "1" "1" |
|
# Verify that reset clears any previous stall |
run_libsim "JTAG WRITE_CONTROL CPU0 stall then reset" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_CONTROL." \ |
" shifting in: 0x000000000109a677aa00000000000044" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed with breakpoint." \ |
"Processing WRITE_CONTROL." \ |
" shifting in: 0x000000000059613d0e00000000000024" \ |
"Resetting PIC." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_CONTROL" "0" "1" "WRITE_CONTROL" "1" "0" |
/jtag-go-command-write.exp
0,0 → 1,2232
# jtag-go-command-write.exp. Tests of the library JTAG GO_COMMAND for writing |
|
# Copyright (C) 2010 Embecosm Limited |
|
# Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
|
# This file is part of OpenRISC 1000 Architectural Simulator. |
|
# This program is free software; you can redistribute it and/or modify it |
# under the terms of the GNU General Public License as published by the Free |
# Software Foundation; either version 3 of the License, or (at your option) |
# any later version. |
|
# This program is distributed in the hope that it will be useful, but WITHOUT |
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
# more details. |
|
# You should have received a copy of the GNU General Public License along |
# with this program. If not, see <http:#www.gnu.org/licenses/>. */ |
|
# ----------------------------------------------------------------------------- |
# This code is commented throughout for use with Doxygen. |
# ----------------------------------------------------------------------------- |
|
|
# These tests check all the behavior associated with the JTAG GO_COMMAND when |
# writing. |
|
# NOTE. All these tests return timing information, but we ignore it, since in |
# general it will not be repeatable. |
|
# Tests of the GO_COMMAND for writing to different modules. This should work |
# fine for Wishbone and CPU0. Other modules will have been weeded out by the |
# prior WRITE_COMMAND. We specify 4 bytes to read each time. |
|
# We use the loop-report OpenRISC program here, since we must be sure that |
# values written make it to the target As SPR's we use MACLO (0x2801) and |
# MACHI (0x2802). As Wishbone we use address 0x100000 - 0x12ffff. Changes to |
# values in the first 16 bytes following 0x100000, 0x110000 and 0x120000 are |
# reported. |
|
# When testing GO_COMMAND (write) after invalid module selection, we cannot |
# guarantee a CRC mismatch (or at least I can't do the maths to prove that no |
# register of all zeros can have a valid CRC field for the possible GO_COMMAND |
# register lengths, although it is highly likely), so we just look for the |
# error message. |
|
# GO_COMMAND writing with no module selection (address 0x100000). |
run_libsim "JTAG SELECT_MODULE GO_COMMAND (write) no module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018f4396f780000000100088" \ |
"ERROR: JTAG WRITE_COMMAND with no module selected." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000001a6f47467eefb6af60" \ |
"ERROR: JTAG GO_COMMAND with no prior WRITE_COMMAND." \ |
" shifted out: 0x0000000000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"WRITE_COMMAND" "2" "100000" "4" "GO_COMMAND_WRITE" "deadbeef" |
|
# GO_COMMAND writing with only invalid module selected. |
run_libsim "JTAG GO_COMMAND (write) invalid module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000001993c98e69" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001933eb7e580010028000088" \ |
"ERROR: JTAG WRITE_COMMAND for CPU1 not supported." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000001a6f47467eefb6af60" \ |
"ERROR: JTAG GO_COMMAND with no prior WRITE_COMMAND." \ |
" shifted out: 0x0000000000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "2" "WRITE_COMMAND" "2" "2801" "4" \ |
"GO_COMMAND_WRITE" "deadbeef" |
|
# GO_COMMAND writing with invalid module selected after valid module |
run_libsim "JTAG GO_COMMAND (write) invalid after valid module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000001efe0d976d" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001933eb7e580010028000088" \ |
"ERROR: JTAG WRITE_COMMAND with no module selected." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000001a6f47467eefb6af60" \ |
"ERROR: JTAG GO_COMMAND with no prior WRITE_COMMAND." \ |
" shifted out: 0x0000000000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "SELECT_MODULE" "6" "WRITE_COMMAND" "2" \ |
"2801" "4" "GO_COMMAND_WRITE" "deadbeef" |
|
# GO_COMMAND writing with valid module selected after invalid module |
run_libsim "JTAG GO_COMMAND (write) valid after invalid module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000001efe0d976d" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018f4396f780000000100088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000001a6f47467eefb6af60" \ |
" shifted out: 0x0164841bc6000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "6" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" \ |
"100000" "4" "GO_COMMAND_WRITE" "deadbeef" |
|
# Verify that writing works correctly from both valid modules, WishBone and |
# CPU0. |
|
# GO_COMMAND writing for Wishbone (address 0x100000). |
run_libsim "JTAG SELECT_MODULE GO_COMMAND (write) WB" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018f4396f780000000100088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000001a6f47467eefb6af60" \ |
" shifted out: 0x0164841bc6000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "0" "WRITE_COMMAND" "2" "100000" "4" \ |
"GO_COMMAND_WRITE" "deadbeef" |
|
# GO_COMMAND writing for CPU0 (address 0x2801, MACLO). |
run_libsim "JTAG SELECT_MODULE GO_COMMAND (write) CPU0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001933eb7e580010028000088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000001a6f47467eefb6af60" \ |
" shifted out: 0x0164841bc6000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "1" "WRITE_COMMAND" "2" "2801" "4" \ |
"GO_COMMAND_WRITE" "deadbeef" |
|
# Tests of GO_COMMAND_WRITE with different access alignments, boundaries and |
# lengths for WishBone. For this we use the loop-report program, which reports |
# any changes in values at 0x100000-0x10000f, 0x110000-0x11000f and |
# 0x120000-0x12000f or the SPRs MACLO (0x2801) and MACHI (0x2800), all of |
# which are initialized to zero. |
|
# First check that a single aligned unit can be written for each access type |
# at its allowed alignments. |
|
# GO_COMMAND writing one byte for Wishbone aligned at byte 0. |
run_libsim "JTAG GO_COMMAND (write) WB 1 byte, aligned byte 0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000319cf96400000000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000006d6fa6e6f60" \ |
" shifted out: 0x0164841bc6000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"New byte at 0x00100000 = 0xde" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100000" "1" \ |
"GO_COMMAND_WRITE" "de" |
|
# GO_COMMAND writing one byte for Wishbone aligned at byte 1. |
run_libsim "JTAG GO_COMMAND (write) WB 1 byte, aligned byte 1" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001f3f6ce6400010000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000006d6fa6e6f60" \ |
" shifted out: 0x0164841bc6000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"New byte at 0x00100001 = 0xde" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100001" "1" \ |
"GO_COMMAND_WRITE" "de" |
|
# GO_COMMAND writing one byte for Wishbone aligned at byte 2. |
run_libsim "JTAG GO_COMMAND (write) WB 1 byte, aligned byte 2" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000d0a9e2e400008000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000006d6fa6e6f60" \ |
" shifted out: 0x0164841bc6000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"New byte at 0x00100002 = 0xde" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100002" "1" \ |
"GO_COMMAND_WRITE" "de" |
|
# GO_COMMAND writing one byte for Wishbone aligned at byte 3. |
run_libsim "JTAG GO_COMMAND (write) WB 1 byte, aligned byte 3" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000112c3d5e400018000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000006d6fa6e6f60" \ |
" shifted out: 0x0164841bc6000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"New byte at 0x00100003 = 0xde" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100003" "1" \ |
"GO_COMMAND_WRITE" "de" |
|
# GO_COMMAND writing one half word for Wishbone aligned at byte 0. |
run_libsim "JTAG GO_COMMAND (write) WB 1 half word, aligned byte 0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000fac02ac100000000100108" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000000e463a0ad6af60" \ |
" shifted out: 0x0164841bc600000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"New byte at 0x00100000 = 0xde" \ |
"New byte at 0x00100001 = 0xad" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "100000" "2" \ |
"GO_COMMAND_WRITE" "dead" |
|
# GO_COMMAND writing one half word for Wishbone aligned at byte 2. |
run_libsim "JTAG GO_COMMAND (write) WB 1 half word, aligned byte 2" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000001bf5314100008000100108" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000000e463a0ad6af60" \ |
" shifted out: 0x0164841bc600000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"New byte at 0x00100002 = 0xde" \ |
"New byte at 0x00100003 = 0xad" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "100002" "2" \ |
"GO_COMMAND_WRITE" "dead" |
|
# GO_COMMAND writing one word for Wishbone aligned at byte 0. |
run_libsim "JTAG GO_COMMAND (write) WB 1 word, aligned byte 0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018f4396f780000000100088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000001a6f47467eefb6af60" \ |
" shifted out: 0x0164841bc6000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"New byte at 0x00100000 = 0xde" \ |
"New byte at 0x00100001 = 0xad" \ |
"New byte at 0x00100002 = 0xbe" \ |
"New byte at 0x00100003 = 0xef" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" "100000" "4" \ |
"GO_COMMAND_WRITE" "deadbeef" |
|
# Verify that longer writes work OK, at different boundaries. For byte access |
# write 9 bytes, for half-word access write 10 bytes and for word access write |
# 12 bytes. |
|
# GO_COMMAND writing 9 bytes for Wishbone aligned at byte 0. |
run_libsim "JTAG GO_COMMAND (write) WB 9 bytes, aligned byte 0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000000af2d9ac20000000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000005b486612bafabafea7eefb6af60" \ |
" shifted out: 0x0164841bc60000000000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"New byte at 0x00100000 = 0xde" \ |
"New byte at 0x00100001 = 0xad" \ |
"New byte at 0x00100002 = 0xbe" \ |
"New byte at 0x00100003 = 0xef" \ |
"New byte at 0x00100004 = 0xca" \ |
"New byte at 0x00100005 = 0xfe" \ |
"New byte at 0x00100006 = 0xba" \ |
"New byte at 0x00100007 = 0xbe" \ |
"New byte at 0x00100008 = 0xba" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100000" "9" \ |
"GO_COMMAND_WRITE" "deadbeefcafebabeba" |
|
# GO_COMMAND writing 9 bytes for Wishbone aligned at byte 1. |
run_libsim "JTAG GO_COMMAND (write) WB 9 bytes, aligned byte 1" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001c898eeac20010000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000005b486612bafabafea7eefb6af60" \ |
" shifted out: 0x0164841bc60000000000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"New byte at 0x00100001 = 0xde" \ |
"New byte at 0x00100002 = 0xad" \ |
"New byte at 0x00100003 = 0xbe" \ |
"New byte at 0x00100004 = 0xef" \ |
"New byte at 0x00100005 = 0xca" \ |
"New byte at 0x00100006 = 0xfe" \ |
"New byte at 0x00100007 = 0xba" \ |
"New byte at 0x00100008 = 0xbe" \ |
"New byte at 0x00100009 = 0xba" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100001" "9" \ |
"GO_COMMAND_WRITE" "deadbeefcafebabeba" |
|
# GO_COMMAND writing 9 bytes for Wishbone aligned at byte 2. |
run_libsim "JTAG GO_COMMAND (write) WB 9 bytes, aligned byte 2" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000ebc7c22c20008000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000005b486612bafabafea7eefb6af60" \ |
" shifted out: 0x0164841bc60000000000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"New byte at 0x00100002 = 0xde" \ |
"New byte at 0x00100003 = 0xad" \ |
"New byte at 0x00100004 = 0xbe" \ |
"New byte at 0x00100005 = 0xef" \ |
"New byte at 0x00100006 = 0xca" \ |
"New byte at 0x00100007 = 0xfe" \ |
"New byte at 0x00100008 = 0xba" \ |
"New byte at 0x00100009 = 0xbe" \ |
"New byte at 0x0010000a = 0xba" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100002" "9" \ |
"GO_COMMAND_WRITE" "deadbeefcafebabeba" |
|
# GO_COMMAND writing 9 bytes for Wishbone aligned at byte 3. |
run_libsim "JTAG GO_COMMAND (write) WB 9 bytes, aligned byte 3" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000129adf52c20018000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000005b486612bafabafea7eefb6af60" \ |
" shifted out: 0x0164841bc60000000000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"New byte at 0x00100003 = 0xde" \ |
"New byte at 0x00100004 = 0xad" \ |
"New byte at 0x00100005 = 0xbe" \ |
"New byte at 0x00100006 = 0xef" \ |
"New byte at 0x00100007 = 0xca" \ |
"New byte at 0x00100008 = 0xfe" \ |
"New byte at 0x00100009 = 0xba" \ |
"New byte at 0x0010000a = 0xbe" \ |
"New byte at 0x0010000b = 0xba" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100003" "9" \ |
"GO_COMMAND_WRITE" "deadbeefcafebabeba" |
|
# GO_COMMAND writing 5 half words for Wishbone aligned at byte 0. |
run_libsim "JTAG GO_COMMAND (write) WB 5 half words, aligned byte 0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000c1ae0a0920000000100108" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x0000000000185f4b7296abafabafea7eefb6af60" \ |
" shifted out: 0x0164841bc6000000000000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"New byte at 0x00100000 = 0xde" \ |
"New byte at 0x00100001 = 0xad" \ |
"New byte at 0x00100002 = 0xbe" \ |
"New byte at 0x00100003 = 0xef" \ |
"New byte at 0x00100004 = 0xca" \ |
"New byte at 0x00100005 = 0xfe" \ |
"New byte at 0x00100006 = 0xba" \ |
"New byte at 0x00100007 = 0xbe" \ |
"New byte at 0x00100008 = 0xba" \ |
"New byte at 0x00100009 = 0xad" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "100000" "a" \ |
"GO_COMMAND_WRITE" "deadbeefcafebabebaad" |
|
# GO_COMMAND writing 5 half words for Wishbone aligned at byte 2. |
run_libsim "JTAG GO_COMMAND (write) WB 5 half words, aligned byte 2" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000209b118920008000100108" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x0000000000185f4b7296abafabafea7eefb6af60" \ |
" shifted out: 0x0164841bc6000000000000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"New byte at 0x00100002 = 0xde" \ |
"New byte at 0x00100003 = 0xad" \ |
"New byte at 0x00100004 = 0xbe" \ |
"New byte at 0x00100005 = 0xef" \ |
"New byte at 0x00100006 = 0xca" \ |
"New byte at 0x00100007 = 0xfe" \ |
"New byte at 0x00100008 = 0xba" \ |
"New byte at 0x00100009 = 0xbe" \ |
"New byte at 0x0010000a = 0xba" \ |
"New byte at 0x0010000b = 0xad" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "100002" "a" \ |
"GO_COMMAND_WRITE" "deadbeefcafebabebaad" |
|
# GO_COMMAND writing 3 words for Wishbone aligned at byte 0. |
run_libsim "JTAG GO_COMMAND (write) WB 3 words, aligned byte 0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001b42db63fa0000000100088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000014adb55b7601f6abafabafea7eefb6af60" \ |
" shifted out: 0x0164841bc60000000000000000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"New byte at 0x00100000 = 0xde" \ |
"New byte at 0x00100001 = 0xad" \ |
"New byte at 0x00100002 = 0xbe" \ |
"New byte at 0x00100003 = 0xef" \ |
"New byte at 0x00100004 = 0xca" \ |
"New byte at 0x00100005 = 0xfe" \ |
"New byte at 0x00100006 = 0xba" \ |
"New byte at 0x00100007 = 0xbe" \ |
"New byte at 0x00100008 = 0xba" \ |
"New byte at 0x00100009 = 0xad" \ |
"New byte at 0x0010000a = 0xf0" \ |
"New byte at 0x0010000b = 0x0d" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" "100000" "c" \ |
"GO_COMMAND_WRITE" "deadbeefcafebabebaadf00d" |
|
# Test of access for CPU0. Much simpler, since access type, alignment and |
# length are more prescribed. Make use of loop-report, which monitors MACLO |
# (0x2801) and MACHI (0x2802). These are 32 bit values and presented in target |
# endianess (which is big-endian for the OpenRISC, so the MS byte is as the |
# highest address. |
|
# GO_COMMAND writing 1 word for CPU0 aligned at byte 0. |
run_libsim "JTAG GO_COMMAND (write) CPU0 1 word, aligned byte 0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001933eb7e580010028000088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000001a6f47467eefb6af60" \ |
" shifted out: 0x0164841bc6000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"New MACLO 0xefbeadde" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "2" "2801" "4" \ |
"GO_COMMAND_WRITE" "deadbeef" |
|
# Check address advances after GO (1 per word for CPU, 4 per word for |
# WB). Test WB with writing and reading all sizes and lengths 1 through |
# 0x10000. Test CPU0 with writing and reading words with a range of lengths, |
# all of which should return length 4. |
|
# - for WB byte access try lengths 1, 2, 3, 4, 5, 8 and 9 |
# - for WB half word access try lengths 2, 4, 6, 8 and 10 |
# - for WB full word access try lengths 4, 8 and 12 |
# - for SPR try length 4 |
|
# Advance address after writing 1 byte for WishBone (access type 0) |
run_libsim "JTAG GO_COMMAND (write) WB write 1 byte address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000319cf96400000000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000006d6fa6e6f60" \ |
" shifted out: 0x0164841bc6000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x0e460cbc200001000010000000000000" \ |
" access_type: 0x0" \ |
" address: 0x100001" \ |
" length: 0x1" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100000" "1" \ |
"GO_COMMAND_WRITE" "de" "READ_COMMAND" |
|
# Advance address after writing 2 bytes for WishBone (access type 0) |
run_libsim "JTAG GO_COMMAND (write) WB write 2 bytes address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001eaedff2500000000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000000e463a0ad6af60" \ |
" shifted out: 0x0164841bc600000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x0ebe2296e10000800010000000000000" \ |
" access_type: 0x0" \ |
" address: 0x100002" \ |
" length: 0x2" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100000" "2" \ |
"GO_COMMAND_WRITE" "dead" "READ_COMMAND" |
|
# Advance address after writing 3 bytes for WishBone (access type 0) |
run_libsim "JTAG GO_COMMAND (write) WB write 3 bytes address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000dc247a4480000000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000001599d9120fb6af60" \ |
" shifted out: 0x0164841bc60000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x0e4a8124808001800010000000000000" \ |
" access_type: 0x0" \ |
" address: 0x100003" \ |
" length: 0x3" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100000" "3" \ |
"GO_COMMAND_WRITE" "deadbe" "READ_COMMAND" |
|
# Advance address after writing 4 bytes for WishBone (access type 0) |
run_libsim "JTAG GO_COMMAND (write) WB write 4 bytes address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000107557c0580000000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000001a6f47467eefb6af60" \ |
" shifted out: 0x0164841bc6000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x0ec23583818000400010000000000000" \ |
" access_type: 0x0" \ |
" address: 0x100004" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100000" "4" \ |
"GO_COMMAND_WRITE" "deadbeef" "READ_COMMAND" |
|
# Advance address after writing 5 bytes for WishBone (access type 0) |
run_libsim "JTAG GO_COMMAND (write) WB write 5 bytes address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000004740b8f440000000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000009ac236c4a7eefb6af60" \ |
" shifted out: 0x0164841bc600000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x13f75a14604001400010000000000000" \ |
" access_type: 0x0" \ |
" address: 0x100005" \ |
" length: 0x5" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100000" "5" \ |
"GO_COMMAND_WRITE" "deadbeefca" "READ_COMMAND" |
|
# Advance address after writing 8 bytes for WishBone (access type 0) |
run_libsim "JTAG GO_COMMAND (write) WB write 8 bytes address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000171893d95c0000000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000014db90944fabafea7eefb6af60" \ |
" shifted out: 0x0164841bc600000000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x134b2e6d21c000200010000000000000" \ |
" access_type: 0x0" \ |
" address: 0x100008" \ |
" length: 0x8" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100000" "8" \ |
"GO_COMMAND_WRITE" "deadbeefcafebabe" "READ_COMMAND" |
|
# Advance address after writing 9 bytes for WishBone (access type 0) |
run_libsim "JTAG GO_COMMAND (write) WB write 9 bytes address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000000af2d9ac20000000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000005b486612bafabafea7eefb6af60" \ |
" shifted out: 0x0164841bc60000000000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x009ea7e8002001200010000000000000" \ |
" access_type: 0x0" \ |
" address: 0x100009" \ |
" length: 0x9" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100000" "9" \ |
"GO_COMMAND_WRITE" "deadbeefcafebabeba" "READ_COMMAND" |
|
# Advance address after writing 1 half word (2 bytes) for WishBone (access |
# type 1) |
run_libsim "JTAG GO_COMMAND (write) WB write 1 half word address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000fac02ac100000000100108" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000000e463a0ad6af60" \ |
" shifted out: 0x0164841bc600000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x08c3cb5a010000800010010000000000" \ |
" access_type: 0x1" \ |
" address: 0x100002" \ |
" length: 0x2" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "100000" "2" \ |
"GO_COMMAND_WRITE" "dead" "READ_COMMAND" |
|
# Advance address after writing 2 half words (4 bytes) for WishBone (access |
# type 1) |
run_libsim "JTAG GO_COMMAND (write) WB write 2 half words address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000001778a9e180000000100108" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000001a6f47467eefb6af60" \ |
" shifted out: 0x0164841bc6000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x08bfdc4f618000400010010000000000" \ |
" access_type: 0x1" \ |
" address: 0x100004" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "100000" "4" \ |
"GO_COMMAND_WRITE" "deadbeef" "READ_COMMAND" |
|
# Advance address after writing 3 half words (6 bytes) for WishBone (access |
# type 1) |
run_libsim "JTAG GO_COMMAND (write) WB write 3 half words address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000008c1c6b5140000000100108" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000000c6961b84fea7eefb6af60" \ |
" shifted out: 0x0164841bc60000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x15729df2414000c00010010000000000" \ |
" access_type: 0x1" \ |
" address: 0x100006" \ |
" length: 0x6" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "100000" "6" \ |
"GO_COMMAND_WRITE" "deadbeefcafe" "READ_COMMAND" |
|
# Advance address after writing 4 half words (8 bytes) for WishBone (access |
# type 1) |
run_libsim "JTAG GO_COMMAND (write) WB write 4 half words address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000061a4e871c0000000100108" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000014db90944fabafea7eefb6af60" \ |
" shifted out: 0x0164841bc600000000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x1536c7a1c1c000200010010000000000" \ |
" access_type: 0x1" \ |
" address: 0x100008" \ |
" length: 0x8" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "100000" "8" \ |
"GO_COMMAND_WRITE" "deadbeefcafebabe" "READ_COMMAND" |
|
# Advance address after writing 5 half words (10 bytes) for WishBone (access |
# type 1) |
run_libsim "JTAG GO_COMMAND (write) WB write 5 half words address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000c1ae0a0920000000100108" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x0000000000185f4b7296abafabafea7eefb6af60" \ |
" shifted out: 0x0164841bc6000000000000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x061b600e212000a00010010000000000" \ |
" access_type: 0x1" \ |
" address: 0x10000a" \ |
" length: 0xa" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "100000" "a" \ |
"GO_COMMAND_WRITE" "deadbeefcafebabebaad" "READ_COMMAND" |
|
# Advance address after writing 1 word (4 bytes) for WishBone (access type 2) |
run_libsim "JTAG GO_COMMAND (write) WB write 1 word address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018f4396f780000000100088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000001a6f47467eefb6af60" \ |
" shifted out: 0x0164841bc6000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x104bd101e18000400010008000000000" \ |
" access_type: 0x2" \ |
" address: 0x100004" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" "100000" "4" \ |
"GO_COMMAND_WRITE" "deadbeef" "READ_COMMAND" |
|
# Advance address after writing 2 words (8 bytes) for WishBone (access type 2) |
run_libsim "JTAG GO_COMMAND (write) WB write 2 words address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001f99fd767c0000000100088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000014db90944fabafea7eefb6af60" \ |
" shifted out: 0x0164841bc600000000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x0dc2caef41c000200010008000000000" \ |
" access_type: 0x2" \ |
" address: 0x100008" \ |
" length: 0x8" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" "100000" "8" \ |
"GO_COMMAND_WRITE" "deadbeefcafebabe" "READ_COMMAND" |
|
# Advance address after writing 3 words (12 bytes) for WishBone (access type |
# 2) |
run_libsim "JTAG GO_COMMAND (write) WB write 3 words address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001b42db63fa0000000100088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000014adb55b7601f6abafabafea7eefb6af60" \ |
" shifted out: 0x0164841bc60000000000000000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x1e937a55c1a000600010008000000000" \ |
" access_type: 0x2" \ |
" address: 0x10000c" \ |
" length: 0xc" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" "100000" "c" \ |
"GO_COMMAND_WRITE" "deadbeefcafebabebaadf00d" "READ_COMMAND" |
|
# Advance address after writing 1 word for CPU0 (access type 2). The address |
# should advance by 1 (word, since SPRs are word addressed). |
run_libsim "JTAG GO_COMMAND (write) CPU0 write 1 word address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001933eb7e580010028000088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000001a6f47467eefb6af60" \ |
" shifted out: 0x0164841bc6000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x0f059be9218000802800008000000000" \ |
" access_type: 0x2" \ |
" address: 0x2802" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "2" "2801" "4" \ |
"GO_COMMAND_WRITE" "deadbeef" "READ_COMMAND" |
|
# Tests of overrun and underrun. For Wishbone check both on different access |
# sizes. |
|
# GO_COMMAND_WRITE for WishBone underrun for byte access |
run_libsim "JTAG GO_COMMAND (write) WB byte access underrun" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000171893d95c0000000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000000c1a78bb0bafea7eefb6af60" \ |
" shifted out: 0x015fea3b0e200000000000000000000000" \ |
" status: 0x8" \ |
" time taken:" \ |
"New byte at 0x00100000 = 0xde" \ |
"New byte at 0x00100001 = 0xad" \ |
"New byte at 0x00100002 = 0xbe" \ |
"New byte at 0x00100003 = 0xef" \ |
"New byte at 0x00100004 = 0xca" \ |
"New byte at 0x00100005 = 0xfe" \ |
"New byte at 0x00100006 = 0xba" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100000" "8" \ |
"GO_COMMAND_WRITE" "deadbeefcafeba" |
|
# GO_COMMAND_WRITE for WishBone overrun for byte access |
run_libsim "JTAG GO_COMMAND (write) WB byte access overrun" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000171893d95c0000000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000005b486612bafabafea7eefb6af60" \ |
" shifted out: 0x015fea3b0e2000000000000000000000000000" \ |
" status: 0x8" \ |
" time taken:" \ |
"New byte at 0x00100000 = 0xde" \ |
"New byte at 0x00100001 = 0xad" \ |
"New byte at 0x00100002 = 0xbe" \ |
"New byte at 0x00100003 = 0xef" \ |
"New byte at 0x00100004 = 0xca" \ |
"New byte at 0x00100005 = 0xfe" \ |
"New byte at 0x00100006 = 0xba" \ |
"New byte at 0x00100007 = 0xbe" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100000" "8" \ |
"GO_COMMAND_WRITE" "deadbeefcafebabeba" |
|
# GO_COMMAND_WRITE for WishBone underrun for half word access |
run_libsim "JTAG GO_COMMAND (write) WB half word access underrun" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000061a4e871c0000000100108" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000000c1a78bb0bafea7eefb6af60" \ |
" shifted out: 0x015fea3b0e200000000000000000000000" \ |
" status: 0x8" \ |
" time taken:" \ |
"New byte at 0x00100000 = 0xde" \ |
"New byte at 0x00100001 = 0xad" \ |
"New byte at 0x00100002 = 0xbe" \ |
"New byte at 0x00100003 = 0xef" \ |
"New byte at 0x00100004 = 0xca" \ |
"New byte at 0x00100005 = 0xfe" \ |
"New byte at 0x00100006 = 0xba" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "100000" "8" \ |
"GO_COMMAND_WRITE" "deadbeefcafeba" |
|
# GO_COMMAND_WRITE for WishBone overrun for half word access |
run_libsim "JTAG GO_COMMAND (write) WB half word access overrun" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000061a4e871c0000000100108" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000005b486612bafabafea7eefb6af60" \ |
" shifted out: 0x015fea3b0e2000000000000000000000000000" \ |
" status: 0x8" \ |
" time taken:" \ |
"New byte at 0x00100000 = 0xde" \ |
"New byte at 0x00100001 = 0xad" \ |
"New byte at 0x00100002 = 0xbe" \ |
"New byte at 0x00100003 = 0xef" \ |
"New byte at 0x00100004 = 0xca" \ |
"New byte at 0x00100005 = 0xfe" \ |
"New byte at 0x00100006 = 0xba" \ |
"New byte at 0x00100007 = 0xbe" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "100000" "8" \ |
"GO_COMMAND_WRITE" "deadbeefcafebabeba" |
|
# GO_COMMAND_WRITE for WishBone underrun for word access |
run_libsim "JTAG GO_COMMAND (write) WB word access underrun" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001f99fd767c0000000100088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000000c1a78bb0bafea7eefb6af60" \ |
" shifted out: 0x015fea3b0e200000000000000000000000" \ |
" status: 0x8" \ |
" time taken:" \ |
"New byte at 0x00100000 = 0xde" \ |
"New byte at 0x00100001 = 0xad" \ |
"New byte at 0x00100002 = 0xbe" \ |
"New byte at 0x00100003 = 0xef" \ |
"New byte at 0x00100004 = 0xca" \ |
"New byte at 0x00100005 = 0xfe" \ |
"New byte at 0x00100006 = 0xba" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" "100000" "8" \ |
"GO_COMMAND_WRITE" "deadbeefcafeba" |
|
# GO_COMMAND_WRITE for WishBone overrun for word access |
run_libsim "JTAG GO_COMMAND (write) WB word access overrun" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001f99fd767c0000000100088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000005b486612bafabafea7eefb6af60" \ |
" shifted out: 0x015fea3b0e2000000000000000000000000000" \ |
" status: 0x8" \ |
" time taken:" \ |
"New byte at 0x00100000 = 0xde" \ |
"New byte at 0x00100001 = 0xad" \ |
"New byte at 0x00100002 = 0xbe" \ |
"New byte at 0x00100003 = 0xef" \ |
"New byte at 0x00100004 = 0xca" \ |
"New byte at 0x00100005 = 0xfe" \ |
"New byte at 0x00100006 = 0xba" \ |
"New byte at 0x00100007 = 0xbe" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" "100000" "8" \ |
"GO_COMMAND_WRITE" "deadbeefcafebabeba" |
|
# CPU0 underrun and overrun tests should remember that this is a 32-bit access |
# with a big-endian organization. |
|
# GO_COMMAND_WRITE for CPU0 underrun for word access |
run_libsim "JTAG GO_COMMAND (write) CPU0 word access underrun" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001933eb7e580010028000088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000001599d9120fb6af60" \ |
" shifted out: 0x015fea3b0e2000000000000000" \ |
" status: 0x8" \ |
" time taken:" \ |
"New MACLO 0x00beadde" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "2" "2801" "4" \ |
"GO_COMMAND_WRITE" "deadbe" |
|
# GO_COMMAND_WRITE for CPU0 overrun for word access |
run_libsim "JTAG GO_COMMAND (write) CPU0 word access overrun" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001933eb7e580010028000088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000009ac236c4a7eefb6af60" \ |
" shifted out: 0x015fea3b0e20000000000000000000" \ |
" status: 0x8" \ |
" time taken:" \ |
"New MACLO 0xefbeadde" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "2" "2801" "4" \ |
"GO_COMMAND_WRITE" "deadbeefca" |
|
# Test access to invalid areas. We can only do this for Wishbone, since all |
# SPRs are validly accessible (non-writeable ones just return undefined |
# results). |
|
# Test each access type with one unit and test blocks spanning start and end |
# of writeable blocks. |
|
# GO_COMMAND_WRITE for 1 byte write to invalid memory. |
run_libsim "JTAG GO_COMMAND (write) WB 1 byte invalid write" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001ba7d236600000000080008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000006d6fa6e6f60" \ |
" shifted out: 0x0112585a56400000000000" \ |
" status: 0x4" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "200000" "1" \ |
"GO_COMMAND_WRITE" "de" |
|
# GO_COMMAND_WRITE for 2 byte write ending in invalid memory. |
run_libsim "JTAG GO_COMMAND (write) WB 2 byte ending invalid write" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001bbbf3ba70001fffff00008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000000e463a0ad6af60" \ |
" shifted out: 0x0112585a5640000000000000" \ |
" status: 0x4" \ |
" time taken:" \ |
"New byte at 0x001fffff = 0xde" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "1fffff" "2" \ |
"GO_COMMAND_WRITE" "dead" |
|
# GO_COMMAND_WRITE for 2 byte write starting in invalid memory. |
run_libsim "JTAG GO_COMMAND (write) WB 2 byte starting invalid write" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000fd76999f0001fffff7fe08" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000000e463a0ad6af60" \ |
" shifted out: 0x0112585a5640000000000000" \ |
" status: 0x4" \ |
" time taken:" \ |
"New byte at 0xffe00000 = 0xad" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "ffdfffff" "2" \ |
"GO_COMMAND_WRITE" "dead" |
|
# GO_COMMAND_WRITE for 1 half word write to invalid memory. |
run_libsim "JTAG GO_COMMAND (write) WB 1 half word invalid write" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000017121f0c300000000080108" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000000e463a0ad6af60" \ |
" shifted out: 0x0112585a5640000000000000" \ |
" status: 0x4" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "200000" "2" \ |
"GO_COMMAND_WRITE" "dead" |
|
# GO_COMMAND_WRITE for 2 half word write ending in invalid memory. |
run_libsim "JTAG GO_COMMAND (write) WB 2 half word ending invalid write" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000184405a638000fffff00108" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000001a6f47467eefb6af60" \ |
" shifted out: 0x0112585a56400000000000000000" \ |
" status: 0x4" \ |
" time taken:" \ |
"New byte at 0x001ffffe = 0xde" \ |
"New byte at 0x001fffff = 0xad" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "1ffffe" "4" \ |
"GO_COMMAND_WRITE" "deadbeef" |
|
# GO_COMMAND_WRITE for 2 half word write starting in invalid memory. |
run_libsim "JTAG GO_COMMAND (write) WB 2 half word starting invalid write" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000c289f85b8000fffff7ff08" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000001a6f47467eefb6af60" \ |
" shifted out: 0x0112585a56400000000000000000" \ |
" status: 0x4" \ |
" time taken:" \ |
"New byte at 0xffe00000 = 0xbe" \ |
"New byte at 0xffe00001 = 0xef" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "ffdffffe" "4" \ |
"GO_COMMAND_WRITE" "deadbeef" |
|
# GO_COMMAND_WRITE for 1 word write to invalid memory. |
run_libsim "JTAG GO_COMMAND (write) WB 1 word invalid write" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000004a24cf580000000080088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x00000000001a6f47467eefb6af60" \ |
" shifted out: 0x0112585a56400000000000000000" \ |
" status: 0x4" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" "200000" "4" \ |
"GO_COMMAND_WRITE" "deadbeef" |
|
# GO_COMMAND_WRITE for 2 word write ending in invalid memory. |
run_libsim "JTAG GO_COMMAND (write) WB 2 word ending invalid write" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000008b923f65c0007ffff00088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000014db90944fabafea7eefb6af60" \ |
" shifted out: 0x0112585a5640000000000000000000000000" \ |
" status: 0x4" \ |
" time taken:" \ |
"New byte at 0x001ffffc = 0xde" \ |
"New byte at 0x001ffffd = 0xad" \ |
"New byte at 0x001ffffe = 0xbe" \ |
"New byte at 0x001fffff = 0xef" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" "1ffffc" "8" \ |
"GO_COMMAND_WRITE" "deadbeefcafebabe" |
|
# GO_COMMAND_WRITE for 2 word write starting in invalid memory. |
run_libsim "JTAG GO_COMMAND (write) WB 2 word starting invalid write" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001cd5b9d5dc0007ffff7fe88" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_WRITE." \ |
" shifting in: 0x000000000014db90944fabafea7eefb6af60" \ |
" shifted out: 0x0112585a5640000000000000000000000000" \ |
" status: 0x4" \ |
" time taken:" \ |
"New byte at 0xffe00000 = 0xca" \ |
"New byte at 0xffe00001 = 0xfe" \ |
"New byte at 0xffe00002 = 0xba" \ |
"New byte at 0xffe00003 = 0xbe" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-report" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" "ffdffffc" "8" \ |
"GO_COMMAND_WRITE" "deadbeefcafebabe" |
/jtag-basic.exp
0,0 → 1,261
# jtag-basic.exp. Basic tests of the library JTAG interface functions. |
|
# Copyright (C) 2010 Embecosm Limited |
|
# Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
|
# This file is part of OpenRISC 1000 Architectural Simulator. |
|
# This program is free software; you can redistribute it and/or modify it |
# under the terms of the GNU General Public License as published by the Free |
# Software Foundation; either version 3 of the License, or (at your option) |
# any later version. |
|
# This program is distributed in the hope that it will be useful, but WITHOUT |
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
# more details. |
|
# You should have received a copy of the GNU General Public License along |
# with this program. If not, see <http:#www.gnu.org/licenses/>. */ |
|
# ----------------------------------------------------------------------------- |
# This code is commented throughout for use with Doxygen. |
# ----------------------------------------------------------------------------- |
|
|
# These are the tests based on feeding in plain instruction or data registers |
# to the JTAG interface. |
|
# Just check if we can reset |
run_libsim "lib-jtag reset" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag" "" "loop/loop" "R" |
|
# Check instruction loading, 4 bits, MS bit shifted from the bottom. |
run_libsim "lib-jtag IR 0000" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction register." \ |
" shifting in: 00" \ |
"Warning: JTAG EXTEST shifted" \ |
" shifted out: 00" \ |
" time taken " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag" "" "loop/loop" "R" "I" "4" "0" |
|
run_libsim "lib-jtag IR 0001" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction register." \ |
" shifting in: 08" \ |
"Warning: JTAG SAMPLE/PRELOAD shifted" \ |
" shifted out: 08" \ |
" time taken " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag" "" "loop/loop" "R" "I" "4" "8" |
|
run_libsim "lib-jtag IR 0010" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction register." \ |
" shifting in: 04" \ |
"Warning: JTAG IDCODE shifted" \ |
" shifted out: 04" \ |
" time taken " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag" "" "loop/loop" "R" "I" "4" "4" |
|
run_libsim "lib-jtag instr reg 0011" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction register." \ |
" shifting in: 0c" \ |
"ERROR: Unknown JTAG instruction 0x3 shifted" \ |
" shifted out: 0c" \ |
" time taken " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag" "" "loop/loop" "R" "I" "4" "c" |
|
run_libsim "lib-jtag instr reg 0100" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction register." \ |
" shifting in: 02" \ |
"ERROR: Unknown JTAG instruction 0x4 shifted" \ |
" shifted out: 02" \ |
" time taken " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag" "" "loop/loop" "R" "I" "4" "2" |
|
run_libsim "lib-jtag instr reg 0101" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction register." \ |
" shifting in: 0a" \ |
"ERROR: Unknown JTAG instruction 0x5 shifted" \ |
" shifted out: 0a" \ |
" time taken " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag" "" "loop/loop" "R" "I" "4" "a" |
|
run_libsim "lib-jtag instr reg 0110" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction register." \ |
" shifting in: 06" \ |
"ERROR: Unknown JTAG instruction 0x6 shifted" \ |
" shifted out: 06" \ |
" time taken " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag" "" "loop/loop" "R" "I" "4" "6" |
|
run_libsim "lib-jtag instr reg 0111" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction register." \ |
" shifting in: 0e" \ |
"ERROR: Unknown JTAG instruction 0x7 shifted" \ |
" shifted out: 0e" \ |
" time taken " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag" "" "loop/loop" "R" "I" "4" "e" |
|
run_libsim "lib-jtag instr reg 1000" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction register." \ |
" shifting in: 01" \ |
" shifted out: 01" \ |
" time taken " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag" "" "loop/loop" "R" "I" "4" "1" |
|
run_libsim "lib-jtag IR 1001" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction register." \ |
" shifting in: 09" \ |
"Warning: JTAG MBIST shifted" \ |
" shifted out: 09" \ |
" time taken " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag" "" "loop/loop" "R" "I" "4" "9" |
|
run_libsim "lib-jtag instr reg 1010" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction register." \ |
" shifting in: 05" \ |
"ERROR: Unknown JTAG instruction 0xa shifted" \ |
" shifted out: 05" \ |
" time taken " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag" "" "loop/loop" "R" "I" "4" "5" |
|
run_libsim "lib-jtag instr reg 1011" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction register." \ |
" shifting in: 0d" \ |
"ERROR: Unknown JTAG instruction 0xb shifted" \ |
" shifted out: 0d" \ |
" time taken " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag" "" "loop/loop" "R" "I" "4" "d" |
|
run_libsim "lib-jtag instr reg 1100" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction register." \ |
" shifting in: 03" \ |
"ERROR: Unknown JTAG instruction 0xc shifted" \ |
" shifted out: 03" \ |
" time taken " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag" "" "loop/loop" "R" "I" "4" "3" |
|
run_libsim "lib-jtag instr reg 1101" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction register." \ |
" shifting in: 0b" \ |
"ERROR: Unknown JTAG instruction 0xd shifted" \ |
" shifted out: 0b" \ |
" time taken " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag" "" "loop/loop" "R" "I" "4" "b" |
|
run_libsim "lib-jtag instr reg 1110" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction register." \ |
" shifting in: 07" \ |
"ERROR: Unknown JTAG instruction 0xe shifted" \ |
" shifted out: 07" \ |
" time taken " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag" "" "loop/loop" "R" "I" "4" "7" |
|
run_libsim "lib-jtag IR 1111" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction register." \ |
" shifting in: 0f" \ |
"Warning: JTAG BYPASS shifted" \ |
" shifted out: 0f" \ |
" time taken " \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag" "" "loop/loop" "R" "I" "4" "f" |
/jtag-read-command.exp
0,0 → 1,804
# jtag-read-command.exp. Tests of the library JTAG READ_COMMAND functions. |
|
# Copyright (C) 2010 Embecosm Limited |
|
# Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
|
# This file is part of OpenRISC 1000 Architectural Simulator. |
|
# This program is free software; you can redistribute it and/or modify it |
# under the terms of the GNU General Public License as published by the Free |
# Software Foundation; either version 3 of the License, or (at your option) |
# any later version. |
|
# This program is distributed in the hope that it will be useful, but WITHOUT |
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
# more details. |
|
# You should have received a copy of the GNU General Public License along |
# with this program. If not, see <http:#www.gnu.org/licenses/>. */ |
|
# ----------------------------------------------------------------------------- |
# This code is commented throughout for use with Doxygen. |
# ----------------------------------------------------------------------------- |
|
|
# These are the tests of the high level JTAG interface. |
|
# NOTE. All these tests return timing information, but we ignore it, since in |
# general it will not be repeatable. |
|
# Tests of READ_COMMAND returning the correct data back. Use Wishbone as |
# module, since it has the widest range of fields for WRITE_COMMAND. We don't |
# do any actual reading or writing, so the simple loop program is |
# sufficient. |
|
# Test of READ_COMMAND when no WRITE_COMMAND has been issued. |
run_libsim "JTAG READ_COMMAND no prior write" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
"ERROR: JTAG READ_COMMAND finds no data" \ |
" shifted out: 0x0c526410200000000000000000000000" \ |
" access_type: 0x0" \ |
" address: 0x0" \ |
" length: 0x1" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "READ_COMMAND" |
|
# READ_COMMAND when invalid WRITE_COMMAND has been issued. |
run_libsim "JTAG READ_COMMAND no valid prior write" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000009f6e431380000000100188" \ |
"ERROR: JTAG WRITE_COMMAND unknown access type 3." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
"ERROR: JTAG READ_COMMAND finds no data." \ |
" shifted out: 0x0c526410200000000000000000000000" \ |
" access_type: 0x0" \ |
" address: 0x0" \ |
" length: 0x1" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "3" "100000" "4" \ |
"READ_COMMAND" |
|
# READ_COMMAND when invalid WRITE_COMMAND has been issued after a previously |
# valid WRITE_COMMAND. |
run_libsim "JTAG READ_COMMAND invalid after valid prior write" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018f4396f780000000100088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000009f6e431380000000100188" \ |
"ERROR: JTAG WRITE_COMMAND unknown access type 3." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
"ERROR: JTAG READ_COMMAND finds no data." \ |
" shifted out: 0x0c526410200000000000000000000000" \ |
" access_type: 0x0" \ |
" address: 0x0" \ |
" length: 0x1" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" "100000" "4" \ |
"WRITE_COMMAND" "3" "100000" "4" "READ_COMMAND" |
|
# READ_COMMAND when valid WRITE_COMMAND has been issued after a previously |
# invalid WRITE_COMMAND. |
run_libsim "JTAG READ_COMMAND valid after invalid prior write" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000009f6e431380000000100188" \ |
"ERROR: JTAG WRITE_COMMAND unknown access type 3." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018f4396f780000000100088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x103b4b8c218000000010008000000000" \ |
" access_type: 0x2" \ |
" address: 0x100000" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "3" "100000" "4" \ |
"WRITE_COMMAND" "2" "100000" "4" "READ_COMMAND" |
|
# Tests of READ_COMMAND with WRITE_COMMANDS to different modules. Should work |
# for WB and CPU0. Rejection of other modules should happen earlier, so not |
# tested here. |
|
# READ_COMMAND for Wishbone |
run_libsim "JTAG SELECT_MODULE READ_COMMAND WB" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018f4396f780000000100088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x103b4b8c218000000010008000000000" \ |
" access_type: 0x2" \ |
" address: 0x100000" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "0" "WRITE_COMMAND" "2" "100000" "4" "READ_COMMAND" |
|
# READ_COMMAND for CPU0 |
run_libsim "JTAG SELECT_MODULE READ_COMMAND CPU0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001933eb7e580010028000088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x0e26c4c5a18001002800008000000000" \ |
" access_type: 0x2" \ |
" address: 0x2801" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" "8" \ |
"SELECT_MODULE" "1" "WRITE_COMMAND" "2" "2801" "4" "READ_COMMAND" |
|
# Tests of READ_COMMAND access types correctly being returned. Errors should |
# be prevented earlier in the WRITE_COMMAND, so we only check behavior that |
# would follow a valid WRITE_COMMAND. |
|
# READ_COMMAND to write bytes for WishBone (access type 0) |
run_libsim "JTAG READ_COMMAND WB write bytes" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000107557c0580000000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x0eb2af0e418000000010000000000000" \ |
" access_type: 0x0" \ |
" address: 0x100000" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100000" "4" \ |
"READ_COMMAND" |
|
# READ_COMMAND to write half words for WishBone (access type 1) |
run_libsim "JTAG READ_COMMAND WB write half words" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000001778a9e180000000100108" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x08cf46c2a18000000010010000000000" \ |
" access_type: 0x1" \ |
" address: 0x100000" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "1" "100000" "4" \ |
"READ_COMMAND" |
|
# READ_COMMAND to write words for WishBone (access type 2) |
run_libsim "JTAG READ_COMMAND WB write words" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018f4396f780000000100088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x103b4b8c218000000010008000000000" \ |
" access_type: 0x2" \ |
" address: 0x100000" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" "100000" "4" \ |
"READ_COMMAND" |
|
# READ_COMMAND to read bytes for WishBone (access type 4) |
run_libsim "JTAG READ_COMMAND WB read bytes" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000982f0f3d80000000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x1c414d2b618000000010004000000000" \ |
" access_type: 0x4" \ |
" address: 0x100000" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100000" "4" \ |
"READ_COMMAND" |
|
# READ_COMMAND to read half words for WishBone (access type 5) |
run_libsim "JTAG READ_COMMAND WB read half words" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018802dad980000000100148" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x1a3ca4e7818000000010014000000000" \ |
" access_type: 0x5" \ |
" address: 0x100000" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "100000" "4" \ |
"READ_COMMAND" |
|
# READ_COMMAND to read words for WishBone (access type 6) |
run_libsim "JTAG READ_COMMAND WB read words" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000001039e5cf800000001000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x02c8a9a901800000001000c000000000" \ |
" access_type: 0x6" \ |
" address: 0x100000" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" "100000" "4" \ |
"READ_COMMAND" |
|
# Check address ranges. For Wishbone check 0x0 and 0xffffffff. For CPU0 check |
# 0x12801 also still works, even though it is an invalid address for a SPR (it |
# should be truncated with a warning). |
|
# READ_COMMAND to write to address 0 for WishBone |
run_libsim "JTAG READ_COMMAND WB write address 0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001efa3017580000000000088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x13ed4917218000000000008000000000" \ |
" access_type: 0x2" \ |
" address: 0x0" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" "0" "4" \ |
"READ_COMMAND" |
|
# READ_COMMAND to write to address 0xffffffff for WishBone |
run_libsim "JTAG READ_COMMAND WB write address 0xffffffff" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000cd06d25e0001fffffffe08" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x1fa286fa800001fffffffe0000000000" \ |
" access_type: 0x0" \ |
" address: 0xffffffff" \ |
" length: 0x1" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "ffffffff" "1" \ |
"READ_COMMAND" |
|
# READ_COMMAND to write to address 0 for CPU0. |
run_libsim "JTAG READ_COMMAND CPU0 write address 0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001efa3017580000000000088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x13ed4917218000000000008000000000" \ |
" access_type: 0x2" \ |
" address: 0x0" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "2" "0" "4" \ |
"READ_COMMAND" |
|
# READ_COMMAND to write to address 0xffff for CPU0. |
run_libsim "JTAG READ_COMMAND CPU0 write address 0xffff" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000012e99654d8001fffe000088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x0040eb25018001fffe00008000000000" \ |
" access_type: 0x2" \ |
" address: 0xffff" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "2" "ffff" "4" \ |
"READ_COMMAND" |
|
# READ_COMMAND to write to address 0x12801 for CPU0. Even though out of range, |
# this should work, since it will be truncated. |
run_libsim "JTAG READ_COMMAND CPU0 write address 0x12801" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000f0f3d6c180010029000088" \ |
"Warning: truncated JTAG SPR address 0x00012801." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x0e26c4c5a18001002800008000000000" \ |
" access_type: 0x2" \ |
" address: 0x2801" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "2" "12801" "4" \ |
"READ_COMMAND" |
|
# Check lengths. For Wishbone check 0x1 and 0x10000. For CPU0 check 0x4, which |
# is the only valid length (tests of failure will have been done as part of |
# the WRITE_COMMAND tests elsewhere). |
|
# READ_COMMAND to write byte length 1 byte for WishBone |
run_libsim "JTAG READ_COMMAND WB write length 1 byte" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000319cf96400000000100008" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x0f84668b200000000010000000000000" \ |
" access_type: 0x0" \ |
" address: 0x100000" \ |
" length: 0x1" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "0" "100000" "1" \ |
"READ_COMMAND" |
|
# READ_COMMAND to write words length 0x10000 bytes for WishBone |
run_libsim "JTAG READ_COMMAND WB write length 0x10000 bytes" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001c5c63669fffe0000100088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x07c6706f21fffe000010008000000000" \ |
" access_type: 0x2" \ |
" address: 0x100000" \ |
" length: 0x10000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "2" "100000" "10000" \ |
"READ_COMMAND" |
|
# READ_COMMAND to write words length 4 bytes for CPU0 |
run_libsim "JTAG READ_COMMAND CPU0 write length 4 bytes" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001933eb7e580010028000088" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x0e26c4c5a18001002800008000000000" \ |
" access_type: 0x2" \ |
" address: 0x2801" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "2" "2801" "4" \ |
"READ_COMMAND" |
/jtag-read-control.exp
0,0 → 1,294
# jtag-read-control.exp. Tests of the library JTAG READ_CONTROL command |
|
# Copyright (C) 2010 Embecosm Limited |
|
# Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
|
# This file is part of OpenRISC 1000 Architectural Simulator. |
|
# This program is free software; you can redistribute it and/or modify it |
# under the terms of the GNU General Public License as published by the Free |
# Software Foundation; either version 3 of the License, or (at your option) |
# any later version. |
|
# This program is distributed in the hope that it will be useful, but WITHOUT |
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
# more details. |
|
# You should have received a copy of the GNU General Public License along |
# with this program. If not, see <http:#www.gnu.org/licenses/>. */ |
|
# ----------------------------------------------------------------------------- |
# This code is commented throughout for use with Doxygen. |
# ----------------------------------------------------------------------------- |
|
|
# These tests check all the behavior associated with the JTAG READ_CONTROL |
# command. |
|
# NOTE. All these tests return timing information, but we ignore it, since in |
# general it will not be repeatable. |
|
# Tests of the READ_CONTROL for reading from different modules. This should |
# work fine for CPU0, but provoke a warning for Wishbone and CPU1 and a |
# different warning for all other modules. Test no module, Wishbone, CPU0, |
# CPU1 and module 6. |
|
# READ_CONTROL with no module selected. |
run_libsim "JTAG READ_CONTROL no module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_CONTROL." \ |
" shifting in: 0x000000000000000000000005ffa8ec38" \ |
"ERROR: JTAG READ_CONTROL with no module selected." \ |
" shifted out: 0x0c526410200000000000000000000000" \ |
" reset: disabled" \ |
" stall: unstalled" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "READ_CONTROL" |
|
# READ_CONTROL with only WishBone module selected. |
run_libsim "JTAG READ_CONTROL WB module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_CONTROL." \ |
" shifting in: 0x000000000000000000000005ffa8ec38" \ |
"ERROR: JTAG READ_CONTROL of WishBone not supported." \ |
" shifted out: 0x0c526410200000000000000000000000" \ |
" reset: disabled" \ |
" stall: unstalled" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "READ_CONTROL" |
|
# READ_CONTROL with only invalid module selected. |
run_libsim "JTAG READ_CONTROL invalid module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000001993c98e69" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_CONTROL." \ |
" shifting in: 0x000000000000000000000005ffa8ec38" \ |
"ERROR: JTAG READ_CONTROL of CPU1 not supported." \ |
" shifted out: 0x0c526410200000000000000000000000" \ |
" reset: disabled" \ |
" stall: unstalled" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "2" "READ_CONTROL" |
|
# READ_CONTROL with invalid module selected after valid module |
run_libsim "JTAG READ_CONTROL invalid after valid module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000001efe0d976d" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_CONTROL." \ |
" shifting in: 0x000000000000000000000005ffa8ec38" \ |
"ERROR: JTAG READ_CONTROL with no module selected." \ |
" shifted out: 0x0c526410200000000000000000000000" \ |
" reset: disabled" \ |
" stall: unstalled" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "SELECT_MODULE" "6" "READ_CONTROL" |
|
# READ_CONTROL with valid module selected after invalid module |
run_libsim "JTAG READ_CONTROL valid after invalid module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000001efe0d976d" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_CONTROL." \ |
" shifting in: 0x000000000000000000000005ffa8ec38" \ |
" shifted out: 0x0c526410200000000000000000000000" \ |
" reset: disabled" \ |
" stall: unstalled" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "6" "SELECT_MODULE" "1" "READ_CONTROL" |
|
# Verify that reading works correctly from the valid module, CPU0. |
|
# READ_CONTROL for CPU0. |
run_libsim "JTAG READ_CONTROL CPU0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_CONTROL." \ |
" shifting in: 0x000000000000000000000005ffa8ec38" \ |
" shifted out: 0x0c526410200000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "READ_CONTROL" |
|
# The only flag that we can sensible read back is the stall flag. In practice |
# the reset flag is only set during the reset sequence, during which we may |
# not get back any data. All we can test (simply) is that if we set the stall |
# flag it reads back correctly. We leave it to the test of WRITE_CONTROL to |
# determine that the stall actually happens! |
|
# Write the stall bit for CPU and read it back. |
run_libsim "JTAG READ_CONTROL CPU0 read stall bit set" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_CONTROL." \ |
" shifting in: 0x000000000109a677aa00000000000044" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed with breakpoint." \ |
"Processing READ_CONTROL." \ |
" shifting in: 0x000000000000000000000005ffa8ec38" \ |
" shifted out: 0x1ea18635000000000000004000000000" \ |
" reset: disabled" \ |
" stall: stalled" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed with breakpoint." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_CONTROL" "0" "1" "READ_CONTROL" |
|
# Clear the stall bit for CPU and read it back. |
run_libsim "JTAG READ_CONTROL CPU0 read stall bit clear" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_CONTROL." \ |
" shifting in: 0x000000000096dc049200000000000004" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_CONTROL." \ |
" shifting in: 0x000000000000000000000005ffa8ec38" \ |
" shifted out: 0x0c526410200000000000000000000000" \ |
" reset: disabled" \ |
" stall: unstalled" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_CONTROL" "0" "0" "READ_CONTROL" |
/jtag-go-command-read.exp
0,0 → 1,2433
# jtag-go-command-read.exp. Tests of the library JTAG GO_COMMAND for reading |
|
# Copyright (C) 2010 Embecosm Limited |
|
# Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
|
# This file is part of OpenRISC 1000 Architectural Simulator. |
|
# This program is free software; you can redistribute it and/or modify it |
# under the terms of the GNU General Public License as published by the Free |
# Software Foundation; either version 3 of the License, or (at your option) |
# any later version. |
|
# This program is distributed in the hope that it will be useful, but WITHOUT |
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
# more details. |
|
# You should have received a copy of the GNU General Public License along |
# with this program. If not, see <http:#www.gnu.org/licenses/>. */ |
|
# ----------------------------------------------------------------------------- |
# This code is commented throughout for use with Doxygen. |
# ----------------------------------------------------------------------------- |
|
|
# These tests check all the behavior associated with the JTAG GO_COMMAND when |
# reading. |
|
# NOTE. All these tests return timing information, but we ignore it, since in |
# general it will not be repeatable. |
|
# Tests of the GO_COMMAND for reading from different modules. This should work |
# fine for Wishbone and CPU0. Other modules will have been weeded out by the |
# prior WRITE_COMMAND. We specify 4 bytes to read each time. |
|
# We use the loop-init OpenRISC program here, since we must be sure that |
# defined values are placed in the various read targets. As SPR's we use MACLO |
# (0x2801) and MACHI (0x2802), which are initialized to 0xdeadbeef and |
# 0xcafebabe respectively (but remember Or1ksim is by default BIG_ENDIAN when |
# reading the results). As Wishbone we use address 0x100000, which is |
# initialized to 0x10111213. |
|
# When testing GO_COMMAND (read) after invalid module selection, we cannot |
# guarantee a CRC mismatch (or at least I can't do the maths to prove that no |
# register of all zeros can have a valid CRC field for the possible GO_COMMAND |
# register lengths, although it is highly likely), so we just look for the |
# error message. |
|
# GO_COMMAND reading with no module selection (address 0x100000). |
run_libsim "JTAG GO_COMMAND (read) no module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000001039e5cf800000001000c8" \ |
"ERROR: JTAG WRITE_COMMAND with no module selected." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000169330ba20" \ |
"ERROR: JTAG GO_COMMAND with no prior WRITE_COMMAND." \ |
" shifted out: 0x0000000000000000000000000000" \ |
" data: 00000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "WRITE_COMMAND" "6" "100000" "4" "GO_COMMAND_READ" "4" |
|
# GO_COMMAND reading with only invalid module selected. |
run_libsim "JTAG GO_COMMAND (read) invalid module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000001993c98e69" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000000c44c4dd800100280000c8" \ |
"ERROR: JTAG WRITE_COMMAND for CPU1 not supported." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000169330ba20" \ |
"ERROR: JTAG GO_COMMAND with no prior WRITE_COMMAND." \ |
" shifted out: 0x0000000000000000000000000000" \ |
" data: 00000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "2" "WRITE_COMMAND" "6" "2801" "4" \ |
"GO_COMMAND_READ" "4" |
|
# GO_COMMAND reading with invalid module selected after valid module |
run_libsim "JTAG GO_COMMAND (read) invalid after valid module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000001efe0d976d" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000000c44c4dd800100280000c8" \ |
"ERROR: JTAG WRITE_COMMAND with no module selected." \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000169330ba20" \ |
"ERROR: JTAG GO_COMMAND with no prior WRITE_COMMAND." \ |
" shifted out: 0x0000000000000000000000000000" \ |
" data: 00000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "SELECT_MODULE" "6" "WRITE_COMMAND" "6" \ |
"2801" "4" "GO_COMMAND_READ" "4" |
|
# GO_COMMAND reading with valid module selected after invalid module |
run_libsim "JTAG GO_COMMAND (read) valid after invalid module" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000001efe0d976d" \ |
" shifted out: 0x01893c98e68000000000" \ |
" status: 0x2" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000001039e5cf800000001000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000169330ba20" \ |
" shifted out: 0x019de5beae190911010000000000" \ |
" data: 10111213" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "6" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" \ |
"100000" "4" "GO_COMMAND_READ" "4" |
|
# Verify that reading works correctly from both valid modules, WishBone and |
# CPU0. |
|
# GO_COMMAND reading for Wishbone (address 0x100000). |
run_libsim "JTAG SELECT_MODULE GO_COMMAND (read) WB" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken: " \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000001039e5cf800000001000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000169330ba20" \ |
" shifted out: 0x019de5beae190911010000000000" \ |
" data: 10111213" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" "100000" "4" \ |
"GO_COMMAND_READ" "4" |
|
# GO_COMMAND reading for CPU0 (address 0x2081, MACLO). |
run_libsim "JTAG SELECT_MODULE GO_COMMAND (read) CPU0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000000c44c4dd800100280000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000169330ba20" \ |
" shifted out: 0x00b8e2228e0f76afbee000000000" \ |
" data: efbeadde" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "6" "2801" "4" \ |
"GO_COMMAND_READ" "4" |
|
# Tests of GO_COMMAND_READ with different access alignments, boundaries and |
# lengths for WishBone. For this we use the loop-init program, which has |
# values initialized at 0x100000-0x10000f (values 0x10 through 0x1f |
# respectively), 0x110000-0x11000f (values 0x20 through 0x2f respectively) and |
# 0x120000-0x12000f (values 0x30 through 0x3f respectively). |
|
# First check that a single aligned unit can be read for each access type at |
# its allowed alignments. |
|
# GO_COMMAND reading one byte for Wishbone aligned at byte 0. |
run_libsim "JTAG GO_COMMAND (read) WB 1 byte, aligned byte 0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001aee68a5c00000000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000169330ba20" \ |
" shifted out: 0x000464d308010000000000" \ |
" data: 10" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100000" "1" \ |
"GO_COMMAND_READ" "1" |
|
# GO_COMMAND reading one byte for Wishbone aligned at byte 1. |
run_libsim "JTAG GO_COMMAND (read) WB 1 byte, aligned byte 1" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000006c8cbd5c00010000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000169330ba20" \ |
" shifted out: 0x0019d3c36c110000000000" \ |
" data: 11" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100001" "1" \ |
"GO_COMMAND_READ" "1" |
|
# GO_COMMAND reading one byte for Wishbone aligned at byte 2. |
run_libsim "JTAG GO_COMMAND (read) WB 1 byte, aligned byte 2" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000014fd391dc00008000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000169330ba20" \ |
" shifted out: 0x000abf5b3a090000000000" \ |
" data: 12" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100002" "1" \ |
"GO_COMMAND_READ" "1" |
|
# GO_COMMAND reading one byte for Wishbone aligned at byte 3. |
run_libsim "JTAG GO_COMMAND (read) WB 1 byte, aligned byte 3" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000008db9a6dc00018000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000169330ba20" \ |
" shifted out: 0x0017084b5e190000000000" \ |
" data: 13" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100003" "1" \ |
"GO_COMMAND_READ" "1" |
|
# GO_COMMAND reading one half word for Wishbone aligned at byte 0. |
run_libsim "JTAG GO_COMMAND (read) WB 1 half word, aligned byte 0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000165ba59f900000000100148" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000169330ba20" \ |
" shifted out: 0x01bf1eca5211010000000000" \ |
" data: 1011" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "100000" "2" \ |
"GO_COMMAND_READ" "2" |
|
# GO_COMMAND reading one half word for Wishbone aligned at byte 2. |
run_libsim "JTAG GO_COMMAND (read) WB 1 half word, aligned byte 2" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001848f427900008000100148" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000169330ba20" \ |
" shifted out: 0x01791cc86819090000000000" \ |
" data: 1213" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "100002" "2" \ |
"GO_COMMAND_READ" "2" |
|
# GO_COMMAND reading one word for Wishbone aligned at byte 0. |
run_libsim "JTAG GO_COMMAND (read) WB 1 word, aligned byte 0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000001039e5cf800000001000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000169330ba20" \ |
" shifted out: 0x019de5beae190911010000000000" \ |
" data: 10111213" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" "100000" "4" \ |
"GO_COMMAND_READ" "4" |
|
# Verify that longer reads work OK, at different boundaries. For byte access |
# read 9 bytes, for half-word access read 10 bytes and for word access read 12 |
# bytes. |
|
# GO_COMMAND reading 9 bytes for Wishbone aligned at byte 0. |
run_libsim "JTAG GO_COMMAND (read) WB 9 bytes, aligned byte 0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000019588aa9420000000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x0000000000000000000000000000169330ba20" \ |
" shifted out: 0x00efe148fc031d0d1505190911010000000000" \ |
" data: 101112131415161718" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100000" "9" \ |
"GO_COMMAND_READ" "9" |
|
# GO_COMMAND reading 9 bytes for Wishbone aligned at byte 1. |
run_libsim "JTAG GO_COMMAND (read) WB 9 bytes, aligned byte 1" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000057e29d9420010000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x0000000000000000000000000000169330ba20" \ |
" shifted out: 0x00df281a0413031d0d15051909110000000000" \ |
" data: 111213141516171819" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100001" "9" \ |
"GO_COMMAND_READ" "9" |
|
# GO_COMMAND reading 9 bytes for Wishbone aligned at byte 2. |
run_libsim "JTAG GO_COMMAND (read) WB 9 bytes, aligned byte 2" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000174bdb11420008000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x0000000000000000000000000000169330ba20" \ |
" shifted out: 0x0058bcb0c60b13031d0d150519090000000000" \ |
" data: 12131415161718191a" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100002" "9" \ |
"GO_COMMAND_READ" "9" |
|
# GO_COMMAND reading 9 bytes for Wishbone aligned at byte 3. |
run_libsim "JTAG GO_COMMAND (read) WB 9 bytes, aligned byte 3" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000b6d7861420018000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x0000000000000000000000000000169330ba20" \ |
" shifted out: 0x00049f56881b0b13031d0d1505190000000000" \ |
" data: 131415161718191a1b" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100003" "9" \ |
"GO_COMMAND_READ" "9" |
|
# GO_COMMAND reading 5 half words for Wishbone aligned at byte 0. |
run_libsim "JTAG GO_COMMAND (read) WB 5 half words, aligned byte 0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000015ed4793120000000100148" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000000000000000169330ba20" \ |
" shifted out: 0x01eb2b18e013031d0d1505190911010000000000" \ |
" data: 10111213141516171819" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "100000" "a" \ |
"GO_COMMAND_READ" "a" |
|
# GO_COMMAND reading 5 half words for Wishbone aligned at byte 2. |
run_libsim "JTAG GO_COMMAND (read) WB 5 half words, aligned byte 2" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001bfe162b120008000100148" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000000000000000169330ba20" \ |
" shifted out: 0x01234b14981b0b13031d0d150519090000000000" \ |
" data: 12131415161718191a1b" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "100002" "a" \ |
"GO_COMMAND_READ" "a" |
|
# GO_COMMAND reading 3 words for Wishbone aligned at byte 0. |
run_libsim "JTAG GO_COMMAND (read) WB 3 words, aligned byte 0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000002b57c507a00000001000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x0000000000000000000000000000000000169330ba20" \ |
" shifted out: 0x00248290b61b0b13031d0d1505190911010000000000" \ |
" data: 101112131415161718191a1b" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" "100000" "c" \ |
"GO_COMMAND_READ" "c" |
|
# Test of access for CPU0. Much simpler, since access type, alignment and |
# length are more prescribed. Make use of loop-init, which initializes MACLO |
# (0x2801) and MACHI (0x2802) to 0xdeadbeef and 0xcafebabe respectively. These |
# are 32 bit values and presented in target endianess (which is big-endian for |
# the OpenRISC, so the MS byte is as the highest address. |
|
# GO_COMMAND reading 1 word for CPU0 aligned at byte 0. |
run_libsim "JTAG GO_COMMAND (read) CPU0 1 word, aligned byte 0" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000000c44c4dd800100280000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000169330ba20" \ |
" shifted out: 0x00b8e2228e0f76afbee000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "6" "2801" "4" \ |
"GO_COMMAND_READ" "4" |
|
# Check address advances after GO_COMMAND read (1 per word for CPU, 4 per word |
# for WB). Test WB with reading all sizes and lengths 1 through 0x10000. Test |
# CPU0 with reading one word. Uses the initialized looping program for |
# reproducible results. |
|
# - for WB byte access try lengths 1, 2, 3, 4, 5, 8, 9, 0xffff and 0x10000 |
# - for WB half word access try lengths 2, 4, 6, 8, 10, 0xfffe and 0x10000 |
# - for WB full word access try lengths 4, 8, 12, 0xfffc and 0x10000 |
# - for CPU0 try length 4 |
|
# READ_COMMAND to advance address after reading 1 byte for WishBone (access |
# type 4) |
run_libsim "JTAG GO_COMMAND (read) WB read 1 byte address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001aee68a5c00000000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000169330ba20" \ |
" shifted out: 0x000464d308010000000000" \ |
" data: 10" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x1cb5ee99000001000010004000000000" \ |
" access_type: 0x4" \ |
" address: 0x100001" \ |
" length: 0x1" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100000" "1" \ |
"GO_COMMAND_READ" "1" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 2 bytes for WishBone (access |
# type 4) |
run_libsim "JTAG GO_COMMAND (read) WB read 2 bytes address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000075978c1d00000000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000169330ba20" \ |
" shifted out: 0x01bf1eca5211010000000000" \ |
" data: 1011" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x1c4dc0b3c10000800010004000000000" \ |
" access_type: 0x4" \ |
" address: 0x100002" \ |
" length: 0x2" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100000" "2" \ |
"GO_COMMAND_READ" "2" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 3 bytes for WishBone (access |
# type 4) |
run_libsim "JTAG GO_COMMAND (read) WB read 3 bytes address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001435e097c80000000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x0000000000000000169330ba20" \ |
" shifted out: 0x00fd0696b60911010000000000" \ |
" data: 101112" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x1cb96301a08001800010004000000000" \ |
" access_type: 0x4" \ |
" address: 0x100003" \ |
" length: 0x3" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100000" "3" \ |
"GO_COMMAND_READ" "3" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 4 bytes for WishBone (access |
# type 4) |
run_libsim "JTAG GO_COMMAND (read) WB read 4 bytes address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000982f0f3d80000000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000169330ba20" \ |
" shifted out: 0x019de5beae190911010000000000" \ |
" data: 10111213" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x1c31d7a6a18000400010004000000000" \ |
" access_type: 0x4" \ |
" address: 0x100004" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100000" "4" \ |
"GO_COMMAND_READ" "4" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 5 bytes for WishBone (access |
# type 4) |
run_libsim "JTAG GO_COMMAND (read) WB read 5 bytes address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001d83acbcc40000000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000000000169330ba20" \ |
" shifted out: 0x0040999fde05190911010000000000" \ |
" data: 1011121314" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x0104b831404001400010004000000000" \ |
" access_type: 0x4" \ |
" address: 0x100005" \ |
" length: 0x5" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100000" "5" \ |
"GO_COMMAND_READ" "5" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 8 bytes for WishBone (access |
# type 4) |
run_libsim "JTAG GO_COMMAND (read) WB read 8 bytes address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000eef34eadc0000000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000000000000000169330ba20" \ |
" shifted out: 0x003458d6401d0d1505190911010000000000" \ |
" data: 1011121314151617" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x01b8cc4801c000200010004000000000" \ |
" access_type: 0x4" \ |
" address: 0x100008" \ |
" length: 0x8" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100000" "8" \ |
"GO_COMMAND_READ" "8" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 9 bytes for WishBone (access |
# type 4) |
run_libsim "JTAG GO_COMMAND (read) WB read 9 bytes address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000019588aa9420000000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x0000000000000000000000000000169330ba20" \ |
" shifted out: 0x00efe148fc031d0d1505190911010000000000" \ |
" data: 101112131415161718" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x126d45cd202001200010004000000000" \ |
" access_type: 0x4" \ |
" address: 0x100009" \ |
" length: 0x9" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100000" "9" \ |
"GO_COMMAND_READ" "9" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 0xffff bytes for WishBone |
# (access type 4). Only partially match the data read back. |
run_libsim "JTAG GO_COMMAND (read) WB read 0xffff bytes address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000109dba9e2fffe0000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000000000000000000000000000000000000" \ |
" shifted out: 0x00a0a530360000000000000000000000000000000000000" \ |
" data: 101112131415161718191a1b1c1d1e1f00000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x19caa5fc00fffffffe10004000000000" \ |
" access_type: 0x4" \ |
" address: 0x10ffff" \ |
" length: 0xffff" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100000" "ffff" \ |
"GO_COMMAND_READ" "ffff" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 0x10000 bytes for WishBone |
# (access type 4). Only partially match the data read back. |
run_libsim "JTAG GO_COMMAND (read) WB read 0x10000 bytes address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000d2aaafa3fffe0000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000000000000000000000000000000000000" \ |
" shifted out: 0x01146b36e80000000000000000000000000000000000000" \ |
" data: 101112131415161718191a1b1c1d1e1f00000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x0db27fb041fffe000110004000000000" \ |
" access_type: 0x4" \ |
" address: 0x110000" \ |
" length: 0x10000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100000" "10000" \ |
"GO_COMMAND_READ" "10000" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 1 half word (2 bytes) for |
# WishBone (access type 5) |
run_libsim "JTAG GO_COMMAND (read) WB read 1 half word address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000165ba59f900000000100148" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000169330ba20" \ |
" shifted out: 0x01bf1eca5211010000000000" \ |
" data: 1011" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x1a30297f210000800010014000000000" \ |
" access_type: 0x5" \ |
" address: 0x100002" \ |
" length: 0x2" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "100000" "2" \ |
"GO_COMMAND_READ" "2" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 2 half words (4 bytes) for |
# WishBone (access type 5) |
run_libsim "JTAG GO_COMMAND (read) WB read 2 half words address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000018802dad980000000100148" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000169330ba20" \ |
" shifted out: 0x019de5beae190911010000000000" \ |
" data: 10111213" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x1a4c3e6a418000400010014000000000" \ |
" access_type: 0x5" \ |
" address: 0x100004" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "100000" "4" \ |
"GO_COMMAND_READ" "4" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 3 half words (6 bytes) for |
# WishBone (access type 5) |
run_libsim "JTAG GO_COMMAND (read) WB read 3 half words address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000011366186940000000100148" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x0000000000000000000000169330ba20" \ |
" shifted out: 0x01d78784e61505190911010000000000" \ |
" data: 101112131415" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x07817fd7614000c00010014000000000" \ |
" access_type: 0x5" \ |
" address: 0x100006" \ |
" length: 0x6" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "100000" "6" \ |
"GO_COMMAND_READ" "6" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 4 half words (8 bytes) for |
# WishBone (access type 5) |
run_libsim "JTAG GO_COMMAND (read) WB read 4 half words address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001fede9b49c0000000100148" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000000000000000169330ba20" \ |
" shifted out: 0x003458d6401d0d1505190911010000000000" \ |
" data: 1011121314151617" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x07c52584e1c000200010014000000000" \ |
" access_type: 0x5" \ |
" address: 0x100008" \ |
" length: 0x8" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "100000" "8" \ |
"GO_COMMAND_READ" "8" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 5 half words (10 bytes) for |
# WishBone (access type 5) |
run_libsim "JTAG GO_COMMAND (read) WB read 5 half words address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000015ed4793120000000100148" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000000000000000169330ba20" \ |
" shifted out: 0x01eb2b18e013031d0d1505190911010000000000" \ |
" data: 10111213141516171819" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x14e8822b012000a00010014000000000" \ |
" access_type: 0x5" \ |
" address: 0x10000a" \ |
" length: 0xa" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "100000" "a" \ |
"GO_COMMAND_READ" "a" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 0x7fff half words (0xfffe |
# bytes) for WishBone (access type 5) |
run_libsim "JTAG GO_COMMAND (read) WB read 0x7fff half words address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000012f3ff9677ffe0000100148" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000000000000000000000000000000000000" \ |
" shifted out: 0x00afd24ee00000000000000000000000000000000000000" \ |
" data: 101112131415161718191a1b1c1d1e1f00000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x1f43ef82817ffefffe10014000000000" \ |
" access_type: 0x5" \ |
" address: 0x10fffe" \ |
" length: 0xfffe" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "100000" "fffe" \ |
"GO_COMMAND_READ" "fffe" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 0x8000 half words (0x10000 |
# bytes) for WishBone (access type 5) |
run_libsim "JTAG GO_COMMAND (read) WB read 0x8000 half words address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001c2877a47fffe0000100148" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000000000000000000000000000000000000" \ |
" shifted out: 0x01146b36e80000000000000000000000000000000000000" \ |
" data: 101112131415161718191a1b1c1d1e1f00000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x0bcf967ca1fffe000110014000000000" \ |
" access_type: 0x5" \ |
" address: 0x110000" \ |
" length: 0x10000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "100000" "10000" \ |
"GO_COMMAND_READ" "10000" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 1 word (4 bytes) for WishBone |
# (access type 6) |
run_libsim "JTAG GO_COMMAND (read) WB read 1 word address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000001039e5cf800000001000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000169330ba20" \ |
" shifted out: 0x019de5beae190911010000000000" \ |
" data: 10111213" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x02b83324c1800040001000c000000000" \ |
" access_type: 0x6" \ |
" address: 0x100004" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" "100000" "4" \ |
"GO_COMMAND_READ" "4" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 2 words (8 bytes) for WishBone |
# (access type 6) |
run_libsim "JTAG GO_COMMAND (read) WB read 2 words address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000066e5a45fc00000001000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000000000000000169330ba20" \ |
" shifted out: 0x003458d6401d0d1505190911010000000000" \ |
" data: 1011121314151617" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x1f3128ca61c00020001000c000000000" \ |
" access_type: 0x6" \ |
" address: 0x100008" \ |
" length: 0x8" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" "100000" "8" \ |
"GO_COMMAND_READ" "8" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 3 words (12 bytes) for WishBone |
# (access type 6) |
run_libsim "JTAG GO_COMMAND (read) WB read 3 words address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000002b57c507a00000001000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x0000000000000000000000000000000000169330ba20" \ |
" shifted out: 0x00248290b61b0b13031d0d1505190911010000000000" \ |
" data: 101112131415161718191a1b" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x0c609870e1a00060001000c000000000" \ |
" access_type: 0x6" \ |
" address: 0x10000c" \ |
" length: 0xc" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" "100000" "c" \ |
"GO_COMMAND_READ" "c" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 0x3fff words (0xfffc bytes) |
# for WishBone (access type 6) |
run_libsim "JTAG GO_COMMAND (read) WB read 0x3fff words address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000002c6004c1bffe00001000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000000000000000000000000000000000000" \ |
" shifted out: 0x00588773a80000000000000000000000000000000000000" \ |
" data: 101112131415161718191a1b1c1d1e1f00000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x1a7aa37121bffe7ffe1000c000000000" \ |
" access_type: 0x6" \ |
" address: 0x10fffc" \ |
" length: 0xfffc" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" "100000" "fffc" \ |
"GO_COMMAND_READ" "fffc" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 0x4000 words (0x10000 bytes) |
# for WishBone (access type 6) |
run_libsim "JTAG GO_COMMAND (read) WB read 0x400 words address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000005abc4551fffe00001000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000000000000000000000000000000000000" \ |
" shifted out: 0x01146b36e80000000000000000000000000000000000000" \ |
" data: 101112131415161718191a1b1c1d1e1f00000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x133b9b3221fffe00011000c000000000" \ |
" access_type: 0x6" \ |
" address: 0x110000" \ |
" length: 0x10000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" "100000" "10000" \ |
"GO_COMMAND_READ" "10000" "READ_COMMAND" |
|
# READ_COMMAND to advance address after reading 1 word for CPU0 |
# (access type 2). The address should advance by 1 (word, since SPRs are word |
# addressed). |
run_libsim "JTAG GO_COMMAND (read) CPU0 read 1 word address advance" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000000c44c4dd800100280000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000169330ba20" \ |
" shifted out: 0x00b8e2228e0f76afbee000000000" \ |
" data: efbeadde" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing READ_COMMAND." \ |
" shifting in: 0x00000000000000000000000b2420de30" \ |
" shifted out: 0x1df679cc01800080280000c000000000" \ |
" access_type: 0x6" \ |
" address: 0x2802" \ |
" length: 0x4" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "6" "2801" "4" \ |
"GO_COMMAND_READ" "4" "READ_COMMAND" |
|
# Tests of overrun and underrun. For Wishbone check both on different access |
# sizes. |
|
# GO_COMMAND_READ for WishBone underrun for byte access |
run_libsim "JTAG GO_COMMAND (read) WB byte access underrun" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000eef34eadc0000000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000000000169330ba20" \ |
" shifted out: 0x000d619cbc2d1505190911010000000000" \ |
" data: 10111213141516" \ |
" status: 0x8" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100000" "8" \ |
"GO_COMMAND_READ" "7" |
|
# GO_COMMAND_READ for WishBone overrun for byte access |
run_libsim "JTAG GO_COMMAND (read) WB byte access overrun" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000eef34eadc0000000100048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x0000000000000000000000000000169330ba20" \ |
" shifted out: 0x004d86398e201d0d1505190911010000000000" \ |
" data: 101112131415161700" \ |
" status: 0x8" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "100000" "8" \ |
"GO_COMMAND_READ" "9" |
|
# GO_COMMAND_READ for WishBone underrun for half word access |
run_libsim "JTAG GO_COMMAND (read) WB half word access underrun" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001fede9b49c0000000100148" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000000000169330ba20" \ |
" shifted out: 0x000d619cbc2d1505190911010000000000" \ |
" data: 10111213141516" \ |
" status: 0x8" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "100000" "8" \ |
"GO_COMMAND_READ" "7" |
|
# GO_COMMAND_READ for WishBone overrun for half word access |
run_libsim "JTAG GO_COMMAND (read) WB half word access overrun" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001fede9b49c0000000100148" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x0000000000000000000000000000169330ba20" \ |
" shifted out: 0x004d86398e201d0d1505190911010000000000" \ |
" data: 101112131415161700" \ |
" status: 0x8" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "100000" "8" \ |
"GO_COMMAND_READ" "9" |
|
# GO_COMMAND_READ for WishBone underrun for word access |
run_libsim "JTAG GO_COMMAND (read) WB word access underrun" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000066e5a45fc00000001000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000000000169330ba20" \ |
" shifted out: 0x000d619cbc2d1505190911010000000000" \ |
" data: 10111213141516" \ |
" status: 0x8" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" "100000" "8" \ |
"GO_COMMAND_READ" "7" |
|
# GO_COMMAND_READ for WishBone overrun for word access |
run_libsim "JTAG GO_COMMAND (read) WB word access overrun" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000066e5a45fc00000001000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x0000000000000000000000000000169330ba20" \ |
" shifted out: 0x004d86398e201d0d1505190911010000000000" \ |
" data: 101112131415161700" \ |
" status: 0x8" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" "100000" "8" \ |
"GO_COMMAND_READ" "9" |
|
# CPU0 underrun and overrun tests should remember that this is a 32-bit access |
# with a big-endian organization. |
|
# GO_COMMAND_READ for CPU0 underrun for word access |
run_libsim "JTAG GO_COMMAND (read) CPU0 word access underrun" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000000c44c4dd800100280000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x0000000000000000169330ba20" \ |
" shifted out: 0x00295bc0a836afbee000000000" \ |
" data: efbead" \ |
" status: 0x8" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "6" "2801" "4" \ |
"GO_COMMAND_READ" "3" |
|
# GO_COMMAND_READ for CPU0 overrun for word access |
run_libsim "JTAG GO_COMMAND (read) CPU0 word access overrun" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x00000000000aff51d871" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000000c44c4dd800100280000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000000000169330ba20" \ |
" shifted out: 0x01eaa76a8c200f76afbee000000000" \ |
" data: efbeadde00" \ |
" status: 0x8" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "1" "WRITE_COMMAND" "6" "2801" "4" \ |
"GO_COMMAND_READ" "5" |
|
# Test access to invalid areas. We can only do this for Wishbone, since all |
# SPRs are validly accessible (non-readable ones just return undefined |
# results). For the default CFG we have the following memory areas. |
# 0x00000000 - 0x001fffff RAM (read/write) |
# 0xf0000000 - 0xf01fffff Flash (read only) |
# 0xffe00000 - 0xffffffff RAM (read/write) |
|
# For convenience the top 8 bytes of the each block of RAM (0x001ffff8 - |
# 0x001fffff) and (0xfffffff8 - 0xffffffff) and the bottom 8 bytes of the |
# second block of RAM (0xffe00000 - 0xffe00007) are initialized to |
# 0xdeadbeefcafebabe. |
|
# Test each access type with one unit and test blocks spanning start and end |
# of readable blocks. |
|
# GO_COMMAND_READ for 1 byte read from invalid memory. |
run_libsim "JTAG GO_COMMAND (read) WB 1 byte invalid read" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000002507505e00000000080048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000169330ba20" \ |
" shifted out: 0x0005bfa20e400000000000" \ |
" data: 00" \ |
" status: 0x4" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "200000" "1" \ |
"GO_COMMAND_READ" "1" |
|
# GO_COMMAND_READ for 2 byte read ending in invalid memory. |
run_libsim "JTAG GO_COMMAND (read) WB 2 byte ending invalid read" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000024c5489f0001fffff00048" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000169330ba20" \ |
" shifted out: 0x01e489dbde400fa000000000" \ |
" data: be00" \ |
" status: 0x4" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "1fffff" "2" \ |
"GO_COMMAND_READ" "2" |
|
# GO_COMMAND_READ for 2 byte read starting in invalid memory. |
run_libsim "JTAG GO_COMMAND (read) WB 2 byte starting invalid read" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000001620ceaa70001fffff7fe48" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000169330ba20" \ |
" shifted out: 0x00945aea064f600000000000" \ |
" data: 00de" \ |
" status: 0x4" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "4" "ffdfffff" "2" \ |
"GO_COMMAND_READ" "2" |
|
# GO_COMMAND_READ for 1 half word read from invalid memory. |
run_libsim "JTAG GO_COMMAND (read) WB 1 half word invalid read" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x0000000000ee5b83fb00000000080148" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000169330ba20" \ |
" shifted out: 0x0061189c3040000000000000" \ |
" data: 0000" \ |
" status: 0x4" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "200000" "2" \ |
"GO_COMMAND_READ" "2" |
|
# GO_COMMAND_READ for 2 half word read ending in invalid memory. |
run_libsim "JTAG GO_COMMAND (read) WB 2 half word ending invalid read" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000001b3a295b8000fffff00148" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000169330ba20" \ |
" shifted out: 0x011ad9043a40000faba000000000" \ |
" data: babe0000" \ |
" status: 0x4" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "1ffffe" "4" \ |
"GO_COMMAND_READ" "4" |
|
# GO_COMMAND_READ for 2 half word read starting in invalid memory. |
run_libsim "JTAG GO_COMMAND (read) WB 2 half word starting invalid read" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000015df38b638000fffff7ff48" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000169330ba20" \ |
" shifted out: 0x016e549cc256af60000000000000" \ |
" data: 0000dead" \ |
" status: 0x4" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "5" "ffdffffe" "4" \ |
"GO_COMMAND_READ" "4" |
|
# GO_COMMAND_READ for 1 word read from invalid memory. |
run_libsim "JTAG GO_COMMAND (read) WB 1 word invalid read" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000019bd83fcd800000000800c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x000000000000000000169330ba20" \ |
" shifted out: 0x0020b944d4400000000000000000" \ |
" data: 00000000" \ |
" status: 0x4" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" "200000" "4" \ |
"GO_COMMAND_READ" "4" |
|
# GO_COMMAND_READ for 2 word read ending in invalid memory. |
run_libsim "JTAG GO_COMMAND (read) WB 2 word ending invalid read" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x000000000114e84c5dc0007ffff000c8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000000000000000169330ba20" \ |
" shifted out: 0x00f0f84a44400000000fabafea6000000000" \ |
" data: cafebabe00000000" \ |
" status: 0x4" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" "1ffffc" "8" \ |
"GO_COMMAND_READ" "8" |
|
# GO_COMMAND_READ for 2 word read starting in invalid memory. |
run_libsim "JTAG GO_COMMAND (read) WB 2 word starting invalid read" \ |
[list "Initalization succeeded." \ |
"Execution step completed OK." \ |
"Resetting JTAG." \ |
"Execution step completed OK." \ |
"Shifting instruction." \ |
" shifting in: 0x01" \ |
" shifted out: 0x01" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Selecting module." \ |
" shifting in: 0x0000000000174841bc61" \ |
" shifted out: 0x0164841bc60000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing WRITE_COMMAND." \ |
" shifting in: 0x00000000005221ee65c0007ffff7fec8" \ |
" shifted out: 0x164841bc600000000000000000000000" \ |
" status: 0x0" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Processing GO_COMMAND_READ." \ |
" shifting in: 0x00000000000000000000000000169330ba20" \ |
" shifted out: 0x0090e309ce5eefb6af600000000000000000" \ |
" data: 00000000deadbeef" \ |
" status: 0x4" \ |
" time taken:" \ |
"Execution step completed OK." \ |
"Test completed successfully."] \ |
"lib-jtag/lib-jtag-full" "" "loop/loop-init" "RESET" "INSTRUCTION" \ |
"8" "SELECT_MODULE" "0" "WRITE_COMMAND" "6" "ffdffffc" "8" \ |
"GO_COMMAND_READ" "8" |
|
/Makefile.am
0,0 → 1,46
# Makefile.am for libor1ksim DejaGNU tests |
|
# Copyright (C) Marko Mlinar, 2001 |
# Copyright (C) Embecosm Limited, 2010 |
|
# Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
|
# To add new test, edit between marked areas only |
|
# This file is part of OpenRISC 1000 Architectural Simulator. |
|
# This program is free software; you can redistribute it and/or modify it |
# under the terms of the GNU General Public License as published by the Free |
# Software Foundation; either version 3 of the License, or (at your option) |
# any later version. |
|
# This program is distributed in the hope that it will be useful, but WITHOUT |
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
# more details. |
|
# You should have received a copy of the GNU General Public License along |
# with this program. If not, see <http:#www.gnu.org/licenses/>. */ |
|
# ----------------------------------------------------------------------------- |
# This code is commented throughout for use with Doxygen. |
# ----------------------------------------------------------------------------- |
|
|
# Just distribute this stuff |
EXTRA_DIST = default.cfg \ |
int-edge.cfg \ |
int-edge.exp \ |
int-level.cfg \ |
int-level.exp \ |
jtag-basic.exp \ |
jtag-go-command-read.exp \ |
jtag-go-command-write.exp \ |
jtag-read-command.exp \ |
jtag-read-control.exp \ |
jtag-select-module.exp \ |
jtag-write-control.exp \ |
jtag-write-command.exp \ |
lib-iftest.exp \ |
upcalls.exp \ |
upcalls.cfg |
Makefile.am
Property changes :
Added: svn:eol-style
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+native
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Index: upcalls.cfg
===================================================================
--- upcalls.cfg (nonexistent)
+++ upcalls.cfg (revision 135)
@@ -0,0 +1,155 @@
+/* upcalls.cfg -- Or1ksim configuration script file for upcall testing
+
+ Copyright (C) 2001, Marko Mlinar
+ Copyright (C) 2010 Embecosm Limited
+
+ Contributor Marko Mlinar
+ Contributor Jeremy Bennett
+
+ This file is part of OpenRISC 1000 Architectural Simulator.
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 3 of the License, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program. If not, see . */
+
+section memory
+ /*random_seed = 12345
+ type = random*/
+ pattern = 0x00
+ type = unknown /* Fastest */
+
+ name = "FLASH"
+ ce = 0
+ mc = 0
+ baseaddr = 0xf0000000
+ size = 0x00200000
+ delayr = 10
+ delayw = -1
+end
+
+section memory
+ /*random_seed = 12345
+ type = random*/
+ pattern = 0x00
+ type = unknown /* Fastest */
+
+ name = "RAM"
+ ce = 1
+ mc = 0
+ baseaddr = 0x00000000
+ size = 0x00200000
+ delayr = 2
+ delayw = 4
+end
+
+section immu
+ enabled = 1
+ nsets = 64
+ nways = 1
+ ustates = 2
+ pagesize = 8192
+end
+
+section dmmu
+ enabled = 1
+ nsets = 64
+ nways = 1
+ ustates = 2
+ pagesize = 8192
+end
+
+section ic
+ enabled = 1
+ nsets = 256
+ nways = 1
+ ustates = 2
+ blocksize = 16
+end
+
+section dc
+ enabled = 1
+ nsets = 256
+ nways = 1
+ ustates = 2
+ blocksize = 16
+end
+
+section cpu
+ ver = 0x12
+ rev = 0x0001
+ /* upr = */
+ superscalar = 0
+ hazards = 0
+ dependstats = 0
+end
+
+section bpb
+ enabled = 0
+ btic = 0
+end
+
+section debug
+/* enabled = 1
+ rsp_enabled = 1
+ rsp_port = 51000*/
+end
+
+section sim
+ debug = 0
+ profile = 0
+ prof_fn = "sim.profile"
+
+ exe_log = 0
+ exe_log_type = software
+ exe_log_fn = "executed.log"
+end
+
+section mc
+ enabled = 1
+ baseaddr = 0x93000000
+ POC = 0x00000008 /* Power on configuration register */
+ index = 0
+end
+
+section dma
+ baseaddr = 0xB8000000
+ irq = 4
+end
+
+section ethernet
+ enabled = 0
+ baseaddr = 0x92000000
+ irq = 4
+ rtx_type = 0
+end
+
+section VAPI
+ enabled = 0
+ server_port = 9998
+end
+
+section fb
+ enabled = 1
+ baseaddr = 0x97000000
+ refresh_rate = 10000
+ filename = "primary"
+end
+
+section kbd
+ enabled = 0
+end
+
+section generic
+ enabled = 1
+ baseaddr = 0x98000000
+ size = 32
+end
Index: int-edge.exp
===================================================================
--- int-edge.exp (nonexistent)
+++ int-edge.exp (revision 135)
@@ -0,0 +1,130 @@
+# int-edge.exp. Test of the library edge triggered interrupt functions
+
+# Copyright (C) 2010 Embecosm Limited
+
+# Contributor Jeremy Bennett
+
+# This file is part of OpenRISC 1000 Architectural Simulator.
+
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 3 of the License, or (at your option)
+# any later version.
+
+# This program is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+
+# You should have received a copy of the GNU General Public License along
+# with this program. If not, see . */
+
+# -----------------------------------------------------------------------------
+# This code is commented throughout for use with Doxygen.
+# -----------------------------------------------------------------------------
+
+
+# Run the library edge triggered interrupts in a number of ways.
+
+# Sequence of independent interrupts
+run_libsim "int-edge simple 1" \
+ [list "Initalization succeeded." \
+ "Starting interrupt handler" \
+ "Enabling interrupts." \
+ "Triggering interrupt 2" \
+ "PICSR 0x00000004 -> 0x00000000" \
+ "Triggering interrupt 3" \
+ "PICSR 0x00000008 -> 0x00000000" \
+ "Test completed successfully."] \
+ "lib-inttest/lib-inttest-edge" "int-edge.cfg" \
+ "int-logger/int-logger-edge" "1" "2" "3"
+
+run_libsim "int-edge simple 2" \
+ [list "Initalization succeeded." \
+ "Starting interrupt handler" \
+ "Enabling interrupts." \
+ "Triggering interrupt 7" \
+ "PICSR 0x00000080 -> 0x00000000" \
+ "Triggering interrupt 17" \
+ "PICSR 0x00020000 -> 0x00000000" \
+ "Triggering interrupt 31" \
+ "PICSR 0x80000000 -> 0x00000000" \
+ "Test completed successfully."] \
+ "lib-inttest/lib-inttest-edge" "int-edge.cfg" \
+ "int-logger/int-logger-edge" "1" "7" "17" "31"
+
+# Duplicated interrupts
+run_libsim "int-edge duplicated 1" \
+ [list "Initalization succeeded." \
+ "Starting interrupt handler" \
+ "Enabling interrupts." \
+ "Triggering interrupt 2" \
+ "PICSR 0x00000004 -> 0x00000000" \
+ "Triggering interrupt 4" \
+ "PICSR 0x00000010 -> 0x00000000" \
+ "Triggering interrupt 2" \
+ "PICSR 0x00000004 -> 0x00000000" \
+ "Test completed successfully."] \
+ "lib-inttest/lib-inttest-edge" "int-edge.cfg" \
+ "int-logger/int-logger-edge" "1" "2" "4" "2"
+
+run_libsim "int-edge duplicated 2" \
+ [list "Initalization succeeded." \
+ "Starting interrupt handler" \
+ "Enabling interrupts." \
+ "Triggering interrupt 2" \
+ "PICSR 0x00000004 -> 0x00000000" \
+ "Triggering interrupt 2" \
+ "PICSR 0x00000004 -> 0x00000000" \
+ "Triggering interrupt 2" \
+ "PICSR 0x00000004 -> 0x00000000" \
+ "Triggering interrupt 2" \
+ "PICSR 0x00000004 -> 0x00000000" \
+ "Triggering interrupt 2" \
+ "PICSR 0x00000004 -> 0x00000000" \
+ "Triggering interrupt 2" \
+ "PICSR 0x00000004 -> 0x00000000" \
+ "Triggering interrupt 2" \
+ "PICSR 0x00000004 -> 0x00000000" \
+ "Triggering interrupt 2" \
+ "PICSR 0x00000004 -> 0x00000000" \
+ "Test completed successfully."] \
+ "lib-inttest/lib-inttest-edge" "int-edge.cfg" \
+ "int-logger/int-logger-edge" "1" "2" "2" "2" "2" "2" "2" "2" "2"
+
+# All from upcalls
+run_libsim "int-edge all upcall" \
+ [list "Initalization succeeded." \
+ "Starting interrupt handler" \
+ "Enabling interrupts." \
+ "Triggering interrupt 7" \
+ "PICSR 0x00000080 -> 0x00000000" \
+ "Triggering interrupt 17" \
+ "PICSR 0x00020000 -> 0x00000000" \
+ "Triggering interrupt 31" \
+ "PICSR 0x80000000 -> 0x00000000" \
+ "Test completed successfully."] \
+ "lib-inttest/lib-inttest-edge" "int-edge.cfg" \
+ "int-logger/int-logger-edge" "20" "7" "17" "31"
+
+# Check the boundaries of acceptable interrupt numbers
+run_libsim "int-edge check boundaries" \
+ [list "Initalization succeeded." \
+ "Starting interrupt handler" \
+ "Enabling interrupts." \
+ "Triggering interrupt 0" \
+ "PICSR 0x00000001 -> 0x00000000" \
+ "Triggering interrupt 1" \
+ "PICSR 0x00000002 -> 0x00000000" \
+ "Triggering interrupt 31" \
+ "PICSR 0x80000000 -> 0x00000000" \
+ "Warning: Invalid interrupt # 32 - ignored" \
+ "Triggering interrupt 31" \
+ "PICSR 0x80000000 -> 0x00000000" \
+ "Triggering interrupt 1" \
+ "PICSR 0x00000002 -> 0x00000000" \
+ "Triggering interrupt 0" \
+ "PICSR 0x00000001 -> 0x00000000" \
+ "Test completed successfully."] \
+ "lib-inttest/lib-inttest-edge" "int-edge.cfg" \
+ "int-logger/int-logger-edge" "10" "0" "1" "31" "32" "31" "1" "0"
Index: int-edge.cfg
===================================================================
--- int-edge.cfg (nonexistent)
+++ int-edge.cfg (revision 135)
@@ -0,0 +1,160 @@
+/* int-edge.cfg -- Or1ksim configuration script file for edge triggered PIC
+
+ Copyright (C) 2001, Marko Mlinar
+ Copyright (C) 2010 Embecosm Limited
+
+ Contributor Marko Mlinar
+ Contributor Jeremy Bennett
+
+ This file is part of OpenRISC 1000 Architectural Simulator.
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 3 of the License, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program. If not, see . */
+
+section memory
+ /*random_seed = 12345
+ type = random*/
+ pattern = 0x00
+ type = unknown /* Fastest */
+
+ name = "FLASH"
+ ce = 0
+ mc = 0
+ baseaddr = 0xf0000000
+ size = 0x00200000
+ delayr = 10
+ delayw = -1
+end
+
+section memory
+ /*random_seed = 12345
+ type = random*/
+ pattern = 0x00
+ type = unknown /* Fastest */
+
+ name = "RAM"
+ ce = 1
+ mc = 0
+ baseaddr = 0x00000000
+ size = 0x00200000
+ delayr = 2
+ delayw = 4
+end
+
+section immu
+ enabled = 1
+ nsets = 64
+ nways = 1
+ ustates = 2
+ pagesize = 8192
+end
+
+section dmmu
+ enabled = 1
+ nsets = 64
+ nways = 1
+ ustates = 2
+ pagesize = 8192
+end
+
+section ic
+ enabled = 1
+ nsets = 256
+ nways = 1
+ ustates = 2
+ blocksize = 16
+end
+
+section dc
+ enabled = 1
+ nsets = 256
+ nways = 1
+ ustates = 2
+ blocksize = 16
+end
+
+section cpu
+ ver = 0x12
+ rev = 0x0001
+ /* upr = */
+ superscalar = 0
+ hazards = 0
+ dependstats = 0
+end
+
+section bpb
+ enabled = 0
+ btic = 0
+end
+
+section debug
+/* enabled = 1
+ rsp_enabled = 1
+ rsp_port = 51000*/
+end
+
+section sim
+ debug = 0
+ profile = 0
+ prof_fn = "sim.profile"
+
+ exe_log = 0
+ exe_log_type = software
+ exe_log_fn = "executed.log"
+end
+
+section mc
+ enabled = 1
+ baseaddr = 0x93000000
+ POC = 0x00000008 /* Power on configuration register */
+ index = 0
+end
+
+section dma
+ baseaddr = 0xB8000000
+ irq = 4
+end
+
+section ethernet
+ enabled = 0
+ baseaddr = 0x92000000
+ irq = 4
+ rtx_type = 0
+end
+
+section VAPI
+ enabled = 0
+ server_port = 9998
+end
+
+section fb
+ enabled = 1
+ baseaddr = 0x97000000
+ refresh_rate = 10000
+ filename = "primary"
+end
+
+section kbd
+ enabled = 0
+end
+
+section pic
+ enabled = 1
+ edge_trigger = 1
+end
+
+section generic
+ enabled = 1
+ baseaddr = 0x98000000
+ size = 8
+end
Index: int-level.exp
===================================================================
--- int-level.exp (nonexistent)
+++ int-level.exp (revision 135)
@@ -0,0 +1,113 @@
+# int-level.exp. Test of the library level triggered interrupt functions
+
+# Copyright (C) 2010 Embecosm Limited
+
+# Contributor Jeremy Bennett
+
+# This file is part of OpenRISC 1000 Architectural Simulator.
+
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 3 of the License, or (at your option)
+# any later version.
+
+# This program is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+
+# You should have received a copy of the GNU General Public License along
+# with this program. If not, see . */
+
+# -----------------------------------------------------------------------------
+# This code is commented throughout for use with Doxygen.
+# -----------------------------------------------------------------------------
+
+
+# Run the library level triggered interrupts in a number of ways.
+
+# Sequence of independent interrupts
+run_libsim "int-level simple 1" \
+ [list "Initalization succeeded." \
+ "Starting interrupt handler" \
+ "Enabling interrupts." \
+ "Raising interrupt 1" \
+ "PICSR = 0x00000002" \
+ "Clearing interrupt 1" \
+ "Test completed successfully."] \
+ "lib-inttest/lib-inttest-level" "int-level.cfg" \
+ "int-logger/int-logger-level" "+1" "-1"
+
+run_libsim "int-level simple 2" \
+ [list "Initalization succeeded." \
+ "Starting interrupt handler" \
+ "Enabling interrupts." \
+ "Raising interrupt 7" \
+ "PICSR = 0x00000080" \
+ "Clearing interrupt 7" \
+ "Raising interrupt 17" \
+ "PICSR = 0x00020000" \
+ "Clearing interrupt 17" \
+ "Raising interrupt 31" \
+ "PICSR = 0x80000000" \
+ "Clearing interrupt 31" \
+ "Test completed successfully."] \
+ "lib-inttest/lib-inttest-level" "int-level.cfg" \
+ "int-logger/int-logger-level" "+7" "-7" "+17" "-17" "+31" "-31"
+
+# Uncleared interrupt (this only matches the first two reports or PICSR, there
+# are many)
+run_libsim "int-level uncleared interrupt" \
+ [list "Initalization succeeded." \
+ "Starting interrupt handler" \
+ "Enabling interrupts." \
+ "Raising interrupt 1" \
+ "PICSR = 0x00000002" \
+ "PICSR = 0x00000002" \
+ "Test completed successfully."] \
+ "lib-inttest/lib-inttest-level" "int-level.cfg" \
+ "int-logger/int-logger-level" "+1"
+
+# Clearing the wrong interrupt
+run_libsim "int-level wrong clear" \
+ [list "Initalization succeeded." \
+ "Starting interrupt handler" \
+ "Enabling interrupts." \
+ "Raising interrupt 31" \
+ "PICSR = 0x80000000" \
+ "Clearing interrupt 1" \
+ "PICSR = 0x80000000" \
+ "Clearing interrupt 31" \
+ "Test completed successfully."] \
+ "lib-inttest/lib-inttest-level" "int-level.cfg" \
+ "int-logger/int-logger-level" "+31" "-1" "-31"
+
+# Check the boundaries of acceptable interrupt numbers
+run_libsim "int-level check boundaries" \
+ [list "Warning: Invalid interrupt # 32 to raise." \
+ "Warning: Invalid interrupt # 32 to clear." \
+ "Initalization succeeded." \
+ "Starting interrupt handler" \
+ "Enabling interrupts." \
+ "Raising interrupt 0" \
+ "PICSR = 0x00000001" \
+ "Clearing interrupt 0" \
+ "Raising interrupt 1" \
+ "PICSR = 0x00000002" \
+ "Clearing interrupt 1" \
+ "Raising interrupt 31" \
+ "PICSR = 0x80000000" \
+ "Clearing interrupt 31" \
+ "Raising interrupt 31" \
+ "PICSR = 0x80000000" \
+ "Clearing interrupt 31" \
+ "Raising interrupt 1" \
+ "PICSR = 0x00000002" \
+ "Clearing interrupt 1" \
+ "Raising interrupt 0" \
+ "PICSR = 0x00000001" \
+ "Clearing interrupt 0" \
+ "Test completed successfully."] \
+ "lib-inttest/lib-inttest-level" "int-level.cfg" \
+ "int-logger/int-logger-level" "+0" "-0" "+1" "-1" "+31" "-31" "+32" "-32" \
+ "+31" "-31" "+1" "-1" "+0" "-0"
Index: int-level.cfg
===================================================================
--- int-level.cfg (nonexistent)
+++ int-level.cfg (revision 135)
@@ -0,0 +1,160 @@
+/* int-level.cfg -- Or1ksim configuration script file for level triggered PIC
+
+ Copyright (C) 2001, Marko Mlinar
+ Copyright (C) 2010 Embecosm Limited
+
+ Contributor Marko Mlinar
+ Contributor Jeremy Bennett
+
+ This file is part of OpenRISC 1000 Architectural Simulator.
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 3 of the License, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program. If not, see . */
+
+section memory
+ /*random_seed = 12345
+ type = random*/
+ pattern = 0x00
+ type = unknown /* Fastest */
+
+ name = "FLASH"
+ ce = 0
+ mc = 0
+ baseaddr = 0xf0000000
+ size = 0x00200000
+ delayr = 10
+ delayw = -1
+end
+
+section memory
+ /*random_seed = 12345
+ type = random*/
+ pattern = 0x00
+ type = unknown /* Fastest */
+
+ name = "RAM"
+ ce = 1
+ mc = 0
+ baseaddr = 0x00000000
+ size = 0x00200000
+ delayr = 2
+ delayw = 4
+end
+
+section immu
+ enabled = 1
+ nsets = 64
+ nways = 1
+ ustates = 2
+ pagesize = 8192
+end
+
+section dmmu
+ enabled = 1
+ nsets = 64
+ nways = 1
+ ustates = 2
+ pagesize = 8192
+end
+
+section ic
+ enabled = 1
+ nsets = 256
+ nways = 1
+ ustates = 2
+ blocksize = 16
+end
+
+section dc
+ enabled = 1
+ nsets = 256
+ nways = 1
+ ustates = 2
+ blocksize = 16
+end
+
+section cpu
+ ver = 0x12
+ rev = 0x0001
+ /* upr = */
+ superscalar = 0
+ hazards = 0
+ dependstats = 0
+end
+
+section bpb
+ enabled = 0
+ btic = 0
+end
+
+section debug
+/* enabled = 1
+ rsp_enabled = 1
+ rsp_port = 51000*/
+end
+
+section sim
+ debug = 0
+ profile = 0
+ prof_fn = "sim.profile"
+
+ exe_log = 0
+ exe_log_type = software
+ exe_log_fn = "executed.log"
+end
+
+section mc
+ enabled = 1
+ baseaddr = 0x93000000
+ POC = 0x00000008 /* Power on configuration register */
+ index = 0
+end
+
+section dma
+ baseaddr = 0xB8000000
+ irq = 4
+end
+
+section ethernet
+ enabled = 0
+ baseaddr = 0x92000000
+ irq = 4
+ rtx_type = 0
+end
+
+section VAPI
+ enabled = 0
+ server_port = 9998
+end
+
+section fb
+ enabled = 1
+ baseaddr = 0x97000000
+ refresh_rate = 10000
+ filename = "primary"
+end
+
+section kbd
+ enabled = 0
+end
+
+section pic
+ enabled = 1
+ edge_trigger = 0 /* Level triggered */
+end
+
+section generic
+ enabled = 1
+ baseaddr = 0x98000000
+ size = 8
+end
Index: upcalls.exp
===================================================================
--- upcalls.exp (nonexistent)
+++ upcalls.exp (revision 135)
@@ -0,0 +1,78 @@
+# upcalls.exp. Test of the library upcall functions
+
+# Copyright (C) 2010 Embecosm Limited
+
+# Contributor Jeremy Bennett
+
+# This file is part of OpenRISC 1000 Architectural Simulator.
+
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 3 of the License, or (at your option)
+# any later version.
+
+# This program is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+
+# You should have received a copy of the GNU General Public License along
+# with this program. If not, see . */
+
+# -----------------------------------------------------------------------------
+# This code is commented throughout for use with Doxygen.
+# -----------------------------------------------------------------------------
+
+
+# Run the basic upcall test
+run_libsim "upcalls - basic" \
+ [list "Initalization succeeded." \
+ "Setting alignment exception handler." \
+ "Writing registers." \
+ "Wrote byte at 0x98000000 = 0xde." \
+ "Wrote byte at 0x98000001 = 0xad." \
+ "Wrote byte at 0x98000002 = 0xbe." \
+ "Wrote byte at 0x98000003 = 0xef." \
+ "Wrote half word at 0x98000004 = 0xbaad." \
+ "Wrote half word at 0x98000006 = 0xf00d." \
+ "Wrote full word at 0x98000008 = 0xcafebabe." \
+ "Reading registers." \
+ "Read full word at 0x98000000 = 0xdeadbeef." \
+ "Read byte at 0x98000004 = 0xba." \
+ "Read byte at 0x98000005 = 0xad." \
+ "Read byte at 0x98000006 = 0xf0." \
+ "Read byte at 0x98000007 = 0x0d." \
+ "Read half word at 0x98000008 = 0xcafe." \
+ "Read half word at 0x9800000a = 0xbabe." \
+ "All done." \
+ "report(0xdeaddead);" \
+ "exit(0)"] \
+ "lib-upcalls/lib-upcalls" "upcalls.cfg" "upcalls/upcall-basic" \
+ "14" "32"
+
+# Run the misalignment upcall test
+run_libsim "upcalls - misaligned" \
+ [list "Initalization succeeded." \
+ "Setting alignment exception handler." \
+ "Writing registers." \
+ "Wrote byte at 0x98000000 = 0xde." \
+ "Wrote half word at 0x98000002 = 0xdead." \
+ "Writing half word at 0x98000005: misalignment exception." \
+ "Wrote full word at 0x98000008 = 0xdeadbeef." \
+ "Writing full word at 0x9800000d: misalignment exception." \
+ "Writing full word at 0x98000012: misalignment exception." \
+ "Writing full word at 0x98000017: misalignment exception." \
+ "Wrote full word at 0x9800001c = 0xbaadbabe." \
+ "Reading registers." \
+ "Read byte at 0x98000000 = 0xde." \
+ "Read half word at 0x98000002 = 0xdead." \
+ "Reading half word at 0x98000005: misalignment exception." \
+ "Read full word at 0x98000008 = 0xdeadbeef." \
+ "Reading full word at 0x9800000d: misalignment exception." \
+ "Reading full word at 0x98000012: misalignment exception." \
+ "Reading full word at 0x98000017: misalignment exception." \
+ "Read full word at 0x9800001c = 0xbaadbabe." \
+ "report(0xdeaddead);" \
+ "exit(0)"] \
+ "lib-upcalls/lib-upcalls" "upcalls.cfg" "upcalls/upcall-misaligned" \
+ "8" "32"
Index: lib-iftest.exp
===================================================================
--- lib-iftest.exp (nonexistent)
+++ lib-iftest.exp (revision 135)
@@ -0,0 +1,37 @@
+# lib-iftest.exp. Test of the library interface functions.
+
+# Copyright (C) 2010 Embecosm Limited
+
+# Contributor Jeremy Bennett
+
+# This file is part of OpenRISC 1000 Architectural Simulator.
+
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 3 of the License, or (at your option)
+# any later version.
+
+# This program is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+
+# You should have received a copy of the GNU General Public License along
+# with this program. If not, see . */
+
+# -----------------------------------------------------------------------------
+# This code is commented throughout for use with Doxygen.
+# -----------------------------------------------------------------------------
+
+
+# Run the library interface test
+run_libsim "lib-iftest" \
+ [list "Initalization succeeded." \
+ "Running code...done." \
+ "Set time point." \
+ "Running code...done." \
+ "Measured time period correctly." \
+ "Big endian architecture." \
+ "Clock rate 250000000 Hz." \
+ "Test completed successfully."] \
+ "lib-iftest/lib-iftest" "" "loop/loop" "1"