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/openrisc/tags/or1ksim/or1ksim-0.4.0/testsuite/libsim.tests
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Makefile.am Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: upcalls.cfg =================================================================== --- upcalls.cfg (nonexistent) +++ upcalls.cfg (revision 135) @@ -0,0 +1,155 @@ +/* upcalls.cfg -- Or1ksim configuration script file for upcall testing + + Copyright (C) 2001, Marko Mlinar + Copyright (C) 2010 Embecosm Limited + + Contributor Marko Mlinar + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + +section memory + /*random_seed = 12345 + type = random*/ + pattern = 0x00 + type = unknown /* Fastest */ + + name = "FLASH" + ce = 0 + mc = 0 + baseaddr = 0xf0000000 + size = 0x00200000 + delayr = 10 + delayw = -1 +end + +section memory + /*random_seed = 12345 + type = random*/ + pattern = 0x00 + type = unknown /* Fastest */ + + name = "RAM" + ce = 1 + mc = 0 + baseaddr = 0x00000000 + size = 0x00200000 + delayr = 2 + delayw = 4 +end + +section immu + enabled = 1 + nsets = 64 + nways = 1 + ustates = 2 + pagesize = 8192 +end + +section dmmu + enabled = 1 + nsets = 64 + nways = 1 + ustates = 2 + pagesize = 8192 +end + +section ic + enabled = 1 + nsets = 256 + nways = 1 + ustates = 2 + blocksize = 16 +end + +section dc + enabled = 1 + nsets = 256 + nways = 1 + ustates = 2 + blocksize = 16 +end + +section cpu + ver = 0x12 + rev = 0x0001 + /* upr = */ + superscalar = 0 + hazards = 0 + dependstats = 0 +end + +section bpb + enabled = 0 + btic = 0 +end + +section debug +/* enabled = 1 + rsp_enabled = 1 + rsp_port = 51000*/ +end + +section sim + debug = 0 + profile = 0 + prof_fn = "sim.profile" + + exe_log = 0 + exe_log_type = software + exe_log_fn = "executed.log" +end + +section mc + enabled = 1 + baseaddr = 0x93000000 + POC = 0x00000008 /* Power on configuration register */ + index = 0 +end + +section dma + baseaddr = 0xB8000000 + irq = 4 +end + +section ethernet + enabled = 0 + baseaddr = 0x92000000 + irq = 4 + rtx_type = 0 +end + +section VAPI + enabled = 0 + server_port = 9998 +end + +section fb + enabled = 1 + baseaddr = 0x97000000 + refresh_rate = 10000 + filename = "primary" +end + +section kbd + enabled = 0 +end + +section generic + enabled = 1 + baseaddr = 0x98000000 + size = 32 +end Index: int-edge.exp =================================================================== --- int-edge.exp (nonexistent) +++ int-edge.exp (revision 135) @@ -0,0 +1,130 @@ +# int-edge.exp. Test of the library edge triggered interrupt functions + +# Copyright (C) 2010 Embecosm Limited + +# Contributor Jeremy Bennett + +# This file is part of OpenRISC 1000 Architectural Simulator. + +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 3 of the License, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +# You should have received a copy of the GNU General Public License along +# with this program. If not, see . */ + +# ----------------------------------------------------------------------------- +# This code is commented throughout for use with Doxygen. +# ----------------------------------------------------------------------------- + + +# Run the library edge triggered interrupts in a number of ways. + +# Sequence of independent interrupts +run_libsim "int-edge simple 1" \ + [list "Initalization succeeded." \ + "Starting interrupt handler" \ + "Enabling interrupts." \ + "Triggering interrupt 2" \ + "PICSR 0x00000004 -> 0x00000000" \ + "Triggering interrupt 3" \ + "PICSR 0x00000008 -> 0x00000000" \ + "Test completed successfully."] \ + "lib-inttest/lib-inttest-edge" "int-edge.cfg" \ + "int-logger/int-logger-edge" "1" "2" "3" + +run_libsim "int-edge simple 2" \ + [list "Initalization succeeded." \ + "Starting interrupt handler" \ + "Enabling interrupts." \ + "Triggering interrupt 7" \ + "PICSR 0x00000080 -> 0x00000000" \ + "Triggering interrupt 17" \ + "PICSR 0x00020000 -> 0x00000000" \ + "Triggering interrupt 31" \ + "PICSR 0x80000000 -> 0x00000000" \ + "Test completed successfully."] \ + "lib-inttest/lib-inttest-edge" "int-edge.cfg" \ + "int-logger/int-logger-edge" "1" "7" "17" "31" + +# Duplicated interrupts +run_libsim "int-edge duplicated 1" \ + [list "Initalization succeeded." \ + "Starting interrupt handler" \ + "Enabling interrupts." \ + "Triggering interrupt 2" \ + "PICSR 0x00000004 -> 0x00000000" \ + "Triggering interrupt 4" \ + "PICSR 0x00000010 -> 0x00000000" \ + "Triggering interrupt 2" \ + "PICSR 0x00000004 -> 0x00000000" \ + "Test completed successfully."] \ + "lib-inttest/lib-inttest-edge" "int-edge.cfg" \ + "int-logger/int-logger-edge" "1" "2" "4" "2" + +run_libsim "int-edge duplicated 2" \ + [list "Initalization succeeded." \ + "Starting interrupt handler" \ + "Enabling interrupts." \ + "Triggering interrupt 2" \ + "PICSR 0x00000004 -> 0x00000000" \ + "Triggering interrupt 2" \ + "PICSR 0x00000004 -> 0x00000000" \ + "Triggering interrupt 2" \ + "PICSR 0x00000004 -> 0x00000000" \ + "Triggering interrupt 2" \ + "PICSR 0x00000004 -> 0x00000000" \ + "Triggering interrupt 2" \ + "PICSR 0x00000004 -> 0x00000000" \ + "Triggering interrupt 2" \ + "PICSR 0x00000004 -> 0x00000000" \ + "Triggering interrupt 2" \ + "PICSR 0x00000004 -> 0x00000000" \ + "Triggering interrupt 2" \ + "PICSR 0x00000004 -> 0x00000000" \ + "Test completed successfully."] \ + "lib-inttest/lib-inttest-edge" "int-edge.cfg" \ + "int-logger/int-logger-edge" "1" "2" "2" "2" "2" "2" "2" "2" "2" + +# All from upcalls +run_libsim "int-edge all upcall" \ + [list "Initalization succeeded." \ + "Starting interrupt handler" \ + "Enabling interrupts." \ + "Triggering interrupt 7" \ + "PICSR 0x00000080 -> 0x00000000" \ + "Triggering interrupt 17" \ + "PICSR 0x00020000 -> 0x00000000" \ + "Triggering interrupt 31" \ + "PICSR 0x80000000 -> 0x00000000" \ + "Test completed successfully."] \ + "lib-inttest/lib-inttest-edge" "int-edge.cfg" \ + "int-logger/int-logger-edge" "20" "7" "17" "31" + +# Check the boundaries of acceptable interrupt numbers +run_libsim "int-edge check boundaries" \ + [list "Initalization succeeded." \ + "Starting interrupt handler" \ + "Enabling interrupts." \ + "Triggering interrupt 0" \ + "PICSR 0x00000001 -> 0x00000000" \ + "Triggering interrupt 1" \ + "PICSR 0x00000002 -> 0x00000000" \ + "Triggering interrupt 31" \ + "PICSR 0x80000000 -> 0x00000000" \ + "Warning: Invalid interrupt # 32 - ignored" \ + "Triggering interrupt 31" \ + "PICSR 0x80000000 -> 0x00000000" \ + "Triggering interrupt 1" \ + "PICSR 0x00000002 -> 0x00000000" \ + "Triggering interrupt 0" \ + "PICSR 0x00000001 -> 0x00000000" \ + "Test completed successfully."] \ + "lib-inttest/lib-inttest-edge" "int-edge.cfg" \ + "int-logger/int-logger-edge" "10" "0" "1" "31" "32" "31" "1" "0" Index: int-edge.cfg =================================================================== --- int-edge.cfg (nonexistent) +++ int-edge.cfg (revision 135) @@ -0,0 +1,160 @@ +/* int-edge.cfg -- Or1ksim configuration script file for edge triggered PIC + + Copyright (C) 2001, Marko Mlinar + Copyright (C) 2010 Embecosm Limited + + Contributor Marko Mlinar + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + +section memory + /*random_seed = 12345 + type = random*/ + pattern = 0x00 + type = unknown /* Fastest */ + + name = "FLASH" + ce = 0 + mc = 0 + baseaddr = 0xf0000000 + size = 0x00200000 + delayr = 10 + delayw = -1 +end + +section memory + /*random_seed = 12345 + type = random*/ + pattern = 0x00 + type = unknown /* Fastest */ + + name = "RAM" + ce = 1 + mc = 0 + baseaddr = 0x00000000 + size = 0x00200000 + delayr = 2 + delayw = 4 +end + +section immu + enabled = 1 + nsets = 64 + nways = 1 + ustates = 2 + pagesize = 8192 +end + +section dmmu + enabled = 1 + nsets = 64 + nways = 1 + ustates = 2 + pagesize = 8192 +end + +section ic + enabled = 1 + nsets = 256 + nways = 1 + ustates = 2 + blocksize = 16 +end + +section dc + enabled = 1 + nsets = 256 + nways = 1 + ustates = 2 + blocksize = 16 +end + +section cpu + ver = 0x12 + rev = 0x0001 + /* upr = */ + superscalar = 0 + hazards = 0 + dependstats = 0 +end + +section bpb + enabled = 0 + btic = 0 +end + +section debug +/* enabled = 1 + rsp_enabled = 1 + rsp_port = 51000*/ +end + +section sim + debug = 0 + profile = 0 + prof_fn = "sim.profile" + + exe_log = 0 + exe_log_type = software + exe_log_fn = "executed.log" +end + +section mc + enabled = 1 + baseaddr = 0x93000000 + POC = 0x00000008 /* Power on configuration register */ + index = 0 +end + +section dma + baseaddr = 0xB8000000 + irq = 4 +end + +section ethernet + enabled = 0 + baseaddr = 0x92000000 + irq = 4 + rtx_type = 0 +end + +section VAPI + enabled = 0 + server_port = 9998 +end + +section fb + enabled = 1 + baseaddr = 0x97000000 + refresh_rate = 10000 + filename = "primary" +end + +section kbd + enabled = 0 +end + +section pic + enabled = 1 + edge_trigger = 1 +end + +section generic + enabled = 1 + baseaddr = 0x98000000 + size = 8 +end Index: int-level.exp =================================================================== --- int-level.exp (nonexistent) +++ int-level.exp (revision 135) @@ -0,0 +1,113 @@ +# int-level.exp. Test of the library level triggered interrupt functions + +# Copyright (C) 2010 Embecosm Limited + +# Contributor Jeremy Bennett + +# This file is part of OpenRISC 1000 Architectural Simulator. + +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 3 of the License, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +# You should have received a copy of the GNU General Public License along +# with this program. If not, see . */ + +# ----------------------------------------------------------------------------- +# This code is commented throughout for use with Doxygen. +# ----------------------------------------------------------------------------- + + +# Run the library level triggered interrupts in a number of ways. + +# Sequence of independent interrupts +run_libsim "int-level simple 1" \ + [list "Initalization succeeded." \ + "Starting interrupt handler" \ + "Enabling interrupts." \ + "Raising interrupt 1" \ + "PICSR = 0x00000002" \ + "Clearing interrupt 1" \ + "Test completed successfully."] \ + "lib-inttest/lib-inttest-level" "int-level.cfg" \ + "int-logger/int-logger-level" "+1" "-1" + +run_libsim "int-level simple 2" \ + [list "Initalization succeeded." \ + "Starting interrupt handler" \ + "Enabling interrupts." \ + "Raising interrupt 7" \ + "PICSR = 0x00000080" \ + "Clearing interrupt 7" \ + "Raising interrupt 17" \ + "PICSR = 0x00020000" \ + "Clearing interrupt 17" \ + "Raising interrupt 31" \ + "PICSR = 0x80000000" \ + "Clearing interrupt 31" \ + "Test completed successfully."] \ + "lib-inttest/lib-inttest-level" "int-level.cfg" \ + "int-logger/int-logger-level" "+7" "-7" "+17" "-17" "+31" "-31" + +# Uncleared interrupt (this only matches the first two reports or PICSR, there +# are many) +run_libsim "int-level uncleared interrupt" \ + [list "Initalization succeeded." \ + "Starting interrupt handler" \ + "Enabling interrupts." \ + "Raising interrupt 1" \ + "PICSR = 0x00000002" \ + "PICSR = 0x00000002" \ + "Test completed successfully."] \ + "lib-inttest/lib-inttest-level" "int-level.cfg" \ + "int-logger/int-logger-level" "+1" + +# Clearing the wrong interrupt +run_libsim "int-level wrong clear" \ + [list "Initalization succeeded." \ + "Starting interrupt handler" \ + "Enabling interrupts." \ + "Raising interrupt 31" \ + "PICSR = 0x80000000" \ + "Clearing interrupt 1" \ + "PICSR = 0x80000000" \ + "Clearing interrupt 31" \ + "Test completed successfully."] \ + "lib-inttest/lib-inttest-level" "int-level.cfg" \ + "int-logger/int-logger-level" "+31" "-1" "-31" + +# Check the boundaries of acceptable interrupt numbers +run_libsim "int-level check boundaries" \ + [list "Warning: Invalid interrupt # 32 to raise." \ + "Warning: Invalid interrupt # 32 to clear." \ + "Initalization succeeded." \ + "Starting interrupt handler" \ + "Enabling interrupts." \ + "Raising interrupt 0" \ + "PICSR = 0x00000001" \ + "Clearing interrupt 0" \ + "Raising interrupt 1" \ + "PICSR = 0x00000002" \ + "Clearing interrupt 1" \ + "Raising interrupt 31" \ + "PICSR = 0x80000000" \ + "Clearing interrupt 31" \ + "Raising interrupt 31" \ + "PICSR = 0x80000000" \ + "Clearing interrupt 31" \ + "Raising interrupt 1" \ + "PICSR = 0x00000002" \ + "Clearing interrupt 1" \ + "Raising interrupt 0" \ + "PICSR = 0x00000001" \ + "Clearing interrupt 0" \ + "Test completed successfully."] \ + "lib-inttest/lib-inttest-level" "int-level.cfg" \ + "int-logger/int-logger-level" "+0" "-0" "+1" "-1" "+31" "-31" "+32" "-32" \ + "+31" "-31" "+1" "-1" "+0" "-0" Index: int-level.cfg =================================================================== --- int-level.cfg (nonexistent) +++ int-level.cfg (revision 135) @@ -0,0 +1,160 @@ +/* int-level.cfg -- Or1ksim configuration script file for level triggered PIC + + Copyright (C) 2001, Marko Mlinar + Copyright (C) 2010 Embecosm Limited + + Contributor Marko Mlinar + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + +section memory + /*random_seed = 12345 + type = random*/ + pattern = 0x00 + type = unknown /* Fastest */ + + name = "FLASH" + ce = 0 + mc = 0 + baseaddr = 0xf0000000 + size = 0x00200000 + delayr = 10 + delayw = -1 +end + +section memory + /*random_seed = 12345 + type = random*/ + pattern = 0x00 + type = unknown /* Fastest */ + + name = "RAM" + ce = 1 + mc = 0 + baseaddr = 0x00000000 + size = 0x00200000 + delayr = 2 + delayw = 4 +end + +section immu + enabled = 1 + nsets = 64 + nways = 1 + ustates = 2 + pagesize = 8192 +end + +section dmmu + enabled = 1 + nsets = 64 + nways = 1 + ustates = 2 + pagesize = 8192 +end + +section ic + enabled = 1 + nsets = 256 + nways = 1 + ustates = 2 + blocksize = 16 +end + +section dc + enabled = 1 + nsets = 256 + nways = 1 + ustates = 2 + blocksize = 16 +end + +section cpu + ver = 0x12 + rev = 0x0001 + /* upr = */ + superscalar = 0 + hazards = 0 + dependstats = 0 +end + +section bpb + enabled = 0 + btic = 0 +end + +section debug +/* enabled = 1 + rsp_enabled = 1 + rsp_port = 51000*/ +end + +section sim + debug = 0 + profile = 0 + prof_fn = "sim.profile" + + exe_log = 0 + exe_log_type = software + exe_log_fn = "executed.log" +end + +section mc + enabled = 1 + baseaddr = 0x93000000 + POC = 0x00000008 /* Power on configuration register */ + index = 0 +end + +section dma + baseaddr = 0xB8000000 + irq = 4 +end + +section ethernet + enabled = 0 + baseaddr = 0x92000000 + irq = 4 + rtx_type = 0 +end + +section VAPI + enabled = 0 + server_port = 9998 +end + +section fb + enabled = 1 + baseaddr = 0x97000000 + refresh_rate = 10000 + filename = "primary" +end + +section kbd + enabled = 0 +end + +section pic + enabled = 1 + edge_trigger = 0 /* Level triggered */ +end + +section generic + enabled = 1 + baseaddr = 0x98000000 + size = 8 +end Index: upcalls.exp =================================================================== --- upcalls.exp (nonexistent) +++ upcalls.exp (revision 135) @@ -0,0 +1,78 @@ +# upcalls.exp. Test of the library upcall functions + +# Copyright (C) 2010 Embecosm Limited + +# Contributor Jeremy Bennett + +# This file is part of OpenRISC 1000 Architectural Simulator. + +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 3 of the License, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +# You should have received a copy of the GNU General Public License along +# with this program. If not, see . */ + +# ----------------------------------------------------------------------------- +# This code is commented throughout for use with Doxygen. +# ----------------------------------------------------------------------------- + + +# Run the basic upcall test +run_libsim "upcalls - basic" \ + [list "Initalization succeeded." \ + "Setting alignment exception handler." \ + "Writing registers." \ + "Wrote byte at 0x98000000 = 0xde." \ + "Wrote byte at 0x98000001 = 0xad." \ + "Wrote byte at 0x98000002 = 0xbe." \ + "Wrote byte at 0x98000003 = 0xef." \ + "Wrote half word at 0x98000004 = 0xbaad." \ + "Wrote half word at 0x98000006 = 0xf00d." \ + "Wrote full word at 0x98000008 = 0xcafebabe." \ + "Reading registers." \ + "Read full word at 0x98000000 = 0xdeadbeef." \ + "Read byte at 0x98000004 = 0xba." \ + "Read byte at 0x98000005 = 0xad." \ + "Read byte at 0x98000006 = 0xf0." \ + "Read byte at 0x98000007 = 0x0d." \ + "Read half word at 0x98000008 = 0xcafe." \ + "Read half word at 0x9800000a = 0xbabe." \ + "All done." \ + "report(0xdeaddead);" \ + "exit(0)"] \ + "lib-upcalls/lib-upcalls" "upcalls.cfg" "upcalls/upcall-basic" \ + "14" "32" + +# Run the misalignment upcall test +run_libsim "upcalls - misaligned" \ + [list "Initalization succeeded." \ + "Setting alignment exception handler." \ + "Writing registers." \ + "Wrote byte at 0x98000000 = 0xde." \ + "Wrote half word at 0x98000002 = 0xdead." \ + "Writing half word at 0x98000005: misalignment exception." \ + "Wrote full word at 0x98000008 = 0xdeadbeef." \ + "Writing full word at 0x9800000d: misalignment exception." \ + "Writing full word at 0x98000012: misalignment exception." \ + "Writing full word at 0x98000017: misalignment exception." \ + "Wrote full word at 0x9800001c = 0xbaadbabe." \ + "Reading registers." \ + "Read byte at 0x98000000 = 0xde." \ + "Read half word at 0x98000002 = 0xdead." \ + "Reading half word at 0x98000005: misalignment exception." \ + "Read full word at 0x98000008 = 0xdeadbeef." \ + "Reading full word at 0x9800000d: misalignment exception." \ + "Reading full word at 0x98000012: misalignment exception." \ + "Reading full word at 0x98000017: misalignment exception." \ + "Read full word at 0x9800001c = 0xbaadbabe." \ + "report(0xdeaddead);" \ + "exit(0)"] \ + "lib-upcalls/lib-upcalls" "upcalls.cfg" "upcalls/upcall-misaligned" \ + "8" "32" Index: lib-iftest.exp =================================================================== --- lib-iftest.exp (nonexistent) +++ lib-iftest.exp (revision 135) @@ -0,0 +1,37 @@ +# lib-iftest.exp. Test of the library interface functions. + +# Copyright (C) 2010 Embecosm Limited + +# Contributor Jeremy Bennett + +# This file is part of OpenRISC 1000 Architectural Simulator. + +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 3 of the License, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +# You should have received a copy of the GNU General Public License along +# with this program. If not, see . */ + +# ----------------------------------------------------------------------------- +# This code is commented throughout for use with Doxygen. +# ----------------------------------------------------------------------------- + + +# Run the library interface test +run_libsim "lib-iftest" \ + [list "Initalization succeeded." \ + "Running code...done." \ + "Set time point." \ + "Running code...done." \ + "Measured time period correctly." \ + "Big endian architecture." \ + "Clock rate 250000000 Hz." \ + "Test completed successfully."] \ + "lib-iftest/lib-iftest" "" "loop/loop" "1"

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