Subversion Repositories openrisc

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/ipc.h

ipc.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: task.c =================================================================== --- task.c (nonexistent) +++ task.c (revision 105) @@ -0,0 +1,79 @@ +/* task.c. Microkernel task handler for Or1ksim + + Copyright (C) 2000 Damjan Lampret + Copyright (C) 2010 Embecosm Limited + + Contributor Damjan Lampret + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + +/* ---------------------------------------------------------------------------- + This code is commented throughout for use with Doxygen. + --------------------------------------------------------------------------*/ + +/* This file is part of test microkernel for OpenRISC 1000. */ + +#include "support.h" +#include "uos.h" +#include "ipc.h" +#include "int.h" + +extern struct tcb tasks[MAX_TASKS+1]; + +int task(int id) +{ + struct _msg { + char id; + unsigned long count; + } msg; + + printf("Task %d started\n", id); + + if(id == 1) { + msg.id = 1; + msg.count = 0; + uos_msgsnd(2, (char *)&msg, sizeof(msg)); + } + + for(;;) { + uos_msgrcv(0, (char *)&msg, sizeof(msg)); + + printf("Task %d: Got massage from task %d: 0x%.8x. " + "Sending message to task %d: 0x%.8x \n", id, msg.id, + (int)msg.count, (id == 3 ? 1 : (id + 1)), + (int)(msg.count + 1)); + msg.id = id; + + if((id == 1) && (msg.count > 15)) { + report(msg.count + 0xdeadde9c); + exit(0); + + + msg.count += 1; + uos_msgsnd((id == 3 ? 1 : (id + 1)), (char *)&msg, sizeof(msg)); + } + } +} + +/* Called by kernel_init to collect all tasks entries. */ +void tasks_entries() +{ + tasks[1].regs.pc = (unsigned long)task; + tasks[2].regs.pc = (unsigned long)task; + tasks[3].regs.pc = (unsigned long)task; +} +

task.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: uos.c =================================================================== --- uos.c (nonexistent) +++ uos.c (revision 105) @@ -0,0 +1,342 @@ +/* uos.c. Microkernel for Or1ksim + + Copyright (C) 2000 Damjan Lampret + Copyright (C) 2010 Embecosm Limited + + Contributor Damjan Lampret + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + +/* ---------------------------------------------------------------------------- + This code is commented throughout for use with Doxygen. + --------------------------------------------------------------------------*/ + +/* This file is part of test microkernel for OpenRISC 1000. */ + +#include "support.h" +#include "spr-defs.h" +#include "uos.h" +#include "ipc.h" +#include "int.h" + +/* External functions prototypes */ +int tick_init(unsigned long period, void (* inf)(void)); + +/* Pointers to contexts used by except_or32.S routines */ +unsigned long *task_context; +unsigned long *kernel_context; + +/* TCBs for all tasks in the system */ +struct tcb tasks[MAX_TASKS+1]; + +/* Stacks for the tasks (stacks[0] is kernel stack) */ +unsigned char stacks[MAX_TASKS+1][STACK_SIZE]; + +/* MCBs for IPC messages */ +struct mcb msgs[MAX_MSGS]; + +/* Pointer to linked list of free MCBs. */ +struct mcb *free_mcbs; + +/* TID of the current user task */ +tid_t curtask = 0; + +/* Statistics */ +int kernel_sched_cnt = 0; +int kernel_syscall_cnt = 0; + +/* Timestamp via or1ksim (CPU cycle number). */ +unsigned long timestamp() +{ + register unsigned long cycles asm("r3"); + asm("l.sys 201"); + return cycles; +} + +/* Standard function for filling memory with a constant byte. */ +void *memset(void *dst, int c, size_t size) +{ + char *tmp = dst; + + for(;tmp && (tmp < (char *)dst + size); tmp++) + *(char *)tmp = (char)c; + + return dst; +} + +/* Traverse linked list of MCBs and show individual messages. */ +void kernel_show_mcbs(struct mcb *mcb) +{ + for(;mcb; mcb = mcb->next) { + printf("MCB len=%u origintask=%u ", mcb->length, mcb->origin); + printf("msg:%s\n", mcb->msg); + } +} + +/* Show all contexts. */ +void kernel_show_contexts() +{ + int i; + tid_t t; + + for(t = 1; t <= MAX_TASKS; t++) { + printf("\ntask TID=%d: PC=0x%x ", t, (unsigned)tasks[t].regs.pc & ~0x3); + printf("SP(r1)=0x%x ", (unsigned)tasks[t].regs.sp); + printf("SR[IEE]=%d\n", (unsigned)tasks[t].regs.sr & SPR_SR_IEE); + printf("SR[TEE]=%d\n", (unsigned)tasks[t].regs.sr & SPR_SR_TEE); + printf("SR[SM]=%d\n", (unsigned)tasks[t].regs.sr & SPR_SR_SM); + for(i = 1; i < GPRS; i++) { + if (i % 4 == 0) + printf("\n"); + printf("r%d=0x%.8x ", i, (unsigned)tasks[t].regs.gprs[i]); + } + printf("\n"); + kernel_show_mcbs(tasks[t].waiting_msgs); + } + printf("\n"); +} + +/* Simple round-robin scheduler that directly calls dispatcher. It is + called by low level external interrupt exception handler or by + kernel_syscall if KERNEL_SYSCALL_SCHED is defined. */ +void kernel_sched() +{ + if ((++curtask > MAX_TASKS) || !(tasks[curtask].regs.pc & ~0x3)) + curtask = 1; + task_context = (unsigned long *)&tasks[curtask].regs; + +#if KERNEL_OUTPUT + printf("kernel_sched(): entry number %d, ", ++kernel_sched_cnt); + printf("dispatching task TID=%d, time %u cycles", curtask, timestamp()); + + kernel_show_contexts(); +#endif + + dispatch(); +} + +/* System call uos_msgsnd. */ +void +uos_msgsnd(tid_t desttask, char *buf, int len) +{ + asm("l.sys 1"); + asm("l.nop"); +} + +/* System call uos_msgrcv. */ +void +uos_msgrcv(tid_t origintask, char *buf, int len) +{ + asm("l.sys 2"); + asm("l.nop"); +} + +/* Handles system call uos_msgsnd. */ +void kernel_msgsnd(tid_t tid) +{ + struct mcb *mcb; + struct mcb **dstmq; + struct tcb *task; + + task = &tasks[tid]; + + /* Sanity checks. */ + + /* Does destination task exist? */ + if (!task->regs.gprs[1] || (task->regs.gprs[1] > MAX_TASKS)) { + task->regs.gprs[9] = IPC_ENOTASK; + return; + } + + /* Are there any free MCBs? */ + if (!free_mcbs) { + task->regs.gprs[9] = IPC_EOUTOFMCBS; + return; + } + + /* Is message too big to fit into MCB's message buffer? */ + if (task->regs.gprs[3] > MAX_MSGLEN) { + task->regs.gprs[9] = IPC_ETOOBIG; + return; + } + + /* OK, send the message. */ + + /* First, allocate MCB. */ + mcb = free_mcbs; + free_mcbs = mcb->next; + + /* Second, copy message to the MCB. */ + memcpy(mcb->msg, (void *)task->regs.gprs[2], task->regs.gprs[3]); + mcb->origin = tid; + mcb->length = task->regs.gprs[3]; + mcb->next = NULL; + + /* Insert MCB into destination task's message queue at + the end. */ + dstmq = &tasks[task->regs.gprs[1]].waiting_msgs; + for(;*dstmq;) + dstmq = &((*dstmq)->next); + *dstmq = mcb; + + task->regs.gprs[9] = IPC_NOERR; + return; +} + +/* Handles system call uos_msgrcv. */ +void kernel_msgrcv(tid_t tid) +{ + struct mcb *curmsg, **linkp; + struct tcb *task; + + task = &tasks[tid]; + + /* Sanity checks. */ + + /* Does origin task exist? */ + if (task->regs.gprs[1] > MAX_TASKS) { + task->regs.gprs[9] = IPC_ENOTASK; + return; + } + + /* Are there any messages waiting for reception? */ + if (!task->waiting_msgs) { + task->regs.gprs[9] = IPC_ENOMSGS; + return; + } + + /* OK, receive the message. */ + + /* Search waiting messages for one coming from origintask. If + origintask is zero then grab the first message. */ + curmsg = task->waiting_msgs; + linkp = &task->waiting_msgs; + for(;task->regs.gprs[1] && curmsg->next && curmsg->origin != task->regs.gprs[1];) { + linkp = &curmsg->next; + curmsg = curmsg->next; + } + + /* Is receive buffer too small for receiving message? */ + if (task->regs.gprs[3] < curmsg->length) { + task->regs.gprs[9] = IPC_ETOOBIG; + return; + } + + /* Now copy the message from the MCB. */ + memcpy((void *)task->regs.gprs[2], curmsg->msg, task->regs.gprs[3]); + + /* Remove MCB from task's waiting queue and place it + back into free MCBs queue. */ + *linkp = curmsg->next; + curmsg->next = free_mcbs; + free_mcbs = curmsg; + + task->regs.gprs[9] = IPC_NOERR; + return; +} + +/* Handles all uOS system calls. It is called by low level system call + exception handler. */ +void kernel_syscall() +{ + unsigned short syscall_num; + +#if KERNEL_OUTPUT + printf("kernel_syscall(): entry number %d, ", ++kernel_syscall_cnt); + printf("current TID=%d, time %u cycles", curtask, timestamp()); + + kernel_show_contexts(); +#endif + syscall_num = *(unsigned short *)((tasks[curtask].regs.pc & ~0x3) - 6); + + switch(syscall_num) { + case IPC_MSGSND: + kernel_msgsnd(curtask); + break; + case IPC_MSGRCV: + kernel_msgrcv(curtask); + break; + default: + printf("kernel_syscall(): unknown syscall (%u)\n", syscall_num); + } + +#if KERNEL_SYSCALL_SCHED + kernel_sched(); +#endif + dispatch(); +} + +/* Called by reset exception handler to initialize the kernel and start + rolling first task. */ +void +kernel_init() +{ + tid_t t; + int i; + + printf("Initializing kernel:\n"); + + printf(" Clearing kernel structures...\n"); + memset(tasks, 0, sizeof(tasks)); + memset(stacks, 0, sizeof(stacks)); + memset(msgs, 0, sizeof(msgs)); + + printf(" Initializing MCBs... %d MCB(s)\n", MAX_MSGS); + for(i = 0; i < (MAX_MSGS - 1); i++) + msgs[i].next = &msgs[i+1]; + free_mcbs = &msgs[0]; + + printf(" Initializing TCBs... %d user task(s)\n", MAX_TASKS); + + tasks_entries(); + + for(t = 0; t <= MAX_TASKS; t++) { + tasks[t].regs.sp = (unsigned long)stacks[t] + STACK_SIZE - 4; + /* Disable EXR for kernel context */ + tasks[t].regs.sr |= (t == 0 ? SPR_SR_SM : SPR_SR_TEE | SPR_SR_IEE); + tasks[t].regs.gprs[1] = t; + } + + /* First task runs in seprvisor mode */ + tasks[1].regs.sr |= SPR_SR_SM; + + /* TID=0 is reserved for kernel use */ + kernel_context = (unsigned long *)&tasks[0].regs; + + /* First task to be scheduled is task TID=1 */ + task_context = (unsigned long *)&tasks[1].regs; + + /* Initialize initrrupt controller */ + int_init(); + + printf(" Exceptions will be enabled when first task is dispatched.\n"); + printf("Kernel initalized. Starting first user task.\n"); + +#if KERNEL_SYSCALL_SCHED + kernel_sched(); /* Lets schedule and dispatch our first task */ +#else + tick_init(TICK_PERIOD, kernel_sched); + kernel_sched(); /* Lets schedule and dispatch our first task */ +#endif + /* ... */ /* We never get here */ +} + +int main () +{ + kernel_init(); + return 0; +}

uos.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: Makefile.am =================================================================== --- Makefile.am (nonexistent) +++ Makefile.am (revision 105) @@ -0,0 +1,41 @@ +# Makefile.am for or1ksim uos test code + +# Copyright (C) Marko Mlinar, 2001 +# Copyright (C) Embecosm Limited, 2010 + +# Contributor Marko Mlinar +# Contributor Jeremy Bennett + +# This file is part of OpenRISC 1000 Architectural Simulator. + +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 3 of the License, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +# You should have received a copy of the GNU General Public License along +# with this program. If not, see . */ + +# ----------------------------------------------------------------------------- +# This code is commented throughout for use with Doxygen. +# ----------------------------------------------------------------------------- + + +# A test program to show that basic C functionality works +check_PROGRAMS = uos + +uos_SOURCES = except-or32.S \ + ipc.h \ + task.c \ + tick.c \ + uos.h \ + uos.c + +uos_LDFLAGS = -T$(srcdir)/../default.ld + +uos_LDADD = ../support/libsupport.la

Makefile.am Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: tick.c =================================================================== --- tick.c (nonexistent) +++ tick.c (revision 105) @@ -0,0 +1,60 @@ +/* tick.c. Microkernel tick handler for Or1ksim + + Copyright (C) 2000 Damjan Lampret + Copyright (C) 2010 Embecosm Limited + + Contributor Damjan Lampret + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + +/* ---------------------------------------------------------------------------- + This code is commented throughout for use with Doxygen. + --------------------------------------------------------------------------*/ + +/* This file is part of test microkernel for OpenRISC 1000. */ + +#include "spr-defs.h" +#include "support.h" + +/* Tick timer period */ +unsigned long tick_period; + +/* Inform of tick interrupt */ +void (*tick_inf)(); + +/* Tick interrupt routine */ +void tick_int() +{ + /* Call inf routine */ + (*tick_inf)(); + + /* Set new counter period iand clear inet pending bit */ + mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | (tick_period & SPR_TTMR_PERIOD)); +} + +/* Initialize routine */ +int tick_init(unsigned long period, void (* inf)()) +{ + /* Save tick timer period and inform routine */ + tick_period = period; + tick_inf = inf; + + /* Set counter period, enable timer and interrupt */ + mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | (period & SPR_TTMR_PERIOD)); + + return 0; +}

tick.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: except-or32.S =================================================================== --- except-or32.S (nonexistent) +++ except-or32.S (revision 105) @@ -0,0 +1,377 @@ +/* except-or32.S Microkernel exception handler for Or1ksim + + Copyright (C) 2000 Damjan Lampret + Copyright (C) 2010 Embecosm Limited + + Contributor Damjan Lampret + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + +/* ---------------------------------------------------------------------------- + This code is commented throughout for use with Doxygen. + --------------------------------------------------------------------------*/ + + /* This file is part of test microkernel for OpenRISC 1000. */ + +#include "spr-defs.h" +#include "board.h" + +#define MC_CSR (0x00) +#define MC_POC (0x04) +#define MC_BA_MASK (0x08) +#define MC_CSC(i) (0x10 + (i) * 8) +#define MC_TMS(i) (0x14 + (i) * 8) + + +/* + * Context is saved to area pointed by pointer in R3. Original + * R3 is at memory location 0 and task's PC is at memory location 4. + */ +#define SAVEREGS \ + l.lwz r3,0(r3); \ + l.sw 4(r3),r1; \ + l.sw 8(r3),r2; \ + l.lwz r2,0(r0); /* saving original r3*/ \ + l.sw 12(r3),r2; \ + l.sw 16(r3),r4; \ + l.sw 20(r3),r5; \ + l.sw 24(r3),r6; \ + l.sw 28(r3),r7; \ + l.sw 32(r3),r8; \ + l.sw 36(r3),r9; \ + l.sw 40(r3),r10; \ + l.sw 44(r3),r11; \ + l.sw 48(r3),r12; \ + l.sw 52(r3),r13; \ + l.sw 56(r3),r14; \ + l.sw 60(r3),r15; \ + l.sw 64(r3),r16; \ + l.sw 68(r3),r17; \ + l.sw 72(r3),r18; \ + l.sw 76(r3),r19; \ + l.sw 80(r3),r20; \ + l.sw 84(r3),r21; \ + l.sw 88(r3),r22; \ + l.sw 92(r3),r23; \ + l.sw 96(r3),r24; \ + l.sw 100(r3),r25; \ + l.sw 104(r3),r26; \ + l.sw 108(r3),r27; \ + l.sw 112(r3),r28; \ + l.sw 116(r3),r29; \ + l.sw 120(r3),r30; \ + l.sw 124(r3),r31; \ + l.lwz r2,4(r0); /* saving original PC*/ \ + l.sw 0(r3),r2; \ + \ + l.mfspr r2,r0,SPR_ESR_BASE; \ + l.sw 128(r3),r2 /* saving SR */ + +/* + * Pointer to context is in R3. All registers are loaded and execution is + * transfered to the loaded context's task + */ +#define LOADREGS_N_GO \ + l.lwz r3,0(r3); \ + l.lwz r2,0(r3); /* prepare PC*/ \ + l.mtspr r0,r2,SPR_EPCR_BASE; \ + \ + l.lwz r2,128(r3); /* prepare SR*/ \ + l.mtspr r0,r2,SPR_ESR_BASE; \ + \ + l.lwz r1,4(r3); \ + l.lwz r2,8(r3); \ + l.lwz r4,16(r3); \ + l.lwz r5,20(r3); \ + l.lwz r6,24(r3); \ + l.lwz r7,28(r3); \ + l.lwz r8,32(r3); \ + l.lwz r9,36(r3); \ + l.lwz r10,40(r3); \ + l.lwz r11,44(r3); \ + l.lwz r12,48(r3); \ + l.lwz r13,52(r3); \ + l.lwz r14,56(r3); \ + l.lwz r15,60(r3); \ + l.lwz r16,64(r3); \ + l.lwz r17,68(r3); \ + l.lwz r18,72(r3); \ + l.lwz r19,76(r3); \ + l.lwz r20,80(r3); \ + l.lwz r21,84(r3); \ + l.lwz r22,88(r3); \ + l.lwz r23,92(r3); \ + l.lwz r24,96(r3); \ + l.lwz r25,100(r3); \ + l.lwz r26,104(r3); \ + l.lwz r27,108(r3); \ + l.lwz r28,112(r3); \ + l.lwz r29,116(r3); \ + l.lwz r30,120(r3); \ + l.lwz r31,124(r3); \ + \ + l.lwz r3,12(r3); /* prepare r3*/ \ + \ + l.rfe; /* Call task */ \ + l.nop + +/* + * All registers are loaded from save area. + */ +#define LOADREGS \ + l.lwz r3,0(r3); \ + l.lwz r2,0(r3); /* prepare PC*/ \ + l.mtspr r0,r2,SPR_EPCR_BASE; \ + \ + l.lwz r2,128(r3); /* prepare SR*/ \ + l.mtspr r0,r2,SPR_ESR_BASE; \ + \ + l.lwz r1,4(r3); \ + l.lwz r2,8(r3); \ + l.lwz r4,16(r3); \ + l.lwz r5,20(r3); \ + l.lwz r6,24(r3); \ + l.lwz r7,28(r3); \ + l.lwz r8,32(r3); \ + l.lwz r9,36(r3); \ + l.lwz r10,40(r3); \ + l.lwz r11,44(r3); \ + l.lwz r12,48(r3); \ + l.lwz r13,52(r3); \ + l.lwz r14,56(r3); \ + l.lwz r15,60(r3); \ + l.lwz r16,64(r3); \ + l.lwz r17,68(r3); \ + l.lwz r18,72(r3); \ + l.lwz r19,76(r3); \ + l.lwz r20,80(r3); \ + l.lwz r21,84(r3); \ + l.lwz r22,88(r3); \ + l.lwz r23,92(r3); \ + l.lwz r24,96(r3); \ + l.lwz r25,100(r3); \ + l.lwz r26,104(r3); \ + l.lwz r27,108(r3); \ + l.lwz r28,112(r3); \ + l.lwz r29,116(r3); \ + l.lwz r30,120(r3); \ + l.lwz r31,124(r3); \ + \ + l.lwz r3,12(r3); /* prepare r3*/ + +/* + * Set new PC in saved context + */ +#define SET_CONTEXTPC(AREA,SUBROUTINE,TMPREG) \ + l.lwz AREA,0(AREA); \ + l.movhi TMPREG,hi(SUBROUTINE); \ + l.addi TMPREG,r0,lo(SUBROUTINE); \ + l.sw 0(AREA),TMPREG; + +/* + * Printf via or1ksim hook + */ +#if KERNEL_OUTPUT +#define PRINTF(REG,STR) \ + l.movhi REG,hi(STR); \ + l.addi REG,r0,lo(STR); \ + l.nop NOP_PRINTF +#else +#define PRINTF(REG,STR) +#endif + +/* + * Reset Exception handler + */ +.org 0x100 +_reset_vector: + + l.movhi r3,hi(MC_BASE_ADDR) + l.ori r3,r3,lo(MC_BASE_ADDR) + + l.addi r4,r3,MC_CSC(0) + l.movhi r5,hi(FLASH_BASE_ADDR) + l.srai r5,r5,6 + l.ori r5,r5,0x0025 + l.sw 0(r4),r5 + + l.addi r4,r3,MC_TMS(0) + l.movhi r5,hi(FLASH_TMS_VAL) + l.ori r5,r5,lo(FLASH_TMS_VAL) + l.sw 0(r4),r5 + + l.addi r4,r3,MC_BA_MASK + l.addi r5,r0,MC_MASK_VAL + l.sw 0(r4),r5 + + l.addi r4,r3,MC_CSR + l.movhi r5,hi(MC_CSR_VAL) + l.ori r5,r5,lo(MC_CSR_VAL) + l.sw 0(r4),r5 + + l.addi r4,r3,MC_TMS(1) + l.movhi r5,hi(SDRAM_TMS_VAL) + l.ori r5,r5,lo(SDRAM_TMS_VAL) + l.sw 0(r4),r5 + + l.addi r4,r3,MC_CSC(1) + l.movhi r5,hi(SDRAM_BASE_ADDR) + l.srai r5,r5,6 + l.ori r5,r5,0x0411 + l.sw 0(r4),r5 + + l.jr r9 + l.nop + + /* Copy data section */ + l.movhi r3,hi(_src_beg) + l.ori r3,r3,lo(_src_beg) + l.addi r4,r0,0x200 + l.movhi r5,hi(_except_end) + l.ori r5,r5,lo(_except_end) + l.movhi r6,hi(_except_beg) + l.ori r6,r6,lo(_except_beg) + l.sub r5,r6,r5 +1: + l.lwz r6,0(r3) + l.sw 0(r4),r6 + l.addi r3,r3,4 + l.addi r4,r4,4 + l.addi r5,r5,-4 + l.sfgtsi r5,0 + l.bf 1b + l.nop + + l.movhi r4,hi(_dst_beg) + l.ori r4,r4,lo(_dst_beg) + l.movhi r5,hi(_dst_end) + l.ori r5,r5,lo(_dst_end) + l.sub r5,r5,r4 + l.sfeqi r5,0 + l.bf 2f + l.nop +1: + l.lwz r6,0(r3) + l.sw 0(r4),r6 + l.addi r3,r3,4 + l.addi r4,r4,4 + l.addi r5,r5,-4 + l.sfgtsi r5,0 + l.bf 1b + l.nop + +2: + + + l.movhi r2,hi(_reset) + l.ori r2,r2,lo(_reset) + l.jr r2 + l.nop + +/* + * Switch to a new context pointed by _task_context + */ +.global _dispatch +.align 4 +_dispatch: + /* load user task GPRs and PC */ + l.movhi r3,hi(_task_context) + l.addi r3,r0,lo(_task_context) + LOADREGS_N_GO + +.section .except, "ax" + +/* + * Bus Error Exception handler + */ +.org 0x0200 +_buserr: + l.nop + l.sw 0(r0),r3 /* Save r3 */ + PRINTF(r3, _buserr_str) +_hang: + l.j _hang + l.nop + +_buserr_str: + .ascii "Bus error exception.\n\000" + +/* + * External Interrupt Exception handler + */ +.org 0x800 +_extint: + l.nop + l.sw 0(r0),r3 /* Save r3 */ + PRINTF(r3,_extint_str) + l.mfspr r3,r0,SPR_EPCR_BASE /* Get EPCR */ + l.sw 4(r0),r3 /* and save it */ + + /* now save user task context */ + l.movhi r3,hi(_task_context) + l.addi r3,r0,lo(_task_context) + SAVEREGS + + /* set kernel context's PC to kernel's scheduler */ + l.movhi r3,hi(_kernel_context) + l.addi r3,r0,lo(_kernel_context) + SET_CONTEXTPC(r3,_int_main,r4) + + /* load kernel context */ + l.movhi r3,hi(_kernel_context) + l.addi r3,r0,lo(_kernel_context) + LOADREGS + + l.movhi r3,hi(_int_main) + l.addi r3,r0,lo(_int_main) + l.jr r3 + l.nop + +_extint_str: + .ascii "External interrupt exception.\n\000" + +/* + * System Call Exception handler + */ +.org 0x0c00 +_syscall: + l.nop + l.sw 0(r0),r3 /* Save r3 */ + PRINTF(r3,_syscall_str) + l.mfspr r3,r0,SPR_EPCR_BASE /* Get EPCR */ + l.addi r3,r3,4 /* increment because EPCR instruction was already executed */ + l.sw 4(r0),r3 /* and save it */ + + /* now save user task context */ + l.movhi r3,hi(_task_context) + l.addi r3,r0,lo(_task_context) + SAVEREGS + + /* set kernel context's PC to kernel's syscall entry */ + l.movhi r3,hi(_kernel_context) + l.addi r3,r0,lo(_kernel_context) + SET_CONTEXTPC(r3,_kernel_syscall,r4) + + /* load kernel context */ + l.movhi r3,hi(_kernel_context) + l.addi r3,r0,lo(_kernel_context) + LOADREGS_N_GO + +_syscall_str: + .ascii "System call exception.\n\000" + +

except-or32.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: uos.h =================================================================== --- uos.h (nonexistent) +++ uos.h (revision 105) @@ -0,0 +1,84 @@ +/* uos.h. Microkernel header for Or1ksim + + Copyright (C) 2000 Damjan Lampret + Copyright (C) 2010 Embecosm Limited + + Contributor Damjan Lampret + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + +/* ---------------------------------------------------------------------------- + This code is commented throughout for use with Doxygen. + --------------------------------------------------------------------------*/ + +/* This file is part of test microkernel for OpenRISC 1000. */ + +/* Length of the IPC message's useful data. */ +#define MAX_MSGLEN 100 + +/* Number of user tasks in the system. */ +#define MAX_TASKS 8 + +/* Number of IPC messages in the system. */ +#define MAX_MSGS 16 + +/* Number of general purpose registers (not counting r0 and r1). */ +#define GPRS 30 + +/* Size of kernel and user task stacks. Size for individual task. */ +#define STACK_SIZE 2048 + +/* Define this if you want kernel debug output. Note that you must + assemble except_or32.S with KERNEL_OUTPUT defined in Makefile. This + definition is only for main uos.c. */ +#define KERNEL_OUTPUT 0 + +/* Define this if you want task switch at every system call. */ +#define KERNEL_SYSCALL_SCHED 0 + +/* System tick timer period */ +#define TICK_PERIOD 0x500 + +/* Task ID type (if we would have processes then we would call it PID) */ +typedef int tid_t; + +/* System call numbers */ +#define IPC_MSGSND 1 +#define IPC_MSGRCV 2 + +/* Message Control Block structure */ +struct mcb { + char msg[MAX_MSGLEN]; /* Message's data */ + int length; /* Message's length */ + tid_t origin; /* TID of message's origin task */ + struct mcb *next; /* Next message in linked list */ +}; + +/* Task Control Block structure */ +struct tcb { + struct regs { + unsigned long pc; /* Task's PC */ + unsigned long sp; /* Task's stack (r1)*/ + unsigned long gprs[GPRS]; /* Task's GPRs r2-r15 */ + unsigned long sr; /* Task's supervision register */ + } regs; + struct mcb *waiting_msgs; /* Waiting messages */ +}; + +extern void dispatch(); +/* Called by kernel_init to collect all tasks entries. */ +extern void tasks_entries();

uos.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: README =================================================================== --- README (nonexistent) +++ README (revision 105) @@ -0,0 +1,31 @@ + Or1ksim Test Suite: uOS Micro OS + ================================ + +This is the Micro OS (uOS) developed by Damjan Lampret. At present the code +builds, but there is no suitable Or1ksim configuration. + +Jeremy Bennett +19 April 2010 + + +ORIGINAL README +=============== + +This is the Micro OS (uOS) for testing operating system features of OpenRISC +1000 architecture. Specifically non reentrant, preemptive multitasking +microkernel. Purpose of this code is not to be a true operating system but +merely a testbench for testing the architecture, or1ksim and software +development tools (GCC, Binutils, ...). + +This test OS has all necessary exception handlers to handle exceptions. There +are two tasks: one task generates data and passes that data via IPC to the +second task. Second task outputs the data via or1ksim syscall to the +simulator. + +Currently only OR32 is supported (exception handlers are written in +assembly). Tools required to compile sources are the latest or32-coff-gcc, +or32-coff-as and or32-coff-ld. Also make sure you undefine +VIRTUAL_MACHINE_ONLY when compiling or1ksim. + +-- +10/Jun/2000, Damjan Lampret, lampret@opencores.org

README Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property