Subversion Repositories openrisc_2011-10-31

/Makefile.in

/board.h

board.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: support.c =================================================================== --- support.c (nonexistent) +++ support.c (revision 128) @@ -0,0 +1,892 @@ +/* support.c -- Support code for Or1ksim testing. + + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + Copyright (C) 2008, 2010 Embecosm Limited + + Contributor Damjan Lampret + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + +/* ---------------------------------------------------------------------------- + This code is commented throughout for use with Doxygen. + --------------------------------------------------------------------------*/ + +/* Support */ + +#include "spr-defs.h" +#include "support.h" +#include "int.h" + + +/* Forward declarations of interrupt handlers */ +static void excpt_dummy(); +extern void int_main(); + +/* Exception handlers. All are dummy except the interrupt handler */ +unsigned long excpt_buserr = (unsigned long) excpt_dummy; +unsigned long excpt_dpfault = (unsigned long) excpt_dummy; +unsigned long excpt_ipfault = (unsigned long) excpt_dummy; +unsigned long excpt_tick = (unsigned long) excpt_dummy; +unsigned long excpt_align = (unsigned long) excpt_dummy; +unsigned long excpt_illinsn = (unsigned long) excpt_dummy; +unsigned long excpt_int = (unsigned long) int_main; +unsigned long excpt_dtlbmiss = (unsigned long) excpt_dummy; +unsigned long excpt_itlbmiss = (unsigned long) excpt_dummy; +unsigned long excpt_range = (unsigned long) excpt_dummy; +unsigned long excpt_syscall = (unsigned long) excpt_dummy; +unsigned long excpt_break = (unsigned long) excpt_dummy; +unsigned long excpt_trap = (unsigned long) excpt_dummy; + + +/* --------------------------------------------------------------------------*/ +/*!Is a character a decimal digit? + + @param[in] c The character to test + + @return 1 (TRUE) if the character is a decimal digit, 0 (FALSE) + otherwise */ +/* --------------------------------------------------------------------------*/ +static int +is_digit (char c) +{ + return ('0' <= c) && (c <= '9'); + +} /* is_digit () */ + + +/* --------------------------------------------------------------------------*/ +/*!Print a char in a width + + The char is always right justified. + + @param[in] c The character to print + @param[in] width The width to print in + + @return The number of characters actually printed (always width) */ +/* --------------------------------------------------------------------------*/ +static int +printf_char (char c, + int width) +{ + int i; + + /* Spacing */ + for (i = 1; i < width; i++) + { + putchar (' '); + } + + /* The char */ + putchar (c); + + return width; + +} /* printf_char () */ + + +/* --------------------------------------------------------------------------*/ +/*!Convert a digit to a char + + We don't worry about the base. If the value supplied is over 10, we assume + its a letter. + + @param[in] d The digit to convert. + + @return The character representation. */ +/* --------------------------------------------------------------------------*/ +static char +dig2char (int d) +{ + return (d < 10) ? '0' + d : 'a' + d - 10; + +} /* dit2char () */ + + +/* --------------------------------------------------------------------------*/ +/*!Print a number to a base to a string + + The number is unsigned, left justified and null terminated + + @param[in] uval The value to print + @param[in] buf The buffer to print in + @param[in] base The base to use. + + @return the length of the string created. */ +/* --------------------------------------------------------------------------*/ +static int +print_base (long unsigned int uval, + char buf[], + unsigned int base) +{ + /* Initially print backwards. Always have at least a zero. */ + int i = 0; + + do + { + buf[i] = dig2char (uval % base); + uval = uval / base; + i++; + } + while (0 != uval); + + buf[i] = 0; /* End of string */ + + int len = i; /* Length of the string */ + + /* Reverse the string */ + for (i = 0; i < (len / 2); i++) + { + char c = buf[i]; + buf[i] = buf[len - i - 1]; + buf[len - i - 1] = c; + } + + return len; + +} /* print_base () */ + + +/* --------------------------------------------------------------------------*/ +/*!Print a character multiple times + + @param[in] c The char to print + @param[in] num Number of times to print */ +/* --------------------------------------------------------------------------*/ +static void +print_multichar (char c, + int num) +{ + for (; num > 0; num--) + { + putchar (c); + } +} /* print_multichar () */ + + +/* --------------------------------------------------------------------------*/ +/*!Print a string + + @param[in] str The string to print */ +/* --------------------------------------------------------------------------*/ +static void +print_str (char str []) +{ + int i; + + for (i = 0; 0 != str[i]; i++) + { + putchar (str[i]); + } +} /* print_str () */ + + +/* --------------------------------------------------------------------------*/ +/*!Return the length of a string + + @param[in] str The string whose length is wanted + + @return The length of the string */ +/* --------------------------------------------------------------------------*/ +static int +strlen (char str []) +{ + int i; + + for (i = 0; str[i] != 0; i++) + { + } + + return i; + +} /* strlen () */ + + +/* --------------------------------------------------------------------------*/ +/*!Print a string in a width + + @param[in] str The string to print + @param[in] width The width to print it in (at least) + + @return The number of chars printed */ +/* --------------------------------------------------------------------------*/ +static int +printf_str (char str [], + int width) +{ + int len = strlen (str); + + if (width > len) + { + print_multichar (' ', width - len); + } + + print_str (str); + + return (width > len) ? width : len; + +} /* printf_str () */ + + +/* --------------------------------------------------------------------------*/ +/*!Print a decimal in a width + + The number is always right justified and signed. + + @param[in] val The value to print + @param[in] width The width to print in (at least) + @param[in] leading_zeros_p 1 (TRUE) if we should print leading zeros, + 0 (FALSE) otherwise + + @return The number of chars printed */ +/* --------------------------------------------------------------------------*/ +static int +printf_decimal (long int val, + int width, + int leading_zeros_p) +{ + int is_signed_p = 0; + + /* Note if we need a sign */ + if (val < 0) + { + val = -val; + is_signed_p = 1; + } + + /* Array to store the number in. We know the max for 32 bits is 10 + digits. Allow for end of string marker */ + char num_array[11]; + + int num_width = print_base ((unsigned long int) val, num_array, 10); + + /* Now print out the number. */ + num_width += is_signed_p ? 1 : 0; + + if (num_width < width) + { + if (leading_zeros_p) + { + if (is_signed_p) + { + putchar ('-'); + } + + print_multichar ('0', width - num_width); + } + else + { + print_multichar (' ', width - num_width); + + if (is_signed_p) + { + putchar ('-'); + } + } + } + else + { + if (is_signed_p) + { + putchar ('-'); + } + } + + print_str (num_array); + + return width > num_width ? width : num_width; + +} /* printf_decimal () */ + + +/* --------------------------------------------------------------------------*/ +/*!Print a unsigned to a base in a width + + The number is always right justified and unsigned. + + @param[in] val The value to print + @param[in] width The width to print in (at least) + @param[in] leading_zeros_p 1 (TRUE) if we should print leading zeros, + 0 (FALSE) otherwise + @param[in] base Base to use when printing + + @return The number of chars printed */ +/* --------------------------------------------------------------------------*/ +static int +printf_unsigned_base (unsigned long int val, + int width, + int leading_zeros_p, + unsigned int base) +{ + int is_signed_p = 0; + + /* Note if we need a sign */ + if (val < 0) + { + val = -val; + is_signed_p = 1; + } + + /* Array to store the number in. We know the max for 32 bits of octal is 11 + digits. Allow for end of string marker */ + char num_array[12]; + + int num_width = print_base (val, num_array, base); + + /* Now print out the number. */ + num_width += is_signed_p ? 1 : 0; + + if (num_width < width) + { + print_multichar (leading_zeros_p ? '0' : ' ', width - num_width); + } + + print_str (num_array); + + return width > num_width ? width : num_width; + +} /* printf_unsigned_base () */ + + +/* --------------------------------------------------------------------------*/ +/*!Dummy exception handler + + Used for most exceptions as the default hander which does nothing. */ +/* --------------------------------------------------------------------------*/ +static void +excpt_dummy() +{ +} /* excpt_dummy ()*/ + + +/*! Function to be called at entry point - not defined here. */ +extern int main (); + +/* --------------------------------------------------------------------------*/ +/*!Start function + + Called by reset exception handler. */ +/* --------------------------------------------------------------------------*/ +void +reset () +{ + exit (main ()); + +} /* reset () */ + +/* --------------------------------------------------------------------------*/ +/*!Exit function + + Return value by making a syscall + + @param[in] rc Return code */ +/* --------------------------------------------------------------------------*/ +void +exit (int rc) +{ + __asm__ __volatile__ ("l.add r3,r0,%0\n\t" + "l.nop %1": : "r" (rc), "K" (NOP_EXIT)); + + /* Header declares function as __noreturn, so ensure that is so. */ + while (1) + { + } +} /* exit () */ + + +/* --------------------------------------------------------------------------*/ +/*!Activate printing a character in the simulator + + @param[in] c The character to print + + @return The char printed cast to an int */ +/* --------------------------------------------------------------------------*/ +int +putchar (int c) +{ + __asm__ __volatile__ ("l.addi\tr3,%0,0\n\t" + "l.nop %1": : "r" (c), "K" (NOP_PUTC)); + + return c; + +} /* putchar () */ + + +/* --------------------------------------------------------------------------*/ +/*!Print a string + + We need to define this, since the compiler will replace calls to printf + using just constant strings with trailing newlines with calls to puts + without the newline. + + @param[in] str The string to print (without a newline) + + @return The char printed cast to an int */ +/* --------------------------------------------------------------------------*/ +int +puts (const char *str) +{ + return printf ("%s\n", str); + +} /* puts () */ + + +/* --------------------------------------------------------------------------*/ +/*!Activate printf support in simulator + + @note This doesn't actually work, so we implement the basics of printf by + steam, calling useful subsidiary functions based on putchar (), which + does work. + + @param[in] fmt The format string + @param[in] ... The variable arguments if any + + @return The number of characters printed */ +/* --------------------------------------------------------------------------*/ +int +printf(const char *fmt, + ...) +{ + int num_chars = 0; /* How many chars printed */ + + va_list args; + va_start (args, fmt); + + int i; /* Index into the string */ + + for (i = 0; fmt[i] != 0; i++) + { + if ('%' == fmt[i]) + { + int width; + int leading_zeros_p; + + /* Decode the field */ + i++; + + /* Are leading zeros requested? */ + if ('0' == fmt[i]) + { + leading_zeros_p = 1; + i++; + } + else + { + leading_zeros_p = 0; + } + + /* Is there a width specification? */ + width = 0; + + while (is_digit (fmt[i])) + { + width = width * 10 + fmt[i] - '0'; + i++; + } + + /* We just ignore any "l" specification. We do everything as + 32-bit. */ + i += ('l' == fmt[i]) ? 1 : 0; + + /* Deal with each field according to the type indicactor */ + char ch; + char *str; + long int val; + unsigned long int uval; + + /* There is a bug in GCC for OR1K, which can't handle two many + cases. For now we split this into two disjoint case statements. */ + switch (fmt[i]) + { + case 'c': + ch = va_arg (args, int); + num_chars += printf_char (ch, width); + break; + + case 'o': + uval = va_arg (args, unsigned long int); + num_chars +=printf_unsigned_base (uval, width, leading_zeros_p, + 8); + break; + + case 's': + str = va_arg (args, char *); + num_chars += printf_str (str, width); + break; + + case 'x': + uval = va_arg (args, unsigned long int); + num_chars += printf_unsigned_base (uval, width, leading_zeros_p, + 16); + break; + + default: + /* Default is to do nothing silently */ + break; + } + + switch (fmt[i]) + { + case'd': case 'i': + val = va_arg (args, long int); + num_chars += printf_decimal (val, width, leading_zeros_p); + break; + } + } + else + { + putchar (fmt[i]); + num_chars++; + } + } + + va_end (args); + + return num_chars; + +} /* printf () */ + + +/* --------------------------------------------------------------------------*/ +/*!Report a 32-bit value + + Uses the built-in simulator functionality. + + @param[in] value Value to report. */ +/* --------------------------------------------------------------------------*/ +void +report (unsigned long int value) +{ + __asm__ __volatile__ ("l.addi\tr3,%0,0\n\t" + "l.nop %1": : "r" (value), "K" (NOP_REPORT)); + +} /* report () */ + + +/* --------------------------------------------------------------------------*/ +/*!Mutliply two 32-bit values to give a 64-bit result + + This is not supported by the OR1K GCC. + + Use the identity + + (ax + b).(cx + d) = ac.x^2 + (ad + bc).x + bd + + x = 2^16. None of this should overflow. + + @param[in] op1 First operand + @param[in] op2 Second operand + + @return The result */ +/* --------------------------------------------------------------------------*/ +static unsigned long long int +l_mulu (unsigned long int op1, + unsigned long int op2) +{ + unsigned long int a, b, c, d; + + a = op1 >> 16; + b = op1 & 0xffff; + c = op2 >> 16; + d = op2 & 0xffff; + + /* Add in the terms */ + unsigned long long int res; + + /* printf ("a = 0x%08lx, b = 0x%08lx, c = 0x%08lx, d = 0x%08lx\n", a, b, c, d); */ + res = (unsigned long long int) (a * c) << 32; + /* printf (" interim res = 0x%08lx%08lx\n", (unsigned long int) (res >> 32), */ + /* (unsigned long int) res); */ + res += ((unsigned long long int) (a * d) << 16); + /* printf (" interim res = 0x%08lx%08lx\n", (unsigned long int) (res >> 32), */ + /* (unsigned long int) res); */ + res += ((unsigned long long int) (b * c) << 16); + /* printf (" interim res = 0x%08lx%08lx\n", (unsigned long int) (res >> 32), */ + /* (unsigned long int) res); */ + res += (unsigned long long int) (b * d); + /* printf (" interim res = 0x%08lx%08lx\n", (unsigned long int) (res >> 32), */ + /* (unsigned long int) res); */ + + /* printf ("0x%08lx * 0x%08lx = 0x%08lx%08lx\n", op1, op2, */ + /* (unsigned long int) (res >> 32), (unsigned long int) res); */ + + return res; + +} /* l_mulu () */ + + +/* --------------------------------------------------------------------------*/ +/*!Mutliply two 64-bit values + + This is not supported by the OR1K GCC. + + Use the identity + + (ax + b).(cx + d) = ac.x^2 + (ad + bc).x + bd + + x = 2^32. We can discard the first term (overflow), though since this is + for testing we'll print a message. + + The second term may overflow, so we compute the coefficient to 64-bit to + see if we have overflowed. + + The final term may overflow, so we also compute this to 64-bit, so we can + add the top 64-bits in. + + @param[in] op1 First operand + @param[in] op2 Second operand + + @return The result */ +/* --------------------------------------------------------------------------*/ +static unsigned long long int +ll_mulu (unsigned long long int op1, + unsigned long long int op2) +{ + unsigned long int a, b, c, d; + unsigned long long int tmp, res; + + a = op1 >> 32; + b = op1 & 0xffffffff; + c = op2 >> 32; + d = op2 & 0xffffffff; + + if ((a > 0) && (c > 0)) + { + printf ("ll_mulu overflows\n"); + } + + /* Compute and test the second term */ + tmp = l_mulu (a, d); + + if (tmp >= 0x100000000ULL) + { + printf ("ll_mulu overflows\n"); + } + + res = tmp << 32; + + tmp = l_mulu (b, c); + + if (tmp >= 0x100000000ULL) + { + printf ("ll_mulu overflows\n"); + } + + res += tmp << 32; + + /* Compute the third term. Although the term can't overflow, it could + overflow the result. So just check our answer is larger when the final + term is added in. */ + tmp = res; + + res += l_mulu (b, d); + + if (res < tmp) + { + printf ("ll_mulu overflows\n"); + } + + /* printf ("0x%08lx%08lx * 0x%08lx%08lx = 0x%08lx%08lx\n", a, b, c, d, */ + /* (unsigned long int) (res >> 32), (unsigned long int) res); */ + + return res; + +} /* ll_mulu () */ + +/* --------------------------------------------------------------------------*/ +/*!Divide a 64-bit value by a 32 bit value + + Until I can get hold of a copy of Knuth volume 2 to check the algorithm, + this is a bitwise version. + + @param[in] op1 First operand + @param[in] op2 Second operand + + @return The result */ +/* --------------------------------------------------------------------------*/ +static unsigned long long int +ll_divu (unsigned long long int dividend, + unsigned long int divisor) +{ + unsigned long long int t, num_bits; + unsigned long long int q, bit, d; + int i; + + if (divisor == 0) + { + printf ("ERROR: Invalid division by zero\n"); + return 0; + } + + if (divisor > dividend) + { + return 0; + } + + if (divisor == dividend) + { + return 1ULL; + } + + /* printf ("0x%08x%08x / 0x%08x = ", (unsigned int) (dividend >> 32), */ + /* (unsigned int) (dividend & 0xffffffff), (unsigned int) divisor); */ + + num_bits = 64; + + unsigned long long int remainder = 0; + unsigned long long int quotient = 0; + + while (remainder < divisor) + { + bit = (dividend & 0x8000000000000000ULL) >> 63; + remainder = (remainder << 1) | bit; + d = dividend; + dividend = dividend << 1; + num_bits--; + } + + /* The loop, above, always goes one iteration too far. To avoid inserting + an "if" statement inside the loop the last iteration is simply + reversed. */ + dividend = d; + remainder = remainder >> 1; + num_bits++; + + for (i = 0; i < num_bits; i++) + { + bit = (dividend & 0x8000000000000000ULL) >> 63; + remainder = (remainder << 1) | bit; + t = remainder - divisor; + q = !((t & 0x8000000000000000ULL) >> 63); + dividend = dividend << 1; + quotient = (quotient << 1) | q; + + if (q) + { + remainder = t; + } + } + + /* printf ("0x%08x%08x\n", (unsigned int) (quotient >> 32), */ + /* (unsigned int) (quotient & 0xffffffff)); */ + + return quotient; + +} /* ll_divu () */ + +/* --------------------------------------------------------------------------*/ +/*!Read the simulator timer + + Uses the built-in simulator functionality to return the time in + microseconds. + + @note Beware that this timer can wrap around. + + @return The time used since the simulator started. */ +/* --------------------------------------------------------------------------*/ +unsigned long int +read_timer() +{ + unsigned long int cycles_lo; + unsigned long int cycles_hi; + unsigned long int cycle_ps; + unsigned long long int time_us; + + __asm__ __volatile__ ("l.nop\t\t%0" : : "K" (NOP_GET_TICKS)); + __asm__ __volatile__ ("l.add\t\t%0,r0,r11": "=r" (cycles_lo) : ); + __asm__ __volatile__ ("l.add\t\t%0,r0,r12": "=r" (cycles_hi) : ); + __asm__ __volatile__ ("l.nop\t\t%0" : : "K" (NOP_GET_PS)); + __asm__ __volatile__ ("l.add\t\t%0,r0,r11": "=r" (cycle_ps) : ); + + unsigned long long int cycles = ((unsigned long long int) cycles_hi << 32) | + ((unsigned long long int) cycles_lo); + + /* This could overflow 64 bits, but if so then the result would overflow 32 + bits. */ + time_us = ll_mulu (cycles, (unsigned long long int) cycle_ps); + time_us = ll_divu (time_us, 1000000UL); + return (unsigned long int) time_us; + +} /* read_timer () */ + + +/* --------------------------------------------------------------------------*/ +/*!Write a SPR + + @todo Surely the SPR should be a short int, since it is only 16-bits. Left + as is for now due to large amount of user code that might need + changing. + + @param[in] spr The SPR to write + @param[in] value The value to write to the SPR */ +/* --------------------------------------------------------------------------*/ +void +mtspr (unsigned long int spr, + unsigned long int value) +{ + __asm__ __volatile__ ("l.mtspr\t\t%0,%1,0": : "r" (spr), "r" (value)); + +} /* mtspr () */ + + +/* --------------------------------------------------------------------------*/ +/*!Read a SPR + + @todo Surely the SPR should be a short int, since it is only 16-bits. Left + as is for now due to large amount of user code that might need + changing. + + @param[in] spr The SPR to write + + @return The value read from the SPR */ +/* --------------------------------------------------------------------------*/ +unsigned long int +mfspr (unsigned long spr) +{ + unsigned long value; + + __asm__ __volatile__ ("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr)); + + return value; + +} /* mfspr () */ + + +/* --------------------------------------------------------------------------*/ +/*!Copy between regions of memory + + This should match the library version of memcpy + + @param[out] dstvoid Pointer to the destination memory area + @param[in] srcvoid Pointer to the source memory area + @param[in] length Number of bytes to copy. */ +/* --------------------------------------------------------------------------*/ +void * +memcpy (void *__restrict dstvoid, + __const void *__restrict srcvoid, + size_t length) +{ + char *dst = dstvoid; + const char *src = (const char *) srcvoid; + + while (length--) + { + *dst++ = *src++; + } + + return dst; + +} /* memcpy () */

support.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: int.h =================================================================== --- int.h (nonexistent) +++ int.h (revision 128) @@ -0,0 +1,41 @@ +/* int.c -- Header for interrupt handling for Or1ksim tests. + + Copyright (C) 2001 Simon Srot, srot@opencores.org + Copyright (C) 2008, 2010 Embecosm Limited + + Contributor Simon Srot + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + +/* ---------------------------------------------------------------------------- + This code is commented throughout for use with Doxygen. + --------------------------------------------------------------------------*/ + +/* Number of interrupt handlers */ +#define MAX_INT_HANDLERS 32 + +/* Handler entry */ +struct ihnd { + void (*handler)(void *); + void *arg; +}; + +/* Add interrupt handler */ +int int_add(unsigned long vect, void (* handler)(void *), void *arg); + +/* Initialize routine */ +int int_init();

int.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: support.h =================================================================== --- support.h (nonexistent) +++ support.h (revision 128) @@ -0,0 +1,93 @@ +/* support.h Support headers for testing Or1ksim. + + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + Copyright (C) 2010 Embecosm Limited + + Contributor Damjan Lampret + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + +/* ---------------------------------------------------------------------------- + This code is commented throughout for use with Doxygen. + --------------------------------------------------------------------------*/ + +/* This file should is included in each C test. It calls main () function and + add support for basic functions */ + +#ifndef SUPPORT_H +#define SUPPORT_H + +#include +#include +#include + + +/*! Convenience macros for accessing memory. */ +#define REG8(add) *((volatile unsigned char *) (add)) +#define REG16(add) *((volatile unsigned short *) (add)) +#define REG32(add) *((volatile unsigned long *) (add)) + +/* Start function */ +extern void reset (); + +/* Return a value by making a syscall */ +extern void exit (int i) __attribute__ ((__noreturn__)); + +/* Version of putchar that works with Or1ksim */ +extern int putchar (int c); + +/* Version of puts that works with Or1ksim */ +extern int puts (const char *str); + +/* Restricted version of printf that works with Or1ksim */ +extern int printf (const char *fmt, + ...); + +/* Prints out a value */ +extern void report (unsigned long int value); + +/* Read the simulator timer */ +extern unsigned long int read_timer (); + +/* For writing into SPR. */ +extern void mtspr (unsigned long int spr, + unsigned long int value); + +/* For reading SPR. */ +extern unsigned long int mfspr (unsigned long int spr); + +/* memcpy clone */ +extern void *memcpy (void *__restrict __dest, + __const void *__restrict __src, + size_t __n); + +/* Externally used exception handlers */ +extern unsigned long int excpt_buserr; +extern unsigned long int excpt_dpfault; +extern unsigned long int excpt_ipfault; +extern unsigned long int excpt_tick; +extern unsigned long int excpt_align; +extern unsigned long int excpt_illinsn; +extern unsigned long int excpt_int; +extern unsigned long int excpt_dtlbmiss; +extern unsigned long int excpt_itlbmiss; +extern unsigned long int excpt_range; +extern unsigned long int excpt_syscall; +extern unsigned long int excpt_break; +extern unsigned long int excpt_trap; + +#endif

support.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: Makefile.am =================================================================== --- Makefile.am (nonexistent) +++ Makefile.am (revision 128) @@ -0,0 +1,36 @@ +# Makefile.am for or1ksim testsuite support sub-module + +# Copyright (C) Damjan Lampret 1999 +# Copyright (C) Embecosm Limited, 2010 + +# Contributor Jeremy Bennett + +# This file is part of OpenRISC 1000 Architectural Simulator. + +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 3 of the License, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +# You should have received a copy of the GNU General Public License along +# with this program. If not, see . */ + +# ----------------------------------------------------------------------------- +# This code is commented throughout for use with Doxygen. +# ----------------------------------------------------------------------------- + + +# Support library for use when testing +check_LTLIBRARIES = libsupport.la + +libsupport_la_SOURCES = board.h \ + int.c \ + int.h \ + spr-defs.h \ + support.c \ + support.h

Makefile.am Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: spr-defs.h =================================================================== --- spr-defs.h (nonexistent) +++ spr-defs.h (revision 128) @@ -0,0 +1,553 @@ +/* spr_defs.h -- Defines OR1K architecture specific special-purpose registers + + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + Copyright (C) 2008 Embecosm Limited + + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + + +/* Definition of special-purpose registers (SPRs). This is just a copy of + cpu/or1k/spr_defs.h. It really should not be duplicated here. */ + +#define MAX_GRPS (32) +#define MAX_SPRS_PER_GRP_BITS (11) +#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS) +#define MAX_SPRS (0x10000) + +/* Base addresses for the groups */ +#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS) + +/* System control and status group */ +#define SPR_VR (SPRGROUP_SYS + 0) +#define SPR_UPR (SPRGROUP_SYS + 1) +#define SPR_CPUCFGR (SPRGROUP_SYS + 2) +#define SPR_DMMUCFGR (SPRGROUP_SYS + 3) +#define SPR_IMMUCFGR (SPRGROUP_SYS + 4) +#define SPR_DCCFGR (SPRGROUP_SYS + 5) +#define SPR_ICCFGR (SPRGROUP_SYS + 6) +#define SPR_DCFGR (SPRGROUP_SYS + 7) +#define SPR_PCCFGR (SPRGROUP_SYS + 8) +#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */ +#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */ +#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */ +#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */ +#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */ +#define SPR_EEAR_BASE (SPRGROUP_SYS + 48) +#define SPR_EEAR_LAST (SPRGROUP_SYS + 63) +#define SPR_ESR_BASE (SPRGROUP_SYS + 64) +#define SPR_ESR_LAST (SPRGROUP_SYS + 79) + +/* Data MMU group */ +#define SPR_DMMUCR (SPRGROUP_DMMU + 0) +#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) +#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) +#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) +#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) + +/* Instruction MMU group */ +#define SPR_IMMUCR (SPRGROUP_IMMU + 0) +#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) +#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100) +#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100) +#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100) + +/* Data cache group */ +#define SPR_DCCR (SPRGROUP_DC + 0) +#define SPR_DCBPR (SPRGROUP_DC + 1) +#define SPR_DCBFR (SPRGROUP_DC + 2) +#define SPR_DCBIR (SPRGROUP_DC + 3) +#define SPR_DCBWR (SPRGROUP_DC + 4) +#define SPR_DCBLR (SPRGROUP_DC + 5) +#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) +#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) + +/* Instruction cache group */ +#define SPR_ICCR (SPRGROUP_IC + 0) +#define SPR_ICBPR (SPRGROUP_IC + 1) +#define SPR_ICBIR (SPRGROUP_IC + 2) +#define SPR_ICBLR (SPRGROUP_IC + 3) +#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200) +#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200) + +/* MAC group */ +#define SPR_MACLO (SPRGROUP_MAC + 1) +#define SPR_MACHI (SPRGROUP_MAC + 2) + +/* Debug group */ +#define SPR_DVR(N) (SPRGROUP_D + (N)) +#define SPR_DCR(N) (SPRGROUP_D + 8 + (N)) +#define SPR_DMR1 (SPRGROUP_D + 16) +#define SPR_DMR2 (SPRGROUP_D + 17) +#define SPR_DWCR0 (SPRGROUP_D + 18) +#define SPR_DWCR1 (SPRGROUP_D + 19) +#define SPR_DSR (SPRGROUP_D + 20) +#define SPR_DRR (SPRGROUP_D + 21) + +/* Performance counters group */ +#define SPR_PCCR(N) (SPRGROUP_PC + (N)) +#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N)) + +/* Power management group */ +#define SPR_PMR (SPRGROUP_PM + 0) + +/* PIC group */ +#define SPR_PICMR (SPRGROUP_PIC + 0) +#define SPR_PICPR (SPRGROUP_PIC + 1) +#define SPR_PICSR (SPRGROUP_PIC + 2) + +/* Tick Timer group */ +#define SPR_TTMR (SPRGROUP_TT + 0) +#define SPR_TTCR (SPRGROUP_TT + 1) + +/* + * Bit definitions for the Version Register + * + */ +#define SPR_VR_VER 0xffff0000 /* Processor version */ +#define SPR_VR_REV 0x0000003f /* Processor revision */ + +/* + * Bit definitions for the Unit Present Register + * + */ +#define SPR_UPR_UP 0x00000001 /* UPR present */ +#define SPR_UPR_DCP 0x00000002 /* Data cache present */ +#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */ +#define SPR_UPR_DMP 0x00000008 /* Data MMU present */ +#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */ +#define SPR_UPR_MP 0x00000020 /* MAC present */ +#define SPR_UPR_DUP 0x00000040 /* Debug unit present */ +#define SPR_UPR_PCUP 0x00000080 /* Performance counters unit present */ +#define SPR_UPR_PMP 0x00000100 /* Power management present */ +#define SPR_UPR_PICP 0x00000200 /* PIC present */ +#define SPR_UPR_TTP 0x00000400 /* Tick timer present */ +#define SPR_UPR_RES 0x00fe0000 /* Reserved */ +#define SPR_UPR_CUP 0xff000000 /* Context units present */ + +/* + * JPB: Bit definitions for the CPU configuration register + * + */ +#define SPR_CPUCFGR_NSGF 0x0000000f /* Number of shadow GPR files */ +#define SPR_CPUCFGR_CGF 0x00000010 /* Custom GPR file */ +#define SPR_CPUCFGR_OB32S 0x00000020 /* ORBIS32 supported */ +#define SPR_CPUCFGR_OB64S 0x00000040 /* ORBIS64 supported */ +#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */ +#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */ +#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */ +#define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */ + +/* + * JPB: Bit definitions for the Debug configuration register and other + * constants. + * + */ + +#define SPR_DCFGR_NDP 0x00000007 /* Number of matchpoints mask */ +#define SPR_DCFGR_NDP1 0x00000000 /* One matchpoint supported */ +#define SPR_DCFGR_NDP2 0x00000001 /* Two matchpoints supported */ +#define SPR_DCFGR_NDP3 0x00000002 /* Three matchpoints supported */ +#define SPR_DCFGR_NDP4 0x00000003 /* Four matchpoints supported */ +#define SPR_DCFGR_NDP5 0x00000004 /* Five matchpoints supported */ +#define SPR_DCFGR_NDP6 0x00000005 /* Six matchpoints supported */ +#define SPR_DCFGR_NDP7 0x00000006 /* Seven matchpoints supported */ +#define SPR_DCFGR_NDP8 0x00000007 /* Eight matchpoints supported */ +#define SPR_DCFGR_WPCI 0x00000080 /* Watchpoint counters implemented */ + +#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \ + 2 == n ? SPR_DCFGR_NDP2 : \ + 3 == n ? SPR_DCFGR_NDP3 : \ + 4 == n ? SPR_DCFGR_NDP4 : \ + 5 == n ? SPR_DCFGR_NDP5 : \ + 6 == n ? SPR_DCFGR_NDP6 : \ + 7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8) +#define MAX_MATCHPOINTS 8 +#define MAX_WATCHPOINTS (MAX_MATCHPOINTS + 2) + +/* + * Bit definitions for the Supervision Register + * + */ +#define SPR_SR_SM 0x00000001 /* Supervisor Mode */ +#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */ +#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */ +#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */ +#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */ +#define SPR_SR_DME 0x00000020 /* Data MMU Enable */ +#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */ +#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */ +#define SPR_SR_CE 0x00000100 /* CID Enable */ +#define SPR_SR_F 0x00000200 /* Condition Flag */ +#define SPR_SR_CY 0x00000400 /* Carry flag */ +#define SPR_SR_OV 0x00000800 /* Overflow flag */ +#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */ +#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */ +#define SPR_SR_EPH 0x00004000 /* Exception Prefix High */ +#define SPR_SR_FO 0x00008000 /* Fixed one */ +#define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */ +#define SPR_SR_RES 0x0ffe0000 /* Reserved */ +#define SPR_SR_CID 0xf0000000 /* Context ID */ + +/* + * Bit definitions for the Data MMU Control Register + * + */ +#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */ +#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ +#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ +#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ + +/* + * Bit definitions for the Instruction MMU Control Register + * + */ +#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */ +#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ +#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ +#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ + +/* + * Bit definitions for the Data TLB Match Register + * + */ +#define SPR_DTLBMR_V 0x00000001 /* Valid */ +#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ +#define SPR_DTLBMR_CID 0x0000003c /* Context ID */ +#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */ +#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */ + +/* + * Bit definitions for the Data TLB Translate Register + * + */ +#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */ +#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */ +#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */ +#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ +#define SPR_DTLBTR_A 0x00000010 /* Accessed */ +#define SPR_DTLBTR_D 0x00000020 /* Dirty */ +#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */ +#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */ +#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */ +#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */ +#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */ + +/* + * Bit definitions for the Instruction TLB Match Register + * + */ +#define SPR_ITLBMR_V 0x00000001 /* Valid */ +#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ +#define SPR_ITLBMR_CID 0x0000003c /* Context ID */ +#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */ +#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */ + +/* + * Bit definitions for the Instruction TLB Translate Register + * + */ +#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */ +#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */ +#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */ +#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ +#define SPR_ITLBTR_A 0x00000010 /* Accessed */ +#define SPR_ITLBTR_D 0x00000020 /* Dirty */ +#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */ +#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */ +#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */ + +/* + * Bit definitions for Data Cache Control register + * + */ +#define SPR_DCCR_EW 0x000000ff /* Enable ways */ + +/* + * Bit definitions for Insn Cache Control register + * + */ +#define SPR_ICCR_EW 0x000000ff /* Enable ways */ + +/* + * Bit definitions for Data Cache Configuration Register + * + */ + +#define SPR_DCCFGR_NCW 0x00000007 +#define SPR_DCCFGR_NCS 0x00000078 +#define SPR_DCCFGR_CBS 0x00000080 +#define SPR_DCCFGR_CWS 0x00000100 +#define SPR_DCCFGR_CCRI 0x00000200 +#define SPR_DCCFGR_CBIRI 0x00000400 +#define SPR_DCCFGR_CBPRI 0x00000800 +#define SPR_DCCFGR_CBLRI 0x00001000 +#define SPR_DCCFGR_CBFRI 0x00002000 +#define SPR_DCCFGR_CBWBRI 0x00004000 + +/* + * Bit definitions for Instruction Cache Configuration Register + * + */ +#define SPR_ICCFGR_NCW 0x00000007 +#define SPR_ICCFGR_NCS 0x00000078 +#define SPR_ICCFGR_CBS 0x00000080 +#define SPR_ICCFGR_CCRI 0x00000200 +#define SPR_ICCFGR_CBIRI 0x00000400 +#define SPR_ICCFGR_CBPRI 0x00000800 +#define SPR_ICCFGR_CBLRI 0x00001000 + +/* + * Bit definitions for Data MMU Configuration Register + * + */ + +#define SPR_DMMUCFGR_NTW 0x00000003 +#define SPR_DMMUCFGR_NTS 0x0000001C +#define SPR_DMMUCFGR_NAE 0x000000E0 +#define SPR_DMMUCFGR_CRI 0x00000100 +#define SPR_DMMUCFGR_PRI 0x00000200 +#define SPR_DMMUCFGR_TEIRI 0x00000400 +#define SPR_DMMUCFGR_HTR 0x00000800 + +/* + * Bit definitions for Instruction MMU Configuration Register + * + */ + +#define SPR_IMMUCFGR_NTW 0x00000003 +#define SPR_IMMUCFGR_NTS 0x0000001C +#define SPR_IMMUCFGR_NAE 0x000000E0 +#define SPR_IMMUCFGR_CRI 0x00000100 +#define SPR_IMMUCFGR_PRI 0x00000200 +#define SPR_IMMUCFGR_TEIRI 0x00000400 +#define SPR_IMMUCFGR_HTR 0x00000800 + +/* + * Bit definitions for Debug Control registers + * + */ +#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */ +#define SPR_DCR_CC 0x0000000e /* Compare condition */ +#define SPR_DCR_SC 0x00000010 /* Signed compare */ +#define SPR_DCR_CT 0x000000e0 /* Compare to */ + +/* Bit results with SPR_DCR_CC mask */ +#define SPR_DCR_CC_MASKED 0x00000000 +#define SPR_DCR_CC_EQUAL 0x00000002 +#define SPR_DCR_CC_LESS 0x00000004 +#define SPR_DCR_CC_LESSE 0x00000006 +#define SPR_DCR_CC_GREAT 0x00000008 +#define SPR_DCR_CC_GREATE 0x0000000a +#define SPR_DCR_CC_NEQUAL 0x0000000c + +/* Bit results with SPR_DCR_CT mask */ +#define SPR_DCR_CT_DISABLED 0x00000000 +#define SPR_DCR_CT_IFEA 0x00000020 +#define SPR_DCR_CT_LEA 0x00000040 +#define SPR_DCR_CT_SEA 0x00000060 +#define SPR_DCR_CT_LD 0x00000080 +#define SPR_DCR_CT_SD 0x000000a0 +#define SPR_DCR_CT_LSEA 0x000000c0 +#define SPR_DCR_CT_LSD 0x000000e0 +/* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */ + +/* + * Bit definitions for Debug Mode 1 register + * + */ +#define SPR_DMR1_CW 0x000fffff /* Chain register pair data */ +#define SPR_DMR1_CW0_AND 0x00000001 +#define SPR_DMR1_CW0_OR 0x00000002 +#define SPR_DMR1_CW0 (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR) +#define SPR_DMR1_CW1_AND 0x00000004 +#define SPR_DMR1_CW1_OR 0x00000008 +#define SPR_DMR1_CW1 (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR) +#define SPR_DMR1_CW2_AND 0x00000010 +#define SPR_DMR1_CW2_OR 0x00000020 +#define SPR_DMR1_CW2 (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR) +#define SPR_DMR1_CW3_AND 0x00000040 +#define SPR_DMR1_CW3_OR 0x00000080 +#define SPR_DMR1_CW3 (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR) +#define SPR_DMR1_CW4_AND 0x00000100 +#define SPR_DMR1_CW4_OR 0x00000200 +#define SPR_DMR1_CW4 (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR) +#define SPR_DMR1_CW5_AND 0x00000400 +#define SPR_DMR1_CW5_OR 0x00000800 +#define SPR_DMR1_CW5 (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR) +#define SPR_DMR1_CW6_AND 0x00001000 +#define SPR_DMR1_CW6_OR 0x00002000 +#define SPR_DMR1_CW6 (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR) +#define SPR_DMR1_CW7_AND 0x00004000 +#define SPR_DMR1_CW7_OR 0x00008000 +#define SPR_DMR1_CW7 (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR) +#define SPR_DMR1_CW8_AND 0x00010000 +#define SPR_DMR1_CW8_OR 0x00020000 +#define SPR_DMR1_CW8 (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR) +#define SPR_DMR1_CW9_AND 0x00040000 +#define SPR_DMR1_CW9_OR 0x00080000 +#define SPR_DMR1_CW9 (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR) +#define SPR_DMR1_RES1 0x00300000 /* Reserved */ +#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/ +#define SPR_DMR1_BT 0x00800000 /* Branch trace */ +#define SPR_DMR1_RES2 0xff000000 /* Reserved */ + +/* + * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB + * + */ +#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */ +#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */ +#define SPR_DMR2_AWTC 0x00000ffc /* Assign watchpoints to counters */ +#define SPR_DMR2_AWTC_OFF 2 /* Bit offset to AWTC field */ +#define SPR_DMR2_WGB 0x003ff000 /* Watchpoints generating breakpoint */ +#define SPR_DMR2_WGB_OFF 12 /* Bit offset to WGB field */ +#define SPR_DMR2_WBS 0xffc00000 /* JPB: Watchpoint status */ +#define SPR_DMR2_WBS_OFF 22 /* Bit offset to WBS field */ + +/* + * Bit definitions for Debug watchpoint counter registers + * + */ +#define SPR_DWCR_COUNT 0x0000ffff /* Count */ +#define SPR_DWCR_MATCH 0xffff0000 /* Match */ +#define SPR_DWCR_MATCH_OFF 16 /* Match bit offset */ + +/* + * Bit definitions for Debug stop register + * + */ +#define SPR_DSR_RSTE 0x00000001 /* Reset exception */ +#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */ +#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */ +#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */ +#define SPR_DSR_TTE 0x00000010 /* Tick Timer exception */ +#define SPR_DSR_AE 0x00000020 /* Alignment exception */ +#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */ +#define SPR_DSR_IE 0x00000080 /* Interrupt exception */ +#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */ +#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */ +#define SPR_DSR_RE 0x00000400 /* Range exception */ +#define SPR_DSR_SCE 0x00000800 /* System call exception */ +#define SPR_DSR_SSE 0x00001000 /* Single Step Exception */ +#define SPR_DSR_TE 0x00002000 /* Trap exception */ + +/* + * Bit definitions for Debug reason register + * + */ +#define SPR_DRR_RSTE 0x00000001 /* Reset exception */ +#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */ +#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */ +#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */ +#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */ +#define SPR_DRR_AE 0x00000020 /* Alignment exception */ +#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */ +#define SPR_DRR_IE 0x00000080 /* Interrupt exception */ +#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */ +#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */ +#define SPR_DRR_RE 0x00000400 /* Range exception */ +#define SPR_DRR_SCE 0x00000800 /* System call exception */ +#define SPR_DRR_TE 0x00001000 /* Trap exception */ + +/* + * Bit definitions for Performance counters mode registers + * + */ +#define SPR_PCMR_CP 0x00000001 /* Counter present */ +#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */ +#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */ +#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */ +#define SPR_PCMR_LA 0x00000010 /* Load access event */ +#define SPR_PCMR_SA 0x00000020 /* Store access event */ +#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/ +#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */ +#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */ +#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */ +#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */ +#define SPR_PCMR_BS 0x00000800 /* Branch stall event */ +#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */ +#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */ +#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */ +#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */ + +/* + * Bit definitions for the Power management register + * + */ +#define SPR_PMR_SDF 0x0000000f /* Slow down factor */ +#define SPR_PMR_DME 0x00000010 /* Doze mode enable */ +#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */ +#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */ +#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */ + +/* + * Bit definitions for PICMR + * + */ +#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */ + +/* + * Bit definitions for PICPR + * + */ +#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */ + +/* + * Bit definitions for PICSR + * + */ +#define SPR_PICSR_IS 0xffffffff /* Interrupt status */ + +/* + * Bit definitions for Tick Timer Control Register + * + */ +#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */ +#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD +#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */ +#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */ +#define SPR_TTMR_DI 0x00000000 /* Disabled */ +#define SPR_TTMR_RT 0x40000000 /* Restart tick */ +#define SPR_TTMR_SR 0x80000000 /* Single run */ +#define SPR_TTMR_CR 0xc0000000 /* Continuous run */ +#define SPR_TTMR_M 0xc0000000 /* Tick mode */ + +/* + * l.nop constants + * + */ +#define NOP_NOP 0x0000 /* Normal nop instruction */ +#define NOP_EXIT 0x0001 /* End of simulation */ +#define NOP_REPORT 0x0002 /* Simple report */ +/*#define NOP_PRINTF 0x0003 Simprintf instruction now obsolete */ +#define NOP_PUTC 0x0004 /* JPB: Simputc instruction */ +#define NOP_CNT_RESET 0x0005 /* Reset statistics counters */ +#define NOP_GET_TICKS 0x0006 /* JPB: Get # ticks running */ +#define NOP_GET_PS 0x0007 /* JPB: Get picosecs/cycle */ +#define NOP_REPORT_FIRST 0x0400 /* Report with number */ +#define NOP_REPORT_LAST 0x03ff /* Report with number */

spr-defs.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: int.c =================================================================== --- int.c (nonexistent) +++ int.c (revision 128) @@ -0,0 +1,102 @@ +/* int.c -- Interrupt handling for Or1ksim tests. + + Copyright (C) 2001 Simon Srot, srot@opencores.org + Copyright (C) 2008, 2010 Embecosm Limited + + Contributor Simon Srot + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + +/* ---------------------------------------------------------------------------- + This code is commented throughout for use with Doxygen. + --------------------------------------------------------------------------*/ + +/* This file is part of test microkernel for OpenRISC 1000. */ + +#include "support.h" +#include "spr-defs.h" +#include "int.h" + +/* Interrupt handlers table */ +struct ihnd int_handlers[MAX_INT_HANDLERS]; + +/* Initialize routine */ +int int_init() +{ + int i; + + for(i = 0; i < MAX_INT_HANDLERS; i++) { + int_handlers[i].handler = 0; + int_handlers[i].arg = 0; + } + + return 0; +} + +/* Add interrupt handler */ +int int_add(unsigned long vect, void (* handler)(void *), void *arg) +{ + if(vect >= MAX_INT_HANDLERS) + return -1; + + int_handlers[vect].handler = handler; + int_handlers[vect].arg = arg; + + mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect)); + + return 0; +} + +/* Disable interrupt */ +int int_disable(unsigned long vect) +{ + if(vect >= MAX_INT_HANDLERS) + return -1; + + mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << vect)); + + return 0; +} + +/* Enable interrupt */ +int int_enable(unsigned long vect) +{ + if(vect >= MAX_INT_HANDLERS) + return -1; + + mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect)); + + return 0; +} + +/* Main interrupt handler */ +void int_main() +{ + unsigned long picsr = mfspr(SPR_PICSR); + unsigned long i = 0; + + mtspr(SPR_PICSR, 0); + + while(i < 32) { + if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) { + (*int_handlers[i].handler)(int_handlers[i].arg); + mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(0x00000001L << i)); + } + i++; + } +} +

int.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property