Subversion Repositories openrisc_2011-10-31

/Makefile.in

/is-sub-test.S

is-sub-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: is-and-test.S =================================================================== --- is-and-test.S (nonexistent) +++ is-and-test.S (revision 347) @@ -0,0 +1,237 @@ +/* is-and-test.S. l.and and l.andi instruction test of Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * Test coverage + * + * The l.and and l.andi instructions should never set the carry and overflow + * flags. + * + * Problems in this area were reported in Bugs 1782, 1783 and 1784. Having + * fixed the problem, this is (in good software engineering style), a + * regression test to go with the fix. + * + * This is not a comprehensive test of any instruction (yet). + * + * Of course what is really needed is a comprehensive instruction test... + * ------------------------------------------------------------------------- */ + + +#include "inst-set-test.h" + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of bitwise AND in registers + * + * This opcode should never set the flags. Result is compared with the native + * computed value. + * + * Arguments + * op1: First operand value + * op2: Second operand value + * ------------------------------------------------------------------------- */ +#define TEST_AND(op1, op2) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + LOAD_CONST (r6,op2) ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +50: l.and r4,r5,r6 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" & 0x") ;\ + PUTH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (op1 & op2) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, op1 & op2) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 51f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 52f ;\ + l.nop ;\ + ;\ +51: PUTS (" - exception triggered: FALSE\n") ;\ +52: + + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of bitwise AND with an immediate operand + * + * This opcode should never set the flags. Result is compared with the native + * computed value. + * + * Arguments + * op1: First operand value + * op2: Second operand value + * ------------------------------------------------------------------------- */ +#define TEST_ANDI(op1, op2) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +53: l.andi r4,r5,op2 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" & 0x") ;\ + PUTHH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (op1 & op2) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, op1 & op2) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 53b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 54f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 55f ;\ + l.nop ;\ + ;\ +54: PUTS (" - exception triggered: FALSE\n") ;\ +55: + + +/* ---------------------------------------------------------------------------- + * Start of code + * ------------------------------------------------------------------------- */ + .section .text + .global _start +_start: + /* Always set OVE. We should never trigger an exception, even if this + bit is set. */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */ + l.or r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag set **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * Test of and, l.and + * ------------------------------------------------------------------------- */ +_and: + LOAD_STR (r3, "l.and\n") + l.jal _puts + l.nop + + /* Test a range of operands */ + TEST_AND (0x00000000, 0x00000000) + TEST_AND (0xffffffff, 0xffffffff) + TEST_AND (0xaaaaaaaa, 0x00000000) + TEST_AND (0xaaaaaaaa, 0xaaaaaaaa) + TEST_AND (0x55555555, 0x00000000) + TEST_AND (0x55555555, 0x55555555) + TEST_AND (0xaaaaaaaa, 0x55555555) + TEST_AND (0x4c70f07c, 0xb38f0f83) + TEST_AND (0x4c70f07c, 0xc4c70f07) + TEST_AND (0xb38f0f83, 0x38f0f83b) + +/* ---------------------------------------------------------------------------- + * Test of and with immediate half word, l.andi + * ------------------------------------------------------------------------- */ +_andi: + LOAD_STR (r3, "l.andi\n") + l.jal _puts + l.nop + + /* Test a range of operands */ + TEST_ANDI (0x00000000, 0x0000) + TEST_ANDI (0xffffffff, 0xffff) + TEST_ANDI (0xaaaaaaaa, 0x0000) + TEST_ANDI (0xaaaaaaaa, 0xaaaa) + TEST_ANDI (0x55555555, 0x0000) + TEST_ANDI (0x55555555, 0x5555) + TEST_ANDI (0xaaaaaaaa, 0x5555) + TEST_ANDI (0x4c70f07c, 0x0f83) + TEST_ANDI (0x4c70f07c, 0x0f07) + TEST_ANDI (0xb38f0f83, 0xf83b) + +/* ---------------------------------------------------------------------------- + * All done + * ------------------------------------------------------------------------- */ +_exit: + LOAD_STR (r3, "Test completed\n") + l.jal _puts + l.nop + + TEST_EXIT

is-and-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: is-xor-test.S =================================================================== --- is-xor-test.S (nonexistent) +++ is-xor-test.S (revision 347) @@ -0,0 +1,256 @@ +/* is-xor-test.S. l.xor and l.xori instruction test of Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * Test coverage + * + * The l.xor and l.xori instructions should never set the carry and overflow + * flags. + * + * Problems in this area were reported in Bugs 1782, 1783 and 1784. Having + * fixed the problem, this is (in good software engineering style), a + * regression test to go with the fix. + * + * This is not a comprehensive test of any instruction (yet). + * + * Of course what is really needed is a comprehensive instruction test... + * ------------------------------------------------------------------------- */ + + +#include "inst-set-test.h" + +/* A macro to sign extend a 16-bit value */ +#define SE(v) (v | ((v & 0x8000) << 1) | \ + ((v & 0x8000) << 2) | \ + ((v & 0x8000) << 3) | \ + ((v & 0x8000) << 4) | \ + ((v & 0x8000) << 5) | \ + ((v & 0x8000) << 6) | \ + ((v & 0x8000) << 7) | \ + ((v & 0x8000) << 8) | \ + ((v & 0x8000) << 9) | \ + ((v & 0x8000) << 10) | \ + ((v & 0x8000) << 11) | \ + ((v & 0x8000) << 12) | \ + ((v & 0x8000) << 13) | \ + ((v & 0x8000) << 14) | \ + ((v & 0x8000) << 15) | \ + ((v & 0x8000) << 16) ) + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of bitwise XOR in registers + * + * This opcode should never set the flags. Result is compared with the native + * computed value. + * + * Arguments + * op1: First operand value + * op2: Second operand value + * ------------------------------------------------------------------------- */ +#define TEST_XOR(op1, op2) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + LOAD_CONST (r6,op2) ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +50: l.xor r4,r5,r6 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" ^ 0x") ;\ + PUTH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (op1 ^ op2) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, op1 ^ op2) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 51f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 52f ;\ + l.nop ;\ + ;\ +51: PUTS (" - exception triggered: FALSE\n") ;\ +52: + + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of bitwise XOR with an immediate operand + * + * This opcode should never set the flags. Result is compared with the native + * computed value. Note that the OR1K architecture specfies that the immediate + * operand is sign-extended, not zero-extended. + * + * Arguments + * op1: First operand value + * op2: Second operand value + * ------------------------------------------------------------------------- */ +#define TEST_XORI(op1, op2) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +53: l.xori r4,r5,op2 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" ^ 0x") ;\ + PUTHH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (op1 ^ SE (op2)) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, op1 ^ SE (op2)) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 53b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 54f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 55f ;\ + l.nop ;\ + ;\ +54: PUTS (" - exception triggered: FALSE\n") ;\ +55: + + +/* ---------------------------------------------------------------------------- + * Start of code + * ------------------------------------------------------------------------- */ + .section .text + .global _start +_start: + /* Always set OVE. We should never trigger an exception, even if this + bit is set. */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */ + l.or r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag set **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * Test of xor, l.xor + * ------------------------------------------------------------------------- */ +_xor: + LOAD_STR (r3, "l.xor\n") + l.jal _puts + l.nop + + /* Test a range of operands */ + TEST_XOR (0x00000000, 0x00000000) + TEST_XOR (0xffffffff, 0xffffffff) + TEST_XOR (0xaaaaaaaa, 0x00000000) + TEST_XOR (0xaaaaaaaa, 0xaaaaaaaa) + TEST_XOR (0x55555555, 0x00000000) + TEST_XOR (0x55555555, 0x55555555) + TEST_XOR (0xaaaaaaaa, 0x55555555) + TEST_XOR (0x4c70f07c, 0xb38f0f83) + TEST_XOR (0x4c70f07c, 0xc4c70f07) + TEST_XOR (0xb38f0f83, 0x38f0f83b) + +/* ---------------------------------------------------------------------------- + * Test of xor with immediate half word, l.xori + * ------------------------------------------------------------------------- */ +_xori: + LOAD_STR (r3, "l.xori\n") + l.jal _puts + l.nop + + /* Test a range of operands */ + TEST_XORI (0x00000000, 0x0000) + TEST_XORI (0xffffffff, 0xffff) + TEST_XORI (0xaaaaaaaa, 0x0000) + TEST_XORI (0xaaaaaaaa, 0xaaaa) + TEST_XORI (0x55555555, 0x0000) + TEST_XORI (0x55555555, 0x5555) + TEST_XORI (0xaaaaaaaa, 0x5555) + TEST_XORI (0x4c70f07c, 0x0f83) + TEST_XORI (0x4c70f07c, 0x0f07) + TEST_XORI (0xb38f0f83, 0xf83b) + +/* ---------------------------------------------------------------------------- + * All done + * ------------------------------------------------------------------------- */ +_exit: + LOAD_STR (r3, "Test completed\n") + l.jal _puts + l.nop + + TEST_EXIT

is-xor-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: is-shift-test.S =================================================================== --- is-shift-test.S (nonexistent) +++ is-shift-test.S (revision 347) @@ -0,0 +1,378 @@ +/* is-shift-test.S. shift instructions test of Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * Test coverage + * + * The shift instructions should never set the carry and overflow flags. + * + * Problems in this area were reported in Bugs 1782, 1783 and 1784. Having + * fixed the problem, this is (in good software engineering style), a + * regression test to go with the fix. + * + * This is not a comprehensive test of any instruction (yet). + * + * Of course what is really needed is a comprehensive instruction test... + * ------------------------------------------------------------------------- */ + + +#include "inst-set-test.h" + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of shift in registers + * + * This opcode should never set the flags. + * + * Arguments + * opc: The operand + * op1: First operand value + * op2: Second operand value + * res: The expected result + * ------------------------------------------------------------------------- */ +#define TEST_SHIFT(opc, op1, op2, res) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + LOAD_CONST (r6,op2) ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +50: opc r4,r5,r6 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" shifted by 0x") ;\ + PUTH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (res) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, res) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 51f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 52f ;\ + l.nop ;\ + ;\ +51: PUTS (" - exception triggered: FALSE\n") ;\ +52: + + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of shift with an immediate operand + * + * This opcode should never set the flags. + * + * Arguments + * opc: The operand + * op1: First operand value + * op2: Second operand value + * res: The expected result + * ------------------------------------------------------------------------- */ +#define TEST_SHIFTI(opc, op1, op2, res) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +53: opc r4,r5,op2 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" shifted by 0x") ;\ + PUTHH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (res) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, res) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 53b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 54f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 55f ;\ + l.nop ;\ + ;\ +54: PUTS (" - exception triggered: FALSE\n") ;\ +55: + + +/* ---------------------------------------------------------------------------- + * Start of code + * ------------------------------------------------------------------------- */ + .section .text + .global _start +_start: + /* Always set OVE. We should never trigger an exception, even if this + bit is set. */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */ + l.or r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag set **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * Test of shift left logical, l.sll + * ------------------------------------------------------------------------- */ +_sll: + LOAD_STR (r3, "l.sll\n") + l.jal _puts + l.nop + + /* Shift left by zero. */ + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00000000, 0xb38f0f83) + + /* Shift left by amounts in the 1-31 range */ + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00000001, 0x671e1f06) + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00000004, 0x38f0f830) + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00000010, 0x0f830000) + TEST_SHIFT (l.sll, 0xb38f0f83, 0x0000001f, 0x80000000) + + /* Shift left by larger amounts - should be masked. */ + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00000021, 0x671e1f06) + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00002224, 0x38f0f830) + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00f789f0, 0x0f830000) + TEST_SHIFT (l.sll, 0xb38f0f83, 0xffffffff, 0x80000000) + +/* ---------------------------------------------------------------------------- + * Test of shift left logical with immediate, l.slli + * ------------------------------------------------------------------------- */ +_slli: + LOAD_STR (r3, "l.slli\n") + l.jal _puts + l.nop + + /* Shift left by zero. */ + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0000, 0xb38f0f83) + + /* Shift left by amounts in the 1-31 range */ + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0001, 0x671e1f06) + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0004, 0x38f0f830) + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0010, 0x0f830000) + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x001f, 0x80000000) + + /* Shift left by larger amounts - should be masked. */ + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0021, 0x671e1f06) + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0024, 0x38f0f830) + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0030, 0x0f830000) + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x003f, 0x80000000) + +/* ---------------------------------------------------------------------------- + * Test of shift right arithmetic, l.sra + * ------------------------------------------------------------------------- */ +_sra: + LOAD_STR (r3, "l.sra\n") + l.jal _puts + l.nop + + /* Shift right by zero. */ + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00000000, 0xb38f0f83) + + /* Shift right by amounts in the 1-31 range */ + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00000001, 0xd9c787c1) + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00000004, 0xfb38f0f8) + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00000010, 0xffffb38f) + TEST_SHIFT (l.sra, 0xb38f0f83, 0x0000001f, 0xffffffff) + + TEST_SHIFT (l.sra, 0x4c70f07c, 0x00000001, 0x2638783e) + TEST_SHIFT (l.sra, 0x4c70f07c, 0x00000004, 0x04c70f07) + TEST_SHIFT (l.sra, 0x4c70f07c, 0x00000010, 0x00004c70) + TEST_SHIFT (l.sra, 0x4c70f07c, 0x0000001f, 0x00000000) + + /* Shift right by larger amounts - should be masked. */ + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00000021, 0xd9c787c1) + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00002224, 0xfb38f0f8) + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00f789f0, 0xffffb38f) + TEST_SHIFT (l.sra, 0xb38f0f83, 0xffffffff, 0xffffffff) + + TEST_SHIFT (l.sra, 0x4c70f07c, 0x00000021, 0x2638783e) + TEST_SHIFT (l.sra, 0x4c70f07c, 0x00002224, 0x04c70f07) + TEST_SHIFT (l.sra, 0x4c70f07c, 0x00f789f0, 0x00004c70) + TEST_SHIFT (l.sra, 0x4c70f07c, 0xffffffff, 0x00000000) + + +/* ---------------------------------------------------------------------------- + * Test of shift right arithmetic with immediate, l.srai + * ------------------------------------------------------------------------- */ +_srai: + LOAD_STR (r3, "l.srai\n") + l.jal _puts + l.nop + + /* Shift right by zero. */ + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0000, 0xb38f0f83) + + /* Shift right by amounts in the 1-31 range */ + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0001, 0xd9c787c1) + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0004, 0xfb38f0f8) + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0010, 0xffffb38f) + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x001f, 0xffffffff) + + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x0001, 0x2638783e) + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x0004, 0x04c70f07) + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x0010, 0x00004c70) + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x001f, 0x00000000) + + /* Shift right by larger amounts - should be masked. */ + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0021, 0xd9c787c1) + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0024, 0xfb38f0f8) + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0030, 0xffffb38f) + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x003f, 0xffffffff) + + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x0021, 0x2638783e) + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x0024, 0x04c70f07) + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x0030, 0x00004c70) + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x003f, 0x00000000) + +/* ---------------------------------------------------------------------------- + * Test of shift right logical, l.srl + * ------------------------------------------------------------------------- */ +_srl: + LOAD_STR (r3, "l.srl\n") + l.jal _puts + l.nop + + /* Shift right by zero. */ + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00000000, 0xb38f0f83) + + /* Shift right by amounts in the 1-31 range */ + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00000001, 0x59c787c1) + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00000004, 0x0b38f0f8) + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00000010, 0x0000b38f) + TEST_SHIFT (l.srl, 0xb38f0f83, 0x0000001f, 0x00000001) + + TEST_SHIFT (l.srl, 0x4c70f07c, 0x00000001, 0x2638783e) + TEST_SHIFT (l.srl, 0x4c70f07c, 0x00000004, 0x04c70f07) + TEST_SHIFT (l.srl, 0x4c70f07c, 0x00000010, 0x00004c70) + TEST_SHIFT (l.srl, 0x4c70f07c, 0x0000001f, 0x00000000) + + /* Shift right by larger amounts - should be masked. */ + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00000021, 0x59c787c1) + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00002224, 0x0b38f0f8) + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00f789f0, 0x0000b38f) + TEST_SHIFT (l.srl, 0xb38f0f83, 0xffffffff, 0x00000001) + + TEST_SHIFT (l.srl, 0x4c70f07c, 0x00000021, 0x2638783e) + TEST_SHIFT (l.srl, 0x4c70f07c, 0x00002224, 0x04c70f07) + TEST_SHIFT (l.srl, 0x4c70f07c, 0x00f789f0, 0x00004c70) + TEST_SHIFT (l.srl, 0x4c70f07c, 0xffffffff, 0x00000000) + + +/* ---------------------------------------------------------------------------- + * Test of shift right logical with immediate, l.srli + * ------------------------------------------------------------------------- */ +_srli: + LOAD_STR (r3, "l.srli\n") + l.jal _puts + l.nop + + /* Shift right by zero. */ + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0000, 0xb38f0f83) + + /* Shift right by amounts in the 1-31 range */ + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0001, 0x59c787c1) + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0004, 0x0b38f0f8) + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0010, 0x0000b38f) + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x001f, 0x00000001) + + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x0001, 0x2638783e) + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x0004, 0x04c70f07) + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x0010, 0x00004c70) + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x001f, 0x00000000) + + /* Shift right by larger amounts - should be masked. */ + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0021, 0x59c787c1) + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0024, 0x0b38f0f8) + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0030, 0x0000b38f) + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x003f, 0x00000001) + + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x0021, 0x2638783e) + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x0024, 0x04c70f07) + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x0030, 0x00004c70) + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x003f, 0x00000000) + +/* ---------------------------------------------------------------------------- + * All done + * ------------------------------------------------------------------------- */ +_exit: + LOAD_STR (r3, "Test completed\n") + l.jal _puts + l.nop + + TEST_EXIT

is-shift-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: is-or-test.S =================================================================== --- is-or-test.S (nonexistent) +++ is-or-test.S (revision 347) @@ -0,0 +1,237 @@ +/* is-or-test.S. l.or and l.ori instruction test of Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * Test coverage + * + * The l.or and l.ori instructions should never set the carry and overflow + * flags. + * + * Problems in this area were reported in Bugs 1782, 1783 and 1784. Having + * fixed the problem, this is (in good software engineering style), a + * regression test to go with the fix. + * + * This is not a comprehensive test of any instruction (yet). + * + * Of course what is really needed is a comprehensive instruction test... + * ------------------------------------------------------------------------- */ + + +#include "inst-set-test.h" + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of bitwise OR in registers + * + * This opcode should never set the flags. Result is compared with the native + * computed value. + * + * Arguments + * op1: First operand value + * op2: Second operand value + * ------------------------------------------------------------------------- */ +#define TEST_OR(op1, op2) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + LOAD_CONST (r6,op2) ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +50: l.or r4,r5,r6 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" | 0x") ;\ + PUTH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (op1 | op2) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, op1 | op2) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 51f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 52f ;\ + l.nop ;\ + ;\ +51: PUTS (" - exception triggered: FALSE\n") ;\ +52: + + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of bitwise OR with an immediate operand + * + * This opcode should never set the flags. Result is compared with the native + * computed value. + * + * Arguments + * op1: First operand value + * op2: Second operand value + * ------------------------------------------------------------------------- */ +#define TEST_ORI(op1, op2) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +53: l.ori r4,r5,op2 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" | 0x") ;\ + PUTHH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (op1 | op2) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, op1 | op2) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 53b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 54f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 55f ;\ + l.nop ;\ + ;\ +54: PUTS (" - exception triggered: FALSE\n") ;\ +55: + + +/* ---------------------------------------------------------------------------- + * Start of code + * ------------------------------------------------------------------------- */ + .section .text + .global _start +_start: + /* Always set OVE. We should never trigger an exception, even if this + bit is set. */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */ + l.or r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag set **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * Test of or, l.or + * ------------------------------------------------------------------------- */ +_or: + LOAD_STR (r3, "l.or\n") + l.jal _puts + l.nop + + /* Test a range of operands */ + TEST_OR (0x00000000, 0x00000000) + TEST_OR (0xffffffff, 0xffffffff) + TEST_OR (0xaaaaaaaa, 0x00000000) + TEST_OR (0xaaaaaaaa, 0xaaaaaaaa) + TEST_OR (0x55555555, 0x00000000) + TEST_OR (0x55555555, 0x55555555) + TEST_OR (0xaaaaaaaa, 0x55555555) + TEST_OR (0x4c70f07c, 0xb38f0f83) + TEST_OR (0x4c70f07c, 0xc4c70f07) + TEST_OR (0xb38f0f83, 0x38f0f83b) + +/* ---------------------------------------------------------------------------- + * Test of or with immediate half word, l.ori + * ------------------------------------------------------------------------- */ +_ori: + LOAD_STR (r3, "l.ori\n") + l.jal _puts + l.nop + + /* Test a range of operands */ + TEST_ORI (0x00000000, 0x0000) + TEST_ORI (0xffffffff, 0xffff) + TEST_ORI (0xaaaaaaaa, 0x0000) + TEST_ORI (0xaaaaaaaa, 0xaaaa) + TEST_ORI (0x55555555, 0x0000) + TEST_ORI (0x55555555, 0x5555) + TEST_ORI (0xaaaaaaaa, 0x5555) + TEST_ORI (0x4c70f07c, 0x0f83) + TEST_ORI (0x4c70f07c, 0x0f07) + TEST_ORI (0xb38f0f83, 0xf83b) + +/* ---------------------------------------------------------------------------- + * All done + * ------------------------------------------------------------------------- */ +_exit: + LOAD_STR (r3, "Test completed\n") + l.jal _puts + l.nop + + TEST_EXIT

is-or-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: Makefile.am =================================================================== --- Makefile.am (nonexistent) +++ Makefile.am (revision 347) @@ -0,0 +1,137 @@ +# Makefile.am for or1ksim instruction set test programs: + +# Copyright (C) Embecosm Limited, 2010 + +# Contributor Jeremy Bennett + +# This file is part of OpenRISC 1000 Architectural Simulator. + +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 3 of the License, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +# You should have received a copy of the GNU General Public License along +# with this program. If not, see . */ + +# ----------------------------------------------------------------------------- +# This code is commented throughout for use with Doxygen. +# ----------------------------------------------------------------------------- + + +# Tests of the instruction set. Broken out into separate tests, to avoid them +# getting too large. The original instruction set test is still here, but not +# built by default. +EXTRA_DIST = inst-set-test.ld + +if BUILD_ALL_TESTS +INST_SET_TEST_OLD = inst-set-test-old +else +INST_SET_TEST_OLD = +endif + +# Support library for use when testing the instruction set. +check_LTLIBRARIES = libinst-set-test.la + +libinst_set_test_la_SOURCES = inst-set-test.S + +# The test programs +check_PROGRAMS = is-add-test \ + is-and-test \ + is-div-test \ + is-find-test \ + is-jump-test \ + is-lws-test \ + is-mac-test \ + is-mul-test \ + is-or-test \ + is-ror-test \ + is-shift-test \ + is-spr-test \ + is-sub-test \ + is-xor-test \ + $(INST_SET_TEST_OLD) + +# The new instruction set tests. +is_add_test_SOURCES = inst-set-test.h \ + is-add-test.S +is_add_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_add_test_LDADD = inst-set-test.lo + +is_and_test_SOURCES = inst-set-test.h \ + is-and-test.S +is_and_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_and_test_LDADD = inst-set-test.lo + +is_div_test_SOURCES = inst-set-test.h \ + is-div-test.S +is_div_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_div_test_LDADD = inst-set-test.lo + +is_find_test_SOURCES = inst-set-test.h \ + is-find-test.S +is_find_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_find_test_LDADD = inst-set-test.lo + +is_jump_test_SOURCES = inst-set-test.h \ + is-jump-test.S +is_jump_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_jump_test_LDADD = inst-set-test.lo + +is_lws_test_SOURCES = inst-set-test.h \ + is-lws-test.S +is_lws_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_lws_test_LDADD = inst-set-test.lo + +is_mac_test_SOURCES = inst-set-test.h \ + is-mac-test.S +is_mac_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_mac_test_LDADD = inst-set-test.lo + +is_mul_test_SOURCES = inst-set-test.h \ + is-mul-test.S +is_mul_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_mul_test_LDADD = inst-set-test.lo + +is_or_test_SOURCES = inst-set-test.h \ + is-or-test.S +is_or_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_or_test_LDADD = inst-set-test.lo + +is_ror_test_SOURCES = inst-set-test.h \ + is-ror-test.S +is_ror_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_ror_test_LDADD = inst-set-test.lo + +is_shift_test_SOURCES = inst-set-test.h \ + is-shift-test.S +is_shift_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_shift_test_LDADD = inst-set-test.lo + +is_spr_test_SOURCES = inst-set-test.h \ + is-spr-test.S +is_spr_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_spr_test_LDADD = inst-set-test.lo + +is_sub_test_SOURCES = inst-set-test.h \ + is-sub-test.S +is_sub_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_sub_test_LDADD = inst-set-test.lo + +is_xor_test_SOURCES = inst-set-test.h \ + is-xor-test.S +is_xor_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_xor_test_LDADD = inst-set-test.lo + +# The old test which builds with warnings and runs with errors +inst_set_test_old_SOURCES = inst-set-test-old.c + +inst_set_test_old_LDFLAGS = -T$(srcdir)/../default.ld + +inst_set_test_old_LDADD = ../except/except.lo \ + ../support/libsupport.la

Makefile.am Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: is-spr-test.S =================================================================== --- is-spr-test.S (nonexistent) +++ is-spr-test.S (revision 347) @@ -0,0 +1,212 @@ +/* is-spr-test.S. l.mfspr and l.mtspr instruction test of Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * Test coverage + * + * The l.mfspr and l.mtspr should OR the immdediate operand with the register + * to determine the SPR address, not add it (Bug 1779). + * + * Having fixed the problem, this is (in good software engineering style), a + * regresison test to go with the fix. + * + * This is not a comprehensive test of either instruction (yet). + * + * Of course what is really needed is a comprehensive instruction test... + * ------------------------------------------------------------------------- */ + + +#include "inst-set-test.h" + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of l.mfspr + * + * MACLO is used as the SPR, since it can be read and cleared using l.macrc + * and can be set using l.maci. op1 and op2 should be chosen to address this + * register. + * + * The value placed in the register is entirely arbitrary - we use 0xdeadbeef. + * + * Arguments + * op1: First l.mfspr operand value + * op2: Second l.mfspr operand value + * ------------------------------------------------------------------------- */ +#define TEST_MFSPR(op1, op2) \ + l.macrc r2 ;\ + LOAD_CONST (r2,0xdeadbeef) ;\ + l.maci r2,1 ;\ + ;\ + l.mfspr r3,r0,SPR_SR ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 /* Clear flags */ ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* First operand in register */ ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +50: l.mfspr r4,r5,op2 ;\ + l.mfspr r2,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r2) /* Save EPCR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" l.mfspr 0x") ;\ + PUTH (op1) ;\ + PUTS (" | 0x") ;\ + PUTHH (op2) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, 0xdeadbeef) ;\ + ;\ + LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 51f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 52f ;\ + l.nop ;\ + ;\ +51: PUTS (" - exception triggered: FALSE\n") ;\ +52: + + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of l.mtspr + * + * MACLO is used as the SPR, since it can be read and cleared using l.macrc. + * op1 and op2 should be chosen to address this register. + * + * The value placed in the register is entirely arbitrary - we use 0xdeadbeef. + * + * Arguments + * op1: First l.mfspr operand value + * op2: Second l.mfspr operand value + * ------------------------------------------------------------------------- */ +#define TEST_MTSPR(op1, op2) \ + l.macrc r2 ;\ + ;\ + l.mfspr r3,r0,SPR_SR ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 /* Clear flags */ ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* First operand in register */ ;\ + LOAD_CONST (r4,0xdeadbeef) /* First operand in register */ ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +50: l.mtspr r5,r4,op2 ;\ + l.mfspr r2,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r2) /* Save EPCR for later */ ;\ + l.macrc r4 ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" l.mtspr 0x") ;\ + PUTH (op1) ;\ + PUTS (" | 0x") ;\ + PUTHH (op2) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, 0xdeadbeef) ;\ + ;\ + LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 51f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 52f ;\ + l.nop ;\ + ;\ +51: PUTS (" - exception triggered: FALSE\n") ;\ +52: + + +/* ---------------------------------------------------------------------------- + * Start of code + * ------------------------------------------------------------------------- */ + .section .text + .global _start +_start: + +/* ---------------------------------------------------------------------------- + * Test of move from SPR, l.mfspr + * + * MACLO (0x2801) is always used as the test register. + * ------------------------------------------------------------------------- */ +_mfspr: + LOAD_STR (r3, "l.mfspr\n") + l.jal _puts + l.nop + + /* Move a test value using zero in the register */ + TEST_MFSPR (0x00000000, 0x2801) + + /* Move a test value using zero as the constant */ + TEST_MFSPR (0x00002801, 0x0000) + + /* Move a test value using non-zero in both register and constant. + Some of these values will not give the correct result if OR rather + than ADD is used to determine the SPR address */ + TEST_MFSPR (0x00002801, 0x2801) + TEST_MFSPR (0x00000801, 0x2000) + TEST_MFSPR (0x00002000, 0x0801) + TEST_MFSPR (0x00002801, 0x0001) + TEST_MFSPR (0x00000800, 0x2801) + +/* ---------------------------------------------------------------------------- + * Test of move to SPR, l.mtspr + * + * MACLO (0x2801) is always used as the test register. + * ------------------------------------------------------------------------- */ +_mtspr: + LOAD_STR (r3, "l.mtspr\n") + l.jal _puts + l.nop + + /* Move a test value using zero in the register */ + TEST_MTSPR (0x00000000, 0x2801) + + /* Move a test value using zero as the constant */ + TEST_MTSPR (0x00002801, 0x0000) + + /* Move a test value using non-zero in both register and constant. + Some of these values will not give the correct result if OR rather + than ADD is used to determine the SPR address */ + TEST_MTSPR (0x00002801, 0x2801) + TEST_MTSPR (0x00000801, 0x2000) + TEST_MTSPR (0x00002000, 0x0801) + TEST_MTSPR (0x00002801, 0x0001) + TEST_MTSPR (0x00000800, 0x2801) + +/* ---------------------------------------------------------------------------- + * All done + * ------------------------------------------------------------------------- */ +_exit: + LOAD_STR (r3, "Test completed\n") + l.jal _puts + l.nop + + TEST_EXIT

is-spr-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: is-ror-test.S =================================================================== --- is-ror-test.S (nonexistent) +++ is-ror-test.S (revision 347) @@ -0,0 +1,189 @@ +/* is-div-test.S. l.div and l.divu instruction test of Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * Test coverage + * + * The l.ror and l.rori instructions were missing from Or1ksim. + * + * Having fixed the problem, this is (in good software engineering style), a + * regresison test to go with the fix. + * + * This is not a comprehensive test of either instruction (yet). + * + * Of course what is really needed is a comprehensive instruction test... + * ------------------------------------------------------------------------- */ + + +#include "inst-set-test.h" + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of rotate right + * + * Arguments + * op1: First operand value + * op2: Second operand value + * res: Expected result + * ------------------------------------------------------------------------- */ +#define TEST_ROR(op1, op2, res) \ + LOAD_CONST (r5,op1) /* Load numbers to rotate */ ;\ + LOAD_CONST (r6,op2) ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +50: l.ror r4,r5,r6 ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" ROR 0x") ;\ + PUTH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (res) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, res) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 51f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 52f ;\ + l.nop ;\ + ;\ +51: PUTS (" - exception triggered: FALSE\n") ;\ +52: + + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of rotate right immediate + * + * Arguments + * op1: First operand value + * op2: Second operand value + * res: Expected result + * ------------------------------------------------------------------------- */ +#define TEST_RORI(op1, op2, res) \ + LOAD_CONST (r5,op1) /* Load numbers to rotate */ ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +53: l.rori r4,r5,op2 ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" RORI 0x") ;\ + PUTHQ (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (res) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, res) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 53b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 54f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 55f ;\ + l.nop ;\ + ;\ +54: PUTS (" - exception triggered: FALSE\n") ;\ +55: + + +/* ---------------------------------------------------------------------------- + * Start of code + * ------------------------------------------------------------------------- */ + .section .text + .global _start +_start: + +/* ---------------------------------------------------------------------------- + * Test of rotate right, l.ror + * ------------------------------------------------------------------------- */ +_ror: + LOAD_STR (r3, "l.ror\n") + l.jal _puts + l.nop + + /* Rotate by zero */ + TEST_ROR (0xb38f0f83, 0x00000000, 0xb38f0f83) + + /* Rotate by amounts in the 1 - 31 range. */ + TEST_ROR (0xb38f0f83, 0x00000001, 0xd9c787c1) + TEST_ROR (0xb38f0f83, 0x00000004, 0x3b38f0f8) + TEST_ROR (0xb38f0f83, 0x00000010, 0x0f83b38f) + TEST_ROR (0xb38f0f83, 0x0000001f, 0x671e1f07) + + /* Rotate by larger amounts - should be masked. */ + TEST_ROR (0xb38f0f83, 0x00000021, 0xd9c787c1) + TEST_ROR (0xb38f0f83, 0x00002224, 0x3b38f0f8) + TEST_ROR (0xb38f0f83, 0x00f789f0, 0x0f83b38f) + TEST_ROR (0xb38f0f83, 0xffffffff, 0x671e1f07) + + +/* ---------------------------------------------------------------------------- + * Test of rotate right immediate, l.rori + * ------------------------------------------------------------------------- */ +_rori: + LOAD_STR (r3, "l.rori\n") + l.jal _puts + l.nop + + /* Rotate by zero */ + TEST_RORI (0xb38f0f83, 0x00000000, 0xb38f0f83) + + /* Rotate by amounts in the 1 - 31 range. */ + TEST_RORI (0xb38f0f83, 0x01, 0xd9c787c1) + TEST_RORI (0xb38f0f83, 0x04, 0x3b38f0f8) + TEST_RORI (0xb38f0f83, 0x10, 0x0f83b38f) + TEST_RORI (0xb38f0f83, 0x1f, 0x671e1f07) + + /* Rotate by larger amounts (32 - 63) - should be masked. */ + TEST_RORI (0xb38f0f83, 0x21, 0xd9c787c1) + TEST_RORI (0xb38f0f83, 0x24, 0x3b38f0f8) + TEST_RORI (0xb38f0f83, 0x30, 0x0f83b38f) + TEST_RORI (0xb38f0f83, 0x3f, 0x671e1f07) + + +/* ---------------------------------------------------------------------------- + * All done + * ------------------------------------------------------------------------- */ +_exit: + LOAD_STR (r3, "Test completed\n") + l.jal _puts + l.nop + + TEST_EXIT

is-ror-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: is-jump-test.S =================================================================== --- is-jump-test.S (nonexistent) +++ is-jump-test.S (revision 347) @@ -0,0 +1,149 @@ +/* is-jump-test.S. l.j, l.jal, l.jalr and l.jr instruction test of Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * Test coverage + * + * The l.jalr and l.jr instructions should trigger an alignment exception if + * the register does not holde an aligned address (Bug 1775). + * + * Having fixed the problem, this is (in good software engineering style), a + * regresison test to go with the fix. + * + * This is not a comprehensive test of either instruction (yet). + * + * Of course what is really needed is a comprehensive instruction test... + * ------------------------------------------------------------------------- */ + + +#include "inst-set-test.h" + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of a jump using a register destination + * + * We manually construct the opcode, to allow us to force r9 into the + * destination field, to test exception handling. Usually the assembler would + * prevent this. + * + * Arguments + * opc_mask: The opcode mask + * regno: Register number to use + * offset: Offset in bytes forward of target (testing alignment + * ------------------------------------------------------------------------- */ +#define TEST_JUMP(opc_mask, dest, offset) \ + LOAD_CONST (r31,51f + offset) ;\ + .word (0xe01f0004|(dest << 21)) /* l.ori rD,r31,r0 */ ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +50: .word (opc_mask|(dest << 11)) /* Jump opcode */ ;\ + l.nop ;\ + ;\ + /* Jump failed, we drop through to here */ ;\ + l.mfspr r2,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r2) /* Save EPCR for later */ ;\ + PUTS (" Jump to 0x") ;\ + PUTH (51f + offset) ;\ + PUTS (" using register 0x") ;\ + PUTHQ (dest) ;\ + PUTS (" failed\n") ;\ + l.j 52f ;\ + l.nop ;\ + ;\ + /* Jump succeeded we get here */ ;\ +51: l.mfspr r2,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r2) /* Save EPCR for later */ ;\ + PUTS (" Jump to 0x") ;\ + PUTH (51b + offset) ;\ + PUTS (" using register 0x") ;\ + PUTHQ (dest) ;\ + PUTS (" OK\n") ;\ + ;\ + /* Report if we got exception */ ;\ +52: POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 53f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 54f ;\ + l.nop ;\ + ;\ +53: PUTS (" - exception triggered: FALSE\n") ;\ +54: + + +/* ---------------------------------------------------------------------------- + * Start of code + * ------------------------------------------------------------------------- */ + .section .text + .global _start +_start: + +/* ---------------------------------------------------------------------------- + * Test of jump and link register, l.jalr + * ------------------------------------------------------------------------- */ +_jalr: + LOAD_STR (r3, "l.jalr\n") + l.jal _puts + l.nop + + /* Test with various alignment offsets */ + TEST_JUMP (0x48000000, 5, 0) /* No offset */ + TEST_JUMP (0x48000000, 5, 1) /* No offset */ + TEST_JUMP (0x48000000, 5, 2) /* No offset */ + TEST_JUMP (0x48000000, 5, 3) /* No offset */ + + /* Test with link register as the destination */ + TEST_JUMP (0x48000000, 9, 0) /* No offset */ + +/* ---------------------------------------------------------------------------- + * Test of jump register, l.jr + * ------------------------------------------------------------------------- */ +_jr: + LOAD_STR (r3, "l.jr\n") + l.jal _puts + l.nop + + /* Test with various alignment offsets */ + TEST_JUMP (0x44000000, 5, 0) /* No offset */ + TEST_JUMP (0x44000000, 5, 1) /* No offset */ + TEST_JUMP (0x44000000, 5, 2) /* No offset */ + TEST_JUMP (0x44000000, 5, 3) /* No offset */ + + /* Test with link register as the destination (OK here) */ + TEST_JUMP (0x44000000, 9, 0) /* No offset */ + +/* ---------------------------------------------------------------------------- + * All done + * ------------------------------------------------------------------------- */ +_exit: + LOAD_STR (r3, "Test completed\n") + l.jal _puts + l.nop + + TEST_EXIT

is-jump-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: inst-set-test.S =================================================================== --- inst-set-test.S (nonexistent) +++ inst-set-test.S (revision 347) @@ -0,0 +1,482 @@ +/* inst-set-test.S. Instruction set test library for Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions + * + * A simple rising stack is provided starting at _stack and pointed to by + * r1. r1 points to the next free word. Only 32-bit registers may be pushed + * onto the stack. + * + * Local labels up to 49 are reserved for macros. Each is used only once in + * all macros. You can get in a serious mess if you get local label clashing + * in macros. + * + * Arguments to functions are passed in r3 through r8. + * r9 is the link (return address) + * r11 is for returning results + * + * All registers apart from r2, r9 and r11 are preserved across function calls. + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * This library contains the stack implementation and reset sequence and a set + * of library functions. + * + * The functions provided here provide simple utilities that are useful when + * writing tests in assembler. + * ------------------------------------------------------------------------- */ + +#include "inst-set-test.h" + +/* ---------------------------------------------------------------------------- + * Simple stack, will be pointed to by r1, which is the next empty slot + * ------------------------------------------------------------------------- */ + .section .stack + .balign 4 + .global _stack +_stack: + .space 0x1000,0x0 + +/* ---------------------------------------------------------------------------- + * Exception handling + * ------------------------------------------------------------------------- */ + .section .boot-text + +/* ---------------------------------------------------------------------------- + * Reset exception + * + * Set up the stack and jump to _start + * ------------------------------------------------------------------------- */ + .org 0x100 + .global _reset +_reset: + l.movhi r1,hi(_stack) /* Set up the stack */ + l.ori r1,r1,lo(_stack) + + l.j _start /* Jump to the start of code */ + l.nop + +/* ---------------------------------------------------------------------------- + * Alignment exception + * + * Don't be tempted to use the LOAD_STR macro here, it will dump us back into + * text section. + * + * The handling is a bit dubious at present. We just patch the instruction and + * restart. This will go wrong in branch delay slots. Really we need to single + * step past and then continue. + * + * Print a message identifying the exception type. + * ------------------------------------------------------------------------- */ + .section .rodata +50: .string " ALIGNMENT exception\n" + + .section .boot-text + .org 0x600 + .global _align +_align: + /* Report exception */ + LOAD_CONST (r3, 50b) + l.jal _puts + l.nop + + /* Patch with l.nop */ + l.mfspr r2,r0,SPR_EPCR_BASE /* Addr of problem instr */ + LOAD_CONST (r3, 0x15000000) /* l.nop */ + l.sw 0(r2),r3 + + /* All done */ + l.rfe +_align_end: + +/* ---------------------------------------------------------------------------- + * Illegal instruction exception + * + * Don't be tempted to use the LOAD_STR macro here, it will dump us back into + * text section. + * + * The handling is a bit dubious at present. We just patch the instruction and + * restart. This will go wrong in branch delay slots. Really we need to single + * step past and then continue. + * + * Print a message identifying the exception type. + * ------------------------------------------------------------------------- */ + .section .rodata +51: .string " ILLEGAL INSTRUCTION exception\n" + + .section .boot-text + .org 0x700 + .global _illegal +_illegal: + /* Report exception */ + LOAD_CONST (r3, 51b) + l.jal _puts + l.nop + + /* Patch with l.nop */ + l.mfspr r2,r0,SPR_EPCR_BASE /* Addr of problem instr */ + LOAD_CONST (r3, 0x15000000) /* l.nop */ + l.sw 0(r2),r3 + + /* All done */ + l.rfe +_illegal_end: + +/* ---------------------------------------------------------------------------- + * Range exception + * + * Don't be tempted to use the LOAD_STR macro here, it will dump us back into + * text section. + * + * The handling is a bit dubious at present. We just patch the instruction and + * restart. This will go wrong in branch delay slots. Really we need to single + * step past and then continue. + * + * Print a message identifying the exception type. + * ------------------------------------------------------------------------- */ + .section .rodata +52: .string " RANGE exception\n" + + .section .boot-text + .org 0xb00 + .global _range +_range: + /* Report exception */ + LOAD_CONST (r3, 52b) + l.jal _puts + l.nop + + /* Patch with l.nop */ + l.mfspr r2,r0,SPR_EPCR_BASE /* Addr of problem instr */ + LOAD_CONST (r3, 0x15000000) /* l.nop */ + l.sw 0(r2),r3 + + /* All done */ + l.rfe +_range_end: + +/* ---------------------------------------------------------------------------- + * End of exception vectors + * + * Guarantee the exception vector space does not have general purpose code + * ------------------------------------------------------------------------- */ + .org 0xffc + l.nop + +/* ---------------------------------------------------------------------------- + * All subroutines are in the text section. + * ------------------------------------------------------------------------- */ + .section .text + +/* ---------------------------------------------------------------------------- + * Subroutine to print out a string + * + * The string is followed by a newline + * + * Parameters: + * r3 Pointer to the string to print + * ------------------------------------------------------------------------- */ + .global _puts +_puts: + PUSH (r3) + l.add r2,r0,r3 /* Copy the string pointer */ + + /* Loop getting and printing each char until end of string */ +60: l.lbz r3,0(r2) + l.sfeq r3,r0 /* NULL termination? */ + l.bf 61f + + l.addi r2,r2,1 /* Delay slot, move to next char */ + l.j 60b /* Repeat */ + l.nop NOP_PUTC /* Delay slot */ + +61: POP (r3) + l.jr r9 /* Return */ + l.nop + +/* ---------------------------------------------------------------------------- + * Subroutine to print out a register in hex + * + * Parameters: + * r3 The value to print + * ------------------------------------------------------------------------- */ + .section .rodata +62: .string "0123456789abcdef" + .section .text + + .global _puth +_puth: + PUSH (r3) + PUSH (r4) + + l.add r2,r0,r3 /* Copy the value pointer */ + LOAD_CONST (r4,62b) /* Ptr to digit chars */ + + l.srli r3,r2,28 /* Print each digit in turn. */ + l.add r3,r4,r3 + l.lbz r3,0(r3) + l.nop NOP_PUTC + + l.srli r3,r2,24 + l.andi r3,r3,0xf + l.add r3,r4,r3 + l.lbz r3,0(r3) + l.nop NOP_PUTC + + l.srli r3,r2,20 + l.andi r3,r3,0xf + l.add r3,r4,r3 + l.lbz r3,0(r3) + l.nop NOP_PUTC + + l.srli r3,r2,16 + l.andi r3,r3,0xf + l.add r3,r4,r3 + l.lbz r3,0(r3) + l.nop NOP_PUTC + + l.srli r3,r2,12 + l.andi r3,r3,0xf + l.add r3,r4,r3 + l.lbz r3,0(r3) + l.nop NOP_PUTC + + l.srli r3,r2,8 + l.andi r3,r3,0xf + l.add r3,r4,r3 + l.lbz r3,0(r3) + l.nop NOP_PUTC + + l.srli r3,r2,4 + l.andi r3,r3,0xf + l.add r3,r4,r3 + l.lbz r3,0(r3) + l.nop NOP_PUTC + + l.andi r3,r2,0xf + l.add r3,r4,r3 + l.lbz r3,0(r3) + l.nop NOP_PUTC + + POP (r4) /* Return */ + POP (r3) + l.jr r9 + l.nop + +/* ---------------------------------------------------------------------------- + * Subroutine to print out the lower half of a register in hex + * + * Parameters: + * r3 The value to print + * ------------------------------------------------------------------------- */ + .section .rodata +63: .string "0123456789abcdef" + .section .text + + .global _puthh +_puthh: + PUSH (r3) + PUSH (r4) + + l.add r2,r0,r3 /* Copy the value pointer */ + LOAD_CONST (r4,63b) /* Ptr to digit chars */ + + l.srli r3,r2,12 /* Print each digit in turn. */ + l.andi r3,r3,0xf + l.add r3,r4,r3 + l.lbz r3,0(r3) + l.nop NOP_PUTC + + l.srli r3,r2,8 + l.andi r3,r3,0xf + l.add r3,r4,r3 + l.lbz r3,0(r3) + l.nop NOP_PUTC + + l.srli r3,r2,4 + l.andi r3,r3,0xf + l.add r3,r4,r3 + l.lbz r3,0(r3) + l.nop NOP_PUTC + + l.andi r3,r2,0xf + l.add r3,r4,r3 + l.lbz r3,0(r3) + l.nop NOP_PUTC + + POP (r4) /* Return */ + POP (r3) + l.jr r9 + l.nop + +/* ---------------------------------------------------------------------------- + * Subroutine to print out the lowest byte of a register in hex + * + * Parameters: + * r3 The value to print + * ------------------------------------------------------------------------- */ + .section .rodata +63: .string "0123456789abcdef" + .section .text + + .global _puthq +_puthq: + PUSH (r3) + PUSH (r4) + + l.add r2,r0,r3 /* Copy the value pointer */ + LOAD_CONST (r4,63b) /* Ptr to digit chars */ + + l.srli r3,r2,4 /* Print each digit in turn. */ + l.andi r3,r3,0xf + l.add r3,r4,r3 + l.lbz r3,0(r3) + l.nop NOP_PUTC + + l.andi r3,r2,0xf + l.add r3,r4,r3 + l.lbz r3,0(r3) + l.nop NOP_PUTC + + POP (r4) /* Return */ + POP (r3) + l.jr r9 + l.nop + +/* ---------------------------------------------------------------------------- + * Subroutine to print out a test name prompt + * + * The string is preceded by two spaces + * + * Parameters: + * r3 Pointer to the test name to print + * ------------------------------------------------------------------------- */ + .global _ptest +_ptest: + PUSH (r9) /* Save the return address */ + PUSH (r3) /* Save the test name for later */ + + LOAD_STR (r3, " ") /* Prefix */ + l.jal _puts + l.nop + + POP(r3) /* Test name */ + l.jal _puts + l.nop + + POP (r9) + l.jr r9 + l.nop + +/* ---------------------------------------------------------------------------- + * Subroutine to print out "OK" + * + * The string is followed by a newline + * ------------------------------------------------------------------------- */ + .global _pok +_pok: + PUSH (r9) /* Save the return address */ + PUSH (r3) + + LOAD_STR (r3, "OK\n") + l.jal _puts + l.nop + + POP (r3) + POP (r9) + l.jr r9 + l.nop + +/* ---------------------------------------------------------------------------- + * Subroutine to print out "Failed" + * + * The string is followed by a ": ", which will then allow a report + * ------------------------------------------------------------------------- */ + .global _pfail +_pfail: + PUSH (r9) /* Save the return address */ + PUSH (r3) + + LOAD_STR (r3, "Failed: ") + l.jal _puts + l.nop + + POP (r3) + POP (r9) + l.jr r9 + l.nop + +/* ---------------------------------------------------------------------------- + * Subroutine to print out "TRUE" + * ------------------------------------------------------------------------- */ + .global _ptrue +_ptrue: + PUSH (r9) /* Save the return address */ + PUSH (r3) + + LOAD_STR (r3, "TRUE") + l.jal _puts + l.nop + + POP (r3) + POP (r9) + l.jr r9 + l.nop + +/* ---------------------------------------------------------------------------- + * Subroutine to print out "FALSE" + * ------------------------------------------------------------------------- */ + .global _pfalse +_pfalse: + PUSH (r9) /* Save the return address */ + PUSH (r3) + + LOAD_STR (r3, "FALSE") + l.jal _puts + l.nop + + POP (r3) + POP (r9) + l.jr r9 + l.nop + +/* ---------------------------------------------------------------------------- + * Subroutine to print out "unexpected" + * + * Preceded by a space and followed by a newline + * ------------------------------------------------------------------------- */ + .global _punexpected +_punexpected: + PUSH (r9) /* Save the return address */ + PUSH (r3) + + LOAD_STR (r3, " unexpected\n") + l.jal _puts + l.nop + + POP (r3) + POP (r9) + l.jr r9 + l.nop

inst-set-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: is-add-test.S =================================================================== --- is-add-test.S (nonexistent) +++ is-add-test.S (revision 347) @@ -0,0 +1,627 @@ +/* is-add-test.S. l.add, l.addc, l.addi and l.addic instruction test of Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * Test coverage + * + * The l.add, l.addc, l.addi and l.addic instructions should set the carry and + * overflow flags. + * + * In addition the l.addc and l.addic instructions should add in the carry + * bit. + * + * Problems in this area were reported in Bugs 1771 and 1776. Having fixed the + * problem, this is (in good software engineering style), a regression test + * to go with the fix. + * + * This is not a comprehensive test of any instruction (yet). + * + * Of course what is really needed is a comprehensive instruction test... + * ------------------------------------------------------------------------- */ + + +#include "inst-set-test.h" + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of addition in registers + * + * + * Arguments + * set_flags: Flags to set in the SR + * clr_flags: Flags to clear in the SR + * opc: The opcode + * op1: First operand value + * op2: Second operand value + * res: Expected result + * cy: Expected carry flag + * ov: Expected overflow flag + * ------------------------------------------------------------------------- */ +#define TEST_ADD(set_flags, clr_flags, opc, op1, op2, res, cy, ov) \ + l.mfspr r3,r0,SPR_SR ;\ + LOAD_CONST (r2, set_flags) /* Set flags */ ;\ + l.or r3,r3,r2 ;\ + LOAD_CONST (r2, ~clr_flags) /* Clear flags */ ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load numbers to add */ ;\ + LOAD_CONST (r6,op2) ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +50: opc r4,r5,r6 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" + 0x") ;\ + PUTH (op2) ;\ + ;\ + LOAD_CONST (r2, set_flags) /* Are we adding in carry */ ;\ + LOAD_CONST (r4, SPR_SR_CY) ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 51f ;\ + l.nop ;\ + ;\ + PUTS (" + c") /* CY set to add in? */ ;\ + l.j 52f ;\ + l.nop ;\ + ;\ +51: PUTS (" ") /* CY clear to add in? */ ;\ + ;\ +52: PUTS (" = 0x") ;\ + PUTH (res) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, res) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", cy) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", ov) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 53f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 54f ;\ + l.nop ;\ + ;\ +53: PUTS (" - exception triggered: FALSE\n") ;\ +54: + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of addition with an immediate value + * + * + * Arguments + * set_flags: Flags to set in the SR + * clr_flags: Flags to clear in the SR + * opc: The opcode + * op1: First operand value + * op2: Second operand value (immediate) + * res: Expected result + * cy: Expected carry flag + * ov: Expected overflow flag + * ------------------------------------------------------------------------- */ +#define TEST_ADDI(set_flags, clr_flags, opc, op1, op2, res, cy, ov) \ + l.mfspr r3,r0,SPR_SR ;\ + LOAD_CONST (r2, set_flags) /* Set flags */ ;\ + l.or r3,r3,r2 ;\ + LOAD_CONST (r2, ~clr_flags) /* Clear flags */ ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load numbers to add */ ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +55: opc r4,r5,op2 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" + 0x") ;\ + PUTH (op2) ;\ + ;\ + LOAD_CONST (r2, set_flags) /* Are we adding in carry */ ;\ + LOAD_CONST (r4, SPR_SR_CY) ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 56f ;\ + l.nop ;\ + ;\ + PUTS (" + c") /* CY set to add in? */ ;\ + l.j 57f ;\ + l.nop ;\ + ;\ +56: PUTS (" ") /* CY clear to add in? */ ;\ + ;\ +57: PUTS (" = 0x") ;\ + PUTH (res) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, res) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", cy) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", ov) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 55b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 58f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 59f ;\ + l.nop ;\ + ;\ +58: PUTS (" - exception triggered: FALSE\n") ;\ +59: + + +/* ---------------------------------------------------------------------------- + * Start of code + * ------------------------------------------------------------------------- */ + .section .text + .global _start +_start: + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */ + l.and r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag cleared **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * Test of add signed, l.add + * ------------------------------------------------------------------------- */ +_add: + LOAD_STR (r3, "l.add\n") + l.jal _puts + l.nop + + /* Add two small positive numbers */ + TEST_ADD (0, SPR_SR_CY | SPR_SR_OV, + l.add, 1, 2, 3, + FALSE, FALSE) + + /* Check carry in is ignored. */ + TEST_ADD (SPR_SR_CY, SPR_SR_OV, + l.add, 1, 2, 3, + FALSE, FALSE) + + /* Add two small negative numbers. Sets the carry flag but not the + overflow flag. */ + TEST_ADD (0, SPR_SR_CY | SPR_SR_OV, + l.add, 0xffffffff, 0xfffffffe, 0xfffffffd, + TRUE, FALSE) + + /* Add two quite large positive numbers. Should set neither the + overflow nor the carry flag. */ + TEST_ADD (0, SPR_SR_CY | SPR_SR_OV, + l.add, 0x40000000, 0x3fffffff, 0x7fffffff, + FALSE, FALSE) + + /* Add two large positive numbers. Should set the overflow, but not + the carry flag. */ + TEST_ADD (0, SPR_SR_CY | SPR_SR_OV, + l.add, 0x40000000, 0x40000000, 0x80000000, + FALSE, TRUE) + + /* Add two quite large negative numbers. Should set the carry, but not + the overflow flag. */ + TEST_ADD (0, SPR_SR_CY | SPR_SR_OV, + l.add, 0xc0000000, 0xc0000000, 0x80000000, + TRUE, FALSE) + + /* Add two large negative numbers. Should set both the overflow and + carry flags. */ + TEST_ADD (0, SPR_SR_CY | SPR_SR_OV, + l.add, 0xbfffffff, 0xbfffffff, 0x7ffffffe, + TRUE, TRUE) + + /* Check that range exceptions are triggered */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */ + l.or r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag set **\n") + l.jal _puts + l.nop + + /* Check that an overflow alone causes a RANGE Exception. */ + TEST_ADD (0, SPR_SR_CY | SPR_SR_OV, + l.add, 0x40000000, 0x40000000, 0x80000000, + FALSE, TRUE) + + /* Check that a carry alone does not cause a RANGE Exception. */ + TEST_ADD (0, SPR_SR_CY | SPR_SR_OV, + l.add, 0xffffffff, 0xfffffffe, 0xfffffffd, + TRUE, FALSE) + + /* Check that carry and overflow together cause an exception. */ + TEST_ADD (0, SPR_SR_CY | SPR_SR_OV, + l.add, 0xbfffffff, 0xbfffffff, 0x7ffffffe, + TRUE, TRUE) + + /* Finished checking range exceptions */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */ + l.and r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag cleared **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * Test of add signed and carry, l.addc + * ------------------------------------------------------------------------- */ +_addc: + LOAD_STR (r3, "l.addc\n") + l.jal _puts + l.nop + + /* Add two small positive numbers */ + TEST_ADD (0, SPR_SR_CY | SPR_SR_OV, + l.addc, 1, 2, 3, + FALSE, FALSE) + + /* Add two small negative numbers. Sets the carry flag but not the + overflow flag. */ + TEST_ADD (0, SPR_SR_CY | SPR_SR_OV, + l.addc, 0xffffffff, 0xfffffffe, 0xfffffffd, + TRUE, FALSE) + + /* Add two quite large positive numbers. Should set neither the + overflow nor the carry flag. */ + TEST_ADD (0, SPR_SR_CY | SPR_SR_OV, + l.addc, 0x40000000, 0x3fffffff, 0x7fffffff, + FALSE, FALSE) + + /* Add two quite large positive numbers with a carry in. Should set + the overflow but not the carry flag. */ + TEST_ADD (SPR_SR_CY, SPR_SR_OV, + l.addc, 0x40000000, 0x3fffffff, 0x80000000, + FALSE, TRUE) + + /* Add two large positive numbers. Should set the overflow, but not + the carry flag. */ + TEST_ADD (0, SPR_SR_CY | SPR_SR_OV, + l.addc, 0x40000000, 0x40000000, 0x80000000, + FALSE, TRUE) + + /* Add the largest unsigned value to zero with a carry. This + potentially can break a simplistic test for carry that does not + consider the carry flag properly. Do it both ways around. */ + TEST_ADD (SPR_SR_CY, SPR_SR_OV, + l.addc, 0xffffffff, 0x00000000, 0x00000000, + TRUE, FALSE) + + TEST_ADD (SPR_SR_CY, SPR_SR_OV, + l.addc, 0x00000000, 0xffffffff, 0x00000000, + TRUE, FALSE) + + /* Add two quite large negative numbers. Should set the carry, but not + the overflow flag. flag. */ + TEST_ADD (0, SPR_SR_CY | SPR_SR_OV, + l.addc, 0xc0000000, 0xc0000000, 0x80000000, + TRUE, FALSE) + + /* Add two quite large negative numbers that would overflow, with a + carry that just avoids the overflow. Should set the carry, but not + the overflow flag. flag. */ + TEST_ADD (SPR_SR_CY, SPR_SR_OV, + l.addc, 0xc0000000, 0xbfffffff, 0x80000000, + TRUE, FALSE) + + /* Add two large negative numbers. Should set both the overflow and + carry flags. */ + TEST_ADD (0, SPR_SR_CY | SPR_SR_OV, + l.addc, 0xbfffffff, 0xbfffffff, 0x7ffffffe, + TRUE, TRUE) + + /* Check that range exceptions are triggered */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */ + l.or r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag set **\n") + l.jal _puts + l.nop + + /* Check that an overflow alone causes a RANGE Exception, even when it + is the carry that causes the overflow. */ + TEST_ADD (0, SPR_SR_CY | SPR_SR_OV, + l.addc, 0x40000000, 0x40000000, 0x80000000, + FALSE, TRUE) + + TEST_ADD (SPR_SR_CY, SPR_SR_OV, + l.addc, 0x40000000, 0x3fffffff, 0x80000000, + FALSE, TRUE) + + /* Check that a carry alone does not cause a RANGE Exception, even + when it is the carry that causes the overflow. */ + TEST_ADD (0, SPR_SR_CY | SPR_SR_OV, + l.addc, 0xffffffff, 0xfffffffe, 0xfffffffd, + TRUE, FALSE) + + TEST_ADD (SPR_SR_CY, SPR_SR_OV, + l.addc, 0x00000000, 0xffffffff, 0x00000000, + TRUE, FALSE) + + /* Check that carry and overflow together cause an exception. */ + TEST_ADD (0, SPR_SR_CY | SPR_SR_OV, + l.addc, 0xbfffffff, 0xbfffffff, 0x7ffffffe, + TRUE, TRUE) + + /* Finished checking range exceptions */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */ + l.and r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag cleared **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * Test of add signed immediate, l.addi + * ------------------------------------------------------------------------- */ +_addi: + LOAD_STR (r3, "l.addi\n") + l.jal _puts + l.nop + + /* Add two small positive numbers */ + TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV, + l.addi, 1, 2, 3, + FALSE, FALSE) + + /* Check carry in is ignored. */ + TEST_ADDI (SPR_SR_CY, SPR_SR_OV, + l.addi, 1, 2, 3, + FALSE, FALSE) + + /* Add two small negative numbers. Sets the carry flag but not the + overflow flag. */ + TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV, + l.addi, 0xffffffff, 0xfffe, 0xfffffffd, + TRUE, FALSE) + + /* Add two quite large positive numbers. Should set neither the + overflow nor the carry flag. */ + TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV, + l.addi, 0x7fff8000, 0x7fff, 0x7fffffff, + FALSE, FALSE) + + /* Add two large positive numbers. Should set the overflow, but not + the carry flag. */ + TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV, + l.addi, 0x7fffc000, 0x4000, 0x80000000, + FALSE, TRUE) + + /* Add two quite large negative numbers. Should set the carry, but not + the overflow flag. */ + TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV, + l.addi, 0x80008000, 0x8000, 0x80000000, + TRUE, FALSE) + + /* Add two large negative numbers. Should set both the overflow and + carry flags. */ + TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV, + l.addi, 0x80007fff, 0x8000, 0x7fffffff, + TRUE, TRUE) + + /* Check that range exceptions are triggered */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */ + l.or r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag set **\n") + l.jal _puts + l.nop + + /* Check that an overflow alone causes a RANGE Exception. */ + TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV, + l.addi, 0x7fffc000, 0x4000, 0x80000000, + FALSE, TRUE) + + /* Check that a carry alone does not cause a RANGE Exception. */ + TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV, + l.addi, 0xffffffff, 0xfffe, 0xfffffffd, + TRUE, FALSE) + + /* Check that carry and overflow together cause an exception. */ + TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV, + l.addi, 0x80007fff, 0x8000, 0x7fffffff, + TRUE, TRUE) + + /* Finished checking range exceptions */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */ + l.and r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag cleared **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * Test of add signed and carry, l.addic + * ------------------------------------------------------------------------- */ +_addic: + LOAD_STR (r3, "l.addic\n") + l.jal _puts + l.nop + + /* Add two small positive numbers */ + TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV, + l.addic, 1, 2, 3, + FALSE, FALSE) + + /* Add two small negative numbers. Sets the carry flag but not the + overflow flag. */ + TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV, + l.addic, 0xffffffff, 0xfffe, 0xfffffffd, + TRUE, FALSE) + + /* Add two quite large positive numbers. Should set neither the + overflow nor the carry flag. */ + TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV, + l.addic, 0x7fff8000, 0x7fff, 0x7fffffff, + FALSE, FALSE) + + /* Add two quite large positive numbers with a carry in. Should set + the overflow but not the carry flag. */ + TEST_ADDI (SPR_SR_CY, SPR_SR_OV, + l.addic, 0x7fff8000, 0x7fff, 0x80000000, + FALSE, TRUE) + + /* Add two large positive numbers. Should set the overflow, but not + the carry flag. */ + TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV, + l.addic, 0x7fffc000, 0x4000, 0x80000000, + FALSE, TRUE) + + /* Add the largest unsigned value to zero with a carry. This + potentially can break a simplistic test for carry that does not + consider the carry flag properly. Do it both ways around. */ + TEST_ADDI (SPR_SR_CY, SPR_SR_OV, + l.addic, 0xffffffff, 0x0000, 0x00000000, + TRUE, FALSE) + + TEST_ADDI (SPR_SR_CY, SPR_SR_OV, + l.addic, 0x00000000, 0xffff, 0x00000000, + TRUE, FALSE) + + /* Add two quite large negative numbers. Should set the carry, but not + the overflow flag. flag. */ + TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV, + l.addic, 0x80008000, 0x8000, 0x80000000, + TRUE, FALSE) + + /* Add two quite large negative numbers that would overflow, with a + carry that just avoids the overflow. Should set the carry, but not + the overflow flag. flag. */ + TEST_ADDI (SPR_SR_CY, SPR_SR_OV, + l.addic, 0x80007fff, 0x8000, 0x80000000, + TRUE, FALSE) + + /* Add two large negative numbers. Should set both the overflow and + carry flags. */ + TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV, + l.addic, 0x80007fff, 0x8000, 0x7fffffff, + TRUE, TRUE) + + /* Check that range exceptions are triggered */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */ + l.or r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag set **\n") + l.jal _puts + l.nop + + /* Check that an overflow alone causes a RANGE Exception, even when it + is the carry that causes the overflow. */ + TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV, + l.addic, 0x7fffc000, 0x4000, 0x80000000, + FALSE, TRUE) + + TEST_ADDI (SPR_SR_CY, SPR_SR_OV, + l.addic, 0x7fffc000, 0x3fff, 0x80000000, + FALSE, TRUE) + + /* Check that a carry alone does not cause a RANGE Exception, even + when it is the carry that causes the overflow. */ + TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV, + l.addic, 0xffffffff, 0xfffe, 0xfffffffd, + TRUE, FALSE) + + TEST_ADDI (SPR_SR_CY, SPR_SR_OV, + l.addic, 0x00000000, 0xffff, 0x00000000, + TRUE, FALSE) + + /* Check that carry and overflow together cause an exception. */ + TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV, + l.addic, 0x80007fff, 0x8000, 0x7fffffff, + TRUE, TRUE) + + /* Finished checking range exceptions */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */ + l.and r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag cleared **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * All done + * ------------------------------------------------------------------------- */ +_exit: + LOAD_STR (r3, "Test completed\n") + l.jal _puts + l.nop + + TEST_EXIT \ No newline at end of file

is-add-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: is-mul-test.S =================================================================== --- is-mul-test.S (nonexistent) +++ is-mul-test.S (revision 347) @@ -0,0 +1,497 @@ +/* is-mul-test.S. l.mul, l.muli and l.mulu instruction test of Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * Test coverage + * + * The l.mul, l.muli and l.mulu instructions should all be present and set the + * carry and overflow flags. + * + * Problems in this area were reported in Bugs 1774, 1782, 1783 and 1784. + * Having fixed the problem, this is (in good software engineering style), a + * regression test to go with the fix. + * + * This is not a comprehensive test of any instruction (yet). + * + * Of course what is really needed is a comprehensive instruction test... + * ------------------------------------------------------------------------- */ + + +#include "inst-set-test.h" + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of multiply signed or unsigned + * + * Arguments + * opc: The opcode + * op1: First operand value + * op2: Second operand value + * res: Expected result + * cy: Expected carry flag + * ov: Expected overflow flag + * ------------------------------------------------------------------------- */ +#define TEST_MUL(opc, op1, op2, res, cy, ov) \ + l.mfspr r3,r0,SPR_SR ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 /* Clear flags */ ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load numbers to add */ ;\ + LOAD_CONST (r6,op2) ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +50: opc r4,r5,r6 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" * 0x") ;\ + PUTH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (res) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, res) ;\ + ;\ + POP (r2) /* Retrieve SR */ ;\ + PUSH (r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", cy) ;\ + ;\ + POP (r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", ov) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 51f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 52f ;\ + l.nop ;\ + ;\ +51: PUTS (" - exception triggered: FALSE\n") ;\ +52: + + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of multiply immediate + * + * Arguments + * op1: First operand value + * op2: Second operand value + * res: Expected result + * cy: Expected carry flag + * ov: Expected overflow flag + * ------------------------------------------------------------------------- */ +#define TEST_MULI(op1, op2, res, cy, ov) \ + l.mfspr r3,r0,SPR_SR ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 /* Clear flags */ ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load numbers to add */ ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +53: l.muli r4,r5,op2 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" * 0x") ;\ + PUTHH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (res) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, res) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", cy) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", ov) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 53b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 54f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 55f ;\ + l.nop ;\ + ;\ +54: PUTS (" - exception triggered: FALSE\n") ;\ +55: + + +/* ---------------------------------------------------------------------------- + * Start of code + * ------------------------------------------------------------------------- */ + .section .text + .global _start +_start: + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */ + l.and r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag cleared **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * Test of multiply signed, l.mul + * ------------------------------------------------------------------------- */ +_mul: + LOAD_STR (r3, "l.mul\n") + l.jal _puts + l.nop + + /* Multiply two small positive numbers. Should set no flags. */ + TEST_MUL (l.mul, 0x00000002, 0x00000003, + 0x00000006, FALSE, FALSE) + + /* Multiply two quite large positive numbers. Should set no flags */ + TEST_MUL (l.mul, 0x00008001, 0x0000fffe, + 0x7ffffffe, FALSE, FALSE) + + /* Multiply two slightly too large positive numbers. Should set the + overflow, but not the carry flag */ + TEST_MUL (l.mul, 0x00008000, 0x00010000, + 0x80000000, FALSE, TRUE) + + /* Multiply two large positive numbers. Should set both the carry and + overflow flags (even though the result is not a negative number. */ + TEST_MUL (l.mul, 0x00010000, 0x00010000, 0x00000000, TRUE, TRUE) + + /* Multiply two small negative numbers. Should set the overflow, but not + the carry flag. */ + TEST_MUL (l.mul, 0xfffffffe, 0xfffffffd, + 0x00000006, TRUE, FALSE) + + /* Multiply two quite large negative numbers. Should set the overflow, + but not the carry flag. */ + TEST_MUL (l.mul, 0xffff7fff, 0xffff0002, + 0x7ffffffe, TRUE, FALSE) + + /* Multiply two slightly too large negative numbers. Should set both the + overflow, and the carry flags */ + TEST_MUL (l.mul, 0xffff7fff, 0xffff0000, + 0x80010000, TRUE, TRUE) + + /* Multiply two large negative numbers. Should set the + both the carry and overflow flags (even though the result is a + positive number. */ + TEST_MUL (l.mul, 0xffff0000, 0xfffeffff, + 0x00010000, TRUE, TRUE) + + /* Multiply one small negative number and one small positive number. + Should set the overflow, but not the carry flag. */ + TEST_MUL (l.mul, 0x00000002, 0xfffffffd, + 0xfffffffa, TRUE, FALSE) + + /* Multiply one quite large negative number and one quite large + positive number. Should set the overflow, but not the carry flag. */ + TEST_MUL (l.mul, 0xffff8000, 0x00010000, + 0x80000000, TRUE, FALSE) + + /* Multiply one slightly too large negative number and one slightly + too large positive number. Should set both the carry and overflow + flags. */ + TEST_MUL (l.mul, 0xffff7fff, 0x00010000, + 0x7fff0000, TRUE, TRUE) + + /* Multiply the largest negative number by positive unity. Should set + neither carry, nor overflow flag. */ + TEST_MUL (l.mul, 0x80000000, 0x00000001, + 0x80000000, FALSE, FALSE) + + /* Check that range exceptions are triggered */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */ + l.or r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag set **\n") + l.jal _puts + l.nop + + /* Check that an overflow alone causes a RANGE Exception. */ + TEST_MUL (l.mul, 0x00008000, 0x00010000, + 0x80000000, FALSE, TRUE) + + /* Check that a carry alone does not cause a RANGE Exception. */ + TEST_MUL (l.mul, 0x00000002, 0xfffffffd, + 0xfffffffa, TRUE, FALSE) + + /* Check that carry and overflow together cause an exception. */ + TEST_MUL (l.mul, 0xffff7fff, 0xffff0000, + 0x80010000, TRUE, TRUE) + + /* Finished checking range exceptions */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */ + l.and r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag cleared **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * Test of multiply signed, l.muli + * ------------------------------------------------------------------------- */ +_muli: + LOAD_STR (r3, "l.muli\n") + l.jal _puts + l.nop + + /* Multiply two small positive numbers. Should set no flags. */ + TEST_MULI (0x00000002, 0x0003, + 0x00000006, FALSE, FALSE) + + /* Multiply two quite large positive numbers. Should set no flags */ + TEST_MULI (0x00010002, 0x7fff, + 0x7ffffffe, FALSE, FALSE) + + /* Multiply two slightly too large positive numbers. Should set the + overflow, but not the carry flag */ + TEST_MULI (0x00020000, 0x4000, + 0x80000000, FALSE, TRUE) + + /* Multiply two large positive numbers. Should set both the carry and + overflow flags (even though the result is not a negative number. */ + TEST_MULI (0x00040000, 0x4000, + 0x00000000, TRUE, TRUE) + + /* Multiply two small negative numbers. Should set the overflow, but not + the carry flag. */ + TEST_MULI (0xfffffffe, 0xfffd, + 0x00000006, TRUE, FALSE) + + /* Multiply two quite large negative numbers. Should set the overflow, + but not the carry flag. */ + TEST_MULI (0xfffefffe, 0x8001, + 0x7ffffffe, TRUE, FALSE) + + /* Multiply two slightly too large negative numbers. Should set both the + overflow, and the carry flags */ + TEST_MULI (0xfffe0000, 0xbfff, + 0x80020000, TRUE, TRUE) + + /* Multiply two large negative numbers. Should set the + both the carry and overflow flags (even though the result is a + positive number. */ + TEST_MULI (0xfffdfffe, 0x8000, + 0x00010000, TRUE, TRUE) + + /* Multiply one small negative number and one small positive number. + Should set the overflow, but not the carry flag. */ + TEST_MULI (0x00000002, 0xfffd, + 0xfffffffa, TRUE, FALSE) + + /* Multiply one quite large negative number and one quite large + positive number. Should set the overflow, but not the carry flag. */ + TEST_MULI (0x00010000, 0x8000, + 0x80000000, TRUE, FALSE) + + /* Multiply one slightly too large negative number and one slightly + too large positive number. Should set both the carry and overflow + flags. */ + TEST_MULI (0xfffdfffc, 0x4000, + 0x7fff0000, TRUE, TRUE) + + /* Multiply the largest negative number by positive unity. Should set + neither carry, nor overflow flag. */ + TEST_MULI (0x80000000, 0x0001, + 0x80000000, FALSE, FALSE) + + /* Check that range exceptions are triggered */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */ + l.or r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag set **\n") + l.jal _puts + l.nop + + /* Check that an overflow alone causes a RANGE Exception. */ + TEST_MULI (0x00020000, 0x4000, + 0x80000000, FALSE, TRUE) + + /* Check that a carry alone does not cause a RANGE Exception. */ + TEST_MULI (0xfffffffe, 0xfffd, + 0x00000006, TRUE, FALSE) + + /* Check that carry and overflow together cause an exception. */ + TEST_MULI (0xfffdfffe, 0x8000, + 0x00010000, TRUE, TRUE) + + /* Finished checking range exceptions */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */ + l.and r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag cleared **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * Test of multiply unsigned, l.mulu + * ------------------------------------------------------------------------- */ +_mulu: + LOAD_STR (r3, "l.mulu\n") + l.jal _puts + l.nop + + /* Multiply two small positive numbers. Should set no flags. */ + TEST_MUL (l.mulu, 0x00000002, 0x00000003, + 0x00000006, FALSE, FALSE) + + /* Multiply two quite large positive numbers. Should set no flags */ + TEST_MUL (l.mulu, 0x00008001, 0x0000fffe, + 0x7ffffffe, FALSE, FALSE) + + /* Multiply two slightly too large positive numbers. Should set the + overflow, but not the carry flag */ + TEST_MUL (l.mulu, 0x00008000, 0x00010000, + 0x80000000, FALSE, FALSE) + + /* Multiply two large positive numbers. Should set both the carry and + overflow flags (even though the result is not a negative number. */ + TEST_MUL (l.mulu, 0x00010000, 0x00010000, + 0x00000000, TRUE, FALSE) + + /* Multiply two small negative numbers. Should set the overflow, but not + the carry flag. */ + TEST_MUL (l.mulu, 0xfffffffe, 0xfffffffd, + 0x00000006, TRUE, FALSE) + + /* Multiply two quite large negative numbers. Should set the overflow, + but not the carry flag. */ + TEST_MUL (l.mulu, 0xffff7fff, 0xffff0002, + 0x7ffffffe, TRUE, FALSE) + + /* Multiply two slightly too large negative numbers. Should set both the + overflow, and the carry flags */ + TEST_MUL (l.mulu, 0xffff7fff, 0xffff0000, + 0x80010000, TRUE, FALSE) + + /* Multiply two large negative numbers. Should set the + both the carry and overflow flags (even though the result is a + positive number. */ + TEST_MUL (l.mulu, 0xffff0000, 0xfffeffff, + 0x00010000, TRUE, FALSE) + + /* Multiply one small negative number and one small positive number. + Should set the overflow, but not the carry flag. */ + TEST_MUL (l.mulu, 0x00000002, 0xfffffffd, + 0xfffffffa, TRUE, FALSE) + + /* Multiply one quite large negative number and one quite large + positive number. Should set the overflow, but not the carry flag. */ + TEST_MUL (l.mulu, 0xffff8000, 0x00010000, + 0x80000000, TRUE, FALSE) + + /* Multiply one slightly too large negative number and one slightly + too large positive number. Should set both the carry and overflow + flags. */ + TEST_MUL (l.mulu, 0xffff7fff, 0x00010000, + 0x7fff0000, TRUE, FALSE) + + /* Multiply the largest negative number by positive unity. Should set + neither carry, nor overflow flag. */ + TEST_MUL (l.mulu, 0x80000000, 0x00000001, + 0x80000000, FALSE, FALSE) + + /* Check that range exceptions are never triggered */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */ + l.or r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag set **\n") + l.jal _puts + l.nop + + /* Check that what would cause an overflow alone in 2's complement does + not cause a RANGE Exception. */ + TEST_MUL (l.mulu, 0x00008000, 0x00010000, + 0x80000000, FALSE, FALSE) + + /* Check that a carry alone does not cause a RANGE Exception. */ + TEST_MUL (l.mulu, 0x00000002, 0xfffffffd, + 0xfffffffa, TRUE, FALSE) + + /* Check that what would cause an overflow and carry in 2's complement + does not cause a RANGE Exception. */ + TEST_MUL (l.mulu, 0xffff7fff, 0xffff0000, + 0x80010000, TRUE, FALSE) + + /* Finished checking range exceptions */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */ + l.and r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag cleared **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * All done + * ------------------------------------------------------------------------- */ +_exit: + LOAD_STR (r3, "Test completed\n") + l.jal _puts + l.nop + + TEST_EXIT

is-mul-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: is-find-test.S =================================================================== --- is-find-test.S (nonexistent) +++ is-find-test.S (revision 347) @@ -0,0 +1,140 @@ +/* is-find.test.S. l.ff1 and l.fl1 instruction test of Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * Test coverage + * + * The l.ff1 and l.fl1 should fine the first and last bits in a register + * respectively. + * + * Problems in this area were reported in Bug 1772. Having fixed the problem, + * this is (in good software engineering style), a regression test to go with + * the fix. + * + * This is not a comprehensive test of any instruction (yet). + * + * Of course what is really needed is a comprehensive instruction test... + * ------------------------------------------------------------------------- */ + + +#include "inst-set-test.h" + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of find + * + * Arguments + * op: First operand value + * res: Expected result + * ------------------------------------------------------------------------- */ +#define TEST_FF1(op, res) \ + LOAD_CONST (r4,33) /* Invalid result */ ;\ + LOAD_CONST (r5,op) /* Load number to analyse */ ;\ + l.ff1 r4,r5 ;\ + PUSH (r4) /* Save for later */ ;\ + ;\ + PUTS (" ff1 (0x") ;\ + PUTH (op) ;\ + PUTS (") = 0x") ;\ + PUTHQ (res) ;\ + PUTS (": ") ;\ + ;\ + CHECK_RES1 (r4, res) + + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of find + * + * Arguments + * op: First operand value + * res: Expected result + * ------------------------------------------------------------------------- */ +#define TEST_FL1(op, res) \ + LOAD_CONST (r4,33) /* Invalid result */ ;\ + LOAD_CONST (r5,op) /* Load number to analyse */ ;\ + l.fl1 r4,r5 ;\ + PUSH (r4) /* Save for later */ ;\ + ;\ + PUTS (" fl1 (0x") ;\ + PUTH (op) ;\ + PUTS (") = 0x") ;\ + PUTHQ (res) ;\ + PUTS (": ") ;\ + ;\ + CHECK_RES1 (r4, res) + + +/* ---------------------------------------------------------------------------- + * Start of code + * ------------------------------------------------------------------------- */ + .section .text + .global _start +_start: + +/* ---------------------------------------------------------------------------- + * Test of find first 1, l.ff1 + * ------------------------------------------------------------------------- */ +_ff1: + LOAD_STR (r3, "l.ff1\n") + l.jal _puts + l.nop + + /* Try a range of candidates. */ + TEST_FF1 (0x00000001, 1) + TEST_FF1 (0x80000000, 32) + TEST_FF1 (0x55555555, 1) + TEST_FF1 (0xaaaaaaaa, 2) + TEST_FF1 (0x00018000, 16) + TEST_FF1 (0xc0000000, 31) + TEST_FF1 (0x00000000, 0) + +/* ---------------------------------------------------------------------------- + * Test of find first 1, l.fl1 + * ------------------------------------------------------------------------- */ +_fl1: + LOAD_STR (r3, "l.fl1\n") + l.jal _puts + l.nop + + /* Try a range of candidates. */ + TEST_FL1 (0x00000001, 1) + TEST_FL1 (0x80000000, 32) + TEST_FL1 (0x55555555, 31) + TEST_FL1 (0xaaaaaaaa, 32) + TEST_FL1 (0x00018000, 17) + TEST_FL1 (0xc0000000, 32) + TEST_FL1 (0x00000000, 0) + +/* ---------------------------------------------------------------------------- + * All done + * ------------------------------------------------------------------------- */ +_exit: + LOAD_STR (r3, "Test completed\n") + l.jal _puts + l.nop + + TEST_EXIT

is-find-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: is-mac-test.S =================================================================== --- is-mac-test.S (nonexistent) +++ is-mac-test.S (revision 347) @@ -0,0 +1,991 @@ +/* is-mac-test.S. l.mac, l.maci, l.macrc and l.msb instruction test of Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * Test coverage + * + * The l.mac, l.maci, l.macrc and l.msb instructions perform operations related + * to combined signed multiply and addition/subtraction. + * + * The precise definition of these instructions is in flux. In addition there + * are known problems with the assembler/disassembler (will not correctly + * handle l.maci) and with the Verilog RTL implementation (not functional). + * + * Problems in this area were reported in Bugs 1773 and 1777. Having fixed the + * problem, this is (in good software engineering style), a regression test + * to go with the fix. + * + * This is not a comprehensive test of any instruction (yet). + * + * Of course what is really needed is a comprehensive instruction test... + * ------------------------------------------------------------------------- */ + + +#include "inst-set-test.h" + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of multiply accumulate read and clear + * + * Arguments + * machi: Inital value of MACHI + * maclo: Inital value of MACLO + * op1: First operand value + * op2: Second operand value + * res: Expected result + * ------------------------------------------------------------------------- */ +#define TEST_MACRC(machi, maclo, op1, op2, res) \ + LOAD_CONST (r2,maclo) ;\ + l.mtspr r0,r2,SPR_MACLO ;\ + LOAD_CONST (r2,machi) ;\ + l.mtspr r0,r2,SPR_MACHI ;\ + ;\ + LOAD_CONST (r5,op1) /* Load numbers to add */ ;\ + LOAD_CONST (r6,op2) ;\ + l.mac r5,r6 ;\ + l.macrc r4 ;\ + PUSH (r4) /* Save for later */ ;\ + PUTS (" 0x") ;\ + PUTH (machi) ;\ + PUTS (" ") ;\ + PUTH (maclo) ;\ + PUTS (" + 0x") ;\ + PUTH (op1) ;\ + PUTS (" * 0x") ;\ + PUTH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (res) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES ("", r4, res) ;\ + ;\ + l.mfspr r5,r0,SPR_MACHI ;\ + l.sfne r5,r0 ;\ + l.bf 50f ;\ + ;\ + PUTS (" - MACHI cleared\n") ;\ + ;\ +50: l.mfspr r6,r0,SPR_MACLO ;\ + l.sfne r6,r0 ;\ + l.bf 51f ;\ + ;\ + PUTS (" - MACLO cleared\n") ;\ +51: + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of multiply accumulate in registers + * + * Arguments + * machi: Inital value of MACHI + * maclo: Inital value of MACLO + * op1: First operand value + * op2: Second operand value + * reshi: Expected result + * reslo: Expected result + * ------------------------------------------------------------------------- */ +#define TEST_MAC(machi, maclo, op1, op2, reshi, reslo) \ + LOAD_CONST (r2,maclo) ;\ + l.mtspr r0,r2,SPR_MACLO ;\ + LOAD_CONST (r2,machi) ;\ + l.mtspr r0,r2,SPR_MACHI ;\ + ;\ + LOAD_CONST (r5,op1) /* Load numbers to add */ ;\ + LOAD_CONST (r6,op2) ;\ + l.mac r5,r6 ;\ + l.mfspr r5,r0,SPR_MACHI ;\ + l.mfspr r6,r0,SPR_MACLO ;\ + PUSH (r5) /* Save for later */ ;\ + PUSH (r6) ;\ + PUTS (" 0x") ;\ + PUTH (machi) ;\ + PUTS (" ") ;\ + PUTH (maclo) ;\ + PUTS (" + 0x") ;\ + PUTH (op1) ;\ + PUTS (" * 0x") ;\ + PUTH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (reshi) ;\ + PUTS (" ") ;\ + PUTH (reslo) ;\ + PUTS (": ") ;\ + POP (r6) ;\ + POP (r5) ;\ + CHECK_RES2 (r5, r6, reshi, reslo) + + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of multiply accumulate with immediate arg + * + * There is currently a bug in the assembler, so we must hand construct + * l.maci r5,op1. + * + * Arguments + * machi: Inital value of MACHI + * maclo: Inital value of MACLO + * op1: First operand value + * op2: Second operand value + * reshi: Expected result + * reslo: Expected result + * ------------------------------------------------------------------------- */ +#define TEST_MACI(machi, maclo, op1, op2, reshi, reslo) \ + LOAD_CONST (r2,maclo) ;\ + l.mtspr r0,r2,SPR_MACLO ;\ + LOAD_CONST (r2,machi) ;\ + l.mtspr r0,r2,SPR_MACHI ;\ + ;\ + LOAD_CONST (r5,op1) /* Load number to add */ ;\ + .word (0x4c050000|op2) /* l.maci r5,op2 */ ;\ + /* l.maci r5,op2 */ ;\ + l.mfspr r5,r0,SPR_MACHI ;\ + l.mfspr r6,r0,SPR_MACLO ;\ + PUSH (r5) /* Save for later */ ;\ + PUSH (r6) ;\ + PUTS (" 0x") ;\ + PUTH (machi) ;\ + PUTS (" ") ;\ + PUTH (maclo) ;\ + PUTS (" + 0x") ;\ + PUTH (op1) ;\ + PUTS (" * 0x") ;\ + PUTH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (reshi) ;\ + PUTS (" ") ;\ + PUTH (reslo) ;\ + PUTS (": ") ;\ + POP (r6) ;\ + POP (r5) ;\ + CHECK_RES2 (r5, r6, reshi, reslo) + + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of multiply and subract + * + * Arguments + * machi: Inital value of MACHI + * maclo: Inital value of MACLO + * op1: First operand value + * op2: Second operand value + * reshi: Expected result + * reslo: Expected result + * ------------------------------------------------------------------------- */ +#define TEST_MSB(machi, maclo, op1, op2, reshi, reslo) \ + LOAD_CONST (r2,maclo) ;\ + l.mtspr r0,r2,SPR_MACLO ;\ + LOAD_CONST (r2,machi) ;\ + l.mtspr r0,r2,SPR_MACHI ;\ + ;\ + LOAD_CONST (r5,op1) /* Load numbers to add */ ;\ + LOAD_CONST (r6,op2) ;\ + l.msb r5,r6 ;\ + l.mfspr r5,r0,SPR_MACHI ;\ + l.mfspr r6,r0,SPR_MACLO ;\ + PUSH (r5) /* Save for later */ ;\ + PUSH (r6) ;\ + PUTS (" 0x") ;\ + PUTH (machi) ;\ + PUTS (" ") ;\ + PUTH (maclo) ;\ + PUTS (" - 0x") ;\ + PUTH (op1) ;\ + PUTS (" * 0x") ;\ + PUTH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (reshi) ;\ + PUTS (" ") ;\ + PUTH (reslo) ;\ + PUTS (": ") ;\ + POP (r6) ;\ + POP (r5) ;\ + CHECK_RES2 (r5, r6, reshi, reslo) + + +/* ---------------------------------------------------------------------------- + * Start of code + * ------------------------------------------------------------------------- */ + .section .text + .global _start +_start: + +/* ---------------------------------------------------------------------------- + * Test of multiply signed and accumulate, l.mac + * ------------------------------------------------------------------------- */ +_mac: + LOAD_STR (r3, "l.mac\n") + l.jal _puts + l.nop + + /* MAC two small positive numbers on a zero total */ + TEST_MAC (0x00000000, 0x00000000, + 0x00000002, 0x00000003, + 0x00000000, 0x00000006) + + /* MAC two small positive numbers on a small positive total */ + TEST_MAC (0x00000000, 0x00000006, + 0x00000002, 0x00000003, + 0x00000000, 0x0000000c) + + /* MAC two small positive numbers on a moderate positive total */ + TEST_MAC (0x00000000, 0xfffffffa, + 0x00000002, 0x00000003, + 0x00000001, 0x00000000) + + /* MAC two small positive numbers on a large positive total */ + TEST_MAC (0x3fffffff, 0xfffffffa, + 0x00000002, 0x00000003, + 0x40000000, 0x00000000) + + /* MAC two small positive numbers on a small negative total */ + TEST_MAC (0xffffffff, 0xfffffffa, + 0x00000002, 0x00000003, + 0x00000000, 0x00000000) + + /* MAC two small positive numbers on a moderate negative total */ + TEST_MAC (0xffffffff, 0x00000000, + 0x00000002, 0x00000003, + 0xffffffff, 0x00000006) + + /* MAC two small positive numbers on a large negative total */ + TEST_MAC (0x80000000, 0x00000000, + 0x00000002, 0x00000003, + 0x80000000, 0x00000006) + + PUTC ('\n') + + /* MAC two moderate positive numbers on a zero total */ + TEST_MAC (0x00000000, 0x00000000, + 0x00008001, 0x0000fffe, + 0x00000000, 0x7ffffffe) + + /* MAC two moderate positive numbers on a small positive total */ + TEST_MAC (0x00000000, 0x00000002, + 0x00008001, 0x0000fffe, + 0x00000000, 0x80000000) + + /* MAC two moderate positive numbers on a moderate positive total */ + TEST_MAC (0x00000000, 0x80000002, + 0x00008001, 0x0000fffe, + 0x00000001, 0x00000000) + + /* MAC two moderate positive numbers on a large positive total */ + TEST_MAC (0x7fffffff, 0x80000001, + 0x00008001, 0x0000fffe, + 0x7fffffff, 0xffffffff) + + /* MAC two moderate positive numbers on a small negative total */ + TEST_MAC (0xffffffff, 0xffffffff, + 0x00008001, 0x0000fffe, + 0x00000000, 0x7ffffffd) + + /* MAC two moderate positive numbers on a moderate negative total */ + TEST_MAC (0xffffffff, 0x80000002, + 0x00008001, 0x0000fffe, + 0x00000000, 0x00000000) + + /* MAC two moderate positive numbers on a large negative total */ + TEST_MAC (0xfffffffe, 0x80000002, + 0x00008001, 0x0000fffe, + 0xffffffff, 0x00000000) + + PUTC ('\n') + + /* MAC two small negative numbers on a zero total */ + TEST_MAC (0x00000000, 0x00000000, + 0xfffffffe, 0xfffffffd, + 0x00000000, 0x00000006) + + /* MAC two small negative numbers on a small positive total */ + TEST_MAC (0x00000000, 0x00000006, + 0xfffffffe, 0xfffffffd, + 0x00000000, 0x0000000c) + + /* MAC two small negative numbers on a small negative total */ + TEST_MAC (0xffffffff, 0xffffffff, + 0xfffffffe, 0xfffffffd, + 0x00000000, 0x00000005) + + PUTC ('\n') + + /* MAC one small positive and one small negative number on a zero + total */ + TEST_MAC (0x00000000, 0x00000000, + 0x00000002, 0xfffffffd, + 0xffffffff, 0xfffffffa) + + /* MAC one small positive and one small negative number on a small + positive total */ + TEST_MAC (0x00000000, 0x0000000c, + 0x00000002, 0xfffffffd, + 0x00000000, 0x00000006) + + /* MAC one small positive and one small negative number on a moderate + positive total */ + TEST_MAC (0x00000001, 0x00000005, + 0x00000002, 0xfffffffd, + 0x00000000, 0xffffffff) + + /* MAC one small positive and one small negative number on a large + positive total */ + TEST_MAC (0x7fffffff, 0xffffffff, + 0x00000002, 0xfffffffd, + 0x7fffffff, 0xfffffff9) + + /* MAC one small positive and one small negative number on a small + negative total */ + TEST_MAC (0xffffffff, 0xffffffff, + 0x00000002, 0xfffffffd, + 0xffffffff, 0xfffffff9) + + /* MAC one small positive and one small negative number on a moderate + negative total */ + TEST_MAC (0xffffffff, 0x00000005, + 0x00000002, 0xfffffffd, + 0xfffffffe, 0xffffffff) + + /* MAC one small positive and one small negative number on a large + negative total */ + TEST_MAC (0x80000000, 0x00000006, + 0x00000002, 0xfffffffd, + 0x80000000, 0x00000000) + + PUTC ('\n') + + /* MAC one moderate positive and one moderate negative number on a + zero total */ + TEST_MAC (0x00000000, 0x00000000, + 0x00008000, 0xffff0000, + 0xffffffff, 0x80000000) + + /* MAC one moderate positive and one moderate negative number on a + small positive total */ + TEST_MAC (0x00000000, 0x00000006, + 0x00008000, 0xffff0000, + 0xffffffff, 0x80000006) + + /* MAC one moderate positive and one moderate negative number on a + moderate positive total */ + TEST_MAC (0x00000000, 0x80000000, + 0x00008000, 0xffff0000, + 0x00000000, 0x00000000) + + /* MAC one moderate positive and one moderate negative number on a + large positive total */ + TEST_MAC (0x7fffffff, 0xffffffff, + 0x00008000, 0xffff0000, + 0x7fffffff, 0x7fffffff) + + /* MAC one moderate positive and one moderate negative number on a + small negative total */ + TEST_MAC (0xffffffff, 0xffffffff, + 0x00008000, 0xffff0000, + 0xffffffff, 0x7fffffff) + + /* MAC one moderate positive and one moderate negative number on a + moderate negative total */ + TEST_MAC (0xffffffff, 0x7fffffff, + 0x00008000, 0xffff0000, + 0xfffffffe, 0xffffffff) + + /* MAC one moderate positive and one moderate negative number on a + large negative total */ + TEST_MAC (0x80000000, 0x80000000, + 0x00008000, 0xffff0000, + 0x80000000, 0x00000000) + + PUTC ('\n') + +/* ---------------------------------------------------------------------------- + * Test of multiply signed and accumulate, l.maci + * ------------------------------------------------------------------------- */ +_maci: + LOAD_STR (r3, "l.maci\n") + l.jal _puts + l.nop + + /* MAC two small positive numbers on a zero total */ + TEST_MACI (0x00000000, 0x00000000, + 0x00000002, 0x0003, + 0x00000000, 0x00000006) + + /* MAC two small positive numbers on a small positive total */ + TEST_MACI (0x00000000, 0x00000006, + 0x00000002, 0x0003, + 0x00000000, 0x0000000c) + + /* MAC two small positive numbers on a moderate positive total */ + TEST_MACI (0x00000000, 0xfffffffa, + 0x00000002, 0x0003, + 0x00000001, 0x00000000) + + /* MAC two small positive numbers on a large positive total */ + TEST_MACI (0x3fffffff, 0xfffffffa, + 0x00000002, 0x0003, + 0x40000000, 0x00000000) + + /* MAC two small positive numbers on a small negative total */ + TEST_MACI (0xffffffff, 0xfffffffa, + 0x00000002, 0x0003, + 0x00000000, 0x00000000) + + /* MAC two small positive numbers on a moderate negative total */ + TEST_MACI (0xffffffff, 0x00000000, + 0x00000002, 0x0003, + 0xffffffff, 0x00000006) + + /* MAC two small positive numbers on a large negative total */ + TEST_MACI (0x80000000, 0x00000000, + 0x00000002, 0x0003, + 0x80000000, 0x00000006) + + PUTC ('\n') +tmp: + /* MAC two moderate positive numbers on a zero total */ + TEST_MACI (0x00000000, 0x00000000, + 0x00010002, 0x7fff, + 0x00000000, 0x7ffffffe) + + /* MAC two moderate positive numbers on a small positive total */ + TEST_MACI (0x00000000, 0x00000002, + 0x00010002, 0x7fff, + 0x00000000, 0x80000000) + + /* MAC two moderate positive numbers on a moderate positive total */ + TEST_MACI (0x00000000, 0x80000002, + 0x00010002, 0x7fff, + 0x00000001, 0x00000000) + + /* MAC two moderate positive numbers on a large positive total */ + TEST_MACI (0x7fffffff, 0x80000001, + 0x00010002, 0x7fff, + 0x7fffffff, 0xffffffff) + + /* MAC two moderate positive numbers on a small negative total */ + TEST_MACI (0xffffffff, 0xffffffff, + 0x00010002, 0x7fff, + 0x00000000, 0x7ffffffd) + + /* MAC two moderate positive numbers on a moderate negative total */ + TEST_MACI (0xffffffff, 0x80000002, + 0x00010002, 0x7fff, + 0x00000000, 0x00000000) + + /* MAC two moderate positive numbers on a large negative total */ + TEST_MACI (0xfffffffe, 0x80000002, + 0x00010002, 0x7fff, + 0xffffffff, 0x00000000) + + PUTC ('\n') + + /* MAC two small negative numbers on a zero total */ + TEST_MACI (0x00000000, 0x00000000, + 0xfffffffe, 0xfffd, + 0x00000000, 0x00000006) + + /* MAC two small negative numbers on a small positive total */ + TEST_MACI (0x00000000, 0x00000006, + 0xfffffffe, 0xfffd, + 0x00000000, 0x0000000c) + + /* MAC two small negative numbers on a small negative total */ + TEST_MACI (0xffffffff, 0xffffffff, + 0xfffffffe, 0xfffd, + 0x00000000, 0x00000005) + + PUTC ('\n') + + /* MAC one small positive and one small negative number on a zero + total */ + TEST_MACI (0x00000000, 0x00000000, + 0x00000002, 0xfffd, + 0xffffffff, 0xfffffffa) + + /* MAC one small positive and one small negative number on a small + positive total */ + TEST_MACI (0x00000000, 0x0000000c, + 0x00000002, 0xfffd, + 0x00000000, 0x00000006) + + /* MAC one small positive and one small negative number on a moderate + positive total */ + TEST_MACI (0x00000001, 0x00000005, + 0x00000002, 0xfffd, + 0x00000000, 0xffffffff) + + /* MAC one small positive and one small negative number on a large + positive total */ + TEST_MACI (0x7fffffff, 0xffffffff, + 0x00000002, 0xfffd, + 0x7fffffff, 0xfffffff9) + + /* MAC one small positive and one small negative number on a small + negative total */ + TEST_MACI (0xffffffff, 0xffffffff, + 0x00000002, 0xfffd, + 0xffffffff, 0xfffffff9) + + /* MAC one small positive and one small negative number on a moderate + negative total */ + TEST_MACI (0xffffffff, 0x00000005, + 0x00000002, 0xfffd, + 0xfffffffe, 0xffffffff) + + /* MAC one small positive and one small negative number on a large + negative total */ + TEST_MACI (0x80000000, 0x00000006, + 0x00000002, 0xfffd, + 0x80000000, 0x00000000) + + PUTC ('\n') + + /* MAC one moderate positive and one moderate negative number on a + zero total */ + TEST_MACI (0x00000000, 0x00000000, + 0x00010000, 0x8000, + 0xffffffff, 0x80000000) + + /* MAC one moderate positive and one moderate negative number on a + small positive total */ + TEST_MACI (0x00000000, 0x00000006, + 0x00010000, 0x8000, + 0xffffffff, 0x80000006) + + /* MAC one moderate positive and one moderate negative number on a + moderate positive total */ + TEST_MACI (0x00000000, 0x80000000, + 0x00010000, 0x8000, + 0x00000000, 0x00000000) + + /* MAC one moderate positive and one moderate negative number on a + large positive total */ + TEST_MACI (0x7fffffff, 0xffffffff, + 0x00010000, 0x8000, + 0x7fffffff, 0x7fffffff) + + /* MAC one moderate positive and one moderate negative number on a + small negative total */ + TEST_MACI (0xffffffff, 0xffffffff, + 0x00010000, 0x8000, + 0xffffffff, 0x7fffffff) + + /* MAC one moderate positive and one moderate negative number on a + moderate negative total */ + TEST_MACI (0xffffffff, 0x7fffffff, + 0x00010000, 0x8000, + 0xfffffffe, 0xffffffff) + + /* MAC one moderate positive and one moderate negative number on a + large negative total */ + TEST_MACI (0x80000000, 0x80000000, + 0x00010000, 0x8000, + 0x80000000, 0x00000000) + + PUTC ('\n') + +/* ---------------------------------------------------------------------------- + * Test of multiply signed and accumulate, read and clear l.macrc + * ------------------------------------------------------------------------- */ +_macrc: + LOAD_STR (r3, "l.macrc\n") + l.jal _puts + l.nop + + /* MAC two small positive numbers on a zero total */ + TEST_MACRC (0x00000000, 0x00000000, + 0x00000002, 0x00000003, + 0x00000006) + + /* MAC two small positive numbers on a small positive total */ + TEST_MACRC (0x00000000, 0x00000006, + 0x00000002, 0x00000003, + 0x0000000c) + + /* MAC two small positive numbers on a moderate positive total */ + TEST_MACRC (0x00000000, 0xfffffffa, + 0x00000002, 0x00000003, + 0x00000000) + + /* MAC two small positive numbers on a large positive total */ + TEST_MACRC (0x3fffffff, 0xfffffffa, + 0x00000002, 0x00000003, + 0x00000000) + + /* MAC two small positive numbers on a small negative total */ + TEST_MACRC (0xffffffff, 0xfffffffa, + 0x00000002, 0x00000003, + 0x00000000) + + /* MAC two small positive numbers on a moderate negative total */ + TEST_MACRC (0xffffffff, 0x00000000, + 0x00000002, 0x00000003, + 0x00000006) + + /* MAC two small positive numbers on a large negative total */ + TEST_MACRC (0x80000000, 0x00000000, + 0x00000002, 0x00000003, + 0x00000006) + + PUTC ('\n') + + /* MAC two moderate positive numbers on a zero total */ + TEST_MACRC (0x00000000, 0x00000000, + 0x00008001, 0x0000fffe, + 0x7ffffffe) + + /* MAC two moderate positive numbers on a small positive total */ + TEST_MACRC (0x00000000, 0x00000002, + 0x00008001, 0x0000fffe, + 0x80000000) + + /* MAC two moderate positive numbers on a moderate positive total */ + TEST_MACRC (0x00000000, 0x80000002, + 0x00008001, 0x0000fffe, + 0x00000000) + + /* MAC two moderate positive numbers on a large positive total */ + TEST_MACRC (0x7fffffff, 0x80000001, + 0x00008001, 0x0000fffe, + 0xffffffff) + + /* MAC two moderate positive numbers on a small negative total */ + TEST_MACRC (0xffffffff, 0xffffffff, + 0x00008001, 0x0000fffe, + 0x7ffffffd) + + /* MAC two moderate positive numbers on a moderate negative total */ + TEST_MACRC (0xffffffff, 0x80000002, + 0x00008001, 0x0000fffe, + 0x00000000) + + /* MAC two moderate positive numbers on a large negative total */ + TEST_MACRC (0xfffffffe, 0x80000002, + 0x00008001, 0x0000fffe, + 0x00000000) + + PUTC ('\n') + + /* MAC two small negative numbers on a zero total */ + TEST_MACRC (0x00000000, 0x00000000, + 0xfffffffe, 0xfffffffd, + 0x00000006) + + /* MAC two small negative numbers on a small positive total */ + TEST_MACRC (0x00000000, 0x00000006, + 0xfffffffe, 0xfffffffd, + 0x0000000c) + + /* MAC two small negative numbers on a small negative total */ + TEST_MACRC (0xffffffff, 0xffffffff, + 0xfffffffe, 0xfffffffd, + 0x00000005) + + PUTC ('\n') + + /* MAC one small positive and one small negative number on a zero + total */ + TEST_MACRC (0x00000000, 0x00000000, + 0x00000002, 0xfffffffd, + 0xfffffffa) + + /* MAC one small positive and one small negative number on a small + positive total */ + TEST_MACRC (0x00000000, 0x0000000c, + 0x00000002, 0xfffffffd, + 0x00000006) + + /* MAC one small positive and one small negative number on a moderate + positive total */ + TEST_MACRC (0x00000001, 0x00000005, + 0x00000002, 0xfffffffd, + 0xffffffff) + + /* MAC one small positive and one small negative number on a large + positive total */ + TEST_MACRC (0x7fffffff, 0xffffffff, + 0x00000002, 0xfffffffd, + 0xfffffff9) + + /* MAC one small positive and one small negative number on a small + negative total */ + TEST_MACRC (0xffffffff, 0xffffffff, + 0x00000002, 0xfffffffd, + 0xfffffff9) + + /* MAC one small positive and one small negative number on a moderate + negative total */ + TEST_MACRC (0xffffffff, 0x00000005, + 0x00000002, 0xfffffffd, + 0xffffffff) + + /* MAC one small positive and one small negative number on a large + negative total */ + TEST_MACRC (0x80000000, 0x00000006, + 0x00000002, 0xfffffffd, + 0x00000000) + + PUTC ('\n') + + /* MAC one moderate positive and one moderate negative number on a + zero total */ + TEST_MACRC (0x00000000, 0x00000000, + 0x00008000, 0xffff0000, + 0x80000000) + + /* MAC one moderate positive and one moderate negative number on a + small positive total */ + TEST_MACRC (0x00000000, 0x00000006, + 0x00008000, 0xffff0000, + 0x80000006) + + /* MAC one moderate positive and one moderate negative number on a + moderate positive total */ + TEST_MACRC (0x00000000, 0x80000000, + 0x00008000, 0xffff0000, + 0x00000000) + + /* MAC one moderate positive and one moderate negative number on a + large positive total */ + TEST_MACRC (0x7fffffff, 0xffffffff, + 0x00008000, 0xffff0000, + 0x7fffffff) + + /* MAC one moderate positive and one moderate negative number on a + small negative total */ + TEST_MACRC (0xffffffff, 0xffffffff, + 0x00008000, 0xffff0000, + 0x7fffffff) + + /* MAC one moderate positive and one moderate negative number on a + moderate negative total */ + TEST_MACRC (0xffffffff, 0x7fffffff, + 0x00008000, 0xffff0000, + 0xffffffff) + + /* MAC one moderate positive and one moderate negative number on a + large negative total */ + TEST_MACRC (0x80000000, 0x80000000, + 0x00008000, 0xffff0000, + 0x00000000) + + PUTC ('\n') + +/* ---------------------------------------------------------------------------- + * Test of multiply signed and accumulate, l.msb + * ------------------------------------------------------------------------- */ +_msb: + LOAD_STR (r3, "l.msb\n") + l.jal _puts + l.nop + + /* MSB two small positive numbers on a zero total */ + TEST_MSB (0x00000000, 0x00000000, + 0x00000002, 0x00000003, + 0xffffffff, 0xfffffffa) + + /* MSB two small positive numbers on a small positive total */ + TEST_MSB (0x00000000, 0x0000000c, + 0x00000002, 0x00000003, + 0x00000000, 0x00000006) + + /* MSB two small positive numbers on a moderate positive total */ + TEST_MSB (0x00000001, 0x00000000, + 0x00000002, 0x00000003, + 0x00000000, 0xfffffffa) + + /* MSB two small positive numbers on a large positive total */ + TEST_MSB (0x40000000, 0x00000000, + 0x00000002, 0x00000003, + 0x3fffffff, 0xfffffffa) + + /* MSB two small positive numbers on a small negative total */ + TEST_MSB (0xffffffff, 0xfffffffa, + 0x00000002, 0x00000003, + 0xffffffff, 0xfffffff4) + + /* MSB two small positive numbers on a moderate negative total */ + TEST_MSB (0xffffffff, 0x00000005, + 0x00000002, 0x00000003, + 0xfffffffe, 0xffffffff) + + /* MSB two small positive numbers on a large negative total */ + TEST_MSB (0x80000000, 0x00000006, + 0x00000002, 0x00000003, + 0x80000000, 0x00000000) + + PUTC ('\n') + + /* MSB two moderate positive numbers on a zero total */ + TEST_MSB (0x00000000, 0x00000000, + 0x00008001, 0x0000fffe, + 0xffffffff, 0x80000002) + + /* MSB two moderate positive numbers on a small positive total */ + TEST_MSB (0x00000000, 0x00000002, + 0x00008001, 0x0000fffe, + 0xffffffff, 0x80000004) + + /* MSB two moderate positive numbers on a moderate positive total */ + TEST_MSB (0x00000000, 0x80000002, + 0x00008001, 0x0000fffe, + 0x00000000, 0x00000004) + + /* MSB two moderate positive numbers on a large positive total */ + TEST_MSB (0x7fffffff, 0x7ffffffd, + 0x00008001, 0x0000fffe, + 0x7ffffffe, 0xffffffff) + + /* MSB two moderate positive numbers on a small negative total */ + TEST_MSB (0xffffffff, 0xffffffff, + 0x00008001, 0x0000fffe, + 0xffffffff, 0x80000001) + + /* MSB two moderate positive numbers on a moderate negative total */ + TEST_MSB (0xffffffff, 0x80000002, + 0x00008001, 0x0000fffe, + 0xffffffff, 0x00000004) + + /* MSB two moderate positive numbers on a large negative total */ + TEST_MSB (0xfffffffe, 0x80000002, + 0x00008001, 0x0000fffe, + 0xfffffffe, 0x00000004) + + PUTC ('\n') + + /* MSB two small negative numbers on a zero total */ + TEST_MSB (0x00000000, 0x00000006, + 0xfffffffe, 0xfffffffd, + 0x00000000, 0x00000000) + + /* MSB two small negative numbers on a small positive total */ + TEST_MSB (0x00000000, 0x0000000c, + 0xfffffffe, 0xfffffffd, + 0x00000000, 0x00000006) + + /* MSB two small negative numbers on a small negative total */ + TEST_MSB (0xffffffff, 0xffffffff, + 0xfffffffe, 0xfffffffd, + 0xffffffff, 0xfffffff9) + + PUTC ('\n') + + /* MSB one small positive and one small negative number on a zero + total */ + TEST_MSB (0x00000000, 0x00000000, + 0x00000002, 0xfffffffd, + 0x00000000, 0x00000006) + + /* MSB one small positive and one small negative number on a small + positive total */ + TEST_MSB (0x00000000, 0x00000006, + 0x00000002, 0xfffffffd, + 0x00000000, 0x0000000c) + + /* MSB one small positive and one small negative number on a moderate + positive total */ + TEST_MSB (0x00000000, 0xffffffff, + 0x00000002, 0xfffffffd, + 0x00000001, 0x00000005) + + /* MSB one small positive and one small negative number on a large + positive total */ + TEST_MSB (0x7fffffff, 0xfffffff9, + 0x00000002, 0xfffffffd, + 0x7fffffff, 0xffffffff) + + /* MSB one small positive and one small negative number on a small + negative total */ + TEST_MSB (0xffffffff, 0xfffffff9, + 0x00000002, 0xfffffffd, + 0xffffffff, 0xffffffff) + + /* MSB one small positive and one small negative number on a moderate + negative total */ + TEST_MSB (0xfffffffe, 0xffffffff, + 0x00000002, 0xfffffffd, + 0xffffffff, 0x00000005) + + /* MSB one small positive and one small negative number on a large + negative total */ + TEST_MSB (0x80000000, 0x00000000, + 0x00000002, 0xfffffffd, + 0x80000000, 0x00000006) + + PUTC ('\n') + + /* MSB one moderate positive and one moderate negative number on a + zero total */ + TEST_MSB (0x00000000, 0x00000000, + 0x00008000, 0xffff0000, + 0x00000000, 0x80000000) + + /* MSB one moderate positive and one moderate negative number on a + small positive total */ + TEST_MSB (0x00000000, 0x00000006, + 0x00008000, 0xffff0000, + 0x00000000, 0x80000006) + + /* MSB one moderate positive and one moderate negative number on a + moderate positive total */ + TEST_MSB (0x00000000, 0x80000000, + 0x00008000, 0xffff0000, + 0x00000001, 0x00000000) + + /* MSB one moderate positive and one moderate negative number on a + large positive total */ + TEST_MSB (0x7fffffff, 0x7fffffff, + 0x00008000, 0xffff0000, + 0x7fffffff, 0xffffffff) + + /* MSB one moderate positive and one moderate negative number on a + small negative total */ + TEST_MSB (0xffffffff, 0xffffffff, + 0x00008000, 0xffff0000, + 0x00000000, 0x7fffffff) + + /* MSB one moderate positive and one moderate negative number on a + moderate negative total */ + TEST_MSB (0xfffffffe, 0xffffffff, + 0x00008000, 0xffff0000, + 0xffffffff, 0x7fffffff) + + /* MSB one moderate positive and one moderate negative number on a + large negative total */ + TEST_MSB (0x80000000, 0x00000000, + 0x00008000, 0xffff0000, + 0x80000000, 0x80000000) + + PUTC ('\n') + +/* ---------------------------------------------------------------------------- + * All done + * ------------------------------------------------------------------------- */ +_exit: + LOAD_STR (r3, "Test completed\n") + l.jal _puts + l.nop + + TEST_EXIT

is-mac-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: inst-set-test.h =================================================================== --- inst-set-test.h (nonexistent) +++ inst-set-test.h (revision 347) @@ -0,0 +1,386 @@ +/* inst-set-test.h. Macros for instruction set testing + + Copyright (C) 1999-2006 OpenCores + Copyright (C) 2010 Embecosm Limited + + Contributors various OpenCores participants + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + + +#include "spr-defs.h" +#include "board.h" + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + + +/* ---------------------------------------------------------------------------- + * Useful constants + * ------------------------------------------------------------------------- */ + +/* Indicator of completion */ +#define ALL_DONE (0xdeaddead) + +/* Logical values */ +#define TRUE 1 +#define FALSE 0 + + +/* ---------------------------------------------------------------------------- + * Macro to push a register onto the stack + * + * r1 points to the next free slot. Push the supplied register on, then + * advance the stack pointer. + * + * Arguments: + * reg The register to push + * + * Registers modified + * r1 + * ------------------------------------------------------------------------- */ +#define PUSH(reg) \ + l.sw 0(r1),reg /* Push */ ;\ + l.addi r1,r1,4 /* Advance the stack */ + +/* ---------------------------------------------------------------------------- + * Macro to pop a register off the stack + * + * r1 points to the next free slot. Decrement the stack pointer, then pop the + * requested register. + * + * Arguments: + * reg The register to pop + * + * Registers modified + * r1 + * ------------------------------------------------------------------------- */ +#define POP(reg) \ + l.addi r1,r1,-4 /* Decrement the stack */ ;\ + l.lws reg,0(r1) /* Pop */ + +/* ---------------------------------------------------------------------------- + * Macro to load a 32-bit constant into a register + * + * Arguments: + * reg The register to load + * val The value to load + * + * ------------------------------------------------------------------------- */ +#define LOAD_CONST(reg,val) \ + l.movhi reg,hi(val) ;\ + l.ori reg,reg,lo(val) + +/* ---------------------------------------------------------------------------- + * Macro to define and load a pointer to a string + * + * Arguments: + * reg The register to load + * str The string + * + * ------------------------------------------------------------------------- */ +#define LOAD_STR(reg,str) \ + .section .rodata ;\ +1: ;\ + .string str ;\ + ;\ + .section .text ;\ + l.movhi reg,hi(1b) ;\ + l.ori reg,reg,lo(1b) + +/* ---------------------------------------------------------------------------- + * Macro to print a character + * + * Arguments: + * c The character to print + * ------------------------------------------------------------------------- */ +#define PUTC(c) \ + l.addi r3,r0,c ;\ + l.nop NOP_PUTC + +/* ---------------------------------------------------------------------------- + * Macro to print a string + * + * Arguments: + * s The string to print + * ------------------------------------------------------------------------- */ +#define PUTS(s) \ + LOAD_STR (r3, s) ;\ + PUSH (r9) ;\ + l.jal _puts ;\ + l.nop ;\ + POP (r9) + +/* ---------------------------------------------------------------------------- + * Macro to print a hex value + * + * Arguments: + * v The value to print + * ------------------------------------------------------------------------- */ +#define PUTH(v) \ + LOAD_CONST (r3, v) ;\ + PUSH (r9) ;\ + l.jal _puth ;\ + l.nop ;\ + POP (r9) + +/* ---------------------------------------------------------------------------- + * Macro to print a half word hex value + * + * Arguments: + * v The value to print + * ------------------------------------------------------------------------- */ +#define PUTHH(v) \ + LOAD_CONST (r3, v) ;\ + PUSH (r9) ;\ + l.jal _puthh ;\ + l.nop ;\ + POP (r9) + +/* ---------------------------------------------------------------------------- + * Macro to print a byte hex value + * + * Arguments: + * v The value to print + * ------------------------------------------------------------------------- */ +#define PUTHQ(v) \ + LOAD_CONST (r3, v) ;\ + PUSH (r9) ;\ + l.jal _puthq ;\ + l.nop ;\ + POP (r9) + +/* ---------------------------------------------------------------------------- + * Macro for recording the result of a test + * + * The test result is in reg. Print out the name of test indented two spaces, + * followed by ": ", either "OK" or "Failed" and a newline. + * + * Arguments: + * str Textual name of the test + * reg The result to test (not r2) + * val Desired result of the test + * ------------------------------------------------------------------------- */ +#define CHECK_RES(str,reg,val) \ + .section .rodata ;\ +2: ;\ + .string str ;\ + ;\ + .section .text ;\ + PUSH (reg) /* Save the register to test */ ;\ + ;\ + LOAD_CONST (r3,2b) /* Print out the string */ ;\ + l.jal _ptest ;\ + l.nop ;\ + ;\ + LOAD_CONST(r2,val) /* The desired result */ ;\ + POP (reg) /* The register to test */ ;\ + PUSH (reg) /* May need again later */ ;\ + l.sfeq r2,reg /* Does the result match? */ ;\ + l.bf 3f ;\ + l.nop ;\ + ;\ + l.jal _pfail /* Test failed */ ;\ + l.nop ;\ + POP (reg) /* Report the register */ ;\ + l.add r3,r0,reg ;\ + l.j 4f ;\ + l.nop NOP_REPORT ;\ +3: ;\ + POP (reg) /* Discard the register */ ;\ + l.jal _pok /* Test succeeded */ ;\ + l.nop ;\ +4: + +/* ---------------------------------------------------------------------------- + * Macro for recording the result of a comparison + * + * If the flag is set print the string argument indented by 2 spaces, followed + * by "TRUE" and a newline, otherwise print the string argument indented by + * two spaces, followed by "FALSE" and a newline. + * + * Arguments: + * str Textual name of the test + * res Expected result (TRUE or FALSE) + * ------------------------------------------------------------------------- */ +#define CHECK_FLAG(str,res) \ + .section .rodata ;\ +5: ;\ + .string str ;\ + ;\ + .section .text ;\ + l.bnf 7f /* Branch if result FALSE */ ;\ + ;\ + /* Branch for TRUE result */ ;\ + LOAD_CONST (r3,5b) /* The string to print */ ;\ + l.jal _ptest ;\ + l.nop ;\ + ;\ + l.addi r2,r0,TRUE /* Was it expected? */ ;\ + l.addi r3,r0,res ;\ + l.sfeq r2,r3 ;\ + l.bnf 6f /* Branch if not expected */ ;\ + ;\ + /* Sub-branch for TRUE found and expected */ ;\ + l.jal _ptrue ;\ + l.nop ;\ + PUTC ('\n') ;\ + l.j 9f ;\ + l.nop ;\ +6: ;\ + /* Sub-branch for TRUE found and not expected */ ;\ + l.jal _ptrue ;\ + l.nop ;\ + l.jal _punexpected ;\ + l.nop ;\ + l.j 9f ;\ + l.nop ;\ + ;\ +7: ;\ + /* Branch for FALSE result */ ;\ + LOAD_CONST (r3,5b) /* The string to print */ ;\ + l.jal _ptest ;\ + l.nop ;\ + ;\ + l.addi r2,r0,FALSE /* Was it expected? */ ;\ + l.addi r3,r0,res ;\ + l.sfeq r2,r3 ;\ + l.bnf 8f /* Branch if not expected */ ;\ + ;\ + /* Sub-branch for FALSE found and expected */ ;\ + l.jal _pfalse ;\ + l.nop ;\ + PUTC ('\n') ;\ + l.j 9f ;\ + l.nop ;\ +8: ;\ + /* Sub-branch for FALSE found and not expected */ ;\ + l.jal _pfalse ;\ + l.nop ;\ + l.jal _punexpected ;\ + l.nop ;\ +9: + +/* ---------------------------------------------------------------------------- + * Macro for recording the result of a test (in two regs) + * + * The test result is in reg1 and reg2. Print out the name of test indented + * two spaces, followed by ": ", either "OK" or "Failed" and a newline. + * + * Arguments: + * str Textual name of the test + * reg1 The result to test (not r2) + * reg2 The result to test (not r2) + * val1 Desired result of the test + * val2 Desired result of the test + * ------------------------------------------------------------------------- */ +#define CHECK_RES2(reg1, reg2, val1, val2) \ + PUSH (reg2) /* Save the test registers */ ;\ + PUSH (reg1) ;\ + ;\ + LOAD_CONST(r2,val1) /* First desired result */ ;\ + POP (reg1) /* First register to test */ ;\ + PUSH (reg1) /* May need again later */ ;\ + l.sfeq r2,reg1 /* Does the result match? */ ;\ + l.bf 10f ;\ + l.nop ;\ + ;\ + /* First register failed. */ ;\ + l.jal _pfail /* Test failed */ ;\ + l.nop ;\ + POP (reg1) /* Report the registers */ ;\ + l.add r3,r0,reg1 ;\ + l.nop NOP_REPORT ;\ + POP (reg2) /* Report the registers */ ;\ + l.add r3,r0,reg2 ;\ + l.j 12f ;\ + l.nop NOP_REPORT ;\ + ;\ + /* First register matched, check the second */ ;\ +10: ;\ + LOAD_CONST(r2,val2) /* Second desired result */ ;\ + POP (reg1) /* First register to test */ ;\ + POP (reg2) /* Second register to test */ ;\ + PUSH (reg2) /* May need again later */ ;\ + PUSH (reg1) /* May need again later */ ;\ + l.sfeq r2,reg2 /* Does the result match? */ ;\ + l.bf 11f ;\ + l.nop ;\ + ;\ + /* Second register failed. */ ;\ + l.jal _pfail /* Test failed */ ;\ + l.nop ;\ + POP (reg1) /* Report the registers */ ;\ + l.add r3,r0,reg1 ;\ + l.nop NOP_REPORT ;\ + POP (reg2) /* Report the registers */ ;\ + l.add r3,r0,reg2 ;\ + l.j 12f ;\ + l.nop NOP_REPORT ;\ + ;\ + /* Both registers passed */ ;\ +11: ;\ + POP (reg1) /* Discard the registers */ ;\ + POP (reg2) /* Discard the registers */ ;\ + l.jal _pok /* Test succeeded */ ;\ + l.nop ;\ +12: + +/* ---------------------------------------------------------------------------- + * Macro for recording the result of a test + * + * This is a newer version of CHECK_RES, which should eventually become the + * standard macro to use. + * + * The test result is in reg. If it matches the supplied val, print "OK" and a + * newline, otherwise "Failed" and report the value of the register (which will + * be followed by a newline). + * + * Arguments: + * reg The result to test (not r2) + * val Desired result of the test + * ------------------------------------------------------------------------- */ +#define CHECK_RES1(reg,val) \ + LOAD_CONST(r2,val) /* The desired result */ ;\ + PUSH (reg) /* May need again later */ ;\ + l.sfeq r2,reg /* Does the result match? */ ;\ + l.bf 13f ;\ + l.nop ;\ + ;\ + l.jal _pfail /* Test failed */ ;\ + l.nop ;\ + POP (reg) /* Report the register */ ;\ + l.add r3,r0,reg ;\ + l.j 14f ;\ + l.nop NOP_REPORT ;\ +13: ;\ + POP (reg) /* Discard the register */ ;\ + l.jal _pok /* Test succeeded */ ;\ + l.nop ;\ +14: + +/* ---------------------------------------------------------------------------- + * Macro to report 0xdeaddead and then terminate + * ------------------------------------------------------------------------- */ +#define TEST_EXIT \ + l.movhi r3,hi(ALL_DONE) ;\ + l.ori r3,r3,lo(ALL_DONE) ;\ + l.nop NOP_REPORT ;\ + ;\ + l.addi r3,r0,0 ;\ + l.nop NOP_EXIT

inst-set-test.h Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: is-div-test.S =================================================================== --- is-div-test.S (nonexistent) +++ is-div-test.S (revision 347) @@ -0,0 +1,286 @@ +/* is-div-test.S. l.div and l.divu instruction test of Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * Test coverage + * + * The l.div and l.divu instructions should set the carry flag as well as + * triggering an event when divide by zero occurs. + * + * Having fixed the problem, this is (in good software engineering style), a + * regresison test to go with the fix. + * + * This is not a comprehensive test of either instruction (yet). + * + * Of course what is really needed is a comprehensive instruction test... + * ------------------------------------------------------------------------- */ + + +#include "inst-set-test.h" + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of divide signed or unsigned + * + * Arguments + * opc: The opcode + * op1: First operand value + * op2: Second operand value + * res: Expected result + * cy: Expected carry flag + * ov: Expected overflow flag + * ------------------------------------------------------------------------- */ +#define TEST_DIV(opc, op1, op2, res, cy, ov) \ + l.mfspr r3,r0,SPR_SR ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 /* Clear flags */ ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + l.or r4,r0,r0 /* Clear result reg */ ;\ + LOAD_CONST (r5,op1) /* Load numbers to add */ ;\ + LOAD_CONST (r6,op2) ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +50: opc r4,r5,r6 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" / 0x") ;\ + PUTH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (res) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, res) ;\ + ;\ + POP (r2) /* Retrieve SR */ ;\ + PUSH (r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", cy) ;\ + ;\ + POP (r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", ov) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 51f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 52f ;\ + l.nop ;\ + ;\ +51: PUTS (" - exception triggered: FALSE\n") ;\ +52: + + +/* ---------------------------------------------------------------------------- + * Start of code + * ------------------------------------------------------------------------- */ + .section .text + .global _start +_start: + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */ + l.and r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag cleared **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * Test of divide signed, l.div + * ------------------------------------------------------------------------- */ +_div: + LOAD_STR (r3, "l.div\n") + l.jal _puts + l.nop + + /* Divide two positive numbers and check rounding. Should set no + flags. */ + TEST_DIV (l.div, 0x0000000c, 0x00000003, + 0x00000004, FALSE, FALSE) + + TEST_DIV (l.div, 0x0000000b, 0x00000003, + 0x00000003, FALSE, FALSE) + + /* Divide two negative numbers and check rounding. Should set no + flags. */ + TEST_DIV (l.div, 0xfffffff4, 0xfffffffd, + 0x00000004, FALSE, FALSE) + + TEST_DIV (l.div, 0xfffffff5, 0xfffffffd, + 0x00000003, FALSE, FALSE) + + /* Divide a negative number by a positive number and check + rounding. Should set no flags. */ + TEST_DIV (l.div, 0xfffffff4, 0x00000003, + 0xfffffffc, FALSE, FALSE) + + TEST_DIV (l.div, 0xfffffff5, 0x00000003, + 0xfffffffd, FALSE, FALSE) + + /* Divide a positive number by a negative number and check + rounding. Should set no flags. */ + TEST_DIV (l.div, 0x0000000c, 0xfffffffd, + 0xfffffffc, FALSE, FALSE) + + TEST_DIV (l.div, 0x0000000b, 0xfffffffd, + 0xfffffffd, FALSE, FALSE) + + /* Divide by zero. Should set the overflow flag. */ + TEST_DIV (l.div, 0x0000000c, 0x00000000, + 0x00000000, TRUE, FALSE) + + TEST_DIV (l.div, 0xfffffff4, 0x00000000, + 0x00000000, TRUE, FALSE) + + /* Check that range exceptions are triggered */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */ + l.or r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag set **\n") + l.jal _puts + l.nop + + /* Divide by zero. Should set the overflow flag and trigger an + exception. */ + TEST_DIV (l.div, 0x0000000c, 0x00000000, + 0x00000000, TRUE, FALSE) + + TEST_DIV (l.div, 0xfffffff4, 0x00000000, + 0x00000000, TRUE, FALSE) + + /* Finished checking range exceptions */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */ + l.and r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag cleared **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * Test of divide unsigned, l.divu + * ------------------------------------------------------------------------- */ +_divu: + LOAD_STR (r3, "l.divu\n") + l.jal _puts + l.nop + + /* Divide two positive numbers and check rounding. Should set no + flags. */ + TEST_DIV (l.divu, 0x0000000c, 0x00000003, + 0x00000004, FALSE, FALSE) + + TEST_DIV (l.divu, 0x0000000b, 0x00000003, + 0x00000003, FALSE, FALSE) + + /* Divide two numbers that would be negative under 2's complement and + check rounding. Should set no flags. */ + TEST_DIV (l.divu, 0xfffffff4, 0xfffffffd, + 0x00000000, FALSE, FALSE) + + TEST_DIV (l.divu, 0xfffffff5, 0xfffffffd, + 0x00000000, FALSE, FALSE) + + /* Divide a number that would be negative under 2's complement by a + number that would be positive under 2's complement and check + rounding. Should set no flags. */ + TEST_DIV (l.divu, 0xfffffff4, 0x00000003, + 0x55555551, FALSE, FALSE) + + TEST_DIV (l.divu, 0xfffffff5, 0x00000003, + 0x55555551, FALSE, FALSE) + + /* Divide a number that would be positive under 2's complement by a + number that would be negative under 2's complement and check + rounding. Should set no flags. */ + TEST_DIV (l.divu, 0x0000000c, 0xfffffffd, + 0x00000000, FALSE, FALSE) + + TEST_DIV (l.divu, 0x0000000b, 0xfffffffd, + 0x00000000, FALSE, FALSE) + + /* Divide by zero. Should set the overflow flag. */ + TEST_DIV (l.divu, 0x0000000c, 0x00000000, + 0x00000000, TRUE, FALSE) + + TEST_DIV (l.divu, 0xfffffff4, 0x00000000, + 0x00000000, TRUE, FALSE) + + /* Check that range exceptions are triggered */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */ + l.or r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag set **\n") + l.jal _puts + l.nop + + /* Divide by zero. Should set the overflow flag and trigger an + exception. */ + TEST_DIV (l.divu, 0x0000000c, 0x00000000, + 0x00000000, TRUE, FALSE) + + TEST_DIV (l.divu, 0xfffffff4, 0x00000000, + 0x00000000, TRUE, FALSE) + + /* Finished checking range exceptions */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */ + l.and r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag cleared **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * All done + * ------------------------------------------------------------------------- */ +_exit: + LOAD_STR (r3, "Test completed\n") + l.jal _puts + l.nop + + TEST_EXIT

is-div-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: is-lws-test.S =================================================================== --- is-lws-test.S (nonexistent) +++ is-lws-test.S (revision 347) @@ -0,0 +1,125 @@ +/* is-lws-test.S. l.lws instruction test of Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * Test coverage + * + * The l.lws instruction was omitted from Or1ksim originally. It is specified + * for ORBIS32, even though it is functionally equivalent to l.lwz. + * + * Having fixed the problem, this is (in good software engineering style), a + * regresison test to go with the fix. + * + * Of course what is really needed is a comprehensive instruction test... + * ------------------------------------------------------------------------- */ + + +#include "inst-set-test.h" + +/* ---------------------------------------------------------------------------- + * Test of load single word and extend with sign: l.lws + * ------------------------------------------------------------------------- */ + .section .rodata + .balign 4 +50: .word 0xdeadbeef +51: .word 0x00000000 +52: .word 0x7fffffff +53: .word 0x80000000 +54: .word 0xffffffff + + .section .text + .global _start +_start: + LOAD_STR (r3, "l.lws\n") + l.jal _puts + l.nop + + /* Load with zero offset */ + LOAD_CONST (r5,50b) + l.lws r4,0(r5) + CHECK_RES (" l.lws r4,0(r5): r4=0xdeadbeef: ", r4, 0xdeadbeef) + + LOAD_CONST (r5,51b) + l.lws r4,0(r5) + CHECK_RES (" l.lws r4,0(r5): r4=0x00000000: ", r4, 0x00000000) + + LOAD_CONST (r5,52b) + l.lws r4,0(r5) + CHECK_RES (" l.lws r4,0(r5): r4=0x7fffffff: ", r4, 0x7fffffff) + + LOAD_CONST (r5,53b) + l.lws r4,0(r5) + CHECK_RES (" l.lws r4,0(r5): r4=0x80000000: ", r4, 0x80000000) + + LOAD_CONST (r5,54b) + l.lws r4,0(r5) + CHECK_RES (" l.lws r4,0(r5): r4=0xffffffff: ", r4, 0xffffffff) + + /* Load with positive offset */ + LOAD_CONST (r5,50b) + l.lws r4,4(r5) + CHECK_RES (" l.lws r4,0(r5): r4=0x00000000: ", r4, 0x00000000) + + LOAD_CONST (r5,50b) + l.lws r4,8(r5) + CHECK_RES (" l.lws r4,0(r5): r4=0x7fffffff: ", r4, 0x7fffffff) + + LOAD_CONST (r5,50b) + l.lws r4,12(r5) + CHECK_RES (" l.lws r4,0(r5): r4=0x80000000: ", r4, 0x80000000) + + LOAD_CONST (r5,50b) + l.lws r4,16(r5) + CHECK_RES (" l.lws r4,0(r5): r4=0xffffffff: ", r4, 0xffffffff) + + /* Load with negative offset */ + LOAD_CONST (r5,54b) + l.lws r4,-16(r5) + CHECK_RES (" l.lws r4,0(r5): r4=0xdeadbeef: ", r4, 0xdeadbeef) + + LOAD_CONST (r5,54b) + l.lws r4,-12(r5) + CHECK_RES (" l.lws r4,0(r5): r4=0x00000000: ", r4, 0x00000000) + + LOAD_CONST (r5,54b) + l.lws r4,-8(r5) + CHECK_RES (" l.lws r4,0(r5): r4=0x7fffffff: ", r4, 0x7fffffff) + + LOAD_CONST (r5,54b) + l.lws r4,-4(r5) + CHECK_RES (" l.lws r4,0(r5): r4=0x80000000: ", r4, 0x80000000) + +/* ---------------------------------------------------------------------------- + * All done + * ------------------------------------------------------------------------- */ +_exit: + LOAD_STR (r3, "Test completed\n") + l.jal _puts + l.nop + + TEST_EXIT

is-lws-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: inst-set-test-old.c =================================================================== --- inst-set-test-old.c (nonexistent) +++ inst-set-test-old.c (revision 347) @@ -0,0 +1,296 @@ +/* inst-set-test.c. Instruction set test for Or1ksim + + Copyright (C) 1999-2006 OpenCores + Copyright (C) 2010 Embecosm Limited + + Contributors various OpenCores participants + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + +/* ---------------------------------------------------------------------------- + This code is commented throughout for use with Doxygen. + --------------------------------------------------------------------------*/ + +/* This is a complex instruction test for OR1200 */ +/* trap, movhi, mul, nop, rfe, sys instructions not tested*/ +/* Currently not working. Compiles with warnings, runs with errors. */ + +#include "support.h" + +volatile unsigned long test = 0xdeaddead; + +#define TEST_32(c1,c2,val1,val2,op) \ + test ^= ((c1 (val1)) op (c2 (val2))); test ^= ((c1 (val2)) op (c2 (val1)));\ + test ^= ((c1 (val1)) op (c2 (val2))); test ^= ((c1 (val2)) op (c2 (val1)));\ + test ^= ((c1 (val1)) op (c2 (val2))); test ^= ((c1 (val2)) op (c2 (val1)));\ + test ^= ((c1 (val1)) op (c2 (val2))); test ^= ((c1 (val2)) op (c2 (val1)));\ + test ^= ((c1 (val1)) op (c2 (val2))); test ^= ((c1 (val2)) op (c2 (val1)));\ + test ^= ((c1 (val1)) op (c2 (val2))); test ^= ((c1 (val2)) op (c2 (val1)));\ + test ^= ((c1 (val1)) op (c2 (val2))); test ^= ((c1 (val2)) op (c2 (val1)));\ + test ^= ((c1 (val1)) op (c2 (val2))); test ^= ((c1 (val2)) op (c2 (val1)));\ + +#define TEST_CASTS(val1,val2,op)\ + TEST_32((unsigned long), (unsigned long), val1, val2, op);\ + TEST_32((unsigned long), (signed long), val1, val2, op);\ + TEST_32((unsigned long), (unsigned short), val1, val2, op);\ + TEST_32((unsigned long), (signed short), val1, val2, op);\ + TEST_32((unsigned long), (unsigned char), val1, val2, op);\ + TEST_32((unsigned long), (signed char), val1, val2, op);\ + \ + TEST_32((unsigned short), (unsigned long), val1, val2, op);\ + TEST_32((unsigned short), (signed long), val1, val2, op);\ + TEST_32((unsigned short), (unsigned short), val1, val2, op);\ + TEST_32((unsigned short), (signed short), val1, val2, op);\ + TEST_32((unsigned short), (unsigned char), val1, val2, op);\ + TEST_32((unsigned short), (signed char), val1, val2, op);\ + \ + TEST_32((unsigned char), (unsigned long), val1, val2, op);\ + TEST_32((unsigned char), (signed long), val1, val2, op);\ + TEST_32((unsigned char), (unsigned short), val1, val2, op);\ + TEST_32((unsigned char), (signed short), val1, val2, op)\ + TEST_32((unsigned char), (unsigned char), val1, val2, op);\ + TEST_32((unsigned char), (signed char), val1, val2, op); + + +void add_test () +{ + int i, j; + TEST_CASTS(0x12345678, 0x12345678, +); + TEST_CASTS(0x12345678, 0x87654321, +); + TEST_CASTS(0x87654321, 0x12345678, +); + TEST_CASTS(0x87654321, 0x87654321, +); + + TEST_CASTS(0x1234, -0x1234, +); + TEST_CASTS(0x1234, -0x1234, +); + TEST_CASTS(-0x1234, 0x1234, +); + TEST_CASTS(-0x1234, -0x1234, +); + + for (i = -1; i <= 1; i++) + for (j = -1; j <= 1; j++) + TEST_CASTS (i, j, +); + report (test); +} + +void and_test () +{ +/* TEST_CASTS(0x12345678, 0x12345678, &); + TEST_CASTS(0x12345678, 0x87654321, &); + TEST_CASTS(0x87654321, 0x12345678, &); + TEST_CASTS(0x87654321, 0x87654321, &); + + TEST_CASTS(0x12345678, 0x0, &); + TEST_CASTS(0x12345678, 0xffffffff, &); + TEST_CASTS(0x87654321, 0x80000000, &); + TEST_CASTS(0x87654321, 0x08000000, &); + + TEST_CASTS(0x12345678, 0x12345678, &&); + TEST_CASTS(0x12345678, 0x87654321, &&); + TEST_CASTS(0x87654321, 0x12345678, &&); + TEST_CASTS(0x87654321, 0x87654321, &&); + + TEST_CASTS(0x12345678, 0x0, &&); + TEST_CASTS(0x12345678, 0xffffffff, &&); + TEST_CASTS(0x87654321, 0x80000000, &&); + TEST_CASTS(0x87654321, 0x08000000, &&); + report (test);*/ +} + +void branch_test () +{ + /* bf, bnf, j, jal, jalr, jr, sfeq, sfges, sfgeu, sfgts, sfgtu, sfles, sfleu, sflts, sfltu, sfne */ + report (test); +} + +void load_store_test () +{ + volatile long a; + volatile short b; + volatile char c; + unsigned long *pa = (unsigned long *)&a; + unsigned short *pb = (unsigned short *)&b; + unsigned char *pc = (unsigned char *)&c; + + test ^= a = 0xdeadbeef; + test ^= b = 0x12345678; + test ^= c = 0x87654321; + test ^= a = b; + test ^= b = c; + test ^= a; + test ^= (unsigned long)a; + test ^= (unsigned short)a; + test ^= (unsigned char)a; + + test ^= (unsigned long)b; + test ^= (unsigned short)b; + test ^= (unsigned char)b; + + test ^= (unsigned long)c; + test ^= (unsigned short)c; + test ^= (unsigned char)c; + + test ^= *pa = 0xabcdef12; + test ^= *pb = 0x12345678; + test ^= *pc = 0xdeadbeef; + + test ^= (signed long)c; + test ^= (signed short)c; + test ^= (signed char)c; + + test ^= (signed long)a; + test ^= (signed short)a; + test ^= (signed char)a; + + test ^= (signed long)b; + test ^= (signed short)b; + test ^= (signed char)b; + + test ^= *pa = 0xaabbccdd; + test ^= *pb = 0x56789012; + test ^= *pc = 0xb055b055; + + test ^= (unsigned long)b; + test ^= (signed long)c; + test ^= (unsigned long)a; + test ^= (unsigned short)c; + test ^= (unsigned short)a; + test ^= (unsigned char)c; + test ^= (unsigned short)b; + test ^= (unsigned char)b; + test ^= (unsigned char)a; + report (test); +} + +void or_test () +{ +/* TEST_CASTS(0x12345678, 0x12345678, |); + TEST_CASTS(0x12345678, 0x87654321, |); + TEST_CASTS(0x87654321, 0x12345678, |); + TEST_CASTS(0x87654321, 0x87654321, |); + + TEST_CASTS(0x12345678, 0x0, |); + TEST_CASTS(0x12345678, 0xffffffff, |); + TEST_CASTS(0x87654321, 0x80000000, |); + TEST_CASTS(0x87654321, 0x08000000, |); + + TEST_CASTS(0x12345678, 0x12345678, ||); + TEST_CASTS(0x12345678, 0x87654321, ||); + TEST_CASTS(0x87654321, 0x12345678, ||); + TEST_CASTS(0x87654321, 0x87654321, ||); + + TEST_CASTS(0x12345678, 0x0, ||); + TEST_CASTS(0x12345678, 0xffffffff, ||); + TEST_CASTS(0x87654321, 0x80000000, ||); + TEST_CASTS(0x87654321, 0x08000000, ||);*/ + report (test); +} + +void xor_test () +{ +/* TEST_CASTS(0x12345678, 0x12345678, ^); + TEST_CASTS(0x12345678, 0x87654321, ^); + TEST_CASTS(0x87654321, 0x12345678, ^); + TEST_CASTS(0x87654321, 0x87654321, ^); + + TEST_CASTS(0x12345678, 0x0, ^); + TEST_CASTS(0x12345678, 0xffffffff, ^); + TEST_CASTS(0x87654321, 0x80000000, ^); + TEST_CASTS(0x87654321, 0x08000000, ^);*/ + report (test); +} + +void sll_test () +{ + int i; + for (i = -1; i < 40; i++) + TEST_CASTS(0xdeaf1234, i, <<); + for (i = -1; i < 33; i++) + TEST_CASTS(0x12345678, i, <<); + for (i = -1; i < 33; i++) + TEST_CASTS(0xdea12345, i, <<); + + test ^= (unsigned long)0xabcd4321 << test; + test ^= (signed long)0xabcd4321 << test; + test ^= (unsigned long)0xabcd << test; + test ^= (signed long)0xabcd << test; + report (test); +} + +void srl_sra_test () +{ + int i; + for (i = -1; i < 40; i++) + TEST_CASTS(0xdeaf1234, i, >>); + for (i = -1; i < 33; i++) + TEST_CASTS(0x12345678, i, >>); + for (i = -1; i < 33; i++) + TEST_CASTS(0xdea12345, i, >>); + + test ^= (unsigned long)0xabcd4321 >> test; + test ^= (signed long)0xabcd4321 >> test; + test ^= (unsigned long)0xabcd >> test; + test ^= (signed long)0xabcd >> test; + report (test); +} + + +void ror_test () +{ + unsigned long a; + int i; + for (i = -1; i < 40; i++) { + asm ("l.ror %0, %1, %2" : "=r" (a) : "r" (0x12345678), "r" (i)); + test ^= a; + asm ("l.ror %0, %1, %2" : "=r" (a) : "r" (0xabcdef), "r" (i)); + test ^= a; + } + asm ("l.ror %0, %1, %2" : "=r" (a) : "r" (0x12345678), "r" (0x12345678)); + test ^= a; + report (test); +} + +void sub_test () +{ +/* int i, j; + TEST_CASTS(0x12345678, 0x12345678, -); + TEST_CASTS(0x12345678, 0x87654321, -); + TEST_CASTS(0x87654321, 0x12345678, -); + TEST_CASTS(0x87654321, 0x87654321, -); + + TEST_CASTS(0x1234, -0x1234, -); + TEST_CASTS(0x1234, -0x1234, -); + TEST_CASTS(-0x1234, 0x1234, -); + TEST_CASTS(-0x1234, -0x1234, -); + + for (i = -1; i <= 1; i++) + for (j = -1; j <= 1; j++) + TEST_CASTS (i, j, -); + report (test);*/ +} + +int main () +{ + add_test (); + and_test (); + branch_test (); + load_store_test (); + or_test (); + sll_test (); + srl_sra_test (); + xor_test (); + sub_test (); + return 0; +}

inst-set-test-old.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: inst-set-test.ld =================================================================== --- inst-set-test.ld (nonexistent) +++ inst-set-test.ld (revision 347) @@ -0,0 +1,68 @@ +/* inst-set.ld. Linker script for Or1ksim instruction set test programs + + Copyright (C) 1999-2006 OpenCores + Copyright (C) 2010 Embecosm Limited + + Contributors various OpenCores participants + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + +/* ---------------------------------------------------------------------------- + This code is commented throughout for use with Doxygen. + --------------------------------------------------------------------------*/ + +/* ---------------------------------------------------------------------------- + This is a much simplified linker script for use with instruction set test + programs. In particular they do not use the memory controller. + --------------------------------------------------------------------------*/ + +MEMORY + { + ram : ORIGIN = 0x00000000, LENGTH = 0x00200000 + } + +/* Force _reset to be linked in wherever it is (library or source) */ +EXTERN(_reset) + +SECTIONS +{ + /* Section .boot-text guarantees that the code for exception + handling is placed first. */ + .text : + { + *(.boot-text) + *(.text) + *(.rodata) + } > ram + + .data : + { + *(.data) + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack ALIGN (0x10) (NOLOAD) : + { + *(.stack) + } > ram +} + +ENTRY (_reset)