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Rev 346 → Rev 388
/Makefile.in
0,0 → 1,521
# Makefile.in generated by automake 1.11.1 from Makefile.am. |
# @configure_input@ |
|
# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, |
# Inc. |
# This Makefile.in is free software; the Free Software Foundation |
# gives unlimited permission to copy and/or distribute it, |
# with or without modifications, as long as this notice is preserved. |
|
# This program is distributed in the hope that it will be useful, |
# but WITHOUT ANY WARRANTY, to the extent permitted by law; without |
# even the implied warranty of MERCHANTABILITY or FITNESS FOR A |
# PARTICULAR PURPOSE. |
|
@SET_MAKE@ |
|
# Makefile -- Makefile for OR1K architecture dependent simulation |
# |
# Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
# Copyright (C) 2008 Embecosm Limited |
# |
# Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
# |
# This file is part of OpenRISC 1000 Architectural Simulator. |
# |
# This program is free software; you can redistribute it and/or modify it |
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# Software Foundation; either version 3 of the License, or (at your option) |
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# |
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opcode/or32.h |
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# Tell versions [3.59,3.63) of GNU make to not export all variables. |
# Otherwise a system limit (for SysV at least) may be exceeded. |
.NOEXPORT: |
/spr-defs.h
0,0 → 1,636
/* ipc.h. Microkernel IPC header for Or1ksim |
|
Copyright (C) 2000 Damjan Lampret |
Copyright (C) 2008, 2010 Embecosm Limited |
|
Contributor Damjan Lampret <lampret@opencores.org> |
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify it |
under the terms of the GNU General Public License as published by the Free |
Software Foundation; either version 3 of the License, or (at your option) |
any later version. |
|
This program is distributed in the hope that it will be useful, but WITHOUT |
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
more details. |
|
You should have received a copy of the GNU General Public License along |
with this program. If not, see <http: www.gnu.org/licenses/>. */ |
|
/* ---------------------------------------------------------------------------- |
This code is commented throughout for use with Doxygen. |
--------------------------------------------------------------------------*/ |
|
/* This file is part of test microkernel for OpenRISC 1000. */ |
/* spr-defs.h -- Defines OR1K architecture specific special-purpose registers |
|
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
Copyright (C) 2008 Embecosm Limited |
|
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify it |
under the terms of the GNU General Public License as published by the Free |
Software Foundation; either version 3 of the License, or (at your option) |
any later version. |
|
This program is distributed in the hope that it will be useful, but WITHOUT |
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
more details. |
|
You should have received a copy of the GNU General Public License along |
with this program. If not, see <http://www.gnu.org/licenses/>. */ |
|
/* This program is commented throughout in a fashion suitable for processing |
with Doxygen. */ |
|
|
#ifndef SPR_DEFS__H |
#define SPR_DEFS__H |
|
/* Definition of special-purpose registers (SPRs). */ |
|
#define MAX_GRPS (32) |
#define MAX_SPRS_PER_GRP_BITS (11) |
#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS) |
#define MAX_SPRS (0x10000) |
|
/* Base addresses for the groups */ |
#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_FP (11<< MAX_SPRS_PER_GRP_BITS) |
|
/* System control and status group */ |
#define SPR_VR (SPRGROUP_SYS + 0) |
#define SPR_UPR (SPRGROUP_SYS + 1) |
#define SPR_CPUCFGR (SPRGROUP_SYS + 2) |
#define SPR_DMMUCFGR (SPRGROUP_SYS + 3) |
#define SPR_IMMUCFGR (SPRGROUP_SYS + 4) |
#define SPR_DCCFGR (SPRGROUP_SYS + 5) |
#define SPR_ICCFGR (SPRGROUP_SYS + 6) |
#define SPR_DCFGR (SPRGROUP_SYS + 7) |
#define SPR_PCCFGR (SPRGROUP_SYS + 8) |
#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */ |
#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */ |
#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */ |
#define SPR_FPCSR (SPRGROUP_SYS + 20) /* CZ 21/06/01 */ |
#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */ |
#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */ |
#define SPR_EEAR_BASE (SPRGROUP_SYS + 48) |
#define SPR_EEAR_LAST (SPRGROUP_SYS + 63) |
#define SPR_ESR_BASE (SPRGROUP_SYS + 64) |
#define SPR_ESR_LAST (SPRGROUP_SYS + 79) |
#define SPR_GPR_BASE (SPRGROUP_SYS + 1024) |
|
/* Data MMU group */ |
#define SPR_DMMUCR (SPRGROUP_DMMU + 0) |
#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) |
#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) |
#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) |
#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) |
|
/* Instruction MMU group */ |
#define SPR_IMMUCR (SPRGROUP_IMMU + 0) |
#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) |
#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100) |
#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100) |
#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100) |
|
/* Data cache group */ |
#define SPR_DCCR (SPRGROUP_DC + 0) |
#define SPR_DCBPR (SPRGROUP_DC + 1) |
#define SPR_DCBFR (SPRGROUP_DC + 2) |
#define SPR_DCBIR (SPRGROUP_DC + 3) |
#define SPR_DCBWR (SPRGROUP_DC + 4) |
#define SPR_DCBLR (SPRGROUP_DC + 5) |
#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) |
#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) |
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/* Instruction cache group */ |
#define SPR_ICCR (SPRGROUP_IC + 0) |
#define SPR_ICBPR (SPRGROUP_IC + 1) |
#define SPR_ICBIR (SPRGROUP_IC + 2) |
#define SPR_ICBLR (SPRGROUP_IC + 3) |
#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200) |
#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200) |
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/* MAC group */ |
#define SPR_MACLO (SPRGROUP_MAC + 1) |
#define SPR_MACHI (SPRGROUP_MAC + 2) |
|
/* Debug group */ |
#define SPR_DVR(N) (SPRGROUP_D + (N)) |
#define SPR_DCR(N) (SPRGROUP_D + 8 + (N)) |
#define SPR_DMR1 (SPRGROUP_D + 16) |
#define SPR_DMR2 (SPRGROUP_D + 17) |
#define SPR_DWCR0 (SPRGROUP_D + 18) |
#define SPR_DWCR1 (SPRGROUP_D + 19) |
#define SPR_DSR (SPRGROUP_D + 20) |
#define SPR_DRR (SPRGROUP_D + 21) |
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/* Performance counters group */ |
#define SPR_PCCR(N) (SPRGROUP_PC + (N)) |
#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N)) |
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/* Power management group */ |
#define SPR_PMR (SPRGROUP_PM + 0) |
|
/* PIC group */ |
#define SPR_PICMR (SPRGROUP_PIC + 0) |
#define SPR_PICPR (SPRGROUP_PIC + 1) |
#define SPR_PICSR (SPRGROUP_PIC + 2) |
|
/* Tick Timer group */ |
#define SPR_TTMR (SPRGROUP_TT + 0) |
#define SPR_TTCR (SPRGROUP_TT + 1) |
|
/* |
* Bit definitions for the Version Register |
* |
*/ |
#define SPR_VR_VER 0xff000000 /* Processor version */ |
#define SPR_VR_CFG 0x00ff0000 /* Processor configuration */ |
#define SPR_VR_RES 0x0000ffc0 /* Reserved */ |
#define SPR_VR_REV 0x0000003f /* Processor revision */ |
|
#define SPR_VR_VER_OFF 24 |
#define SPR_VR_CFG_OFF 16 |
#define SPR_VR_REV_OFF 0 |
|
/* |
* Bit definitions for the Unit Present Register |
* |
*/ |
#define SPR_UPR_UP 0x00000001 /* UPR present */ |
#define SPR_UPR_DCP 0x00000002 /* Data cache present */ |
#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */ |
#define SPR_UPR_DMP 0x00000008 /* Data MMU present */ |
#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */ |
#define SPR_UPR_MP 0x00000020 /* MAC present */ |
#define SPR_UPR_DUP 0x00000040 /* Debug unit present */ |
#define SPR_UPR_PCUP 0x00000080 /* Performance counters unit present */ |
#define SPR_UPR_PMP 0x00000100 /* Power management present */ |
#define SPR_UPR_PICP 0x00000200 /* PIC present */ |
#define SPR_UPR_TTP 0x00000400 /* Tick timer present */ |
#define SPR_UPR_RES 0x00fe0000 /* Reserved */ |
#define SPR_UPR_CUP 0xff000000 /* Context units present */ |
|
/* |
* JPB: Bit definitions for the CPU configuration register |
* |
*/ |
#define SPR_CPUCFGR_NSGF 0x0000000f /* Number of shadow GPR files */ |
#define SPR_CPUCFGR_CGF 0x00000010 /* Custom GPR file */ |
#define SPR_CPUCFGR_OB32S 0x00000020 /* ORBIS32 supported */ |
#define SPR_CPUCFGR_OB64S 0x00000040 /* ORBIS64 supported */ |
#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */ |
#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */ |
#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */ |
#define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */ |
|
/* |
* JPB: Bit definitions for the Debug configuration register and other |
* constants. |
* |
*/ |
|
#define SPR_DCFGR_NDP 0x00000007 /* Number of matchpoints mask */ |
#define SPR_DCFGR_NDP1 0x00000000 /* One matchpoint supported */ |
#define SPR_DCFGR_NDP2 0x00000001 /* Two matchpoints supported */ |
#define SPR_DCFGR_NDP3 0x00000002 /* Three matchpoints supported */ |
#define SPR_DCFGR_NDP4 0x00000003 /* Four matchpoints supported */ |
#define SPR_DCFGR_NDP5 0x00000004 /* Five matchpoints supported */ |
#define SPR_DCFGR_NDP6 0x00000005 /* Six matchpoints supported */ |
#define SPR_DCFGR_NDP7 0x00000006 /* Seven matchpoints supported */ |
#define SPR_DCFGR_NDP8 0x00000007 /* Eight matchpoints supported */ |
#define SPR_DCFGR_WPCI 0x00000008 /* Watchpoint counters implemented */ |
|
#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \ |
2 == n ? SPR_DCFGR_NDP2 : \ |
3 == n ? SPR_DCFGR_NDP3 : \ |
4 == n ? SPR_DCFGR_NDP4 : \ |
5 == n ? SPR_DCFGR_NDP5 : \ |
6 == n ? SPR_DCFGR_NDP6 : \ |
7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8) |
#define MAX_MATCHPOINTS 8 |
#define MAX_WATCHPOINTS (MAX_MATCHPOINTS + 2) |
|
/* |
* Bit definitions for the Supervision Register |
* |
*/ |
#define SPR_SR_SM 0x00000001 /* Supervisor Mode */ |
#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */ |
#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */ |
#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */ |
#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */ |
#define SPR_SR_DME 0x00000020 /* Data MMU Enable */ |
#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */ |
#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */ |
#define SPR_SR_CE 0x00000100 /* CID Enable */ |
#define SPR_SR_F 0x00000200 /* Condition Flag */ |
#define SPR_SR_CY 0x00000400 /* Carry flag */ |
#define SPR_SR_OV 0x00000800 /* Overflow flag */ |
#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */ |
#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */ |
#define SPR_SR_EPH 0x00004000 /* Exception Prefix High */ |
#define SPR_SR_FO 0x00008000 /* Fixed one */ |
#define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */ |
#define SPR_SR_RES 0x0ffe0000 /* Reserved */ |
#define SPR_SR_CID 0xf0000000 /* Context ID */ |
|
/* |
* Bit definitions for the Data MMU Control Register |
* |
*/ |
#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */ |
#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ |
#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ |
#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ |
|
/* |
* Bit definitions for the Instruction MMU Control Register |
* |
*/ |
#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */ |
#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ |
#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ |
#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ |
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/* |
* Bit definitions for the Data TLB Match Register |
* |
*/ |
#define SPR_DTLBMR_V 0x00000001 /* Valid */ |
#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ |
#define SPR_DTLBMR_CID 0x0000003c /* Context ID */ |
#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */ |
#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */ |
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/* |
* Bit definitions for the Data TLB Translate Register |
* |
*/ |
#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */ |
#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */ |
#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */ |
#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ |
#define SPR_DTLBTR_A 0x00000010 /* Accessed */ |
#define SPR_DTLBTR_D 0x00000020 /* Dirty */ |
#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */ |
#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */ |
#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */ |
#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */ |
#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */ |
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/* |
* Bit definitions for the Instruction TLB Match Register |
* |
*/ |
#define SPR_ITLBMR_V 0x00000001 /* Valid */ |
#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ |
#define SPR_ITLBMR_CID 0x0000003c /* Context ID */ |
#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */ |
#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */ |
|
/* |
* Bit definitions for the Instruction TLB Translate Register |
* |
*/ |
#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */ |
#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */ |
#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */ |
#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ |
#define SPR_ITLBTR_A 0x00000010 /* Accessed */ |
#define SPR_ITLBTR_D 0x00000020 /* Dirty */ |
#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */ |
#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */ |
#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */ |
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/* |
* Bit definitions for Data Cache Control register |
* |
*/ |
#define SPR_DCCR_EW 0x000000ff /* Enable ways */ |
|
/* |
* Bit definitions for Insn Cache Control register |
* |
*/ |
#define SPR_ICCR_EW 0x000000ff /* Enable ways */ |
|
/* |
* Bit definitions for Data Cache Configuration Register |
* |
*/ |
|
#define SPR_DCCFGR_NCW 0x00000007 |
#define SPR_DCCFGR_NCS 0x00000078 |
#define SPR_DCCFGR_CBS 0x00000080 |
#define SPR_DCCFGR_CWS 0x00000100 |
#define SPR_DCCFGR_CCRI 0x00000200 |
#define SPR_DCCFGR_CBIRI 0x00000400 |
#define SPR_DCCFGR_CBPRI 0x00000800 |
#define SPR_DCCFGR_CBLRI 0x00001000 |
#define SPR_DCCFGR_CBFRI 0x00002000 |
#define SPR_DCCFGR_CBWBRI 0x00004000 |
|
#define SPR_DCCFGR_NCW_OFF 0 |
#define SPR_DCCFGR_NCS_OFF 3 |
#define SPR_DCCFGR_CBS_OFF 7 |
|
/* |
* Bit definitions for Instruction Cache Configuration Register |
* |
*/ |
#define SPR_ICCFGR_NCW 0x00000007 |
#define SPR_ICCFGR_NCS 0x00000078 |
#define SPR_ICCFGR_CBS 0x00000080 |
#define SPR_ICCFGR_CCRI 0x00000200 |
#define SPR_ICCFGR_CBIRI 0x00000400 |
#define SPR_ICCFGR_CBPRI 0x00000800 |
#define SPR_ICCFGR_CBLRI 0x00001000 |
|
#define SPR_ICCFGR_NCW_OFF 0 |
#define SPR_ICCFGR_NCS_OFF 3 |
#define SPR_ICCFGR_CBS_OFF 7 |
|
/* |
* Bit definitions for Data MMU Configuration Register |
* |
*/ |
|
#define SPR_DMMUCFGR_NTW 0x00000003 |
#define SPR_DMMUCFGR_NTS 0x0000001C |
#define SPR_DMMUCFGR_NAE 0x000000E0 |
#define SPR_DMMUCFGR_CRI 0x00000100 |
#define SPR_DMMUCFGR_PRI 0x00000200 |
#define SPR_DMMUCFGR_TEIRI 0x00000400 |
#define SPR_DMMUCFGR_HTR 0x00000800 |
|
#define SPR_DMMUCFGR_NTW_OFF 0 |
#define SPR_DMMUCFGR_NTS_OFF 2 |
|
/* |
* Bit definitions for Instruction MMU Configuration Register |
* |
*/ |
|
#define SPR_IMMUCFGR_NTW 0x00000003 |
#define SPR_IMMUCFGR_NTS 0x0000001C |
#define SPR_IMMUCFGR_NAE 0x000000E0 |
#define SPR_IMMUCFGR_CRI 0x00000100 |
#define SPR_IMMUCFGR_PRI 0x00000200 |
#define SPR_IMMUCFGR_TEIRI 0x00000400 |
#define SPR_IMMUCFGR_HTR 0x00000800 |
|
#define SPR_IMMUCFGR_NTW_OFF 0 |
#define SPR_IMMUCFGR_NTS_OFF 2 |
|
/* |
* Bit definitions for Debug Control registers |
* |
*/ |
#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */ |
#define SPR_DCR_CC 0x0000000e /* Compare condition */ |
#define SPR_DCR_SC 0x00000010 /* Signed compare */ |
#define SPR_DCR_CT 0x000000e0 /* Compare to */ |
|
/* Bit results with SPR_DCR_CC mask */ |
#define SPR_DCR_CC_MASKED 0x00000000 |
#define SPR_DCR_CC_EQUAL 0x00000002 |
#define SPR_DCR_CC_LESS 0x00000004 |
#define SPR_DCR_CC_LESSE 0x00000006 |
#define SPR_DCR_CC_GREAT 0x00000008 |
#define SPR_DCR_CC_GREATE 0x0000000a |
#define SPR_DCR_CC_NEQUAL 0x0000000c |
|
/* Bit results with SPR_DCR_CT mask */ |
#define SPR_DCR_CT_DISABLED 0x00000000 |
#define SPR_DCR_CT_IFEA 0x00000020 |
#define SPR_DCR_CT_LEA 0x00000040 |
#define SPR_DCR_CT_SEA 0x00000060 |
#define SPR_DCR_CT_LD 0x00000080 |
#define SPR_DCR_CT_SD 0x000000a0 |
#define SPR_DCR_CT_LSEA 0x000000c0 |
#define SPR_DCR_CT_LSD 0x000000e0 |
/* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */ |
|
/* |
* Bit definitions for Debug Mode 1 register |
* |
*/ |
#define SPR_DMR1_CW 0x000fffff /* Chain register pair data */ |
#define SPR_DMR1_CW0_AND 0x00000001 |
#define SPR_DMR1_CW0_OR 0x00000002 |
#define SPR_DMR1_CW0 (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR) |
#define SPR_DMR1_CW1_AND 0x00000004 |
#define SPR_DMR1_CW1_OR 0x00000008 |
#define SPR_DMR1_CW1 (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR) |
#define SPR_DMR1_CW2_AND 0x00000010 |
#define SPR_DMR1_CW2_OR 0x00000020 |
#define SPR_DMR1_CW2 (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR) |
#define SPR_DMR1_CW3_AND 0x00000040 |
#define SPR_DMR1_CW3_OR 0x00000080 |
#define SPR_DMR1_CW3 (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR) |
#define SPR_DMR1_CW4_AND 0x00000100 |
#define SPR_DMR1_CW4_OR 0x00000200 |
#define SPR_DMR1_CW4 (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR) |
#define SPR_DMR1_CW5_AND 0x00000400 |
#define SPR_DMR1_CW5_OR 0x00000800 |
#define SPR_DMR1_CW5 (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR) |
#define SPR_DMR1_CW6_AND 0x00001000 |
#define SPR_DMR1_CW6_OR 0x00002000 |
#define SPR_DMR1_CW6 (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR) |
#define SPR_DMR1_CW7_AND 0x00004000 |
#define SPR_DMR1_CW7_OR 0x00008000 |
#define SPR_DMR1_CW7 (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR) |
#define SPR_DMR1_CW8_AND 0x00010000 |
#define SPR_DMR1_CW8_OR 0x00020000 |
#define SPR_DMR1_CW8 (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR) |
#define SPR_DMR1_CW9_AND 0x00040000 |
#define SPR_DMR1_CW9_OR 0x00080000 |
#define SPR_DMR1_CW9 (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR) |
#define SPR_DMR1_RES1 0x00300000 /* Reserved */ |
#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/ |
#define SPR_DMR1_BT 0x00800000 /* Branch trace */ |
#define SPR_DMR1_RES2 0xff000000 /* Reserved */ |
|
/* |
* Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB |
* |
*/ |
#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */ |
#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */ |
#define SPR_DMR2_AWTC 0x00000ffc /* Assign watchpoints to counters */ |
#define SPR_DMR2_AWTC_OFF 2 /* Bit offset to AWTC field */ |
#define SPR_DMR2_WGB 0x003ff000 /* Watchpoints generating breakpoint */ |
#define SPR_DMR2_WGB_OFF 12 /* Bit offset to WGB field */ |
#define SPR_DMR2_WBS 0xffc00000 /* JPB: Watchpoint status */ |
#define SPR_DMR2_WBS_OFF 22 /* Bit offset to WBS field */ |
|
/* |
* Bit definitions for Debug watchpoint counter registers |
* |
*/ |
#define SPR_DWCR_COUNT 0x0000ffff /* Count */ |
#define SPR_DWCR_MATCH 0xffff0000 /* Match */ |
#define SPR_DWCR_MATCH_OFF 16 /* Match bit offset */ |
|
/* |
* Bit definitions for Debug stop register |
* |
*/ |
#define SPR_DSR_RSTE 0x00000001 /* Reset exception */ |
#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */ |
#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */ |
#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */ |
#define SPR_DSR_TTE 0x00000010 /* Tick Timer exception */ |
#define SPR_DSR_AE 0x00000020 /* Alignment exception */ |
#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */ |
#define SPR_DSR_IE 0x00000080 /* Interrupt exception */ |
#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */ |
#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */ |
#define SPR_DSR_RE 0x00000400 /* Range exception */ |
#define SPR_DSR_SCE 0x00000800 /* System call exception */ |
#define SPR_DSR_FPE 0x00001000 /* Floating Point Exception */ |
#define SPR_DSR_TE 0x00002000 /* Trap exception */ |
|
/* |
* Bit definitions for Debug reason register |
* |
*/ |
#define SPR_DRR_RSTE 0x00000001 /* Reset exception */ |
#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */ |
#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */ |
#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */ |
#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */ |
#define SPR_DRR_AE 0x00000020 /* Alignment exception */ |
#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */ |
#define SPR_DRR_IE 0x00000080 /* Interrupt exception */ |
#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */ |
#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */ |
#define SPR_DRR_RE 0x00000400 /* Range exception */ |
#define SPR_DRR_SCE 0x00000800 /* System call exception */ |
#define SPR_DRR_FPE 0x00001000 /* Floating Point Exception */ |
#define SPR_DRR_TE 0x00002000 /* Trap exception */ |
|
/* |
* Bit definitions for Performance counters mode registers |
* |
*/ |
#define SPR_PCMR_CP 0x00000001 /* Counter present */ |
#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */ |
#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */ |
#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */ |
#define SPR_PCMR_LA 0x00000010 /* Load access event */ |
#define SPR_PCMR_SA 0x00000020 /* Store access event */ |
#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/ |
#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */ |
#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */ |
#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */ |
#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */ |
#define SPR_PCMR_BS 0x00000800 /* Branch stall event */ |
#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */ |
#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */ |
#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */ |
#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */ |
|
/* |
* Bit definitions for the Power management register |
* |
*/ |
#define SPR_PMR_SDF 0x0000000f /* Slow down factor */ |
#define SPR_PMR_DME 0x00000010 /* Doze mode enable */ |
#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */ |
#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */ |
#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */ |
|
/* |
* Bit definitions for PICMR |
* |
*/ |
#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */ |
|
/* |
* Bit definitions for PICPR |
* |
*/ |
#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */ |
|
/* |
* Bit definitions for PICSR |
* |
*/ |
#define SPR_PICSR_IS 0xffffffff /* Interrupt status */ |
|
/* |
* Bit definitions for Tick Timer Control Register |
* |
*/ |
#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */ |
#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD |
#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */ |
#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */ |
#define SPR_TTMR_DI 0x00000000 /* Disabled */ |
#define SPR_TTMR_RT 0x40000000 /* Restart tick */ |
#define SPR_TTMR_SR 0x80000000 /* Single run */ |
#define SPR_TTMR_CR 0xc0000000 /* Continuous run */ |
#define SPR_TTMR_M 0xc0000000 /* Tick mode */ |
|
/* |
* Bit definitions for the FP Control Status Register |
* |
*/ |
#define SPR_FPCSR_FPEE 0x00000001 /* Floating Point Exception Enable */ |
#define SPR_FPCSR_RM 0x00000006 /* Rounding Mode */ |
#define SPR_FPCSR_OVF 0x00000008 /* Overflow Flag */ |
#define SPR_FPCSR_UNF 0x00000010 /* Underflow Flag */ |
#define SPR_FPCSR_SNF 0x00000020 /* SNAN Flag */ |
#define SPR_FPCSR_QNF 0x00000040 /* QNAN Flag */ |
#define SPR_FPCSR_ZF 0x00000080 /* Zero Flag */ |
#define SPR_FPCSR_IXF 0x00000100 /* Inexact Flag */ |
#define SPR_FPCSR_IVF 0x00000200 /* Invalid Flag */ |
#define SPR_FPCSR_INF 0x00000400 /* Infinity Flag */ |
#define SPR_FPCSR_DZF 0x00000800 /* Divide By Zero Flag */ |
#define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \ |
SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF | \ |
SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF) |
|
#define FPCSR_RM_RN (0<<1) |
#define FPCSR_RM_RZ (1<<1) |
#define FPCSR_RM_RIP (2<<1) |
#define FPCSR_RM_RIN (3<<1) |
|
/* |
* l.nop constants |
* |
*/ |
#define NOP_NOP 0x0000 /* Normal nop instruction */ |
#define NOP_EXIT 0x0001 /* End of simulation */ |
#define NOP_REPORT 0x0002 /* Simple report */ |
/*#define NOP_PRINTF 0x0003 Simprintf instruction (obsolete)*/ |
#define NOP_PUTC 0x0004 /* JPB: Simputc instruction */ |
#define NOP_CNT_RESET 0x0005 /* Reset statistics counters */ |
#define NOP_GET_TICKS 0x0006 /* JPB: Get # ticks running */ |
#define NOP_GET_PS 0x0007 /* JPB: Get picosecs/cycle */ |
#define NOP_REPORT_FIRST 0x0400 /* Report with number */ |
#define NOP_REPORT_LAST 0x03ff /* Report with number */ |
|
#endif /* SPR_DEFS__H */ |
spr-defs.h
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Index: opcode/or32.h
===================================================================
--- opcode/or32.h (nonexistent)
+++ opcode/or32.h (revision 388)
@@ -0,0 +1,200 @@
+/* Table of opcodes for the OpenRISC 1000 ISA.
+
+ Copyright 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
+ Copyright (C) 2008 Embecosm Limited
+
+ Contributed by Damjan Lampret (lampret@opencores.org).
+ Contributor Jeremy Bennett
+
+ This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
+ This file is also part of or1k_gen_isa, GDB and GAS.
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 3 of the License, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program. If not, see . */
+
+/* This program is commented throughout in a fashion suitable for processing
+ with Doxygen. */
+
+/* We treat all letters the same in encode/decode routines so
+ we need to assign some characteristics to them like signess etc.*/
+
+#ifndef OR32_H_ISA
+#define OR32_H_ISA
+
+#define NUM_UNSIGNED (0)
+#define NUM_SIGNED (1)
+
+#ifndef PARAMS
+#define PARAMS(x) x
+#endif
+
+#ifndef CONST
+#define CONST const
+#endif
+
+#define MAX_GPRS 32
+#define PAGE_SIZE 8192
+#undef __HALF_WORD_INSN__
+
+#define OPERAND_DELIM (',')
+
+#define OR32_IF_DELAY (1)
+#define OR32_W_FLAG (2)
+#define OR32_R_FLAG (4)
+
+#if defined(HAVE_EXECUTION)
+# if SIMPLE_EXECUTION
+# include "simpl32-defs.h"
+# elif DYNAMIC_EXECUTION
+# include "dyn32-defs.h"
+# endif
+#endif
+
+
+struct or32_letter {
+ char letter;
+ int sign;
+ /* int reloc; relocation per letter ??*/
+};
+
+enum insn_type {
+ it_unknown,
+ it_exception,
+ it_arith,
+ it_shift,
+ it_compare,
+ it_branch,
+ it_jump,
+ it_load,
+ it_store,
+ it_movimm,
+ it_move,
+ it_extend,
+ it_nop,
+ it_mac,
+ it_float };
+
+/* Main instruction specification array. */
+struct or32_opcode {
+ /* Name of the instruction. */
+ char *name;
+
+ /* A string of characters which describe the operands.
+ Valid characters are:
+ ,() Itself. Characters appears in the assembly code.
+ rA Register operand.
+ rB Register operand.
+ rD Register operand (destination).
+ I An immediate operand, range -32768 to 32767.
+ J An immediate operand, range . (unused)
+ K An immediate operand, range 0 to 65535.
+ L An immediate operand, range 0 to 63.
+ M An immediate operand, range . (unused)
+ N An immediate operand, range -33554432 to 33554431.
+ O An immediate operand, range . (unused) */
+ char *args;
+
+ /* Opcode and operand encoding. */
+ char *encoding;
+
+#ifdef HAVE_EXECUTION
+# if COMPLEX_EXECUTION
+ char *function_name;
+# elif SIMPLE_EXECUTION
+ void (*exec)(struct iqueue_entry *);
+# else /* DYNAMIC_EXECUTION */
+ void (*exec)(struct op_queue *opq, int param_t[3], int);
+# endif
+#else /* HAVE_EXECUTION */
+ void (*exec)(void);
+#endif
+
+ unsigned int flags;
+ enum insn_type func_unit;
+};
+
+/* This operand is the last in the list */
+#define OPTYPE_LAST (0x80000000)
+/* This operand marks the end of the operand sequence (for things like I(rD)) */
+#define OPTYPE_OP (0x40000000)
+/* The operand specifies a register index */
+#define OPTYPE_REG (0x20000000)
+/* The operand must be sign extended */
+#define OPTYPE_SIG (0x10000000)
+/* Operand is a relative address, the `I' in `I(rD)' */
+#define OPTYPE_DIS (0x08000000)
+/* The operand is a destination */
+#define OPTYPE_DST (0x04000000)
+/* Which bit of the operand is the sign bit */
+#define OPTYPE_SBIT (0x00001F00)
+/* Amount to shift the instruction word right to get the operand */
+#define OPTYPE_SHR (0x0000001F)
+#define OPTYPE_SBIT_SHR (8)
+
+/* MM: Data how to decode operands. */
+extern struct insn_op_struct {
+ unsigned long type;
+ unsigned long data;
+} **or1ksim_op_start;
+
+/* Leaf flag used in automata building */
+#define LEAF_FLAG (0x80000000)
+
+struct temp_insn_struct
+{
+ unsigned long insn;
+ unsigned long insn_mask;
+ int in_pass;
+};
+
+extern unsigned long *or1ksim_automata;
+extern struct temp_insn_struct *or1ksim_ti;
+
+extern CONST struct or32_opcode or1ksim_or32_opcodes[];
+
+extern char *or1ksim_disassembled;
+
+/* Calculates instruction length in bytes. Always 4 for OR32. */
+extern int or1ksim_insn_len PARAMS((int insn_index));
+
+/* MM: Returns instruction name from index. */
+extern CONST char *or1ksim_insn_name PARAMS ((int index));
+
+/* MM: Constructs new FSM, based on or1ksim_or32_opcodes. */
+extern void or1ksim_build_automata PARAMS ((int quiet));
+
+/* MM: Destructs FSM. */
+extern void or1ksim_destruct_automata PARAMS ((void));
+
+/* MM: Decodes instruction using FSM. Call or1ksim_build_automata first. */
+extern int or1ksim_insn_decode PARAMS((unsigned int insn));
+
+/* Disassemble one instruction from insn to disassemble.
+ Return the size of the instruction. */
+extern int or1ksim_disassemble_insn (unsigned long insn);
+
+/* Disassemble one instruction from insn index.
+ Return the size of the instruction. */
+int or1ksim_disassemble_index (unsigned long insn, int index);
+
+/* FOR INTERNAL USE ONLY */
+/* Automatically does zero- or sign- extension and also finds correct
+ sign bit position if sign extension is correct extension. Which extension
+ is proper is figured out from letter description. */
+unsigned long or1ksim_extend_imm(unsigned long imm, char l);
+
+/* Extracts value from opcode */
+unsigned long or1ksim_or32_extract(char param_ch, char *enc_initial, unsigned long insn);
+
+#endif
+
opcode/or32.h
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Index: sprs.c
===================================================================
--- sprs.c (nonexistent)
+++ sprs.c (revision 388)
@@ -0,0 +1,274 @@
+/* sprs.c -- Simulation of OR1K special-purpose registers
+
+ Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
+ Copyright (C) 2008 Embecosm Limited
+
+ Contributor Jeremy Bennett
+
+ This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 3 of the License, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program. If not, see . */
+
+/* This program is commented throughout in a fashion suitable for processing
+ with Doxygen. */
+
+
+/* Autoconf and/or portability configuration */
+#include "config.h"
+#include "port.h"
+
+/* System includes */
+#include
+#include
+#include
+
+/* Package includes */
+#include "sprs.h"
+#include "sim-config.h"
+#include "debug.h"
+#include "execute.h"
+#include "spr-defs.h"
+#include "tick.h"
+#include "dcache-model.h"
+#include "icache-model.h"
+#include "dmmu.h"
+#include "immu.h"
+#include "toplevel-support.h"
+#include "pic.h"
+
+
+DECLARE_DEBUG_CHANNEL(immu);
+
+/* Set a specific SPR with a value. */
+void mtspr(uint16_t regno, const uorreg_t value)
+{
+ uorreg_t prev_val;
+
+ prev_val = cpu_state.sprs[regno];
+ cpu_state.sprs[regno] = value;
+
+ /* MM: Register hooks. */
+ switch (regno) {
+ case SPR_TTCR:
+ spr_write_ttcr (value);
+ break;
+ case SPR_TTMR:
+ spr_write_ttmr (prev_val);
+ break;
+ /* Data cache simulateing stuff */
+ case SPR_DCBPR:
+ /* FIXME: This is not correct. The arch. manual states: "Memory accesses
+ * are not recorded (Unlike load or store instructions) and cannot invoke
+ * any exception". If the physical address is invalid a bus error will be
+ * generated. Also if the effective address is not resident in the mmu
+ * the read will happen from address 0, which is naturally not correct. */
+ dc_simulate_read(peek_into_dtlb(value, 0, 1), value, 4);
+ cpu_state.sprs[SPR_DCBPR] = 0;
+ break;
+ case SPR_DCBFR:
+ dc_inv(value);
+ cpu_state.sprs[SPR_DCBFR] = -1;
+ break;
+ case SPR_DCBIR:
+ dc_inv(value);
+ cpu_state.sprs[SPR_DCBIR] = 0;
+ break;
+ case SPR_DCBWR:
+ cpu_state.sprs[SPR_DCBWR] = 0;
+ break;
+ case SPR_DCBLR:
+ cpu_state.sprs[SPR_DCBLR] = 0;
+ break;
+ /* Instruction cache simulateing stuff */
+ case SPR_ICBPR:
+ /* FIXME: The arch manual does not say what happens when an invalid memory
+ * location is specified. I guess the same as for the DCBPR register */
+ ic_simulate_fetch(peek_into_itlb(value), value);
+ cpu_state.sprs[SPR_ICBPR] = 0;
+ break;
+ case SPR_ICBIR:
+ ic_inv(value);
+ cpu_state.sprs[SPR_ICBIR] = 0;
+ break;
+ case SPR_ICBLR:
+ cpu_state.sprs[SPR_ICBLR] = 0;
+ break;
+ case SPR_SR:
+ cpu_state.sprs[regno] |= SPR_SR_FO;
+ if((value & SPR_SR_IEE) && !(prev_val & SPR_SR_IEE))
+ pic_ints_en();
+#if DYNAMIC_EXECUTION
+ if((value & SPR_SR_IME) && !(prev_val & SPR_SR_IME)) {
+ TRACE_(immu)("IMMU just became enabled (%lli).\n", runtime.sim.cycles);
+ recheck_immu(IMMU_GOT_ENABLED);
+ } else if(!(value & SPR_SR_IME) && (prev_val & SPR_SR_IME)) {
+ TRACE_(immu)("Remove counting of mmu hit delay with cycles (%lli)\n",
+ runtime.sim.cycles);
+ recheck_immu(IMMU_GOT_DISABLED);
+ }
+#endif
+ break;
+ case SPR_NPC:
+ {
+ /* The debugger has redirected us to a new address */
+ /* This is usually done to reissue an instruction
+ which just caused a breakpoint exception. */
+
+ /* JPB patch. When GDB stepi, this may be used to set the PC to the
+ value it is already at. If this is the case, then we do nothing (in
+ particular we do not trash a delayed branch) */
+
+ if (value != cpu_state.pc)
+ {
+ cpu_state.pc = value;
+
+ if(!value && config.sim.verbose)
+ PRINTF("WARNING: PC just set to 0!\n");
+
+ /* Clear any pending delay slot jumps also */
+ cpu_state.delay_insn = 0;
+ pcnext = value + 4;
+
+ /* Further JPB patch. If the processor is stalled, then subsequent
+ reads of the NPC should return 0 until the processor is
+ unstalled. If the processor is stalled, note that the NPC has
+ been updated while the processor was stalled. */
+
+ if (runtime.cpu.stalled)
+ {
+ cpu_state.npc_not_valid = 1;
+ }
+ }
+ }
+ break;
+ case SPR_PICSR:
+ if(!config.pic.edge_trigger)
+ cpu_state.sprs[SPR_PICSR] = prev_val;
+ break;
+ case SPR_PICMR:
+ if(cpu_state.sprs[SPR_SR] & SPR_SR_IEE)
+ pic_ints_en();
+ break;
+ case SPR_PMR:
+ /* PMR[SDF] and PMR[DCGE] are ignored completely. */
+ if (config.pm.enabled && (value & SPR_PMR_SUME)) {
+ PRINTF ("SUSPEND: PMR[SUME] bit was set.\n");
+ sim_done();
+ }
+ break;
+ default:
+ /* Mask reserved bits in DTLBMR and DTLBMR registers */
+ if ( (regno >= SPR_DTLBMR_BASE(0)) && (regno < SPR_DTLBTR_LAST(3))) {
+ if((regno & 0xff) < 0x80)
+ cpu_state.sprs[regno] = DADDR_PAGE(value) |
+ (value & (SPR_DTLBMR_V | SPR_DTLBMR_PL1 | SPR_DTLBMR_CID | SPR_DTLBMR_LRU));
+ else
+ cpu_state.sprs[regno] = DADDR_PAGE(value) |
+ (value & (SPR_DTLBTR_CC | SPR_DTLBTR_CI | SPR_DTLBTR_WBC | SPR_DTLBTR_WOM |
+ SPR_DTLBTR_A | SPR_DTLBTR_D | SPR_DTLBTR_URE | SPR_DTLBTR_UWE | SPR_DTLBTR_SRE |
+ SPR_DTLBTR_SWE));
+ }
+
+ /* Mask reseved bits in ITLBMR and ITLBMR registers */
+ if ( (regno >= SPR_ITLBMR_BASE(0)) && (regno < SPR_ITLBTR_LAST(3))) {
+ if((regno & 0xff) < 0x80)
+ cpu_state.sprs[regno] = IADDR_PAGE(value) |
+ (value & (SPR_ITLBMR_V | SPR_ITLBMR_PL1 | SPR_ITLBMR_CID | SPR_ITLBMR_LRU));
+ else
+ cpu_state.sprs[regno] = IADDR_PAGE(value) |
+ (value & (SPR_ITLBTR_CC | SPR_ITLBTR_CI | SPR_ITLBTR_WBC | SPR_ITLBTR_WOM |
+ SPR_ITLBTR_A | SPR_ITLBTR_D | SPR_ITLBTR_SXE | SPR_ITLBTR_UXE));
+
+#if DYNAMIC_EXECUTION
+ if(cpu_state.sprs[SPR_SR] & SPR_SR_IME) {
+ /* The immu got reconfigured. Recheck if the current page in execution
+ * is resident in the immu ways. This check would be done during the
+ * instruction fetch but since the dynamic execution model does not do
+ * instruction fetchs, do it now. */
+ recheck_immu(0);
+ }
+#endif
+ }
+
+ /* Links to GPRS */
+ if(regno >= 0x0400 && regno < 0x0420) {
+ cpu_state.reg[regno - 0x0400] = value;
+ }
+ break;
+ }
+}
+
+/* Get a specific SPR. */
+uorreg_t mfspr(const uint16_t regno)
+{
+ uorreg_t ret;
+
+ ret = cpu_state.sprs[regno];
+
+ switch (regno) {
+ case SPR_NPC:
+
+ /* The NPC is the program counter UNLESS the NPC has been changed and we
+ are stalled, which will have flushed the pipeline, so the value is
+ zero. Currently this is optional behavior, since it breaks GDB.
+ */
+
+ if (config.sim.strict_npc && cpu_state.npc_not_valid)
+ {
+ ret = 0;
+ }
+ else
+ {
+ ret = cpu_state.pc;
+ }
+ break;
+
+ case SPR_TTCR:
+ ret = spr_read_ttcr();
+ break;
+ case SPR_FPCSR:
+ // If hard floating point is disabled - return 0
+ if (!config.cpu.hardfloat)
+ ret = 0;
+ break;
+ default:
+ /* Links to GPRS */
+ if(regno >= 0x0400 && regno < 0x0420)
+ ret = cpu_state.reg[regno - 0x0400];
+ }
+
+ return ret;
+}
+
+/* Show status of important SPRs. */
+void sprs_status(void)
+{
+ PRINTF("VR : 0x%"PRIxREG" UPR : 0x%"PRIxREG"\n", cpu_state.sprs[SPR_VR],
+ cpu_state.sprs[SPR_UPR]);
+ PRINTF("SR : 0x%"PRIxREG"\n", cpu_state.sprs[SPR_SR]);
+ PRINTF("MACLO: 0x%"PRIxREG" MACHI: 0x%"PRIxREG"\n",
+ cpu_state.sprs[SPR_MACLO], cpu_state.sprs[SPR_MACHI]);
+ PRINTF("EPCR0: 0x%"PRIxADDR" EPCR1: 0x%"PRIxADDR"\n",
+ cpu_state.sprs[SPR_EPCR_BASE], cpu_state.sprs[SPR_EPCR_BASE+1]);
+ PRINTF("EEAR0: 0x%"PRIxADDR" EEAR1: 0x%"PRIxADDR"\n",
+ cpu_state.sprs[SPR_EEAR_BASE], cpu_state.sprs[SPR_EEAR_BASE+1]);
+ PRINTF("ESR0 : 0x%"PRIxREG" ESR1 : 0x%"PRIxREG"\n",
+ cpu_state.sprs[SPR_ESR_BASE], cpu_state.sprs[SPR_ESR_BASE+1]);
+ PRINTF("TTMR : 0x%"PRIxREG" TTCR : 0x%"PRIxREG"\n",
+ cpu_state.sprs[SPR_TTMR], cpu_state.sprs[SPR_TTCR]);
+ PRINTF("PICMR: 0x%"PRIxREG" PICSR: 0x%"PRIxREG"\n",
+ cpu_state.sprs[SPR_PICMR], cpu_state.sprs[SPR_PICSR]);
+ PRINTF("PPC: 0x%"PRIxADDR" NPC : 0x%"PRIxADDR"\n",
+ cpu_state.sprs[SPR_PPC], cpu_state.sprs[SPR_NPC]);
+}
sprs.c
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Index: arch.h
===================================================================
--- arch.h (nonexistent)
+++ arch.h (revision 388)
@@ -0,0 +1,50 @@
+/* arch.h -- OR1K architecture specific macros
+
+ Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
+ Copyright (C) 2008 Embecosm Limited
+
+ Contributor Jeremy Bennett
+
+ This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 3 of the License, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program. If not, see . */
+
+/* This program is commented throughout in a fashion suitable for processing
+ with Doxygen. */
+
+
+#ifndef ARCH__H
+#define ARCH__H
+
+/* Autoconf and/or portability configuration */
+#include "port.h"
+
+/*! Index of the link register */
+#define LINK_REGNO 9
+
+/* Conversion macros */
+#define ADDR_C(c) UINT32_C(c)
+#define REG_C(c) UINT32_C(c)
+
+/* Strings for printing OpenRISC types */
+#define PRIxADDR "08" PRIx32 /*!< print an openrisc address in hex */
+#define PRIxREG "08" PRIx32 /*!< print an openrisc register in hex */
+#define PRIdREG PRId32 /*!< print an openrisc register in decimals */
+
+/* Basic types for openrisc */
+typedef uint32_t oraddr_t; /*!< Address as addressed by openrisc */
+typedef uint32_t uorreg_t; /*!< An unsigned register of openrisc */
+typedef int32_t orreg_t; /*!< A signed register of openrisc */
+
+#endif /* ARCH__H */
arch.h
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Index: spr-dump.c
===================================================================
--- spr-dump.c (nonexistent)
+++ spr-dump.c (revision 388)
@@ -0,0 +1,542 @@
+/* spr_dump.c -- Dump given spr in human readable form
+
+ Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
+ Copyright (C) 2008 Embecosm Limited
+
+ Contributor Jeremy Bennett
+
+ This file is part of OpenRISC 1000 Architectural Simulator.
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 3 of the License, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program. If not, see . */
+
+/* This program is commented throughout in a fashion suitable for processing
+ with Doxygen. */
+
+
+/* Autoconf and/or portability configuration */
+#include "config.h"
+#include "port.h"
+
+/* System includes */
+#include
+
+/* Package includes */
+#include "arch.h"
+#include "spr-defs.h"
+#include "debug.h"
+#include "misc.h"
+
+
+struct spr_bit_def {
+ const char *name;
+ uorreg_t mask;
+};
+
+struct spr_def {
+ uint16_t from_spr;
+ uint16_t to_spr;
+ const char *name;
+ const struct spr_bit_def *bits;
+};
+
+/* One value spr */
+static const struct spr_bit_def spr_one_val[] = {
+ { "", 0xffffffff },
+ { NULL, 0 } };
+
+/*---------------------------------------------------------[ System group ]---*/
+/* Supervisor register */
+static const struct spr_bit_def spr_sr[] = {
+ { "SR_SM", SPR_SR_SM },
+ { "SR_TEE", SPR_SR_TEE },
+ { "SR_IEE", SPR_SR_IEE },
+ { "SR_DCE", SPR_SR_DCE },
+ { "SR_ICE", SPR_SR_ICE },
+ { "SR_DME", SPR_SR_DME },
+ { "SR_IME", SPR_SR_IME },
+ { "SR_LEE", SPR_SR_IME },
+ { "SR_CE", SPR_SR_CE },
+ { "SR_F", SPR_SR_F },
+ { "SR_CY", SPR_SR_CY },
+ { "SR_OV", SPR_SR_OV },
+ { "SR_OVE", SPR_SR_OVE },
+ { "SR_DSX", SPR_SR_DSX },
+ { "SR_EPH", SPR_SR_EPH },
+ { "SR_FO", SPR_SR_FO },
+ { "SR_SUMRA", SPR_SR_SUMRA },
+ { "SR_RES", SPR_SR_RES },
+ { "SR_CID", SPR_SR_CID },
+ { NULL, 0 } };
+
+/* Version register */
+static const struct spr_bit_def spr_vr[] = {
+ { "VR_VER", SPR_VR_VER },
+ { "VR_REV", SPR_VR_REV },
+ { NULL, 0 } };
+
+/* upr register */
+static const struct spr_bit_def spr_upr[] = {
+ { "UPR_UP", SPR_UPR_UP },
+ { "UPR_DCP", SPR_UPR_DCP },
+ { "UPR_ICP", SPR_UPR_ICP },
+ { "UPR_DMP", SPR_UPR_DMP },
+ { "UPR_IMP", SPR_UPR_IMP },
+ { "UPR_MP", SPR_UPR_MP },
+ { "UPR_DUP", SPR_UPR_DUP },
+ { "UPR_PCUP", SPR_UPR_PCUP },
+ { "UPR_PMP", SPR_UPR_PMP },
+ { "UPR_PICP", SPR_UPR_PICP },
+ { "UPR_TTP", SPR_UPR_TTP },
+ { "UPR_RES", SPR_UPR_RES },
+ { "UPR_CUP", SPR_UPR_CUP },
+ { NULL, 0 } };
+
+/* CPUCFGR register */
+static const struct spr_bit_def spr_cpucfgr[] = {
+ { "CPUCFGR_OB32S", SPR_CPUCFGR_OB32S },
+ { "CPUCFGR_OB64S", SPR_CPUCFGR_OB64S },
+ { "CPUCFGR_OF32S", SPR_CPUCFGR_OF32S },
+ { "CPUCFGR_OF64S", SPR_CPUCFGR_OF64S },
+ { "CPUCFGR_OV64S", SPR_CPUCFGR_OV64S },
+ { NULL, 0 } };
+
+/* dmmucfgr register */
+static const struct spr_bit_def spr_dmmucfgr[] = {
+ { "DMMUCFGR_NTW", SPR_DMMUCFGR_NTW },
+ { "DMMUCFGR_NTS", SPR_DMMUCFGR_NTS },
+ { "DMMUCFGR_NAE", SPR_DMMUCFGR_NAE },
+ { "DMMUCFGR_CRI", SPR_DMMUCFGR_CRI },
+ { "DMMUCFGR_PRI", SPR_DMMUCFGR_PRI },
+ { "DMMUCFGR_TEIRI", SPR_DMMUCFGR_TEIRI },
+ { "DMMUCFGR_HTR", SPR_DMMUCFGR_HTR },
+ { NULL, 0 } };
+
+/* immucfgr register */
+static const struct spr_bit_def spr_immucfgr[] = {
+ { "IMMUCFGR_NTW", SPR_IMMUCFGR_NTW },
+ { "IMMUCFGR_NTS", SPR_IMMUCFGR_NTS },
+ { "IMMUCFGR_NAE", SPR_IMMUCFGR_NAE },
+ { "IMMUCFGR_CRI", SPR_IMMUCFGR_CRI },
+ { "IMMUCFGR_PRI", SPR_IMMUCFGR_PRI },
+ { "IMMUCFGR_TEIRI", SPR_IMMUCFGR_TEIRI },
+ { "IMMUCFGR_HTR", SPR_IMMUCFGR_HTR },
+ { NULL, 0 } };
+
+/* dccfgr register */
+static const struct spr_bit_def spr_dccfgr[] = {
+ { "DCCFGR_NCW", SPR_DCCFGR_NCW },
+ { "DCCFGR_NCS", SPR_DCCFGR_NCS },
+ { "DCCFGR_CBS", SPR_DCCFGR_CBS },
+ { "DCCFGR_CWS", SPR_DCCFGR_CWS },
+ { "DCCFGR_CCRI", SPR_DCCFGR_CCRI },
+ { "DCCFGR_CBIRI", SPR_DCCFGR_CBIRI },
+ { "DCCFGR_CBPRI", SPR_DCCFGR_CBPRI },
+ { "DCCFGR_CBLRI", SPR_DCCFGR_CBLRI },
+ { "DCCFGR_CBFRI", SPR_DCCFGR_CBFRI },
+ { "DCCFGR_CBWBRI", SPR_DCCFGR_CBWBRI },
+ { NULL, 0 } };
+
+/* iccfgr register */
+static const struct spr_bit_def spr_iccfgr[] = {
+ { "ICCFGR_NCW", SPR_ICCFGR_NCW },
+ { "ICCFGR_NCS", SPR_ICCFGR_NCS },
+ { "ICCFGR_CBS", SPR_ICCFGR_CBS },
+ { "ICCFGR_CCRI", SPR_ICCFGR_CCRI },
+ { "ICCFGR_CBIRI", SPR_ICCFGR_CBIRI },
+ { "ICCFGR_CBPRI", SPR_ICCFGR_CBPRI },
+ { "ICCFGR_CBLRI", SPR_ICCFGR_CBLRI },
+ { NULL, 0 } };
+
+/* DCFGR register */
+static const struct spr_bit_def spr_dcfgr[] = {
+ { "DCFGR_NDP", SPR_DCFGR_NDP },
+ { "DCFGR_WPCI", SPR_DCFGR_WPCI },
+ { NULL, 0 } };
+
+/* System group */
+static const struct spr_def spr_sys_group[] = {
+ /* 000-000 */ { 0x000, 0x000, "SPR_VR", spr_vr },
+ /* 001-001 */ { 0x001, 0x001, "SPR_UPR", spr_upr },
+ /* 002-002 */ { 0x002, 0x002, "SPR_CPUCFGR", spr_cpucfgr }, /* JPB */
+ /* 003-003 */ { 0x003, 0x003, "SPR_DMMUCFGR", spr_dmmucfgr },
+ /* 004-004 */ { 0x004, 0x004, "SPR_IMMUCFGR", spr_immucfgr },
+ /* 005-005 */ { 0x005, 0x005, "SPR_DCCFGR", spr_dccfgr },
+ /* 006-006 */ { 0x006, 0x006, "SPR_ICCFGR", spr_iccfgr },
+ /* 007-007 */ { 0x007, 0x007, "SPR_DCFGR", spr_dcfgr }, /* JPB */
+ /* 010-010 */ { 0x010, 0x010, "SPR_NPC", spr_one_val },
+ /* 011-011 */ { 0x011, 0x011, "SPR_SR", spr_sr },
+ /* 012-012 */ { 0x012, 0x012, "SPR_PPC", spr_one_val },
+ /* 020-02f */ { 0x020, 0x02f, "SPR_EPCR(%i)", spr_one_val },
+ /* 030-03f */ { 0x030, 0x03f, "SPR_EEAR(%i)", spr_one_val },
+ /* 040-04f */ { 0x040, 0x04f, "SPR_ESR(%i)", spr_sr },
+ /* 400-41f */ { 0x400, 0x41f, "GPR(%i)", spr_one_val },
+ /* ------- */ { -1, -1, NULL, NULL } };
+
+/*-----------------------------------------------------------[ DMMU group ]---*/
+/* Data MMU conrtol reg */
+static const struct spr_bit_def spr_dmmucr[] = {
+ { "DMMUCR_P2S", SPR_DMMUCR_P2S },
+ { "DMMUCR_P1S", SPR_DMMUCR_P1S },
+ { "DMMUCR_VADDR_WIDTH", SPR_DMMUCR_VADDR_WIDTH },
+ { "DMMUCR_PADDR_WIDTH", SPR_DMMUCR_PADDR_WIDTH },
+ { NULL, 0 } };
+
+/* dtlbmr register */
+static const struct spr_bit_def spr_dtlbmr[] = {
+ { "DTLBMR_V", SPR_DTLBMR_V },
+ { "DTLBMR_PL1", SPR_DTLBMR_PL1 },
+ { "DTLBMR_CID", SPR_DTLBMR_CID },
+ { "DTLBMR_LRU", SPR_DTLBMR_LRU },
+ { "DTLBMR_VPN", SPR_DTLBMR_VPN },
+ { NULL, 0 } };
+
+/* dtlbtr register */
+static const struct spr_bit_def spr_dtlbtr[] = {
+ { "DTLBTR_CC", SPR_DTLBTR_CC },
+ { "DTLBTR_CI", SPR_DTLBTR_CI },
+ { "DTLBTR_WBC", SPR_DTLBTR_WBC },
+ { "DTLBTR_WOM", SPR_DTLBTR_WOM },
+ { "DTLBTR_A", SPR_DTLBTR_A },
+ { "DTLBTR_D", SPR_DTLBTR_D },
+ { "DTLBTR_URE", SPR_DTLBTR_URE },
+ { "DTLBTR_UWE", SPR_DTLBTR_UWE },
+ { "DTLBTR_SRE", SPR_DTLBTR_SRE },
+ { "DTLBTR_SWE", SPR_DTLBTR_SWE },
+ { "DTLBTR_PPN", SPR_DTLBTR_PPN },
+ { NULL, 0 } };
+
+/* DMMU group */
+static const struct spr_def spr_dmmu_group[] = {
+ /* 000-000 */ { 0, 0, "SPR_DMMUCR", spr_dmmucr },
+ /* 200-27f */ { 0x200, 0x27f, "SPR_DTLBMR way 0 set %i", spr_dtlbmr },
+ /* 280-2ff */ { 0x280, 0x2ff, "SPR_DTLBTR way 0 set %i", spr_dtlbtr },
+ /* 300-37f */ { 0x300, 0x37f, "SPR_DTLBMR way 1 set %i", spr_dtlbmr },
+ /* 380-3ff */ { 0x380, 0x3ff, "SPR_DTLBTR way 1 set %i", spr_dtlbtr },
+ /* 400-47f */ { 0x400, 0x47f, "SPR_DTLBMR way 2 set %i", spr_dtlbmr },
+ /* 480-4ff */ { 0x480, 0x4ff, "SPR_DTLBTR way 2 set %i", spr_dtlbtr },
+ /* 500-57f */ { 0x500, 0x57f, "SPR_DTLBMR way 3 set %i", spr_dtlbmr },
+ /* 580-5ff */ { 0x580, 0x5ff, "SPR_DTLBTR way 3 set %i", spr_dtlbtr },
+ /* ------- */ { -1, -1, NULL, NULL } };
+
+/*-----------------------------------------------------------[ IMMU group ]---*/
+/* Instruction MMU conrtol reg */
+static const struct spr_bit_def spr_immucr[] = {
+ { "IMMUCR_P2S", SPR_IMMUCR_P2S },
+ { "IMMUCR_P1S", SPR_IMMUCR_P1S },
+ { "IMMUCR_VADDR_WIDTH", SPR_IMMUCR_VADDR_WIDTH },
+ { "IMMUCR_PADDR_WIDTH", SPR_IMMUCR_PADDR_WIDTH },
+ { NULL, 0 } };
+
+/* itlbmr register */
+static const struct spr_bit_def spr_itlbmr[] = {
+ { "ITLBMR_V", SPR_ITLBMR_V },
+ { "ITLBMR_PL1", SPR_ITLBMR_PL1 },
+ { "ITLBMR_CID", SPR_ITLBMR_CID },
+ { "ITLBMR_LRU", SPR_ITLBMR_LRU },
+ { "ITLBMR_VPN", SPR_ITLBMR_VPN },
+ { NULL, 0 } };
+
+/* itlbtr register */
+static const struct spr_bit_def spr_itlbtr[] = {
+ { "ITLBTR_CC", SPR_ITLBTR_CC },
+ { "ITLBTR_CI", SPR_ITLBTR_CI },
+ { "ITLBTR_WBC", SPR_ITLBTR_WBC },
+ { "ITLBTR_WOM", SPR_ITLBTR_WOM },
+ { "ITLBTR_A", SPR_ITLBTR_A },
+ { "ITLBTR_D", SPR_ITLBTR_D },
+ { "ITLBTR_URE", SPR_ITLBTR_SXE },
+ { "ITLBTR_UWE", SPR_ITLBTR_UXE },
+ { "ITLBTR_PPN", SPR_ITLBTR_PPN },
+ { NULL, 0 } };
+
+/* IMMU group */
+static const struct spr_def spr_immu_group[] = {
+ /* 000-000 */ { 0, 0, "SPR_IMMUCR", spr_immucr },
+ /* 200-27f */ { 0x200, 0x27f, "SPR_ITLBMR way 0 set %i", spr_itlbmr },
+ /* 280-2ff */ { 0x280, 0x2ff, "SPR_ITLBTR way 0 set %i", spr_itlbtr },
+ /* 300-37f */ { 0x300, 0x37f, "SPR_ITLBMR way 1 set %i", spr_itlbmr },
+ /* 380-3ff */ { 0x380, 0x3ff, "SPR_ITLBTR way 1 set %i", spr_itlbtr },
+ /* 400-47f */ { 0x400, 0x47f, "SPR_ITLBMR way 2 set %i", spr_itlbmr },
+ /* 480-4ff */ { 0x480, 0x4ff, "SPR_ITLBTR way 2 set %i", spr_itlbtr },
+ /* 500-57f */ { 0x500, 0x57f, "SPR_ITLBMR way 3 set %i", spr_itlbmr },
+ /* 580-5ff */ { 0x580, 0x5ff, "SPR_ITLBTR way 3 set %i", spr_itlbtr },
+ /* ------- */ { -1, -1, NULL, NULL } };
+
+/*-----------------------------------------------------[ Data cache group ]---*/
+static const struct spr_bit_def spr_dccr[] = {
+ { "DCCR_EW", SPR_DCCR_EW },
+ { NULL, 0 } };
+
+static const struct spr_def spr_dc_group[] = {
+ /* 000-000 */ { 0x000, 0x000, "SPR_DCCR", spr_dccr },
+ /* 001-001 */ { 0x001, 0x001, "SPR_DCBPR", spr_one_val },
+ /* 002-002 */ { 0x002, 0x002, "SPR_DCBFR", spr_one_val },
+ /* 003-003 */ { 0x003, 0x003, "SPR_DCBIR", spr_one_val },
+ /* 004-004 */ { 0x004, 0x004, "SPR_DCBWR", spr_one_val },
+ /* 005-005 */ { 0x005, 0x005, "SPR_DCBLR", spr_one_val },
+ /* 200-3ff */ { 0x200, 0x3ff, "SPR_DCR way 0 set %i", spr_one_val },
+ /* 400-5ff */ { 0x400, 0x5ff, "SPR_DCR way 1 set %i", spr_one_val },
+ /* 600-7ff */ { 0x600, 0x7ff, "SPR_DCR way 2 set %i", spr_one_val },
+ /* 800-9ff */ { 0x800, 0x9ff, "SPR_DCR way 3 set %i", spr_one_val },
+ /* ------- */ { -1, -1, NULL, NULL } };
+
+/*----------------------------------------------[ Instruction cache group ]---*/
+static const struct spr_bit_def spr_iccr[] = {
+ { "ICCR_EW", SPR_ICCR_EW },
+ { NULL, 0 } };
+
+static const struct spr_def spr_ic_group[] = {
+ /* 000-000 */ { 0x000, 0x000, "SPR_ICCR", spr_iccr },
+ /* 001-001 */ { 0x001, 0x001, "SPR_ICBPR", spr_one_val },
+ /* 002-002 */ { 0x002, 0x002, "SPR_ICBFR", spr_one_val },
+ /* 003-003 */ { 0x003, 0x003, "SPR_ICBIR", spr_one_val },
+ /* 200-3ff */ { 0x200, 0x3ff, "SPR_ICR way 0 set %i", spr_one_val },
+ /* 400-5ff */ { 0x400, 0x5ff, "SPR_ICR way 1 set %i", spr_one_val },
+ /* 600-7ff */ { 0x600, 0x7ff, "SPR_ICR way 2 set %i", spr_one_val },
+ /* 800-9ff */ { 0x800, 0x9ff, "SPR_ICR way 3 set %i", spr_one_val },
+ /* ------- */ { -1, -1, NULL, NULL } };
+
+/*------------------------------------------------------------[ MAC group ]---*/
+static const struct spr_def spr_mac_group[] = {
+ /* 1-1 */ { 0x1, 0x1, "SPR_MACLO", spr_one_val },
+ /* 2-2 */ { 0x2, 0x2, "SPR_MACHI", spr_one_val },
+ /* ------- */ { -1, -1, NULL, NULL } };
+
+/*----------------------------------------------------------[ Debug group ]---*/
+/* dmr1 register */
+static const struct spr_bit_def spr_dmr1[] = {
+ { "DMR1_CW0", SPR_DMR1_CW0 },
+ { "DMR1_CW1", SPR_DMR1_CW1 },
+ { "DMR1_CW2", SPR_DMR1_CW2 },
+ { "DMR1_CW3", SPR_DMR1_CW3 },
+ { "DMR1_CW4", SPR_DMR1_CW4 },
+ { "DMR1_CW5", SPR_DMR1_CW5 },
+ { "DMR1_CW6", SPR_DMR1_CW6 },
+ { "DMR1_CW7", SPR_DMR1_CW7 },
+ { "DMR1_CW8", SPR_DMR1_CW8 },
+ { "DMR1_CW9", SPR_DMR1_CW9 },
+ { "DMR1_RES1", SPR_DMR1_RES1 },
+ { "DMR1_ST", SPR_DMR1_ST },
+ { "DMR1_BT", SPR_DMR1_BT },
+ { "DMR1_RES2", SPR_DMR1_RES2 },
+ { NULL, 0 } };
+
+/* dmr2 register */
+static const struct spr_bit_def spr_dmr2[] = {
+ { "DMR2_WCE0", SPR_DMR2_WCE0 },
+ { "DMR2_WCE1", SPR_DMR2_WCE1 },
+ { "DMR2_AWTC", SPR_DMR2_AWTC },
+ { "DMR2_WGB", SPR_DMR2_WGB },
+ { "DMR2_WBS", SPR_DMR2_WBS }, /* JPB */
+ { NULL, 0 } };
+
+/* dwcr register */
+static const struct spr_bit_def spr_dwcr[] = {
+ { "DWCR_COUNT", SPR_DWCR_COUNT },
+ { "DWCR_MATCH", SPR_DWCR_MATCH },
+ { NULL, 0 } };
+
+/* dsr register */
+static const struct spr_bit_def spr_dsr[] = {
+ { "DSR_RSTE", SPR_DSR_RSTE },
+ { "DSR_BUSE", SPR_DSR_BUSEE },
+ { "DSR_DPFE", SPR_DSR_DPFE },
+ { "DSR_IPFE", SPR_DSR_IPFE },
+ { "DSR_TTE", SPR_DSR_TTE },
+ { "DSR_AE", SPR_DSR_AE },
+ { "DSR_IIE", SPR_DSR_IIE },
+ { "DSR_IE", SPR_DSR_IE },
+ { "DSR_DME", SPR_DSR_DME },
+ { "DSR_IME", SPR_DSR_IME },
+ { "DSR_RE", SPR_DSR_RE },
+ { "DSR_SCE", SPR_DSR_SCE },
+ { "DSR_FPE", SPR_DSR_FPE },
+ { "DSR_TE", SPR_DSR_TE },
+ { NULL, 0 } };
+
+/* drr register */
+static const struct spr_bit_def spr_drr[] = {
+ { "DRR_RSTE", SPR_DRR_RSTE },
+ { "DRR_BUSE", SPR_DRR_BUSEE },
+ { "DRR_DPFE", SPR_DRR_DPFE },
+ { "DRR_IPFE", SPR_DRR_IPFE },
+ { "DRR_TTE", SPR_DRR_TTE },
+ { "DRR_AE", SPR_DRR_AE },
+ { "DRR_IIE", SPR_DRR_IIE },
+ { "DRR_IE", SPR_DRR_IE },
+ { "DRR_DME", SPR_DRR_DME },
+ { "DRR_IME", SPR_DRR_IME },
+ { "DRR_RE", SPR_DRR_RE },
+ { "DRR_SCE", SPR_DRR_SCE },
+ { "DRR_TE", SPR_DRR_TE },
+ { NULL, 0 } };
+
+/* Debug group */
+static const struct spr_def spr_d_group[] = {
+#if 0
+ /* 00-07 */ { 0x00, 0x07, "SPR_DVR(%i)", spr_dvr },
+ /* 08-0f */ { 0x08, 0x0f, "SPR_DCR(%i)", spr_dcr },
+#endif
+ /* 10-10 */ { 0x10, 0x10, "SPR_DMR1", spr_dmr1 },
+ /* 11-11 */ { 0x11, 0x11, "SPR_DMR2", spr_dmr2 },
+ /* 12-12 */ { 0x12, 0x12, "SPR_DWCR0", spr_dwcr },
+ /* 13-13 */ { 0x13, 0x13, "SPR_DWCR1", spr_dwcr },
+ /* 14-14 */ { 0x14, 0x14, "SPR_DSR", spr_dsr },
+ /* 15-15 */ { 0x15, 0x15, "SPR_DRR", spr_drr },
+ /* ----- */ { -1, -1, NULL, NULL } };
+
+/*-------------------------------------------[ Performance counters group ]---*/
+static const struct spr_bit_def spr_pcmr[] = {
+ { "PCMR_CP", SPR_PCMR_CP },
+ { "PCMR_UMRA", SPR_PCMR_UMRA },
+ { "PCMR_CISM", SPR_PCMR_CISM },
+ { "PCMR_CIUM", SPR_PCMR_CIUM },
+ { "PCMR_LA", SPR_PCMR_LA },
+ { "PCMR_SA", SPR_PCMR_SA },
+ { "PCMR_IF", SPR_PCMR_IF },
+ { "PCMR_DCM", SPR_PCMR_DCM },
+ { "PCMR_ICM", SPR_PCMR_ICM },
+ { "PCMR_IFS", SPR_PCMR_IFS },
+ { "PCMR_LSUS", SPR_PCMR_LSUS },
+ { "PCMR_BS", SPR_PCMR_BS },
+ { "PCMR_DTLBM", SPR_PCMR_DTLBM },
+ { "PCMR_ITLBM", SPR_PCMR_ITLBM },
+ { "PCMR_DDS", SPR_PCMR_DDS },
+ { "PCMR_WPE", SPR_PCMR_WPE },
+ { NULL, 0 } };
+
+static const struct spr_def spr_pc_group[] = {
+ /* 00-07 */ { 0x00, 0x07, "PCCR", spr_one_val },
+ /* 08-0f */ { 0x08, 0x0f, "PCMR", spr_pcmr },
+ /* ----- */ { -1, -1, NULL, NULL } };
+
+/*------------------------------------------------[ Power managment group ]---*/
+static const struct spr_bit_def spr_pmr[] = {
+ { "PMR_SDF", SPR_PMR_SDF },
+ { "PMR_DME", SPR_PMR_DME },
+ { "PMR_SME", SPR_PMR_SME },
+ { "PMR_DCGE", SPR_PMR_DCGE },
+ { "PMR_SUME", SPR_PMR_SUME },
+ { NULL, 0 } };
+
+static const struct spr_def spr_pm_group[] = {
+ /* 0-0 */ { 0x0, 0x0, "SPR_PMR", spr_pmr },
+ /* --- */ { -1, -1, NULL, NULL } };
+
+/*------------------------------------------------------------[ PIC group ]---*/
+/* picmr register */
+static const struct spr_bit_def spr_picmr[] = {
+ { "PICMR_IUM", SPR_PICMR_IUM },
+ { NULL, 0 } };
+
+static const struct spr_def spr_pic_group[] = {
+ /* 0-0 */ { 0, 0, "PICMR", spr_picmr },
+ /* 2-2 */ { 2, 2, "PICSR", spr_one_val },
+ /* --- */ { -1, -1, NULL, NULL } };
+
+/*-----------------------------------------------------[ Tick timer group ]---*/
+static const struct spr_bit_def spr_ttmr[] = {
+ { "TTMR_PERIOD", SPR_TTMR_PERIOD },
+ { "TTMR_IP", SPR_TTMR_IP },
+ { "TTMR_IE", SPR_TTMR_IE },
+ { "TTMR_M", SPR_TTMR_M },
+ { NULL, 0 } };
+
+static const struct spr_def spr_tt_group[] = {
+ /* 0-0 */ { 0, 0, "TTMR", spr_ttmr },
+ /* 1-1 */ { 0, 0, "TTCR", spr_one_val },
+ /* --- */ { -1, -1, NULL, NULL } };
+
+/* Spr groups */
+static const struct spr_def *spr_groups[] = {
+ /* 00 */ spr_sys_group,
+ /* 01 */ spr_dmmu_group,
+ /* 02 */ spr_immu_group,
+ /* 03 */ spr_dc_group,
+ /* 04 */ spr_ic_group,
+ /* 05 */ spr_mac_group,
+ /* 06 */ spr_d_group,
+ /* 07 */ spr_pc_group,
+ /* 08 */ spr_pm_group,
+ /* 09 */ spr_pic_group,
+ /* 0a */ spr_tt_group };
+
+/* Should be long enough for everything */
+static char ret_spr[1000];
+
+/* Dumps the given spr in nice, human readable form */
+char *dump_spr(uint16_t spr, uorreg_t spr_val)
+{
+ const struct spr_def *spr_def;
+ uint16_t spr_in_group = spr & (MAX_SPRS_PER_GRP - 1);
+ uint16_t spr_group = spr >> MAX_SPRS_PER_GRP_BITS;
+ const struct spr_bit_def *spr_bit_def;
+
+ int first_bit = 1;
+ int i;
+ uorreg_t tmp;
+
+ spr_def = spr_groups[spr_group];
+
+ /* Find the given spr */
+ for(; spr_def->from_spr != 0xffff; spr_def++) {
+ if((spr_def->from_spr <= spr_in_group) && (spr_def->to_spr >= spr_in_group))
+ break;
+ }
+
+ if(spr_def->from_spr == 0xffff) {
+ sprintf(ret_spr, "Spr %"PRIx16", group %"PRIx16" = 0x%"PRIxREG"\n",
+ spr_in_group, spr_group, spr_val);
+ return ret_spr;
+ }
+
+ /* Decode the spr bits and show them in a pretty format */
+ if(spr_def->from_spr == spr_def->to_spr)
+ sprintf(ret_spr, "%s", spr_def->name);
+ else
+ sprintf(ret_spr, spr_def->name, spr_in_group - spr_def->from_spr);
+ strcat(ret_spr, " = ");
+
+ /* First get all the single-bit bit fields and dump them */
+ for(spr_bit_def = spr_def->bits; spr_bit_def->name; spr_bit_def++) {
+ if(!is_power2(spr_bit_def->mask))
+ continue;
+
+ if(!(spr_bit_def->mask & spr_val))
+ continue;
+
+ if(!first_bit)
+ strcat(ret_spr, " | ");
+ else
+ first_bit = 0;
+ strcat(ret_spr, spr_bit_def->name);
+ }
+
+ /* Now dump all the multi-bit bit fields */
+ for(spr_bit_def = spr_def->bits; spr_bit_def->name; spr_bit_def++) {
+ if(is_power2(spr_bit_def->mask))
+ continue;
+ if(!first_bit)
+ strcat(ret_spr, " | ");
+ else
+ first_bit = 0;
+ for(tmp = spr_bit_def->mask, i = 0; !(tmp & 1); i++)
+ tmp >>= 1;
+
+ sprintf(ret_spr, "%s%s = %" PRIxREG, ret_spr, spr_bit_def->name,
+ (spr_val >> i) & tmp);
+ }
+ return ret_spr;
+}
+
spr-dump.c
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+Id
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Index: Makefile.am
===================================================================
--- Makefile.am (nonexistent)
+++ Makefile.am (revision 388)
@@ -0,0 +1,33 @@
+# Makefile -- Makefile for OR1K architecture dependent simulation
+#
+# Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
+# Copyright (C) 2008 Embecosm Limited
+#
+# Contributor Jeremy Bennett
+#
+# This file is part of OpenRISC 1000 Architectural Simulator.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 3 of the License, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program. If not, see .
+
+
+noinst_LTLIBRARIES = libor1k.la
+libor1k_la_SOURCES = sprs.c \
+ except.c \
+ spr-dump.c \
+ sprs.h \
+ except.h \
+ spr-dump.h \
+ arch.h \
+ spr-defs.h \
+ opcode/or32.h
Makefile.am
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## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+Id
\ No newline at end of property
Index: except.c
===================================================================
--- except.c (nonexistent)
+++ except.c (revision 388)
@@ -0,0 +1,161 @@
+/* except.c -- Simulation of OR1K exceptions
+
+ Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
+ Copyright (C) 2008 Embecosm Limited
+
+ Contributor Jeremy Bennett
+
+ This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 3 of the License, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program. If not, see . */
+
+/* This program is commented throughout in a fashion suitable for processing
+ with Doxygen. */
+
+
+/* Autoconf and/or portability configuration */
+#include "config.h"
+
+/* Package includes */
+#include "except.h"
+#include "sim-config.h"
+#include "arch.h"
+#include "debug.h"
+#include "spr-defs.h"
+#include "execute.h"
+#include "debug-unit.h"
+
+#if DYNAMIC_EXECUTION
+#include "sched.h"
+#include "op-support.h"
+#endif
+
+extern void op_join_mem_cycles(void);
+
+
+
+int except_pending = 0;
+
+/* Asserts OR1K exception. */
+/* WARNING: Don't expect except_handle to return. Sometimes it _may_ return at
+ * other times it may not. */
+void
+except_handle (oraddr_t except, oraddr_t ea)
+{
+ oraddr_t except_vector;
+
+ if (debug_ignore_exception (except))
+ return;
+
+#if !(DYNAMIC_EXECUTION)
+ /* In the dynamic recompiler, this function never returns, so this is not
+ * needed. Ofcourse we could set it anyway, but then all code that checks
+ * this variable would break, since it is never reset */
+ except_pending = 1;
+#endif
+
+ except_vector =
+ except + (cpu_state.sprs[SPR_SR] & SPR_SR_EPH ? 0xf0000000 : 0x00000000);
+
+#if !(DYNAMIC_EXECUTION)
+ pcnext = except_vector;
+#endif
+
+ cpu_state.sprs[SPR_EEAR_BASE] = ea;
+ cpu_state.sprs[SPR_ESR_BASE] = cpu_state.sprs[SPR_SR];
+
+ cpu_state.sprs[SPR_SR] &= ~SPR_SR_OVE; /* Disable overflow flag exception. */
+
+ cpu_state.sprs[SPR_SR] |= SPR_SR_SM; /* SUPV mode */
+ cpu_state.sprs[SPR_SR] &= ~(SPR_SR_IEE | SPR_SR_TEE); /* Disable interrupts. */
+
+ /* Address translation is always disabled when starting exception. */
+ cpu_state.sprs[SPR_SR] &= ~SPR_SR_DME;
+
+#if DYNAMIC_EXECUTION
+ /* If we were called from do_scheduler and there were more jobs scheduled to
+ * run after this, they won't run unless the following call is made since this
+ * function never returns. (If we weren't called from do_scheduler, then the
+ * job at the head of the queue will still have some time remaining) */
+ if (scheduler.job_queue->time <= 0)
+ do_scheduler ();
+#endif
+
+ switch (except)
+ {
+ /* EPCR is irrelevent */
+ case EXCEPT_RESET:
+ break;
+ /* EPCR is loaded with address of instruction that caused the exception */
+ case EXCEPT_ITLBMISS:
+ case EXCEPT_IPF:
+ cpu_state.sprs[SPR_EPCR_BASE] = ea - (cpu_state.delay_insn ? 4 : 0);
+#if DYNAMIC_EXECUTION
+ op_join_mem_cycles ();
+#endif
+ break;
+ case EXCEPT_BUSERR:
+ case EXCEPT_DPF:
+ case EXCEPT_ALIGN:
+ case EXCEPT_ILLEGAL:
+ case EXCEPT_DTLBMISS:
+ case EXCEPT_RANGE:
+ case EXCEPT_TRAP:
+ /* All these exceptions happen during a simulated instruction */
+#if DYNAMIC_EXECUTION
+ /* Since these exceptions happen during a simulated instruction and this
+ * function jumps out to the exception vector the scheduler would never have
+ * a chance to run, therefore run it now */
+ run_sched_out_of_line ();
+#endif
+ cpu_state.sprs[SPR_EPCR_BASE] =
+ cpu_state.pc - (cpu_state.delay_insn ? 4 : 0);
+ break;
+ /* EPCR is loaded with address of next not-yet-executed instruction */
+ case EXCEPT_SYSCALL:
+ cpu_state.sprs[SPR_EPCR_BASE] =
+ (cpu_state.pc + 4) - (cpu_state.delay_insn ? 4 : 0);
+ break;
+ /* These exceptions happen AFTER (or before) an instruction has been
+ * simulated, therefore the pc already points to the *next* instruction */
+ case EXCEPT_TICK:
+ case EXCEPT_INT:
+ cpu_state.sprs[SPR_EPCR_BASE] =
+ cpu_state.pc - (cpu_state.delay_insn ? 4 : 0);
+#if !(DYNAMIC_EXECUTION)
+ /* If we don't update the pc now, then it will only happen *after* the next
+ * instruction (There would be serious problems if the next instruction just
+ * happens to be a branch), when it should happen NOW. */
+ cpu_state.pc = pcnext;
+ pcnext += 4;
+#endif
+ break;
+ }
+
+ /* Address trnaslation is here because run_sched_out_of_line calls
+ * eval_insn_direct which checks out the immu for the address translation but
+ * if it would be disabled above then there would be not much point... */
+ cpu_state.sprs[SPR_SR] &= ~SPR_SR_IME;
+
+ /* Complex/simple execution strictly don't need this because of the
+ * next_delay_insn thingy but in the dynamic execution modell that doesn't
+ * exist and thus cpu_state.delay_insn would stick in the exception handler
+ * causeing grief if the first instruction of the exception handler is also in
+ * the delay slot of the previous instruction */
+ cpu_state.delay_insn = 0;
+
+#if DYNAMIC_EXECUTION
+ do_jump (except_vector);
+#endif
+}
except.c
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+Id
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Index: .cvsignore
===================================================================
--- .cvsignore (nonexistent)
+++ .cvsignore (revision 388)
@@ -0,0 +1,2 @@
+Makefile
+.deps
Index: spr-dump.h
===================================================================
--- spr-dump.h (nonexistent)
+++ spr-dump.h (revision 388)
@@ -0,0 +1,41 @@
+/* spr_dump.h -- Dump given spr in human readable form header
+
+ Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
+ Copyright (C) 2008 Embecosm Limited
+
+ Contributor Jeremy Bennett
+
+ This file is part of OpenRISC 1000 Architectural Simulator.
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 3 of the License, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program. If not, see . */
+
+/* This program is commented throughout in a fashion suitable for processing
+ with Doxygen. */
+
+
+#ifndef SPR_DUMP__H
+#define SPR_DUMP__H
+
+/* System includes */
+#include
+
+/* Package includes */
+#include "arch.h"
+
+
+/* Function prototypes for external use */
+extern char *dump_spr (uint16_t spr,
+ uorreg_t spr_val);
+
+#endif /* SPR_DUMP__H */
spr-dump.h
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Index: sprs.h
===================================================================
--- sprs.h (nonexistent)
+++ sprs.h (revision 388)
@@ -0,0 +1,44 @@
+/* sprs.h -- OR1K architecture specific special-purpose registers
+
+ Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
+ Copyright (C) 2008 Embecosm Limited
+
+ Contributor Jeremy Bennett
+
+ This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 3 of the License, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program. If not, see . */
+
+/* This program is commented throughout in a fashion suitable for processing
+ with Doxygen. */
+
+
+#ifndef SPRS__H
+#define SPRS__H
+
+/* Autoconf and/or portability configuration */
+#include "port.h"
+
+/* Package includes */
+#include "arch.h"
+
+/* Function prototypes for external use */
+extern void mtspr (uint16_t regno,
+ const uorreg_t value);
+extern uorreg_t mfspr (const uint16_t regno);
+extern void sprs_status ();
+extern char *dump_spr (uint16_t spr,
+ uorreg_t spr_val);
+
+#endif /* SPRS__H */
sprs.h
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Index: except.h
===================================================================
--- except.h (nonexistent)
+++ except.h (revision 388)
@@ -0,0 +1,55 @@
+/* except.h -- OR1K architecture specific exceptions
+
+ Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
+ Copyright (C) 2008 Embecosm Limited
+
+ Contributor Jeremy Bennett
+
+ This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 3 of the License, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program. If not, see . */
+
+/* This program is commented throughout in a fashion suitable for processing
+ with Doxygen. */
+
+
+#ifndef EXCEPT__H
+#define EXCEPT__H
+
+
+/* Package includes */
+#include "arch.h"
+
+/* Definition of OR1K exceptions */
+#define EXCEPT_NONE 0x0000
+#define EXCEPT_RESET 0x0100
+#define EXCEPT_BUSERR 0x0200
+#define EXCEPT_DPF 0x0300
+#define EXCEPT_IPF 0x0400
+#define EXCEPT_TICK 0x0500
+#define EXCEPT_ALIGN 0x0600
+#define EXCEPT_ILLEGAL 0x0700
+#define EXCEPT_INT 0x0800
+#define EXCEPT_DTLBMISS 0x0900
+#define EXCEPT_ITLBMISS 0x0a00
+#define EXCEPT_RANGE 0x0b00
+#define EXCEPT_SYSCALL 0x0c00
+#define EXCEPT_FPE 0x0d00
+#define EXCEPT_TRAP 0x0e00
+
+/* Function prototypes for external use */
+extern void except_handle (oraddr_t except, oraddr_t ea);
+extern int except_pending;
+
+#endif /* EXCEPT__H */
except.h
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