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https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/bootloaders
- from Rev 195 to Rev 246
- ↔ Reverse comparison
Rev 195 → Rev 246
/orpmon/include/spr_defs.h
File deleted
orpmon/include/spr_defs.h
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpmon/include/build.h
===================================================================
--- orpmon/include/build.h (revision 195)
+++ orpmon/include/build.h (revision 246)
@@ -1 +1 @@
-#define BUILD_VERSION "Fri Jul 9 18:27:45 CEST 2010"
+#define BUILD_VERSION "Mon Aug 23 20:04:04 CEST 2010"
Index: orpmon/include/spincursor.h
===================================================================
--- orpmon/include/spincursor.h (revision 195)
+++ orpmon/include/spincursor.h (revision 246)
@@ -2,4 +2,3 @@
void spincursor(void);
void enable_spincursor(void);
void disable_spincursor(void);
-
Index: orpmon/include/spr-defs.h
===================================================================
--- orpmon/include/spr-defs.h (nonexistent)
+++ orpmon/include/spr-defs.h (revision 246)
@@ -0,0 +1,636 @@
+/* ipc.h. Microkernel IPC header for Or1ksim
+
+ Copyright (C) 2000 Damjan Lampret
+ Copyright (C) 2008, 2010 Embecosm Limited
+
+ Contributor Damjan Lampret
+ Contributor Jeremy Bennett
+
+ This file is part of OpenRISC 1000 Architectural Simulator.
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 3 of the License, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program. If not, see . */
+
+/* ----------------------------------------------------------------------------
+ This code is commented throughout for use with Doxygen.
+ --------------------------------------------------------------------------*/
+
+/* This file is part of test microkernel for OpenRISC 1000. */
+/* spr-defs.h -- Defines OR1K architecture specific special-purpose registers
+
+ Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
+ Copyright (C) 2008 Embecosm Limited
+
+ Contributor Jeremy Bennett
+
+ This file is part of OpenRISC 1000 Architectural Simulator.
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 3 of the License, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program. If not, see . */
+
+/* This program is commented throughout in a fashion suitable for processing
+ with Doxygen. */
+
+
+#ifndef SPR_DEFS__H
+#define SPR_DEFS__H
+
+/* Definition of special-purpose registers (SPRs). */
+
+#define MAX_GRPS (32)
+#define MAX_SPRS_PER_GRP_BITS (11)
+#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
+#define MAX_SPRS (0x10000)
+
+/* Base addresses for the groups */
+#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_FP (11<< MAX_SPRS_PER_GRP_BITS)
+
+/* System control and status group */
+#define SPR_VR (SPRGROUP_SYS + 0)
+#define SPR_UPR (SPRGROUP_SYS + 1)
+#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
+#define SPR_DMMUCFGR (SPRGROUP_SYS + 3)
+#define SPR_IMMUCFGR (SPRGROUP_SYS + 4)
+#define SPR_DCCFGR (SPRGROUP_SYS + 5)
+#define SPR_ICCFGR (SPRGROUP_SYS + 6)
+#define SPR_DCFGR (SPRGROUP_SYS + 7)
+#define SPR_PCCFGR (SPRGROUP_SYS + 8)
+#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
+#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
+#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */
+#define SPR_FPCSR (SPRGROUP_SYS + 20) /* CZ 21/06/01 */
+#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */
+#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */
+#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
+#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
+#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
+#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
+#define SPR_GPR_BASE (SPRGROUP_SYS + 1024)
+
+/* Data MMU group */
+#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
+#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
+#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
+#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
+#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
+
+/* Instruction MMU group */
+#define SPR_IMMUCR (SPRGROUP_IMMU + 0)
+#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
+#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
+#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
+#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
+
+/* Data cache group */
+#define SPR_DCCR (SPRGROUP_DC + 0)
+#define SPR_DCBPR (SPRGROUP_DC + 1)
+#define SPR_DCBFR (SPRGROUP_DC + 2)
+#define SPR_DCBIR (SPRGROUP_DC + 3)
+#define SPR_DCBWR (SPRGROUP_DC + 4)
+#define SPR_DCBLR (SPRGROUP_DC + 5)
+#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
+#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
+
+/* Instruction cache group */
+#define SPR_ICCR (SPRGROUP_IC + 0)
+#define SPR_ICBPR (SPRGROUP_IC + 1)
+#define SPR_ICBIR (SPRGROUP_IC + 2)
+#define SPR_ICBLR (SPRGROUP_IC + 3)
+#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
+#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
+
+/* MAC group */
+#define SPR_MACLO (SPRGROUP_MAC + 1)
+#define SPR_MACHI (SPRGROUP_MAC + 2)
+
+/* Debug group */
+#define SPR_DVR(N) (SPRGROUP_D + (N))
+#define SPR_DCR(N) (SPRGROUP_D + 8 + (N))
+#define SPR_DMR1 (SPRGROUP_D + 16)
+#define SPR_DMR2 (SPRGROUP_D + 17)
+#define SPR_DWCR0 (SPRGROUP_D + 18)
+#define SPR_DWCR1 (SPRGROUP_D + 19)
+#define SPR_DSR (SPRGROUP_D + 20)
+#define SPR_DRR (SPRGROUP_D + 21)
+
+/* Performance counters group */
+#define SPR_PCCR(N) (SPRGROUP_PC + (N))
+#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N))
+
+/* Power management group */
+#define SPR_PMR (SPRGROUP_PM + 0)
+
+/* PIC group */
+#define SPR_PICMR (SPRGROUP_PIC + 0)
+#define SPR_PICPR (SPRGROUP_PIC + 1)
+#define SPR_PICSR (SPRGROUP_PIC + 2)
+
+/* Tick Timer group */
+#define SPR_TTMR (SPRGROUP_TT + 0)
+#define SPR_TTCR (SPRGROUP_TT + 1)
+
+/*
+ * Bit definitions for the Version Register
+ *
+ */
+#define SPR_VR_VER 0xff000000 /* Processor version */
+#define SPR_VR_CFG 0x00ff0000 /* Processor configuration */
+#define SPR_VR_RES 0x0000ffc0 /* Reserved */
+#define SPR_VR_REV 0x0000003f /* Processor revision */
+
+#define SPR_VR_VER_OFF 24
+#define SPR_VR_CFG_OFF 16
+#define SPR_VR_REV_OFF 0
+
+/*
+ * Bit definitions for the Unit Present Register
+ *
+ */
+#define SPR_UPR_UP 0x00000001 /* UPR present */
+#define SPR_UPR_DCP 0x00000002 /* Data cache present */
+#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */
+#define SPR_UPR_DMP 0x00000008 /* Data MMU present */
+#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */
+#define SPR_UPR_MP 0x00000020 /* MAC present */
+#define SPR_UPR_DUP 0x00000040 /* Debug unit present */
+#define SPR_UPR_PCUP 0x00000080 /* Performance counters unit present */
+#define SPR_UPR_PMP 0x00000100 /* Power management present */
+#define SPR_UPR_PICP 0x00000200 /* PIC present */
+#define SPR_UPR_TTP 0x00000400 /* Tick timer present */
+#define SPR_UPR_RES 0x00fe0000 /* Reserved */
+#define SPR_UPR_CUP 0xff000000 /* Context units present */
+
+/*
+ * JPB: Bit definitions for the CPU configuration register
+ *
+ */
+#define SPR_CPUCFGR_NSGF 0x0000000f /* Number of shadow GPR files */
+#define SPR_CPUCFGR_CGF 0x00000010 /* Custom GPR file */
+#define SPR_CPUCFGR_OB32S 0x00000020 /* ORBIS32 supported */
+#define SPR_CPUCFGR_OB64S 0x00000040 /* ORBIS64 supported */
+#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */
+#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */
+#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */
+#define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */
+
+/*
+ * JPB: Bit definitions for the Debug configuration register and other
+ * constants.
+ *
+ */
+
+#define SPR_DCFGR_NDP 0x00000007 /* Number of matchpoints mask */
+#define SPR_DCFGR_NDP1 0x00000000 /* One matchpoint supported */
+#define SPR_DCFGR_NDP2 0x00000001 /* Two matchpoints supported */
+#define SPR_DCFGR_NDP3 0x00000002 /* Three matchpoints supported */
+#define SPR_DCFGR_NDP4 0x00000003 /* Four matchpoints supported */
+#define SPR_DCFGR_NDP5 0x00000004 /* Five matchpoints supported */
+#define SPR_DCFGR_NDP6 0x00000005 /* Six matchpoints supported */
+#define SPR_DCFGR_NDP7 0x00000006 /* Seven matchpoints supported */
+#define SPR_DCFGR_NDP8 0x00000007 /* Eight matchpoints supported */
+#define SPR_DCFGR_WPCI 0x00000008 /* Watchpoint counters implemented */
+
+#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \
+ 2 == n ? SPR_DCFGR_NDP2 : \
+ 3 == n ? SPR_DCFGR_NDP3 : \
+ 4 == n ? SPR_DCFGR_NDP4 : \
+ 5 == n ? SPR_DCFGR_NDP5 : \
+ 6 == n ? SPR_DCFGR_NDP6 : \
+ 7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8)
+#define MAX_MATCHPOINTS 8
+#define MAX_WATCHPOINTS (MAX_MATCHPOINTS + 2)
+
+/*
+ * Bit definitions for the Supervision Register
+ *
+ */
+#define SPR_SR_SM 0x00000001 /* Supervisor Mode */
+#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */
+#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */
+#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
+#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
+#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
+#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
+#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
+#define SPR_SR_CE 0x00000100 /* CID Enable */
+#define SPR_SR_F 0x00000200 /* Condition Flag */
+#define SPR_SR_CY 0x00000400 /* Carry flag */
+#define SPR_SR_OV 0x00000800 /* Overflow flag */
+#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
+#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
+#define SPR_SR_EPH 0x00004000 /* Exception Prefix High */
+#define SPR_SR_FO 0x00008000 /* Fixed one */
+#define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
+#define SPR_SR_RES 0x0ffe0000 /* Reserved */
+#define SPR_SR_CID 0xf0000000 /* Context ID */
+
+/*
+ * Bit definitions for the Data MMU Control Register
+ *
+ */
+#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */
+#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
+#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
+#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
+
+/*
+ * Bit definitions for the Instruction MMU Control Register
+ *
+ */
+#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */
+#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
+#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
+#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
+
+/*
+ * Bit definitions for the Data TLB Match Register
+ *
+ */
+#define SPR_DTLBMR_V 0x00000001 /* Valid */
+#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
+#define SPR_DTLBMR_CID 0x0000003c /* Context ID */
+#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */
+#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */
+
+/*
+ * Bit definitions for the Data TLB Translate Register
+ *
+ */
+#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */
+#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */
+#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */
+#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
+#define SPR_DTLBTR_A 0x00000010 /* Accessed */
+#define SPR_DTLBTR_D 0x00000020 /* Dirty */
+#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */
+#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */
+#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
+#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
+#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */
+
+/*
+ * Bit definitions for the Instruction TLB Match Register
+ *
+ */
+#define SPR_ITLBMR_V 0x00000001 /* Valid */
+#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
+#define SPR_ITLBMR_CID 0x0000003c /* Context ID */
+#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */
+#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */
+
+/*
+ * Bit definitions for the Instruction TLB Translate Register
+ *
+ */
+#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */
+#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */
+#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */
+#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
+#define SPR_ITLBTR_A 0x00000010 /* Accessed */
+#define SPR_ITLBTR_D 0x00000020 /* Dirty */
+#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */
+#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */
+#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */
+
+/*
+ * Bit definitions for Data Cache Control register
+ *
+ */
+#define SPR_DCCR_EW 0x000000ff /* Enable ways */
+
+/*
+ * Bit definitions for Insn Cache Control register
+ *
+ */
+#define SPR_ICCR_EW 0x000000ff /* Enable ways */
+
+/*
+ * Bit definitions for Data Cache Configuration Register
+ *
+ */
+
+#define SPR_DCCFGR_NCW 0x00000007
+#define SPR_DCCFGR_NCS 0x00000078
+#define SPR_DCCFGR_CBS 0x00000080
+#define SPR_DCCFGR_CWS 0x00000100
+#define SPR_DCCFGR_CCRI 0x00000200
+#define SPR_DCCFGR_CBIRI 0x00000400
+#define SPR_DCCFGR_CBPRI 0x00000800
+#define SPR_DCCFGR_CBLRI 0x00001000
+#define SPR_DCCFGR_CBFRI 0x00002000
+#define SPR_DCCFGR_CBWBRI 0x00004000
+
+#define SPR_DCCFGR_NCW_OFF 0
+#define SPR_DCCFGR_NCS_OFF 3
+#define SPR_DCCFGR_CBS_OFF 7
+
+/*
+ * Bit definitions for Instruction Cache Configuration Register
+ *
+ */
+#define SPR_ICCFGR_NCW 0x00000007
+#define SPR_ICCFGR_NCS 0x00000078
+#define SPR_ICCFGR_CBS 0x00000080
+#define SPR_ICCFGR_CCRI 0x00000200
+#define SPR_ICCFGR_CBIRI 0x00000400
+#define SPR_ICCFGR_CBPRI 0x00000800
+#define SPR_ICCFGR_CBLRI 0x00001000
+
+#define SPR_ICCFGR_NCW_OFF 0
+#define SPR_ICCFGR_NCS_OFF 3
+#define SPR_ICCFGR_CBS_OFF 7
+
+/*
+ * Bit definitions for Data MMU Configuration Register
+ *
+ */
+
+#define SPR_DMMUCFGR_NTW 0x00000003
+#define SPR_DMMUCFGR_NTS 0x0000001C
+#define SPR_DMMUCFGR_NAE 0x000000E0
+#define SPR_DMMUCFGR_CRI 0x00000100
+#define SPR_DMMUCFGR_PRI 0x00000200
+#define SPR_DMMUCFGR_TEIRI 0x00000400
+#define SPR_DMMUCFGR_HTR 0x00000800
+
+#define SPR_DMMUCFGR_NTW_OFF 0
+#define SPR_DMMUCFGR_NTS_OFF 2
+
+/*
+ * Bit definitions for Instruction MMU Configuration Register
+ *
+ */
+
+#define SPR_IMMUCFGR_NTW 0x00000003
+#define SPR_IMMUCFGR_NTS 0x0000001C
+#define SPR_IMMUCFGR_NAE 0x000000E0
+#define SPR_IMMUCFGR_CRI 0x00000100
+#define SPR_IMMUCFGR_PRI 0x00000200
+#define SPR_IMMUCFGR_TEIRI 0x00000400
+#define SPR_IMMUCFGR_HTR 0x00000800
+
+#define SPR_IMMUCFGR_NTW_OFF 0
+#define SPR_IMMUCFGR_NTS_OFF 2
+
+/*
+ * Bit definitions for Debug Control registers
+ *
+ */
+#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
+#define SPR_DCR_CC 0x0000000e /* Compare condition */
+#define SPR_DCR_SC 0x00000010 /* Signed compare */
+#define SPR_DCR_CT 0x000000e0 /* Compare to */
+
+/* Bit results with SPR_DCR_CC mask */
+#define SPR_DCR_CC_MASKED 0x00000000
+#define SPR_DCR_CC_EQUAL 0x00000002
+#define SPR_DCR_CC_LESS 0x00000004
+#define SPR_DCR_CC_LESSE 0x00000006
+#define SPR_DCR_CC_GREAT 0x00000008
+#define SPR_DCR_CC_GREATE 0x0000000a
+#define SPR_DCR_CC_NEQUAL 0x0000000c
+
+/* Bit results with SPR_DCR_CT mask */
+#define SPR_DCR_CT_DISABLED 0x00000000
+#define SPR_DCR_CT_IFEA 0x00000020
+#define SPR_DCR_CT_LEA 0x00000040
+#define SPR_DCR_CT_SEA 0x00000060
+#define SPR_DCR_CT_LD 0x00000080
+#define SPR_DCR_CT_SD 0x000000a0
+#define SPR_DCR_CT_LSEA 0x000000c0
+#define SPR_DCR_CT_LSD 0x000000e0
+/* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */
+
+/*
+ * Bit definitions for Debug Mode 1 register
+ *
+ */
+#define SPR_DMR1_CW 0x000fffff /* Chain register pair data */
+#define SPR_DMR1_CW0_AND 0x00000001
+#define SPR_DMR1_CW0_OR 0x00000002
+#define SPR_DMR1_CW0 (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR)
+#define SPR_DMR1_CW1_AND 0x00000004
+#define SPR_DMR1_CW1_OR 0x00000008
+#define SPR_DMR1_CW1 (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR)
+#define SPR_DMR1_CW2_AND 0x00000010
+#define SPR_DMR1_CW2_OR 0x00000020
+#define SPR_DMR1_CW2 (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR)
+#define SPR_DMR1_CW3_AND 0x00000040
+#define SPR_DMR1_CW3_OR 0x00000080
+#define SPR_DMR1_CW3 (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR)
+#define SPR_DMR1_CW4_AND 0x00000100
+#define SPR_DMR1_CW4_OR 0x00000200
+#define SPR_DMR1_CW4 (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR)
+#define SPR_DMR1_CW5_AND 0x00000400
+#define SPR_DMR1_CW5_OR 0x00000800
+#define SPR_DMR1_CW5 (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR)
+#define SPR_DMR1_CW6_AND 0x00001000
+#define SPR_DMR1_CW6_OR 0x00002000
+#define SPR_DMR1_CW6 (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR)
+#define SPR_DMR1_CW7_AND 0x00004000
+#define SPR_DMR1_CW7_OR 0x00008000
+#define SPR_DMR1_CW7 (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR)
+#define SPR_DMR1_CW8_AND 0x00010000
+#define SPR_DMR1_CW8_OR 0x00020000
+#define SPR_DMR1_CW8 (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR)
+#define SPR_DMR1_CW9_AND 0x00040000
+#define SPR_DMR1_CW9_OR 0x00080000
+#define SPR_DMR1_CW9 (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR)
+#define SPR_DMR1_RES1 0x00300000 /* Reserved */
+#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/
+#define SPR_DMR1_BT 0x00800000 /* Branch trace */
+#define SPR_DMR1_RES2 0xff000000 /* Reserved */
+
+/*
+ * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
+ *
+ */
+#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */
+#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */
+#define SPR_DMR2_AWTC 0x00000ffc /* Assign watchpoints to counters */
+#define SPR_DMR2_AWTC_OFF 2 /* Bit offset to AWTC field */
+#define SPR_DMR2_WGB 0x003ff000 /* Watchpoints generating breakpoint */
+#define SPR_DMR2_WGB_OFF 12 /* Bit offset to WGB field */
+#define SPR_DMR2_WBS 0xffc00000 /* JPB: Watchpoint status */
+#define SPR_DMR2_WBS_OFF 22 /* Bit offset to WBS field */
+
+/*
+ * Bit definitions for Debug watchpoint counter registers
+ *
+ */
+#define SPR_DWCR_COUNT 0x0000ffff /* Count */
+#define SPR_DWCR_MATCH 0xffff0000 /* Match */
+#define SPR_DWCR_MATCH_OFF 16 /* Match bit offset */
+
+/*
+ * Bit definitions for Debug stop register
+ *
+ */
+#define SPR_DSR_RSTE 0x00000001 /* Reset exception */
+#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */
+#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */
+#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */
+#define SPR_DSR_TTE 0x00000010 /* Tick Timer exception */
+#define SPR_DSR_AE 0x00000020 /* Alignment exception */
+#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */
+#define SPR_DSR_IE 0x00000080 /* Interrupt exception */
+#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
+#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
+#define SPR_DSR_RE 0x00000400 /* Range exception */
+#define SPR_DSR_SCE 0x00000800 /* System call exception */
+#define SPR_DSR_FPE 0x00001000 /* Floating Point Exception */
+#define SPR_DSR_TE 0x00002000 /* Trap exception */
+
+/*
+ * Bit definitions for Debug reason register
+ *
+ */
+#define SPR_DRR_RSTE 0x00000001 /* Reset exception */
+#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */
+#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */
+#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */
+#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */
+#define SPR_DRR_AE 0x00000020 /* Alignment exception */
+#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */
+#define SPR_DRR_IE 0x00000080 /* Interrupt exception */
+#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
+#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
+#define SPR_DRR_RE 0x00000400 /* Range exception */
+#define SPR_DRR_SCE 0x00000800 /* System call exception */
+#define SPR_DRR_FPE 0x00001000 /* Floating Point Exception */
+#define SPR_DRR_TE 0x00002000 /* Trap exception */
+
+/*
+ * Bit definitions for Performance counters mode registers
+ *
+ */
+#define SPR_PCMR_CP 0x00000001 /* Counter present */
+#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */
+#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */
+#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */
+#define SPR_PCMR_LA 0x00000010 /* Load access event */
+#define SPR_PCMR_SA 0x00000020 /* Store access event */
+#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/
+#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */
+#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */
+#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */
+#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */
+#define SPR_PCMR_BS 0x00000800 /* Branch stall event */
+#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */
+#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */
+#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */
+#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */
+
+/*
+ * Bit definitions for the Power management register
+ *
+ */
+#define SPR_PMR_SDF 0x0000000f /* Slow down factor */
+#define SPR_PMR_DME 0x00000010 /* Doze mode enable */
+#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */
+#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */
+#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */
+
+/*
+ * Bit definitions for PICMR
+ *
+ */
+#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */
+
+/*
+ * Bit definitions for PICPR
+ *
+ */
+#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */
+
+/*
+ * Bit definitions for PICSR
+ *
+ */
+#define SPR_PICSR_IS 0xffffffff /* Interrupt status */
+
+/*
+ * Bit definitions for Tick Timer Control Register
+ *
+ */
+#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */
+#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
+#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */
+#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */
+#define SPR_TTMR_DI 0x00000000 /* Disabled */
+#define SPR_TTMR_RT 0x40000000 /* Restart tick */
+#define SPR_TTMR_SR 0x80000000 /* Single run */
+#define SPR_TTMR_CR 0xc0000000 /* Continuous run */
+#define SPR_TTMR_M 0xc0000000 /* Tick mode */
+
+/*
+ * Bit definitions for the FP Control Status Register
+ *
+ */
+#define SPR_FPCSR_FPEE 0x00000001 /* Floating Point Exception Enable */
+#define SPR_FPCSR_RM 0x00000006 /* Rounding Mode */
+#define SPR_FPCSR_OVF 0x00000008 /* Overflow Flag */
+#define SPR_FPCSR_UNF 0x00000010 /* Underflow Flag */
+#define SPR_FPCSR_SNF 0x00000020 /* SNAN Flag */
+#define SPR_FPCSR_QNF 0x00000040 /* QNAN Flag */
+#define SPR_FPCSR_ZF 0x00000080 /* Zero Flag */
+#define SPR_FPCSR_IXF 0x00000100 /* Inexact Flag */
+#define SPR_FPCSR_IVF 0x00000200 /* Invalid Flag */
+#define SPR_FPCSR_INF 0x00000400 /* Infinity Flag */
+#define SPR_FPCSR_DZF 0x00000800 /* Divide By Zero Flag */
+#define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \
+ SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF | \
+ SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF)
+
+#define FPCSR_RM_RN (0<<1)
+#define FPCSR_RM_RZ (1<<1)
+#define FPCSR_RM_RIP (2<<1)
+#define FPCSR_RM_RIN (3<<1)
+
+/*
+ * l.nop constants
+ *
+ */
+#define NOP_NOP 0x0000 /* Normal nop instruction */
+#define NOP_EXIT 0x0001 /* End of simulation */
+#define NOP_REPORT 0x0002 /* Simple report */
+/*#define NOP_PRINTF 0x0003 Simprintf instruction (obsolete)*/
+#define NOP_PUTC 0x0004 /* JPB: Simputc instruction */
+#define NOP_CNT_RESET 0x0005 /* Reset statistics counters */
+#define NOP_GET_TICKS 0x0006 /* JPB: Get # ticks running */
+#define NOP_GET_PS 0x0007 /* JPB: Get picosecs/cycle */
+#define NOP_REPORT_FIRST 0x0400 /* Report with number */
+#define NOP_REPORT_LAST 0x03ff /* Report with number */
+
+#endif /* SPR_DEFS__H */
Index: orpmon/include/board.h
===================================================================
--- orpmon/include/board.h (revision 195)
+++ orpmon/include/board.h (revision 246)
@@ -14,23 +14,20 @@
* 2 - ORSoC A3PE1500 board
* 3 - ORSoC A3P1000 board
*/
-#define BOARD 3
+#define BOARD 2
/* Ethernet IP and TFTP config
* 0 - JB ORSoC board
* 1 - AE ORSoC board
* 2 - JB Southpole board
- * 3 - Unassigned
+ * 3 - JB ORSoC board 2
+ * 4 - Unassigned
*/
-#define IPCONFIG 0
+#define IPCONFIG 3
#if BOARD==0
// Nibbler on bender1
-# define IC_ENABLE 1
-# define IC_SIZE 4096
-# define DC_ENABLE 1
-# define DC_SIZE 2048
# define FLASH_BASE_ADDR 0xf0000000
# define FLASH_SIZE 0x02000000
# define FLASH_BLOCK_SIZE 0x00020000
@@ -45,17 +42,11 @@
# define FLASH_ORG_16_1 1
#elif BOARD==1
//Marvin
-
-# define IC_ENABLE 1
-# define IC_SIZE 8192
-# define DC_ENABLE 0
-# define DC_SIZE 8192
# define FLASH_BASE_ADDR 0xf0000000
# define FLASH_SIZE 0x04000000
# define FLASH_BLOCK_SIZE 0x00040000
# define START_ADD 0x0
# define CONFIG_OR32_MC_VERSION 1
-/*# define IN_CLK 100000000*/
# define IN_CLK 50000000
# define FLASH_ORG_16_2 1
# define BOARD_DEF_NAME "marvin"
@@ -62,22 +53,14 @@
#elif BOARD==2
//ORSoC usbethdev board
-# define IC_ENABLE 1
-# define IC_SIZE 8192
-# define DC_ENABLE 0
-# define DC_SIZE 8192
# define FLASH_BASE_ADDR 0xf0000000
# define FLASH_SIZE 0x04000000
# define FLASH_BLOCK_SIZE 0x00040000
# define START_ADD 0x0
-# define SDRAM_SIZE 0x02000000
-# define SDRAM_ROW_SIZE 0x00000400
-# define SDRAM_BANK_SIZE 0x00800000
-//# define IN_CLK 32000000
-//# define IN_CLK 24000000
+# define SDRAM_SIZE 0x02000000
+# define SDRAM_ROW_SIZE 0x00000400
+# define SDRAM_BANK_SIZE 0x00800000
# define IN_CLK 20000000
-//# define IN_CLK 16000000
-//# define IN_CLK 17000000
# define FLASH_ORG_16_2 1
# define BOARD_DEF_NAME "ORSoC devboard"
@@ -84,33 +67,24 @@
#elif BOARD==3
//ORSoC A3P1000 usbethdev board
-# define IC_ENABLE 1
-# define IC_SIZE 4096
-# define DC_ENABLE 0
-# define DC_SIZE 8192
# define FLASH_BASE_ADDR 0xf0000000
# define FLASH_SIZE 0x04000000
# define FLASH_BLOCK_SIZE 0x00040000
# define START_ADD 0x0
-# define SDRAM_SIZE 0x02000000
-# define SDRAM_ROW_SIZE 0x00000400
-# define SDRAM_BANK_SIZE 0x00800000
-//# define IN_CLK 20000000
-# define IN_CLK 24000000
+# define SDRAM_SIZE 0x02000000
+# define SDRAM_ROW_SIZE 0x00000400
+# define SDRAM_BANK_SIZE 0x00800000
+# define IN_CLK 25000000
# define FLASH_ORG_16_2 1
# define BOARD_DEF_NAME "ORSoC A3P1000 devboard"
#else
//Custom Board
-# define IC_ENABLE 0
-# define IC_SIZE 8192
-# define DC_ENABLE 0
-# define DC_SIZE 8192
+
# define FLASH_BASE_ADDR 0xf0000000
# define FLASH_SIZE 0x04000000
# define FLASH_BLOCK_SIZE 0x00040000
# define START_ADD 0x0
-# define CONFIG_OR32_MC_VERSION 1
# define IN_CLK 25000000
# define FLASH_ORG_16_2 1
# define BOARD_DEF_NAME "custom"
@@ -167,8 +141,24 @@
#define ETH_MACADDR4 0x78
#define ETH_MACADDR5 0x9c
-#elif IPCONFIG==3 // Unassigned config...
+#elif IPCONFIG==3 // ORSoC LAN
+#define BOARD_DEF_IP 0xc0a80003 // 192.168.0.3
+#define BOARD_DEF_MASK 0xffffff00 // 255.255.255.0
+#define BOARD_DEF_GW 0xc0a80002 // 192.168.0.2
+#define BOARD_DEF_TBOOT_SRVR 0xc0a80108 // 192.168.1.8
+#define BOARD_DEF_IMAGE_NAME "boot.img"
+#define BOARD_DEF_LOAD_SPACE 0xa00000
+#define ETH_MDIOPHYADDR 0x00
+#define ETH_MACADDR0 0xad
+#define ETH_MACADDR1 0xaa
+#define ETH_MACADDR2 0x34
+#define ETH_MACADDR3 0x56
+#define ETH_MACADDR4 0x78
+#define ETH_MACADDR5 0x9d
+
+#elif IPCONFIG==4 // Unassigned config...
+
#define BOARD_DEF_IP 0x0a01010a // 10.1.1.10
#define BOARD_DEF_MASK 0xffffff00 // 255.255.255.0
#define BOARD_DEF_GW 0x0a010101 // 10.1.1.1
@@ -221,7 +211,8 @@
#define KBD_IRQ 5
#define SANCHO_BASE_ADD 0x98000000
-#define ETH_DATA_BASE (SDRAM_SIZE - (0x600 * 128)) /* Address for ETH_DATA */
+/* Address for ETH_DATA */
+#define ETH_DATA_BASE (SDRAM_SIZE - (0x600 * 128))
#define CRT_ENABLED 0
#define FB_BASE_ADDR 0xa8000000
/orpmon/reset.S
1,4 → 1,4
#include "spr_defs.h" |
#include "spr-defs.h" |
#include "board.h" |
#include "mc.h" |
|
69,8 → 69,13
l.addi r5,r0,0x00 |
l.sw 0(r3),r5 |
.endif |
l.addi r3,r0,SPR_SR_SM |
l.mtspr r0,r3,SPR_SR |
l.movhi r0, 0 |
/* Clear status register, set supervisor mode */ |
l.ori r1, r0, SPR_SR_SM |
l.mtspr r0, r1, SPR_SR |
/* Clear timer */ |
l.mtspr r0, r0, SPR_TTMR |
/* Jump to start routine */ |
l.movhi r3,hi(_start) |
l.ori r3,r3,lo(_start) |
l.jr r3 |
83,9 → 88,11
.org (0x200 - 0x100 + _reset) |
.endif |
_buserr: |
/* Just trap */ |
.if 0 |
/* Just trap */ |
l.trap 0 |
l.nop |
.endif |
l.nop 0x1 |
l.j 0 |
l.nop |
|
98,10 → 105,12
.endif |
_tickint: |
l.addi r1,r1,-128 |
l.sw 0x4(r1),r2 |
l.movhi r2,hi(_tick) |
l.ori r2,r2,lo(_tick) |
l.jr r2 |
l.sw 0(r1), r2 |
l.addi r2, r1, 128 |
l.sw 0x4(r1),r3 |
l.movhi r3,hi(_tick) |
l.ori r3,r3,lo(_tick) |
l.jr r3 |
l.nop |
|
.if IN_FLASH |
111,17 → 120,10
.org (0x600 - 0x100 + _reset) |
.endif |
_alignerr: |
.if 0 |
/* Let's crash on align errors */ |
l.addi r1,r1,-128 |
l.sw 0x08(r1),r2 |
l.movhi r2,hi(_align) |
l.ori r2,r2,lo(_align) |
l.jr r2 |
l.nop |
.endif |
.if 0 |
l.trap 0 |
l.nop |
.endif |
l.nop 0x1 |
l.j 0 |
l.nop |
|
130,10 → 132,12
.else |
.org (0x700 - 0x100 + _reset) |
.endif |
_illinsn: |
_illinsn: |
.if 0 |
/* Just trap */ |
l.trap 0 |
l.nop |
.endif |
l.nop 0x1 |
l.j 0 |
l.nop |
|
145,10 → 149,12
.endif |
_userint: |
l.addi r1,r1,-128 |
l.sw 0x4(r1),r2 |
l.movhi r2,hi(_int_wrapper) |
l.ori r2,r2,lo(_int_wrapper) |
l.jr r2 |
l.sw 0x0(r1),r2 |
l.addi r2, r1, 128 |
l.sw 0x4(r1), r3 |
l.movhi r3,hi(_int_wrapper) |
l.ori r3,r3,lo(_int_wrapper) |
l.jr r3 |
l.nop |
|
.section .text |
201,137 → 207,162
l.addi r4,r0,0 |
3: |
.endif |
/* |
l.jal _ic_disable |
l.nop |
*/ |
.if IC_ENABLE |
l.jal _ic_enable |
l.nop |
.endif |
|
.if DC_ENABLE |
l.jal _dc_enable |
|
/* Instruction cache enable */ |
/* Check if IC present and skip enabling otherwise */ |
l.mfspr r24,r0,SPR_UPR |
l.andi r26,r24,SPR_UPR_ICP |
l.sfeq r26,r0 |
l.bf .L8 |
l.nop |
|
/* Disable IC */ |
l.mfspr r6,r0,SPR_SR |
l.addi r5,r0,-1 |
l.xori r5,r5,SPR_SR_ICE |
l.and r5,r6,r5 |
l.mtspr r0,r5,SPR_SR |
|
/* Establish cache block size |
If BS=0, 16; |
If BS=1, 32; |
r14 contain block size |
*/ |
l.mfspr r24,r0,SPR_ICCFGR |
l.andi r26,r24,SPR_ICCFGR_CBS |
l.srli r28,r26,7 |
l.ori r30,r0,16 |
l.sll r14,r30,r28 |
|
/* Establish number of cache sets |
r16 contains number of cache sets |
r28 contains log(# of cache sets) |
*/ |
l.andi r26,r24,SPR_ICCFGR_NCS |
l.srli r28,r26,3 |
l.ori r30,r0,1 |
l.sll r16,r30,r28 |
|
/* Invalidate IC */ |
l.addi r6,r0,0 |
l.sll r5,r14,r28 |
|
.L7: |
l.mtspr r0,r6,SPR_ICBIR |
l.sfne r6,r5 |
l.bf .L7 |
l.add r6,r6,r14 |
|
/* Enable IC */ |
l.mfspr r6,r0,SPR_SR |
l.ori r6,r6,SPR_SR_ICE |
l.mtspr r0,r6,SPR_SR |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
|
.L8: |
/* Data cache enable */ |
/* Check if DC present and skip enabling otherwise */ |
l.mfspr r24,r0,SPR_UPR |
l.andi r26,r24,SPR_UPR_DCP |
l.sfeq r26,r0 |
l.bf .L10 |
l.nop |
.endif |
/* Disable DC */ |
l.mfspr r6,r0,SPR_SR |
l.addi r5,r0,-1 |
l.xori r5,r5,SPR_SR_DCE |
l.and r5,r6,r5 |
l.mtspr r0,r5,SPR_SR |
/* Establish cache block size |
If BS=0, 16; |
If BS=1, 32; |
r14 contain block size |
*/ |
l.mfspr r24,r0,SPR_DCCFGR |
l.andi r26,r24,SPR_DCCFGR_CBS |
l.srli r28,r26,7 |
l.ori r30,r0,16 |
l.sll r14,r30,r28 |
/* Establish number of cache sets |
r16 contains number of cache sets |
r28 contains log(# of cache sets) |
*/ |
l.andi r26,r24,SPR_DCCFGR_NCS |
l.srli r28,r26,3 |
l.ori r30,r0,1 |
l.sll r16,r30,r28 |
/* Invalidate DC */ |
l.addi r6,r0,0 |
l.sll r5,r14,r28 |
.L9: |
l.mtspr r0,r6,SPR_DCBIR |
l.sfne r6,r5 |
l.bf .L9 |
l.add r6,r6,r14 |
/* Enable DC */ |
l.mfspr r6,r0,SPR_SR |
l.ori r6,r6,SPR_SR_DCE |
l.mtspr r0,r6,SPR_SR |
|
.L10: |
/* Set up stack */ |
l.movhi r1,hi(_stack-4) |
l.ori r1,r1,lo(_stack-4) |
l.addi r2,r0,-3 |
l.and r1,r1,r2 |
|
l.movhi r2,hi(_main) |
l.ori r2,r2,lo(_main) |
l.jr r2 |
l.addi r2,r0,0 |
|
_ic_enable: |
|
/* Flush IC */ |
l.addi r10,r0,0 |
l.addi r11,r0,IC_SIZE |
1: |
l.mtspr r0,r10,SPR_ICBIR |
l.sfne r10,r11 |
l.bf 1b |
l.addi r10,r10,16 |
|
/* Enable IC */ |
l.mfspr r10,r0,SPR_SR |
l.ori r10,r10,(SPR_SR_ICE|SPR_SR_SM) |
l.mtspr r0,r10,SPR_SR |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
|
l.jr r9 |
l.nop |
|
_ic_disable: |
|
l.addi r10,r0,0 |
l.addi r11,r0,IC_SIZE |
1: |
l.mtspr r0,r10,SPR_ICBIR |
l.sfne r10,r11 |
l.bf 1b |
l.addi r10,r10,16 |
/* l.or r2, r1, r1 - remove this helped with odd UART output problem?!*/ |
|
l.movhi r3,hi(main) |
l.ori r3,r3,lo(main) |
l.jr r3 |
l.nop |
|
l.mfspr r10,r0,SPR_SR |
l.movhi r11, 0xffff |
l.ori r11, r11, 0xffef |
l.and r10, r10, r11 |
l.ori r10, r10, SPR_SR_SM |
l.mtspr r0,r10,SPR_SR |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
|
l.jr r9 |
l.nop |
|
_dc_enable: |
|
/* Flush DC */ |
l.addi r10,r0,0 |
l.addi r11,r0,DC_SIZE |
1: |
l.mtspr r0,r10,SPR_DCBIR |
l.sfne r10,r11 |
l.bf 1b |
l.addi r10,r10,16 |
|
/* Enable DC */ |
l.mfspr r10,r0,SPR_SR |
l.ori r10,r10,(SPR_SR_DCE|SPR_SR_SM) |
l.mtspr r0,r10,SPR_SR |
|
l.jr r9 |
l.nop |
|
|
_tick: |
l.sw 0x8(r1),r4 |
l.sw 0xc(r1),r5 |
l.sw 0x10(r1),r6 |
l.sw 0x14(r1),r7 |
l.sw 0x18(r1),r8 |
l.sw 0x1c(r1),r9 |
l.sw 0x20(r1),r10 |
l.sw 0x24(r1),r11 |
l.sw 0x28(r1),r12 |
l.sw 0x2c(r1),r13 |
l.sw 0x30(r1),r14 |
l.sw 0x34(r1),r15 |
l.sw 0x38(r1),r16 |
l.sw 0x3c(r1),r17 |
l.sw 0x40(r1),r18 |
l.sw 0x44(r1),r19 |
l.sw 0x48(r1),r20 |
l.sw 0x4c(r1),r21 |
l.sw 0x50(r1),r22 |
l.sw 0x54(r1),r23 |
l.sw 0x58(r1),r24 |
l.sw 0x5c(r1),r25 |
l.sw 0x60(r1),r26 |
l.sw 0x64(r1),r27 |
l.sw 0x68(r1),r28 |
l.sw 0x6c(r1),r29 |
l.sw 0x70(r1),r30 |
l.sw 0x74(r1),r31 |
l.sw 0x78(r1),r3 |
|
l.movhi r3,hi(_tick_interrupt) |
l.ori r3,r3,lo(_tick_interrupt) |
l.sw 0x8(r1), r4 |
l.sw 0xc(r1), r5 |
l.sw 0x10(r1), r6 |
l.sw 0x14(r1), r7 |
l.sw 0x18(r1), r8 |
l.sw 0x1c(r1), r9 |
l.sw 0x20(r1), r10 |
l.sw 0x24(r1), r11 |
l.sw 0x28(r1), r12 |
l.sw 0x2c(r1), r13 |
l.sw 0x30(r1), r14 |
l.sw 0x34(r1), r15 |
l.sw 0x38(r1), r16 |
l.sw 0x3c(r1), r17 |
l.sw 0x40(r1), r18 |
l.sw 0x44(r1), r19 |
l.sw 0x48(r1), r20 |
l.sw 0x4c(r1), r21 |
l.sw 0x50(r1), r22 |
l.sw 0x54(r1), r23 |
l.sw 0x58(r1), r24 |
l.sw 0x5c(r1), r25 |
l.sw 0x60(r1), r26 |
l.sw 0x64(r1), r27 |
l.sw 0x68(r1), r28 |
l.sw 0x6c(r1), r29 |
l.sw 0x70(r1), r30 |
l.sw 0x74(r1), r31 |
|
l.movhi r3,hi(tick_interrupt) |
l.ori r3,r3,lo(tick_interrupt) |
l.jalr r3 |
l.nop |
|
l.lwz r2,0x4(r1) |
l.lwz r3,0x4(r1) |
l.lwz r4,0x8(r1) |
l.lwz r5,0xc(r1) |
l.lwz r6,0x10(r1) |
359,51 → 390,50
l.lwz r28,0x68(r1) |
l.lwz r29,0x6c(r1) |
l.lwz r30,0x70(r1) |
l.mfspr r31,r0,0x40 |
l.lwz r31,0x74(r1) |
l.lwz r3,0x78(r1) |
l.lwz r31,0x74(r1) |
|
l.lwz r2, 0x0(r1) |
l.addi r1,r1,128 |
l.rfe |
l.nop |
|
_int_wrapper: |
l.sw 0x8(r1),r4 |
l.sw 0xc(r1),r5 |
l.sw 0x10(r1),r6 |
l.sw 0x14(r1),r7 |
l.sw 0x18(r1),r8 |
l.sw 0x1c(r1),r9 |
l.sw 0x20(r1),r10 |
l.sw 0x24(r1),r11 |
l.sw 0x28(r1),r12 |
l.sw 0x2c(r1),r13 |
l.sw 0x30(r1),r14 |
l.sw 0x34(r1),r15 |
l.sw 0x38(r1),r16 |
l.sw 0x3c(r1),r17 |
l.sw 0x40(r1),r18 |
l.sw 0x44(r1),r19 |
l.sw 0x48(r1),r20 |
l.sw 0x4c(r1),r21 |
l.sw 0x50(r1),r22 |
l.sw 0x54(r1),r23 |
l.sw 0x58(r1),r24 |
l.sw 0x5c(r1),r25 |
l.sw 0x60(r1),r26 |
l.sw 0x64(r1),r27 |
l.sw 0x68(r1),r28 |
l.sw 0x6c(r1),r29 |
l.sw 0x70(r1),r30 |
l.sw 0x74(r1),r31 |
l.sw 0x78(r1),r3 |
|
l.movhi r3,hi(_int_main) |
l.ori r3,r3,lo(_int_main) |
l.sw 0x8(r1), r4 |
l.sw 0xc(r1), r5 |
l.sw 0x10(r1), r6 |
l.sw 0x14(r1), r7 |
l.sw 0x18(r1), r8 |
l.sw 0x1c(r1), r9 |
l.sw 0x20(r1), r10 |
l.sw 0x24(r1), r11 |
l.sw 0x28(r1), r12 |
l.sw 0x2c(r1), r13 |
l.sw 0x30(r1), r14 |
l.sw 0x34(r1), r15 |
l.sw 0x38(r1), r16 |
l.sw 0x3c(r1), r17 |
l.sw 0x40(r1), r18 |
l.sw 0x44(r1), r19 |
l.sw 0x48(r1), r20 |
l.sw 0x4c(r1), r21 |
l.sw 0x50(r1), r22 |
l.sw 0x54(r1), r23 |
l.sw 0x58(r1), r24 |
l.sw 0x5c(r1), r25 |
l.sw 0x60(r1), r26 |
l.sw 0x64(r1), r27 |
l.sw 0x68(r1), r28 |
l.sw 0x6c(r1), r29 |
l.sw 0x70(r1), r30 |
l.sw 0x74(r1), r31 |
|
l.movhi r3,hi(int_main) |
l.ori r3,r3,lo(int_main) |
l.jalr r3 |
l.nop |
|
l.lwz r2,0x4(r1) |
l.lwz r3,0x4(r1) |
l.lwz r4,0x8(r1) |
l.lwz r5,0xc(r1) |
l.lwz r6,0x10(r1) |
431,14 → 461,13
l.lwz r28,0x68(r1) |
l.lwz r29,0x6c(r1) |
l.lwz r30,0x70(r1) |
l.lwz r31,0x74(r1) |
l.lwz r3,0x78(r1) |
l.lwz r31,0x74(r1) |
|
l.mtspr r0,r0,SPR_PICSR |
|
l.lwz r2, 0x0(r1) |
l.addi r1,r1,128 |
l.rfe |
l.nop |
|
|
_align: |
l.sw 0x0c(r1),r3 |
/orpmon/services/modem.c
2,7 → 2,7
#include "support.h" |
#include "net.h" |
#include "uart.h" |
#include "spr_defs.h" |
#include "spr-defs.h" |
#include "flash.h" |
|
#define SOH 0x01 |
/orpmon/services/net.c
67,8 → 67,10
#include "arp.h" |
#if OC_LAN==1 |
#include "eth.h" |
#else if SMC91111_LAN==1 |
#include "smc91111.h" |
#else |
# if SMC91111_LAN==1 |
# include "smc91111.h" |
# endif |
#endif |
|
#if 0 |
310,8 → 312,10
|
memcpy(p, (void *)pkt, len); |
eth_send(p, len); |
#else if SMC91111_LAN==1 |
#else |
# if SMC91111_LAN==1 |
eth_send(pkt, len); |
# endif |
#endif |
} |
|
/orpmon/services/tftp.c
10,8 → 10,6
#include "tftp.h" |
#include "bootp.h" |
|
//#undef ET_DEBUG |
#define ET_DEBUG |
|
#define WELL_KNOWN_PORT 69 /* Well known TFTP port # */ |
#define TIMEOUT 2 /* Seconds to timeout for a lost pkt */ |
161,7 → 159,7
int len = 0; |
|
#ifdef ET_DEBUG |
//printf("TftpSend: %d\n", TftpState); |
printf("TftpSend: %d\n", TftpState); |
#endif |
|
|
279,25 → 277,28
break; |
} |
} |
|
|
if (TftpBlock == TftpLastBlock) { |
/* |
* Same block again; ignore it. |
*/ |
break; |
/* |
* Same block again; resend ack (maybe got lost last time) |
*/ |
TftpSend (); |
break; |
} |
|
TftpLastBlock = TftpBlock; |
NetSetTimeout (TIMEOUT * TICKS_PER_SEC, TftpTimeout); |
|
store_block (TftpBlock - 1, pkt + 2, len); |
|
else |
{ |
TftpLastBlock = TftpBlock; |
NetSetTimeout (TIMEOUT * TICKS_PER_SEC, TftpTimeout); |
|
store_block (TftpBlock - 1, pkt + 2, len); |
} |
|
/* |
* Acknoledge the block just received, which will prompt |
* the server for the next one. |
*/ |
TftpSend (); |
|
|
if (len < 512) { |
/* |
* We received the whole thing. Try to |
/orpmon/cmds/load.c
3,7 → 3,7
#include "flash.h" |
#include "net.h" |
#include "uart.h" |
#include "spr_defs.h" |
#include "spr-defs.h" |
|
#ifndef MAX_IMAGES |
#define MAX_IMAGES 20 |
592,6 → 592,9
p1[i] = p2[i]; |
} |
|
// DC disable command in cpu.c |
extern int dc_disable_cmd(int argc, char *argv[]); |
|
int tboot_cmd (int argc, char *argv[]) |
{ |
int copied; |
612,8 → 615,14
break; |
} |
|
// global.src_addr = (unsigned long)0x0; |
|
// Disable data cache if present |
if (mfspr(SPR_SR) & SPR_SR_DCE) |
{ |
printf("Disabling data cache\n"); |
dc_disable_cmd(0, 0); |
} |
|
// Kick off copy |
copied =NetLoop(TFTP); |
if (copied <= 0) { |
printf("tboot: error while getting the image '%s'", tftp_filename); |
/orpmon/cmds/eth.c
2,7 → 2,7
#include "uart.h" |
#include "eth.h" |
#include "support.h" |
#include "spr_defs.h" |
#include "spr-defs.h" |
#include "net.h" |
|
#if 1 |
/orpmon/cmds/dhry.c
15,7 → 15,7
**************************************************************************** |
*/ |
#include "dhry.h" |
#include "spr_defs.h" |
#include "spr-defs.h" |
#include "common.h" |
#include "support.h" |
|
/orpmon/cmds/cpu.c
1,6 → 1,6
#include "common.h" |
#include "support.h" |
#include "spr_defs.h" |
#include "spr-defs.h" |
|
int ic_enable_cmd (int argc, char *argv[]) |
{ |
62,11 → 62,22
|
int dc_disable_cmd (int argc, char *argv[]) |
{ |
unsigned long sr; |
|
if (argc) return -1; |
|
unsigned long sr = mfspr(SPR_SR); |
|
// If it's enabled and write back is on, we'd better flush it first |
// (CWS=1 is write back) |
|
unsigned long dccfgr = mfspr(SPR_DCCFGR); |
int i; |
int bs= (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16; |
int ways = (1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3)); |
for(i=0;i<ways;i++) |
mtspr(SPR_DCBFR, i*bs); |
|
/* Disable DC */ |
asm("l.mfspr %0,r0,%1": "=r" (sr) : "i" (SPR_SR)); |
sr &= ~SPR_SR_DCE; |
asm("l.mtspr r0,%0,%1": : "r" (sr), "i" (SPR_SR)); |
asm("l.nop"); |
/orpmon/cmds/camera.c
1,6 → 1,6
#include "common.h" |
#include "support.h" |
#include "spr_defs.h" |
#include "spr-defs.h" |
|
/* Camera and CRT test. |
Draws gray cross across the screen, few color boxes at top left and moves around camera captured screen left/right |
/orpmon/cmds/memory.c
1,6 → 1,6
#include "common.h" |
#include "support.h" |
#include "spr_defs.h" |
#include "spr-defs.h" |
#include "spincursor.h" |
|
void show_mem (int start, int stop) |
/orpmon/sim.cfg
74,27 → 74,29
nmemories = <value> |
number of memory instances connected |
|
instance specific: |
baseaddr = <hex_value> |
memory start address |
baseaddr = <hex_value> |
memory start address |
|
size = <hex_value> |
memory size |
size = <hex_value> |
memory size |
|
name = "<string>" |
memory block name |
name = "<string>" |
memory block name |
|
ce = <value> |
chip enable index of the memory instance |
ce = <value> |
chip enable index of the memory instance |
|
delayr = <value> |
cycles, required for read access, -1 if instance does not support reading |
mc = <value> |
memory controller this memory is connected to |
|
delayw = <value> |
cycles, required for write access, -1 if instance does not support writing |
delayr = <value> |
cycles, required for read access, -1 if instance does not support reading |
|
log = "<filename>" |
filename, where to log memory accesses to, no log, if log command is not specified |
delayw = <value> |
cycles, required for write access, -1 if instance does not support writing |
|
log = "<filename>" |
filename, where to log memory accesses to, no log, if log command is not specified |
*/ |
|
|
104,34 → 106,43
pattern = 0x00 |
type = unknown /* Fastest */ |
|
name = "FLASH" |
ce = 0 |
mc = 0 |
baseaddr = 0xf0000000 |
size = 0x01000000 |
delayr = 1 |
delayw = -1 |
end |
|
nmemories = 3 |
device 0 |
name = "FLASH" |
ce = 0 |
baseaddr = 0xf0000000 |
size = 0x00800000 |
delayr = 10 |
delayw = -1 |
enddevice |
section memory |
/*random_seed = 12345 |
type = random*/ |
pattern = 0x00 |
type = unknown /* Fastest */ |
|
device 1 |
name = "RAM" |
ce = 1 |
baseaddr = 0x00000000 |
size = 0x00400000 |
delayr = 1 |
delayw = 2 |
enddevice |
name = "RAM" |
ce = 1 |
mc = 0 |
baseaddr = 0x00000000 |
size = 0x02000000 |
delayr = 1 |
delayw = 1 |
end |
|
device 2 |
name = "SRAM" |
ce = 2 |
baseaddr = 0x08000000 |
size = 0x00400000 |
delayr = 1 |
delayw = 2 |
enddevice |
section memory |
/*random_seed = 12345 |
type = random*/ |
pattern = 0x00 |
type = unknown /* Fastest */ |
|
name = "SRAM" |
mc = 0 |
ce = 2 |
baseaddr = 0xa4000000 |
size = 0x00100000 |
delayr = 1 |
delayw = 1 |
end |
|
|
246,12 → 257,12
*/ |
|
section ic |
enabled = 1 |
nsets = 256 |
enabled = 0 |
nsets = 512 |
nways = 1 |
blocksize = 16 |
hitdelay = 0 |
missdelay = 0 |
hitdelay = 20 |
missdelay = 20 |
end |
|
|
290,14 → 301,14
*/ |
|
section dc |
enabled = 1 |
nsets = 256 |
enabled = 0 |
nsets = 512 |
nways = 1 |
blocksize = 16 |
load_hitdelay = 0 |
load_missdelay = 0 |
store_hitdelay = 0 |
store_missdelay = 0 |
load_hitdelay = 20 |
load_missdelay = 20 |
store_hitdelay = 20 |
store_missdelay = 20 |
end |
|
|
361,36 → 372,18
filename for the exection log file. |
valid only if 'exe_log' is set |
|
spr_log = 0/1 |
'0': log reads/writes to/from sprs |
'1': don't log reads/write to/from sprs |
|
spr_log_fn = "<filename>" |
filename for the sprs log file. |
valid only if 'spr_log' is set |
|
clkcycle = <value>[ps|ns|us|ms] |
specifies time measurement for one cycle |
*/ |
|
section sim |
/* verbose = 1 */ |
verbose = 1 |
debug = 0 |
profile = 0 |
prof_fn = "sim.profile" |
|
history = 1 |
/* iprompt = 0 */ |
exe_log = 0 |
exe_log_type = software |
exe_log_start = 0 |
/* exe_log_end = 20000000*/ |
exe_log_marker = 10000 |
exe_log_fn = "executed.log" |
|
spr_log = 0 |
spr_log_fn = "spr.log" |
clkcycle = 100ns |
history = 0 |
/*exe_log = 1*/ |
/*exe_log_fn = "exe.log"*/ |
clkcycle = 10ns |
end |
|
|
441,7 → 434,9
|
sr = <value> |
sets the initial Supervision Register value |
|
supervisor mode (SM) and fixed one (FO) set = 0x8001 |
exception prefix high (EPH, vectors@0xf0000000) = 0x4000 |
together, (SM | FO | EPH) = 0xc001 |
superscalar = 0/1 |
'0': CPU is scalar |
'1': CPU is superscalar |
464,8 → 459,10
*/ |
|
section cpu |
ver = 0x1200 |
rev = 0x0001 |
ver = 0x12 |
cfg = 0x00 |
rev = 0x01 |
sr = 0x8001 /*SPR_SR_FO | SPR_SR_SM | SPR_SR_EPH */ |
/* upr = */ |
superscalar = 0 |
hazards = 0 |
546,11 → 543,12
vapi_id = <hex_value> |
Used to create "fake" vapi log file containing the JTAG proxy messages. |
*/ |
|
section debug |
enabled = 0 |
gdb_enabled = 0 |
server_port = 9999 |
/* gdb_enabled = 0 */ |
/* server_port = 9999*/ |
rsp_enabled = 1 |
rsp_port = 50001 |
end |
|
|
567,6 → 565,9
|
POC = <hex_value> |
Power On Configuration register |
|
index = <value> |
Index of this memory controller amongst all the memory controllers |
*/ |
|
section mc |
573,6 → 574,7
enabled = 0 |
baseaddr = 0x93000000 |
POC = 0x00000008 /* Power on configuration register */ |
index = 0 |
end |
|
|
637,7 → 639,9
enabled = 1 |
baseaddr = 0x90000000 |
irq = 2 |
channel = "file:uart0.rx,uart0.tx" |
/* channel = "file:uart0.rx,uart0.tx" */ |
/* channel = "tcp:10084" */ |
channel = "xterm:" |
jitter = -1 /* async behaviour */ |
16550 = 1 |
end |
706,12 → 710,13
*/ |
|
section ethernet |
enabled = 1 |
baseaddr = 0x92000000 |
dma = 0 |
/* dma = 0 */ |
irq = 4 |
rtx_type = 0 |
tx_channel = 0 |
rx_channel = 1 |
/* tx_channel = 0 */ |
/* rx_channel = 1 */ |
rxfile = "eth0.rx" |
txfile = "eth0.tx" |
sockif = "eth0" |
737,7 → 742,7
*/ |
|
section gpio |
enabled = 1 |
enabled = 0 |
baseaddr = 0x91000000 |
irq = 3 |
base_vapi_id = 0x0200 |
764,7 → 769,7
*/ |
|
section vga |
enabled = 1 |
enabled = 0 |
baseaddr = 0x97100000 |
irq = 8 |
refresh_rate = 100000 |
778,16 → 783,12
|
enabled = 0/1 |
whether tick timer is enabled |
*/ |
|
irq = <value> |
irq number |
*/ |
/* |
section tick |
section pic |
enabled = 1 |
irq = 0 |
edge_trigger = 1 |
end |
*/ |
|
/* FB SECTION |
|
810,7 → 811,7
*/ |
|
section fb |
enabled = 1 |
enabled = 0 |
baseaddr = 0x97000000 |
refresh_rate = 1000000 |
filename = "primary" |
829,7 → 830,7
*/ |
|
section kbd |
enabled = 1 |
enabled = 0 |
irq = 5 |
baseaddr = 0x94000000 |
rxfile = "kbd.rx" |
880,51 → 881,10
*/ |
|
section ata |
enabled = 1 |
enabled = 0 |
baseaddr = 0x9e000000 |
irq = 15 |
|
dev_type0 = 1 |
dev_file0 = "/tmp/sim_atadev0" |
dev_size0 = 1 |
dev_packet0 = 0 |
|
dev_type1 = 0 |
dev_file1 = "" |
dev_size1 = 0 |
dev_packet1 = 0 |
end |
|
|
/* CUC SECTION |
|
This section configures the OpenRISC Custom Unit Compiler |
|
memory_order = none/weak/strong/exact |
none different memory ordering, even if there are dependencies, |
burst can be made, width can change |
weak different memory ordering, if there cannot be dependencies |
burst can be made, width can change |
strong same memory ordering, burst can be made, width can change |
exact exacltly the same memory ordering and widths |
|
calling_convention = 0/1 |
whether programs follow OpenRISC calling conventions |
|
enable_bursts = 0/1 |
whether burst are detected |
|
no_multicycle = 0/1 |
if selected no multicycle logic paths will be generated |
|
timings_fn = "<filename>" |
*/ |
|
section cuc |
memory_order = weak |
calling_convention = 1 |
enable_bursts = 1 |
no_multicycle = 1 |
timings_fn = "virtex.tim" |
end |
|
/orpmon/common/spincursor.c
1,10 → 1,10
#include "uart.h" |
#include "board.h" |
#include "support.h" |
|
int spin_cursor_enabled = 0; |
static int last_spin_char = 0; |
static int last_spin_ticks = 0; |
|
|
void enable_spincursor(void) |
{ |
spin_cursor_enabled = 1; |
19,10 → 19,15
|
void spincursor(void) |
{ |
static int last_spin_char = 0; |
static int last_spin_ticks = 0; |
|
if (!spin_cursor_enabled) |
return; |
|
if ((get_timer(0) - last_spin_ticks) < (TICKS_PER_US*2000)) |
return; |
|
// Put a backspace |
uart_putc(0x8); |
if (last_spin_char == 0) |
/orpmon/common/common.c
3,7 → 3,8
#include "screen.h" |
#include "support.h" |
#include "keyboard.h" |
#include "spr_defs.h" |
#include "spr-defs.h" |
#include "spincursor.h" |
#include "int.h" |
|
#include "build.h" |
10,6 → 11,7
|
#define MAX_COMMANDS 100 |
|
// Value from linker script |
extern unsigned long src_addr; |
|
bd_t bd; |
92,6 → 94,53
return 0; |
} |
|
void |
print_or1k_cache_info() |
{ |
// Read out UPR, check what modules we have |
unsigned long upr = mfspr(SPR_UPR); |
printf("Instruction cache:\t"); |
if (upr & SPR_UPR_ICP) |
{ |
// We have instruction cache, read out ICCFGR |
|
unsigned long iccfgr = mfspr(SPR_ICCFGR); |
unsigned int cbs; // cache block size |
unsigned long ncs = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3); |
if (iccfgr & SPR_ICCFGR_CBS) |
cbs = 32; |
else |
cbs = 16; |
|
printf("%dkB (BS: %d Sets: %d)\n", |
(cbs * ncs)/1024, cbs, ncs); |
|
} |
else |
printf(" not present\n"); |
|
printf("Data cache:\t\t"); |
if (upr & SPR_UPR_DCP) |
{ |
// We have instruction cache, read out DCCFGR |
|
unsigned long iccfgr = mfspr(SPR_DCCFGR); |
unsigned int cbs; // cache block size |
unsigned long ncs = 1 << ((iccfgr & SPR_DCCFGR_NCS) >> 3); |
if (iccfgr & SPR_DCCFGR_CBS) |
cbs = 32; |
else |
cbs = 16; |
|
printf("%dkB (BS: %d Sets: %d)\n", |
(cbs * ncs)/1024, cbs, ncs); |
|
} |
else |
printf(" not present\n"); |
|
} |
|
unsigned long parse_ip (char *ip) |
{ |
unsigned long num; |
159,27 → 208,39
char *command_str; |
char *argv[20]; |
int argc = 0; |
int chcnt = 0; |
|
/* Show prompt */ |
#ifdef XESS |
printf ("\norp-xsv> "); |
#else |
printf ("\n" BOARD_DEF_NAME"> "); |
#endif |
|
/* Get characters from UART */ |
c = getc(); |
while (c != '\r' && c != '\f' && c != '\n') |
{ |
if (c == '\b') |
pstr--; |
else |
*pstr++ = c; |
putc(c); |
c = getc(); |
} |
*pstr = '\0'; |
printf ("\n"); |
while(1) |
{ |
c=getc(); |
if (c == '\r' || c == '\f' || c == '\n') |
{ |
// Mark end of string |
*pstr = '\0'; |
putc('\n'); |
break; |
} |
else if (c == '\b') // Backspace |
{ |
if (chcnt > 0) |
{ |
putc(c); |
putc(' '); // cover char with space |
putc(c); |
pstr--; |
chcnt--; |
} |
} |
else |
{ |
putc(c); |
*pstr++ = c; |
chcnt++; |
} |
} |
|
/* Skip leading blanks */ |
pstr = str; |
209,7 → 270,8
switch ( command[i].func(argc, &argv[0]) ) |
{ |
case -1: |
printf ("Missing/wrong parameters, usage: %s %s\n", command[i].name, command[i].params); |
printf ("Missing/wrong parameters, usage: %s %s\n", |
command[i].name, command[i].params); |
break; |
} |
|
228,7 → 290,7
} |
|
#if HELP_ENABLED |
extern unsigned long src_addr; // Stack section ends here |
extern unsigned long src_addr; // Stack section ends here, will print it out |
/* Displays help screen */ |
int help_cmd (int argc, char *argv[]) |
{ |
237,14 → 299,11
printf ("%-10s %-20s - %s\n", command[i].name, command[i].params, command[i].help); |
|
// Build info.... |
printf("Info: CPU@ %dMHz", IN_CLK/1000000); |
#if IC_ENABLE==1 |
printf(" IC=%dB",IC_SIZE); |
#endif |
#if DC_ENABLE==1 |
printf(" DC=%dB",DC_SIZE); |
#endif |
printf("\n"); |
printf("CPU info\n"); |
printf("Frequency\t\t%dMHz\n", IN_CLK/1000000); |
print_or1k_cache_info(); |
printf("\n"); |
printf("Info: Stack section addr 0x%x\n",(unsigned long) &src_addr); |
printf("Build tag: %s", BUILD_VERSION); |
|
322,7 → 381,8
module_hdbug_init (); |
#endif |
|
tick_init(); |
#ifdef TICK_CMDS |
#endif |
|
} |
int tboot_cmd (int argc, char *argv[]); |
330,13 → 390,17
int main(int argc, char **argv) |
{ |
extern unsigned long calc_mycrc32 (void); |
|
#if 0 |
extern unsigned long mycrc32, mysize; |
#endif |
|
timestamp = 0; // clear timer counter |
|
int_init (); |
|
change_console_type (CONSOLE_TYPE); |
|
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE); |
|
#if SELF_CHECK |
346,18 → 410,24
else |
printf ("OK\n"); |
#endif /* SELF_CHECK */ |
|
num_commands=0; |
mon_init (); |
|
disable_spincursor(); |
|
tick_init(); |
|
|
if (HELP_ENABLED) register_command ("help", "", "shows this help", help_cmd); |
|
#ifdef XESS |
printf ("\nORP-XSV Monitor (type 'help' for help)\n"); |
#else |
printf ("\n" BOARD_DEF_NAME " monitor (type 'help' for help)\n"); |
printf("\tbuild: %s", BUILD_VERSION); |
#endif |
|
while(1) mon_command(); |
// Run tboot in sim for now: tboot_cmd (0,0); |
// Loop forever, accepting commands |
while(1) |
{ |
mon_command(); |
} |
|
} |
/orpmon/common/support.c
1,6 → 1,6
/* Support */ |
|
#include "spr_defs.h" |
#include "spr-defs.h" |
#include "support.h" |
#include "common.h" |
#include "int.h" |
/orpmon/flash.ld
73,6 → 73,6
_fprog_addr = .; |
*(.mytext) |
. += 0x500; |
_src_addr = .; |
src_addr = .; |
} > ram |
} |
/orpmon/config.mk
5,13 → 5,8
else echo sh; fi ; fi) |
|
HOSTCC = cc |
#HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer |
HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fno-omit-frame-pointer -g |
HOSTCFLAGS = -Wall -Wstrict-prototypes -fno-omit-frame-pointer |
|
# |
# Specify the path to the tool chain |
# |
TOOL_PREFIX = /tools/or32-uclinux |
|
######################################################################### |
|
29,9 → 24,10
RANLIB = $(CROSS_COMPILE)ranlib |
|
CFLAGS += -I$(TOPDIR)/include -DOR1K -Wall -Wstrict-prototypes |
CFLAGS += -Werror-implicit-function-declaration -fno-omit-frame-pointer |
CFLAGS += -Werror-implicit-function-declaration |
#CFLAGS += -fno-omit-frame-pointer |
CFLAGS += -fno-strength-reduce -O2 -g -pipe -fno-builtin |
#CFLAGS += -msoft-mul -msoft-div -nostdlib |
CFLAGS += -mhard-mul -mhard-div -msoft-float -nostdlib |
CFLAGS += -nostdlib |
#CFLAGS += -DDEBUG |
|
/orpmon/ram.ld
1,11 → 1,16
|
/* Seen 3 bad pages, 180-182 (0xb400-0xb6ff), so put text after these pages */ |
|
MEMORY |
{ |
vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000 |
/*ram : ORIGIN = 0x00002000, LENGTH = 0x02000000 - 0x00002000*/ |
ram : ORIGIN = 0x00002000, LENGTH = 0x02000000 - 0x00002000 |
|
/* Uncomment the following to work around bad pages in a flash mem */ |
/* |
ram : ORIGIN = 0x00001200, LENGTH = 0xB400 - 0x1200 |
ram2 : ORIGIN = 0xb700, LENGTH = 0x02000000 - 0xb700 |
*/ |
/*flash : ORIGIN = 0xf0000000, LENGTH = 0x04000000*/ |
} |
|
24,7 → 29,7
_text_begin = .; |
*(.text) |
_text_end = .; |
} > ram2 |
} > ram |
|
.data : |
/* AT ( ADDR (.text) + SIZEOF(.text) + SIZEOF(.mytext))*/ |
46,8 → 51,8
.stack : |
{ |
*(.stack) |
_src_addr = .; |
} > ram2 |
src_addr = .; |
} > ram |
/* |
.monitor : |
{ |
/orpmon/drivers/eth.c
6,7 → 6,7
#include "uart.h" |
#include "eth.h" |
#include "int.h" |
#include "spr_defs.h" |
#include "spr-defs.h" |
|
//#define PRINT_PACKETS |
//#define ETHPHY_10MBPS |
332,6 → 332,7
void eth_send (void *buf, unsigned long len) |
{ |
eth_bd *bd; |
int i; |
|
#ifdef PRINT_PACKETS |
printf("transmitted packet:\t"); |
341,6 → 342,7
bd = (eth_bd *)ETH_BD_BASE; |
|
bd[tx_last].addr = (unsigned long)buf; |
|
retry_eth_send: |
bd[tx_last].len_status &= 0x0000ffff & ~ETH_TX_BD_STATS; |
if (eth_monitor_enabled) // enable IRQ when sending |
369,6 → 371,7
{ |
eth_bd *bd; |
unsigned long len = 0; |
int i; |
|
bd = (eth_bd *)ETH_BD_BASE + ETH_TXBD_NUM; |
|
378,7 → 381,7
|
if(bd[rx_next].len_status & ETH_RX_BD_EMPTY) |
return len; |
|
|
if(bd[rx_next].len_status & ETH_RX_BD_OVERRUN) { |
printf("eth rx: ETH_RX_BD_OVERRUN\n"); |
bad = 1; |
413,6 → 416,7
printf("received packet:\t"); |
print_packet(bd[rx_next].addr, bd[rx_next].len_status >> 16); |
#endif |
|
receive((void *)bd[rx_next].addr, bd[rx_next].len_status >> 16); |
len += bd[rx_next].len_status >> 16; |
} |
/orpmon/drivers/int.c
3,7 → 3,7
|
#include "common.h" |
#include "support.h" |
#include "spr_defs.h" |
#include "spr-defs.h" |
#include "int.h" |
|
#ifdef OR1K |
/orpmon/drivers/tick.c
1,7 → 1,7
|
#include "common.h" |
#include "support.h" |
#include "spr_defs.h" |
#include "spr-defs.h" |
#include "spincursor.h" |
|
void tick_init(void) |
/orpmon/drivers/uart.c
31,7 → 31,7
{ |
int divisor; |
float float_divisor; |
|
|
/* Reset receiver and transmiter */ |
REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_4; |
|