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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/gnu-old/binutils-2.18.50/gas/testsuite/gas/ppc
    from Rev 156 to Rev 816
    ↔ Reverse comparison
  •

Rev 156 → Rev 816

/booke_xcoff64.d
0,0 → 1,125
#as: -a64 -mppc64 -mbooke64
#objdump: -dr -Mbooke64
#name: xcoff64 BookE tests
 
.*: file format aix5?coff64-rs6000
 
Disassembly of section .text:
 
0000000000000000 <.text>:
0: 7c 22 3f 64 tlbre r1,r2,7
4: 7c be 1f a4 tlbwe r5,r30,3
8: 24 25 00 30 bce 1,4\*cr1\+gt,38 <.text\+0x38>
c: 24 46 00 3d bcel 2,4\*cr1\+eq,48 <.text\+0x48>
10: 24 67 00 5a bcea 3,4\*cr1\+so,58 <.text\+0x58>
12: R_BA_16 .text
14: 24 88 00 7b bcela 4,4\*cr2\+lt,78 <.text\+0x78>
16: R_BA_16 .text
18: 4c a9 00 22 bclre 5,4\*cr2\+gt
1c: 4c aa 00 23 bclrel 5,4\*cr2\+eq
20: 4d 0b 04 22 bcctre 8,4\*cr2\+so
24: 4d 0c 04 23 bcctrel 8,4\*cr3\+lt
28: 58 00 00 74 be 9c <.text\+0x9c>
2c: 58 00 00 89 bel b4 <.text\+0xb4>
30: 58 00 00 f2 bea f0 <.text\+0xf0>
30: R_BA_26 .text
34: 58 00 01 27 bela 124 <.text\+0x124>
34: R_BA_26 .text
38: e9 09 00 80 lbze r8,8\(r9\)
3c: e9 8f 00 41 lbzue r12,4\(r15\)
40: 7c 86 40 fe lbzuxe r4,r6,r8
44: 7c 65 38 be lbzxe r3,r5,r7
48: f8 a6 06 40 lde r5,400\(r6\)
4c: f8 c7 07 11 ldue r6,452\(r7\)
50: 7c e8 4e 3e ldxe r7,r8,r9
54: 7d 4b 66 7e lduxe r10,r11,r12
58: f9 81 02 06 lfde f12,128\(r1\)
5c: f8 25 00 47 lfdue f1,16\(r5\)
60: 7c a1 1c be lfdxe f5,r1,r3
64: 7c c2 24 fe lfduxe f6,r2,r4
68: f9 09 00 c4 lfse f8,48\(r9\)
6c: f9 2a 01 15 lfsue f9,68\(r10\)
70: 7d 44 44 7e lfsuxe f10,r4,r8
74: 7d 23 3c 3e lfsxe f9,r3,r7
78: e9 45 03 24 lhae r10,50\(r5\)
7c: e8 23 00 55 lhaue r1,5\(r3\)
80: 7c a1 1a fe lhauxe r5,r1,r3
84: 7f be fa be lhaxe r29,r30,r31
88: 7c 22 1e 3c lhbrxe r1,r2,r3
8c: e8 83 01 22 lhze r4,18\(r3\)
90: e8 c9 01 43 lhzue r6,20\(r9\)
94: 7c a7 4a 7e lhzuxe r5,r7,r9
98: 7d 27 2a 3e lhzxe r9,r7,r5
9c: 7d 4f a0 fc lwarxe r10,r15,r20
a0: 7c aa 94 3c lwbrxe r5,r10,r18
a4: eb 9d 00 46 lwze r28,4\(r29\)
a8: e9 0a 02 87 lwzue r8,40\(r10\)
ac: 7c 66 48 7e lwzuxe r3,r6,r9
b0: 7f dd e0 3e lwzxe r30,r29,r28
b4: 7c 06 3d fc dcbae r6,r7
b8: 7c 08 48 bc dcbfe r8,r9
bc: 7c 0a 5b bc dcbie r10,r11
c0: 7c 08 f0 7c dcbste r8,r30
c4: 7c c3 0a 3c dcbte 6,r3,r1
c8: 7c a4 11 fa dcbtste 5,r4,r2
cc: 7c 0f 77 fc dcbze r15,r14
d0: 7c 03 27 bc icbie r3,r4
d4: 7c a8 48 2c icbt 5,r8,r9
d8: 7c ca 78 3c icbte 6,r10,r15
dc: 7c a6 02 26 mfapidi r5,r6
e0: 7c 07 46 24 tlbivax r7,r8
e4: 7c 09 56 26 tlbivaxe r9,r10
e8: 7c 0b 67 24 tlbsx r11,r12
ec: 7c 0d 77 26 tlbsxe r13,r14
f0: 7c 22 1b 14 adde64 r1,r2,r3
f4: 7c 85 37 14 adde64o r4,r5,r6
f8: 7c e8 03 d4 addme64 r7,r8
fc: 7d 2a 07 d4 addme64o r9,r10
100: 7d 6c 03 94 addze64 r11,r12
104: 7d ae 07 94 addze64o r13,r14
108: 7e 80 04 40 mcrxr64 cr5
10c: 7d f0 8b 10 subfe64 r15,r16,r17
110: 7e 53 a7 10 subfe64o r18,r19,r20
114: 7e b6 03 d0 subfme64 r21,r22
118: 7e f8 07 d0 subfme64o r23,r24
11c: 7f 3a 03 90 subfze64 r25,r26
120: 7f 7c 07 90 subfze64o r27,r28
124: e8 22 03 28 stbe r1,50\(r2\)
128: e8 64 02 89 stbue r3,40\(r4\)
12c: 7c a6 39 fe stbuxe r5,r6,r7
130: 7d 09 51 be stbxe r8,r9,r10
134: 7d 6c 6b ff stdcxe. r11,r12,r13
138: f9 cf 00 78 stde r14,28\(r15\)
13c: fa 11 00 59 stdue r16,20\(r17\)
140: 7e 53 a7 3e stdxe r18,r19,r20
144: 7e b6 bf 7e stduxe r21,r22,r23
148: f8 38 00 3e stfde f1,12\(r24\)
14c: f8 59 00 0f stfdue f2,0\(r25\)
150: 7c 7a dd be stfdxe f3,r26,r27
154: 7c 9c ed fe stfduxe f4,r28,r29
158: 7c be ff be stfiwxe f5,r30,r31
15c: f8 de 00 6c stfse f6,24\(r30\)
160: f8 fd 00 5d stfsue f7,20\(r29\)
164: 7d 1c dd 3e stfsxe f8,r28,r27
168: 7d 3a cd 7e stfsuxe f9,r26,r25
16c: 7f 17 b7 3c sthbrxe r24,r23,r22
170: ea b4 01 ea sthe r21,30\(r20\)
174: ea 72 02 8b sthue r19,40\(r18\)
178: 7e 30 7b 7e sthuxe r17,r16,r15
17c: 7d cd 63 3e sthxe r14,r13,r12
180: 7d 6a 4d 3c stwbrxe r11,r10,r9
184: 7d 07 31 3d stwcxe. r8,r7,r6
188: e8 a4 03 2e stwe r5,50\(r4\)
18c: e8 62 02 8f stwue r3,40\(r2\)
190: 7c 22 19 7e stwuxe r1,r2,r3
194: 7c 85 31 3e stwxe r4,r5,r6
198: 4c 00 00 66 rfci
19c: 7c 60 01 06 wrtee r3
1a0: 7c 00 81 46 wrteei 1
1a4: 7c 85 02 06 mfdcrx r4,r5
1a8: 7c aa 3a 86 mfdcr r5,234
1ac: 7c e6 03 06 mtdcrx r6,r7
1b0: 7d 10 6b 86 mtdcr 432,r8
1b4: 7c 00 04 ac msync
1b8: 7c 09 55 ec dcba r9,r10
1bc: 7c 00 06 ac mbar
/altivec_and_spe.s
0,0 → 1,4
.text
dssall
mtspefscr 8
rfid
/textalign-xcoff-001.d
0,0 → 1,14
#objdump: -h
#source: textalign-xcoff-001.s
#as:
 
.*: file format aixcoff-rs6000
 
Sections:
Idx Name Size VMA LMA File off Algn
0 \.text 00000004 0+0 0+0 000000a8 2\*\*2
CONTENTS, ALLOC, LOAD, CODE
1 \.data 00000008 0+04 0+04 000000ac 2\*\*3
CONTENTS, ALLOC, LOAD, RELOC, DATA
2 \.bss 00000000 0+0c 0+0c 00000000 2\*\*3
ALLOC
/regnames.d
0,0 → 1,8
#as: -mregnames
#objdump: -s -j .text
#name: PowerPC symbolic regnames
 
.*
 
Contents of section \.text:
0000 4fbdcb82 88850004 .*
/textalign-xcoff-002.d
0,0 → 1,14
#objdump: -h
#source: textalign-xcoff-001.s
#as: -mppc64 -a64
 
.*: file format .*coff64-rs6000
 
Sections:
Idx Name Size VMA LMA File off Algn
0 \.text 00000004 0000000000000000 0000000000000000 000000f0 2\*\*2
CONTENTS, ALLOC, LOAD, CODE
1 \.data 00000008 0000000000000004 0000000000000004 000000f4 2\*\*3
CONTENTS, ALLOC, LOAD, RELOC, DATA
2 \.bss 00000000 000000000000000c 000000000000000c 00000000 2\*\*3
ALLOC
/machine.d
0,0 → 1,9
#objdump: -s -j .text
#name: PowerPC .machine test
 
.*
 
Contents of section \.text:
0000 7c11eba6 7c100ba6 4c000066 00000200 .*
0010 44000002 4c0000a4 7c000224 4e800020 .*
0020 7c11eba6 .*
/altivec.s
0,0 → 1,10
# PowerPC AltiVec tests
#as: -m601 -maltivec
.section ".text"
start:
dss 3
dssall
dst 5,4,1
dstt 8,7,0
dstst 5,6,3
dststt 4,5,2
/align.s
0,0 → 1,6
.comm default_align_4,16
.comm align_1,32,1
.comm align_2,64,2
.comm align_4,128,3
.comm align_8,256,4
 
/test1xcoff32.s
0,0 → 1,82
 
 
 
 
.csect [RW]
dsym0: .long 0xdeadbeef
dsym1:
 
.toc
.L_tsym0:
.tc ignored0[TC],dsym0
.L_tsym1:
.tc ignored1[TC],dsym1
.L_tsym2:
.tc ignored2[TC],usym0
.L_tsym3:
.tc ignored3[TC],usym1
.L_tsym4:
.tc ignored4[TC],esym0
.L_tsym5:
.tc ignored5[TC],esym1
.L_tsym6:
.tc ignored6[TC],.text
 
.csect .crazy_table[RO]
xdsym0: .long 0xbeefed
xdsym1:
.csect [PR]
.lglobl reference_csect_relative_symbols
reference_csect_relative_symbols:
lwz 3,xdsym0(3)
lwz 3,xdsym1(3)
lwz 3,xusym0(3)
lwz 3,xusym1(3)
 
.lglobl dubious_references_to_default_RW_csect
dubious_references_to_default_RW_csect:
lwz 3,dsym0(3)
lwz 3,dsym1(3)
lwz 3,usym0(3)
lwz 3,usym1(3)
 
.lglobl reference_via_toc
reference_via_toc:
lwz 3,.L_tsym0(2)
lwz 3,.L_tsym1(2)
lwz 3,.L_tsym2(2)
lwz 3,.L_tsym3(2)
lwz 3,.L_tsym4(2)
lwz 3,.L_tsym5(2)
 
.lglobl subtract_symbols
subtract_symbols:
li 3,dsym1-dsym0
li 3,dsym0-dsym1
li 3,usym1-usym0
li 3,usym0-usym1
li 3,dsym0-usym0
li 3,usym0-dsym0
lwz 3,dsym1-dsym0(4)
 
.lglobl load_addresses
load_addresses:
la 3,xdsym0(0)
la 3,xusym0(0)
 
la 3,.L_tsym6(2)
 
.csect [RW]
usym0: .long 0xcafebabe
usym1: .long 0xbaad
.csect .crazy_table[RO]
xusym0: .long 0xbeefed
xusym1:
/test1elf32.s
0,0 → 1,58
 
 
 
 
.section ".data"
dsym0: .long 0xdeadbeef
dsym1:
 
 
 
.section ".text"
lwz 3,dsym0@l(3)
lwz 3,dsym1@l(3)
lwz 3,usym0@l(3)
lwz 3,usym1@l(3)
lwz 3,esym0@l(3)
lwz 3,esym1@l(3)
 
 
 
li 3,dsym1-dsym0
li 3,dsym0-dsym1
li 3,usym1-usym0
li 3,usym0-usym1
li 3,dsym0-usym0
li 3,usym0-dsym0
 
li 3,dsym0@l
li 3,dsym0@h
li 3,dsym0@ha
 
 
li 3,usym0-usym1@l
li 3,usym0-usym1@h
li 3,usym0-usym1@ha
 
 
lwz 3,dsym1-dsym0@l(4)
 
lwz 3,.text@l(0)
 
.section ".data"
usym0: .long 0xcafebabe
usym1:
 
datpt: .long jk-.+10000000
dat0: .long jk-dat1
dat1: .long jk-dat1
dat2: .long jk-dat1
 
/booke_xcoff64.s
0,0 → 1,136
# Motorola PowerPC BookE tests
#as: -a64 -mppc64 -mbooke64
.csect .text[PR]
.csect main[DS]
main:
.csect .text[PR]
.main:
tlbre 1, 2, 7
tlbwe 5, 30, 3
bce 1, 5, branch_target_1
bcel 2, 6, branch_target_2
bcea 3, 7, branch_target_3
bcela 4, 8, branch_target_4
bclre 5, 9
bclrel 5, 10
bcctre 8, 11
bcctrel 8, 12
be branch_target_5
bel branch_target_6
bea branch_target_7
bela branch_target_8
 
branch_target_1:
lbze 8, 8(9)
lbzue 12, 4(15)
lbzuxe 4, 6, 8
lbzxe 3, 5, 7
 
branch_target_2:
lde 5, 400(6)
ldue 6, 452(7)
ldxe 7, 8, 9
lduxe 10, 11, 12
 
branch_target_3:
lfde 12, 128(1)
lfdue 1, 16(5)
lfdxe 5, 1, 3
lfduxe 6, 2, 4
lfse 8, 48(9)
lfsue 9, 68(10)
lfsuxe 10, 4, 8
lfsxe 9, 3, 7
 
branch_target_4:
lhae 10, 50(5)
lhaue 1, 5(3)
lhauxe 5, 1, 3
lhaxe 29, 30, 31
lhbrxe 1, 2, 3
lhze 4, 18(3)
lhzue 6, 20(9)
lhzuxe 5, 7, 9
lhzxe 9, 7, 5
 
branch_target_5:
lwarxe 10, 15, 20
lwbrxe 5, 10, 18
lwze 28, 4(29)
lwzue 8, 40(10)
lwzuxe 3, 6, 9
lwzxe 30, 29, 28
 
branch_target_6:
dcbae 6, 7
dcbfe 8, 9
dcbie 10, 11
dcbste 8, 30
dcbte 6, 3, 1
dcbtste 5, 4, 2
dcbze 15, 14
icbie 3, 4
icbt 5, 8, 9
icbte 6, 10, 15
mfapidi 5, 6
tlbivax 7, 8
tlbivaxe 9, 10
tlbsx 11, 12
tlbsxe 13, 14
 
branch_target_7:
adde64 1, 2, 3
adde64o 4, 5, 6
addme64 7, 8
addme64o 9, 10
addze64 11, 12
addze64o 13, 14
mcrxr64 5
subfe64 15, 16, 17
subfe64o 18, 19, 20
subfme64 21, 22
subfme64o 23, 24
subfze64 25, 26
subfze64o 27, 28
 
branch_target_8:
stbe 1, 50(2)
stbue 3, 40(4)
stbuxe 5, 6, 7
stbxe 8, 9, 10
stdcxe. 11, 12, 13
stde 14, 28(15)
stdue 16, 20(17)
stdxe 18, 19, 20
stduxe 21, 22, 23
stfde 1, 12(24)
stfdue 2, 0(25)
stfdxe 3, 26, 27
stfduxe 4, 28, 29
stfiwxe 5, 30, 31
stfse 6, 24(30)
stfsue 7, 20(29)
stfsxe 8, 28, 27
stfsuxe 9, 26, 25
sthbrxe 24, 23, 22
sthe 21, 30(20)
sthue 19, 40(18)
sthuxe 17, 16, 15
sthxe 14, 13, 12
stwbrxe 11, 10, 9
stwcxe. 8, 7, 6
stwe 5, 50(4)
stwue 3, 40(2)
stwuxe 1, 2, 3
stwxe 4, 5, 6
 
rfci
wrtee 3
wrteei 1
mfdcrx 4, 5
mfdcr 5, 234
mtdcrx 6, 7
mtdcr 432, 8
msync
dcba 9, 10
mbar 0
/astest64.d
0,0 → 1,75
#objdump: -Dr
#name: PowerPC 64-bit test 1
 
.*: +file format elf64-powerpc
 
Disassembly of section \.text:
 
0000000000000000 <foo>:
0: 60 00 00 00 nop
4: 60 00 00 00 nop
8: 60 00 00 00 nop
 
000000000000000c <a>:
c: 48 00 00 04 b 10 <apfour>
 
0000000000000010 <apfour>:
10: 48 00 00 08 b 18 <apfour\+0x8>
14: 48 00 00 00 b 14 <apfour\+0x4>
14: R_PPC64_REL24 x
18: 48 00 00 04 b 1c <apfour\+0xc>
18: R_PPC64_REL24 \.data\+0x4
1c: 48 00 00 00 b 1c <apfour\+0xc>
1c: R_PPC64_REL24 z
20: 48 00 00 14 b 34 <apfour\+0x24>
20: R_PPC64_REL24 z\+0x14
24: 48 00 00 04 b 28 <apfour\+0x18>
28: 48 00 00 00 b 28 <apfour\+0x18>
28: R_PPC64_REL24 a
2c: 4b ff ff e4 b 10 <apfour>
30: 48 00 00 04 b 34 <apfour\+0x24>
30: R_PPC64_REL24 a\+0x4
34: 4b ff ff e0 b 14 <apfour\+0x4>
38: 00 00 00 38 \.long 0x38
38: R_PPC64_ADDR32 \.text\+0x38
3c: 00 00 00 44 \.long 0x44
3c: R_PPC64_ADDR32 \.text\+0x44
40: 00 00 00 00 \.long 0x0
40: R_PPC64_REL32 x
44: 00 00 00 04 \.long 0x4
44: R_PPC64_REL32 x\+0x4
48: 00 00 00 00 \.long 0x0
48: R_PPC64_REL32 z
4c: 00 00 00 04 \.long 0x4
4c: R_PPC64_REL32 \.data\+0x4
50: 00 00 00 00 \.long 0x0
50: R_PPC64_ADDR32 x
54: 00 00 00 04 \.long 0x4
54: R_PPC64_ADDR32 \.data\+0x4
58: 00 00 00 00 \.long 0x0
58: R_PPC64_ADDR32 z
5c: ff ff ff fc fnmsub f31,f31,f31,f31
5c: R_PPC64_ADDR32 x\+0xfffffffffffffffc
60: 00 00 00 00 \.long 0x0
60: R_PPC64_ADDR32 \.data
64: ff ff ff fc fnmsub f31,f31,f31,f31
64: R_PPC64_ADDR32 z\+0xfffffffffffffffc
68: ff ff ff a4 \.long 0xffffffa4
6c: ff ff ff a4 \.long 0xffffffa4
70: 00 00 00 00 \.long 0x0
70: R_PPC64_ADDR32 a
74: 00 00 00 10 \.long 0x10
74: R_PPC64_ADDR32 \.text\+0x10
78: 00 00 00 10 \.long 0x10
78: R_PPC64_ADDR32 \.text\+0x10
7c: ff ff ff fc fnmsub f31,f31,f31,f31
80: 00 00 00 12 \.long 0x12
80: R_PPC64_ADDR32 \.text\+0x12
84: 00 00 00 00 \.long 0x0
Disassembly of section \.data:
 
0000000000000000 <x>:
0: 00 00 00 00 \.long 0x0
 
0000000000000004 <y>:
4: 00 00 00 00 \.long 0x0
/range64.l
0,0 → 1,6
.*: Assembler messages:
.*:3: Error: operand out of domain \(-1 is not a multiple of 4\)
.*:4: Error: operand out of domain \(2 is not a multiple of 4\)
.*:5: Error: operand out of range.*
.*:6: Error: operand out of range.*
.*:7: Error: operand out of range.*
/cell.d
0,0 → 1,31
#as: -mcell
#objdump: -dr -Mcell
#name: Cell tests
 
 
.*: +file format elf(32)?(64)?-powerpc.*
 
 
Disassembly of section \.text:
 
0000000000000000 <.text>:
0: 7c 01 14 0e lvlx v0,r1,r2
4: 7c 00 14 0e lvlx v0,0,r2
8: 7c 01 16 0e lvlxl v0,r1,r2
c: 7c 00 16 0e lvlxl v0,0,r2
10: 7c 01 14 4e lvrx v0,r1,r2
14: 7c 00 14 4e lvrx v0,0,r2
18: 7c 01 16 4e lvrxl v0,r1,r2
1c: 7c 00 16 4e lvrxl v0,0,r2
20: 7c 01 15 0e stvlx v0,r1,r2
24: 7c 00 15 0e stvlx v0,0,r2
28: 7c 01 17 0e stvlxl v0,r1,r2
2c: 7c 00 17 0e stvlxl v0,0,r2
30: 7c 01 15 4e stvrx v0,r1,r2
34: 7c 00 15 4e stvrx v0,0,r2
38: 7c 01 17 4e stvrxl v0,r1,r2
3c: 7c 00 17 4e stvrxl v0,0,r2
40: 7c 00 0c 28 ldbrx r0,0,r1
44: 7c 01 14 28 ldbrx r0,r1,r2
48: 7c 00 0d 28 stdbrx r0,0,r1
4c: 7c 01 15 28 stdbrx r0,r1,r2
/textalign-xcoff-001.s
0,0 → 1,11
.globl __start
.globl .__start
 
__start:
.csect .data[DS]
.long .__start
 
.csect .text[pr]
.__start:
nop
/regnames.s
0,0 → 1,3
.text
cror 4*%cr7+gt,%cr7*4+gt,4*%cr6+gt
lbz r4,4(r5)
/power4.d
0,0 → 1,104
#objdump: -drx -Mpower4
#as: -mpower4
#name: Power4 instructions
 
.*: +file format elf64-powerpc
.*
architecture: powerpc:common64, flags 0x0+11:
HAS_RELOC, HAS_SYMS
start address 0x0+
 
Sections:
Idx Name +Size +VMA +LMA +File off +Algn
+0 \.text +0+c4 +0+ +0+ +.*
+CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+1 \.data +0+10 +0+ +0+ +.*
+CONTENTS, ALLOC, LOAD, DATA
+2 \.bss +0+ +0+ +0+ +.*
+ALLOC
+3 \.toc +0+30 +0+ +0+ +.*
+CONTENTS, ALLOC, LOAD, RELOC, DATA
SYMBOL TABLE:
0+ l +d +\.text 0+ (|\.text)
0+ l +d +\.data 0+ (|\.data)
0+ l +d +\.bss 0+ (|\.bss)
0+ l +\.data 0+ dsym0
0+8 l +\.data 0+ dsym1
0+ l +d +\.toc 0+ (|\.toc)
0+8 l +\.data 0+ usym0
0+10 l +\.data 0+ usym1
0+ +\*UND\* 0+ esym0
0+ +\*UND\* 0+ esym1
 
 
Disassembly of section \.text:
 
0+ <\.text>:
+0: e0 83 00 00 lq r4,0\(r3\)
2: R_PPC64_ADDR16_LO_DS \.data
+4: e0 83 00 00 lq r4,0\(r3\)
6: R_PPC64_ADDR16_LO_DS \.data\+0x8
+8: e0 83 00 00 lq r4,0\(r3\)
a: R_PPC64_ADDR16_LO_DS \.data\+0x8
+c: e0 83 00 10 lq r4,16\(r3\)
e: R_PPC64_ADDR16_LO_DS \.data\+0x10
+10: e0 83 00 00 lq r4,0\(r3\)
12: R_PPC64_ADDR16_LO_DS esym0
+14: e0 83 00 00 lq r4,0\(r3\)
16: R_PPC64_ADDR16_LO_DS esym1
+18: e0 82 00 00 lq r4,0\(r2\)
1a: R_PPC64_TOC16_DS \.toc
+1c: e0 82 00 00 lq r4,0\(r2\)
1e: R_PPC64_TOC16_DS \.toc\+0x8
+20: e0 82 00 10 lq r4,16\(r2\)
22: R_PPC64_TOC16_DS \.toc\+0x10
+24: e0 82 00 10 lq r4,16\(r2\)
26: R_PPC64_TOC16_DS \.toc\+0x18
+28: e0 82 00 20 lq r4,32\(r2\)
2a: R_PPC64_TOC16_DS \.toc\+0x20
+2c: e0 82 00 20 lq r4,32\(r2\)
2e: R_PPC64_TOC16_DS \.toc\+0x28
+30: e0 c2 00 20 lq r6,32\(r2\)
32: R_PPC64_TOC16_LO_DS \.toc\+0x28
+34: e0 80 00 00 lq r4,0\(0\)
36: R_PPC64_ADDR16_LO_DS \.text
+38: e0 c3 00 00 lq r6,0\(r3\)
3a: R_PPC64_GOT16_DS \.data
+3c: e0 c3 00 00 lq r6,0\(r3\)
3e: R_PPC64_GOT16_LO_DS \.data
+40: e0 c3 00 00 lq r6,0\(r3\)
42: R_PPC64_PLT16_LO_DS \.data
+44: e0 c3 00 00 lq r6,0\(r3\)
46: R_PPC64_SECTOFF_DS \.data\+0x8
+48: e0 c3 00 00 lq r6,0\(r3\)
4a: R_PPC64_SECTOFF_LO_DS \.data\+0x8
+4c: e0 c4 00 10 lq r6,16\(r4\)
+50: f8 c7 00 02 stq r6,0\(r7\)
+54: f8 c7 00 12 stq r6,16\(r7\)
+58: f8 c7 ff f2 stq r6,-16\(r7\)
+5c: f8 c7 80 02 stq r6,-32768\(r7\)
+60: f8 c7 7f f2 stq r6,32752\(r7\)
+64: 00 00 02 00 attn
+68: 7c 6f f1 20 mtcr r3
+6c: 7c 6f f1 20 mtcr r3
+70: 7c 68 11 20 mtcrf 129,r3
+74: 7c 70 11 20 mtocrf 1,r3
+78: 7c 70 21 20 mtocrf 2,r3
+7c: 7c 70 41 20 mtocrf 4,r3
+80: 7c 70 81 20 mtocrf 8,r3
+84: 7c 71 01 20 mtocrf 16,r3
+88: 7c 72 01 20 mtocrf 32,r3
+8c: 7c 74 01 20 mtocrf 64,r3
+90: 7c 78 01 20 mtocrf 128,r3
+94: 7c 60 00 26 mfcr r3
+98: 7c 70 10 26 mfocrf r3,1
+9c: 7c 70 20 26 mfocrf r3,2
+a0: 7c 70 40 26 mfocrf r3,4
+a4: 7c 70 80 26 mfocrf r3,8
+a8: 7c 71 00 26 mfocrf r3,16
+ac: 7c 72 00 26 mfocrf r3,32
+b0: 7c 74 00 26 mfocrf r3,64
+b4: 7c 78 00 26 mfocrf r3,128
+b8: 7c 01 17 ec dcbz r1,r2
+bc: 7c 23 27 ec dcbzl r3,r4
+c0: 7c 05 37 ec dcbz r5,r6
/ppc750ps.d
0,0 → 1,72
#as: -m750cl
#objdump: -dr -Mppcps
#name: PPC750CL paired single tests
 
.*: +file format elf(32)?(64)?-powerpc.*
 
Disassembly of section \.text:
 
0+0000000 <start>:
0: e0 03 d0 04 psq_l f0,4\(r3\),1,5
4: e4 22 30 08 psq_lu f1,8\(r2\),0,3
8: 10 45 25 4c psq_lux f2,r5,r4,1,2
c: 10 62 22 8c psq_lx f3,r2,r4,0,5
10: f0 62 30 08 psq_st f3,8\(r2\),0,3
14: f4 62 70 08 psq_stu f3,8\(r2\),0,7
18: 10 43 22 ce psq_stux f2,r3,r4,0,5
1c: 10 c7 46 0e psq_stx f6,r7,r8,1,4
20: 10 a0 3a 10 ps_abs f5,f7
24: 10 a0 3a 11 ps_abs. f5,f7
28: 10 22 18 2a ps_add f1,f2,f3
2c: 10 22 18 2b ps_add. f1,f2,f3
30: 11 82 20 40 ps_cmpo0 cr3,f2,f4
34: 11 82 20 c0 ps_cmpo1 cr3,f2,f4
38: 11 82 20 00 ps_cmpu0 cr3,f2,f4
3c: 11 82 20 80 ps_cmpu1 cr3,f2,f4
40: 10 44 30 24 ps_div f2,f4,f6
44: 10 44 30 25 ps_div. f2,f4,f6
48: 10 01 18 ba ps_madd f0,f1,f2,f3
4c: 10 01 18 bb ps_madd. f0,f1,f2,f3
50: 10 22 20 dc ps_madds0 f1,f2,f3,f4
54: 10 22 20 dd ps_madds0. f1,f2,f3,f4
58: 10 22 20 de ps_madds1 f1,f2,f3,f4
5c: 10 22 20 df ps_madds1. f1,f2,f3,f4
60: 10 44 34 20 ps_merge00 f2,f4,f6
64: 10 44 34 21 ps_merge00. f2,f4,f6
68: 10 44 34 60 ps_merge01 f2,f4,f6
6c: 10 44 34 61 ps_merge01. f2,f4,f6
70: 10 44 34 a0 ps_merge10 f2,f4,f6
74: 10 44 34 a1 ps_merge10. f2,f4,f6
78: 10 44 34 e0 ps_merge11 f2,f4,f6
7c: 10 44 34 e1 ps_merge11. f2,f4,f6
80: 10 60 28 90 ps_mr f3,f5
84: 10 60 28 91 ps_mr. f3,f5
88: 10 44 41 b8 ps_msub f2,f4,f6,f8
8c: 10 44 41 b9 ps_msub. f2,f4,f6,f8
90: 10 43 01 72 ps_mul f2,f3,f5
94: 10 43 01 73 ps_mul. f2,f3,f5
98: 10 64 01 d8 ps_muls0 f3,f4,f7
9c: 10 64 01 d9 ps_muls0. f3,f4,f7
a0: 10 64 01 da ps_muls1 f3,f4,f7
a4: 10 64 01 db ps_muls1. f3,f4,f7
a8: 10 20 29 10 ps_nabs f1,f5
ac: 10 20 29 11 ps_nabs. f1,f5
b0: 10 20 28 50 ps_neg f1,f5
b4: 10 20 28 51 ps_neg. f1,f5
b8: 10 23 39 7e ps_nmadd f1,f3,f5,f7
bc: 10 23 39 7f ps_nmadd. f1,f3,f5,f7
c0: 10 23 39 7c ps_nmsub f1,f3,f5,f7
c4: 10 23 39 7d ps_nmsub. f1,f3,f5,f7
c8: 11 20 18 30 ps_res f9,f3
cc: 11 20 18 31 ps_res. f9,f3
d0: 11 20 18 34 ps_rsqrte f9,f3
d4: 11 20 18 35 ps_rsqrte. f9,f3
d8: 10 22 20 ee ps_sel f1,f2,f3,f4
dc: 10 22 20 ef ps_sel. f1,f2,f3,f4
e0: 10 ab 10 28 ps_sub f5,f11,f2
e4: 10 ab 10 29 ps_sub. f5,f11,f2
e8: 10 45 52 54 ps_sum0 f2,f5,f9,f10
ec: 10 45 52 55 ps_sum0. f2,f5,f9,f10
f0: 10 45 52 56 ps_sum1 f2,f5,f9,f10
f4: 10 45 52 57 ps_sum1. f2,f5,f9,f10
f8: 10 03 2f ec dcbz_l r3,r5
/machine.s
0,0 → 1,15
.machine "403"
.text
mtpid 0
.machine push
.machine "booke"
mtpid 0
.machine Any
rfci
attn
sc
rfsvc
tlbiel 0
blr
.machine pop
mtpid 0
/booke_xcoff.d
0,0 → 1,25
#as: -mppc32 -mbooke32
#objdump: -mpowerpc -dr -Mbooke32
#name: xcoff BookE tests
 
.*: file format aixcoff-rs6000
 
Disassembly of section .text:
 
(00000000)?00000000 <.text>:
0: 7c 22 3f 64 tlbre r1,r2,7
4: 7c be 1f a4 tlbwe r5,r30,3
8: 7c a8 48 2c icbt 5,r8,r9
c: 7c a6 02 26 mfapidi r5,r6
10: 7c 07 46 24 tlbivax r7,r8
14: 7c 0b 67 24 tlbsx r11,r12
18: 4c 00 00 66 rfci
1c: 7c 60 01 06 wrtee r3
20: 7c 00 81 46 wrteei 1
24: 7c 85 02 06 mfdcrx r4,r5
28: 7c aa 3a 86 mfdcr r5,234
2c: 7c e6 03 06 mtdcrx r6,r7
30: 7d 10 6b 86 mtdcr 432,r8
34: 7c 00 04 ac msync
38: 7c 09 55 ec dcba r9,r10
3c: 7c 00 06 ac mbar
/range64.s
0,0 → 1,7
.text
ld 4,-32768(3)
ld 5,-1(3)
ld 6,2(3)
ld 7,32767(3)
ld 8,32768(3)
ld 9,-32769(3)
/astest2.d
0,0 → 1,87
#objdump: -Dr
#name: PowerPC test 2
 
.*: +file format elf32-powerpc
 
Disassembly of section \.text:
 
0+0000000 <foo>:
0: 60 00 00 00 nop
4: 60 00 00 00 nop
8: 60 00 00 00 nop
c: 48 00 00 04 b 10 <foo\+0x10>
10: 48 00 00 08 b 18 <foo\+0x18>
14: 48 00 00 00 b 14 <foo\+0x14>
14: R_PPC_REL24 x
18: 48 00 00 04 b 1c <foo\+0x1c>
18: R_PPC_REL24 \.data\+0x4
1c: 48 00 00 00 b 1c <foo\+0x1c>
1c: R_PPC_REL24 z
20: 48 00 00 14 b 34 <foo\+0x34>
20: R_PPC_REL24 z\+0x14
24: 48 00 00 04 b 28 <foo\+0x28>
28: 48 00 00 00 b 28 <foo\+0x28>
28: R_PPC_REL24 a
2c: 48 00 00 50 b 7c <apfour>
30: 48 00 00 04 b 34 <foo\+0x34>
30: R_PPC_REL24 a\+0x4
34: 48 00 00 4c b 80 <apfour\+0x4>
38: 48 00 00 00 b 38 <foo\+0x38>
38: R_PPC_LOCAL24PC a
3c: 48 00 00 40 b 7c <apfour>
40: 00 00 00 40 \.long 0x40
40: R_PPC_ADDR32 \.text\+0x40
44: 00 00 00 4c \.long 0x4c
44: R_PPC_ADDR32 \.text\+0x4c
48: 00 00 00 00 \.long 0x0
48: R_PPC_REL32 x
4c: 00 00 00 04 \.long 0x4
4c: R_PPC_REL32 x\+0x4
50: 00 00 00 00 \.long 0x0
50: R_PPC_REL32 z
54: 00 00 00 04 \.long 0x4
54: R_PPC_REL32 \.data\+0x4
58: 00 00 00 00 \.long 0x0
58: R_PPC_ADDR32 x
5c: 00 00 00 04 \.long 0x4
5c: R_PPC_ADDR32 \.data\+0x4
60: 00 00 00 00 \.long 0x0
60: R_PPC_ADDR32 z
64: ff ff ff fc fnmsub f31,f31,f31,f31
64: R_PPC_ADDR32 x\+0xf+ffffffc
68: 00 00 00 00 \.long 0x0
68: R_PPC_ADDR32 \.data
6c: ff ff ff fc fnmsub f31,f31,f31,f31
6c: R_PPC_ADDR32 z\+0xf+ffffffc
70: 00 00 00 08 \.long 0x8
74: 00 00 00 08 \.long 0x8
 
0+0000078 <a>:
78: 00 00 00 00 \.long 0x0
78: R_PPC_ADDR32 a
 
0+000007c <apfour>:
7c: 00 00 00 7c \.long 0x7c
7c: R_PPC_ADDR32 \.text\+0x7c
80: 00 00 00 7c \.long 0x7c
80: R_PPC_ADDR32 \.text\+0x7c
84: ff ff ff fc fnmsub f31,f31,f31,f31
88: 00 00 00 7e \.long 0x7e
88: R_PPC_ADDR32 \.text\+0x7e
8c: 00 00 00 00 \.long 0x0
90: 60 00 00 00 nop
94: 40 a5 ff fc ble- cr1,90 <apfour\+0x14>
98: 41 a9 ff f8 bgt- cr2,90 <apfour\+0x14>
9c: 40 8d ff f4 ble\+ cr3,90 <apfour\+0x14>
a0: 41 91 ff f0 bgt\+ cr4,90 <apfour\+0x14>
a4: 40 95 00 10 ble- cr5,b4 <nop>
a8: 41 99 00 0c bgt- cr6,b4 <nop>
ac: 40 bd 00 08 ble\+ cr7,b4 <nop>
b0: 41 a1 00 04 bgt\+ b4 <nop>
Disassembly of section \.data:
 
0+0000000 <x>:
0: 00 00 00 00 \.long 0x0
 
0+0000004 <y>:
4: 00 00 00 00 \.long 0x0
/altivec_xcoff64.d
0,0 → 1,15
#as: -a64 -mppc64 -maltivec
#objdump: -dr
#name: xcoff64 AltiVec tests
 
.*: file format aix5?coff64-rs6000
 
Disassembly of section .text:
 
0000000000000000 <.text>:
0: 7c 60 06 6c dss 3
4: 7e 00 06 6c dssall
8: 7c 25 22 ac dst r5,r4,1
c: 7e 08 3a ac dstt r8,r7,0
10: 7c 65 32 ec dstst r5,r6,3
14: 7e 44 2a ec dststt r4,r5,2
/e500mc.d
0,0 → 1,51
#as: -mppc -me500mc
#objdump: -dr -Me500mc
#name: Power E500MC tests
 
.*: +file format elf(32)?(64)?-powerpc.*
 
Disassembly of section \.text:
 
0+0000000 <start>:
0: 4c 00 00 4e rfdi
4: 4c 00 00 cc rfgi
8: 4c 1f f9 8c dnh 0,1023
c: 4f e0 01 8c dnh 31,0
10: 7c 09 57 be icbiep r9,r10
14: 7c 00 69 dc msgclr r13
18: 7c 00 71 9c msgsnd r14
1c: 7c 00 00 7c wait
20: 7f 9c e3 78 mdors
24: 7c 00 02 1c ehpriv
28: 7c 18 cb c6 dsn r24,r25
2c: 7c 22 18 be lbepx r1,r2,r3
30: 7c 85 32 3e lhepx r4,r5,r6
34: 7c e8 48 3e lwepx r7,r8,r9
38: 7d 4b 60 3a ldepx r10,r11,r12
3c: 7d ae 7c be lfdepx r13,r14,r15
40: 7e 11 91 be stbepx r16,r17,r18
44: 7e 74 ab 3e sthepx r19,r20,r21
48: 7e d7 c1 3e stwepx r22,r23,r24
4c: 7f 3a d9 3a stdepx r25,r26,r27
50: 7f 9d f5 be stfdepx r28,r29,r30
54: 7c 01 14 06 lbdx r0,r1,r2
58: 7d 8d 74 46 lhdx r12,r13,r14
5c: 7c 64 2c 86 lwdx r3,r4,r5
60: 7f 5b e6 46 lfddx f26,r27,r28
64: 7d f0 8c c6 lddx r15,r16,r17
68: 7c c7 45 06 stbdx r6,r7,r8
6c: 7e 53 a5 46 sthdx r18,r19,r20
70: 7d 2a 5d 86 stwdx r9,r10,r11
74: 7f be ff 46 stfddx f29,r30,r31
78: 7e b6 bd c6 stddx r21,r22,r23
7c: 7c 20 0d ec dcbal r0,r1
80: 7c 26 3f ec dcbzl r6,r7
84: 7c 1f 00 7e dcbstep r31,r0
88: 7c 01 10 fe dcbfep r1,r2
8c: 7c 64 29 fe dcbtstep r3,r4,r5
90: 7c c7 42 7e dcbtep r6,r7,r8
94: 7c 0b 67 fe dcbzep r11,r12
98: 7c 00 06 26 tlbilx 0,0,r0
9c: 7c 20 06 26 tlbilx 1,0,r0
a0: 7c 62 1e 26 tlbilx 3,r2,r3
a4: 7c 64 2e 26 tlbilx 3,r4,r5
/aix.exp
0,0 → 1,66
# Copyright (C) 2001, 2002 Free Software Foundation, Inc.
# Contributed by Red Hat
 
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
#
 
#
# Aix on PowerPC tests
#
proc do_align_test {} {
set testname "align.s: Alignment of symbols part 1"
set x0 0
set x1 0
set x2 0
set x3 0
set x4 0
 
set testname "align.s (part 2)"
 
if [gas_test_old "align.s" "" "Alignment of symbols part 1"] {
objdump_start_no_subdir "a.out" "-t"
 
while 1 {
expect {
-re "AUX val 16 prmhsh 0 snhsh 0 typ 3 algn 2 clss 5 stb 0 snstb 0" { set x0 1 }
-re "AUX val 32 prmhsh 0 snhsh 0 typ 3 algn 1 clss 5 stb 0 snstb 0" { set x1 1 }
-re "AUX val 64 prmhsh 0 snhsh 0 typ 3 algn 2 clss 5 stb 0 snstb 0" { set x2 1 }
-re "AUX val 128 prmhsh 0 snhsh 0 typ 3 algn 3 clss 5 stb 0 snstb 0" { set x3 1 }
-re "AUX val 256 prmhsh 0 snhsh 0 typ 3 algn 4 clss 5 stb 0 snstb 0" { set x4 1 }
-re "\[^\n\]*\n" { }
timeout { perror "timeout\n"; break }
eof { break }
}
}
 
objdump_finish
 
if [all_ones $x0 $x1 $x2 $x3 $x4] then {
pass $testname
} else {
fail $testname
}
}
}
 
 
if [istarget powerpc-ibm-aix*] then {
 
# Make sure that symbols are correctly aligned
do_align_test
 
run_dump_test "textalign-xcoff-001"
run_dump_test "textalign-xcoff-002"
}
/astest64.s
0,0 → 1,50
.section ".data"
.globl x
.globl z
x: .long 0
z = . + 4
four = z - x - 4
y: .long 0
.section ".text"
foo:
nop ; nop ; nop
.globl a
a: b .+4
b: b .+8
b x
b y
b z
b z+20
b .+four
b a
b b
b a+4
b b+4
.long .
.long .+8
.long x-.
.long x+4-.
.long z-.
.long y-.
.long x
.long y
.long z
.long x-four
.long y-four
.long z-four
.long a-.
.long b-.
.long a
.long b
 
apfour = a + four
.long apfour
.long a-apfour
.long apfour+2
.long apfour-b
 
.type foo,@function
.type a,@function
.type b,@function
.type apfour,@function
/simpshft.d
0,0 → 1,27
#objdump: -s -j .text
#as: -mppc64
#name: PowerPC test 3, simplified shifts
 
.*
 
Contents of section \.text:
0000 78640fe0 7883f80e 78a545e4 78640020 xd..x...x.E.xd.
0010 54640ffe 5083f800 54a5402e 5464043e Td..P...T.@.Td.>
0020 78640004 786407e4 7864f806 7864ffe6 xd..xd..xd..xd..
0030 7864f842 7864ffe2 7864000c 7864080c xd.Bxd..xd..xd..
0040 78640fac 786407ec 78640000 78640800 xd..xd..xd..xd..
0050 7864f802 78640000 7864f802 78640800 xd..xd..xd..xd..
0060 78652010 786407e4 7864f806 78640000 xe .xd..xd..xd..
0070 7864f842 78640fe0 78640000 78640040 xd.Bxd..xd..xd.@
0080 786407e0 786407e4 786407a4 78640004 xd..xd..xd..xd..
0090 78640008 78640048 786407e8 78640fa8 xd..xd.Hxd..xd..
00a0 7864f80a 54640000 5464003e 5464f800 xd..Td..Td.>Td..
00b0 5464f83e 5464f87e 5464fffe 50640000 Td.>Td.~Td..Pd..
00c0 5064003e 50640ffe 5064f800 5064003e Pd.>Pd..Pd..Pd.>
00d0 506407fe 5464003e 5464083e 5464f83e Pd..Td.>Td.>Td.>
00e0 5464003e 5464f83e 5464083e 5c65203e Td.>Td.>Td.>\\e >
00f0 5464003e 5464083c 5464f800 5464003e Td.>Td.<Td..Td.>
0100 5464f87e 54640ffe 5464003e 5464007e Td.~Td..Td.>Td.~
0110 546407fe 5464003e 5464003c 54640000 Td..Td.>Td.<Td..
0120 5464003e 5464007e 546407fe 54640fbc Td.>Td.~Td..Td..
0130 5464f800 00000000 Td......
/astest2_64.d
0,0 → 1,75
#objdump: -Dr
#name: PowerPC 64-bit test 2
 
.*: +file format elf64-powerpc
 
Disassembly of section \.text:
 
0000000000000000 <foo>:
0: 60 00 00 00 nop
4: 60 00 00 00 nop
8: 60 00 00 00 nop
c: 48 00 00 04 b 10 <foo\+0x10>
10: 48 00 00 08 b 18 <foo\+0x18>
14: 48 00 00 00 b 14 <foo\+0x14>
14: R_PPC64_REL24 x
18: 48 00 00 04 b 1c <foo\+0x1c>
18: R_PPC64_REL24 \.data\+0x4
1c: 48 00 00 00 b 1c <foo\+0x1c>
1c: R_PPC64_REL24 z
20: 48 00 00 14 b 34 <foo\+0x34>
20: R_PPC64_REL24 z\+0x14
24: 48 00 00 04 b 28 <foo\+0x28>
28: 48 00 00 00 b 28 <foo\+0x28>
28: R_PPC64_REL24 a
2c: 48 00 00 48 b 74 <apfour>
30: 48 00 00 04 b 34 <foo\+0x34>
30: R_PPC64_REL24 a\+0x4
34: 48 00 00 44 b 78 <apfour\+0x4>
38: 00 00 00 38 \.long 0x38
38: R_PPC64_ADDR32 \.text\+0x38
3c: 00 00 00 44 \.long 0x44
3c: R_PPC64_ADDR32 \.text\+0x44
40: 00 00 00 00 \.long 0x0
40: R_PPC64_REL32 x
44: 00 00 00 04 \.long 0x4
44: R_PPC64_REL32 x\+0x4
48: 00 00 00 00 \.long 0x0
48: R_PPC64_REL32 z
4c: 00 00 00 04 \.long 0x4
4c: R_PPC64_REL32 \.data\+0x4
50: 00 00 00 00 \.long 0x0
50: R_PPC64_ADDR32 x
54: 00 00 00 04 \.long 0x4
54: R_PPC64_ADDR32 \.data\+0x4
58: 00 00 00 00 \.long 0x0
58: R_PPC64_ADDR32 z
5c: ff ff ff fc fnmsub f31,f31,f31,f31
5c: R_PPC64_ADDR32 x\+0xfffffffffffffffc
60: 00 00 00 00 \.long 0x0
60: R_PPC64_ADDR32 \.data
64: ff ff ff fc fnmsub f31,f31,f31,f31
64: R_PPC64_ADDR32 z\+0xfffffffffffffffc
68: 00 00 00 08 \.long 0x8
6c: 00 00 00 08 \.long 0x8
 
0000000000000070 <a>:
70: 00 00 00 00 \.long 0x0
70: R_PPC64_ADDR32 a
 
0000000000000074 <apfour>:
74: 00 00 00 74 \.long 0x74
74: R_PPC64_ADDR32 \.text\+0x74
78: 00 00 00 74 \.long 0x74
78: R_PPC64_ADDR32 \.text\+0x74
7c: ff ff ff fc fnmsub f31,f31,f31,f31
80: 00 00 00 76 \.long 0x76
80: R_PPC64_ADDR32 \.text\+0x76
84: 00 00 00 00 \.long 0x0
Disassembly of section \.data:
 
0000000000000000 <x>:
0: 00 00 00 00 \.long 0x0
 
0000000000000004 <y>:
4: 00 00 00 00 \.long 0x0
/cell.s
0,0 → 1,24
.section ".text"
lvlx %r0, %r1, %r2
lvlx %r0, 0, %r2
lvlxl %r0, %r1, %r2
lvlxl %r0, 0, %r2
lvrx %r0, %r1, %r2
lvrx %r0, 0, %r2
lvrxl %r0, %r1, %r2
lvrxl %r0, 0, %r2
 
stvlx %r0, %r1, %r2
stvlx %r0, 0, %r2
stvlxl %r0, %r1, %r2
stvlxl %r0, 0, %r2
stvrx %r0, %r1, %r2
stvrx %r0, 0, %r2
stvrxl %r0, %r1, %r2
stvrxl %r0, 0, %r2
 
ldbrx %r0, 0, %r1
ldbrx %r0, %r1, %r2
 
stdbrx %r0, 0, %r1
stdbrx %r0, %r1, %r2
/power4.s
0,0 → 1,78
.section ".data"
dsym0: .llong 0xdeadbeef
dsym1:
 
.section ".toc"
.L_tsym0:
.tc ignored0[TC],dsym0
.L_tsym1:
.tc ignored1[TC],dsym1
.L_tsym2:
.tc ignored2[TC],usym0
.L_tsym3:
.tc ignored3[TC],usym1
.L_tsym4:
.tc ignored4[TC],esym0
.L_tsym5:
.tc ignored5[TC],esym1
 
.section ".text"
lq 4,dsym0@l(3)
lq 4,dsym1@l(3)
lq 4,usym0@l(3)
lq 4,usym1@l(3)
lq 4,esym0@l(3)
lq 4,esym1@l(3)
lq 4,.L_tsym0@toc(2)
lq 4,.L_tsym1@toc(2)
lq 4,.L_tsym2@toc(2)
lq 4,.L_tsym3@toc(2)
lq 4,.L_tsym4@toc(2)
lq 4,.L_tsym5@toc(2)
lq 6,.L_tsym5@toc@l(2)
lq 4,.text@l(0)
lq 6,dsym0@got(3)
lq 6,dsym0@got@l(3)
lq 6,dsym0@plt@l(3)
lq 6,dsym1@sectoff(3)
lq 6,dsym1@sectoff@l(3)
lq 6,usym1-dsym0@l(4)
stq 6,0(7)
stq 6,16(7)
stq 6,-16(7)
stq 6,-32768(7)
stq 6,32752(7)
 
attn
 
mtcr 3
mtcrf 0xff,3
mtcrf 0x81,3
mtcrf 0x01,3
mtcrf 0x02,3
mtcrf 0x04,3
mtcrf 0x08,3
mtcrf 0x10,3
mtcrf 0x20,3
mtcrf 0x40,3
mtcrf 0x80,3
mfcr 3
# mfcr 3,0xff #Error, invalid mask
# mfcr 3,0x81 #Error, invalid mask
mfcr 3,0x01
mfcr 3,0x02
mfcr 3,0x04
mfcr 3,0x08
mfcr 3,0x10
mfcr 3,0x20
mfcr 3,0x40
mfcr 3,0x80
 
dcbz 1, 2
dcbzl 3, 4
dcbz 5, 6
 
.section ".data"
usym0: .llong 0xcafebabe
usym1:
 
/booke.d
0,0 → 1,156
#as: -mbooke64
#objdump: -dr -Mbooke
#name: BookE tests
 
.*: +file format elf(32)?(64)?-powerpc.*
 
Disassembly of section \.text:
 
0+0000000 <start>:
0: 24 25 00 30 bce 1,4\*cr1\+gt,30 <branch_target_1>
4: 24 46 00 3d bcel 2,4\*cr1\+eq,40 <branch_target_2>
8: 24 67 00 52 bcea 3,4\*cr1\+so,50 <branch_target_3>
8: R_PPC(64)?_ADDR14 \.text\+0x50
c: 24 88 00 73 bcela 4,4\*cr2\+lt,70 <branch_target_4>
c: R_PPC(64)?_ADDR14 \.text\+0x70
10: 4c a9 00 22 bclre 5,4\*cr2\+gt
14: 4c aa 00 23 bclrel 5,4\*cr2\+eq
18: 4d 0b 04 22 bcctre 8,4\*cr2\+so
1c: 4d 0c 04 23 bcctrel 8,4\*cr3\+lt
20: 58 00 00 74 be 94 <branch_target_5>
24: 58 00 00 89 bel ac <branch_target_6>
28: 58 00 00 f6 bea f4 <branch_target_7>
28: R_PPC(64)?_ADDR24 \.text\+0xf4
2c: 58 00 01 2b bela 128 <branch_target_8>
2c: R_PPC(64)?_ADDR24 \.text\+0x128
 
0+0000030 <branch_target_1>:
30: e9 09 00 80 lbze r8,8\(r9\)
34: e9 8f 00 41 lbzue r12,4\(r15\)
38: 7c 86 40 fe lbzuxe r4,r6,r8
3c: 7c 65 38 be lbzxe r3,r5,r7
 
0+0000040 <branch_target_2>:
40: f8 a6 06 40 lde r5,400\(r6\)
44: f8 c7 07 11 ldue r6,452\(r7\)
48: 7c e8 4e 3e ldxe r7,r8,r9
4c: 7d 4b 66 7e lduxe r10,r11,r12
 
0+0000050 <branch_target_3>:
50: f9 81 02 06 lfde f12,128\(r1\)
54: f8 25 00 47 lfdue f1,16\(r5\)
58: 7c a1 1c be lfdxe f5,r1,r3
5c: 7c c2 24 fe lfduxe f6,r2,r4
60: f9 09 00 c4 lfse f8,48\(r9\)
64: f9 2a 01 15 lfsue f9,68\(r10\)
68: 7d 44 44 7e lfsuxe f10,r4,r8
6c: 7d 23 3c 3e lfsxe f9,r3,r7
 
0+0000070 <branch_target_4>:
70: e9 45 03 24 lhae r10,50\(r5\)
74: e8 23 00 55 lhaue r1,5\(r3\)
78: 7c a1 1a fe lhauxe r5,r1,r3
7c: 7f be fa be lhaxe r29,r30,r31
80: 7c 22 1e 3c lhbrxe r1,r2,r3
84: e8 83 01 22 lhze r4,18\(r3\)
88: e8 c9 01 43 lhzue r6,20\(r9\)
8c: 7c a7 4a 7e lhzuxe r5,r7,r9
90: 7d 27 2a 3e lhzxe r9,r7,r5
 
0+0000094 <branch_target_5>:
94: 7d 4f a0 fc lwarxe r10,r15,r20
98: 7c aa 94 3c lwbrxe r5,r10,r18
9c: eb 9d 00 46 lwze r28,4\(r29\)
a0: e9 0a 02 87 lwzue r8,40\(r10\)
a4: 7c 66 48 7e lwzuxe r3,r6,r9
a8: 7f dd e0 3e lwzxe r30,r29,r28
 
0+00000ac <branch_target_6>:
ac: 7c 06 3d fc dcbae r6,r7
b0: 7c 08 48 bc dcbfe r8,r9
b4: 7c 0a 5b bc dcbie r10,r11
b8: 7c 08 f0 7c dcbste r8,r30
bc: 7c c3 0a 3c dcbte 6,r3,r1
c0: 7c a4 11 fa dcbtste 5,r4,r2
c4: 7c 0f 77 fc dcbze r15,r14
c8: 7c 03 27 bc icbie r3,r4
cc: 7c a8 48 2c icbt 5,r8,r9
d0: 7c ca 78 3c icbte 6,r10,r15
d4: 7c a6 02 26 mfapidi r5,r6
d8: 7c 07 46 24 tlbivax r7,r8
dc: 7c 09 56 26 tlbivaxe r9,r10
e0: 7c 0b 67 24 tlbsx r11,r12
e4: 7c 0d 77 26 tlbsxe r13,r14
e8: 7c 00 07 a4 tlbwe
ec: 7c 00 07 a4 tlbwe
f0: 7c 21 0f a4 tlbwe r1,r1,1
 
0+00000f4 <branch_target_7>:
f4: 7c 22 1b 14 adde64 r1,r2,r3
f8: 7c 85 37 14 adde64o r4,r5,r6
fc: 7c e8 03 d4 addme64 r7,r8
100: 7d 2a 07 d4 addme64o r9,r10
104: 7d 6c 03 94 addze64 r11,r12
108: 7d ae 07 94 addze64o r13,r14
10c: 7e 80 04 40 mcrxr64 cr5
110: 7d f0 8b 10 subfe64 r15,r16,r17
114: 7e 53 a7 10 subfe64o r18,r19,r20
118: 7e b6 03 d0 subfme64 r21,r22
11c: 7e f8 07 d0 subfme64o r23,r24
120: 7f 3a 03 90 subfze64 r25,r26
124: 7f 7c 07 90 subfze64o r27,r28
 
0+0000128 <branch_target_8>:
128: e8 22 03 28 stbe r1,50\(r2\)
12c: e8 64 02 89 stbue r3,40\(r4\)
130: 7c a6 39 fe stbuxe r5,r6,r7
134: 7d 09 51 be stbxe r8,r9,r10
138: 7d 6c 6b ff stdcxe\. r11,r12,r13
13c: f9 cf 00 78 stde r14,28\(r15\)
140: fa 11 00 59 stdue r16,20\(r17\)
144: 7e 53 a7 3e stdxe r18,r19,r20
148: 7e b6 bf 7e stduxe r21,r22,r23
14c: f8 38 00 3e stfde f1,12\(r24\)
150: f8 59 00 0f stfdue f2,0\(r25\)
154: 7c 7a dd be stfdxe f3,r26,r27
158: 7c 9c ed fe stfduxe f4,r28,r29
15c: 7c be ff be stfiwxe f5,r30,r31
160: f8 de 00 6c stfse f6,24\(r30\)
164: f8 fd 00 5d stfsue f7,20\(r29\)
168: 7d 1c dd 3e stfsxe f8,r28,r27
16c: 7d 3a cd 7e stfsuxe f9,r26,r25
170: 7f 17 b7 3c sthbrxe r24,r23,r22
174: ea b4 01 ea sthe r21,30\(r20\)
178: ea 72 02 8b sthue r19,40\(r18\)
17c: 7e 30 7b 7e sthuxe r17,r16,r15
180: 7d cd 63 3e sthxe r14,r13,r12
184: 7d 6a 4d 3c stwbrxe r11,r10,r9
188: 7d 07 31 3d stwcxe\. r8,r7,r6
18c: e8 a4 03 2e stwe r5,50\(r4\)
190: e8 62 02 8f stwue r3,40\(r2\)
194: 7c 22 19 7e stwuxe r1,r2,r3
198: 7c 85 31 3e stwxe r4,r5,r6
19c: 4c 00 00 66 rfci
1a0: 7c 60 01 06 wrtee r3
1a4: 7c 00 81 46 wrteei 1
1a8: 7c 85 02 06 mfdcrx r4,r5
1ac: 7c aa 3a 86 mfdcr r5,234
1b0: 7c e6 03 06 mtdcrx r6,r7
1b4: 7d 10 6b 86 mtdcr 432,r8
1b8: 7c 00 04 ac msync
1bc: 7c 09 55 ec dcba r9,r10
1c0: 7c 00 06 ac mbar
1c4: 7c 00 06 ac mbar
1c8: 7c 20 06 ac mbar 1
1cc: 7d 8d 77 24 tlbsx r12,r13,r14
1d0: 7d 8d 77 25 tlbsx\. r12,r13,r14
1d4: 7d 8d 77 26 tlbsxe r12,r13,r14
1d8: 7d 8d 77 27 tlbsxe\. r12,r13,r14
1dc: 7c 12 42 a6 mfsprg r0,2
1e0: 7c 12 42 a6 mfsprg r0,2
1e4: 7c 12 43 a6 mtsprg 2,r0
1e8: 7c 12 43 a6 mtsprg 2,r0
1ec: 7c 07 42 a6 mfsprg r0,7
1f0: 7c 07 42 a6 mfsprg r0,7
1f4: 7c 17 43 a6 mtsprg 7,r0
1f8: 7c 17 43 a6 mtsprg 7,r0
/ppc750ps.s
0,0 → 1,66
# PowerPC 750 paired single precision tests
.section ".text"
start:
psq_l 0, 4(3), 1, 5
psq_lu 1, 8(2), 0, 3
psq_lux 2, 5, 4, 1, 2
psq_lx 3, 2, 4, 0, 5
psq_st 3, 8(2), 0, 3
psq_stu 3, 8(2), 0, 7
psq_stux 2, 3, 4, 0, 5
psq_stx 6, 7, 8, 1, 4
ps_abs 5,7
ps_abs. 5,7
ps_add 1,2,3
ps_add. 1,2,3
ps_cmpo0 3,2,4
ps_cmpo1 3,2,4
ps_cmpu0 3,2,4
ps_cmpu1 3,2,4
ps_div 2,4,6
ps_div. 2,4,6
ps_madd 0,1,2,3
ps_madd. 0,1,2,3
ps_madds0 1,2,3,4
ps_madds0. 1,2,3,4
ps_madds1 1,2,3,4
ps_madds1. 1,2,3,4
ps_merge00 2,4,6
ps_merge00. 2,4,6
ps_merge01 2,4,6
ps_merge01. 2,4,6
ps_merge10 2,4,6
ps_merge10. 2,4,6
ps_merge11 2,4,6
ps_merge11. 2,4,6
ps_mr 3,5
ps_mr. 3,5
ps_msub 2,4,6,8
ps_msub. 2,4,6,8
ps_mul 2,3,5
ps_mul. 2,3,5
ps_muls0 3,4,7
ps_muls0. 3,4,7
ps_muls1 3,4,7
ps_muls1. 3,4,7
ps_nabs 1,5
ps_nabs. 1,5
ps_neg 1,5
ps_neg. 1,5
ps_nmadd 1,3,5,7
ps_nmadd. 1,3,5,7
ps_nmsub 1,3,5,7
ps_nmsub. 1,3,5,7
ps_res 9,3
ps_res. 9,3
ps_rsqrte 9,3
ps_rsqrte. 9,3
ps_sel 1,2,3,4
ps_sel. 1,2,3,4
ps_sub 5,11,2
ps_sub. 5,11,2
ps_sum0 2,5,9,10
ps_sum0. 2,5,9,10
ps_sum1 2,5,9,10
ps_sum1. 2,5,9,10
dcbz_l 3,5
/test1elf64.d
0,0 → 1,151
#objdump: -Drx
#name: PowerPC Test 1, 64 bit elf
 
.*: +file format elf64-powerpc
.*
architecture: powerpc:common64, flags 0x00000011:
HAS_RELOC, HAS_SYMS
start address 0x0000000000000000
 
Sections:
Idx Name Size VMA LMA File off Algn
0 \.text 00000090 0000000000000000 0000000000000000 .*
CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
1 \.data 00000030 0000000000000000 0000000000000000 .*
CONTENTS, ALLOC, LOAD, RELOC, DATA
2 \.bss 00000000 0000000000000000 0000000000000000 .*
ALLOC
3 \.toc 00000030 0000000000000000 0000000000000000 .*
CONTENTS, ALLOC, LOAD, RELOC, DATA
SYMBOL TABLE:
0000000000000000 l d \.text 0000000000000000 (|\.text)
0000000000000000 l d \.data 0000000000000000 (|\.data)
0000000000000000 l d \.bss 0000000000000000 (|\.bss)
0000000000000000 l \.data 0000000000000000 dsym0
0000000000000008 l \.data 0000000000000000 dsym1
0000000000000000 l d \.toc 0000000000000000 (|\.toc)
0000000000000008 l \.data 0000000000000000 usym0
0000000000000010 l \.data 0000000000000000 usym1
0000000000000010 l \.data 0000000000000000 datpt
0000000000000014 l \.data 0000000000000000 dat0
0000000000000018 l \.data 0000000000000000 dat1
000000000000001c l \.data 0000000000000000 dat2
0000000000000020 l \.data 0000000000000000 dat3
0000000000000028 l \.data 0000000000000000 dat4
0000000000000000 \*UND\* 0000000000000000 esym0
0000000000000000 \*UND\* 0000000000000000 esym1
0000000000000000 \*UND\* 0000000000000000 jk
 
 
Disassembly of section \.text:
 
0000000000000000 <\.text>:
0: e8 63 00 00 ld r3,0\(r3\)
2: R_PPC64_ADDR16_LO_DS \.data
4: e8 63 00 08 ld r3,8\(r3\)
6: R_PPC64_ADDR16_LO_DS \.data\+0x8
8: e8 63 00 08 ld r3,8\(r3\)
a: R_PPC64_ADDR16_LO_DS \.data\+0x8
c: e8 63 00 10 ld r3,16\(r3\)
e: R_PPC64_ADDR16_LO_DS \.data\+0x10
10: e8 63 00 00 ld r3,0\(r3\)
12: R_PPC64_ADDR16_LO_DS esym0
14: e8 63 00 00 ld r3,0\(r3\)
16: R_PPC64_ADDR16_LO_DS esym1
18: e8 62 00 00 ld r3,0\(r2\)
1a: R_PPC64_TOC16_DS \.toc
1c: e8 62 00 08 ld r3,8\(r2\)
1e: R_PPC64_TOC16_DS \.toc\+0x8
20: e8 62 00 10 ld r3,16\(r2\)
22: R_PPC64_TOC16_DS \.toc\+0x10
24: e8 62 00 18 ld r3,24\(r2\)
26: R_PPC64_TOC16_DS \.toc\+0x18
28: e8 62 00 20 ld r3,32\(r2\)
2a: R_PPC64_TOC16_DS \.toc\+0x20
2c: e8 62 00 28 ld r3,40\(r2\)
2e: R_PPC64_TOC16_DS \.toc\+0x28
30: 3c 80 00 28 lis r4,40
32: R_PPC64_TOC16_HA \.toc\+0x28
34: e8 62 00 28 ld r3,40\(r2\)
36: R_PPC64_TOC16_LO_DS \.toc\+0x28
38: 38 60 00 08 li r3,8
3c: 38 60 ff f8 li r3,-8
40: 38 60 00 08 li r3,8
44: 38 60 ff f8 li r3,-8
48: 38 60 ff f8 li r3,-8
4c: 38 60 00 08 li r3,8
50: 38 60 00 00 li r3,0
52: R_PPC64_ADDR16_LO \.data
54: 38 60 00 00 li r3,0
56: R_PPC64_ADDR16_HI \.data
58: 38 60 00 00 li r3,0
5a: R_PPC64_ADDR16_HA \.data
5c: 38 60 00 00 li r3,0
5e: R_PPC64_ADDR16_HIGHER \.data
60: 38 60 00 00 li r3,0
62: R_PPC64_ADDR16_HIGHERA \.data
64: 38 60 00 00 li r3,0
66: R_PPC64_ADDR16_HIGHEST \.data
68: 38 60 00 00 li r3,0
6a: R_PPC64_ADDR16_HIGHESTA \.data
6c: 38 60 ff f8 li r3,-8
70: 38 60 ff ff li r3,-1
74: 38 60 00 00 li r3,0
78: 38 60 ff ff li r3,-1
7c: 38 60 00 00 li r3,0
80: 38 60 ff ff li r3,-1
84: 38 60 00 00 li r3,0
88: e8 64 00 08 ld r3,8\(r4\)
8c: e8 60 00 00 ld r3,0\(0\)
8e: R_PPC64_ADDR16_LO_DS \.text
Disassembly of section \.data:
 
0000000000000000 <dsym0>:
0: 00 00 00 00 \.long 0x0
4: de ad be ef stfdu f21,-16657\(r13\)
 
0000000000000008 <dsym1>:
8: 00 00 00 00 \.long 0x0
c: ca fe ba be lfd f23,-17730\(r30\)
 
0000000000000010 <datpt>:
10: 00 98 96 80 \.long 0x989680
10: R_PPC64_REL32 jk\+0x989680
 
0000000000000014 <dat0>:
14: ff ff ff fc fnmsub f31,f31,f31,f31
14: R_PPC64_REL32 jk\+0xfffffffffffffffc
 
0000000000000018 <dat1>:
18: 00 00 00 00 \.long 0x0
18: R_PPC64_REL32 jk
 
000000000000001c <dat2>:
1c: 00 00 00 04 \.long 0x4
1c: R_PPC64_REL32 jk\+0x4
 
0000000000000020 <dat3>:
20: 00 00 00 00 \.long 0x0
20: R_PPC64_REL64 jk\+0x8
24: 00 00 00 08 \.long 0x8
 
0000000000000028 <dat4>:
28: 00 00 00 00 \.long 0x0
28: R_PPC64_REL64 jk\+0x10
2c: 00 00 00 10 \.long 0x10
Disassembly of section \.toc:
 
0000000000000000 <\.toc>:
\.\.\.
0: R_PPC64_ADDR64 \.data
8: R_PPC64_ADDR64 \.data\+0x8
c: 00 00 00 08 \.long 0x8
10: 00 00 00 00 \.long 0x0
10: R_PPC64_ADDR64 \.data\+0x8
14: 00 00 00 08 \.long 0x8
18: 00 00 00 00 \.long 0x0
18: R_PPC64_ADDR64 \.data\+0x10
1c: 00 00 00 10 \.long 0x10
\.\.\.
20: R_PPC64_ADDR64 esym0
28: R_PPC64_ADDR64 esym1
/booke_xcoff.s
0,0 → 1,24
# Motorola PowerPC BookE tests
#as: -mbooke32
.csect .text[PR]
.csect main[DS]
main:
.csect .text[PR]
.main:
 
tlbre 1, 2, 7
tlbwe 5, 30, 3
icbt 5, 8, 9
mfapidi 5, 6
tlbivax 7, 8
tlbsx 11, 12
rfci
wrtee 3
wrteei 1
mfdcrx 4, 5
mfdcr 5, 234
mtdcrx 6, 7
mtdcr 432, 8
msync
dcba 9, 10
mbar 0
/astest.d
0,0 → 1,78
#objdump: -Dr
#name: PowerPC test 1
 
.*: +file format elf32-powerpc
 
Disassembly of section \.text:
 
0+0000000 <foo>:
0: 60 00 00 00 nop
4: 60 00 00 00 nop
8: 60 00 00 00 nop
 
0+000000c <a>:
c: 48 00 00 04 b 10 <apfour>
 
0+0000010 <apfour>:
10: 48 00 00 08 b 18 <apfour\+0x8>
14: 48 00 00 00 b 14 <apfour\+0x4>
14: R_PPC_REL24 x
18: 48 00 00 04 b 1c <apfour\+0xc>
18: R_PPC_REL24 \.data\+0x4
1c: 48 00 00 00 b 1c <apfour\+0xc>
1c: R_PPC_REL24 z
20: 48 00 00 14 b 34 <apfour\+0x24>
20: R_PPC_REL24 z\+0x14
24: 48 00 00 04 b 28 <apfour\+0x18>
28: 48 00 00 00 b 28 <apfour\+0x18>
28: R_PPC_REL24 a
2c: 4b ff ff e4 b 10 <apfour>
30: 48 00 00 04 b 34 <apfour\+0x24>
30: R_PPC_REL24 a\+0x4
34: 4b ff ff e0 b 14 <apfour\+0x4>
38: 48 00 00 00 b 38 <apfour\+0x28>
38: R_PPC_LOCAL24PC a
3c: 4b ff ff d4 b 10 <apfour>
40: 00 00 00 40 \.long 0x40
40: R_PPC_ADDR32 \.text\+0x40
44: 00 00 00 4c \.long 0x4c
44: R_PPC_ADDR32 \.text\+0x4c
48: 00 00 00 00 \.long 0x0
48: R_PPC_REL32 x
4c: 00 00 00 04 \.long 0x4
4c: R_PPC_REL32 x\+0x4
50: 00 00 00 00 \.long 0x0
50: R_PPC_REL32 z
54: 00 00 00 04 \.long 0x4
54: R_PPC_REL32 \.data\+0x4
58: 00 00 00 00 \.long 0x0
58: R_PPC_ADDR32 x
5c: 00 00 00 04 \.long 0x4
5c: R_PPC_ADDR32 \.data\+0x4
60: 00 00 00 00 \.long 0x0
60: R_PPC_ADDR32 z
64: ff ff ff fc fnmsub f31,f31,f31,f31
64: R_PPC_ADDR32 x\+0xf+ffffffc
68: 00 00 00 00 \.long 0x0
68: R_PPC_ADDR32 \.data
6c: ff ff ff fc fnmsub f31,f31,f31,f31
6c: R_PPC_ADDR32 z\+0xf+ffffffc
70: ff ff ff 9c \.long 0xffffff9c
74: ff ff ff 9c \.long 0xffffff9c
78: 00 00 00 00 \.long 0x0
78: R_PPC_ADDR32 a
7c: 00 00 00 10 \.long 0x10
7c: R_PPC_ADDR32 \.text\+0x10
80: 00 00 00 10 \.long 0x10
80: R_PPC_ADDR32 \.text\+0x10
84: ff ff ff fc fnmsub f31,f31,f31,f31
88: 00 00 00 12 \.long 0x12
88: R_PPC_ADDR32 \.text\+0x12
8c: 00 00 00 00 \.long 0x0
Disassembly of section \.data:
 
0+0000000 <x>:
0: 00 00 00 00 \.long 0x0
 
0+0000004 <y>:
4: 00 00 00 00 \.long 0x0
/astest2.s
0,0 → 1,66
four = 4
.section ".text"
foo:
nop ; nop ; nop
.globl a
b .+4
b .+8
b x
b y
b z
b z+20
b .+four
b a
b b
b a+4
b b+4
b a@local
b b@local
.long .
.long .+8
.long x-.
.long x+4-.
.long z-.
.long y-.
.long x
.long y
.long z
.long x-four
.long y-four
.long z-four
.long a-.
.long b-.
a: .long a
b: .long b
 
apfour = a + four
.long apfour
.long a-apfour
.long apfour+2
.long apfour-b
 
.section ".data"
.globl x
.globl z
x: .long 0
z = . + 4
y: .long 0
 
.type foo,@function
.type a,@function
.type b,@function
.type apfour,@function
 
.section ".text"
.L1:
nop
ble- 1,.L1
bgt- 2,.L1
ble+ 3,.L1
bgt+ 4,.L1
ble- 5,.L2
bgt- 6,.L2
ble+ 7,.L2
bgt+ 0,.L2
.L2:
nop:
/range.l
0,0 → 1,3
.*: Assembler messages:
.*:6: Error: operand out of range.*
.*:7: Error: operand out of range.*
/reloc.d
0,0 → 1,12
#readelf: -r --wide
#name: reloc
 
Relocation section '\.rela\.data' at .* contains 2 entries:
Offset Info Type Sym\. Value Symbol's Name \+ Addend
0+08 .* R_PPC_ADDR32 .* y \+ f+fc
0+0c .* R_PPC_ADDR32 .* y \+ 0
 
Relocation section '\.rela\.data\.other' at .* contains 2 entries:
Offset Info Type Sym\. Value Symbol's Name \+ Addend
0+00 .* R_PPC_ADDR32 .* x \+ 0
0+04 .* R_PPC_ADDR32 .* x \+ f+fc
/altivec_xcoff64.s
0,0 → 1,13
# PowerPC xcoff64 AltiVec tests
#as: -a64 -mppc64 -maltivec
.csect .text[PR]
.csect main[DS]
main:
.csect .text[PR]
.main:
dss 3
dssall
dst 5,4,1
dstt 8,7,0
dstst 5,6,3
dststt 4,5,2
/e500mc.s
0,0 → 1,45
# Power E500MC tests
.section ".text"
start:
rfdi
rfgi
dnh 0, 1023
dnh 31, 0
icbiep 9, 10
msgclr 13
msgsnd 14
wait
mdors
ehpriv
dsn 24, 25
lbepx 1, 2, 3
lhepx 4, 5, 6
lwepx 7, 8, 9
ldepx 10, 11, 12
lfdepx 13, 14, 15
stbepx 16, 17, 18
sthepx 19, 20, 21
stwepx 22, 23, 24
stdepx 25, 26, 27
stfdepx 28, 29, 30
lbdx 0, 1, 2
lhdx 12, 13, 14
lwdx 3, 4, 5
lfddx 26, 27, 28
lddx 15, 16, 17
stbdx 6, 7, 8
sthdx 18, 19, 20
stwdx 9, 10, 11
stfddx 29, 30, 31
stddx 21, 22, 23
dcbal 0, 1
dcbzl 6, 7
dcbstep 31, 0
dcbfep 1, 2
dcbtstep 3, 4, 5
dcbtep 6, 7, 8
dcbzep 11, 12
tlbilxlpid
tlbilxpid
tlbilxva 2, 3
tlbilx 3, 4, 5
/e500.d
0,0 → 1,51
#as: -mppc -me500
#objdump: -dr -Me500
#name: e500 tests
 
.*: +file format elf(32)?(64)?-powerpc.*
 
Disassembly of section \.text:
 
0+0000000 <start>:
0: 7c 43 25 de isel r2,r3,r4,23
4: 7c 85 33 0c dcblc 4,r5,r6
8: 7c e8 49 4c dcbtls 7,r8,r9
c: 7d 4b 61 0c dcbtstls 10,r11,r12
10: 7d ae 7b cc icbtls 13,r14,r15
14: 7e 11 91 cc icblc 16,r17,r18
18: 7c 89 33 9c mtpmr 201,r4
1c: 7c ab 32 9c mfpmr r5,203
20: 7c 00 04 0c bblels
24: 7c 00 04 4c bbelr
28: 7d 00 83 a6 mtspefscr r8
2c: 7d 20 82 a6 mfspefscr r9
30: 10 a0 22 cf efscfd r5,r4
34: 10 a4 02 e4 efdabs r5,r4
38: 10 a4 02 e5 efdnabs r5,r4
3c: 10 a4 02 e6 efdneg r5,r4
40: 10 a4 1a e0 efdadd r5,r4,r3
44: 10 a4 1a e1 efdsub r5,r4,r3
48: 10 a4 1a e8 efdmul r5,r4,r3
4c: 10 a4 1a e9 efddiv r5,r4,r3
50: 12 84 1a ec efdcmpgt cr5,r4,r3
54: 12 84 1a ed efdcmplt cr5,r4,r3
58: 12 84 1a ee efdcmpeq cr5,r4,r3
5c: 12 84 1a fc efdtstgt cr5,r4,r3
60: 12 84 1a fc efdtstgt cr5,r4,r3
64: 12 84 1a fd efdtstlt cr5,r4,r3
68: 12 84 1a fe efdtsteq cr5,r4,r3
6c: 10 a0 22 f1 efdcfsi r5,r4
70: 10 a0 22 e3 efdcfsid r5,r4
74: 10 a0 22 f0 efdcfui r5,r4
78: 10 a0 22 e2 efdcfuid r5,r4
7c: 10 a0 22 f3 efdcfsf r5,r4
80: 10 a0 22 f2 efdcfuf r5,r4
84: 10 a0 22 f5 efdctsi r5,r4
88: 10 a0 22 eb efdctsidz r5,r4
8c: 10 a0 22 fa efdctsiz r5,r4
90: 10 a0 22 f4 efdctui r5,r4
94: 10 a0 22 ea efdctuidz r5,r4
98: 10 a0 22 f8 efdctuiz r5,r4
9c: 10 a0 22 f7 efdctsf r5,r4
a0: 10 a0 22 f6 efdctuf r5,r4
a4: 10 a0 22 ef efdcfs r5,r4
/range.s
0,0 → 1,7
.text
lbz 4,-32768(3)
lbz 5,-1(3)
lbz 6,2(3)
lbz 7,32767(3)
lbz 8,32768(3)
lbz 9,-32769(3)
/altivec_xcoff.d
0,0 → 1,15
#as: -mppc -maltivec
#objdump: -mpowerpc -dr
#name: xcoff AltiVec tests
 
.*: file format aixcoff-rs6000
 
Disassembly of section .text:
 
(00000000)?00000000 <.text>:
0: 7c 60 06 6c dss 3
4: 7e 00 06 6c dssall
8: 7c 25 22 ac dst r5,r4,1
c: 7e 08 3a ac dstt r8,r7,0
10: 7c 65 32 ec dstst r5,r6,3
14: 7e 44 2a ec dststt r4,r5,2
/simpshft.s
0,0 → 1,110
# These are all the examples from section F.4 of
# "PowerPC Microprocessor Family: The Programming Environments".
# 64-bit examples
extrdi %r4,%r3,1,0
insrdi %r3,%r4,1,0
sldi %r5,%r5,8
clrldi %r4,%r3,32
# 32-bit examples
extrwi %r4,%r3,1,0
insrwi %r3,%r4,1,0
slwi %r5,%r5,8
clrlwi %r4,%r3,16
 
 
# These test the remaining corner cases for 64-bit operations.
extldi %r4,%r3,1,0
extldi %r4,%r3,64,0
extldi %r4,%r3,1,63
extldi %r4,%r3,64,63 # bit weird, that one.
extrdi %r4,%r3,63,0
extrdi %r4,%r3,1,62
 
insrdi %r4,%r3,64,0
insrdi %r4,%r3,63,0
insrdi %r4,%r3,1,62
insrdi %r4,%r3,1,63
 
rotldi %r4,%r3,0
rotldi %r4,%r3,1
rotldi %r4,%r3,63
 
rotrdi %r4,%r3,0
rotrdi %r4,%r3,1
rotrdi %r4,%r3,63
 
rotld %r5,%r3,%r4
 
sldi %r4,%r3,0
sldi %r4,%r3,63
 
srdi %r4,%r3,0
srdi %r4,%r3,1
srdi %r4,%r3,63
 
clrldi %r4,%r3,0
clrldi %r4,%r3,1
clrldi %r4,%r3,63
 
clrrdi %r4,%r3,0
clrrdi %r4,%r3,1
clrrdi %r4,%r3,63
clrlsldi %r4,%r3,0,0
clrlsldi %r4,%r3,1,0
clrlsldi %r4,%r3,63,0
clrlsldi %r4,%r3,63,1
clrlsldi %r4,%r3,63,63
# These test the remaining corner cases for 32-bit operations.
extlwi %r4,%r3,1,0
extlwi %r4,%r3,32,0
extlwi %r4,%r3,1,31
extlwi %r4,%r3,32,31 # bit weird, that one.
extrwi %r4,%r3,31,0
extrwi %r4,%r3,1,30
inslwi %r4,%r3,1,0
inslwi %r4,%r3,32,0
inslwi %r4,%r3,1,31
insrwi %r4,%r3,1,0
insrwi %r4,%r3,32,0
insrwi %r4,%r3,1,31
rotlwi %r4,%r3,0
rotlwi %r4,%r3,1
rotlwi %r4,%r3,31
 
rotrwi %r4,%r3,0
rotrwi %r4,%r3,1
rotrwi %r4,%r3,31
 
rotlw %r5,%r3,%r4
 
slwi %r4,%r3,0
slwi %r4,%r3,1
slwi %r4,%r3,31
 
srwi %r4,%r3,0
srwi %r4,%r3,1
srwi %r4,%r3,31
 
clrlwi %r4,%r3,0
clrlwi %r4,%r3,1
clrlwi %r4,%r3,31
 
clrrwi %r4,%r3,0
clrrwi %r4,%r3,1
clrrwi %r4,%r3,31
clrlslwi %r4,%r3,0,0
clrlslwi %r4,%r3,1,0
clrlslwi %r4,%r3,31,0
clrlslwi %r4,%r3,31,1
clrlslwi %r4,%r3,31,31
 
# Force alignment so that we pass the test on AIX
.p2align 3,0
/astest2_64.s
0,0 → 1,50
four = 4
.section ".text"
foo:
nop ; nop ; nop
.globl a
b .+4
b .+8
b x
b y
b z
b z+20
b .+four
b a
b b
b a+4
b b+4
.long .
.long .+8
.long x-.
.long x+4-.
.long z-.
.long y-.
.long x
.long y
.long z
.long x-four
.long y-four
.long z-four
.long a-.
.long b-.
a: .long a
b: .long b
 
apfour = a + four
.long apfour
.long a-apfour
.long apfour+2
.long apfour-b
 
.section ".data"
.globl x
.globl z
x: .long 0
z = . + 4
y: .long 0
 
.type foo,@function
.type a,@function
.type b,@function
.type apfour,@function
/booke.s
0,0 → 1,150
# Motorola PowerPC BookE tests
#as: -mbooke32
.section ".text"
start:
bce 1, 5, branch_target_1
bcel 2, 6, branch_target_2
bcea 3, 7, branch_target_3
bcela 4, 8, branch_target_4
bclre 5, 9
bclrel 5, 10
bcctre 8, 11
bcctrel 8, 12
be branch_target_5
bel branch_target_6
bea branch_target_7
bela branch_target_8
 
branch_target_1:
lbze 8, 8(9)
lbzue 12, 4(15)
lbzuxe 4, 6, 8
lbzxe 3, 5, 7
 
branch_target_2:
lde 5, 400(6)
ldue 6, 452(7)
ldxe 7, 8, 9
lduxe 10, 11, 12
 
branch_target_3:
lfde 12, 128(1)
lfdue 1, 16(5)
lfdxe 5, 1, 3
lfduxe 6, 2, 4
lfse 8, 48(9)
lfsue 9, 68(10)
lfsuxe 10, 4, 8
lfsxe 9, 3, 7
 
branch_target_4:
lhae 10, 50(5)
lhaue 1, 5(3)
lhauxe 5, 1, 3
lhaxe 29, 30, 31
lhbrxe 1, 2, 3
lhze 4, 18(3)
lhzue 6, 20(9)
lhzuxe 5, 7, 9
lhzxe 9, 7, 5
 
branch_target_5:
lwarxe 10, 15, 20
lwbrxe 5, 10, 18
lwze 28, 4(29)
lwzue 8, 40(10)
lwzuxe 3, 6, 9
lwzxe 30, 29, 28
 
branch_target_6:
dcbae 6, 7
dcbfe 8, 9
dcbie 10, 11
dcbste 8, 30
dcbte 6, 3, 1
dcbtste 5, 4, 2
dcbze 15, 14
icbie 3, 4
icbt 5, 8, 9
icbte 6, 10, 15
mfapidi 5, 6
tlbivax 7, 8
tlbivaxe 9, 10
tlbsx 11, 12
tlbsxe 13, 14
tlbwe
tlbwe 0,0,0
tlbwe 1,1,1
 
branch_target_7:
adde64 1, 2, 3
adde64o 4, 5, 6
addme64 7, 8
addme64o 9, 10
addze64 11, 12
addze64o 13, 14
mcrxr64 5
subfe64 15, 16, 17
subfe64o 18, 19, 20
subfme64 21, 22
subfme64o 23, 24
subfze64 25, 26
subfze64o 27, 28
 
branch_target_8:
stbe 1, 50(2)
stbue 3, 40(4)
stbuxe 5, 6, 7
stbxe 8, 9, 10
stdcxe. 11, 12, 13
stde 14, 28(15)
stdue 16, 20(17)
stdxe 18, 19, 20
stduxe 21, 22, 23
stfde 1, 12(24)
stfdue 2, 0(25)
stfdxe 3, 26, 27
stfduxe 4, 28, 29
stfiwxe 5, 30, 31
stfse 6, 24(30)
stfsue 7, 20(29)
stfsxe 8, 28, 27
stfsuxe 9, 26, 25
sthbrxe 24, 23, 22
sthe 21, 30(20)
sthue 19, 40(18)
sthuxe 17, 16, 15
sthxe 14, 13, 12
stwbrxe 11, 10, 9
stwcxe. 8, 7, 6
stwe 5, 50(4)
stwue 3, 40(2)
stwuxe 1, 2, 3
stwxe 4, 5, 6
 
rfci
wrtee 3
wrteei 1
mfdcrx 4, 5
mfdcr 5, 234
mtdcrx 6, 7
mtdcr 432, 8
msync
dcba 9, 10
mbar
mbar 0
mbar 1
 
tlbsx 12, 13, 14
tlbsx. 12, 13, 14
tlbsxe 12, 13, 14
tlbsxe. 12, 13, 14
 
mfsprg 0, 2
mfsprg2 0
mtsprg 2, 0
mtsprg2 0
mfsprg 0, 7
mfsprg7 0
mtsprg 7, 0
mtsprg7 0
/altivec_and_spe.d
0,0 → 1,12
#as: -maltivec -mspe -mppc64
#objdump: -d -Mppc64
#name: Check that ISA extensions can be specified before CPU selection
 
.*: +file format elf.*-powerpc.*
 
Disassembly of section \.text:
 
0+00 <.*>:
0: 7e 00 06 6c dssall
4: 7d 00 83 a6 mtspr 512,r8
8: 4c 00 00 24 rfid
/test1elf64.s
0,0 → 1,95
 
 
 
 
.section ".data"
dsym0: .llong 0xdeadbeef
dsym1:
 
 
.section ".toc"
.L_tsym0:
.tc ignored0[TC],dsym0
.L_tsym1:
.tc ignored1[TC],dsym1
.L_tsym2:
.tc ignored2[TC],usym0
.L_tsym3:
.tc ignored3[TC],usym1
.L_tsym4:
.tc ignored4[TC],esym0
.L_tsym5:
.tc ignored5[TC],esym1
 
 
.section ".text"
ld 3,dsym0@l(3)
ld 3,dsym1@l(3)
ld 3,usym0@l(3)
ld 3,usym1@l(3)
ld 3,esym0@l(3)
ld 3,esym1@l(3)
 
 
ld 3,.L_tsym0@toc(2)
ld 3,.L_tsym1@toc(2)
ld 3,.L_tsym2@toc(2)
ld 3,.L_tsym3@toc(2)
ld 3,.L_tsym4@toc(2)
ld 3,.L_tsym5@toc(2)
 
lis 4,.L_tsym5@toc@ha
ld 3,.L_tsym5@toc@l(2)
 
 
li 3,dsym1-dsym0
li 3,dsym0-dsym1
li 3,usym1-usym0
li 3,usym0-usym1
li 3,dsym0-usym0
li 3,usym0-dsym0
 
li 3,dsym0@l
li 3,dsym0@h
li 3,dsym0@ha
 
li 3,dsym0@higher
li 3,dsym0@highera
li 3,dsym0@highest
li 3,dsym0@highesta
 
 
li 3,usym0-usym1@l
li 3,usym0-usym1@h
li 3,usym0-usym1@ha
 
li 3,usym0-usym1@higher
li 3,usym0-usym1@highera
li 3,usym0-usym1@highest
li 3,usym0-usym1@highesta
 
 
ld 3,dsym1-dsym0@l(4)
 
ld 3,.text@l(0)
 
.section ".data"
usym0: .llong 0xcafebabe
usym1:
 
datpt: .long jk-.+10000000
dat0: .long jk-dat1
dat1: .long jk-dat1
dat2: .long jk-dat1
 
dat3: .llong jk-dat1
dat4: .llong jk-dat1
 
/generate.sh
0,0 → 1,6
#! /bin/sh
 
m4 -DELF32 test1elf.asm >test1elf32.s
m4 -DELF64 test1elf.asm >test1elf64.s
m4 -DXCOFF32 test1xcoff.asm >test1xcoff32.s
#m4 -DXCOFF64 test1xcoff.asm >test1xcoff64.s
generate.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: astest.s =================================================================== --- astest.s (nonexistent) +++ astest.s (revision 816) @@ -0,0 +1,52 @@ + .section ".data" + .globl x + .globl z +x: .long 0 +z = . + 4 +four = z - x - 4 +y: .long 0 + + .section ".text" +foo: + nop ; nop ; nop + .globl a +a: b .+4 +b: b .+8 + b x + b y + b z + b z+20 + b .+four + b a + b b + b a+4 + b b+4 + b a@local + b b@local + .long . + .long .+8 + .long x-. + .long x+4-. + .long z-. + .long y-. + .long x + .long y + .long z + .long x-four + .long y-four + .long z-four + .long a-. + .long b-. + .long a + .long b + +apfour = a + four + .long apfour + .long a-apfour + .long apfour+2 + .long apfour-b + + .type foo,@function + .type a,@function + .type b,@function + .type apfour,@function Index: reloc.s =================================================================== --- reloc.s (nonexistent) +++ reloc.s (revision 816) @@ -0,0 +1,13 @@ + .reloc x+8, R_PPC_ADDR32, y-4 + + .data +x: + .long 0,0,0,0 + + .section .data.other,"aw",@progbits +y: + .long 0,0,0,0 + + .reloc 0, R_PPC_ADDR32, x + .reloc y+4, R_PPC_ADDR32, x-4 + .reloc x+12, R_PPC_ADDR32, y Index: test1xcoff.asm =================================================================== --- test1xcoff.asm (nonexistent) +++ test1xcoff.asm (revision 816) @@ -0,0 +1,82 @@ +dnl divert(-1) +ifdef(`XCOFF64', +` define(`WORD',`.llong') + define(`LDW',`ld')') +ifdef(`XCOFF32', +` define(`WORD',`.long') + define(`LDW',`lwz')') +dnl divert(0) dnl + +define(`nl',` +') nl nl nl nl nl nl + + .csect [RW] +dsym0: WORD 0xdeadbeef +dsym1: + + .toc +.L_tsym0: + .tc ignored0[TC],dsym0 +.L_tsym1: + .tc ignored1[TC],dsym1 +.L_tsym2: + .tc ignored2[TC],usym0 +.L_tsym3: + .tc ignored3[TC],usym1 +.L_tsym4: + .tc ignored4[TC],esym0 +.L_tsym5: + .tc ignored5[TC],esym1 +.L_tsym6: + .tc ignored6[TC],.text + + .csect .crazy_table[RO] +xdsym0: WORD 0xbeefed +xdsym1: + .csect [PR] + .lglobl reference_csect_relative_symbols +reference_csect_relative_symbols: + LDW 3,xdsym0(3) + LDW 3,xdsym1(3) + LDW 3,xusym0(3) + LDW 3,xusym1(3) + + .lglobl dubious_references_to_default_RW_csect +dubious_references_to_default_RW_csect: + LDW 3,dsym0(3) + LDW 3,dsym1(3) + LDW 3,usym0(3) + LDW 3,usym1(3) + + .lglobl reference_via_toc +reference_via_toc: + LDW 3,.L_tsym0(2) + LDW 3,.L_tsym1(2) + LDW 3,.L_tsym2(2) + LDW 3,.L_tsym3(2) + LDW 3,.L_tsym4(2) + LDW 3,.L_tsym5(2) + + .lglobl subtract_symbols +subtract_symbols: + li 3,dsym1-dsym0 + li 3,dsym0-dsym1 + li 3,usym1-usym0 + li 3,usym0-usym1 + li 3,dsym0-usym0 + li 3,usym0-dsym0 + LDW 3,dsym1-dsym0(4) + + .lglobl load_addresses +load_addresses: + la 3,xdsym0(0) + la 3,xusym0(0) + + la 3,.L_tsym6(2) + + .csect [RW] +usym0: WORD 0xcafebabe +usym1: WORD 0xbaad + .csect .crazy_table[RO] +xusym0: WORD 0xbeefed +xusym1: Index: test1elf.asm =================================================================== --- test1elf.asm (nonexistent) +++ test1elf.asm (revision 816) @@ -0,0 +1,95 @@ +dnl divert(-1) +ifdef(`ELF64', +` define(`WORD',`.llong') + define(`LDW',`ld')') +ifdef(`ELF32', +` define(`WORD',`.long') + define(`LDW',`lwz')') +dnl divert(0) dnl + +define(`nl',` +') nl nl nl nl nl nl + + .section ".data" +dsym0: WORD 0xdeadbeef +dsym1: + +ifdef(`ELF64',` + .section ".toc" +.L_tsym0: + .tc ignored0[TC],dsym0 +.L_tsym1: + .tc ignored1[TC],dsym1 +.L_tsym2: + .tc ignored2[TC],usym0 +.L_tsym3: + .tc ignored3[TC],usym1 +.L_tsym4: + .tc ignored4[TC],esym0 +.L_tsym5: + .tc ignored5[TC],esym1 +') + + .section ".text" + LDW 3,dsym0@l(3) + LDW 3,dsym1@l(3) + LDW 3,usym0@l(3) + LDW 3,usym1@l(3) + LDW 3,esym0@l(3) + LDW 3,esym1@l(3) + +ifdef(`ELF64',` + LDW 3,.L_tsym0@toc(2) + LDW 3,.L_tsym1@toc(2) + LDW 3,.L_tsym2@toc(2) + LDW 3,.L_tsym3@toc(2) + LDW 3,.L_tsym4@toc(2) + LDW 3,.L_tsym5@toc(2) + + lis 4,.L_tsym5@toc@ha + LDW 3,.L_tsym5@toc@l(2) +') + + li 3,dsym1-dsym0 + li 3,dsym0-dsym1 + li 3,usym1-usym0 + li 3,usym0-usym1 + li 3,dsym0-usym0 + li 3,usym0-dsym0 + + li 3,dsym0@l + li 3,dsym0@h + li 3,dsym0@ha +ifdef(`ELF64',` + li 3,dsym0@higher + li 3,dsym0@highera + li 3,dsym0@highest + li 3,dsym0@highesta +') + + li 3,usym0-usym1@l + li 3,usym0-usym1@h + li 3,usym0-usym1@ha +ifdef(`ELF64',` + li 3,usym0-usym1@higher + li 3,usym0-usym1@highera + li 3,usym0-usym1@highest + li 3,usym0-usym1@highesta +') + + LDW 3,dsym1-dsym0@l(4) + + LDW 3,.text@l(0) + + .section ".data" +usym0: WORD 0xcafebabe +usym1: + +datpt: .long jk-.+10000000 +dat0: .long jk-dat1 +dat1: .long jk-dat1 +dat2: .long jk-dat1 +ifdef(`ELF64',` +dat3: .llong jk-dat1 +dat4: .llong jk-dat1 +') Index: altivec.d =================================================================== --- altivec.d (nonexistent) +++ altivec.d (revision 816) @@ -0,0 +1,15 @@ +#as: -a32 -m601 -maltivec +#objdump: -dr +#name: AltiVec tests + +.*: +file format elf32-powerpc.* + +Disassembly of section \.text: + +00000000 : + 0: 7c 60 06 6c dss 3 + 4: 7e 00 06 6c dssall + 8: 7c 25 22 ac dst r5,r4,1 + c: 7e 08 3a ac dstt r8,r7,0 + 10: 7c 65 32 ec dstst r5,r6,3 + 14: 7e 44 2a ec dststt r4,r5,2 Index: e500.s =================================================================== --- e500.s (nonexistent) +++ e500.s (revision 816) @@ -0,0 +1,47 @@ +# Motorola PowerPC e500 tests + .section ".text" +start: + isel 2, 3, 4, 23 + dcblc 4, 5, 6 + dcbtls 7, 8, 9 + dcbtstls 10, 11, 12 + icbtls 13, 14, 15 + icblc 16, 17, 18 + mtpmr 201, 4 + mfpmr 5, 203 + bblels + bbelr + mtspefscr 8 + mfspefscr 9 + + # Double-precision opcodes. + efscfd 5,4 + efdabs 5,4 + efdnabs 5,4 + efdneg 5,4 + efdadd 5,4,3 + efdsub 5,4,3 + efdmul 5,4,3 + efddiv 5,4,3 + efdcmpgt 5,4,3 + efdcmplt 5,4,3 + efdcmpeq 5,4,3 + efdtstgt 5,4,3 + efdtstgt 5,4,3 + efdtstlt 5,4,3 + efdtsteq 5,4,3 + efdcfsi 5,4 + efdcfsid 5,4 + efdcfui 5,4 + efdcfuid 5,4 + efdcfsf 5,4 + efdcfuf 5,4 + efdctsi 5,4 + efdctsidz 5,4 + efdctsiz 5,4 + efdctui 5,4 + efdctuidz 5,4 + efdctuiz 5,4 + efdctsf 5,4 + efdctuf 5,4 + efdcfs 5,4 Index: altivec_xcoff.s =================================================================== --- altivec_xcoff.s (nonexistent) +++ altivec_xcoff.s (revision 816) @@ -0,0 +1,15 @@ +# PowerPC xcoff AltiVec tests +#as: -mppc -maltivec + .csect .text[PR] + .csect main[DS] +main: + .csect .text[PR] +.main: + dss 3 + dssall + dst 5,4,1 + dstt 8,7,0 + dstst 5,6,3 + dststt 4,5,2 + + Index: ppc.exp =================================================================== --- ppc.exp (nonexistent) +++ ppc.exp (revision 816) @@ -0,0 +1,49 @@ +# +# Some PowerPC tests +# + +# These tests are currently ELF specific, only because nobody has +# converted them to look for XCOFF relocations. + +if { [istarget powerpc64*-*-*] || [istarget *-*-elf64*]} then { +# FIXME: Pass -x to objdump as well as -Dr for astest64 and astest2_64. + run_dump_test "astest64" + run_dump_test "astest2_64" + run_dump_test "test1elf64" + run_dump_test "power4" + run_dump_test "cell" + run_list_test "range64" "-a64" +} elseif { [istarget powerpc*-*aix*] } then { + run_dump_test "test1xcoff32" +} elseif { [istarget powerpc*-*-*bsd*] \ + || [istarget powerpc*-*-elf*] \ + || [istarget powerpc*-*-eabi*] \ + || [istarget powerpc*-*-sysv4*] \ + || [istarget powerpc*-*-linux*] \ + || [istarget powerpc*-*-solaris*] \ + || [istarget powerpc*-*-rtems*] } then { + run_dump_test "astest" + run_dump_test "astest2" + run_dump_test "test1elf32" +} + +if { [istarget powerpc*-*-*] } then { + run_dump_test "simpshft" + run_dump_test "machine" + run_dump_test "regnames" + + if { [istarget powerpc-*-*aix*] } then { + run_dump_test "altivec_xcoff" + run_dump_test "altivec_xcoff64" + run_dump_test "booke_xcoff" + run_dump_test "booke_xcoff64" + } else { + run_dump_test "altivec" + run_dump_test "altivec_and_spe" + run_dump_test "booke" + run_dump_test "e500" + run_list_test "range" "-a32" + run_dump_test "ppc750ps" + run_dump_test "e500mc" + } +} Index: test1xcoff32.d =================================================================== --- test1xcoff32.d (nonexistent) +++ test1xcoff32.d (revision 816) @@ -0,0 +1,139 @@ +#objdump: -Drx +#as: +#name: PowerPC Test 1, 32 bit XCOFF + +.*: +file format aixcoff-rs6000 +.* +architecture: rs6000:6000, flags 0x00000031: +HAS_RELOC, HAS_SYMS, HAS_LOCALS +start address 0x0+0000 + +Sections: +Idx Name +Size +VMA +LMA +File off +Algn + 0 \.text +00000068 0+0000 0+0000 000000a8 2\*\*2 + +CONTENTS, ALLOC, LOAD, RELOC, CODE + 1 \.data +00000028 0+0068 0+0068 00000110 2\*\*3 + +CONTENTS, ALLOC, LOAD, RELOC, DATA + 2 \.bss +00000000 0+0090 0+0090 00000000 2\*\*3 + +ALLOC +SYMBOL TABLE: +\[ 0\]\(sec -2\)\(fl 0x00\)\(ty 0\)\(scl 103\) \(nx 1\) 0x00000000 fake +File +\[ 2\]\(sec 1\)\(fl 0x00\)\(ty 0\)\(scl 107\) \(nx 1\) 0x00000000 \.crazy_table +AUX val 8 prmhsh 0 snhsh 0 typ 1 algn 2 clss 1 stb 0 snstb 0 +\[ 4\]\(sec 1\)\(fl 0x00\)\(ty 0\)\(scl 107\) \(nx 1\) 0x00000008 +AUX val 96 prmhsh 0 snhsh 0 typ 1 algn 2 clss 0 stb 0 snstb 0 +\[ 6\]\(sec 1\)\(fl 0x00\)\(ty 0\)\(scl 107\) \(nx 1\) 0x00000008 reference_csect_relative_symbols +AUX indx 4 prmhsh 0 snhsh 0 typ 2 algn 0 clss 0 stb 0 snstb 0 +\[ 8\]\(sec 1\)\(fl 0x00\)\(ty 0\)\(scl 107\) \(nx 1\) 0x00000018 dubious_references_to_default_RW_csect +AUX indx 4 prmhsh 0 snhsh 0 typ 2 algn 0 clss 0 stb 0 snstb 0 +\[ 10\]\(sec 1\)\(fl 0x00\)\(ty 0\)\(scl 107\) \(nx 1\) 0x00000028 reference_via_toc +AUX indx 4 prmhsh 0 snhsh 0 typ 2 algn 0 clss 0 stb 0 snstb 0 +\[ 12\]\(sec 1\)\(fl 0x00\)\(ty 0\)\(scl 107\) \(nx 1\) 0x00000040 subtract_symbols +AUX indx 4 prmhsh 0 snhsh 0 typ 2 algn 0 clss 0 stb 0 snstb 0 +\[ 14\]\(sec 1\)\(fl 0x00\)\(ty 0\)\(scl 107\) \(nx 1\) 0x0000005c load_addresses +AUX indx 4 prmhsh 0 snhsh 0 typ 2 algn 0 clss 0 stb 0 snstb 0 +\[ 16\]\(sec 2\)\(fl 0x00\)\(ty 0\)\(scl 107\) \(nx 1\) 0x00000068 +AUX val 12 prmhsh 0 snhsh 0 typ 1 algn 2 clss 5 stb 0 snstb 0 +\[ 18\]\(sec 2\)\(fl 0x00\)\(ty 0\)\(scl 107\) \(nx 1\) 0x00000074 TOC +AUX val 0 prmhsh 0 snhsh 0 typ 1 algn 2 clss 15 stb 0 snstb 0 +\[ 20\]\(sec 2\)\(fl 0x00\)\(ty 0\)\(scl 107\) \(nx 1\) 0x00000074 ignored0 +AUX val 4 prmhsh 0 snhsh 0 typ 1 algn 2 clss 3 stb 0 snstb 0 +\[ 22\]\(sec 2\)\(fl 0x00\)\(ty 0\)\(scl 107\) \(nx 1\) 0x00000078 ignored1 +AUX val 4 prmhsh 0 snhsh 0 typ 1 algn 2 clss 3 stb 0 snstb 0 +\[ 24\]\(sec 2\)\(fl 0x00\)\(ty 0\)\(scl 107\) \(nx 1\) 0x0000007c ignored2 +AUX val 4 prmhsh 0 snhsh 0 typ 1 algn 2 clss 3 stb 0 snstb 0 +\[ 26\]\(sec 2\)\(fl 0x00\)\(ty 0\)\(scl 107\) \(nx 1\) 0x00000080 ignored3 +AUX val 4 prmhsh 0 snhsh 0 typ 1 algn 2 clss 3 stb 0 snstb 0 +\[ 28\]\(sec 2\)\(fl 0x00\)\(ty 0\)\(scl 107\) \(nx 1\) 0x00000084 ignored4 +AUX val 4 prmhsh 0 snhsh 0 typ 1 algn 2 clss 3 stb 0 snstb 0 +\[ 30\]\(sec 2\)\(fl 0x00\)\(ty 0\)\(scl 107\) \(nx 1\) 0x00000088 ignored5 +AUX val 4 prmhsh 0 snhsh 0 typ 1 algn 2 clss 3 stb 0 snstb 0 +\[ 32\]\(sec 2\)\(fl 0x00\)\(ty 0\)\(scl 107\) \(nx 1\) 0x0000008c ignored6 +AUX val 4 prmhsh 0 snhsh 0 typ 1 algn 2 clss 3 stb 0 snstb 0 +\[ 34\]\(sec 0\)\(fl 0x00\)\(ty 0\)\(scl 2\) \(nx 1\) 0x00000000 esym0 +AUX val 0 prmhsh 0 snhsh 0 typ 0 algn 0 clss 0 stb 0 snstb 0 +\[ 36\]\(sec 0\)\(fl 0x00\)\(ty 0\)\(scl 2\) \(nx 1\) 0x00000000 esym1 +AUX val 0 prmhsh 0 snhsh 0 typ 0 algn 0 clss 0 stb 0 snstb 0 + + +Disassembly of section \.text: + +0+0000 <\.crazy_table>: + 0: 00 be ef ed \.long 0xbeefed + 4: 00 be ef ed \.long 0xbeefed + +0+0008 : + 8: 80 63 00 00 l r3,0\(r3\) + c: 80 63 00 04 l r3,4\(r3\) + 10: 80 63 00 04 l r3,4\(r3\) + 14: 80 63 00 00 l r3,0\(r3\) + +0+0018 : + 18: 80 63 00 00 l r3,0\(r3\) + 1c: 80 63 00 04 l r3,4\(r3\) + 20: 80 63 00 04 l r3,4\(r3\) + 24: 80 63 00 08 l r3,8\(r3\) + +0+0028 : + 28: 80 62 00 00 l r3,0\(r2\) + 2a: R_TOC ignored0\+0xf+ff8c + 2c: 80 62 00 04 l r3,4\(r2\) + 2e: R_TOC ignored1\+0xf+ff88 + 30: 80 62 00 08 l r3,8\(r2\) + 32: R_TOC ignored2\+0xf+ff84 + 34: 80 62 00 0c l r3,12\(r2\) + 36: R_TOC ignored3\+0xf+ff80 + 38: 80 62 00 10 l r3,16\(r2\) + 3a: R_TOC ignored4\+0xf+ff7c + 3c: 80 62 00 14 l r3,20\(r2\) + 3e: R_TOC ignored5\+0xf+ff78 + +0+0040 : + 40: 38 60 00 04 lil r3,4 + 44: 38 60 ff fc lil r3,-4 + 48: 38 60 00 04 lil r3,4 + 4c: 38 60 ff fc lil r3,-4 + 50: 38 60 ff fc lil r3,-4 + 54: 38 60 00 04 lil r3,4 + 58: 80 64 00 04 l r3,4\(r4\) + +0+005c : + 5c: 38 60 00 00 lil r3,0 + 60: 38 60 00 04 lil r3,4 + 64: 38 62 00 18 cal r3,24\(r2\) + 66: R_TOC ignored6\+0xf+ff74 +Disassembly of section \.data: + +0+0068 : + 68: de ad be ef stfdu f21,-16657\(r13\) + 6c: ca fe ba be lfd f23,-17730\(r30\) + 70: 00 00 ba ad \.long 0xbaad + +0+0074 : + 74: 00 00 00 68 \.long 0x68 + 74: R_POS \.data\+0xf+ff98 + +0+0078 : + 78: 00 00 00 6c \.long 0x6c + 78: R_POS \.data\+0xf+ff98 + +0+007c : + 7c: 00 00 00 6c \.long 0x6c + 7c: R_POS \.data\+0xf+ff98 + +0+0080 : + 80: 00 00 00 70 \.long 0x70 + 80: R_POS \.data\+0xf+ff98 + +0+0084 : + 84: 00 00 00 00 \.long 0x0 + 84: R_POS esym0 + +0+0088 : + 88: 00 00 00 00 \.long 0x0 + 88: R_POS esym1 + +0+008c : + 8c: 00 00 00 00 \.long 0x0 + 8c: R_POS \.crazy_table Index: test1elf32.d =================================================================== --- test1elf32.d (nonexistent) +++ test1elf32.d (revision 816) @@ -0,0 +1,90 @@ +#objdump: -Drx +#name: PowerPC Test 1, 32 bit elf + +.*: +file format elf32-powerpc +.* +architecture: powerpc:common, flags 0x00000011: +HAS_RELOC, HAS_SYMS +start address 0x00000000 + +Sections: +Idx Name +Size +VMA +LMA +File off +Algn + 0 \.text +00000050 0+0000 0+0000 .* + +CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 1 \.data +00000018 0+0000 0+0000 .* + +CONTENTS, ALLOC, LOAD, RELOC, DATA + 2 \.bss +00000000 0+0000 0+0000 .* + +ALLOC +SYMBOL TABLE: +0+0000 l d \.text 0+0000 (|\.text) +0+0000 l d \.data 0+0000 (|\.data) +0+0000 l d \.bss 0+0000 (|\.bss) +0+0000 l \.data 0+0000 dsym0 +0+0004 l \.data 0+0000 dsym1 +0+0004 l \.data 0+0000 usym0 +0+0008 l \.data 0+0000 usym1 +0+0008 l \.data 0+0000 datpt +0+000c l \.data 0+0000 dat0 +0+0010 l \.data 0+0000 dat1 +0+0014 l \.data 0+0000 dat2 +0+0000 \*UND\* 0+0000 esym0 +0+0000 \*UND\* 0+0000 esym1 +0+0000 \*UND\* 0+0000 jk + + +Disassembly of section \.text: + +0+0000 <\.text>: + 0: 80 63 00 00 lwz r3,0\(r3\) + 2: R_PPC_ADDR16_LO \.data + 4: 80 63 00 04 lwz r3,4\(r3\) + 6: R_PPC_ADDR16_LO \.data\+0x4 + 8: 80 63 00 04 lwz r3,4\(r3\) + a: R_PPC_ADDR16_LO \.data\+0x4 + c: 80 63 00 08 lwz r3,8\(r3\) + e: R_PPC_ADDR16_LO \.data\+0x8 + 10: 80 63 00 00 lwz r3,0\(r3\) + 12: R_PPC_ADDR16_LO esym0 + 14: 80 63 00 00 lwz r3,0\(r3\) + 16: R_PPC_ADDR16_LO esym1 + 18: 38 60 00 04 li r3,4 + 1c: 38 60 ff fc li r3,-4 + 20: 38 60 00 04 li r3,4 + 24: 38 60 ff fc li r3,-4 + 28: 38 60 ff fc li r3,-4 + 2c: 38 60 00 04 li r3,4 + 30: 38 60 00 00 li r3,0 + 32: R_PPC_ADDR16_LO \.data + 34: 38 60 00 00 li r3,0 + 36: R_PPC_ADDR16_HI \.data + 38: 38 60 00 00 li r3,0 + 3a: R_PPC_ADDR16_HA \.data + 3c: 38 60 ff fc li r3,-4 + 40: 38 60 ff ff li r3,-1 + 44: 38 60 00 00 li r3,0 + 48: 80 64 00 04 lwz r3,4\(r4\) + 4c: 80 60 00 00 lwz r3,0\(0\) + 4e: R_PPC_ADDR16_LO \.text +Disassembly of section \.data: + +0+0000 : + 0: de ad be ef stfdu f21,-16657\(r13\) + +0+0004 : + 4: ca fe ba be lfd f23,-17730\(r30\) + +0+0008 : + 8: 00 98 96 80 \.long 0x989680 + 8: R_PPC_REL32 jk\+0x989680 + +0+000c : + c: ff ff ff fc fnmsub f31,f31,f31,f31 + c: R_PPC_REL32 jk\+0xf+fffc + +0+0010 : + 10: 00 00 00 00 \.long 0x0 + 10: R_PPC_REL32 jk + +0+0014 : + 14: 00 00 00 04 \.long 0x4 + 14: R_PPC_REL32 jk\+0x4

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