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- This comparison shows the changes necessary to convert path
/openrisc/trunk/gnu-old/gdb-6.8/include/opcode
- from Rev 816 to Rev 827
- ↔ Reverse comparison
Rev 816 → Rev 827
/i386.h
File deleted
i386.h
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
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Index: h8300.h
===================================================================
--- h8300.h (revision 816)
+++ h8300.h (nonexistent)
@@ -1,1894 +0,0 @@
-/* Opcode table for the H8/300
- Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2001, 2002,
- 2003, 2004, 2005, 2008, 2009
- Free Software Foundation, Inc.
- Written by Steve Chamberlain .
-
- This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
- 02110-1301, USA. */
-
-/* Instructions are stored as a sequence of nibbles.
- If the nibble has value 15 or less than the representation is complete.
- Otherwise, we record what it contains with several flags. */
-
-typedef int op_type;
-
-enum h8_flags
-{
- L_2 = 0x10,
- L_3 = 0x20,
- /* 3 bit constant, zero not accepted. */
- L_3NZ = 0x30,
- L_4 = 0x40,
- L_5 = 0x50,
- L_8 = 0x60,
- L_8U = 0x70,
- L_16 = 0x80,
- L_16U = 0x90,
- L_24 = 0xA0,
- L_32 = 0xB0,
- L_P = 0xC0,
-
- /* Mask to isolate the L_x size bits. */
- SIZE = 0xF0,
-
- REG = 0x0100,
- ABS = 0x0200,
- MEMIND = 0x0300,
- IMM = 0x0400,
- DISP = 0x0500,
- IND = 0x0600,
- POSTINC = 0x0700,
- POSTDEC = 0x0800,
- PREINC = 0x0900,
- PREDEC = 0x0A00,
- PCREL = 0x0B00,
- KBIT = 0x0C00,
- DBIT = 0x0D00,
- CONST_2 = 0x0E00,
- CONST_4 = 0x0F00,
- CONST_8 = 0x1000,
- CONST_16 = 0x1100,
- INDEXB = 0x1200,
- INDEXW = 0x1300,
- INDEXL = 0x1400,
- PCIDXB = 0x1500,
- PCIDXW = 0x1600,
- PCIDXL = 0x1700,
- VECIND = 0x1800,
- LOWREG = 0x1900,
- DATA = 0x2000,
-
- /* Synonyms. */
- INC = POSTINC,
- DEC = PREDEC,
- /* Control Registers. */
- CCR = 0x4000,
- EXR = 0x4100,
- MACH = 0x4200,
- MACL = 0x4300,
- RESERV1 = 0x4400,
- RESERV2 = 0x4500,
- VBR = 0x4600,
- SBR = 0x4700,
- MACREG = 0x4800,
- CCR_EXR = 0x4900,
- VBR_SBR = 0x4A00,
- CC_EX_VB_SB = 0x4B00,
- RESERV3 = 0x4C00,
- RESERV4 = 0x4D00,
- RESERV5 = 0x4E00,
- RESERV6 = 0x4F00,
-
- /* Mask to isolate the addressing mode bits (REG .. PREDEC). */
- MODE = 0x7F00,
-
- CTRL = 0x4000,
-
- NO_SYMBOLS = 0x8000,
- SRC = 0x10000,
- DST = 0x20000,
- OP3 = 0x40000,
- MEMRELAX = 0x80000, /* Move insn which may relax. */
-
- DISPREG = 0x100000,
- IGNORE = 0x200000,
- ABSJMP = 0x400000,
-
- B00 = 0x800000, /* Bit 0 must be low. */
- B01 = 0x1000000, /* Bit 0 must be high. */
- B10 = 0x2000000, /* Bit 1 must be low. */
- B11 = 0x4000000, /* Bit 1 must be high. */
- B20 = 0x8000000, /* Bit 2 must be low. */
- B21 = 0x10000000, /* Bit 2 must be high. */
- B30 = 0x20000000, /* Bit 3 must be low. */
- B31 = 0x40000000, /* Bit 3 must be high. */
- E = 0x80000000, /* End of nibble sequence. */
-
- /* Immediates smaller than 8 bits are always unsigned. */
- IMM3 = IMM | L_3,
- IMM4 = IMM | L_4,
- IMM5 = IMM | L_5,
- IMM3NZ = IMM | L_3NZ,
- IMM2 = IMM | L_2,
-
- IMM8 = IMM | SRC | L_8,
- IMM8U = IMM | SRC | L_8U,
- IMM16 = IMM | SRC | L_16,
- IMM16U = IMM | SRC | L_16U,
- IMM32 = IMM | SRC | L_32,
-
- IMM3NZ_NS = IMM3NZ | NO_SYMBOLS,
- IMM4_NS = IMM4 | NO_SYMBOLS,
- IMM8U_NS = IMM8U | NO_SYMBOLS,
- IMM16U_NS = IMM16U | NO_SYMBOLS,
-
- RD8 = DST | L_8 | REG,
- RD16 = DST | L_16 | REG,
- RD32 = DST | L_32 | REG,
- R3_8 = OP3 | L_8 | REG,
- R3_16 = OP3 | L_16 | REG,
- R3_32 = OP3 | L_32 | REG,
- RS8 = SRC | L_8 | REG,
- RS16 = SRC | L_16 | REG,
- RS32 = SRC | L_32 | REG,
-
- RSP = SRC | L_P | REG,
- RDP = DST | L_P | REG,
-
- PCREL8 = PCREL | L_8,
- PCREL16 = PCREL | L_16,
-
- OP3PCREL8 = OP3 | PCREL | L_8,
- OP3PCREL16 = OP3 | PCREL | L_16,
-
- INDEXB16 = INDEXB | L_16,
- INDEXW16 = INDEXW | L_16,
- INDEXL16 = INDEXL | L_16,
- INDEXB16D = INDEXB | L_16 | DST,
- INDEXW16D = INDEXW | L_16 | DST,
- INDEXL16D = INDEXL | L_16 | DST,
-
- INDEXB32 = INDEXB | L_32,
- INDEXW32 = INDEXW | L_32,
- INDEXL32 = INDEXL | L_32,
- INDEXB32D = INDEXB | L_32 | DST,
- INDEXW32D = INDEXW | L_32 | DST,
- INDEXL32D = INDEXL | L_32 | DST,
-
- DISP2SRC = DISP | L_2 | SRC,
- DISP16SRC = DISP | L_16 | SRC,
- DISP32SRC = DISP | L_32 | SRC,
-
- DISP2DST = DISP | L_2 | DST,
- DISP16DST = DISP | L_16 | DST,
- DISP32DST = DISP | L_32 | DST,
-
- DSTDISPREG = DST | DISPREG,
- SRCDISPREG = SRC | DISPREG,
-
- ABS8SRC = SRC | ABS | L_8,
- ABS16SRC = SRC | ABS | L_16U,
- ABS24SRC = SRC | ABS | L_24,
- ABS32SRC = SRC | ABS | L_32,
-
- ABS8DST = DST | ABS | L_8,
- ABS16DST = DST | ABS | L_16U,
- ABS24DST = DST | ABS | L_24,
- ABS32DST = DST | ABS | L_32,
-
- ABS8OP3 = OP3 | ABS | L_8,
- ABS16OP3 = OP3 | ABS | L_16U,
- ABS24OP3 = OP3 | ABS | L_24,
- ABS32OP3 = OP3 | ABS | L_32,
-
- RDDEC = DST | DEC,
- RSINC = SRC | INC,
- RDINC = DST | INC,
-
- RSPOSTINC = SRC | POSTINC,
- RDPOSTINC = DST | POSTINC,
- RSPREINC = SRC | PREINC,
- RDPREINC = DST | PREINC,
- RSPOSTDEC = SRC | POSTDEC,
- RDPOSTDEC = DST | POSTDEC,
- RSPREDEC = SRC | PREDEC,
- RDPREDEC = DST | PREDEC,
-
- RSIND = SRC | IND,
- RDIND = DST | IND,
- R3_IND = OP3 | IND,
-
-#define MS32 (SRC | L_32 | MACREG)
-#define MD32 (DST | L_32 | MACREG)
-
-#if 1
- OR8 = RS8, /* ??? OR as in One Register. */
- OR16 = RS16,
- OR32 = RS32,
-#else
- OR8 = RD8,
- OR16 = RD16,
- OR32 = RD32
-#endif
-};
-
-enum ctrlreg
-{
- C_CCR = 0,
- C_EXR = 1,
- C_MACH = 2,
- C_MACL = 3,
- C_VBR = 6,
- C_SBR = 7
-};
-
-enum {MAX_CODE_NIBBLES = 33};
-
-struct code
-{
- op_type nib[MAX_CODE_NIBBLES];
-};
-
-struct arg
-{
- op_type nib[3];
-};
-
-/* Availability of instructions on processor models. */
-enum h8_model
-{
- AV_H8,
- AV_H8H,
- AV_H8S,
- AV_H8SX
-};
-
-struct h8_opcode
-{
- int how;
- enum h8_model available;
- int time;
- char *name;
- struct arg args;
- struct code data;
-};
-
-#ifdef DEFINE_TABLE
-
-#define DATA2 DATA, DATA
-#define DATA3 DATA, DATA, DATA
-#define DATA5 DATA, DATA, DATA, DATA, DATA
-#define DATA7 DATA, DATA, DATA, DATA, DATA, DATA, DATA
-
-#define IMM8LIST IMM8, DATA
-#define IMM16LIST IMM16, DATA3
-#define IMM16ULIST IMM16U, DATA3
-#define IMM24LIST IMM24, DATA5
-#define IMM32LIST IMM32, DATA7
-
-#define DISP16LIST DISP | L_16, DATA3
-#define DISP24LIST DISP | L_24, DATA5
-#define DISP32LIST DISP | L_32, DATA7
-
-#define ABS8LIST ABS | L_8, DATA
-#define ABS16LIST ABS | L_16U, DATA3
-#define ABS24LIST ABS | L_24, DATA5
-#define ABS32LIST ABS | L_32, DATA7
-
-#define DSTABS8LIST DST | ABS | L_8, DATA
-#define DSTABS16LIST DST | ABS | L_16U, DATA3
-#define DSTABS24LIST DST | ABS | L_24, DATA5
-#define DSTABS32LIST DST | ABS | L_32, DATA7
-
-#define OP3ABS8LIST OP3 | ABS | L_8, DATA
-#define OP3ABS16LIST OP3 | ABS | L_16, DATA3
-#define OP3ABS24LIST OP3 | ABS | L_24, DATA5
-#define OP3ABS32LIST OP3 | ABS | L_32, DATA7
-
-#define DSTDISP16LIST DST | DISP | L_16, DATA3
-#define DSTDISP24LIST DST | DISP | L_24, DATA5
-#define DSTDISP32LIST DST | DISP | L_32, DATA7
-
-#define A16LIST L_16, DATA3
-#define A24LIST L_24, DATA5
-#define A32LIST L_32, DATA7
-
-/* Extended Operand Prefixes: */
-
-#define PREFIX_010 0x0, 0x1, 0x0
-#define PREFIX_015 0x0, 0x1, 0x5
-#define PREFIX_017 0x0, 0x1, 0x7
-
-#define PREFIX_0100 0x0, 0x1, 0x0, 0x0
-#define PREFIX_010_D2 0x0, 0x1, 0x0, B30 | B21 | DISP2SRC
-#define PREFIX_0101 0x0, 0x1, 0x0, 0x1
-#define PREFIX_0102 0x0, 0x1, 0x0, 0x2
-#define PREFIX_0103 0x0, 0x1, 0x0, 0x3
-#define PREFIX_0104 0x0, 0x1, 0x0, 0x4
-#define PREFIX_0105 0x0, 0x1, 0x0, 0x5
-#define PREFIX_0106 0x0, 0x1, 0x0, 0x6
-#define PREFIX_0107 0x0, 0x1, 0x0, 0x7
-#define PREFIX_0108 0x0, 0x1, 0x0, 0x8
-#define PREFIX_0109 0x0, 0x1, 0x0, 0x9
-#define PREFIX_010A 0x0, 0x1, 0x0, 0xa
-#define PREFIX_010D 0x0, 0x1, 0x0, 0xd
-#define PREFIX_010E 0x0, 0x1, 0x0, 0xe
-
-#define PREFIX_0150 0x0, 0x1, 0x5, 0x0
-#define PREFIX_015_D2 0x0, 0x1, 0x5, B30 | B21 | DISP2SRC
-#define PREFIX_0151 0x0, 0x1, 0x5, 0x1
-#define PREFIX_0152 0x0, 0x1, 0x5, 0x2
-#define PREFIX_0153 0x0, 0x1, 0x5, 0x3
-#define PREFIX_0154 0x0, 0x1, 0x5, 0x4
-#define PREFIX_0155 0x0, 0x1, 0x5, 0x5
-#define PREFIX_0156 0x0, 0x1, 0x5, 0x6
-#define PREFIX_0157 0x0, 0x1, 0x5, 0x7
-#define PREFIX_0158 0x0, 0x1, 0x5, 0x8
-#define PREFIX_0159 0x0, 0x1, 0x5, 0x9
-#define PREFIX_015A 0x0, 0x1, 0x5, 0xa
-#define PREFIX_015D 0x0, 0x1, 0x5, 0xd
-#define PREFIX_015E 0x0, 0x1, 0x5, 0xe
-#define PREFIX_015F 0x0, 0x1, 0x5, 0xf
-
-#define PREFIX_0170 0x0, 0x1, 0x7, 0x0
-#define PREFIX_017_D2S 0x0, 0x1, 0x7, B30 | B21 | DISP2SRC
-#define PREFIX_017_D2D 0x0, 0x1, 0x7, B30 | B21 | DISP2DST
-#define PREFIX_0171 0x0, 0x1, 0x7, 0x1
-#define PREFIX_0172 0x0, 0x1, 0x7, 0x2
-#define PREFIX_0173 0x0, 0x1, 0x7, 0x3
-#define PREFIX_0174 0x0, 0x1, 0x7, 0x4
-#define PREFIX_0175 0x0, 0x1, 0x7, 0x5
-#define PREFIX_0176 0x0, 0x1, 0x7, 0x6
-#define PREFIX_0177 0x0, 0x1, 0x7, 0x7
-#define PREFIX_0178 0x0, 0x1, 0x7, 0x8
-#define PREFIX_0179 0x0, 0x1, 0x7, 0x9
-#define PREFIX_017A 0x0, 0x1, 0x7, 0xa
-#define PREFIX_017D 0x0, 0x1, 0x7, 0xd
-#define PREFIX_017E 0x0, 0x1, 0x7, 0xe
-#define PREFIX_017F 0x0, 0x1, 0x7, 0xf
-
-#define PREFIX_6A15 0x6, 0xa, 0x1, 0x5
-#define PREFIX_6A35 0x6, 0xa, 0x3, 0x5
-#define PREFIX_6B15 0x6, 0xb, 0x1, 0x5
-#define PREFIX_6B35 0x6, 0xb, 0x3, 0x5
-
-#define PREFIX_78R4 0x7, 0x8, B31 | DISPREG, 0x4
-#define PREFIX_78R5 0x7, 0x8, B31 | DISPREG, 0x5
-#define PREFIX_78R6 0x7, 0x8, B31 | DISPREG, 0x6
-#define PREFIX_78R7 0x7, 0x8, B31 | DISPREG, 0x7
-
-#define PREFIX_78R4W 0x7, 0x8, B30 | DISPREG, 0x4
-#define PREFIX_78R5W 0x7, 0x8, B30 | DISPREG, 0x5
-#define PREFIX_78R6W 0x7, 0x8, B30 | DISPREG, 0x6
-#define PREFIX_78R7W 0x7, 0x8, B30 | DISPREG, 0x7
-
-#define PREFIX_78R4WD 0x7, 0x8, B30 | DSTDISPREG, 0x4
-#define PREFIX_78R5WD 0x7, 0x8, B30 | DSTDISPREG, 0x5
-#define PREFIX_78R6WD 0x7, 0x8, B30 | DSTDISPREG, 0x6
-#define PREFIX_78R7WD 0x7, 0x8, B30 | DSTDISPREG, 0x7
-
-#define PREFIX_7974 0x7, 0x9, 0x7, 0x4
-#define PREFIX_7A74 0x7, 0xa, 0x7, 0x4
-#define PREFIX_7A7C 0x7, 0xa, 0x7, 0xc
-
-
-/* Source standard fragment: */
-#define FROM_IND 0, RSIND
-#define FROM_POSTINC 8, RSPOSTINC
-#define FROM_POSTDEC 10, RSPOSTDEC
-#define FROM_PREINC 9, RSPREINC
-#define FROM_PREDEC 11, RSPREDEC
-#define FROM_DISP2 B30 | B20 | DISP2SRC, DISPREG
-#define FROM_DISP16 12, B30 | DISPREG
-#define FROM_DISP32 12, B31 | DISPREG
-#define FROM_DISP16B 13, B30 | DISPREG
-#define FROM_DISP16W 14, B30 | DISPREG
-#define FROM_DISP16L 15, B30 | DISPREG
-#define FROM_DISP32B 13, B31 | DISPREG
-#define FROM_DISP32W 14, B31 | DISPREG
-#define FROM_DISP32L 15, B31 | DISPREG
-#define FROM_ABS16 4, B30 | IGNORE
-#define FROM_ABS32 4, B31 | IGNORE
-
-/* Destination standard fragment: */
-#define TO_IND 0, RDIND
-#define TO_IND_MOV 0, RDIND | B30
-#define TO_POSTINC 8, RDPOSTINC
-#define TO_POSTINC_MOV 8, RDPOSTINC | B30
-#define TO_POSTDEC 10, RDPOSTDEC
-#define TO_POSTDEC_MOV 10, RDPOSTDEC | B30
-#define TO_PREINC 9, RDPREINC
-#define TO_PREINC_MOV 9, RDPREINC | B30
-#define TO_PREDEC 11, RDPREDEC
-#define TO_PREDEC_MOV 11, RDPREDEC | B30
-#define TO_DISP2 B30 | B20 | DISP2DST, DSTDISPREG
-#define TO_DISP2_MOV B30 | B20 | DISP2DST, DSTDISPREG | B30
-#define TO_DISP16 12, B30 | DSTDISPREG
-#define TO_DISP32 12, B31 | DSTDISPREG
-#define TO_DISP16B 13, B30 | DSTDISPREG
-#define TO_DISP16W 14, B30 | DSTDISPREG
-#define TO_DISP16L 15, B30 | DSTDISPREG
-#define TO_DISP32B 13, B31 | DSTDISPREG
-#define TO_DISP32W 14, B31 | DSTDISPREG
-#define TO_DISP32L 15, B31 | DSTDISPREG
-#define TO_ABS16 4, B30 | IGNORE
-#define TO_ABS32 4, B31 | IGNORE
-
-/* Source fragment for three-word instruction: */
-#define TFROM_IND 6, 9, B30 | RSIND, 12
-#define TFROM_DISP2 6, 9, B30 | DISPREG, 12
-#define TFROM_ABS16 6, 11, B30 | B20 | B10 | IGNORE, 12, ABS16LIST
-#define TFROM_ABS32 6, 11, B30 | B20 | B11 | IGNORE, 12, ABS32LIST
-#define TFROM_POSTINC 6, 13, B30 | RSPOSTINC, 12
-#define TFROM_PREINC 6, 13, B30 | RSPREINC, 12
-#define TFROM_POSTDEC 6, 13, B30 | RSPOSTDEC, 12
-#define TFROM_PREDEC 6, 13, B30 | RSPREDEC, 12
-#define TFROM_DISP16 6, 15, B30 | DISPREG, 12, DISP16LIST
-#define TFROM_DISP32 6, 11, 2, 12, DISP32LIST
-#define TFROM_DISP16B 6, 15, B30 | DISPREG, 12, DISP16LIST
-#define TFROM_DISP16W 6, 15, B30 | DISPREG, 12, DISP16LIST
-#define TFROM_DISP16L 6, 15, B30 | DISPREG, 12, DISP16LIST
-#define TFROM_DISP32B 6, 11, 2, 12, DISP32LIST
-#define TFROM_DISP32W 6, 11, 2, 12, DISP32LIST
-#define TFROM_DISP32L 6, 11, 2, 12, DISP32LIST
-#define TFROM_ABS16W 6, 11, 1, 12, ABS16LIST
-#define TFROM_ABS32W 6, 11, 3, 12, ABS32LIST
-
-/* Source fragment for three-word instruction: */
-#define TFROM_IND_B 6, 8, B30 | RSIND, 12
-#define TFROM_ABS16_B 6, 10, B30 | B20 | B10 | IGNORE, 12, ABS16LIST
-#define TFROM_ABS32_B 6, 10, B30 | B20 | B11 | IGNORE, 12, ABS32LIST
-
-#define TFROM_DISP2_B 6, 8, B30 | DISPREG, 12
-#define TFROM_POSTINC_B 6, 12, B30 | RSPOSTINC, 12
-#define TFROM_PREINC_B 6, 12, B30 | RSPREINC, 12
-#define TFROM_POSTDEC_B 6, 12, B30 | RSPOSTDEC, 12
-#define TFROM_PREDEC_B 6, 12, B30 | RSPREDEC, 12
-#define TFROM_DISP16_B 6, 14, B30 | DISPREG, 12, DISP16LIST
-#define TFROM_DISP32_B 6, 10, 2, 12, DISP32LIST
-#define TFROM_DISP16B_B 6, 14, B30 | DISPREG, 12, DISP16LIST
-#define TFROM_DISP16W_B 6, 14, B30 | DISPREG, 12, DISP16LIST
-#define TFROM_DISP16L_B 6, 14, B30 | DISPREG, 12, DISP16LIST
-#define TFROM_DISP32B_B 6, 10, 2, 12, DISP32LIST
-#define TFROM_DISP32W_B 6, 10, 2, 12, DISP32LIST
-#define TFROM_DISP32L_B 6, 10, 2, 12, DISP32LIST
-
-#define TFROM_ABS16W_B 6, 10, 1, 12, ABS16LIST
-#define TFROM_ABS32W_B 6, 10, 3, 12, ABS32LIST
-
-/* Extended Operand Class Expanders: */
-
-#define MOVFROM_STD(CODE, PREFIX, NAME, SRC, SRC_INFIX) \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, SRC_INFIX, TO_IND_MOV, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, SRC_INFIX, TO_PREINC_MOV, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, SRC_INFIX, TO_PREDEC_MOV, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP2_MOV, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP16, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP32, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16B, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16W, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16L, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32B, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32W, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32L, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS16, DSTABS16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS32, DSTABS32LIST, E}}}
-
-#define MOVFROM_AD(CODE, PREFIX, NAME, SRC, SRC_INFIX, SRC_SUFFIX) \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, SRC_INFIX, TO_IND_MOV, SRC_SUFFIX, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, SRC_SUFFIX, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, SRC_SUFFIX, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, SRC_INFIX, TO_PREINC_MOV, SRC_SUFFIX, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, SRC_INFIX, TO_PREDEC_MOV, SRC_SUFFIX, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP2_MOV, SRC_SUFFIX, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP16, SRC_SUFFIX, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP32, SRC_SUFFIX, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16B, SRC_SUFFIX, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16W, SRC_SUFFIX, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16L, SRC_SUFFIX, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32B, SRC_SUFFIX, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32W, SRC_SUFFIX, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32L, SRC_SUFFIX, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS16, SRC_SUFFIX, DSTABS16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS32, SRC_SUFFIX, DSTABS32LIST, E}}}
-
-#define MOVFROM_IMM8(CODE, PREFIX, NAME, SRC) \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, 0, RDIND, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, 8, RDPOSTINC, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, 10, RDPOSTDEC, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, 9, RDPREINC, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, 11, RDPREDEC, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, B30 | B20 | DISP2DST, DSTDISPREG, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, 12, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, 12, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, 13, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, 14, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, 15, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, 13, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, 14, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, 15, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, 4, B30 | IGNORE, IMM8LIST, DSTABS16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, 4, B31 | IGNORE, IMM8LIST, DSTABS32LIST, E}}}
-
-#define MOVFROM_IMM(CODE, PREFIX, NAME, SRC, LIST) \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, LIST, 0, RDIND, DATA2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, LIST, 8, RDPOSTINC, DATA2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, LIST, 10, RDPOSTDEC, DATA2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, LIST, 9, RDPREINC, DATA2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, LIST, 11, RDPREDEC, DATA2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, LIST, B30 | B20 | DISP2DST, DSTDISPREG, DATA2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, LIST, 12, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, LIST, 12, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, LIST, 13, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, LIST, 14, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, LIST, 15, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, LIST, 13, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, LIST, 14, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, LIST, 15, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, LIST, 4, B30 | IGNORE, DATA2, DSTABS16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, LIST, 4, B31 | IGNORE, DATA2, DSTABS32LIST, E}}}
-
-#define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
- {CODE, AV_H8, 4, NAME, {{SRC, RDIND, E}}, {{ 6, OP1, B31 | RDIND, SRC, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, 3, 6, OP3, B31 | RDPOSTINC, SRC, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, 1, 6, OP3, B31 | RDPOSTDEC, SRC, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, 2, 6, OP3, B31 | RDPREINC, SRC, E}}}, \
- {CODE, AV_H8, 6, NAME, {{SRC, RDPREDEC, E}}, {{ 6, OP3, B31 | RDPREDEC, SRC, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, B30 | B20 | DISP2DST, 6, OP1, B31 | DSTDISPREG, SRC, E}}}, \
- {CODE, AV_H8, 6, NAME, {{SRC, DISP16DST, E}}, {{ 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8, 6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, 1, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, 2, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, 3, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8, 4, NAME, {{SRC, ABS16DST, E}}, {{ 6, OP2, 8, SRC, RELAX16 | DSTABS16LIST, E}}}, \
- {CODE, AV_H8, 6, NAME, {{SRC, ABS32DST, E}}, {{ 6, OP2, 10, SRC, MEMRELAX | DSTABS32LIST, E}}}
-
-#define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
- {CODE, AV_H8, 4, NAME, {{RSIND, DST, E}}, {{ 6, OP1, B30 | RSIND, DST, E}}}, \
- {CODE, AV_H8, 6, NAME, {{RSPOSTINC, DST, E}}, {{ 6, OP3, B30 | RSPOSTINC, DST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, 2, 6, OP3, B30 | RSPOSTDEC, DST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSPREINC, DST, E}}, {{PREFIX, 1, 6, OP3, B30 | RSPREINC, DST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, DST, E}}, {{PREFIX, 3, 6, OP3, B30 | RSPREDEC, DST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, DST, E}}, {{PREFIX, B30 | B20 | DISP2SRC, 6, OP1, B30 | DISPREG, DST, E}}}, \
- {CODE, AV_H8, 6, NAME, {{DISP16SRC, DST, E}}, {{ 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \
- {CODE, AV_H8, 6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0, 6, OP2, 2, DST, DISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXB16, DST, E}}, {{PREFIX, 1, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXW16, DST, E}}, {{PREFIX, 2, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXL16, DST, E}}, {{PREFIX, 3, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{7, 8, B30 | DISPREG, 1, 6, OP2, 2, DST, DISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXW32, DST, E}}, {{7, 8, B30 | DISPREG, 2, 6, OP2, 2, DST, DISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXL32, DST, E}}, {{7, 8, B30 | DISPREG, 3, 6, OP2, 2, DST, DISP32LIST, E}}}, \
- {CODE, AV_H8, 4, NAME, {{ABS16SRC, DST, E}}, {{ 6, OP2, 0, DST, RELAX16 | ABS16LIST, E}}}, \
- {CODE, AV_H8, 6, NAME, {{ABS32SRC, DST, E}}, {{ 6, OP2, 2, DST, MEMRELAX | ABS32LIST, E}}}
-
-/* Expansion macros for two-word (plus data) instructions. */
-
-/* Expansion from one source to "standard" destinations. */
-#define EXPAND2_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, NIB1, NIB2) \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, NIB1, NIB2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, NIB1, NIB2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, NIB1, NIB2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, NIB1, NIB2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, NIB1, NIB2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, NIB1, NIB2, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, NIB1, NIB2, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}}
-
-/* Expansion from one destination to "standard" sources. */
-#define EXPAND2_STD_DST(CODE, WEIGHT, NAME, DST, PREFIX, NIB1, NIB2) \
- {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, DST, E}}, {{PREFIX, FROM_POSTINC, NIB1, NIB2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, FROM_POSTDEC, NIB1, NIB2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSPREINC, DST, E}}, {{PREFIX, FROM_PREINC, NIB1, NIB2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, DST, E}}, {{PREFIX, FROM_PREDEC, NIB1, NIB2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, DST, E}}, {{PREFIX, FROM_DISP2, NIB1, NIB2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, DST, E}}, {{PREFIX, FROM_DISP16, NIB1, NIB2, DISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, DST, E}}, {{PREFIX, FROM_DISP32, NIB1, NIB2, DISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXB16, DST, E}}, {{PREFIX, FROM_DISP16B, NIB1, NIB2, DISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXW16, DST, E}}, {{PREFIX, FROM_DISP16W, NIB1, NIB2, DISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXL16, DST, E}}, {{PREFIX, FROM_DISP16L, NIB1, NIB2, DISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{PREFIX, FROM_DISP32B, NIB1, NIB2, DISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXW32, DST, E}}, {{PREFIX, FROM_DISP32W, NIB1, NIB2, DISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXL32, DST, E}}, {{PREFIX, FROM_DISP32L, NIB1, NIB2, DISP32LIST, E}}}
-
-/* Expansion from immediate source to "standard" destinations. */
-#define EXPAND2_STD_IMM(CODE, WEIGHT, NAME, SRC, PREFIX, OPCODE, IGN, IMMLIST) \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, OPCODE, IGN, IMMLIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, OPCODE, IGN, IMMLIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, OPCODE, IGN, IMMLIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, OPCODE, IGN, IMMLIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, OPCODE, IGN, IMMLIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}
-
-/* Expansion from abs/disp source to "standard" destinations. */
-#define EXPAND2_STD_ABSDISP(CODE, WEIGHT, NAME, SRC, PREFIX, DSTLIST, NIB1, NIB2) \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, DSTLIST, TO_POSTINC, NIB1, NIB2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, DSTLIST, TO_POSTDEC, NIB1, NIB2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, DSTLIST, TO_PREINC, NIB1, NIB2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, DSTLIST, TO_PREDEC, NIB1, NIB2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, DSTLIST, TO_DISP2, NIB1, NIB2, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, DSTLIST, TO_DISP16, NIB1, NIB2, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, DSTLIST, TO_DISP32, NIB1, NIB2, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, DSTLIST, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, DSTLIST, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, DSTLIST, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, DSTLIST, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, DSTLIST, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, DSTLIST, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}}
-
-/* Expansion from ind source to "standard" destinations. */
-#define EXPAND2_STD_IND(CODE, WEIGHT, NAME, OPCODE, BIT) \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTINC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTINC, OPCODE, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTDEC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTDEC, OPCODE, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREINC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREINC, OPCODE, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREDEC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREDEC, OPCODE, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP2DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP2, OPCODE, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP16DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP32DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16B, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16W, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16L, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32B, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32W, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32L, OPCODE, IGNORE, DSTDISP32LIST, E}}}
-
-/* Expansion macros for three word (plus data) instructions. */
-
-#define EXPAND3_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE) \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX, 8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, INFIX, 9, RDPREINC, OPCODE, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, INFIX, 11, RDPREDEC, OPCODE, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}
-
-#define EXPAND3_L_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE) \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, INFIX, 0, RDIND, OPCODE, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX, 8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, INFIX, 9, RDPREINC, OPCODE, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, INFIX, 11, RDPREDEC, OPCODE, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, INFIX, 4, B30 | IGNORE, OPCODE, B30 | IGNORE, DSTABS16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, INFIX, 4, B31 | IGNORE, OPCODE, B30 | IGNORE, DSTABS32LIST, E}}}
-
-
-#define EXPAND_STD_MATRIX_L(CODE, NAME, OPCODE) \
- EXPAND3_L_SRC (CODE, 6, NAME, RSIND, PREFIX_0104, TFROM_IND, OPCODE), \
- EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTINC, PREFIX_0104, TFROM_POSTINC, OPCODE), \
- EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTDEC, PREFIX_0106, TFROM_POSTDEC, OPCODE), \
- EXPAND3_L_SRC (CODE, 6, NAME, RSPREINC, PREFIX_0105, TFROM_PREINC, OPCODE), \
- EXPAND3_L_SRC (CODE, 6, NAME, RSPREDEC, PREFIX_0107, TFROM_PREDEC, OPCODE), \
- EXPAND3_L_SRC (CODE, 6, NAME, DISP2SRC, PREFIX_010_D2, TFROM_DISP2, OPCODE), \
- EXPAND3_L_SRC (CODE, 6, NAME, DISP16SRC, PREFIX_0104, TFROM_DISP16, OPCODE), \
- EXPAND3_L_SRC (CODE, 6, NAME, DISP32SRC, PREFIX_78R4, TFROM_DISP32, OPCODE), \
- EXPAND3_L_SRC (CODE, 6, NAME, INDEXB16, PREFIX_0105, TFROM_DISP16B, OPCODE), \
- EXPAND3_L_SRC (CODE, 6, NAME, INDEXW16, PREFIX_0106, TFROM_DISP16W, OPCODE), \
- EXPAND3_L_SRC (CODE, 6, NAME, INDEXL16, PREFIX_0107, TFROM_DISP16L, OPCODE), \
- EXPAND3_L_SRC (CODE, 6, NAME, INDEXB32, PREFIX_78R5, TFROM_DISP32B, OPCODE), \
- EXPAND3_L_SRC (CODE, 6, NAME, INDEXW32, PREFIX_78R6, TFROM_DISP32W, OPCODE), \
- EXPAND3_L_SRC (CODE, 6, NAME, INDEXL32, PREFIX_78R7, TFROM_DISP32L, OPCODE), \
- EXPAND3_L_SRC (CODE, 6, NAME, ABS16SRC, PREFIX_0104, TFROM_ABS16, OPCODE), \
- EXPAND3_L_SRC (CODE, 6, NAME, ABS32SRC, PREFIX_0104, TFROM_ABS32, OPCODE)
-
-
-#define EXPAND_STD_MATRIX_W(CODE, NAME, OPCODE) \
- EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0154, TFROM_POSTINC, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0156, TFROM_POSTDEC, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC, PREFIX_0155, TFROM_PREINC, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC, PREFIX_0157, TFROM_PREDEC, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC, PREFIX_015_D2, TFROM_DISP2, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0154, TFROM_DISP16, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W, TFROM_DISP32, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16, PREFIX_0155, TFROM_DISP16B, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16, PREFIX_0156, TFROM_DISP16W, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16, PREFIX_0157, TFROM_DISP16L, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32, PREFIX_78R5W, TFROM_DISP32B, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32, PREFIX_78R6W, TFROM_DISP32W, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32, PREFIX_78R7W, TFROM_DISP32L, OPCODE)
-
-#define EXPAND_STD_MATRIX_B(CODE, NAME, OPCODE) \
- EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0174, TFROM_POSTINC_B, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0176, TFROM_POSTDEC_B, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC, PREFIX_0175, TFROM_PREINC_B, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC, PREFIX_0177, TFROM_PREDEC_B, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC, PREFIX_017_D2S, TFROM_DISP2_B, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0174, TFROM_DISP16_B, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W, TFROM_DISP32_B, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16, PREFIX_0175, TFROM_DISP16B_B, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16, PREFIX_0176, TFROM_DISP16W_B, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16, PREFIX_0177, TFROM_DISP16L_B, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32, PREFIX_78R5W, TFROM_DISP32B_B, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32, PREFIX_78R6W, TFROM_DISP32W_B, OPCODE), \
- EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32, PREFIX_78R7W, TFROM_DISP32L_B, OPCODE)
-
-
-/* Use the expansion macros to fill out the opcode table. */
-
-#define EXPAND_FROM_REG8(CODE, NAME, OP1, OP2, OP3) \
- {CODE, AV_H8SX, 0, NAME, {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, OP1, OP2, RS8, IGNORE, E}}}, \
- EXPAND2_STD_SRC (CODE, 2, NAME, RS8, PREFIX_0179, OP3, RS8), \
- {CODE, AV_H8SX, 0, NAME, {{RS8, ABS8DST, E}}, {{0x7, 0xf, DSTABS8LIST, OP1, OP2, RS8, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RS8, ABS16DST, E}}, {{0x6, 0xa, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS8, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RS8, ABS32DST, E}}, {{0x6, 0xa, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS8, IGNORE, E}}}
-
-#define EXPAND_TO_REG8(CODE, NAME, OP1, OP2, OP3) \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, OP1, OP2, IGNORE, RD8, E}}}, \
- EXPAND2_STD_DST (CODE, 2, NAME, RD8, PREFIX_017A, OP3, RD8), \
- {CODE, AV_H8SX, 0, NAME, {{ABS8SRC, RD8, E}}, {{0x7, 0xe, ABS8LIST, OP1, OP2, IGNORE, RD8, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD8, E}}, {{0x6, 0xa, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD8, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD8, E}}, {{0x6, 0xa, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD8, E}}}
-
-#define EXPAND_FROM_IND8(CODE, NAME, OPCODE) \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_IND, OPCODE, IGNORE, E}}}, \
- EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B30), \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
-
-#define EXPAND_FROM_ABS16_B(CODE, NAME, OPCODE) \
- {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND, E}}, {{PREFIX_6A15, ABS16LIST, TO_IND, OPCODE, IGNORE, E}}}, \
- EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6A15, ABS16LIST, OPCODE, IGNORE), \
- {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
-
-#define EXPAND_FROM_ABS32_B(CODE, NAME, OPCODE) \
- {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND, E}}, {{PREFIX_6A35, ABS32LIST, TO_IND, OPCODE, IGNORE, E}}}, \
- EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6A35, ABS32LIST, OPCODE, IGNORE), \
- {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
-
-#define EXPAND_FROM_IMM16_W(CODE, NAME, OPCODE) \
- {CODE, AV_H8SX, 0, NAME, {{IMM16, RDIND, E}}, {{PREFIX_015E, TO_IND, OPCODE, IGNORE, IMM16LIST, E}}}, \
- EXPAND2_STD_IMM (CODE, 2, NAME, IMM16, PREFIX_015E, OPCODE, IGNORE, IMM16LIST), \
- {CODE, AV_H8SX, 0, NAME, {{IMM16, ABS16DST, E}}, {{PREFIX_015E, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, IMM16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{IMM16, ABS32DST, E}}, {{PREFIX_015E, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, IMM16LIST, E}}}
-
-#define EXPAND_FROM_REG16(CODE, NAME, OP1, OP2, OP3) \
- {CODE, AV_H8, 2, NAME, {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, OP1, OP2, RS16, IGNORE, E}}}, \
- EXPAND2_STD_SRC (CODE, 2, NAME, RS16, PREFIX_0159, OP3, RS16), \
- {CODE, AV_H8SX, 0, NAME, {{RS16, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS16, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RS16, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS16, IGNORE, E}}}
-
-#define EXPAND_TO_REG16(CODE, NAME, OP1, OP2, OP3) \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, IGNORE, OP1, OP2, IGNORE, RD16, E}}}, \
- EXPAND2_STD_DST (CODE, 2, NAME, RD16, PREFIX_015A, OP3, RD16), \
- {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD16, E}}, {{0x6, 0xb, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD16, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD16, E}}, {{0x6, 0xb, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD16, E}}}
-
-#define EXPAND_FROM_IND16(CODE, NAME, OPCODE) \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_IND, OPCODE, IGNORE, E}}}, \
- EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B31), \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
-
-#define EXPAND_FROM_ABS16_W(CODE, NAME, OPCODE) \
- {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND, E}}, {{PREFIX_6B15, ABS16LIST, TO_IND, OPCODE, IGNORE, E}}}, \
- EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6B15, ABS16LIST, OPCODE, IGNORE), \
- {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
-
-#define EXPAND_FROM_ABS32_W(CODE, NAME, OPCODE) \
- {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND, E}}, {{PREFIX_6B35, ABS32LIST, TO_IND, OPCODE, IGNORE, E}}}, \
- EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6B35, ABS32LIST, OPCODE, IGNORE), \
- {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
-
-#define EXPAND_FROM_IMM16_L(CODE, NAME, OPCODE) \
- {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RDIND, E}}, {{PREFIX_010E, TO_IND, OPCODE, B30 | IGNORE, IMM16ULIST, E}}}, \
- EXPAND2_STD_IMM (CODE, 2, NAME, IMM16U_NS, PREFIX_010E, OPCODE, B30 | IGNORE, IMM16ULIST), \
- {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B30 | IGNORE, DSTABS16LIST, IMM16ULIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B30 | IGNORE, DSTABS32LIST, IMM16ULIST, E}}}
-
-#define EXPAND_FROM_IMM32_L(CODE, NAME, OPCODE) \
- {CODE, AV_H8SX, 0, NAME, {{IMM32, RDIND, E}}, {{PREFIX_010E, TO_IND, OPCODE, B31 | IGNORE, IMM32LIST, E}}}, \
- EXPAND2_STD_IMM (CODE, 2, NAME, IMM32, PREFIX_010E, OPCODE, B31 | IGNORE, IMM32LIST), \
- {CODE, AV_H8SX, 0, NAME, {{IMM32, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B31 | IGNORE, DSTABS16LIST, IMM32LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{IMM32, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B31 | IGNORE, DSTABS32LIST, IMM32LIST, E}}}
-
-#define EXPAND_FROM_REG32(CODE, NAME, OPCODE) \
- {CODE, AV_H8SX, 0, NAME, {{RS32, RDIND, E}}, {{PREFIX_0109, TO_IND, OPCODE, B30 | RS32, E}}}, \
- EXPAND2_STD_SRC (CODE, 2, NAME, RS32, PREFIX_0109, OPCODE, B30 | RS32), \
- {CODE, AV_H8SX, 0, NAME, {{RS32, ABS16DST, E}}, {{PREFIX_0109, TO_ABS16, OPCODE, B30 | RS32, DSTABS16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RS32, ABS32DST, E}}, {{PREFIX_0109, TO_ABS32, OPCODE, B30 | RS32, DSTABS32LIST, E}}}
-
-#define EXPAND_TO_REG32(CODE, NAME, OPCODE) \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, RD32, E}}, {{PREFIX_010A, FROM_IND, OPCODE, B30 | RD32, E}}}, \
- EXPAND2_STD_DST (CODE, 2, NAME, RD32, PREFIX_010A, OPCODE, B30 | RD32), \
- {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS16, OPCODE, B30 | RD32, ABS16LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS32, OPCODE, B30 | RD32, ABS32LIST, E}}}
-
-
-#define EXPAND_TWOOP_B(CODE, NAME, OP1, OP2, OP3, OP4, BIT) \
- {CODE, AV_H8SX, 0, NAME, {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTINC, E}}, {{PREFIX_0174, 0x6, 0xc, B30 | RDPOSTINC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREINC, E}}, {{PREFIX_0175, 0x6, 0xc, B30 | RDPREINC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREDEC, E}}, {{PREFIX_0177, 0x6, 0xc, B30 | RDPREDEC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP2DST, E}}, {{PREFIX_017_D2D, 0x6, 0x8, B30 | DSTDISPREG, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP16DST, E}}, {{PREFIX_0174, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP32DST, E}}, {{PREFIX_78R4WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB16D, E}}, {{PREFIX_0175, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW16D, E}}, {{PREFIX_0176, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL16D, E}}, {{PREFIX_0177, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB32D, E}}, {{PREFIX_78R5WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW32D, E}}, {{PREFIX_78R6WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL32D, E}}, {{PREFIX_78R7WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS8DST, E}}, {{0x7, 0xf, DSTABS8LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS16DST, E}}, {{0x6, 0xa, 0x1, B31 | B20 | IGNORE, DSTABS16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS32DST, E}}, {{0x6, 0xa, 0x3, B31 | B20 | IGNORE, DSTABS32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
- {CODE, AV_H8, 2, NAME, {{RS8, RD8, E}}, {{OP2, OP3, RS8, RD8, E}}}, \
- EXPAND_FROM_REG8 (CODE, NAME, OP2, OP3, OP4), \
- EXPAND_TO_REG8 (CODE, NAME, OP2, OP3, OP4), \
- EXPAND_FROM_IND8 (CODE, NAME, OP4), \
- EXPAND_STD_MATRIX_B (CODE, NAME, OP4), \
- EXPAND_FROM_ABS16_B (CODE, NAME, OP4), \
- EXPAND_FROM_ABS32_B (CODE, NAME, OP4)
-
-#define EXPAND_TWOOP_W(CODE, NAME, OP1, OP2, OP3) \
- {CODE, AV_H8H, 6, NAME, {{IMM16, RD16, E}}, {{0x7, 0x9, OP3, RD16, IMM16LIST, E}}}, \
- EXPAND_FROM_IMM16_W (CODE, NAME, OP3), \
- EXPAND_FROM_REG16 (CODE, NAME, OP1, OP2, OP3), \
- EXPAND_TO_REG16 (CODE, NAME, OP1, OP2, OP3), \
- EXPAND_FROM_IND16 (CODE, NAME, OP3), \
- EXPAND_STD_MATRIX_W (CODE, NAME, OP3), \
- EXPAND_FROM_ABS16_W (CODE, NAME, OP3), \
- EXPAND_FROM_ABS32_W (CODE, NAME, OP3)
-
-#define EXPAND_TWOOP_L(CODE, NAME, OP1) \
- {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, OP1, B31 | RD32, IMM16ULIST, E}}}, \
- {CODE, AV_H8H, 6, NAME, {{IMM32, RD32, E}}, {{0x7, 0xa, OP1, B30 | RD32, IMM32LIST, E}}}, \
- EXPAND_FROM_IMM16_L (CODE, NAME, OP1), \
- EXPAND_FROM_IMM32_L (CODE, NAME, OP1), \
- EXPAND_FROM_REG32 (CODE, NAME, OP1), \
- EXPAND_TO_REG32 (CODE, NAME, OP1), \
- EXPAND_STD_MATRIX_L (CODE, NAME, OP1)
-
-
-/* Old expanders: */
-
-#define BITOP(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \
- {code, AV_H8, 2, name, {{imm, RD8, E}}, {{op00, op01, imm, RD8, E}}}, \
- {code, AV_H8, 6, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, 0, E}}}, \
- {code, AV_H8, 6, name, {{imm, ABS8DST, E}}, {{op20, op21, DSTABS8LIST, op00, op01, imm, 0, E}}}, \
- {code, AV_H8S, 6, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | MEMRELAX | ABS16LIST , op00, op01, imm, op4, E}}}, \
- {code, AV_H8S, 6, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | MEMRELAX | ABS32LIST , op00, op01, imm, op4, E}}}
-
-#define BITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \
- {code, AV_H8SX, 0, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, op4, E}}}, \
- {code, AV_H8SX, 0, name, {{imm, ABS8DST, E}}, {{op20, op21, DSTABS8LIST, op00, op01, imm, op4, E}}}, \
- {code, AV_H8SX, 0, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | ABS16LIST, op00, op01, imm, op4, E}}}, \
- {code, AV_H8SX, 0, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | ABS32LIST, op00, op01, imm, op4, E}}}
-
-#define EBITOP(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \
- BITOP(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \
- BITOP(code, RS8, name, op00, op01, op10, op11, op20, op21, op30, op4)
-
-#define EBITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \
- BITOP_B(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \
- BITOP_B(code, RS8, name, op00, op01, op10, op11, op20, op21, op30, op4)
-
-#define WTWOP(code, name, op1, op2) \
- {code, AV_H8, 2, name, {{RS16, RD16, E}}, {{op1, op2, RS16, RD16, E}}}
-
-#define BRANCH(code, name, op) \
- {code, AV_H8H, 6, name, {{PCREL16, E}}, {{0x5, 0x8, op, 0x0, PCREL16, DATA3 | B00, E}}}, \
- {code, AV_H8, 4, name, {{PCREL8, E}}, {{0x4, op, PCREL8, DATA | B00, E}}}
-
-
-#define UNOP(code, name, op1, op2) \
- {code, AV_H8, 2, name, {{OR8, E}}, {{op1, op2, 0, OR8, E}}}
-
-#define EXPAND_UNOP_STD_B(CODE, NAME, PREFIX, OP1, OP2, OP3) \
- {CODE, AV_H8, 2, NAME, {{OR8, E}}, {{ OP1, OP2, OP3, OR8, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{ 7, 13, B30 | RSIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 12, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 12, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 8, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B30 | DISPREG, 5, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B30 | DISPREG, 6, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B30 | DISPREG, 7, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{ABS8SRC, E}}, {{ 7, 15, ABS8LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{ 6, 10, 1, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{ 6, 10, 3, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, IGNORE, E}}}
-
-#define EXPAND_UNOP_STD_W(CODE, NAME, PREFIX, OP1, OP2, OP3) \
- {CODE, AV_H8H, 2, NAME, {{OR16, E}}, {{ OP1, OP2, OP3, OR16, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{ 7, 13, B31 | RSIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B30 | DISPREG, 5, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B30 | DISPREG, 6, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B30 | DISPREG, 7, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{ 6, 11, 1, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{ 6, 11, 3, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, IGNORE, E}}}
-
-#define EXPAND_UNOP_STD_L(CODE, NAME, PREFIX, OP1, OP2, OP3) \
- {CODE, AV_H8H, 2, NAME, {{OR32, E}}, {{ OP1, OP2, OP3, B30 | OR32, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{PREFIX, 4, 6, 9, B30 | RSIND, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B31 | DISPREG, 4, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B31 | DISPREG, 5, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B31 | DISPREG, 6, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B31 | DISPREG, 7, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{PREFIX, 4, 6, 11, 0, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{PREFIX, 4, 6, 11, 2, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}
-
-#define EXPAND_UNOP_EXTENDED_B(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \
- {CODE, AV_H8, 2, NAME, {{CONST, RD8, E}}, {{ OP1, OP2, OP3, RD8, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{ 7, 13, B30 | RDIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 12, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 12, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 8, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, ABS8DST, E}}, {{ 7, 15, DSTABS8LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{ 6, 10, 1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{ 6, 10, 3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, IGNORE, E}}}
-
-#define EXPAND_UNOP_EXTENDED_W(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \
- {CODE, AV_H8, 2, NAME, {{CONST, RD16, E}}, {{ OP1, OP2, OP3, RD16, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{ 7, 13, B31 | RDIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{ 6, 11, 1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{ 6, 11, 3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, IGNORE, E}}}
-
-#define EXPAND_UNOP_EXTENDED_L(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3, BIT) \
- {CODE, AV_H8, 2, NAME, {{CONST, RD32, E}}, {{ OP1, OP2, OP3, BIT | RD32, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{PREFIX, 4, 6, 9, B30 | RDIND, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B31 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B31 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B31 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B31 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{PREFIX, 4, 6, 11, 0, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \
- {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{PREFIX, 4, 6, 11, 2, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}
-
-#define PREFIXLDC 0x0, 0x1, 0x4, B30 | CCR_EXR | DST
-#define PREFIXSTC 0x0, 0x1, 0x4, B30 | CCR_EXR | SRC
-
-#define O(op, size) (op * 4 + size)
-#define OP_SIZE(HOW) (HOW % 4)
-#define OP_KIND(HOW) (HOW / 4)
-
-enum h8_asm_codes
-{
- O_RECOMPILE = 0,
- O_ADD,
- O_ADDX,
- O_AND,
- O_BAND,
- O_BRA,
- O_BRAB,
- O_BRAW,
- O_BRAL,
- O_BRAS,
- O_BRABC,
- O_BRABS,
- O_BSRBC,
- O_BSRBS,
- O_BRN,
- O_BHI,
- O_BLS,
- O_BCC,
- O_BCS,
- O_BNE,
- O_BVC,
- O_BVS,
- O_BPL,
- O_BMI,
- O_BGE,
- O_BLT,
- O_BGT,
- O_BLE,
- O_ANDC,
- O_BEQ,
- O_BCLR,
- O_BCLREQ,
- O_BCLRNE,
- O_BSETEQ,
- O_BSETNE,
- O_BFLD,
- O_BFST,
- O_BIAND,
- O_BILD,
- O_BIOR,
- O_BIXOR,
- O_BIST,
- O_BISTZ,
- O_BLD,
- O_BNOT,
- O_BOR,
- O_BSET,
- O_BSR,
- O_BXOR,
- O_CMP,
- O_DAA,
- O_DAS,
- O_DEC,
- O_DIVU,
- O_DIVS,
- O_DIVXU,
- O_DIVXS,
- O_INC,
- O_LDC,
- O_MOV,
- O_MOVAB,
- O_MOVAW,
- O_MOVAL,
- O_MOVMD,
- O_MOVSD,
- O_OR,
- O_ROTL,
- O_ROTR,
- O_ROTXL,
- O_ROTXR,
- O_BPT,
- O_SHAL,
- O_SHAR,
- O_SHLL,
- O_SHLR,
- O_SUB,
- O_SUBS,
- O_TRAPA,
- O_XOR,
- O_XORC,
- O_BST,
- O_BSTZ,
- O_BTST,
- O_EEPMOV,
- O_EXTS,
- O_EXTU,
- O_JMP,
- O_JSR,
- O_MULU,
- O_MULUU,
- O_MULS,
- O_MULSU,
- O_MULXU,
- O_MULXS,
- O_NOP,
- O_NOT,
- O_ORC,
- O_RTE,
- O_RTEL,
- O_STC,
- O_SUBX,
- O_NEG,
- O_RTS,
- O_RTSL,
- O_SLEEP,
- O_ILL,
- O_ADDS,
- O_SYSCALL,
- O_TAS,
- O_CLRMAC,
- O_LDMAC,
- O_MAC,
- O_LDM,
- O_STM,
- O_STMAC,
- O_LAST,
- /* Change made for System Call processing. */
- O_SYS_CREAT,
- O_SYS_OPEN,
- O_SYS_READ,
- O_SYS_WRITE,
- O_SYS_LSEEK,
- O_SYS_CLOSE,
- O_SYS_STAT,
- O_SYS_FSTAT,
-/* Space reserved for future file I/O system calls. */
- O_SYS_CMDLINE
- /* End of System Call specific Changes. */
-};
-
-enum h8_size
-{
- SB = 0,
- SW = 1,
- SL = 2,
- SN = 3
-};
-
-
-/* FIXME: Lots of insns have "E, 0, 0, 0, 0" in the nibble code sequences.
- Methinks the zeroes aren't necessary. Once confirmed, nuke 'em. */
-
-struct h8_opcode h8_opcodes[] =
-{
- {O (O_ADD, SB), AV_H8, 2, "add.b", {{IMM8, RD8, E}}, {{0x8, RD8, IMM8LIST, E}}},
- EXPAND_TWOOP_B (O (O_ADD, SB), "add.b", 0x8, 0x0, 0x8, 0x1, 0),
-
- {O (O_ADD, SW), AV_H8, 6, "add.w", {{RS16, RD16, E}}, {{0x0, 0x9, RS16, RD16, E}}},
- {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RD16, E}}, {{0x0, 0xa, B30 | IMM3NZ, RD16, E}}},
- {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}},
- {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}},
- {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}},
- EXPAND_TWOOP_W (O (O_ADD, SW), "add.w", 0x0, 0x9, 0x1),
-
- {O (O_ADD, SL), AV_H8H, 6, "add.l", {{RS32, RD32, E}}, {{0x0, 0xa, B31 | RS32, B30 | RD32, E}}},
- {O (O_ADD, SL), AV_H8SX, 0, "add.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xa, B31 | IMM3NZ, B31 | RD32, E}}},
- EXPAND_TWOOP_L (O (O_ADD, SL), "add.l", 0x1),
-
- {O (O_ADDS, SL), AV_H8, 2, "adds", {{KBIT, RDP, E}}, {{0x0, 0xB,KBIT, RDP, E}}},
-
- {O (O_ADDX, SB), AV_H8, 2, "addx", {{IMM8, RD8, E}}, {{0x9, RD8, IMM8LIST, E}}},
- {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x9, IGNORE, IMM8LIST, E}}},
- {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x9, IGNORE, IMM8LIST, E}}},
- {O (O_ADDX, SB), AV_H8, 2, "addx", {{RS8, RD8, E}}, {{0x0, 0xe, RS8, RD8, E}}},
- {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x0, 0xe, RS8, IGNORE, E}}},
- {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x0, 0xe, RS8, IGNORE, E}}},
- {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, 0x0, 0xe, IGNORE, RD8, E}}},
- {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RD8, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x0, 0xe, IGNORE, RD8, E}}},
- {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND, RDIND, E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}},
- {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}},
-
- {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RD16, E}}, {{PREFIX_0151, 0x7, 0x9, 0x1, RD16, IMM16LIST, E}}},
- {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}},
- {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}},
- {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RD16, E}}, {{PREFIX_0151, 0x0, 0x9, RS16, RD16, E}}},
- {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}},
- {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}},
- {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}},
- {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RD16, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}},
- {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND, RDIND, E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}},
- {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}},
-
- {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RD32, E}}, {{PREFIX_0101, 0x7, 0xa, 0x1, RD32, IMM32LIST, E}}},
- {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}},
- {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}},
- {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RD32, E}}, {{PREFIX_0101, 0x0, 0xa, B31 | RS32, B30 | RD32, E}}},
- {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}},
- {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}},
- {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND, RD32, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}},
- {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}},
- {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}},
- {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}},
-
- {O (O_AND, SB), AV_H8, 2, "and.b", {{IMM8, RD8, E}}, {{0xe, RD8, IMM8LIST, E}}},
- EXPAND_TWOOP_B (O (O_AND, SB), "and.b", 0xe, 0x1, 0x6, 0x6, 0),
-
- {O (O_AND, SW), AV_H8, 2, "and.w", {{RS16, RD16, E}}, {{0x6, 0x6, RS16, RD16, E}}},
- EXPAND_TWOOP_W (O (O_AND, SW), "and.w", 0x6, 0x6, 0x6),
-
- {O (O_AND, SL), AV_H8H, 2, "and.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x6, B30 | RS32, B30 | RD32, E}}},
- EXPAND_TWOOP_L (O (O_AND, SL), "and.l", 0x6),
-
- {O (O_ANDC, SB), AV_H8, 2, "andc", {{IMM8, CCR | DST, E}}, {{0x0, 0x6, IMM8LIST, E}}},
- {O (O_ANDC, SB), AV_H8S, 2, "andc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x6, IMM8LIST, E}}},
-
- BRANCH (O (O_BRA, SB), "bra", 0x0),
-
- {O (O_BRAB, SB), AV_H8SX, 0, "bra", {{LOWREG | L_8, E}}, {{0x5, 0x9, LOWREG | L_8 | B30, 0x5, E}}},
- {O (O_BRAW, SW), AV_H8SX, 0, "bra", {{LOWREG | L_16, E}}, {{0x5, 0x9, LOWREG | L_16 | B30, 0x6, E}}},
- {O (O_BRAL, SL), AV_H8SX, 0, "bra", {{RS32, E}}, {{0x5, 0x9, RS32 | B30, 0x7, E}}},
-
- {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND, OP3PCREL8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}},
- {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST, OP3PCREL8}}, {{0x7, 0xE, DSTABS8LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}},
- {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}},
- {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}},
- {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND, OP3PCREL8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}},
- {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST, OP3PCREL8}}, {{0x7, 0xE, DSTABS8LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}},
- {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}},
- {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}},
- {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
- {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
- {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
- {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
- {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
- {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
- {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
- {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
-
- {O (O_BRAS, SB), AV_H8SX, 0, "bra/s", {{PCREL8, E}}, {{0x4, 0x0, PCREL8, DATA | B01, E}}},
-
- {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
- {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
- {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
- {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
- {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
- {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
- {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
- {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
-
- BRANCH (O (O_BRA, SB), "bt", 0x0),
- BRANCH (O (O_BRN, SB), "brn", 0x1),
- BRANCH (O (O_BRN, SB), "bf", 0x1),
- BRANCH (O (O_BHI, SB), "bhi", 0x2),
- BRANCH (O (O_BLS, SB), "bls", 0x3),
- BRANCH (O (O_BCC, SB), "bcc", 0x4),
- BRANCH (O (O_BCC, SB), "bhs", 0x4),
- BRANCH (O (O_BCS, SB), "bcs", 0x5),
- BRANCH (O (O_BCS, SB), "blo", 0x5),
- BRANCH (O (O_BNE, SB), "bne", 0x6),
- BRANCH (O (O_BEQ, SB), "beq", 0x7),
- BRANCH (O (O_BVC, SB), "bvc", 0x8),
- BRANCH (O (O_BVS, SB), "bvs", 0x9),
- BRANCH (O (O_BPL, SB), "bpl", 0xA),
- BRANCH (O (O_BMI, SB), "bmi", 0xB),
- BRANCH (O (O_BGE, SB), "bge", 0xC),
- BRANCH (O (O_BLT, SB), "blt", 0xD),
- BRANCH (O (O_BGT, SB), "bgt", 0xE),
- BRANCH (O (O_BLE, SB), "ble", 0xF),
-
- EBITOP (O (O_BCLR, SB), IMM3 | B30, "bclr", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
- BITOP (O (O_BAND, SB), IMM3 | B30, "band", 0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
- BITOP (O (O_BIAND, SB), IMM3 | B31, "biand", 0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
- BITOP (O (O_BILD, SB), IMM3 | B31, "bild", 0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
- BITOP (O (O_BIOR, SB), IMM3 | B31, "bior", 0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
- BITOP (O (O_BIST, SB), IMM3 | B31, "bist", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
- BITOP (O (O_BIXOR, SB), IMM3 | B31, "bixor", 0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
- BITOP (O (O_BLD, SB), IMM3 | B30, "bld", 0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
- EBITOP (O (O_BNOT, SB), IMM3 | B30, "bnot", 0x6, 0x1, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
- BITOP (O (O_BOR, SB), IMM3 | B30, "bor", 0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
- EBITOP (O (O_BSET, SB), IMM3 | B30, "bset", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
- BITOP (O (O_BST, SB), IMM3 | B30, "bst", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
- EBITOP (O (O_BTST, SB), IMM3 | B30, "btst", 0x6, 0x3, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
- BITOP (O (O_BXOR, SB), IMM3 | B30, "bxor", 0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
-
- EBITOP_B (O (O_BCLREQ, SB), IMM3 | B30, "bclr/eq", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7),
- EBITOP_B (O (O_BCLRNE, SB), IMM3 | B30, "bclr/ne", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6),
- EBITOP_B (O (O_BSETEQ, SB), IMM3 | B30, "bset/eq", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7),
- EBITOP_B (O (O_BSETNE, SB), IMM3 | B30, "bset/ne", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6),
- BITOP_B (O (O_BISTZ, SB), IMM3 | B31, "bistz", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7),
- BITOP_B (O (O_BSTZ, SB), IMM3 | B30, "bstz", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7),
-
- {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, RDIND, R3_8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0xF, R3_8, IMM8LIST, E}}},
- {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS8DST, R3_8}}, {{0x7, 0xE, DSTABS8LIST, 0xF, R3_8, IMM8LIST, E}}},
- {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS16DST, R3_8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0xF, R3_8, IMM8LIST, E}}},
- {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS32DST, R3_8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0xF, R3_8, IMM8LIST, E}}},
-
- /* Because the assembler treats SRC, DST and OP3 as ordinals,
- I must designate the second argument, an immediate value, as DST.
- May God have mercy on my soul. */
- {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, R3_IND}}, {{0x7, 0xD, B30 | R3_IND, 0x0, 0xF, RS8, DST | IMM8LIST, E}}},
- {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS8OP3}}, {{0x7, 0xF, OP3ABS8LIST, 0xF, RS8, DST | IMM8LIST, E}}},
- {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS16OP3}}, {{0x6, 0xA, 0x1, 0x8, OP3ABS16LIST, 0xF, RS8, DST | IMM8LIST, E}}},
- {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS32OP3}}, {{0x6, 0xA, 0x3, 0x8, OP3ABS32LIST, 0xF, RS8, DST | IMM8LIST, E}}},
-
- {O (O_BSR, SB), AV_H8, 6, "bsr", {{PCREL8, E}}, {{0x5, 0x5, PCREL8, DATA, E}}},
- {O (O_BSR, SB), AV_H8, 6, "bsr", {{PCREL16, E}}, {{0x5, 0xC, 0x0, 0x0, PCREL16, DATA3, E}}},
- {O (O_BSR, SB), AV_H8SX, 0, "bsr", {{LOWREG | L_8, E}}, {{0x5, 0xd, B30 | LOWREG | L_8, 0x5, E}}},
- {O (O_BSR, SW), AV_H8SX, 0, "bsr", {{LOWREG | L_16, E}}, {{0x5, 0xd, B30 | LOWREG | L_16, 0x6, E}}},
- {O (O_BSR, SL), AV_H8SX, 0, "bsr", {{OR32, E}}, {{0x5, 0xd, B30 | OR32, 0x7, E}}},
-
- {O (O_CMP, SB), AV_H8, 2, "cmp.b", {{IMM8, RD8, E}}, {{0xa, RD8, IMM8LIST, E}}},
- EXPAND_TWOOP_B (O (O_CMP, SB), "cmp.b", 0xa, 0x1, 0xc, 0x2, B00),
-
- {O (O_CMP, SW), AV_H8, 2, "cmp.w", {{RS16, RD16, E}}, {{0x1, 0xd, RS16, RD16, E}}},
- {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RD16, E}}, {{0x1, 0xf, B30 | IMM3NZ, RD16, E}}},
- {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}},
- {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}},
- {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}},
- EXPAND_TWOOP_W (O (O_CMP, SW), "cmp.w", 0x1, 0xd, 0x2),
-
- {O (O_CMP, SL), AV_H8H, 6, "cmp.l", {{RS32, RD32, E}}, {{0x1, 0xf, B31 | RS32, B30 | RD32, E}}},
- {O (O_CMP, SL), AV_H8SX, 0, "cmp.l", {{IMM3NZ_NS, RD32, E}}, {{0x1, 0xf, B31 | IMM3NZ, B31 | RD32, E}}},
- EXPAND_TWOOP_L (O (O_CMP, SL), "cmp.l", 0x2),
-
- UNOP (O (O_DAA, SB), "daa", 0x0, 0xF),
- UNOP (O (O_DAS, SB), "das", 0x1, 0xF),
- UNOP (O (O_DEC, SB), "dec.b", 0x1, 0xA),
-
- {O (O_DEC, SW), AV_H8H, 2, "dec.w", {{DBIT, RD16, E}}, {{0x1, 0xB, 0x5 | DBIT, RD16, E}}},
- {O (O_DEC, SL), AV_H8H, 2, "dec.l", {{DBIT, RD32, E}}, {{0x1, 0xB, 0x7 | DBIT, RD32 | B30, E}}},
-
- {O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x1, IMM4, RD16, E}}},
- {O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x1, RS16, RD16, E}}},
- {O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x3, IMM4, B30 | RD32, E}}},
- {O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}},
-
- {O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x1, IMM4, RD16, E}}},
- {O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x1, RS16, RD16, E}}},
- {O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x3, IMM4, B30 | RD32, E}}},
- {O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}},
-
- {O (O_DIVXS, SB), AV_H8SX, 0, "divxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x1, IMM4, RD16, E}}},
- {O (O_DIVXS, SB), AV_H8H, 13, "divxs.b", {{RS8, RD16, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x1, RS8, RD16, E}}},
- {O (O_DIVXS, SW), AV_H8SX, 0, "divxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x3, IMM4, B30 | RD32, E}}},
- {O (O_DIVXS, SW), AV_H8H, 21, "divxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x3, RS16, B30 | RD32, E}}},
-
- {O (O_DIVXU, SB), AV_H8SX, 0, "divxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x1, IMM4, RD16, E}}},
- {O (O_DIVXU, SB), AV_H8, 13, "divxu.b", {{RS8, RD16, E}}, {{0x5, 0x1, RS8, RD16, E}}},
- {O (O_DIVXU, SW), AV_H8SX, 0, "divxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x3, IMM4, B30 | RD32, E}}},
- {O (O_DIVXU, SW), AV_H8H, 21, "divxu.w", {{RS16, RD32, E}}, {{0x5, 0x3, RS16, B30 | RD32, E}}},
-
- {O (O_EEPMOV, SB), AV_H8, 4, "eepmov.b", {{E}}, {{0x7, 0xB, 0x5, 0xC, 0x5, 0x9, 0x8, 0xF, E}}},
- {O (O_EEPMOV, SW), AV_H8H, 4, "eepmov.w", {{E}}, {{0x7, 0xB, 0xD, 0x4, 0x5, 0x9, 0x8, 0xF, E}}},
-
- EXPAND_UNOP_STD_W (O (O_EXTS, SW), "exts.w", PREFIX_015, 0x1, 0x7, 0xd),
- EXPAND_UNOP_STD_L (O (O_EXTS, SL), "exts.l", PREFIX_010, 0x1, 0x7, 0xf),
- EXPAND_UNOP_EXTENDED_L (O (O_EXTS, SL), "exts.l", CONST_2, PREFIX_010, 0x1, 0x7, 0xe, 0),
- EXPAND_UNOP_STD_W (O (O_EXTU, SW), "extu.w", PREFIX_015, 0x1, 0x7, 0x5),
- EXPAND_UNOP_STD_L (O (O_EXTU, SL), "extu.l", PREFIX_010, 0x1, 0x7, 0x7),
- EXPAND_UNOP_EXTENDED_L (O (O_EXTU, SL), "extu.l", CONST_2, PREFIX_010, 0x1, 0x7, 0x6, 0),
-
- UNOP (O (O_INC, SB), "inc", 0x0, 0xA),
-
- {O (O_INC, SW), AV_H8H, 2, "inc.w", {{DBIT, RD16, E}}, {{0x0, 0xB, 0x5 | DBIT, RD16, E}}},
- {O (O_INC, SL), AV_H8H, 2, "inc.l", {{DBIT, RD32, E}}, {{0x0, 0xB, 0x7 | DBIT, RD32 | B30, E}}},
-
- {O (O_JMP, SN), AV_H8, 4, "jmp", {{RSIND, E}}, {{0x5, 0x9, B30 | RSIND, 0x0, E}}},
- {O (O_JMP, SN), AV_H8, 6, "jmp", {{ABSJMP | L_24, E}}, {{0x5, 0xA, SRC | ABSJMP | L_24, DATA5, E}}},
-
- {O (O_JMP, SN), AV_H8SX, 0, "jmp", {{ABSJMP | L_32, E}}, {{0x5, 0x9, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}},
-
- {O (O_JMP, SN), AV_H8, 8, "jmp", {{MEMIND, E}}, {{0x5, 0xB, SRC | MEMIND, DATA, E}}},
- {O (O_JMP, SN), AV_H8SX, 0, "jmp", {{VECIND, E}}, {{0x5, 0x9, B31 | SRC | VECIND, DATA, E}}},
-
- {O (O_JSR, SN), AV_H8, 6, "jsr", {{RSIND, E}}, {{0x5, 0xD, B30 | RSIND, 0x0, E}}},
- {O (O_JSR, SN), AV_H8, 8, "jsr", {{ABSJMP | L_24, E}}, {{0x5, 0xE, SRC | ABSJMP | L_24, DATA5, E}}},
-
- {O (O_JSR, SN), AV_H8SX, 0, "jsr", {{ABSJMP | L_32, E}}, {{0x5, 0xD, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}},
-
- {O (O_JSR, SN), AV_H8, 8, "jsr", {{MEMIND, E}}, {{0x5, 0xF, SRC | MEMIND, DATA, E}}},
- {O (O_JSR, SN), AV_H8SX, 8, "jsr", {{VECIND, E}}, {{0x5, 0xD, SRC | VECIND, DATA, E}}},
-
- {O (O_LDC, SB), AV_H8, 2, "ldc", {{IMM8, CCR | DST, E}}, {{ 0x0, 0x7, IMM8LIST, E}}},
- {O (O_LDC, SB), AV_H8S, 2, "ldc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x7, IMM8LIST, E}}},
- {O (O_LDC, SB), AV_H8, 2, "ldc", {{RS8, CCR | DST, E}}, {{0x0, 0x3, B30 | CCR | DST, RS8, E}}},
- {O (O_LDC, SB), AV_H8S, 2, "ldc", {{RS8, EXR | DST, E}}, {{0x0, 0x3, B30 | EXR | DST, RS8, E}}},
- {O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSIND, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND, IGNORE, E}}},
- {O (O_LDC, SW), AV_H8S, 2, "ldc", {{RSIND, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND, IGNORE, E}}},
- {O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSPOSTINC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}},
- {O (O_LDC, SW), AV_H8S, 2, "ldc", {{RSPOSTINC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}},
- {O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG, IGNORE, SRC | DISP16LIST, E}}},
- {O (O_LDC, SW), AV_H8S, 2, "ldc", {{DISP16SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG, IGNORE, SRC | DISP16LIST, E}}},
- {O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}},
- {O (O_LDC, SW), AV_H8S, 2, "ldc", {{DISP32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}},
- {O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}},
- {O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS16SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}},
- {O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}},
- {O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}},
-
- {O (O_LDC, SL), AV_H8SX, 0, "ldc", {{RS32, B30 | VBR_SBR | DST, E}}, {{0x0, 0x3, B30 | VBR_SBR | DST, RS32, E}}},
-
-
- {O (O_MOV, SB), AV_H8, 2, "mov.b", {{IMM8, RD8, E}}, {{0xF, RD8, IMM8LIST, E}}},
- {O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xa, 0xd, IMM4, DSTABS16LIST, E}}},
- {O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xa, 0xf, IMM4, DSTABS32LIST, E}}},
- MOVFROM_IMM8 (O (O_MOV, SB), PREFIX_017D, "mov.b", IMM8),
-
- {O (O_MOV, SB), AV_H8, 2, "mov.b", {{RS8, RD8, E}}, {{0x0, 0xC, RS8, RD8, E}}},
- MOVFROM_REG_BW (O (O_MOV, SB), "mov.b", RS8, PREFIX_017, 8, 10, 12, 14, MEMRELAX),
- {O (O_MOV, SB), AV_H8, 4, "mov.b", {{RS8, ABS8DST, E}}, {{0x3, RS8, DSTABS8LIST, E}}},
- MOVTO_REG_BW (O (O_MOV, SB), "mov.b", RD8, PREFIX_017, 8, 10, 12, 14, MEMRELAX),
- {O (O_MOV, SB), AV_H8, 4, "mov.b", {{ABS8SRC, RD8, E}}, {{0x2, RD8, ABS8LIST, E}}},
-
- MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSIND, FROM_IND),
- MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTINC, FROM_POSTINC),
- MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTDEC, FROM_POSTDEC),
- MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREINC, FROM_PREINC),
- MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREDEC, FROM_PREDEC),
- MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP2SRC, FROM_DISP2),
- MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP16SRC, FROM_DISP16, DISP16LIST),
- MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP32SRC, FROM_DISP32, DISP32LIST),
- MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB16, FROM_DISP16B, DISP16LIST),
- MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW16, FROM_DISP16W, DISP16LIST),
- MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL16, FROM_DISP16L, DISP16LIST),
- MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB32, FROM_DISP32B, DISP32LIST),
- MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW32, FROM_DISP32W, DISP32LIST),
- MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL32, FROM_DISP32L, DISP32LIST),
- MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS16SRC, FROM_ABS16, ABS16LIST),
- MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS32SRC, FROM_ABS32, ABS32LIST),
-
- {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM3NZ_NS, RD16, E}}, {{0x0, 0xf, B30 | IMM3NZ, RD16, E}}},
- {O (O_MOV, SW), AV_H8, 4, "mov.w", {{IMM16, RD16, E}}, {{0x7, 0x9, 0x0, RD16, IMM16LIST, E}}},
- {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xb, 0xd, IMM4, DSTABS16LIST, E}}},
- {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xb, 0xf, IMM4, DSTABS32LIST, E}}},
-
- MOVFROM_IMM8 (O (O_MOV, SW), PREFIX_015D, "mov.w", IMM8U_NS),
- MOVFROM_IMM (O (O_MOV, SW), PREFIX_7974, "mov.w", IMM16, IMM16LIST),
-
- {O (O_MOV, SW), AV_H8, 2, "mov.w", {{RS16, RD16, E}}, {{0x0, 0xD, RS16, RD16, E}}},
- MOVFROM_REG_BW (O (O_MOV, SW), "mov.w", RS16, PREFIX_015, 9, 11, 13, 15, 0),
- MOVTO_REG_BW (O (O_MOV, SW), "mov.w", RD16, PREFIX_015, 9, 11, 13, 15, 0),
-
- MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSIND, FROM_IND),
- MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTINC, FROM_POSTINC),
- MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTDEC, FROM_POSTDEC),
- MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREINC, FROM_PREINC),
- MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREDEC, FROM_PREDEC),
- MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP2SRC, FROM_DISP2),
- MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP16SRC, FROM_DISP16, DISP16LIST),
- MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP32SRC, FROM_DISP32, DISP32LIST),
- MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB16, FROM_DISP16B, DISP16LIST),
- MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW16, FROM_DISP16W, DISP16LIST),
- MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL16, FROM_DISP16L, DISP16LIST),
- MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB32, FROM_DISP32B, DISP32LIST),
- MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW32, FROM_DISP32W, DISP32LIST),
- MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL32, FROM_DISP32L, DISP32LIST),
- MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS16SRC, FROM_ABS16, ABS16LIST),
- MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS32SRC, FROM_ABS32, ABS32LIST),
-
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xf, B31 | IMM3NZ, B31 | RD32, E}}},
-
- MOVFROM_IMM8 (O (O_MOV, SL), PREFIX_010D, "mov.l", IMM8U_NS),
- MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A7C, "mov.l", IMM16U_NS, IMM16ULIST),
-
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, 0x0, B31 | RD32, IMM16ULIST, E}}},
- {O (O_MOV, SL), AV_H8H, 4, "mov.l", {{IMM32, RD32, E}}, {{0x7, 0xa, 0x0, B30 | RD32, IMM32LIST, E}}},
-
- MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A74, "mov.l", IMM32, IMM32LIST),
-
- {O (O_MOV, SL), AV_H8H, 2, "mov.l", {{RS32, RD32, E}}, {{0x0, 0xf, B31 | RS32, B30 | RD32, E}}},
-
- {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, RDIND, E}}, {{PREFIX_0100, 0x6, 0x9, B31 | RDIND, B30 | RS32, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTINC, E}}, {{PREFIX_0103, 0x6, 0xd, B31 | RDPOSTINC, RS32, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0101, 0x6, 0xd, B31 | RDPOSTDEC, RS32, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPREINC, E}}, {{PREFIX_0102, 0x6, 0xd, B31 | RDPREINC, RS32, E}}},
- {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, RDPREDEC, E}}, {{PREFIX_0100, 0x6, 0xd, B31 | RDPREDEC, RS32, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, DISP2DST, E}}, {{PREFIX_010, B30 | B20 | DISP2DST, 0x6, 0x9, B31 | DSTDISPREG, RS32, E}}},
- {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP16DST, E}}, {{PREFIX_0100, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},
- {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{RS32, DISP32DST, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}},
- {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}},
- {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB16D, E}}, {{PREFIX_0101, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW16D, E}}, {{PREFIX_0102, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL16D, E}}, {{PREFIX_0103, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x1, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x2, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x3, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}},
- {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, ABS16DST, E}}, {{PREFIX_0100, 0x6, 0xb, 0x8, RS32, DSTABS16LIST, E}}},
- {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, ABS32DST, E}}, {{PREFIX_0100, 0x6, 0xb, 0xa, RS32, MEMRELAX | DSTABS32LIST, E}}},
-
- {O (O_MOV, SL), AV_H8H, 4, "mov.l", {{RSIND, RD32, E}}, {{PREFIX_0100, 0x6, 0x9, B30 | RSIND, RD32, E}}},
- {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RSPOSTINC, RD32, E}}, {{PREFIX_0100, 0x6, 0xd, B30 | RSPOSTINC, RD32, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0102, 0x6, 0xd, B30 | RSPOSTDEC, RD32, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREINC, RD32, E}}, {{PREFIX_0101, 0x6, 0xd, B30 | RSPREINC, RD32, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREDEC, RD32, E}}, {{PREFIX_0103, 0x6, 0xd, B30 | RSPREDEC, RD32, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{DISP2SRC, RD32, E}}, {{PREFIX_010, B30 | B20 | DISP2SRC, 0x6, 0x9, B30 | DISPREG, RD32, E}}},
- {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP16SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}},
- {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}},
- {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{PREFIX_0100, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB16, RD32, E}}, {{PREFIX_0101, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW16, RD32, E}}, {{PREFIX_0102, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL16, RD32, E}}, {{PREFIX_0103, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x1, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x2, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}},
- {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x3, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}},
- {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{ABS16SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xb, 0x0, RD32, SRC | ABS16LIST, E}}},
- {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{ABS32SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xb, 0x2, RD32, SRC | MEMRELAX | ABS32LIST, E}}},
-
- MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSIND, FROM_IND),
- MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTINC, FROM_POSTINC),
- MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTDEC, FROM_POSTDEC),
- MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREINC, FROM_PREINC),
- MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREDEC, FROM_PREDEC),
- MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP2SRC, FROM_DISP2),
- MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP16SRC, FROM_DISP16, DISP16LIST),
- MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP32SRC, FROM_DISP32, DISP32LIST),
- MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB16, FROM_DISP16B, DISP16LIST),
- MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW16, FROM_DISP16W, DISP16LIST),
- MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL16, FROM_DISP16L, DISP16LIST),
- MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB32, FROM_DISP32B, DISP32LIST),
- MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW32, FROM_DISP32W, DISP32LIST),
- MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL32, FROM_DISP32L, DISP32LIST),
- MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS16SRC, FROM_ABS16, ABS16LIST),
- MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS32SRC, FROM_ABS32, ABS32LIST),
-
-#define DO_MOVA1(TYPE, OP0, OP1) \
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
-\
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}
-
-#define DO_MOVA2(TYPE, OP0, OP1, OP2) \
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
-\
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}
-
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, E}}, {{0x7, 0xA, 0x8, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, E}}, {{0x7, 0xA, 0x9, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xA, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xB, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xC, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xD, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
-
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, E}}, {{0x7, 0xA, 0x8, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, E}}, {{0x7, 0xA, 0x9, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xA, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xB, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xC, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xD, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
-
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
-
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
- {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
- {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
- {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
-
- DO_MOVA1 (RDIND, 0x0, B30 | RDIND),
- DO_MOVA1 (RDPOSTINC, 0x8, B30 | RDPOSTINC),
- DO_MOVA1 (RDPOSTDEC, 0xA, B30 | RDPOSTDEC),
- DO_MOVA1 (RDPREINC, 0x9, B30 | RDPREINC),
- DO_MOVA1 (RDPREDEC, 0xB, B30 | RDPREDEC),
- DO_MOVA1 (DISP2DST, B30 | B20 | DISP2DST, B30 | DSTDISPREG),
- DO_MOVA2 (DISP16DST, 0xC, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
- DO_MOVA2 (DISP32DST, 0xC, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
- DO_MOVA2 (INDEXB16D, 0xD, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
- DO_MOVA2 (INDEXW16D, 0xE, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
- DO_MOVA2 (INDEXL16D, 0xF, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
- DO_MOVA2 (INDEXB32D, 0xD, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
- DO_MOVA2 (INDEXW32D, 0xE, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
- DO_MOVA2 (INDEXL32D, 0xF, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
- DO_MOVA2 (ABS16DST, 0x4, 0x0, MEMRELAX | DSTABS16LIST),
- DO_MOVA2 (ABS32DST, 0x4, 0x8, MEMRELAX | DSTABS32LIST),
-
- {O (O_MOV, SB), AV_H8, 10, "movfpe", {{ABS16SRC, RD8, E}}, {{0x6, 0xA, 0x4, RD8, ABS16SRC, DATA3, E}}},
- {O (O_MOV, SB), AV_H8, 10, "movtpe", {{RS8, ABS16DST, E}}, {{0x6, 0xA, 0xC, RS8, ABS16DST, DATA3, E}}},
-
- {O (O_MOVMD, SB), AV_H8SX, 0, "movmd.b", {{E}}, {{0x7, 0xb, 0x9, 0x4, E}}},
- {O (O_MOVMD, SW), AV_H8SX, 0, "movmd.w", {{E}}, {{0x7, 0xb, 0xa, 0x4, E}}},
- {O (O_MOVMD, SL), AV_H8SX, 0, "movmd.l", {{E}}, {{0x7, 0xb, 0xb, 0x4, E}}},
- {O (O_MOVSD, SB), AV_H8SX, 0, "movsd.b", {{PCREL16, E}}, {{0x7, 0xb, 0x8, 0x4, PCREL16, DATA3, E}}},
-
- {O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x0, IMM4, RD16, E}}},
- {O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x0, RS16, RD16, E}}},
- {O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x2, IMM4, B30 | RD32, E}}},
- {O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}},
-
- {O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x0, IMM4, RD16, E}}},
- {O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x0, RS16, RD16, E}}},
- {O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x2, IMM4, B30 | RD32, E}}},
- {O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}},
-
- {O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x7, 0x5, 0x2, IMM4, B30 | RD32, E}}},
- {O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x3, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}},
- {O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xf, 0x5, 0x2, IMM4, B30 | RD32, E}}},
- {O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xb, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}},
-
- {O (O_MULXS, SB), AV_H8SX, 0, "mulxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x0, IMM4, RD16, E}}},
- {O (O_MULXS, SB), AV_H8H, 20, "mulxs.b", {{RS8, RD16, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x0, RS8, RD16, E}}},
- {O (O_MULXS, SW), AV_H8SX, 0, "mulxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x2, IMM4, B30 | RD32, E}}},
- {O (O_MULXS, SW), AV_H8H, 20, "mulxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x2, RS16, B30 | RD32, E}}},
-
- {O (O_MULXU, SB), AV_H8SX, 0, "mulxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x0, IMM4, RD16, E}}},
- {O (O_MULXU, SB), AV_H8, 14, "mulxu.b", {{RS8, RD16, E}}, {{0x5, 0x0, RS8, RD16, E}}},
- {O (O_MULXU, SW), AV_H8SX, 0, "mulxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x2, IMM4, B30 | RD32, E}}},
- {O (O_MULXU, SW), AV_H8H, 14, "mulxu.w", {{RS16, RD32, E}}, {{0x5, 0x2, RS16, B30 | RD32, E}}},
-
- EXPAND_UNOP_STD_B (O (O_NEG, SB), "neg.b", PREFIX_017, 0x1, 0x7, 0x8),
- EXPAND_UNOP_STD_W (O (O_NEG, SW), "neg.w", PREFIX_015, 0x1, 0x7, 0x9),
- EXPAND_UNOP_STD_L (O (O_NEG, SL), "neg.l", PREFIX_010, 0x1, 0x7, 0xb),
-
- {O (O_NOP, SN), AV_H8, 2, "nop", {{E}}, {{0x0, 0x0, 0x0, 0x0, E}}},
-
- EXPAND_UNOP_STD_B (O (O_NOT, SB), "not.b", PREFIX_017, 0x1, 0x7, 0x0),
- EXPAND_UNOP_STD_W (O (O_NOT, SW), "not.w", PREFIX_015, 0x1, 0x7, 0x1),
- EXPAND_UNOP_STD_L (O (O_NOT, SL), "not.l", PREFIX_010, 0x1, 0x7, 0x3),
-
- {O (O_OR, SB), AV_H8, 2, "or.b", {{IMM8, RD8, E}}, {{0xc, RD8, IMM8LIST, E}}},
- EXPAND_TWOOP_B (O (O_OR, SB), "or.b", 0xc, 0x1, 0x4, 0x4, 0),
-
- {O (O_OR, SW), AV_H8, 2, "or.w", {{RS16, RD16, E}}, {{0x6, 0x4, RS16, RD16, E}}},
- EXPAND_TWOOP_W (O (O_OR, SW), "or.w", 0x6, 0x4, 0x4),
-
- {O (O_OR, SL), AV_H8H, 2, "or.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x4, B30 | RS32, B30 | RD32, E}}},
- EXPAND_TWOOP_L (O (O_OR, SL), "or.l", 0x4),
-
- {O (O_ORC, SB), AV_H8, 2, "orc", {{IMM8, CCR | DST, E}}, {{0x0, 0x4, IMM8LIST, E}}},
- {O (O_ORC, SB), AV_H8S, 2, "orc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x4, IMM8LIST, E}}},
-
- {O (O_MOV, SW), AV_H8, 6, "pop.w", {{OR16, E}}, {{0x6, 0xD, 0x7, OR16, E}}},
- {O (O_MOV, SL), AV_H8H, 6, "pop.l", {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0x7, OR32 | B30, E}}},
- {O (O_MOV, SW), AV_H8, 6, "push.w", {{OR16, E}}, {{0x6, 0xD, 0xF, OR16, E}}},
- {O (O_MOV, SL), AV_H8H, 6, "push.l", {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0xF, OR32 | B30, E}}},
-
- EXPAND_UNOP_STD_B (O (O_ROTL, SB), "rotl.b", PREFIX_017, 0x1, 0x2, 0x8),
- EXPAND_UNOP_EXTENDED_B (O (O_ROTL, SB), "rotl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0xc),
- EXPAND_UNOP_STD_W (O (O_ROTL, SW), "rotl.w", PREFIX_015, 0x1, 0x2, 0x9),
- EXPAND_UNOP_EXTENDED_W (O (O_ROTL, SW), "rotl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0xd),
- EXPAND_UNOP_STD_L (O (O_ROTL, SL), "rotl.l", PREFIX_010, 0x1, 0x2, 0xb),
- EXPAND_UNOP_EXTENDED_L (O (O_ROTL, SL), "rotl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0xf, B30),
- EXPAND_UNOP_STD_B (O (O_ROTR, SB), "rotr.b", PREFIX_017, 0x1, 0x3, 0x8),
- EXPAND_UNOP_EXTENDED_B (O (O_ROTR, SB), "rotr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0xc),
- EXPAND_UNOP_STD_W (O (O_ROTR, SW), "rotr.w", PREFIX_015, 0x1, 0x3, 0x9),
- EXPAND_UNOP_EXTENDED_W (O (O_ROTR, SW), "rotr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0xd),
- EXPAND_UNOP_STD_L (O (O_ROTR, SL), "rotr.l", PREFIX_010, 0x1, 0x3, 0xb),
- EXPAND_UNOP_EXTENDED_L (O (O_ROTR, SL), "rotr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0xf, B30),
- EXPAND_UNOP_STD_B (O (O_ROTXL, SB), "rotxl.b", PREFIX_017, 0x1, 0x2, 0x0),
- EXPAND_UNOP_EXTENDED_B (O (O_ROTXL, SB), "rotxl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0x4),
- EXPAND_UNOP_STD_W (O (O_ROTXL, SW), "rotxl.w", PREFIX_015, 0x1, 0x2, 0x1),
- EXPAND_UNOP_EXTENDED_W (O (O_ROTXL, SW), "rotxl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0x5),
- EXPAND_UNOP_STD_L (O (O_ROTXL, SL), "rotxl.l", PREFIX_010, 0x1, 0x2, 0x3),
- EXPAND_UNOP_EXTENDED_L (O (O_ROTXL, SL), "rotxl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0x7, B30),
- EXPAND_UNOP_STD_B (O (O_ROTXR, SB), "rotxr.b", PREFIX_017, 0x1, 0x3, 0x0),
- EXPAND_UNOP_EXTENDED_B (O (O_ROTXR, SB), "rotxr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0x4),
- EXPAND_UNOP_STD_W (O (O_ROTXR, SW), "rotxr.w", PREFIX_015, 0x1, 0x3, 0x1),
- EXPAND_UNOP_EXTENDED_W (O (O_ROTXR, SW), "rotxr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0x5),
- EXPAND_UNOP_STD_L (O (O_ROTXR, SL), "rotxr.l", PREFIX_010, 0x1, 0x3, 0x3),
- EXPAND_UNOP_EXTENDED_L (O (O_ROTXR, SL), "rotxr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0x7, B30),
-
-
- {O (O_BPT, SN), AV_H8, 10, "bpt", {{E}}, {{0x7, 0xA, 0xF, 0xF, E}}},
- {O (O_RTE, SN), AV_H8, 10, "rte", {{E}}, {{0x5, 0x6, 0x7, 0x0, E}}},
- {O (O_RTS, SN), AV_H8, 8, "rts", {{E}}, {{0x5, 0x4, 0x7, 0x0, E}}},
- {O (O_RTEL, SN), AV_H8SX, 0, "rte/l", {{RS32, RD32, E}}, {{0x5, 0x6, RS32 | B30, RD32 | B30, E}}},
- {O (O_RTSL, SN), AV_H8SX, 0, "rts/l", {{RS32, RD32, E}}, {{0x5, 0x4, RS32 | B30, RD32 | B30, E}}},
-
- EXPAND_UNOP_STD_B (O (O_SHAL, SB), "shal.b", PREFIX_017, 0x1, 0x0, 0x8),
- EXPAND_UNOP_EXTENDED_B (O (O_SHAL, SB), "shal.b", CONST_2, PREFIX_017, 0x1, 0x0, 0xc),
- EXPAND_UNOP_STD_W (O (O_SHAL, SW), "shal.w", PREFIX_015, 0x1, 0x0, 0x9),
- EXPAND_UNOP_EXTENDED_W (O (O_SHAL, SW), "shal.w", CONST_2, PREFIX_015, 0x1, 0x0, 0xd),
- EXPAND_UNOP_STD_L (O (O_SHAL, SL), "shal.l", PREFIX_010, 0x1, 0x0, 0xb),
- EXPAND_UNOP_EXTENDED_L (O (O_SHAL, SL), "shal.l", CONST_2, PREFIX_010, 0x1, 0x0, 0xf, B30),
- EXPAND_UNOP_STD_B (O (O_SHAR, SB), "shar.b", PREFIX_017, 0x1, 0x1, 0x8),
- EXPAND_UNOP_EXTENDED_B (O (O_SHAR, SB), "shar.b", CONST_2, PREFIX_017, 0x1, 0x1, 0xc),
- EXPAND_UNOP_STD_W (O (O_SHAR, SW), "shar.w", PREFIX_015, 0x1, 0x1, 0x9),
- EXPAND_UNOP_EXTENDED_W (O (O_SHAR, SW), "shar.w", CONST_2, PREFIX_015, 0x1, 0x1, 0xd),
- EXPAND_UNOP_STD_L (O (O_SHAR, SL), "shar.l", PREFIX_010, 0x1, 0x1, 0xb),
- EXPAND_UNOP_EXTENDED_L (O (O_SHAR, SL), "shar.l", CONST_2, PREFIX_010, 0x1, 0x1, 0xf, B30),
-
- EXPAND_UNOP_STD_B (O (O_SHLL, SB), "shll.b", PREFIX_017, 0x1, 0x0, 0x0),
-
- {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{RS8, RD8, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x0, RD8, E}}},
-
- EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_2, PREFIX_017, 0x1, 0x0, 0x4),
- EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_4, PREFIX_017, 0x1, 0x0, 0xa),
- {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x0, RD8, E}}},
-
- EXPAND_UNOP_STD_W (O (O_SHLL, SW), "shll.w", PREFIX_015, 0x1, 0x0, 0x1),
-
- {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{RS8, RD16, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x1, RD16, E}}},
-
- EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_2, PREFIX_015, 0x1, 0x0, 0x5),
- EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_4, PREFIX_015, 0x1, 0x0, 0x2),
- EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_8, PREFIX_015, 0x1, 0x0, 0x6),
- {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x1, RD16, E}}},
-
- EXPAND_UNOP_STD_L (O (O_SHLL, SL), "shll.l", PREFIX_010, 0x1, 0x0, 0x3),
-
- {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{RS8, RD32, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x3, B30 | RD32, E}}},
-
- EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_2, PREFIX_010, 0x1, 0x0, 0x7, B30),
- EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_4, PREFIX_010, 0x1, 0x0, 0x3, B31),
- EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_8, PREFIX_010, 0x1, 0x0, 0x7, B31),
- EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_16, PREFIX_010, 0x1, 0x0, 0xf, B31),
- {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x3, B30 | RD32, E}}},
-
- EXPAND_UNOP_STD_B (O (O_SHLR, SB), "shlr.b", PREFIX_017, 0x1, 0x1, 0x0),
-
- {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{RS8, RD8, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x0, RD8, E}}},
-
- EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_2, PREFIX_017, 0x1, 0x1, 0x4),
- EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_4, PREFIX_017, 0x1, 0x1, 0xa),
- {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x0, RD8, E}}},
-
- EXPAND_UNOP_STD_W (O (O_SHLR, SW), "shlr.w", PREFIX_015, 0x1, 0x1, 0x1),
-
- {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{RS8, RD16, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x1, RD16, E}}},
-
- EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_2, PREFIX_015, 0x1, 0x1, 0x5),
- EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_4, PREFIX_015, 0x1, 0x1, 0x2),
- EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_8, PREFIX_015, 0x1, 0x1, 0x6),
- {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x1, RD16, E}}},
-
- EXPAND_UNOP_STD_L (O (O_SHLR, SL), "shlr.l", PREFIX_010, 0x1, 0x1, 0x3),
-
- {O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{RS8, RD32, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x3, B30 | RD32, E}}},
-
- EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_2, PREFIX_010, 0x1, 0x1, 0x7, B30),
- EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_4, PREFIX_010, 0x1, 0x1, 0x3, B31),
- EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_8, PREFIX_010, 0x1, 0x1, 0x7, B31),
- EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_16, PREFIX_010, 0x1, 0x1, 0xf, B31),
- {O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x3, B30 | RD32, E}}},
-
- {O (O_SLEEP, SN), AV_H8, 2, "sleep", {{E}}, {{0x0, 0x1, 0x8, 0x0, E}}},
-
- {O (O_STC, SB), AV_H8, 2, "stc", {{CCR | SRC, RD8, E}}, {{0x0, 0x2, B30 | CCR | SRC, RD8, E}}},
- {O (O_STC, SB), AV_H8S, 2, "stc", {{EXR | SRC, RD8, E}}, {{0x0, 0x2, B30 | EXR | SRC, RD8, E}}},
- {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, RDIND, E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND, IGNORE, E}}},
- {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, RDIND, E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND, IGNORE, E}}},
- {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, RDPREDEC, E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}},
- {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, RDPREDEC, E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}},
- {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, DISP16DST, E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG, IGNORE, DSTDISP16LIST, E}}},
- {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, DISP16DST, E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG, IGNORE, DSTDISP16LIST, E}}},
- {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, DISP32DST, E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}},
- {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, DISP32DST, E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}},
- {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}},
- {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}},
- {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}},
- {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}},
- {O (O_STC, SL), AV_H8SX, 0, "stc", {{B30 | VBR_SBR | SRC, RD32, E}}, {{0x0, 0x2, B30 | VBR_SBR | SRC, RD32, E}}},
-
-
- EXPAND_TWOOP_B (O (O_SUB, SB), "sub.b", 0xa, 0x1, 0x8, 0x3, B01),
-
- {O (O_SUB, SW), AV_H8, 2, "sub.w", {{RS16, RD16, E}}, {{0x1, 0x9, RS16, RD16, E}}},
- {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RD16, E}}, {{0x1, 0xa, B30 | IMM3NZ, RD16, E}}},
- {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}},
- {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}},
- {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}},
- EXPAND_TWOOP_W (O (O_SUB, SW), "sub.w", 0x1, 0x9, 0x3),
-
- {O (O_SUB, SL), AV_H8H, 6, "sub.l", {{RS32, RD32, E}}, {{0x1, 0xa, B31 | RS32, B30 | RD32, E}}},
- {O (O_SUB, SL), AV_H8SX, 0, "sub.l", {{IMM3NZ_NS, RD32, E}}, {{0x1, 0xa, B31 | IMM3NZ, B31 | RD32, E}}},
- EXPAND_TWOOP_L (O (O_SUB, SL), "sub.l", 0x3),
-
- {O (O_SUBS, SL), AV_H8, 2, "subs", {{KBIT, RDP, E}}, {{0x1, 0xB,KBIT, RDP, E}}},
-
- {O (O_SUBX, SB), AV_H8, 2, "subx", {{IMM8, RD8, E}}, {{0xb, RD8, IMM8LIST, E}}},
- {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0xb, IGNORE, IMM8LIST, E}}},
- {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0xb, IGNORE, IMM8LIST, E}}},
- {O (O_SUBX, SB), AV_H8, 2, "subx", {{RS8, RD8, E}}, {{0x1, 0xe, RS8, RD8, E}}},
- {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x1, 0xe, RS8, IGNORE, E}}},
- {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x1, 0xe, RS8, IGNORE, E}}},
- {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, 0x1, 0xe, IGNORE, RD8, E}}},
- {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RD8, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x1, 0xe, IGNORE, RD8, E}}},
- {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND, RDIND, E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}},
- {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}},
-
- {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RD16, E}}, {{PREFIX_0151, 0x7, 0x9, 0x3, RD16, IMM16LIST, E}}},
- {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}},
- {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}},
- {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RD16, E}}, {{PREFIX_0151, 0x1, 0x9, RS16, RD16, E}}},
- {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}},
- {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}},
- {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}},
- {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RD16, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}},
- {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND, RDIND, E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}},
- {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}},
-
- {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RD32, E}}, {{PREFIX_0101, 0x7, 0xa, 0x3, RD32, IMM32LIST, E}}},
- {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}},
- {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}},
- {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RD32, E}}, {{PREFIX_0101, 0x1, 0xa, B31 | RS32, B30 | RD32, E}}},
- {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}},
- {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}},
- {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND, RD32, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}},
- {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}},
- {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}},
- {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}},
-
- {O (O_TRAPA, SB), AV_H8H, 2, "trapa", {{IMM2, E}}, {{0x5, 0x7, IMM2, IGNORE, E}}},
- {O (O_TAS, SB), AV_H8H, 2, "tas", {{RSIND, E}}, {{0x0, 0x1, 0xe, 0x0, 0x7, 0xb, B30 | RSIND, 0xc, E}}},
-
- {O (O_XOR, SB), AV_H8, 2, "xor.b", {{IMM8, RD8, E}}, {{0xd, RD8, IMM8LIST, E}}},
- EXPAND_TWOOP_B (O (O_XOR, SB), "xor.b", 0xd, 0x1, 0x5, 0x5, 0),
-
- {O (O_XOR, SW), AV_H8, 2, "xor.w", {{RS16, RD16, E}}, {{0x6, 0x5, RS16, RD16, E}}},
- EXPAND_TWOOP_W (O (O_XOR, SW), "xor.w", 0x6, 0x5, 0x5),
-
- {O (O_XOR, SL), AV_H8H, 2, "xor.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x5, B30 | RS32, B30 | RD32, E}}},
- EXPAND_TWOOP_L (O (O_XOR, SL), "xor.l", 0x5),
-
- {O (O_XORC, SB), AV_H8, 2, "xorc", {{IMM8, CCR | DST, E}}, {{0x0, 0x5, IMM8LIST, E}}},
- {O (O_XORC, SB), AV_H8S, 2, "xorc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x5, IMM8LIST, E}}},
-
- {O (O_CLRMAC, SN), AV_H8S, 2, "clrmac", {{E}}, {{0x0, 0x1, 0xa, 0x0, E}}},
- {O (O_MAC, SW), AV_H8S, 2, "mac", {{RSPOSTINC, RDPOSTINC, E}}, {{0x0, 0x1, 0x6, 0x0, 0x6, 0xd, B30 | RSPOSTINC, B30 | RDPOSTINC, E}}},
- {O (O_LDMAC, SL), AV_H8S, 2, "ldmac", {{RS32, MD32, E}}, {{0x0, 0x3, MD32, RS32, E}}},
- {O (O_STMAC, SL), AV_H8S, 2, "stmac", {{MS32, RD32, E}}, {{0x0, 0x2, MS32, RD32, E}}},
- {O (O_LDM, SL), AV_H8H, 6, "ldm.l", {{RSPOSTINC, RD32, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0x7, B30 | RD32, E}}},
- {O (O_STM, SL), AV_H8H, 6, "stm.l", {{RS32, RDPREDEC, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0xF, B30 | RS32, E}}},
- {0, 0, 0, NULL, {{0, 0, 0}}, {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}}
-};
-#else
-extern const struct h8_opcode h8_opcodes[];
-#endif
-
h8300.h
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: score-datadep.h
===================================================================
--- score-datadep.h (revision 816)
+++ score-datadep.h (nonexistent)
@@ -1,65 +0,0 @@
-/* score-datadep.h -- Score Instructions data dependency table
- Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
- Contributed by:
- Brain.lin (brain.lin@sunplusct.com)
- Mei Ligang (ligang@sunnorth.com.cn)
- Pei-Lin Tsai (pltsai@sunplus.com)
-
- This file is part of GAS, the GNU Assembler.
-
- GAS is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- GAS is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GAS; see the file COPYING. If not, write to the Free
- Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
- Boston, MA 02110-1301, USA. */
-
-#ifndef SCORE_DATA_DEPENDENCY_H
-#define SCORE_DATA_DEPENDENCY_H
-
-#define INSN_NAME_LEN 16
-
-enum insn_type_for_dependency
-{
- D_mtcr,
- D_all_insn
-};
-
-struct insn_to_dependency
-{
- char *insn_name;
- enum insn_type_for_dependency type;
-};
-
-struct data_dependency
-{
- enum insn_type_for_dependency pre_insn_type;
- char pre_reg[6];
- enum insn_type_for_dependency cur_insn_type;
- char cur_reg[6];
- int bubblenum_7;
- int bubblenum_3;
- int warn_or_error; /* warning - 0; error - 1 */
-};
-
-static const struct insn_to_dependency insn_to_dependency_table[] =
-{
- /* move spectial instruction. */
- {"mtcr", D_mtcr},
-};
-
-static const struct data_dependency data_dependency_table[] =
-{
- /* Status regiser. */
- {D_mtcr, "cr0", D_all_insn, "", 5, 1, 0},
-};
-
-#endif
score-datadep.h
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: bfin.h
===================================================================
--- bfin.h (revision 816)
+++ bfin.h (nonexistent)
@@ -1,1698 +0,0 @@
-/* bfin.h -- Header file for ADI Blackfin opcode table
- Copyright 2005 Free Software Foundation, Inc.
-
-This file is part of GDB, GAS, and the GNU binutils.
-
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
-
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
-/* Common to all DSP32 instructions. */
-#define BIT_MULTI_INS 0x0800
-
-/* This just sets the multi instruction bit of a DSP32 instruction. */
-#define SET_MULTI_INSTRUCTION_BIT(x) x->value |= BIT_MULTI_INS;
-
-
-/* DSP instructions (32 bit) */
-
-/* dsp32mac
-+----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
-|.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......|
-+----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned long opcode;
- int bits_src1;
- int mask_src1;
- int bits_src0;
- int mask_src0;
- int bits_dst;
- int mask_dst;
- int bits_h10;
- int mask_h10;
- int bits_h00;
- int mask_h00;
- int bits_op0;
- int mask_op0;
- int bits_w0;
- int mask_w0;
- int bits_h11;
- int mask_h11;
- int bits_h01;
- int mask_h01;
- int bits_op1;
- int mask_op1;
- int bits_w1;
- int mask_w1;
- int bits_P;
- int mask_P;
- int bits_MM;
- int mask_MM;
- int bits_mmod;
- int mask_mmod;
- int bits_code2;
- int mask_code2;
- int bits_M;
- int mask_M;
- int bits_code;
- int mask_code;
-} DSP32Mac;
-
-#define DSP32Mac_opcode 0xc0000000
-#define DSP32Mac_src1_bits 0
-#define DSP32Mac_src1_mask 0x7
-#define DSP32Mac_src0_bits 3
-#define DSP32Mac_src0_mask 0x7
-#define DSP32Mac_dst_bits 6
-#define DSP32Mac_dst_mask 0x7
-#define DSP32Mac_h10_bits 9
-#define DSP32Mac_h10_mask 0x1
-#define DSP32Mac_h00_bits 10
-#define DSP32Mac_h00_mask 0x1
-#define DSP32Mac_op0_bits 11
-#define DSP32Mac_op0_mask 0x3
-#define DSP32Mac_w0_bits 13
-#define DSP32Mac_w0_mask 0x1
-#define DSP32Mac_h11_bits 14
-#define DSP32Mac_h11_mask 0x1
-#define DSP32Mac_h01_bits 15
-#define DSP32Mac_h01_mask 0x1
-#define DSP32Mac_op1_bits 16
-#define DSP32Mac_op1_mask 0x3
-#define DSP32Mac_w1_bits 18
-#define DSP32Mac_w1_mask 0x1
-#define DSP32Mac_p_bits 19
-#define DSP32Mac_p_mask 0x1
-#define DSP32Mac_MM_bits 20
-#define DSP32Mac_MM_mask 0x1
-#define DSP32Mac_mmod_bits 21
-#define DSP32Mac_mmod_mask 0xf
-#define DSP32Mac_code2_bits 25
-#define DSP32Mac_code2_mask 0x3
-#define DSP32Mac_M_bits 27
-#define DSP32Mac_M_mask 0x1
-#define DSP32Mac_code_bits 28
-#define DSP32Mac_code_mask 0xf
-
-#define init_DSP32Mac \
-{ \
- DSP32Mac_opcode, \
- DSP32Mac_src1_bits, DSP32Mac_src1_mask, \
- DSP32Mac_src0_bits, DSP32Mac_src0_mask, \
- DSP32Mac_dst_bits, DSP32Mac_dst_mask, \
- DSP32Mac_h10_bits, DSP32Mac_h10_mask, \
- DSP32Mac_h00_bits, DSP32Mac_h00_mask, \
- DSP32Mac_op0_bits, DSP32Mac_op0_mask, \
- DSP32Mac_w0_bits, DSP32Mac_w0_mask, \
- DSP32Mac_h11_bits, DSP32Mac_h11_mask, \
- DSP32Mac_h01_bits, DSP32Mac_h01_mask, \
- DSP32Mac_op1_bits, DSP32Mac_op1_mask, \
- DSP32Mac_w1_bits, DSP32Mac_w1_mask, \
- DSP32Mac_p_bits, DSP32Mac_p_mask, \
- DSP32Mac_MM_bits, DSP32Mac_MM_mask, \
- DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \
- DSP32Mac_code2_bits, DSP32Mac_code2_mask, \
- DSP32Mac_M_bits, DSP32Mac_M_mask, \
- DSP32Mac_code_bits, DSP32Mac_code_mask \
-};
-
-/* dsp32mult
-+----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
-|.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......|
-+----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef DSP32Mac DSP32Mult;
-#define DSP32Mult_opcode 0xc2000000
-
-#define init_DSP32Mult \
-{ \
- DSP32Mult_opcode, \
- DSP32Mac_src1_bits, DSP32Mac_src1_mask, \
- DSP32Mac_src0_bits, DSP32Mac_src0_mask, \
- DSP32Mac_dst_bits, DSP32Mac_dst_mask, \
- DSP32Mac_h10_bits, DSP32Mac_h10_mask, \
- DSP32Mac_h00_bits, DSP32Mac_h00_mask, \
- DSP32Mac_op0_bits, DSP32Mac_op0_mask, \
- DSP32Mac_w0_bits, DSP32Mac_w0_mask, \
- DSP32Mac_h11_bits, DSP32Mac_h11_mask, \
- DSP32Mac_h01_bits, DSP32Mac_h01_mask, \
- DSP32Mac_op1_bits, DSP32Mac_op1_mask, \
- DSP32Mac_w1_bits, DSP32Mac_w1_mask, \
- DSP32Mac_p_bits, DSP32Mac_p_mask, \
- DSP32Mac_MM_bits, DSP32Mac_MM_mask, \
- DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \
- DSP32Mac_code2_bits, DSP32Mac_code2_mask, \
- DSP32Mac_M_bits, DSP32Mac_M_mask, \
- DSP32Mac_code_bits, DSP32Mac_code_mask \
-};
-
-/* dsp32alu
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
-|.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned long opcode;
- int bits_src1;
- int mask_src1;
- int bits_src0;
- int mask_src0;
- int bits_dst1;
- int mask_dst1;
- int bits_dst0;
- int mask_dst0;
- int bits_x;
- int mask_x;
- int bits_s;
- int mask_s;
- int bits_aop;
- int mask_aop;
- int bits_aopcde;
- int mask_aopcde;
- int bits_HL;
- int mask_HL;
- int bits_dontcare;
- int mask_dontcare;
- int bits_code2;
- int mask_code2;
- int bits_M;
- int mask_M;
- int bits_code;
- int mask_code;
-} DSP32Alu;
-
-#define DSP32Alu_opcode 0xc4000000
-#define DSP32Alu_src1_bits 0
-#define DSP32Alu_src1_mask 0x7
-#define DSP32Alu_src0_bits 3
-#define DSP32Alu_src0_mask 0x7
-#define DSP32Alu_dst1_bits 6
-#define DSP32Alu_dst1_mask 0x7
-#define DSP32Alu_dst0_bits 9
-#define DSP32Alu_dst0_mask 0x7
-#define DSP32Alu_x_bits 12
-#define DSP32Alu_x_mask 0x1
-#define DSP32Alu_s_bits 13
-#define DSP32Alu_s_mask 0x1
-#define DSP32Alu_aop_bits 14
-#define DSP32Alu_aop_mask 0x3
-#define DSP32Alu_aopcde_bits 16
-#define DSP32Alu_aopcde_mask 0x1f
-#define DSP32Alu_HL_bits 21
-#define DSP32Alu_HL_mask 0x1
-#define DSP32Alu_dontcare_bits 22
-#define DSP32Alu_dontcare_mask 0x7
-#define DSP32Alu_code2_bits 25
-#define DSP32Alu_code2_mask 0x3
-#define DSP32Alu_M_bits 27
-#define DSP32Alu_M_mask 0x1
-#define DSP32Alu_code_bits 28
-#define DSP32Alu_code_mask 0xf
-
-#define init_DSP32Alu \
-{ \
- DSP32Alu_opcode, \
- DSP32Alu_src1_bits, DSP32Alu_src1_mask, \
- DSP32Alu_src0_bits, DSP32Alu_src0_mask, \
- DSP32Alu_dst1_bits, DSP32Alu_dst1_mask, \
- DSP32Alu_dst0_bits, DSP32Alu_dst0_mask, \
- DSP32Alu_x_bits, DSP32Alu_x_mask, \
- DSP32Alu_s_bits, DSP32Alu_s_mask, \
- DSP32Alu_aop_bits, DSP32Alu_aop_mask, \
- DSP32Alu_aopcde_bits, DSP32Alu_aopcde_mask, \
- DSP32Alu_HL_bits, DSP32Alu_HL_mask, \
- DSP32Alu_dontcare_bits, DSP32Alu_dontcare_mask, \
- DSP32Alu_code2_bits, DSP32Alu_code2_mask, \
- DSP32Alu_M_bits, DSP32Alu_M_mask, \
- DSP32Alu_code_bits, DSP32Alu_code_mask \
-};
-
-/* dsp32shift
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
-|.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned long opcode;
- int bits_src1;
- int mask_src1;
- int bits_src0;
- int mask_src0;
- int bits_dst1;
- int mask_dst1;
- int bits_dst0;
- int mask_dst0;
- int bits_HLs;
- int mask_HLs;
- int bits_sop;
- int mask_sop;
- int bits_sopcde;
- int mask_sopcde;
- int bits_dontcare;
- int mask_dontcare;
- int bits_code2;
- int mask_code2;
- int bits_M;
- int mask_M;
- int bits_code;
- int mask_code;
-} DSP32Shift;
-
-#define DSP32Shift_opcode 0xc6000000
-#define DSP32Shift_src1_bits 0
-#define DSP32Shift_src1_mask 0x7
-#define DSP32Shift_src0_bits 3
-#define DSP32Shift_src0_mask 0x7
-#define DSP32Shift_dst1_bits 6
-#define DSP32Shift_dst1_mask 0x7
-#define DSP32Shift_dst0_bits 9
-#define DSP32Shift_dst0_mask 0x7
-#define DSP32Shift_HLs_bits 12
-#define DSP32Shift_HLs_mask 0x3
-#define DSP32Shift_sop_bits 14
-#define DSP32Shift_sop_mask 0x3
-#define DSP32Shift_sopcde_bits 16
-#define DSP32Shift_sopcde_mask 0x1f
-#define DSP32Shift_dontcare_bits 21
-#define DSP32Shift_dontcare_mask 0x3
-#define DSP32Shift_code2_bits 23
-#define DSP32Shift_code2_mask 0xf
-#define DSP32Shift_M_bits 27
-#define DSP32Shift_M_mask 0x1
-#define DSP32Shift_code_bits 28
-#define DSP32Shift_code_mask 0xf
-
-#define init_DSP32Shift \
-{ \
- DSP32Shift_opcode, \
- DSP32Shift_src1_bits, DSP32Shift_src1_mask, \
- DSP32Shift_src0_bits, DSP32Shift_src0_mask, \
- DSP32Shift_dst1_bits, DSP32Shift_dst1_mask, \
- DSP32Shift_dst0_bits, DSP32Shift_dst0_mask, \
- DSP32Shift_HLs_bits, DSP32Shift_HLs_mask, \
- DSP32Shift_sop_bits, DSP32Shift_sop_mask, \
- DSP32Shift_sopcde_bits, DSP32Shift_sopcde_mask, \
- DSP32Shift_dontcare_bits, DSP32Shift_dontcare_mask, \
- DSP32Shift_code2_bits, DSP32Shift_code2_mask, \
- DSP32Shift_M_bits, DSP32Shift_M_mask, \
- DSP32Shift_code_bits, DSP32Shift_code_mask \
-};
-
-/* dsp32shiftimm
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
-|.sop...|.HLs...|.dst0......|.immag.................|.src1......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned long opcode;
- int bits_src1;
- int mask_src1;
- int bits_immag;
- int mask_immag;
- int bits_dst0;
- int mask_dst0;
- int bits_HLs;
- int mask_HLs;
- int bits_sop;
- int mask_sop;
- int bits_sopcde;
- int mask_sopcde;
- int bits_dontcare;
- int mask_dontcare;
- int bits_code2;
- int mask_code2;
- int bits_M;
- int mask_M;
- int bits_code;
- int mask_code;
-} DSP32ShiftImm;
-
-#define DSP32ShiftImm_opcode 0xc6800000
-#define DSP32ShiftImm_src1_bits 0
-#define DSP32ShiftImm_src1_mask 0x7
-#define DSP32ShiftImm_immag_bits 3
-#define DSP32ShiftImm_immag_mask 0x3f
-#define DSP32ShiftImm_dst0_bits 9
-#define DSP32ShiftImm_dst0_mask 0x7
-#define DSP32ShiftImm_HLs_bits 12
-#define DSP32ShiftImm_HLs_mask 0x3
-#define DSP32ShiftImm_sop_bits 14
-#define DSP32ShiftImm_sop_mask 0x3
-#define DSP32ShiftImm_sopcde_bits 16
-#define DSP32ShiftImm_sopcde_mask 0x1f
-#define DSP32ShiftImm_dontcare_bits 21
-#define DSP32ShiftImm_dontcare_mask 0x3
-#define DSP32ShiftImm_code2_bits 23
-#define DSP32ShiftImm_code2_mask 0xf
-#define DSP32ShiftImm_M_bits 27
-#define DSP32ShiftImm_M_mask 0x1
-#define DSP32ShiftImm_code_bits 28
-#define DSP32ShiftImm_code_mask 0xf
-
-#define init_DSP32ShiftImm \
-{ \
- DSP32ShiftImm_opcode, \
- DSP32ShiftImm_src1_bits, DSP32ShiftImm_src1_mask, \
- DSP32ShiftImm_immag_bits, DSP32ShiftImm_immag_mask, \
- DSP32ShiftImm_dst0_bits, DSP32ShiftImm_dst0_mask, \
- DSP32ShiftImm_HLs_bits, DSP32ShiftImm_HLs_mask, \
- DSP32ShiftImm_sop_bits, DSP32ShiftImm_sop_mask, \
- DSP32ShiftImm_sopcde_bits, DSP32ShiftImm_sopcde_mask, \
- DSP32ShiftImm_dontcare_bits, DSP32ShiftImm_dontcare_mask, \
- DSP32ShiftImm_code2_bits, DSP32ShiftImm_code2_mask, \
- DSP32ShiftImm_M_bits, DSP32ShiftImm_M_mask, \
- DSP32ShiftImm_code_bits, DSP32ShiftImm_code_mask \
-};
-
-/* LOAD / STORE */
-
-/* LDSTidxI
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
-|.offset........................................................|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned long opcode;
- int bits_offset;
- int mask_offset;
- int bits_reg;
- int mask_reg;
- int bits_ptr;
- int mask_ptr;
- int bits_sz;
- int mask_sz;
- int bits_Z;
- int mask_Z;
- int bits_W;
- int mask_W;
- int bits_code;
- int mask_code;
-} LDSTidxI;
-
-#define LDSTidxI_opcode 0xe4000000
-#define LDSTidxI_offset_bits 0
-#define LDSTidxI_offset_mask 0xffff
-#define LDSTidxI_reg_bits 16
-#define LDSTidxI_reg_mask 0x7
-#define LDSTidxI_ptr_bits 19
-#define LDSTidxI_ptr_mask 0x7
-#define LDSTidxI_sz_bits 22
-#define LDSTidxI_sz_mask 0x3
-#define LDSTidxI_Z_bits 24
-#define LDSTidxI_Z_mask 0x1
-#define LDSTidxI_W_bits 25
-#define LDSTidxI_W_mask 0x1
-#define LDSTidxI_code_bits 26
-#define LDSTidxI_code_mask 0x3f
-
-#define init_LDSTidxI \
-{ \
- LDSTidxI_opcode, \
- LDSTidxI_offset_bits, LDSTidxI_offset_mask, \
- LDSTidxI_reg_bits, LDSTidxI_reg_mask, \
- LDSTidxI_ptr_bits, LDSTidxI_ptr_mask, \
- LDSTidxI_sz_bits, LDSTidxI_sz_mask, \
- LDSTidxI_Z_bits, LDSTidxI_Z_mask, \
- LDSTidxI_W_bits, LDSTidxI_W_mask, \
- LDSTidxI_code_bits, LDSTidxI_code_mask \
-};
-
-
-/* LDST
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_reg;
- int mask_reg;
- int bits_ptr;
- int mask_ptr;
- int bits_Z;
- int mask_Z;
- int bits_aop;
- int mask_aop;
- int bits_W;
- int mask_W;
- int bits_sz;
- int mask_sz;
- int bits_code;
- int mask_code;
-} LDST;
-
-#define LDST_opcode 0x9000
-#define LDST_reg_bits 0
-#define LDST_reg_mask 0x7
-#define LDST_ptr_bits 3
-#define LDST_ptr_mask 0x7
-#define LDST_Z_bits 6
-#define LDST_Z_mask 0x1
-#define LDST_aop_bits 7
-#define LDST_aop_mask 0x3
-#define LDST_W_bits 9
-#define LDST_W_mask 0x1
-#define LDST_sz_bits 10
-#define LDST_sz_mask 0x3
-#define LDST_code_bits 12
-#define LDST_code_mask 0xf
-
-#define init_LDST \
-{ \
- LDST_opcode, \
- LDST_reg_bits, LDST_reg_mask, \
- LDST_ptr_bits, LDST_ptr_mask, \
- LDST_Z_bits, LDST_Z_mask, \
- LDST_aop_bits, LDST_aop_mask, \
- LDST_W_bits, LDST_W_mask, \
- LDST_sz_bits, LDST_sz_mask, \
- LDST_code_bits, LDST_code_mask \
-};
-
-/* LDSTii
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_reg;
- int mask_reg;
- int bits_ptr;
- int mask_ptr;
- int bits_offset;
- int mask_offset;
- int bits_op;
- int mask_op;
- int bits_W;
- int mask_W;
- int bits_code;
- int mask_code;
-} LDSTii;
-
-#define LDSTii_opcode 0xa000
-#define LDSTii_reg_bit 0
-#define LDSTii_reg_mask 0x7
-#define LDSTii_ptr_bit 3
-#define LDSTii_ptr_mask 0x7
-#define LDSTii_offset_bit 6
-#define LDSTii_offset_mask 0xf
-#define LDSTii_op_bit 10
-#define LDSTii_op_mask 0x3
-#define LDSTii_W_bit 12
-#define LDSTii_W_mask 0x1
-#define LDSTii_code_bit 13
-#define LDSTii_code_mask 0x7
-
-#define init_LDSTii \
-{ \
- LDSTii_opcode, \
- LDSTii_reg_bit, LDSTii_reg_mask, \
- LDSTii_ptr_bit, LDSTii_ptr_mask, \
- LDSTii_offset_bit, LDSTii_offset_mask, \
- LDSTii_op_bit, LDSTii_op_mask, \
- LDSTii_W_bit, LDSTii_W_mask, \
- LDSTii_code_bit, LDSTii_code_mask \
-};
-
-
-/* LDSTiiFP
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_reg;
- int mask_reg;
- int bits_offset;
- int mask_offset;
- int bits_W;
- int mask_W;
- int bits_code;
- int mask_code;
-} LDSTiiFP;
-
-#define LDSTiiFP_opcode 0xb800
-#define LDSTiiFP_reg_bits 0
-#define LDSTiiFP_reg_mask 0xf
-#define LDSTiiFP_offset_bits 4
-#define LDSTiiFP_offset_mask 0x1f
-#define LDSTiiFP_W_bits 9
-#define LDSTiiFP_W_mask 0x1
-#define LDSTiiFP_code_bits 10
-#define LDSTiiFP_code_mask 0x3f
-
-#define init_LDSTiiFP \
-{ \
- LDSTiiFP_opcode, \
- LDSTiiFP_reg_bits, LDSTiiFP_reg_mask, \
- LDSTiiFP_offset_bits, LDSTiiFP_offset_mask, \
- LDSTiiFP_W_bits, LDSTiiFP_W_mask, \
- LDSTiiFP_code_bits, LDSTiiFP_code_mask \
-};
-
-/* dspLDST
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_reg;
- int mask_reg;
- int bits_i;
- int mask_i;
- int bits_m;
- int mask_m;
- int bits_aop;
- int mask_aop;
- int bits_W;
- int mask_W;
- int bits_code;
- int mask_code;
-} DspLDST;
-
-#define DspLDST_opcode 0x9c00
-#define DspLDST_reg_bits 0
-#define DspLDST_reg_mask 0x7
-#define DspLDST_i_bits 3
-#define DspLDST_i_mask 0x3
-#define DspLDST_m_bits 5
-#define DspLDST_m_mask 0x3
-#define DspLDST_aop_bits 7
-#define DspLDST_aop_mask 0x3
-#define DspLDST_W_bits 9
-#define DspLDST_W_mask 0x1
-#define DspLDST_code_bits 10
-#define DspLDST_code_mask 0x3f
-
-#define init_DspLDST \
-{ \
- DspLDST_opcode, \
- DspLDST_reg_bits, DspLDST_reg_mask, \
- DspLDST_i_bits, DspLDST_i_mask, \
- DspLDST_m_bits, DspLDST_m_mask, \
- DspLDST_aop_bits, DspLDST_aop_mask, \
- DspLDST_W_bits, DspLDST_W_mask, \
- DspLDST_code_bits, DspLDST_code_mask \
-};
-
-
-/* LDSTpmod
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_ptr;
- int mask_ptr;
- int bits_idx;
- int mask_idx;
- int bits_reg;
- int mask_reg;
- int bits_aop;
- int mask_aop;
- int bits_W;
- int mask_W;
- int bits_code;
- int mask_code;
-} LDSTpmod;
-
-#define LDSTpmod_opcode 0x8000
-#define LDSTpmod_ptr_bits 0
-#define LDSTpmod_ptr_mask 0x7
-#define LDSTpmod_idx_bits 3
-#define LDSTpmod_idx_mask 0x7
-#define LDSTpmod_reg_bits 6
-#define LDSTpmod_reg_mask 0x7
-#define LDSTpmod_aop_bits 9
-#define LDSTpmod_aop_mask 0x3
-#define LDSTpmod_W_bits 11
-#define LDSTpmod_W_mask 0x1
-#define LDSTpmod_code_bits 12
-#define LDSTpmod_code_mask 0xf
-
-#define init_LDSTpmod \
-{ \
- LDSTpmod_opcode, \
- LDSTpmod_ptr_bits, LDSTpmod_ptr_mask, \
- LDSTpmod_idx_bits, LDSTpmod_idx_mask, \
- LDSTpmod_reg_bits, LDSTpmod_reg_mask, \
- LDSTpmod_aop_bits, LDSTpmod_aop_mask, \
- LDSTpmod_W_bits, LDSTpmod_W_mask, \
- LDSTpmod_code_bits, LDSTpmod_code_mask \
-};
-
-
-/* LOGI2op
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_dst;
- int mask_dst;
- int bits_src;
- int mask_src;
- int bits_opc;
- int mask_opc;
- int bits_code;
- int mask_code;
-} LOGI2op;
-
-#define LOGI2op_opcode 0x4800
-#define LOGI2op_dst_bits 0
-#define LOGI2op_dst_mask 0x7
-#define LOGI2op_src_bits 3
-#define LOGI2op_src_mask 0x1f
-#define LOGI2op_opc_bits 8
-#define LOGI2op_opc_mask 0x7
-#define LOGI2op_code_bits 11
-#define LOGI2op_code_mask 0x1f
-
-#define init_LOGI2op \
-{ \
- LOGI2op_opcode, \
- LOGI2op_dst_bits, LOGI2op_dst_mask, \
- LOGI2op_src_bits, LOGI2op_src_mask, \
- LOGI2op_opc_bits, LOGI2op_opc_mask, \
- LOGI2op_code_bits, LOGI2op_code_mask \
-};
-
-
-/* ALU2op
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_dst;
- int mask_dst;
- int bits_src;
- int mask_src;
- int bits_opc;
- int mask_opc;
- int bits_code;
- int mask_code;
-} ALU2op;
-
-#define ALU2op_opcode 0x4000
-#define ALU2op_dst_bits 0
-#define ALU2op_dst_mask 0x7
-#define ALU2op_src_bits 3
-#define ALU2op_src_mask 0x7
-#define ALU2op_opc_bits 6
-#define ALU2op_opc_mask 0xf
-#define ALU2op_code_bits 10
-#define ALU2op_code_mask 0x3f
-
-#define init_ALU2op \
-{ \
- ALU2op_opcode, \
- ALU2op_dst_bits, ALU2op_dst_mask, \
- ALU2op_src_bits, ALU2op_src_mask, \
- ALU2op_opc_bits, ALU2op_opc_mask, \
- ALU2op_code_bits, ALU2op_code_mask \
-};
-
-
-/* BRCC
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_offset;
- int mask_offset;
- int bits_B;
- int mask_B;
- int bits_T;
- int mask_T;
- int bits_code;
- int mask_code;
-} BRCC;
-
-#define BRCC_opcode 0x1000
-#define BRCC_offset_bits 0
-#define BRCC_offset_mask 0x3ff
-#define BRCC_B_bits 10
-#define BRCC_B_mask 0x1
-#define BRCC_T_bits 11
-#define BRCC_T_mask 0x1
-#define BRCC_code_bits 12
-#define BRCC_code_mask 0xf
-
-#define init_BRCC \
-{ \
- BRCC_opcode, \
- BRCC_offset_bits, BRCC_offset_mask, \
- BRCC_B_bits, BRCC_B_mask, \
- BRCC_T_bits, BRCC_T_mask, \
- BRCC_code_bits, BRCC_code_mask \
-};
-
-
-/* UJUMP
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 1 | 0 |.offset........................................|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_offset;
- int mask_offset;
- int bits_code;
- int mask_code;
-} UJump;
-
-#define UJump_opcode 0x2000
-#define UJump_offset_bits 0
-#define UJump_offset_mask 0xfff
-#define UJump_code_bits 12
-#define UJump_code_mask 0xf
-
-#define init_UJump \
-{ \
- UJump_opcode, \
- UJump_offset_bits, UJump_offset_mask, \
- UJump_code_bits, UJump_code_mask \
-};
-
-
-/* ProgCtrl
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_poprnd;
- int mask_poprnd;
- int bits_prgfunc;
- int mask_prgfunc;
- int bits_code;
- int mask_code;
-} ProgCtrl;
-
-#define ProgCtrl_opcode 0x0000
-#define ProgCtrl_poprnd_bits 0
-#define ProgCtrl_poprnd_mask 0xf
-#define ProgCtrl_prgfunc_bits 4
-#define ProgCtrl_prgfunc_mask 0xf
-#define ProgCtrl_code_bits 8
-#define ProgCtrl_code_mask 0xff
-
-#define init_ProgCtrl \
-{ \
- ProgCtrl_opcode, \
- ProgCtrl_poprnd_bits, ProgCtrl_poprnd_mask, \
- ProgCtrl_prgfunc_bits, ProgCtrl_prgfunc_mask, \
- ProgCtrl_code_bits, ProgCtrl_code_mask \
-};
-
-/* CALLa
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
-|.lsw...........................................................|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-
-typedef struct
-{
- unsigned long opcode;
- int bits_addr;
- int mask_addr;
- int bits_S;
- int mask_S;
- int bits_code;
- int mask_code;
-} CALLa;
-
-#define CALLa_opcode 0xe2000000
-#define CALLa_addr_bits 0
-#define CALLa_addr_mask 0xffffff
-#define CALLa_S_bits 24
-#define CALLa_S_mask 0x1
-#define CALLa_code_bits 25
-#define CALLa_code_mask 0x7f
-
-#define init_CALLa \
-{ \
- CALLa_opcode, \
- CALLa_addr_bits, CALLa_addr_mask, \
- CALLa_S_bits, CALLa_S_mask, \
- CALLa_code_bits, CALLa_code_mask \
-};
-
-
-/* pseudoDEBUG
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_reg;
- int mask_reg;
- int bits_grp;
- int mask_grp;
- int bits_fn;
- int mask_fn;
- int bits_code;
- int mask_code;
-} PseudoDbg;
-
-#define PseudoDbg_opcode 0xf800
-#define PseudoDbg_reg_bits 0
-#define PseudoDbg_reg_mask 0x7
-#define PseudoDbg_grp_bits 3
-#define PseudoDbg_grp_mask 0x7
-#define PseudoDbg_fn_bits 6
-#define PseudoDbg_fn_mask 0x3
-#define PseudoDbg_code_bits 8
-#define PseudoDbg_code_mask 0xff
-
-#define init_PseudoDbg \
-{ \
- PseudoDbg_opcode, \
- PseudoDbg_reg_bits, PseudoDbg_reg_mask, \
- PseudoDbg_grp_bits, PseudoDbg_grp_mask, \
- PseudoDbg_fn_bits, PseudoDbg_fn_mask, \
- PseudoDbg_code_bits, PseudoDbg_code_mask \
-};
-
-/* PseudoDbg_assert
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
-|.expected......................................................|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned long opcode;
- int bits_expected;
- int mask_expected;
- int bits_regtest;
- int mask_regtest;
- int bits_grp;
- int mask_grp;
- int bits_dbgop;
- int mask_dbgop;
- int bits_dontcare;
- int mask_dontcare;
- int bits_code;
- int mask_code;
-} PseudoDbg_Assert;
-
-#define PseudoDbg_Assert_opcode 0xf0000000
-#define PseudoDbg_Assert_expected_bits 0
-#define PseudoDbg_Assert_expected_mask 0xffff
-#define PseudoDbg_Assert_regtest_bits 16
-#define PseudoDbg_Assert_regtest_mask 0x7
-#define PseudoDbg_Assert_grp_bits 19
-#define PseudoDbg_Assert_grp_mask 0x7
-#define PseudoDbg_Assert_dbgop_bits 22
-#define PseudoDbg_Assert_dbgop_mask 0x3
-#define PseudoDbg_Assert_dontcare_bits 24
-#define PseudoDbg_Assert_dontcare_mask 0x7
-#define PseudoDbg_Assert_code_bits 27
-#define PseudoDbg_Assert_code_mask 0x1f
-
-#define init_PseudoDbg_Assert \
-{ \
- PseudoDbg_Assert_opcode, \
- PseudoDbg_Assert_expected_bits, PseudoDbg_Assert_expected_mask, \
- PseudoDbg_Assert_regtest_bits, PseudoDbg_Assert_regtest_mask, \
- PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask, \
- PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, \
- PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask, \
- PseudoDbg_Assert_code_bits, PseudoDbg_Assert_code_mask \
-};
-
-/* CaCTRL
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_reg;
- int mask_reg;
- int bits_op;
- int mask_op;
- int bits_a;
- int mask_a;
- int bits_code;
- int mask_code;
-} CaCTRL;
-
-#define CaCTRL_opcode 0x0240
-#define CaCTRL_reg_bits 0
-#define CaCTRL_reg_mask 0x7
-#define CaCTRL_op_bits 3
-#define CaCTRL_op_mask 0x3
-#define CaCTRL_a_bits 5
-#define CaCTRL_a_mask 0x1
-#define CaCTRL_code_bits 6
-#define CaCTRL_code_mask 0x3fff
-
-#define init_CaCTRL \
-{ \
- CaCTRL_opcode, \
- CaCTRL_reg_bits, CaCTRL_reg_mask, \
- CaCTRL_op_bits, CaCTRL_op_mask, \
- CaCTRL_a_bits, CaCTRL_a_mask, \
- CaCTRL_code_bits, CaCTRL_code_mask \
-};
-
-/* PushPopMultiple
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_pr;
- int mask_pr;
- int bits_dr;
- int mask_dr;
- int bits_W;
- int mask_W;
- int bits_p;
- int mask_p;
- int bits_d;
- int mask_d;
- int bits_code;
- int mask_code;
-} PushPopMultiple;
-
-#define PushPopMultiple_opcode 0x0400
-#define PushPopMultiple_pr_bits 0
-#define PushPopMultiple_pr_mask 0x7
-#define PushPopMultiple_dr_bits 3
-#define PushPopMultiple_dr_mask 0x7
-#define PushPopMultiple_W_bits 6
-#define PushPopMultiple_W_mask 0x1
-#define PushPopMultiple_p_bits 7
-#define PushPopMultiple_p_mask 0x1
-#define PushPopMultiple_d_bits 8
-#define PushPopMultiple_d_mask 0x1
-#define PushPopMultiple_code_bits 8
-#define PushPopMultiple_code_mask 0x1
-
-#define init_PushPopMultiple \
-{ \
- PushPopMultiple_opcode, \
- PushPopMultiple_pr_bits, PushPopMultiple_pr_mask, \
- PushPopMultiple_dr_bits, PushPopMultiple_dr_mask, \
- PushPopMultiple_W_bits, PushPopMultiple_W_mask, \
- PushPopMultiple_p_bits, PushPopMultiple_p_mask, \
- PushPopMultiple_d_bits, PushPopMultiple_d_mask, \
- PushPopMultiple_code_bits, PushPopMultiple_code_mask \
-};
-
-/* PushPopReg
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_reg;
- int mask_reg;
- int bits_grp;
- int mask_grp;
- int bits_W;
- int mask_W;
- int bits_code;
- int mask_code;
-} PushPopReg;
-
-#define PushPopReg_opcode 0x0100
-#define PushPopReg_reg_bits 0
-#define PushPopReg_reg_mask 0x7
-#define PushPopReg_grp_bits 3
-#define PushPopReg_grp_mask 0x7
-#define PushPopReg_W_bits 6
-#define PushPopReg_W_mask 0x1
-#define PushPopReg_code_bits 7
-#define PushPopReg_code_mask 0x1ff
-
-#define init_PushPopReg \
-{ \
- PushPopReg_opcode, \
- PushPopReg_reg_bits, PushPopReg_reg_mask, \
- PushPopReg_grp_bits, PushPopReg_grp_mask, \
- PushPopReg_W_bits, PushPopReg_W_mask, \
- PushPopReg_code_bits, PushPopReg_code_mask, \
-};
-
-/* linkage
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
-|.framesize.....................................................|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned long opcode;
- int bits_framesize;
- int mask_framesize;
- int bits_R;
- int mask_R;
- int bits_code;
- int mask_code;
-} Linkage;
-
-#define Linkage_opcode 0xe8000000
-#define Linkage_framesize_bits 0
-#define Linkage_framesize_mask 0xffff
-#define Linkage_R_bits 16
-#define Linkage_R_mask 0x1
-#define Linkage_code_bits 17
-#define Linkage_code_mask 0x7fff
-
-#define init_Linkage \
-{ \
- Linkage_opcode, \
- Linkage_framesize_bits, Linkage_framesize_mask, \
- Linkage_R_bits, Linkage_R_mask, \
- Linkage_code_bits, Linkage_code_mask \
-};
-
-/* LoopSetup
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
-|.reg...........| - | - |.eoffset...............................|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned long opcode;
- int bits_eoffset;
- int mask_eoffset;
- int bits_dontcare;
- int mask_dontcare;
- int bits_reg;
- int mask_reg;
- int bits_soffset;
- int mask_soffset;
- int bits_c;
- int mask_c;
- int bits_rop;
- int mask_rop;
- int bits_code;
- int mask_code;
-} LoopSetup;
-
-#define LoopSetup_opcode 0xe0800000
-#define LoopSetup_eoffset_bits 0
-#define LoopSetup_eoffset_mask 0x3ff
-#define LoopSetup_dontcare_bits 10
-#define LoopSetup_dontcare_mask 0x3
-#define LoopSetup_reg_bits 12
-#define LoopSetup_reg_mask 0xf
-#define LoopSetup_soffset_bits 16
-#define LoopSetup_soffset_mask 0xf
-#define LoopSetup_c_bits 20
-#define LoopSetup_c_mask 0x1
-#define LoopSetup_rop_bits 21
-#define LoopSetup_rop_mask 0x3
-#define LoopSetup_code_bits 23
-#define LoopSetup_code_mask 0x1ff
-
-#define init_LoopSetup \
-{ \
- LoopSetup_opcode, \
- LoopSetup_eoffset_bits, LoopSetup_eoffset_mask, \
- LoopSetup_dontcare_bits, LoopSetup_dontcare_mask, \
- LoopSetup_reg_bits, LoopSetup_reg_mask, \
- LoopSetup_soffset_bits, LoopSetup_soffset_mask, \
- LoopSetup_c_bits, LoopSetup_c_mask, \
- LoopSetup_rop_bits, LoopSetup_rop_mask, \
- LoopSetup_code_bits, LoopSetup_code_mask \
-};
-
-/* LDIMMhalf
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
-|.hword.........................................................|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned long opcode;
- int bits_hword;
- int mask_hword;
- int bits_reg;
- int mask_reg;
- int bits_grp;
- int mask_grp;
- int bits_S;
- int mask_S;
- int bits_H;
- int mask_H;
- int bits_Z;
- int mask_Z;
- int bits_code;
- int mask_code;
-} LDIMMhalf;
-
-#define LDIMMhalf_opcode 0xe1000000
-#define LDIMMhalf_hword_bits 0
-#define LDIMMhalf_hword_mask 0xffff
-#define LDIMMhalf_reg_bits 16
-#define LDIMMhalf_reg_mask 0x7
-#define LDIMMhalf_grp_bits 19
-#define LDIMMhalf_grp_mask 0x3
-#define LDIMMhalf_S_bits 21
-#define LDIMMhalf_S_mask 0x1
-#define LDIMMhalf_H_bits 22
-#define LDIMMhalf_H_mask 0x1
-#define LDIMMhalf_Z_bits 23
-#define LDIMMhalf_Z_mask 0x1
-#define LDIMMhalf_code_bits 24
-#define LDIMMhalf_code_mask 0xff
-
-#define init_LDIMMhalf \
-{ \
- LDIMMhalf_opcode, \
- LDIMMhalf_hword_bits, LDIMMhalf_hword_mask, \
- LDIMMhalf_reg_bits, LDIMMhalf_reg_mask, \
- LDIMMhalf_grp_bits, LDIMMhalf_grp_mask, \
- LDIMMhalf_S_bits, LDIMMhalf_S_mask, \
- LDIMMhalf_H_bits, LDIMMhalf_H_mask, \
- LDIMMhalf_Z_bits, LDIMMhalf_Z_mask, \
- LDIMMhalf_code_bits, LDIMMhalf_code_mask \
-};
-
-
-/* CC2dreg
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_reg;
- int mask_reg;
- int bits_op;
- int mask_op;
- int bits_code;
- int mask_code;
-} CC2dreg;
-
-#define CC2dreg_opcode 0x0200
-#define CC2dreg_reg_bits 0
-#define CC2dreg_reg_mask 0x7
-#define CC2dreg_op_bits 3
-#define CC2dreg_op_mask 0x3
-#define CC2dreg_code_bits 5
-#define CC2dreg_code_mask 0x7fff
-
-#define init_CC2dreg \
-{ \
- CC2dreg_opcode, \
- CC2dreg_reg_bits, CC2dreg_reg_mask, \
- CC2dreg_op_bits, CC2dreg_op_mask, \
- CC2dreg_code_bits, CC2dreg_code_mask \
-};
-
-
-/* PTR2op
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_dst;
- int mask_dst;
- int bits_src;
- int mask_src;
- int bits_opc;
- int mask_opc;
- int bits_code;
- int mask_code;
-} PTR2op;
-
-#define PTR2op_opcode 0x4400
-#define PTR2op_dst_bits 0
-#define PTR2op_dst_mask 0x7
-#define PTR2op_src_bits 3
-#define PTR2op_src_mask 0x7
-#define PTR2op_opc_bits 6
-#define PTR2op_opc_mask 0x7
-#define PTR2op_code_bits 9
-#define PTR2op_code_mask 0x7f
-
-#define init_PTR2op \
-{ \
- PTR2op_opcode, \
- PTR2op_dst_bits, PTR2op_dst_mask, \
- PTR2op_src_bits, PTR2op_src_mask, \
- PTR2op_opc_bits, PTR2op_opc_mask, \
- PTR2op_code_bits, PTR2op_code_mask \
-};
-
-
-/* COMP3op
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_src0;
- int mask_src0;
- int bits_src1;
- int mask_src1;
- int bits_dst;
- int mask_dst;
- int bits_opc;
- int mask_opc;
- int bits_code;
- int mask_code;
-} COMP3op;
-
-#define COMP3op_opcode 0x5000
-#define COMP3op_src0_bits 0
-#define COMP3op_src0_mask 0x7
-#define COMP3op_src1_bits 3
-#define COMP3op_src1_mask 0x7
-#define COMP3op_dst_bits 6
-#define COMP3op_dst_mask 0x7
-#define COMP3op_opc_bits 9
-#define COMP3op_opc_mask 0x7
-#define COMP3op_code_bits 12
-#define COMP3op_code_mask 0xf
-
-#define init_COMP3op \
-{ \
- COMP3op_opcode, \
- COMP3op_src0_bits, COMP3op_src0_mask, \
- COMP3op_src1_bits, COMP3op_src1_mask, \
- COMP3op_dst_bits, COMP3op_dst_mask, \
- COMP3op_opc_bits, COMP3op_opc_mask, \
- COMP3op_code_bits, COMP3op_code_mask \
-};
-
-/* ccMV
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_src;
- int mask_src;
- int bits_dst;
- int mask_dst;
- int bits_s;
- int mask_s;
- int bits_d;
- int mask_d;
- int bits_T;
- int mask_T;
- int bits_code;
- int mask_code;
-} CCmv;
-
-#define CCmv_opcode 0x0600
-#define CCmv_src_bits 0
-#define CCmv_src_mask 0x7
-#define CCmv_dst_bits 3
-#define CCmv_dst_mask 0x7
-#define CCmv_s_bits 6
-#define CCmv_s_mask 0x1
-#define CCmv_d_bits 7
-#define CCmv_d_mask 0x1
-#define CCmv_T_bits 8
-#define CCmv_T_mask 0x1
-#define CCmv_code_bits 9
-#define CCmv_code_mask 0x7f
-
-#define init_CCmv \
-{ \
- CCmv_opcode, \
- CCmv_src_bits, CCmv_src_mask, \
- CCmv_dst_bits, CCmv_dst_mask, \
- CCmv_s_bits, CCmv_s_mask, \
- CCmv_d_bits, CCmv_d_mask, \
- CCmv_T_bits, CCmv_T_mask, \
- CCmv_code_bits, CCmv_code_mask \
-};
-
-
-/* CCflag
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_x;
- int mask_x;
- int bits_y;
- int mask_y;
- int bits_G;
- int mask_G;
- int bits_opc;
- int mask_opc;
- int bits_I;
- int mask_I;
- int bits_code;
- int mask_code;
-} CCflag;
-
-#define CCflag_opcode 0x0800
-#define CCflag_x_bits 0
-#define CCflag_x_mask 0x7
-#define CCflag_y_bits 3
-#define CCflag_y_mask 0x7
-#define CCflag_G_bits 6
-#define CCflag_G_mask 0x1
-#define CCflag_opc_bits 7
-#define CCflag_opc_mask 0x7
-#define CCflag_I_bits 10
-#define CCflag_I_mask 0x1
-#define CCflag_code_bits 11
-#define CCflag_code_mask 0x1f
-
-#define init_CCflag \
-{ \
- CCflag_opcode, \
- CCflag_x_bits, CCflag_x_mask, \
- CCflag_y_bits, CCflag_y_mask, \
- CCflag_G_bits, CCflag_G_mask, \
- CCflag_opc_bits, CCflag_opc_mask, \
- CCflag_I_bits, CCflag_I_mask, \
- CCflag_code_bits, CCflag_code_mask, \
-};
-
-
-/* CC2stat
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_cbit;
- int mask_cbit;
- int bits_op;
- int mask_op;
- int bits_D;
- int mask_D;
- int bits_code;
- int mask_code;
-} CC2stat;
-
-#define CC2stat_opcode 0x0300
-#define CC2stat_cbit_bits 0
-#define CC2stat_cbit_mask 0x1f
-#define CC2stat_op_bits 5
-#define CC2stat_op_mask 0x3
-#define CC2stat_D_bits 7
-#define CC2stat_D_mask 0x1
-#define CC2stat_code_bits 8
-#define CC2stat_code_mask 0xff
-
-#define init_CC2stat \
-{ \
- CC2stat_opcode, \
- CC2stat_cbit_bits, CC2stat_cbit_mask, \
- CC2stat_op_bits, CC2stat_op_mask, \
- CC2stat_D_bits, CC2stat_D_mask, \
- CC2stat_code_bits, CC2stat_code_mask \
-};
-
-
-/* REGMV
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_src;
- int mask_src;
- int bits_dst;
- int mask_dst;
- int bits_gs;
- int mask_gs;
- int bits_gd;
- int mask_gd;
- int bits_code;
- int mask_code;
-} RegMv;
-
-#define RegMv_opcode 0x3000
-#define RegMv_src_bits 0
-#define RegMv_src_mask 0x7
-#define RegMv_dst_bits 3
-#define RegMv_dst_mask 0x7
-#define RegMv_gs_bits 6
-#define RegMv_gs_mask 0x7
-#define RegMv_gd_bits 9
-#define RegMv_gd_mask 0x7
-#define RegMv_code_bits 12
-#define RegMv_code_mask 0xf
-
-#define init_RegMv \
-{ \
- RegMv_opcode, \
- RegMv_src_bits, RegMv_src_mask, \
- RegMv_dst_bits, RegMv_dst_mask, \
- RegMv_gs_bits, RegMv_gs_mask, \
- RegMv_gd_bits, RegMv_gd_mask, \
- RegMv_code_bits, RegMv_code_mask \
-};
-
-
-/* COMPI2opD
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 1 | 1 | 0 | 0 |.op|.isrc......................|.dst.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_dst;
- int mask_dst;
- int bits_src;
- int mask_src;
- int bits_op;
- int mask_op;
- int bits_code;
- int mask_code;
-} COMPI2opD;
-
-#define COMPI2opD_opcode 0x6000
-#define COMPI2opD_dst_bits 0
-#define COMPI2opD_dst_mask 0x7
-#define COMPI2opD_src_bits 3
-#define COMPI2opD_src_mask 0x7f
-#define COMPI2opD_op_bits 10
-#define COMPI2opD_op_mask 0x1
-#define COMPI2opD_code_bits 11
-#define COMPI2opD_code_mask 0x1f
-
-#define init_COMPI2opD \
-{ \
- COMPI2opD_opcode, \
- COMPI2opD_dst_bits, COMPI2opD_dst_mask, \
- COMPI2opD_src_bits, COMPI2opD_src_mask, \
- COMPI2opD_op_bits, COMPI2opD_op_mask, \
- COMPI2opD_code_bits, COMPI2opD_code_mask \
-};
-
-/* COMPI2opP
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef COMPI2opD COMPI2opP;
-
-#define COMPI2opP_opcode 0x6800
-#define COMPI2opP_dst_bits 0
-#define COMPI2opP_dst_mask 0x7
-#define COMPI2opP_src_bits 3
-#define COMPI2opP_src_mask 0x7f
-#define COMPI2opP_op_bits 10
-#define COMPI2opP_op_mask 0x1
-#define COMPI2opP_code_bits 11
-#define COMPI2opP_code_mask 0x1f
-
-#define init_COMPI2opP \
-{ \
- COMPI2opP_opcode, \
- COMPI2opP_dst_bits, COMPI2opP_dst_mask, \
- COMPI2opP_src_bits, COMPI2opP_src_mask, \
- COMPI2opP_op_bits, COMPI2opP_op_mask, \
- COMPI2opP_code_bits, COMPI2opP_code_mask \
-};
-
-
-/* dagMODim
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_i;
- int mask_i;
- int bits_m;
- int mask_m;
- int bits_op;
- int mask_op;
- int bits_code2;
- int mask_code2;
- int bits_br;
- int mask_br;
- int bits_code;
- int mask_code;
-} DagMODim;
-
-#define DagMODim_opcode 0x9e60
-#define DagMODim_i_bits 0
-#define DagMODim_i_mask 0x3
-#define DagMODim_m_bits 2
-#define DagMODim_m_mask 0x3
-#define DagMODim_op_bits 4
-#define DagMODim_op_mask 0x1
-#define DagMODim_code2_bits 5
-#define DagMODim_code2_mask 0x3
-#define DagMODim_br_bits 7
-#define DagMODim_br_mask 0x1
-#define DagMODim_code_bits 8
-#define DagMODim_code_mask 0xff
-
-#define init_DagMODim \
-{ \
- DagMODim_opcode, \
- DagMODim_i_bits, DagMODim_i_mask, \
- DagMODim_m_bits, DagMODim_m_mask, \
- DagMODim_op_bits, DagMODim_op_mask, \
- DagMODim_code2_bits, DagMODim_code2_mask, \
- DagMODim_br_bits, DagMODim_br_mask, \
- DagMODim_code_bits, DagMODim_code_mask \
-};
-
-/* dagMODik
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
-+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-*/
-
-typedef struct
-{
- unsigned short opcode;
- int bits_i;
- int mask_i;
- int bits_op;
- int mask_op;
- int bits_code;
- int mask_code;
-} DagMODik;
-
-#define DagMODik_opcode 0x9f60
-#define DagMODik_i_bits 0
-#define DagMODik_i_mask 0x3
-#define DagMODik_op_bits 2
-#define DagMODik_op_mask 0x3
-#define DagMODik_code_bits 3
-#define DagMODik_code_mask 0xfff
-
-#define init_DagMODik \
-{ \
- DagMODik_opcode, \
- DagMODik_i_bits, DagMODik_i_mask, \
- DagMODik_op_bits, DagMODik_op_mask, \
- DagMODik_code_bits, DagMODik_code_mask \
-};
bfin.h
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: arm.h
===================================================================
--- arm.h (revision 816)
+++ arm.h (nonexistent)
@@ -1,212 +0,0 @@
-/* ARM assembler/disassembler support.
- Copyright 2004 Free Software Foundation, Inc.
-
- This file is part of GDB and GAS.
-
- GDB and GAS are free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 1, or (at
- your option) any later version.
-
- GDB and GAS are distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GDB or GAS; see the file COPYING. If not, write to the
- Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
- 02110-1301, USA. */
-
-/* The following bitmasks control CPU extensions: */
-#define ARM_EXT_V1 0x00000001 /* All processors (core set). */
-#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */
-#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */
-#define ARM_EXT_V3 0x00000008 /* MSR MRS. */
-#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */
-#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */
-#define ARM_EXT_V4T 0x00000040 /* Thumb. */
-#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
-#define ARM_EXT_V5T 0x00000100 /* Improved interworking. */
-#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */
-#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */
-#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */
-#define ARM_EXT_V6 0x00001000 /* ARM V6. */
-#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */
-#define ARM_EXT_V6Z 0x00004000 /* ARM V6Z. */
-#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */
-#define ARM_EXT_DIV 0x00010000 /* Integer division. */
-/* The 'M' in Arm V7M stands for Microcontroller.
- On earlier architecture variants it stands for Multiply. */
-#define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */
-#define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */
-#define ARM_EXT_V7 0x00080000 /* Arm V7. */
-#define ARM_EXT_V7A 0x00100000 /* Arm V7A. */
-#define ARM_EXT_V7R 0x00200000 /* Arm V7R. */
-#define ARM_EXT_V7M 0x00400000 /* Arm V7M. */
-#define ARM_EXT_V6M 0x00800000 /* ARM V6M. */
-#define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */
-#define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */
-
-/* Co-processor space extensions. */
-#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
-#define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */
-#define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */
-#define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */
-
-#define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */
-#define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */
-#define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */
-#define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */
-#define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */
-#define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */
-#define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */
-#define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */
-#define FPU_VFP_EXT_V3 0x01000000 /* VFPv3 insns. */
-#define FPU_NEON_EXT_V1 0x00800000 /* Neon (SIMD) insns. */
-#define FPU_VFP_EXT_D32 0x00400000 /* Registers D16-D31. */
-#define FPU_NEON_FP16 0x00200000 /* Half-precision extensions. */
-
-/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
- defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
- ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add
- three more to cover cores prior to ARM6. Finally, there are cores which
- implement further extensions in the co-processor space. */
-#define ARM_AEXT_V1 ARM_EXT_V1
-#define ARM_AEXT_V2 (ARM_AEXT_V1 | ARM_EXT_V2)
-#define ARM_AEXT_V2S (ARM_AEXT_V2 | ARM_EXT_V2S)
-#define ARM_AEXT_V3 (ARM_AEXT_V2S | ARM_EXT_V3)
-#define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M)
-#define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4)
-#define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4)
-#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T)
-#define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T)
-#define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5)
-#define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5)
-#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T)
-#define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T)
-#define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP)
-#define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E)
-#define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J)
-#define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6)
-#define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K)
-#define ARM_AEXT_V6Z (ARM_AEXT_V6 | ARM_EXT_V6Z)
-#define ARM_AEXT_V6ZK (ARM_AEXT_V6 | ARM_EXT_V6K | ARM_EXT_V6Z)
-#define ARM_AEXT_V6T2 (ARM_AEXT_V6 \
- | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR)
-#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K)
-#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_V6Z)
-#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_V6Z)
-#define ARM_AEXT_V7_ARM (ARM_AEXT_V6ZKT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
-#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A)
-#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
-#define ARM_AEXT_NOTM \
- (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM)
-#define ARM_AEXT_V6M \
- ((ARM_AEXT_V6K | ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) \
- & ~(ARM_AEXT_NOTM))
-#define ARM_AEXT_V7M \
- ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \
- & ~(ARM_AEXT_NOTM))
-#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M)
-
-/* Processors with specific extensions in the co-processor space. */
-#define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
-#define ARM_ARCH_IWMMXT \
- ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT)
-#define ARM_ARCH_IWMMXT2 \
- ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2)
-
-#define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE)
-#define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1)
-#define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2)
-#define FPU_VFP_V3D16 (FPU_VFP_V2 | FPU_VFP_EXT_V3)
-#define FPU_VFP_V3 (FPU_VFP_V3D16 | FPU_VFP_EXT_D32)
-#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \
- | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32)
-#define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2)
-
-/* Deprecated */
-#define FPU_ARCH_VFP ARM_FEATURE (0, FPU_ENDIAN_PURE)
-
-#define FPU_ARCH_FPE ARM_FEATURE (0, FPU_FPA_EXT_V1)
-#define FPU_ARCH_FPA ARM_FEATURE (0, FPU_FPA)
-
-#define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD)
-#define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1)
-#define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2)
-#define FPU_ARCH_VFP_V3D16 ARM_FEATURE (0, FPU_VFP_V3D16)
-#define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3)
-#define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1)
-#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \
- ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1)
-#define FPU_ARCH_NEON_FP16 \
- ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_NEON_FP16)
-#define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD)
-
-#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE)
-
-#define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK)
-
-#define ARM_ARCH_V1 ARM_FEATURE (ARM_AEXT_V1, 0)
-#define ARM_ARCH_V2 ARM_FEATURE (ARM_AEXT_V2, 0)
-#define ARM_ARCH_V2S ARM_FEATURE (ARM_AEXT_V2S, 0)
-#define ARM_ARCH_V3 ARM_FEATURE (ARM_AEXT_V3, 0)
-#define ARM_ARCH_V3M ARM_FEATURE (ARM_AEXT_V3M, 0)
-#define ARM_ARCH_V4xM ARM_FEATURE (ARM_AEXT_V4xM, 0)
-#define ARM_ARCH_V4 ARM_FEATURE (ARM_AEXT_V4, 0)
-#define ARM_ARCH_V4TxM ARM_FEATURE (ARM_AEXT_V4TxM, 0)
-#define ARM_ARCH_V4T ARM_FEATURE (ARM_AEXT_V4T, 0)
-#define ARM_ARCH_V5xM ARM_FEATURE (ARM_AEXT_V5xM, 0)
-#define ARM_ARCH_V5 ARM_FEATURE (ARM_AEXT_V5, 0)
-#define ARM_ARCH_V5TxM ARM_FEATURE (ARM_AEXT_V5TxM, 0)
-#define ARM_ARCH_V5T ARM_FEATURE (ARM_AEXT_V5T, 0)
-#define ARM_ARCH_V5TExP ARM_FEATURE (ARM_AEXT_V5TExP, 0)
-#define ARM_ARCH_V5TE ARM_FEATURE (ARM_AEXT_V5TE, 0)
-#define ARM_ARCH_V5TEJ ARM_FEATURE (ARM_AEXT_V5TEJ, 0)
-#define ARM_ARCH_V6 ARM_FEATURE (ARM_AEXT_V6, 0)
-#define ARM_ARCH_V6K ARM_FEATURE (ARM_AEXT_V6K, 0)
-#define ARM_ARCH_V6Z ARM_FEATURE (ARM_AEXT_V6Z, 0)
-#define ARM_ARCH_V6ZK ARM_FEATURE (ARM_AEXT_V6ZK, 0)
-#define ARM_ARCH_V6T2 ARM_FEATURE (ARM_AEXT_V6T2, 0)
-#define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0)
-#define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0)
-#define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0)
-#define ARM_ARCH_V6M ARM_FEATURE (ARM_AEXT_V6M, 0)
-#define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0)
-#define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0)
-#define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0)
-#define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0)
-
-/* Some useful combinations: */
-#define ARM_ARCH_NONE ARM_FEATURE (0, 0)
-#define FPU_NONE ARM_FEATURE (0, 0)
-#define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */
-#define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK)
-#define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0)
-
-/* There are too many feature bits to fit in a single word, so use a
- structure. For simplicity we put all core features in one word and
- everything else in the other. */
-typedef struct
-{
- unsigned long core;
- unsigned long coproc;
-} arm_feature_set;
-
-#define ARM_CPU_HAS_FEATURE(CPU,FEAT) \
- (((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0)
-
-#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \
- do { \
- (TARG).core = (F1).core | (F2).core; \
- (TARG).coproc = (F1).coproc | (F2).coproc; \
- } while (0)
-
-#define ARM_CLEAR_FEATURE(TARG,F1,F2) \
- do { \
- (TARG).core = (F1).core &~ (F2).core; \
- (TARG).coproc = (F1).coproc &~ (F2).coproc; \
- } while (0)
-
-#define ARM_FEATURE(core, coproc) {(core), (coproc)}
arm.h
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
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## -1 +0,0 ##
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\ No newline at end of property
Index: tic54x.h
===================================================================
--- tic54x.h (revision 816)
+++ tic54x.h (nonexistent)
@@ -1,163 +0,0 @@
-/* tic54x.h -- Header file for TI TMS320C54X opcode table
- Copyright 1999, 2000, 2001, 2005, 2009 Free Software Foundation, Inc.
- Written by Timothy Wall (twall@cygnus.com)
-
-This file is part of GDB, GAS, and the GNU binutils.
-
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
-
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
-02110-1301, USA. */
-
-#ifndef _opcode_tic54x_h_
-#define _opcode_tic54x_h_
-
-typedef struct _symbol
-{
- const char *name;
- unsigned short value;
-} symbol;
-
-enum optype {
- OPT = 0x8000,
- OP_None = 0x0,
-
- OP_Xmem, /* AR3 or AR4, indirect */
- OP_Ymem, /* AR3 or AR4, indirect */
- OP_pmad, /* PROG mem, direct */
- OP_dmad, /* DATA mem, direct */
- OP_Smem,
- OP_Lmem, /* 32-bit single-addressed (direct/indirect) */
- OP_MMR,
- OP_PA,
- OP_Sind,
- OP_xpmad,
- OP_xpmad_ms7,
- OP_MMRX,
- OP_MMRY,
-
- OP_SRC1, /* src accumulator in bit 8 */
- OP_SRC, /* src accumulator in bit 9 */
- OP_RND, /* rounded result dst accumulator, opposite of bit 8 */
- OP_DST, /* dst accumulator in bit 8 */
- OP_ARX, /* arX in bits 0-3 */
- OP_SHIFT, /* -16 to 15 (SHIFT), bits 0-4 */
- OP_SHFT, /* 0 to 15 (SHIFT1 in summary), bits 0-3 */
- OP_B, /* ACC B only */
- OP_A, /* ACC A only */
-
- OP_lk, /* 16-bit immediate, '#' optional */
- OP_TS,
- OP_k8, /* -128 <= k <= 128 */
- OP_16, /* literal "16" */
- OP_BITC, /* 0 to 16 */
- OP_CC, /* condition code */
- OP_CC2, /* 4-bit condition code */
- OP_CC3, /* 2-bit condition code */
- OP_123, /* 1, 2, or 3 */
- OP_031, /* 0-31, numeric */
- OP_k5, /* 0 to 31 */
- OP_k8u, /* 0 to 255 */
- OP_ASM, /* "ASM" */
- OP_T, /* "T" */
- OP_DP, /* "DP" */
- OP_ARP, /* "ARP" */
- OP_k3, /* 0-7 */
- OP_lku, /* 0 to 65535 */
- OP_N, /* 0/1 or ST0/ST1 */
- OP_SBIT, /* status bit or 0-15 */
- OP_12, /* one or two */
- OP_k9, /* 9 bits of data page (DP) address */
- OP_TRN, /* "TRN" */
-
-};
-
-typedef struct _template
-{
- /* The opcode mnemonic */
- const char *name;
- unsigned int words; /* insn size in words */
- int minops, maxops; /* min/max operand count */
- /* The significant bits in the opcode. Other bits are zero.
- Instructions with more than 16 bits of opcode store the rest in the upper
- 16 bits.
- */
- unsigned short opcode;
-#define INDIRECT(OP) ((OP)&0x80)
-#define MOD(OP) (((OP)>>3)&0xF)
-#define ARF(OP) ((OP)&0x7)
-#define IS_LKADDR(OP) (INDIRECT(OP) && MOD(OP)>=12)
-#define SRC(OP) ((OP)&0x200)
-#define DST(OP) ((OP)&0x100)
-#define SRC1(OP) ((OP)&0x100)
-#define SHIFT(OP) (((OP)&0x10)?(((OP)&0x1F)-32):((OP)&0x1F))
-#define SHFT(OP) ((OP)&0xF)
-#define ARX(OP) ((OP)&0x7)
-#define XMEM(OP) (((OP)&0x00F0)>>4)
-#define YMEM(OP) ((OP)&0x000F)
-#define XMOD(C) (((C)&0xC)>>2)
-#define XARX(C) (((C)&0x3)+2)
-#define CC3(OP) (((OP)>>8)&0x3)
-#define SBIT(OP) ((OP)&0xF)
-#define MMR(OP) ((OP)&0x7F)
-#define MMRX(OP) ((((OP)>>4)&0xF)+16)
-#define MMRY(OP) (((OP)&0xF)+16)
-
-#define OPTYPE(X) ((X)&~OPT)
-
- /* Ones in this mask indicate which bits must match the opcode field.
- Zeroes indicate don't care bits (operands and/or opcode options) */
- unsigned short mask;
-
- /* An array of operand codes (at most 4 operands) */
-#define MAX_OPERANDS 4
- enum optype operand_types[MAX_OPERANDS];
-
- /* Special purpose flags (e.g. branch type, parallel, delay, etc)
- */
- unsigned short flags;
-#define B_NEXT 0 /* normal execution, next insn is next address */
-#define B_BRANCH 1 /* next insn is in opcode */
-#define B_RET 2 /* next insn is on stack */
-#define B_BACC 3 /* next insn is in acc */
-#define B_REPEAT 4 /* next insn repeats */
-#define FL_BMASK 0x07
-
-#define FL_DELAY 0x10 /* instruction uses delay slots */
-#define FL_EXT 0x20 /* instruction takes two words */
-#define FL_FAR 0x40 /* far mode addressing */
-#define FL_LP 0x80 /* LP-only instruction */
-#define FL_NR 0x100 /* no repeat allowed */
-#define FL_SMR 0x200 /* Smem read (for flagging write-only *+ARx */
-
-#define FL_PAR 0x400 /* Parallel instruction. */
-
- unsigned short opcode2, mask2; /* some insns have an extended opcode */
-
- const char* parname;
- enum optype paroperand_types[MAX_OPERANDS];
-
-} insn_template;
-
-extern const insn_template tic54x_unknown_opcode;
-extern const insn_template tic54x_optab[];
-extern const insn_template tic54x_paroptab[];
-extern const symbol mmregs[], regs[];
-extern const symbol condition_codes[], cc2_codes[], status_bits[];
-extern const symbol cc3_codes[];
-extern const char *misc_symbols[];
-struct disassemble_info;
-extern const insn_template* tic54x_get_insn (struct disassemble_info *,
- bfd_vma, unsigned short, int *);
-
-#endif /* _opcode_tic54x_h_ */
tic54x.h
Property changes :
Deleted: svn:eol-style
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## -1 +0,0 ##
-Id
\ No newline at end of property
Index: ppc.h
===================================================================
--- ppc.h (revision 816)
+++ ppc.h (nonexistent)
@@ -1,364 +0,0 @@
-/* ppc.h -- Header file for PowerPC opcode table
- Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
- 2007, 2008, 2009 Free Software Foundation, Inc.
- Written by Ian Lance Taylor, Cygnus Support
-
-This file is part of GDB, GAS, and the GNU binutils.
-
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
-
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
-#ifndef PPC_H
-#define PPC_H
-
-#include "bfd_stdint.h"
-
-typedef uint64_t ppc_cpu_t;
-
-/* The opcode table is an array of struct powerpc_opcode. */
-
-struct powerpc_opcode
-{
- /* The opcode name. */
- const char *name;
-
- /* The opcode itself. Those bits which will be filled in with
- operands are zeroes. */
- unsigned long opcode;
-
- /* The opcode mask. This is used by the disassembler. This is a
- mask containing ones indicating those bits which must match the
- opcode field, and zeroes indicating those bits which need not
- match (and are presumably filled in by operands). */
- unsigned long mask;
-
- /* One bit flags for the opcode. These are used to indicate which
- specific processors support the instructions. The defined values
- are listed below. */
- ppc_cpu_t flags;
-
- /* One bit flags for the opcode. These are used to indicate which
- specific processors no longer support the instructions. The defined
- values are listed below. */
- ppc_cpu_t deprecated;
-
- /* An array of operand codes. Each code is an index into the
- operand table. They appear in the order which the operands must
- appear in assembly code, and are terminated by a zero. */
- unsigned char operands[8];
-};
-
-/* The table itself is sorted by major opcode number, and is otherwise
- in the order in which the disassembler should consider
- instructions. */
-extern const struct powerpc_opcode powerpc_opcodes[];
-extern const int powerpc_num_opcodes;
-
-/* Values defined for the flags field of a struct powerpc_opcode. */
-
-/* Opcode is defined for the PowerPC architecture. */
-#define PPC_OPCODE_PPC 1
-
-/* Opcode is defined for the POWER (RS/6000) architecture. */
-#define PPC_OPCODE_POWER 2
-
-/* Opcode is defined for the POWER2 (Rios 2) architecture. */
-#define PPC_OPCODE_POWER2 4
-
-/* Opcode is only defined on 32 bit architectures. */
-#define PPC_OPCODE_32 8
-
-/* Opcode is only defined on 64 bit architectures. */
-#define PPC_OPCODE_64 0x10
-
-/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
- is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
- but it also supports many additional POWER instructions. */
-#define PPC_OPCODE_601 0x20
-
-/* Opcode is supported in both the Power and PowerPC architectures
- (ie, compiler's -mcpu=common or assembler's -mcom). */
-#define PPC_OPCODE_COMMON 0x40
-
-/* Opcode is supported for any Power or PowerPC platform (this is
- for the assembler's -many option, and it eliminates duplicates). */
-#define PPC_OPCODE_ANY 0x80
-
-/* Opcode is supported as part of the 64-bit bridge. */
-#define PPC_OPCODE_64_BRIDGE 0x100
-
-/* Opcode is supported by Altivec Vector Unit */
-#define PPC_OPCODE_ALTIVEC 0x200
-
-/* Opcode is supported by PowerPC 403 processor. */
-#define PPC_OPCODE_403 0x400
-
-/* Opcode is supported by PowerPC BookE processor. */
-#define PPC_OPCODE_BOOKE 0x800
-
-/* Opcode is only supported by 64-bit PowerPC BookE processor. */
-#define PPC_OPCODE_BOOKE64 0x1000
-
-/* Opcode is supported by PowerPC 440 processor. */
-#define PPC_OPCODE_440 0x2000
-
-/* Opcode is only supported by Power4 architecture. */
-#define PPC_OPCODE_POWER4 0x4000
-
-/* Opcode is only supported by Power7 architecture. */
-#define PPC_OPCODE_POWER7 0x8000
-
-/* Opcode is only supported by POWERPC Classic architecture. */
-#define PPC_OPCODE_CLASSIC 0x10000
-
-/* Opcode is only supported by e500x2 Core. */
-#define PPC_OPCODE_SPE 0x20000
-
-/* Opcode is supported by e500x2 Integer select APU. */
-#define PPC_OPCODE_ISEL 0x40000
-
-/* Opcode is an e500 SPE floating point instruction. */
-#define PPC_OPCODE_EFS 0x80000
-
-/* Opcode is supported by branch locking APU. */
-#define PPC_OPCODE_BRLOCK 0x100000
-
-/* Opcode is supported by performance monitor APU. */
-#define PPC_OPCODE_PMR 0x200000
-
-/* Opcode is supported by cache locking APU. */
-#define PPC_OPCODE_CACHELCK 0x400000
-
-/* Opcode is supported by machine check APU. */
-#define PPC_OPCODE_RFMCI 0x800000
-
-/* Opcode is only supported by Power5 architecture. */
-#define PPC_OPCODE_POWER5 0x1000000
-
-/* Opcode is supported by PowerPC e300 family. */
-#define PPC_OPCODE_E300 0x2000000
-
-/* Opcode is only supported by Power6 architecture. */
-#define PPC_OPCODE_POWER6 0x4000000
-
-/* Opcode is only supported by PowerPC Cell family. */
-#define PPC_OPCODE_CELL 0x8000000
-
-/* Opcode is supported by CPUs with paired singles support. */
-#define PPC_OPCODE_PPCPS 0x10000000
-
-/* Opcode is supported by Power E500MC */
-#define PPC_OPCODE_E500MC 0x20000000
-
-/* Opcode is supported by PowerPC 405 processor. */
-#define PPC_OPCODE_405 0x40000000
-
-/* Opcode is supported by Vector-Scalar (VSX) Unit */
-#define PPC_OPCODE_VSX 0x80000000
-
-/* Opcode is supported by A2. */
-#define PPC_OPCODE_A2 0x100000000ULL
-
-/* Opcode is supported by PowerPC 476 processor. */
-#define PPC_OPCODE_476 0x200000000ULL
-
-/* A macro to extract the major opcode from an instruction. */
-#define PPC_OP(i) (((i) >> 26) & 0x3f)
-
-/* The operands table is an array of struct powerpc_operand. */
-
-struct powerpc_operand
-{
- /* A bitmask of bits in the operand. */
- unsigned int bitm;
-
- /* How far the operand is left shifted in the instruction.
- -1 to indicate that BITM and SHIFT cannot be used to determine
- where the operand goes in the insn. */
- int shift;
-
- /* Insertion function. This is used by the assembler. To insert an
- operand value into an instruction, check this field.
-
- If it is NULL, execute
- i |= (op & o->bitm) << o->shift;
- (i is the instruction which we are filling in, o is a pointer to
- this structure, and op is the operand value).
-
- If this field is not NULL, then simply call it with the
- instruction and the operand value. It will return the new value
- of the instruction. If the ERRMSG argument is not NULL, then if
- the operand value is illegal, *ERRMSG will be set to a warning
- string (the operand will be inserted in any case). If the
- operand value is legal, *ERRMSG will be unchanged (most operands
- can accept any value). */
- unsigned long (*insert)
- (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
-
- /* Extraction function. This is used by the disassembler. To
- extract this operand type from an instruction, check this field.
-
- If it is NULL, compute
- op = (i >> o->shift) & o->bitm;
- if ((o->flags & PPC_OPERAND_SIGNED) != 0)
- sign_extend (op);
- (i is the instruction, o is a pointer to this structure, and op
- is the result).
-
- If this field is not NULL, then simply call it with the
- instruction value. It will return the value of the operand. If
- the INVALID argument is not NULL, *INVALID will be set to
- non-zero if this operand type can not actually be extracted from
- this operand (i.e., the instruction does not match). If the
- operand is valid, *INVALID will not be changed. */
- long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
-
- /* One bit syntax flags. */
- unsigned long flags;
-};
-
-/* Elements in the table are retrieved by indexing with values from
- the operands field of the powerpc_opcodes table. */
-
-extern const struct powerpc_operand powerpc_operands[];
-extern const unsigned int num_powerpc_operands;
-
-/* Values defined for the flags field of a struct powerpc_operand. */
-
-/* This operand takes signed values. */
-#define PPC_OPERAND_SIGNED (0x1)
-
-/* This operand takes signed values, but also accepts a full positive
- range of values when running in 32 bit mode. That is, if bits is
- 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
- this flag is ignored. */
-#define PPC_OPERAND_SIGNOPT (0x2)
-
-/* This operand does not actually exist in the assembler input. This
- is used to support extended mnemonics such as mr, for which two
- operands fields are identical. The assembler should call the
- insert function with any op value. The disassembler should call
- the extract function, ignore the return value, and check the value
- placed in the valid argument. */
-#define PPC_OPERAND_FAKE (0x4)
-
-/* The next operand should be wrapped in parentheses rather than
- separated from this one by a comma. This is used for the load and
- store instructions which want their operands to look like
- reg,displacement(reg)
- */
-#define PPC_OPERAND_PARENS (0x8)
-
-/* This operand may use the symbolic names for the CR fields, which
- are
- lt 0 gt 1 eq 2 so 3 un 3
- cr0 0 cr1 1 cr2 2 cr3 3
- cr4 4 cr5 5 cr6 6 cr7 7
- These may be combined arithmetically, as in cr2*4+gt. These are
- only supported on the PowerPC, not the POWER. */
-#define PPC_OPERAND_CR (0x10)
-
-/* This operand names a register. The disassembler uses this to print
- register names with a leading 'r'. */
-#define PPC_OPERAND_GPR (0x20)
-
-/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
-#define PPC_OPERAND_GPR_0 (0x40)
-
-/* This operand names a floating point register. The disassembler
- prints these with a leading 'f'. */
-#define PPC_OPERAND_FPR (0x80)
-
-/* This operand is a relative branch displacement. The disassembler
- prints these symbolically if possible. */
-#define PPC_OPERAND_RELATIVE (0x100)
-
-/* This operand is an absolute branch address. The disassembler
- prints these symbolically if possible. */
-#define PPC_OPERAND_ABSOLUTE (0x200)
-
-/* This operand is optional, and is zero if omitted. This is used for
- example, in the optional BF field in the comparison instructions. The
- assembler must count the number of operands remaining on the line,
- and the number of operands remaining for the opcode, and decide
- whether this operand is present or not. The disassembler should
- print this operand out only if it is not zero. */
-#define PPC_OPERAND_OPTIONAL (0x400)
-
-/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
- is omitted, then for the next operand use this operand value plus
- 1, ignoring the next operand field for the opcode. This wretched
- hack is needed because the Power rotate instructions can take
- either 4 or 5 operands. The disassembler should print this operand
- out regardless of the PPC_OPERAND_OPTIONAL field. */
-#define PPC_OPERAND_NEXT (0x800)
-
-/* This operand should be regarded as a negative number for the
- purposes of overflow checking (i.e., the normal most negative
- number is disallowed and one more than the normal most positive
- number is allowed). This flag will only be set for a signed
- operand. */
-#define PPC_OPERAND_NEGATIVE (0x1000)
-
-/* This operand names a vector unit register. The disassembler
- prints these with a leading 'v'. */
-#define PPC_OPERAND_VR (0x2000)
-
-/* This operand is for the DS field in a DS form instruction. */
-#define PPC_OPERAND_DS (0x4000)
-
-/* This operand is for the DQ field in a DQ form instruction. */
-#define PPC_OPERAND_DQ (0x8000)
-
-/* Valid range of operand is 0..n rather than 0..n-1. */
-#define PPC_OPERAND_PLUS1 (0x10000)
-
-/* Xilinx APU and FSL related operands */
-#define PPC_OPERAND_FSL (0x20000)
-#define PPC_OPERAND_FCR (0x40000)
-#define PPC_OPERAND_UDI (0x80000)
-
-/* This operand names a vector-scalar unit register. The disassembler
- prints these with a leading 'vs'. */
-#define PPC_OPERAND_VSR (0x100000)
-
-/* The POWER and PowerPC assemblers use a few macros. We keep them
- with the operands table for simplicity. The macro table is an
- array of struct powerpc_macro. */
-
-struct powerpc_macro
-{
- /* The macro name. */
- const char *name;
-
- /* The number of operands the macro takes. */
- unsigned int operands;
-
- /* One bit flags for the opcode. These are used to indicate which
- specific processors support the instructions. The values are the
- same as those for the struct powerpc_opcode flags field. */
- ppc_cpu_t flags;
-
- /* A format string to turn the macro into a normal instruction.
- Each %N in the string is replaced with operand number N (zero
- based). */
- const char *format;
-};
-
-extern const struct powerpc_macro powerpc_macros[];
-extern const int powerpc_num_macros;
-
-extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, const char *);
-
-#endif /* PPC_H */
ppc.h
Property changes :
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## -1 +0,0 ##
-native
\ No newline at end of property
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## -1 +0,0 ##
-Id
\ No newline at end of property
Index: or32.h
===================================================================
--- or32.h (revision 816)
+++ or32.h (nonexistent)
@@ -1,193 +0,0 @@
-/* Table of opcodes for the OpenRISC 1000 ISA.
- Copyright 2002, 2003 Free Software Foundation, Inc.
- Contributed by Damjan Lampret (lampret@opencores.org).
-
- This file is part of or1k_gen_isa, or1ksim, GDB and GAS.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
-/* We treat all letters the same in encode/decode routines so
- we need to assign some characteristics to them like signess etc. */
-
-#ifndef OR32_H_ISA
-#define OR32_H_ISA
-
-#define NUM_UNSIGNED (0)
-#define NUM_SIGNED (1)
-
-#define MAX_GPRS 32
-#define PAGE_SIZE 8192
-#undef __HALF_WORD_INSN__
-
-#define OPERAND_DELIM (',')
-
-#define OR32_IF_DELAY (1)
-#define OR32_W_FLAG (2)
-#define OR32_R_FLAG (4)
-
-#if defined(HAS_EXECUTION)
-# if SIMPLE_EXECUTION
-# include "simpl32_defs.h"
-# elif DYNAMIC_EXECUTION
-# include "dyn32_defs.h"
-# else
-extern void l_none (void);
-# endif
-#else
-extern void l_none (void);
-#endif
-
-struct or32_letter
-{
- char letter;
- int sign;
- /* int reloc; relocation per letter ?? */
-};
-
-enum insn_type {
- it_unknown,
- it_exception,
- it_arith,
- it_shift,
- it_compare,
- it_branch,
- it_jump,
- it_load,
- it_store,
- it_movimm,
- it_move,
- it_extend,
- it_nop,
- it_mac,
- it_float };
-
-/* Main instruction specification array. */
-struct or32_opcode
-{
- /* Name of the instruction. */
- char *name;
-
- /* A string of characters which describe the operands.
- Valid characters are:
- ,() Itself. Characters appears in the assembly code.
- rA Register operand.
- rB Register operand.
- rD Register operand.
- I An immediate operand, range -32768 to 32767.
- J An immediate operand, range . (unused)
- K An immediate operand, range 0 to 65535.
- L An immediate operand, range 0 to 63.
- M An immediate operand, range . (unused)
- N An immediate operand, range -33554432 to 33554431.
- O An immediate operand, range . (unused). */
- char *args;
-
- /* Opcode and operand encoding. */
- char *encoding;
-
-#ifdef HAS_EXECUTION
-# if COMPLEX_EXECUTION
- char *function_name;
-# elif SIMPLE_EXECUTION
- void (*exec)(struct iqueue_entry *);
-# else /* DYNAMIC_EXECUTION */
- void (*exec)(struct op_queue *opq, int param_t[3], orreg_t param[3], int);
-# endif
-#else /* HAS_EXECUTION */
- void (*exec)(void);
-#endif
-
- unsigned int flags;
- enum insn_type func_unit;
-};
-
-#define OPTYPE_LAST (0x80000000)
-#define OPTYPE_OP (0x40000000)
-#define OPTYPE_REG (0x20000000)
-#define OPTYPE_SIG (0x10000000)
-#define OPTYPE_DIS (0x08000000)
-#define OPTYPE_DST (0x04000000)
-#define OPTYPE_SBIT (0x00001F00)
-#define OPTYPE_SHR (0x0000001F)
-#define OPTYPE_SBIT_SHR (8)
-
-/* MM: Data how to decode operands. */
-extern struct insn_op_struct
-{
- unsigned long type;
- unsigned long data;
-} **op_start;
-
-/* Leaf flag used in automata building */
-#define LEAF_FLAG (0x80000000)
-
-struct temp_insn_struct
-{
- unsigned long insn;
- unsigned long insn_mask;
- int in_pass;
-};
-
-extern unsigned long *automata;
-extern struct temp_insn_struct *ti;
-
-extern const struct or32_letter or32_letters[];
-
-extern const struct or32_opcode or32_opcodes[];
-
-extern const unsigned int or32_num_opcodes;
-
-/* Calculates instruction length in bytes. Always 4 for OR32. */
-extern int insn_len (int);
-
-/* Is individual insn's operand signed or unsigned? */
-extern int letter_signed (char);
-
-/* Number of letters in the individual lettered operand. */
-extern int letter_range (char);
-
-/* MM: Returns index of given instruction name. */
-extern int insn_index (char *);
-
-/* MM: Returns instruction name from index. */
-extern const char *insn_name (int);
-
-/* MM: Constructs new FSM, based on or32_opcodes. */
-extern void build_automata (void);
-
-/* MM: Destructs FSM. */
-extern void destruct_automata (void);
-
-/* MM: Decodes instruction using FSM. Call build_automata first. */
-extern int insn_decode (unsigned int);
-
-/* Disassemble one instruction from insn to disassemble.
- Return the size of the instruction. */
-int disassemble_insn (unsigned long);
-
-/* Extract instruction */
-extern unsigned long insn_extract(char,char*);
-
-/* Disassemble one instruction from insn index.
- Return the size of the instruction. */
-int disassemble_index (unsigned long,int);
-
-/* FOR INTERNAL USE ONLY */
-/* Automatically does zero- or sign- extension and also finds correct
- sign bit position if sign extension is correct extension. Which extension
- is proper is figured out from letter description. */
-unsigned long extend_imm(unsigned long,char);
-
-#endif
or32.h
Property changes :
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## -1 +0,0 ##
-native
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## -1 +0,0 ##
-Id
\ No newline at end of property
Index: avr.h
===================================================================
--- avr.h (revision 816)
+++ avr.h (nonexistent)
@@ -1,284 +0,0 @@
-/* Opcode table for the Atmel AVR micro controllers.
-
- Copyright 2000, 2001, 2004, 2006, 2008 Free Software Foundation, Inc.
- Contributed by Denis Chertykov
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
- any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
-#define AVR_ISA_1200 0x0001 /* In the beginning there was ... */
-#define AVR_ISA_LPM 0x0002 /* device has LPM */
-#define AVR_ISA_LPMX 0x0004 /* device has LPM Rd,Z[+] */
-#define AVR_ISA_SRAM 0x0008 /* device has SRAM (LD, ST, PUSH, POP, ...) */
-#define AVR_ISA_MEGA 0x0020 /* device has >8K program memory (JMP and CALL
- supported, no 8K wrap on RJMP and RCALL) */
-#define AVR_ISA_MUL 0x0040 /* device has new core (MUL, FMUL, ...) */
-#define AVR_ISA_ELPM 0x0080 /* device has >64K program memory (ELPM) */
-#define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] */
-#define AVR_ISA_SPM 0x0200 /* device can program itself */
-#define AVR_ISA_BRK 0x0400 /* device has BREAK (on-chip debug) */
-#define AVR_ISA_EIND 0x0800 /* device has >128K program memory (none yet) */
-#define AVR_ISA_MOVW 0x1000 /* device has MOVW */
-
-#define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM)
-#define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM)
-/* For the attiny26 which is missing LPM Rd,Z+. */
-#define AVR_ISA_2xxe (AVR_ISA_2xxx | AVR_ISA_LPMX)
-#define AVR_ISA_RF401 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX)
-#define AVR_ISA_TINY2 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX | \
- AVR_ISA_SPM | AVR_ISA_BRK)
-#define AVR_ISA_M603 (AVR_ISA_2xxx | AVR_ISA_MEGA)
-#define AVR_ISA_M103 (AVR_ISA_M603 | AVR_ISA_ELPM)
-#define AVR_ISA_M8 (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_MOVW | \
- AVR_ISA_LPMX | AVR_ISA_SPM)
-#define AVR_ISA_PWMx (AVR_ISA_M8 | AVR_ISA_BRK)
-#define AVR_ISA_M161 (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | \
- AVR_ISA_LPMX | AVR_ISA_SPM)
-#define AVR_ISA_94K (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | AVR_ISA_LPMX)
-#define AVR_ISA_M323 (AVR_ISA_M161 | AVR_ISA_BRK)
-#define AVR_ISA_M128 (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX)
-
-#define AVR_ISA_AVR1 AVR_ISA_TINY1
-#define AVR_ISA_AVR2 AVR_ISA_2xxx
-#define AVR_ISA_AVR25 AVR_ISA_TINY2
-#define AVR_ISA_AVR3 AVR_ISA_M603
-#define AVR_ISA_AVR31 AVR_ISA_M103
-#define AVR_ISA_AVR35 (AVR_ISA_AVR3 | AVR_ISA_MOVW | \
- AVR_ISA_LPMX | AVR_ISA_SPM | AVR_ISA_BRK)
-#define AVR_ISA_AVR3_ALL (AVR_ISA_AVR3 | AVR_ISA_AVR31 | AVR_ISA_AVR35)
-#define AVR_ISA_AVR4 AVR_ISA_PWMx
-#define AVR_ISA_AVR5 AVR_ISA_M323
-#define AVR_ISA_AVR51 AVR_ISA_M128
-#define AVR_ISA_AVR6 (AVR_ISA_1200 | AVR_ISA_LPM | AVR_ISA_LPMX | \
- AVR_ISA_SRAM | AVR_ISA_MEGA | AVR_ISA_MUL | \
- AVR_ISA_ELPM | AVR_ISA_ELPMX | AVR_ISA_SPM | \
- AVR_ISA_SPM | AVR_ISA_BRK | AVR_ISA_EIND | \
- AVR_ISA_MOVW)
-
-#define REGISTER_P(x) ((x) == 'r' \
- || (x) == 'd' \
- || (x) == 'w' \
- || (x) == 'a' \
- || (x) == 'v')
-
-/* Undefined combination of operands - does the register
- operand overlap with pre-decremented or post-incremented
- pointer register (like ld r31,Z+)? */
-#define AVR_UNDEF_P(x) (((x) & 0xFFED) == 0x91E5 || \
- ((x) & 0xFDEF) == 0x91AD || ((x) & 0xFDEF) == 0x91AE || \
- ((x) & 0xFDEF) == 0x91C9 || ((x) & 0xFDEF) == 0x91CA || \
- ((x) & 0xFDEF) == 0x91E1 || ((x) & 0xFDEF) == 0x91E2)
-
-/* Is this a skip instruction {cpse,sbic,sbis,sbrc,sbrs}? */
-#define AVR_SKIP_P(x) (((x) & 0xFC00) == 0x1000 || \
- ((x) & 0xFD00) == 0x9900 || ((x) & 0xFC08) == 0xFC00)
-
-/* Is this `ldd r,b+0' or `std b+0,r' (b={Y,Z}, disassembled as
- `ld r,b' or `st b,r' respectively - next opcode entry)? */
-#define AVR_DISP0_P(x) (((x) & 0xFC07) == 0x8000)
-
-/* constraint letters
- r - any register
- d - `ldi' register (r16-r31)
- v - `movw' even register (r0, r2, ..., r28, r30)
- a - `fmul' register (r16-r23)
- w - `adiw' register (r24,r26,r28,r30)
- e - pointer registers (X,Y,Z)
- b - base pointer register and displacement ([YZ]+disp)
- z - Z pointer register (for [e]lpm Rd,Z[+])
- M - immediate value from 0 to 255
- n - immediate value from 0 to 255 ( n = ~M ). Relocation impossible
- s - immediate value from 0 to 7
- P - Port address value from 0 to 63. (in, out)
- p - Port address value from 0 to 31. (cbi, sbi, sbic, sbis)
- K - immediate value from 0 to 63 (used in `adiw', `sbiw')
- i - immediate value
- l - signed pc relative offset from -64 to 63
- L - signed pc relative offset from -2048 to 2047
- h - absolute code address (call, jmp)
- S - immediate value from 0 to 7 (S = s << 4)
- ? - use this opcode entry if no parameters, else use next opcode entry
-
- Order is important - some binary opcodes have more than one name,
- the disassembler will only see the first match.
-
- Remaining undefined opcodes (1699 total - some of them might work
- as normal instructions if not all of the bits are decoded):
-
- 0x0001...0x00ff (255) (known to be decoded as `nop' by the old core)
- "100100xxxxxxx011" (128) 0x9[0-3][0-9a-f][3b]
- "100100xxxxxx1000" (64) 0x9[0-3][0-9a-f]8
- "1001001xxxxx01xx" (128) 0x9[23][0-9a-f][4-7]
- "1001010xxxxx0100" (32) 0x9[45][0-9a-f]4
- "1001010x001x1001" (4) 0x9[45][23]9
- "1001010x01xx1001" (8) 0x9[45][4-7]9
- "1001010x1xxx1001" (16) 0x9[45][8-9a-f]9
- "1001010xxxxx1011" (32) 0x9[45][0-9a-f]b
- "10010101001x1000" (2) 0x95[23]8
- "1001010101xx1000" (4) 0x95[4-7]8
- "1001010110111000" (1) 0x95b8
- "1001010111111000" (1) 0x95f8 (`espm' removed in databook update)
- "11111xxxxxxx1xxx" (1024) 0xf[8-9a-f][0-9a-f][8-9a-f]
- */
-
-AVR_INSN (clc, "", "1001010010001000", 1, AVR_ISA_1200, 0x9488)
-AVR_INSN (clh, "", "1001010011011000", 1, AVR_ISA_1200, 0x94d8)
-AVR_INSN (cli, "", "1001010011111000", 1, AVR_ISA_1200, 0x94f8)
-AVR_INSN (cln, "", "1001010010101000", 1, AVR_ISA_1200, 0x94a8)
-AVR_INSN (cls, "", "1001010011001000", 1, AVR_ISA_1200, 0x94c8)
-AVR_INSN (clt, "", "1001010011101000", 1, AVR_ISA_1200, 0x94e8)
-AVR_INSN (clv, "", "1001010010111000", 1, AVR_ISA_1200, 0x94b8)
-AVR_INSN (clz, "", "1001010010011000", 1, AVR_ISA_1200, 0x9498)
-
-AVR_INSN (sec, "", "1001010000001000", 1, AVR_ISA_1200, 0x9408)
-AVR_INSN (seh, "", "1001010001011000", 1, AVR_ISA_1200, 0x9458)
-AVR_INSN (sei, "", "1001010001111000", 1, AVR_ISA_1200, 0x9478)
-AVR_INSN (sen, "", "1001010000101000", 1, AVR_ISA_1200, 0x9428)
-AVR_INSN (ses, "", "1001010001001000", 1, AVR_ISA_1200, 0x9448)
-AVR_INSN (set, "", "1001010001101000", 1, AVR_ISA_1200, 0x9468)
-AVR_INSN (sev, "", "1001010000111000", 1, AVR_ISA_1200, 0x9438)
-AVR_INSN (sez, "", "1001010000011000", 1, AVR_ISA_1200, 0x9418)
-
- /* Same as {cl,se}[chinstvz] above. */
-AVR_INSN (bclr, "S", "100101001SSS1000", 1, AVR_ISA_1200, 0x9488)
-AVR_INSN (bset, "S", "100101000SSS1000", 1, AVR_ISA_1200, 0x9408)
-
-AVR_INSN (icall,"", "1001010100001001", 1, AVR_ISA_2xxx, 0x9509)
-AVR_INSN (ijmp, "", "1001010000001001", 1, AVR_ISA_2xxx, 0x9409)
-
-AVR_INSN (lpm, "?", "1001010111001000", 1, AVR_ISA_TINY1,0x95c8)
-AVR_INSN (lpm, "r,z", "1001000ddddd010+", 1, AVR_ISA_LPMX, 0x9004)
-AVR_INSN (elpm, "?", "1001010111011000", 1, AVR_ISA_ELPM, 0x95d8)
-AVR_INSN (elpm, "r,z", "1001000ddddd011+", 1, AVR_ISA_ELPMX,0x9006)
-
-AVR_INSN (nop, "", "0000000000000000", 1, AVR_ISA_1200, 0x0000)
-AVR_INSN (ret, "", "1001010100001000", 1, AVR_ISA_1200, 0x9508)
-AVR_INSN (reti, "", "1001010100011000", 1, AVR_ISA_1200, 0x9518)
-AVR_INSN (sleep,"", "1001010110001000", 1, AVR_ISA_1200, 0x9588)
-AVR_INSN (break,"", "1001010110011000", 1, AVR_ISA_BRK, 0x9598)
-AVR_INSN (wdr, "", "1001010110101000", 1, AVR_ISA_1200, 0x95a8)
-AVR_INSN (spm, "", "1001010111101000", 1, AVR_ISA_SPM, 0x95e8)
-
-AVR_INSN (adc, "r,r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00)
-AVR_INSN (add, "r,r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00)
-AVR_INSN (and, "r,r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000)
-AVR_INSN (cp, "r,r", "000101rdddddrrrr", 1, AVR_ISA_1200, 0x1400)
-AVR_INSN (cpc, "r,r", "000001rdddddrrrr", 1, AVR_ISA_1200, 0x0400)
-AVR_INSN (cpse, "r,r", "000100rdddddrrrr", 1, AVR_ISA_1200, 0x1000)
-AVR_INSN (eor, "r,r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400)
-AVR_INSN (mov, "r,r", "001011rdddddrrrr", 1, AVR_ISA_1200, 0x2c00)
-AVR_INSN (mul, "r,r", "100111rdddddrrrr", 1, AVR_ISA_MUL, 0x9c00)
-AVR_INSN (or, "r,r", "001010rdddddrrrr", 1, AVR_ISA_1200, 0x2800)
-AVR_INSN (sbc, "r,r", "000010rdddddrrrr", 1, AVR_ISA_1200, 0x0800)
-AVR_INSN (sub, "r,r", "000110rdddddrrrr", 1, AVR_ISA_1200, 0x1800)
-
- /* Shorthand for {eor,add,adc,and} r,r above. */
-AVR_INSN (clr, "r=r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400)
-AVR_INSN (lsl, "r=r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00)
-AVR_INSN (rol, "r=r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00)
-AVR_INSN (tst, "r=r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000)
-
-AVR_INSN (andi, "d,M", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000)
- /*XXX special case*/
-AVR_INSN (cbr, "d,n", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000)
-
-AVR_INSN (ldi, "d,M", "1110KKKKddddKKKK", 1, AVR_ISA_1200, 0xe000)
-AVR_INSN (ser, "d", "11101111dddd1111", 1, AVR_ISA_1200, 0xef0f)
-
-AVR_INSN (ori, "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000)
-AVR_INSN (sbr, "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000)
-
-AVR_INSN (cpi, "d,M", "0011KKKKddddKKKK", 1, AVR_ISA_1200, 0x3000)
-AVR_INSN (sbci, "d,M", "0100KKKKddddKKKK", 1, AVR_ISA_1200, 0x4000)
-AVR_INSN (subi, "d,M", "0101KKKKddddKKKK", 1, AVR_ISA_1200, 0x5000)
-
-AVR_INSN (sbrc, "r,s", "1111110rrrrr0sss", 1, AVR_ISA_1200, 0xfc00)
-AVR_INSN (sbrs, "r,s", "1111111rrrrr0sss", 1, AVR_ISA_1200, 0xfe00)
-AVR_INSN (bld, "r,s", "1111100ddddd0sss", 1, AVR_ISA_1200, 0xf800)
-AVR_INSN (bst, "r,s", "1111101ddddd0sss", 1, AVR_ISA_1200, 0xfa00)
-
-AVR_INSN (in, "r,P", "10110PPdddddPPPP", 1, AVR_ISA_1200, 0xb000)
-AVR_INSN (out, "P,r", "10111PPrrrrrPPPP", 1, AVR_ISA_1200, 0xb800)
-
-AVR_INSN (adiw, "w,K", "10010110KKddKKKK", 1, AVR_ISA_2xxx, 0x9600)
-AVR_INSN (sbiw, "w,K", "10010111KKddKKKK", 1, AVR_ISA_2xxx, 0x9700)
-
-AVR_INSN (cbi, "p,s", "10011000pppppsss", 1, AVR_ISA_1200, 0x9800)
-AVR_INSN (sbi, "p,s", "10011010pppppsss", 1, AVR_ISA_1200, 0x9a00)
-AVR_INSN (sbic, "p,s", "10011001pppppsss", 1, AVR_ISA_1200, 0x9900)
-AVR_INSN (sbis, "p,s", "10011011pppppsss", 1, AVR_ISA_1200, 0x9b00)
-
-AVR_INSN (brcc, "l", "111101lllllll000", 1, AVR_ISA_1200, 0xf400)
-AVR_INSN (brcs, "l", "111100lllllll000", 1, AVR_ISA_1200, 0xf000)
-AVR_INSN (breq, "l", "111100lllllll001", 1, AVR_ISA_1200, 0xf001)
-AVR_INSN (brge, "l", "111101lllllll100", 1, AVR_ISA_1200, 0xf404)
-AVR_INSN (brhc, "l", "111101lllllll101", 1, AVR_ISA_1200, 0xf405)
-AVR_INSN (brhs, "l", "111100lllllll101", 1, AVR_ISA_1200, 0xf005)
-AVR_INSN (brid, "l", "111101lllllll111", 1, AVR_ISA_1200, 0xf407)
-AVR_INSN (brie, "l", "111100lllllll111", 1, AVR_ISA_1200, 0xf007)
-AVR_INSN (brlo, "l", "111100lllllll000", 1, AVR_ISA_1200, 0xf000)
-AVR_INSN (brlt, "l", "111100lllllll100", 1, AVR_ISA_1200, 0xf004)
-AVR_INSN (brmi, "l", "111100lllllll010", 1, AVR_ISA_1200, 0xf002)
-AVR_INSN (brne, "l", "111101lllllll001", 1, AVR_ISA_1200, 0xf401)
-AVR_INSN (brpl, "l", "111101lllllll010", 1, AVR_ISA_1200, 0xf402)
-AVR_INSN (brsh, "l", "111101lllllll000", 1, AVR_ISA_1200, 0xf400)
-AVR_INSN (brtc, "l", "111101lllllll110", 1, AVR_ISA_1200, 0xf406)
-AVR_INSN (brts, "l", "111100lllllll110", 1, AVR_ISA_1200, 0xf006)
-AVR_INSN (brvc, "l", "111101lllllll011", 1, AVR_ISA_1200, 0xf403)
-AVR_INSN (brvs, "l", "111100lllllll011", 1, AVR_ISA_1200, 0xf003)
-
- /* Same as br?? above. */
-AVR_INSN (brbc, "s,l", "111101lllllllsss", 1, AVR_ISA_1200, 0xf400)
-AVR_INSN (brbs, "s,l", "111100lllllllsss", 1, AVR_ISA_1200, 0xf000)
-
-AVR_INSN (rcall, "L", "1101LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xd000)
-AVR_INSN (rjmp, "L", "1100LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xc000)
-
-AVR_INSN (call, "h", "1001010hhhhh111h", 2, AVR_ISA_MEGA, 0x940e)
-AVR_INSN (jmp, "h", "1001010hhhhh110h", 2, AVR_ISA_MEGA, 0x940c)
-
-AVR_INSN (asr, "r", "1001010rrrrr0101", 1, AVR_ISA_1200, 0x9405)
-AVR_INSN (com, "r", "1001010rrrrr0000", 1, AVR_ISA_1200, 0x9400)
-AVR_INSN (dec, "r", "1001010rrrrr1010", 1, AVR_ISA_1200, 0x940a)
-AVR_INSN (inc, "r", "1001010rrrrr0011", 1, AVR_ISA_1200, 0x9403)
-AVR_INSN (lsr, "r", "1001010rrrrr0110", 1, AVR_ISA_1200, 0x9406)
-AVR_INSN (neg, "r", "1001010rrrrr0001", 1, AVR_ISA_1200, 0x9401)
-AVR_INSN (pop, "r", "1001000rrrrr1111", 1, AVR_ISA_2xxx, 0x900f)
-AVR_INSN (push, "r", "1001001rrrrr1111", 1, AVR_ISA_2xxx, 0x920f)
-AVR_INSN (ror, "r", "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407)
-AVR_INSN (swap, "r", "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402)
-
- /* Known to be decoded as `nop' by the old core. */
-AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MOVW, 0x0100)
-AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL, 0x0200)
-AVR_INSN (mulsu,"a,a", "000000110ddd0rrr", 1, AVR_ISA_MUL, 0x0300)
-AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL, 0x0308)
-AVR_INSN (fmuls,"a,a", "000000111ddd0rrr", 1, AVR_ISA_MUL, 0x0380)
-AVR_INSN (fmulsu,"a,a","000000111ddd1rrr", 1, AVR_ISA_MUL, 0x0388)
-
-AVR_INSN (sts, "i,r", "1001001ddddd0000", 2, AVR_ISA_2xxx, 0x9200)
-AVR_INSN (lds, "r,i", "1001000ddddd0000", 2, AVR_ISA_2xxx, 0x9000)
-
- /* Special case for b+0, `e' must be next entry after `b',
- b={Y=1,Z=0}, ee={X=11,Y=10,Z=00}, !=1 if -e or e+ or X. */
-AVR_INSN (ldd, "r,b", "10o0oo0dddddbooo", 1, AVR_ISA_2xxx, 0x8000)
-AVR_INSN (ld, "r,e", "100!000dddddee-+", 1, AVR_ISA_1200, 0x8000)
-AVR_INSN (std, "b,r", "10o0oo1rrrrrbooo", 1, AVR_ISA_2xxx, 0x8200)
-AVR_INSN (st, "e,r", "100!001rrrrree-+", 1, AVR_ISA_1200, 0x8200)
-
- /* These are for devices that don't exist yet
- (>128K program memory, PC = EIND:Z). */
-AVR_INSN (eicall, "", "1001010100011001", 1, AVR_ISA_EIND, 0x9519)
-AVR_INSN (eijmp, "", "1001010000011001", 1, AVR_ISA_EIND, 0x9419)
-
avr.h
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: s390.h
===================================================================
--- s390.h (revision 816)
+++ s390.h (nonexistent)
@@ -1,148 +0,0 @@
-/* s390.h -- Header file for S390 opcode table
- Copyright 2000, 2001, 2003 Free Software Foundation, Inc.
- Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
-
- This file is part of BFD, the Binary File Descriptor library.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
- 02110-1301, USA. */
-
-#ifndef S390_H
-#define S390_H
-
-/* List of instruction sets variations. */
-
-enum s390_opcode_mode_val
- {
- S390_OPCODE_ESA = 0,
- S390_OPCODE_ZARCH
- };
-
-enum s390_opcode_cpu_val
- {
- S390_OPCODE_G5 = 0,
- S390_OPCODE_G6,
- S390_OPCODE_Z900,
- S390_OPCODE_Z990,
- S390_OPCODE_Z9_109,
- S390_OPCODE_Z9_EC,
- S390_OPCODE_Z10
- };
-
-/* The opcode table is an array of struct s390_opcode. */
-
-struct s390_opcode
- {
- /* The opcode name. */
- const char * name;
-
- /* The opcode itself. Those bits which will be filled in with
- operands are zeroes. */
- unsigned char opcode[6];
-
- /* The opcode mask. This is used by the disassembler. This is a
- mask containing ones indicating those bits which must match the
- opcode field, and zeroes indicating those bits which need not
- match (and are presumably filled in by operands). */
- unsigned char mask[6];
-
- /* The opcode length in bytes. */
- int oplen;
-
- /* An array of operand codes. Each code is an index into the
- operand table. They appear in the order which the operands must
- appear in assembly code, and are terminated by a zero. */
- unsigned char operands[6];
-
- /* Bitmask of execution modes this opcode is available for. */
- unsigned int modes;
-
- /* First cpu this opcode is available for. */
- enum s390_opcode_cpu_val min_cpu;
- };
-
-/* The table itself is sorted by major opcode number, and is otherwise
- in the order in which the disassembler should consider
- instructions. */
-extern const struct s390_opcode s390_opcodes[];
-extern const int s390_num_opcodes;
-
-/* A opcode format table for the .insn pseudo mnemonic. */
-extern const struct s390_opcode s390_opformats[];
-extern const int s390_num_opformats;
-
-/* Values defined for the flags field of a struct powerpc_opcode. */
-
-/* The operands table is an array of struct s390_operand. */
-
-struct s390_operand
- {
- /* The number of bits in the operand. */
- int bits;
-
- /* How far the operand is left shifted in the instruction. */
- int shift;
-
- /* One bit syntax flags. */
- unsigned long flags;
- };
-
-/* Elements in the table are retrieved by indexing with values from
- the operands field of the powerpc_opcodes table. */
-
-extern const struct s390_operand s390_operands[];
-
-/* Values defined for the flags field of a struct s390_operand. */
-
-/* This operand names a register. The disassembler uses this to print
- register names with a leading 'r'. */
-#define S390_OPERAND_GPR 0x1
-
-/* This operand names a floating point register. The disassembler
- prints these with a leading 'f'. */
-#define S390_OPERAND_FPR 0x2
-
-/* This operand names an access register. The disassembler
- prints these with a leading 'a'. */
-#define S390_OPERAND_AR 0x4
-
-/* This operand names a control register. The disassembler
- prints these with a leading 'c'. */
-#define S390_OPERAND_CR 0x8
-
-/* This operand is a displacement. */
-#define S390_OPERAND_DISP 0x10
-
-/* This operand names a base register. */
-#define S390_OPERAND_BASE 0x20
-
-/* This operand names an index register, it can be skipped. */
-#define S390_OPERAND_INDEX 0x40
-
-/* This operand is a relative branch displacement. The disassembler
- prints these symbolically if possible. */
-#define S390_OPERAND_PCREL 0x80
-
-/* This operand takes signed values. */
-#define S390_OPERAND_SIGNED 0x100
-
-/* This operand is a length. */
-#define S390_OPERAND_LENGTH 0x200
-
-/* This operand is optional. Only a single operand at the end of
- the instruction may be optional. */
-#define S390_OPERAND_OPTIONAL 0x400
-
- #endif /* S390_H */
s390.h
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: ChangeLog
===================================================================
--- ChangeLog (revision 816)
+++ ChangeLog (nonexistent)
@@ -1,917 +0,0 @@
-2009-10-02 Peter Bergner
-
- * ppc.h (PPC_OPCODE_476): Define.
-
-2009-10-01 Peter Bergner
-
- * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
-
-2009-09-22 Peter Bergner
-
- * ppc.h (ppc_cpu_t): Typedef to uint64_t.
-
-2009-09-21 Ben Elliston
-
- * ppc.h (PPC_OPCODE_PPCA2): New.
-
-2009-09-05 Martin Thuresson
-
- * ia64.h (struct ia64_operand): Renamed member class to op_class.
-
-2009-08-29 Martin Thuresson
-
- * tic30.h (template): Rename type template to
- insn_template. Updated code to use new name.
- * tic54x.h (template): Rename type template to
- insn_template.
-
-2009-08-20 Nick Hudson
-
- * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
-
-2009-06-11 Anthony Green
-
- * moxie.h (MOXIE_F3_PCREL): Define.
- (moxie_form3_opc_info): Grow.
-
-2009-06-06 Anthony Green
-
- * moxie.h (MOXIE_F1_M): Define.
-
-2009-04-15 Anthony Green
-
- * moxie.h: Created.
-
-2009-04-06 DJ Delorie
-
- * h8300.h: Add relaxation attributes to MOVA opcodes.
-
-2009-03-10 Alan Modra
-
- * ppc.h (ppc_parse_cpu): Declare.
-
-2009-03-02 Qinwei
-
- * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
- and _IMM11 for mbitclr and mbitset.
- * score-datadep.h: Update dependency information.
-
-2009-02-26 Peter Bergner
-
- * ppc.h (PPC_OPCODE_POWER7): New.
-
-2009-02-06 Doug Evans
-
- * i386.h: Add comment regarding sse* insns and prefixes.
-
-2009-02-03 Sandip Matte
-
- * mips.h (INSN_XLR): Define.
- (INSN_CHIP_MASK): Update.
- (CPU_XLR): Define.
- (OPCODE_IS_MEMBER): Update.
- (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
-
-2009-01-28 Doug Evans
-
- * opcode/i386.h: Add multiple inclusion protection.
- (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
- (EDI_REG_NUM): New macros.
- (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
- (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
- (REX_PREFIX_P): New macro.
-
-2009-01-09 Peter Bergner
-
- * ppc.h (struct powerpc_opcode): New field "deprecated".
- (PPC_OPCODE_NOPOWER4): Delete.
-
-2008-11-28 Joshua Kinard
-
- * mips.h: Define CPU_R14000, CPU_R16000.
- (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
-
-2008-11-18 Catherine Moore
-
- * arm.h (FPU_NEON_FP16): New.
- (FPU_ARCH_NEON_FP16): New.
-
-2008-11-06 Chao-ying Fu
-
- * mips.h: Doucument '1' for 5-bit sync type.
-
-2008-08-28 H.J. Lu
-
- * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
- IA64_RS_CR.
-
-2008-08-01 Peter Bergner
-
- * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
-
-2008-07-30 Michael J. Eager
-
- * ppc.h (PPC_OPCODE_405): Define.
- (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
-
-2008-06-13 Peter Bergner
-
- * ppc.h (ppc_cpu_t): New typedef.
- (struct powerpc_opcode ): Use it.
- (struct powerpc_operand ): Likewise.
- (struct powerpc_macro ): Likewise.
-
-2008-06-12 Adam Nemet
-
- * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
- Update comment before MIPS16 field descriptors to mention MIPS16.
- (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
- BBIT.
- (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
- New bit masks and shift counts for cins and exts.
-
- * mips.h: Document new field descriptors +Q.
- (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
-
-2008-04-28 Adam Nemet
-
- * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
- (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
-
-2008-04-14 Edmar Wienskoski
-
- * ppc.h: (PPC_OPCODE_E500MC): New.
-
-2008-04-03 H.J. Lu
-
- * i386.h (MAX_OPERANDS): Set to 5.
- (MAX_MNEM_SIZE): Changed to 20.
-
-2008-03-28 Eric B. Weddington
-
- * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
-
-2008-03-09 Paul Brook
-
- * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
-
-2008-03-04 Paul Brook
-
- * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
- (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
- (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
-
-2008-02-27 Denis Vlasenko
- Nick Clifton
-
- PR 3134
- * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
- with a 32-bit displacement but without the top bit of the 4th byte
- set.
-
-2008-02-18 M R Swami Reddy
-
- * cr16.h (cr16_num_optab): Declared.
-
-2008-02-14 Hakan Ardo
-
- PR gas/2626
- * avr.h (AVR_ISA_2xxe): Define.
-
-2008-02-04 Adam Nemet
-
- * mips.h: Update copyright.
- (INSN_CHIP_MASK): New macro.
- (INSN_OCTEON): New macro.
- (CPU_OCTEON): New macro.
- (OPCODE_IS_MEMBER): Handle Octeon instructions.
-
-2008-01-23 Eric B. Weddington
-
- * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
-
-2008-01-03 Eric B. Weddington
-
- * avr.h (AVR_ISA_USB162): Add new opcode set.
- (AVR_ISA_AVR3): Likewise.
-
-2007-11-29 Mark Shinwell
-
- * mips.h (INSN_LOONGSON_2E): New.
- (INSN_LOONGSON_2F): New.
- (CPU_LOONGSON_2E): New.
- (CPU_LOONGSON_2F): New.
- (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
-
-2007-11-29 Mark Shinwell
-
- * mips.h (INSN_ISA*): Redefine certain values as an
- enumeration. Update comments.
- (mips_isa_table): New.
- (ISA_MIPS*): Redefine to match enumeration.
- (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
- values.
-
-2007-08-08 Ben Elliston
-
- * ppc.h (PPC_OPCODE_PPCPS): New.
-
-2007-07-03 Nathan Sidwell
-
- * m68k.h: Document j K & E.
-
-2007-06-29 M R Swami Reddy
-
- * cr16.h: New file for CR16 target.
-
-2007-05-02 Alan Modra
-
- * ppc.h (PPC_OPERAND_PLUS1): Update comment.
-
-2007-04-23 Nathan Sidwell
-
- * m68k.h (mcfisa_c): New.
- (mcfusp, mcf_mask): Adjust.
-
-2007-04-20 Alan Modra
-
- * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
- (num_powerpc_operands): Declare.
- (PPC_OPERAND_SIGNED et al): Redefine as hex.
- (PPC_OPERAND_PLUS1): Define.
-
-2007-03-21 H.J. Lu
-
- * i386.h (REX_MODE64): Renamed to ...
- (REX_W): This.
- (REX_EXTX): Renamed to ...
- (REX_R): This.
- (REX_EXTY): Renamed to ...
- (REX_X): This.
- (REX_EXTZ): Renamed to ...
- (REX_B): This.
-
-2007-03-15 H.J. Lu
-
- * i386.h: Add entries from config/tc-i386.h and move tables
- to opcodes/i386-opc.h.
-
-2007-03-13 H.J. Lu
-
- * i386.h (FloatDR): Removed.
- (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
-
-2007-03-01 Alan Modra
-
- * spu-insns.h: Add soma double-float insns.
-
-2007-02-20 Thiemo Seufer
- Chao-Ying Fu
-
- * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
- (INSN_DSPR2): Add flag for DSP R2 instructions.
- (M_BALIGN): New macro.
-
-2007-02-14 Alan Modra
-
- * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
- and Seg3ShortFrom with Shortform.
-
-2007-02-11 H.J. Lu
-
- PR gas/4027
- * i386.h (i386_optab): Put the real "test" before the pseudo
- one.
-
-2007-01-08 Kazu Hirata
-
- * m68k.h (m68010up): OR fido_a.
-
-2006-12-25 Kazu Hirata
-
- * m68k.h (fido_a): New.
-
-2006-12-24 Kazu Hirata
-
- * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
- mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
- values.
-
-2006-11-08 H.J. Lu
-
- * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
-
-2006-10-31 Mei Ligang
-
- * score-inst.h (enum score_insn_type): Add Insn_internal.
-
-2006-10-25 Trevor Smigiel
- Yukishige Shibata
- Nobuhisa Fujinami
- Takeaki Fukuoka
- Alan Modra
-
- * spu-insns.h: New file.
- * spu.h: New file.
-
-2006-10-24 Andrew Pinski
-
- * ppc.h (PPC_OPCODE_CELL): Define.
-
-2006-10-23 Dwarakanath Rajagopal
-
- * i386.h : Modify opcode to support for the change in POPCNT opcode
- in amdfam10 architecture.
-
-2006-09-28 H.J. Lu
-
- * i386.h: Replace CpuMNI with CpuSSSE3.
-
-2006-09-26 Mark Shinwell
- Joseph Myers
- Ian Lance Taylor
- Ben Elliston
-
- * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
-
-2006-09-17 Mei Ligang
-
- * score-datadep.h: New file.
- * score-inst.h: New file.
-
-2006-07-14 H.J. Lu
-
- * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
- movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
- movdq2q and movq2dq.
-
-2006-07-10 Dwarakanath Rajagopal
- Michael Meissner
-
- * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
-
-2006-06-12 H.J. Lu
-
- * i386.h (i386_optab): Add "nop" with memory reference.
-
-2006-06-12 H.J. Lu
-
- * i386.h (i386_optab): Update comment for 64bit NOP.
-
-2006-06-06 Ben Elliston
- Anton Blanchard
-
- * ppc.h (PPC_OPCODE_POWER6): Define.
- Adjust whitespace.
-
-2006-06-05 Thiemo Seufer
-
- * mips.h: Improve description of MT flags.
-
-2006-05-25 Richard Sandiford
-
- * m68k.h (mcf_mask): Define.
-
-2006-05-05 Thiemo Seufer
- David Ung
-
- * mips.h (enum): Add macro M_CACHE_AB.
-
-2006-05-04 Thiemo Seufer
- Nigel Stephens
- David Ung
-
- * mips.h: Add INSN_SMARTMIPS define.
-
-2006-04-30 Thiemo Seufer
- David Ung
-
- * mips.h: Defines udi bits and masks. Add description of
- characters which may appear in the args field of udi
- instructions.
-
-2006-04-26 Thiemo Seufer
-
- * mips.h: Improve comments describing the bitfield instruction
- fields.
-
-2006-04-26 Julian Brown
-
- * arm.h (FPU_VFP_EXT_V3): Define constant.
- (FPU_NEON_EXT_V1): Likewise.
- (FPU_VFP_HARD): Update.
- (FPU_VFP_V3): Define macro.
- (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
-
-2006-04-07 Joerg Wunsch
-
- * avr.h (AVR_ISA_PWMx): New.
-
-2006-03-28 Nathan Sidwell
-
- * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
- cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
- cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
- cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
- cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
-
-2006-03-10 Paul Brook
-
- * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
-
-2006-03-04 John David Anglin
-
- * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
- first. Correct mask of bb "B" opcode.
-
-2006-02-27 H.J. Lu
-
- * i386.h (i386_optab): Support Intel Merom New Instructions.
-
-2006-02-24 Paul Brook
-
- * arm.h: Add V7 feature bits.
-
-2006-02-23 H.J. Lu
-
- * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
-
-2006-01-31 Paul Brook
- Richard Earnshaw
-
- * arm.h: Use ARM_CPU_FEATURE.
- (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
- (arm_feature_set): Change to a structure.
- (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
- ARM_FEATURE): New macros.
-
-2005-12-07 Hans-Peter Nilsson
-
- * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
- (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
- (ADD_PC_INCR_OPCODE): Don't define.
-
-2005-12-06 H.J. Lu
-
- PR gas/1874
- * i386.h (i386_optab): Add 64bit support for monitor and mwait.
-
-2005-11-14 David Ung
-
- * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
- instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
- save/restore encoding of the args field.
-
-2005-10-28 Dave Brolley
-
- Contribute the following changes:
- 2005-02-16 Dave Brolley
-
- * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
- cgen_isa_mask_* to cgen_bitset_*.
- * cgen.h: Likewise.
-
- 2003-10-21 Richard Sandiford
-
- * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
- (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
- (CGEN_CPU_TABLE): Make isas a ponter.
-
- 2003-09-29 Dave Brolley
-
- * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
- (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
- (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
-
- 2002-12-13 Dave Brolley
-
- * cgen.h (symcat.h): #include it.
- (cgen-bitset.h): #include it.
- (CGEN_ATTR_VALUE_TYPE): Now a union.
- (CGEN_ATTR_VALUE): Reference macros generated in opcodes/-desc.h.
- (CGEN_ATTR_ENTRY): 'value' now unsigned.
- (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
- * cgen-bitset.h: New file.
-
-2005-09-30 Catherine Moore
-
- * bfin.h: New file.
-
-2005-10-24 Jan Beulich
-
- * ia64.h (enum ia64_opnd): Move memory operand out of set of
- indirect operands.
-
-2005-10-16 John David Anglin
-
- * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
- Add FLAG_STRICT to pa10 ftest opcode.
-
-2005-10-12 John David Anglin
-
- * hppa.h (pa_opcodes): Remove lha entries.
-
-2005-10-08 John David Anglin
-
- * hppa.h (FLAG_STRICT): Revise comment.
- (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
- before corresponding pa11 opcodes. Add strict pa10 register-immediate
- entries for "fdc".
-
-2005-09-30 Catherine Moore
-
- * bfin.h: New file.
-
-2005-09-24 John David Anglin
-
- * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
-
-2005-09-06 Chao-ying Fu
-
- * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
- OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
- define.
- Document !, $, *, &, g, +t, +T operand formats for MT instructions.
- (INSN_ASE_MASK): Update to include INSN_MT.
- (INSN_MT): New define for MT ASE.
-
-2005-08-25 Chao-ying Fu
-
- * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
- OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
- OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
- OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
- OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
- Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
- instructions.
- (INSN_DSP): New define for DSP ASE.
-
-2005-08-18 Alan Modra
-
- * a29k.h: Delete.
-
-2005-08-15 Daniel Jacobowitz
-
- * ppc.h (PPC_OPCODE_E300): Define.
-
-2005-08-12 Martin Schwidefsky
-
- * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
-
-2005-07-28 John David Anglin
-
- PR gas/336
- * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
- and pitlb.
-
-2005-07-27 Jan Beulich
-
- * i386.h (i386_optab): Add comment to movd. Use LongMem for all
- movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
- Add movq-s as 64-bit variants of movd-s.
-
-2005-07-18 John David Anglin
-
- * hppa.h: Fix punctuation in comment.
-
- * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
- implicit space-register addressing. Set space-register bits on opcodes
- using implicit space-register addressing. Add various missing pa20
- long-immediate opcodes. Remove various opcodes using implicit 3-bit
- space-register addressing. Use "fE" instead of "fe" in various
- fstw opcodes.
-
-2005-07-18 Jan Beulich
-
- * i386.h (i386_optab): Operands of aam and aad are unsigned.
-
-2007-07-15 H.J. Lu
-
- * i386.h (i386_optab): Support Intel VMX Instructions.
-
-2005-07-10 John David Anglin
-
- * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
-
-2005-07-05 Jan Beulich
-
- * i386.h (i386_optab): Add new insns.
-
-2005-07-01 Nick Clifton
-
- * sparc.h: Add typedefs to structure declarations.
-
-2005-06-20 H.J. Lu
-
- PR 1013
- * i386.h (i386_optab): Update comments for 64bit addressing on
- mov. Allow 64bit addressing for mov and movq.
-
-2005-06-11 John David Anglin
-
- * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
- respectively, in various floating-point load and store patterns.
-
-2005-05-23 John David Anglin
-
- * hppa.h (FLAG_STRICT): Correct comment.
- (pa_opcodes): Update load and store entries to allow both PA 1.X and
- PA 2.0 mneumonics when equivalent. Entries with cache control
- completers now require PA 1.1. Adjust whitespace.
-
-2005-05-19 Anton Blanchard
-
- * ppc.h (PPC_OPCODE_POWER5): Define.
-
-2005-05-10 Nick Clifton
-
- * Update the address and phone number of the FSF organization in
- the GPL notices in the following files:
- a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
- crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
- i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
- mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
- pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
- tic54x.h, tic80.h, v850.h, vax.h
-
-2005-05-09 Jan Beulich
-
- * i386.h (i386_optab): Add ht and hnt.
-
-2005-04-18 Mark Kettenis
-
- * i386.h: Insert hyphens into selected VIA PadLock extensions.
- Add xcrypt-ctr. Provide aliases without hyphens.
-
-2005-04-13 H.J. Lu
-
- Moved from ../ChangeLog
-
- 2005-04-12 Paul Brook
- * m88k.h: Rename psr macros to avoid conflicts.
-
- 2005-03-12 Zack Weinberg
- * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
- Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
- and ARM_ARCH_V6ZKT2.
-
- 2004-11-29 Tomer Levi
- * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
- Remove redundant instruction types.
- (struct argument): X_op - new field.
- (struct cst4_entry): Remove.
- (no_op_insn): Declare.
-
- 2004-11-05 Tomer Levi
- * crx.h (enum argtype): Rename types, remove unused types.
-
- 2004-10-27 Tomer Levi
- * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
- (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
- (enum operand_type): Rearrange operands, edit comments.
- replace us with ui for unsigned immediate.
- replace d with disps/dispu/dispe for signed/unsigned/escaped
- displacements (respectively).
- replace rbase_ridx_scl2_dispu with rindex_disps for register index.
- (instruction type): Add NO_TYPE_INS.
- (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
- (operand_entry): New field - 'flags'.
- (operand flags): New.
-
- 2004-10-21 Tomer Levi
- * crx.h (operand_type): Remove redundant types i3, i4,
- i5, i8, i12.
- Add new unsigned immediate types us3, us4, us5, us16.
-
-2005-04-12 Mark Kettenis
-
- * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
- adjust them accordingly.
-
-2005-04-01 Jan Beulich
-
- * i386.h (i386_optab): Add rdtscp.
-
-2005-03-29 H.J. Lu
-
- * i386.h (i386_optab): Don't allow the `l' suffix for moving
- between memory and segment register. Allow movq for moving between
- general-purpose register and segment register.
-
-2005-02-09 Jan Beulich
-
- PR gas/707
- * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
- FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
- fnstsw.
-
-2006-02-07 Nathan Sidwell
-
- * m68k.h (m68008, m68ec030, m68882): Remove.
- (m68k_mask): New.
- (cpu_m68k, cpu_cf): New.
- (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
- mcf5470, mcf5480): Rename to cpu_. Add m680x0 variants.
-
-2005-01-25 Alexandre Oliva
-
- 2004-11-10 Alexandre Oliva
- * cgen.h (enum cgen_parse_operand_type): Add
- CGEN_PARSE_OPERAND_SYMBOLIC.
-
-2005-01-21 Fred Fish
-
- * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
- Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
- Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
-
-2005-01-19 Fred Fish
-
- * mips.h (struct mips_opcode): Add new pinfo2 member.
- (INSN_ALIAS): New define for opcode table entries that are
- specific instances of another entry, such as 'move' for an 'or'
- with a zero operand.
- (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
- (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
-
-2004-12-09 Ian Lance Taylor
-
- * mips.h (CPU_RM9000): Define.
- (OPCODE_IS_MEMBER): Handle CPU_RM9000.
-
-2004-11-25 Jan Beulich
-
- * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
- to/from test registers are illegal in 64-bit mode. Add missing
- NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
- (previously one had to explicitly encode a rex64 prefix). Re-enable
- lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
- support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
-
-2004-11-23 Jan Beulich
-
- * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
- available only with SSE2. Change the MMX additions introduced by SSE
- and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
- instructions by their now designated identifier (since combining i686
- and 3DNow! does not really imply 3DNow!A).
-
-2004-11-19 Alan Modra
-
- * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
- struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
-
-2004-11-08 Inderpreet Singh
- Vineet Sharma
-
- * maxq.h: New file: Disassembly information for the maxq port.
-
-2004-11-05 H.J. Lu
-
- * i386.h (i386_optab): Put back "movzb".
-
-2004-11-04 Hans-Peter Nilsson
-
- * cris.h (enum cris_insn_version_usage): Tweak formatting and
- comments. Remove member cris_ver_sim. Add members
- cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
- cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
- (struct cris_support_reg, struct cris_cond15): New types.
- (cris_conds15): Declare.
- (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
- (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
- (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
- (NOP_Z_BITS): Define in terms of NOP_OPCODE.
- (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
- SIZE_FIELD_UNSIGNED.
-
-2004-11-04 Jan Beulich
-
- * i386.h (sldx_Suf): Remove.
- (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
- (q_FP): Define, implying no REX64.
- (x_FP, sl_FP): Imply FloatMF.
- (i386_optab): Split reg and mem forms of moving from segment registers
- so that the memory forms can ignore the 16-/32-bit operand size
- distinction. Adjust a few others for Intel mode. Remove *FP uses from
- all non-floating-point instructions. Unite 32- and 64-bit forms of
- movsx, movzx, and movd. Adjust floating point operations for the above
- changes to the *FP macros. Add DefaultSize to floating point control
- insns operating on larger memory ranges. Remove left over comments
- hinting at certain insns being Intel-syntax ones where the ones
- actually meant are already gone.
-
-2004-10-07 Tomer Levi
-
- * crx.h: Add COPS_REG_INS - Coprocessor Special register
- instruction type.
-
-2004-09-30 Paul Brook
-
- * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
- (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
-
-2004-09-11 Theodore A. Roth
-
- * avr.h: Add support for
- atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
-
-2004-09-09 Segher Boessenkool
-
- * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
-
-2004-08-24 Dmitry Diky
-
- * msp430.h (msp430_opc): Add new instructions.
- (msp430_rcodes): Declare new instructions.
- (msp430_hcodes): Likewise..
-
-2004-08-13 Nick Clifton
-
- PR/301
- * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
- processors.
-
-2004-08-30 Michal Ludvig
-
- * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
-
-2004-07-22 H.J. Lu
-
- * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
-
-2004-07-21 Jan Beulich
-
- * i386.h: Adjust instruction descriptions to better match the
- specification.
-
-2004-07-16 Richard Earnshaw
-
- * arm.h: Remove all old content. Replace with architecture defines
- from gas/config/tc-arm.c.
-
-2004-07-09 Andreas Schwab
-
- * m68k.h: Fix comment.
-
-2004-07-07 Tomer Levi
-
- * crx.h: New file.
-
-2004-06-24 Alan Modra
-
- * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
-
-2004-05-24 Peter Barada
-
- * m68k.h: Add 'size' to m68k_opcode.
-
-2004-05-05 Peter Barada
-
- * m68k.h: Switch from ColdFire chip name to core variant.
-
-2004-04-22 Peter Barada
-
- * m68k.h: Add mcfmac/mcfemac definitions. Update operand
- descriptions for new EMAC cases.
- Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
- handle Motorola MAC syntax.
- Allow disassembly of ColdFire V4e object files.
-
-2004-03-16 Alan Modra
-
- * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
-
-2004-03-12 Jakub Jelinek
-
- * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
-
-2004-03-12 Michal Ludvig
-
- * i386.h (i386_optab): Added xstore as an alias for xstorerng.
-
-2004-03-12 Michal Ludvig
-
- * i386.h (i386_optab): Added xstore/xcrypt insns.
-
-2004-02-09 Anil Paranjpe
-
- * h8300.h (32bit ldc/stc): Add relaxing support.
-
-2004-01-12 Anil Paranjpe
-
- * h8300.h (BITOP): Pass MEMRELAX flag.
-
-2004-01-09 Anil Paranjpe
-
- * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
- except for the H8S.
-
-For older changes see ChangeLog-9103
-
-Local Variables:
-mode: change-log
-left-margin: 8
-fill-column: 74
-version-control: never
-End:
ChangeLog
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: ia64.h
===================================================================
--- ia64.h (revision 816)
+++ ia64.h (nonexistent)
@@ -1,397 +0,0 @@
-/* ia64.h -- Header file for ia64 opcode table
- Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006
- Free Software Foundation, Inc.
- Contributed by David Mosberger-Tang */
-
-#ifndef opcode_ia64_h
-#define opcode_ia64_h
-
-#include
-
-#include "bfd.h"
-
-
-typedef BFD_HOST_U_64_BIT ia64_insn;
-
-enum ia64_insn_type
- {
- IA64_TYPE_NIL = 0, /* illegal type */
- IA64_TYPE_A, /* integer alu (I- or M-unit) */
- IA64_TYPE_I, /* non-alu integer (I-unit) */
- IA64_TYPE_M, /* memory (M-unit) */
- IA64_TYPE_B, /* branch (B-unit) */
- IA64_TYPE_F, /* floating-point (F-unit) */
- IA64_TYPE_X, /* long encoding (X-unit) */
- IA64_TYPE_DYN, /* Dynamic opcode */
- IA64_NUM_TYPES
- };
-
-enum ia64_unit
- {
- IA64_UNIT_NIL = 0, /* illegal unit */
- IA64_UNIT_I, /* integer unit */
- IA64_UNIT_M, /* memory unit */
- IA64_UNIT_B, /* branching unit */
- IA64_UNIT_F, /* floating-point unit */
- IA64_UNIT_L, /* long "unit" */
- IA64_UNIT_X, /* may be integer or branch unit */
- IA64_NUM_UNITS
- };
-
-/* Changes to this enumeration must be propagated to the operand table in
- bfd/cpu-ia64-opc.c
- */
-enum ia64_opnd
- {
- IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/
-
- /* constants */
- IA64_OPND_AR_CSD, /* application register csd (ar.csd) */
- IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */
- IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */
- IA64_OPND_C1, /* the constant 1 */
- IA64_OPND_C8, /* the constant 8 */
- IA64_OPND_C16, /* the constant 16 */
- IA64_OPND_GR0, /* gr0 */
- IA64_OPND_IP, /* instruction pointer (ip) */
- IA64_OPND_PR, /* predicate register (pr) */
- IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */
- IA64_OPND_PSR, /* processor status register (psr) */
- IA64_OPND_PSR_L, /* processor status register L (psr.l) */
- IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */
-
- /* register operands: */
- IA64_OPND_AR3, /* third application register # (bits 20-26) */
- IA64_OPND_B1, /* branch register # (bits 6-8) */
- IA64_OPND_B2, /* branch register # (bits 13-15) */
- IA64_OPND_CR3, /* third control register # (bits 20-26) */
- IA64_OPND_F1, /* first floating-point register # */
- IA64_OPND_F2, /* second floating-point register # */
- IA64_OPND_F3, /* third floating-point register # */
- IA64_OPND_F4, /* fourth floating-point register # */
- IA64_OPND_P1, /* first predicate # */
- IA64_OPND_P2, /* second predicate # */
- IA64_OPND_R1, /* first register # */
- IA64_OPND_R2, /* second register # */
- IA64_OPND_R3, /* third register # */
- IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */
-
- /* memory operands: */
- IA64_OPND_MR3, /* memory at addr of third register # */
-
- /* indirect operands: */
- IA64_OPND_CPUID_R3, /* cpuid[reg] */
- IA64_OPND_DBR_R3, /* dbr[reg] */
- IA64_OPND_DTR_R3, /* dtr[reg] */
- IA64_OPND_ITR_R3, /* itr[reg] */
- IA64_OPND_IBR_R3, /* ibr[reg] */
- IA64_OPND_MSR_R3, /* msr[reg] */
- IA64_OPND_PKR_R3, /* pkr[reg] */
- IA64_OPND_PMC_R3, /* pmc[reg] */
- IA64_OPND_PMD_R3, /* pmd[reg] */
- IA64_OPND_RR_R3, /* rr[reg] */
-
- /* immediate operands: */
- IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */
- IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */
- IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */
- IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
- IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */
- IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */
- IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */
- IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */
- IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */
- IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */
- IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */
- IA64_OPND_IMMU5b, /* unsigned 5-bit immediate (32 + bits 14-18) */
- IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */
- IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */
- IA64_OPND_SOF, /* 8-bit stack frame size */
- IA64_OPND_SOL, /* 8-bit size of locals */
- IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */
- IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */
- IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
- IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */
- IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
- IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
- IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */
- IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */
- IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */
- IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */
- IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
- IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */
- IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */
- IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
- IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */
- IA64_OPND_IMMU62, /* unsigned 62-bit immediate */
- IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */
- IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
- IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */
- IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */
- IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */
- IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */
- IA64_OPND_POS6, /* 6-bit count (bits 14-19) */
- IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
- IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */
- IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */
- IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
- IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */
- IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
- IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */
-
- IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */
- };
-
-enum ia64_dependency_mode
-{
- IA64_DV_RAW,
- IA64_DV_WAW,
- IA64_DV_WAR,
-};
-
-enum ia64_dependency_semantics
-{
- IA64_DVS_NONE,
- IA64_DVS_IMPLIED,
- IA64_DVS_IMPLIEDF,
- IA64_DVS_DATA,
- IA64_DVS_INSTR,
- IA64_DVS_SPECIFIC,
- IA64_DVS_STOP,
- IA64_DVS_OTHER,
-};
-
-enum ia64_resource_specifier
-{
- IA64_RS_ANY,
- IA64_RS_AR_K,
- IA64_RS_AR_UNAT,
- IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
- IA64_RS_ARb, /* 48-63, 112-127 */
- IA64_RS_BR,
- IA64_RS_CFM,
- IA64_RS_CPUID,
- IA64_RS_CR_IIB,
- IA64_RS_CR_IRR,
- IA64_RS_CR_LRR,
- IA64_RS_CR, /* 3-7,10-15,18,28-63,75-79,82-127 */
- IA64_RS_DBR,
- IA64_RS_FR,
- IA64_RS_FRb,
- IA64_RS_GR0,
- IA64_RS_GR,
- IA64_RS_IBR,
- IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */
- IA64_RS_MSR,
- IA64_RS_PKR,
- IA64_RS_PMC,
- IA64_RS_PMD,
- IA64_RS_PR, /* non-rotating, 1-15 */
- IA64_RS_PRr, /* rotating, 16-62 */
- IA64_RS_PR63,
- IA64_RS_RR,
-
- IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */
- IA64_RS_CRX, /* CRs not in RS_CR */
- IA64_RS_PSR, /* PSR bits */
- IA64_RS_RSE, /* implementation-specific RSE resources */
- IA64_RS_AR_FPSR,
-};
-
-enum ia64_rse_resource
-{
- IA64_RSE_N_STACKED_PHYS,
- IA64_RSE_BOF,
- IA64_RSE_STORE_REG,
- IA64_RSE_LOAD_REG,
- IA64_RSE_BSPLOAD,
- IA64_RSE_RNATBITINDEX,
- IA64_RSE_CFLE,
- IA64_RSE_NDIRTY,
-};
-
-/* Information about a given resource dependency */
-struct ia64_dependency
-{
- /* Name of the resource */
- const char *name;
- /* Does this dependency need further specification? */
- enum ia64_resource_specifier specifier;
- /* Mode of dependency */
- enum ia64_dependency_mode mode;
- /* Dependency semantics */
- enum ia64_dependency_semantics semantics;
- /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
-#define REG_NONE (-1)
- int regindex;
- /* Special info on semantics */
- const char *info;
-};
-
-/* Two arrays of indexes into the ia64_dependency table.
- chks are dependencies to check for conflicts when an opcode is
- encountered; regs are dependencies to register (mark as used) when an
- opcode is used. chks correspond to readers (RAW) or writers (WAW or
- WAR) of a resource, while regs correspond to writers (RAW or WAW) and
- readers (WAR) of a resource. */
-struct ia64_opcode_dependency
-{
- int nchks;
- const unsigned short *chks;
- int nregs;
- const unsigned short *regs;
-};
-
-/* encode/extract the note/index for a dependency */
-#define RDEP(N,X) (((N)<<11)|(X))
-#define NOTE(X) (((X)>>11)&0x1F)
-#define DEP(X) ((X)&0x7FF)
-
-/* A template descriptor describes the execution units that are active
- for each of the three slots. It also specifies the location of
- instruction group boundaries that may be present between two slots. */
-struct ia64_templ_desc
- {
- int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */
- enum ia64_unit exec_unit[3];
- const char *name;
- };
-
-/* The opcode table is an array of struct ia64_opcode. */
-
-struct ia64_opcode
- {
- /* The opcode name. */
- const char *name;
-
- /* The type of the instruction: */
- enum ia64_insn_type type;
-
- /* Number of output operands: */
- int num_outputs;
-
- /* The opcode itself. Those bits which will be filled in with
- operands are zeroes. */
- ia64_insn opcode;
-
- /* The opcode mask. This is used by the disassembler. This is a
- mask containing ones indicating those bits which must match the
- opcode field, and zeroes indicating those bits which need not
- match (and are presumably filled in by operands). */
- ia64_insn mask;
-
- /* An array of operand codes. Each code is an index into the
- operand table. They appear in the order which the operands must
- appear in assembly code, and are terminated by a zero. */
- enum ia64_opnd operands[5];
-
- /* One bit flags for the opcode. These are primarily used to
- indicate specific processors and environments support the
- instructions. The defined values are listed below. */
- unsigned int flags;
-
- /* Used by ia64_find_next_opcode (). */
- short ent_index;
-
- /* Opcode dependencies. */
- const struct ia64_opcode_dependency *dependencies;
- };
-
-/* Values defined for the flags field of a struct ia64_opcode. */
-
-#define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */
-#define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */
-#define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */
-#define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */
-#define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */
-#define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */
-#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */
-#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */
-#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */
-#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */
-#define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */
-
-/* A macro to extract the major opcode from an instruction. */
-#define IA64_OP(i) (((i) >> 37) & 0xf)
-
-enum ia64_operand_class
- {
- IA64_OPND_CLASS_CST, /* constant */
- IA64_OPND_CLASS_REG, /* register */
- IA64_OPND_CLASS_IND, /* indirect register */
- IA64_OPND_CLASS_ABS, /* absolute value */
- IA64_OPND_CLASS_REL, /* IP-relative value */
- };
-
-/* The operands table is an array of struct ia64_operand. */
-
-struct ia64_operand
-{
- enum ia64_operand_class op_class;
-
- /* Set VALUE as the operand bits for the operand of type SELF in the
- instruction pointed to by CODE. If an error occurs, *CODE is not
- modified and the returned string describes the cause of the
- error. If no error occurs, NULL is returned. */
- const char *(*insert) (const struct ia64_operand *self, ia64_insn value,
- ia64_insn *code);
-
- /* Extract the operand bits for an operand of type SELF from
- instruction CODE store them in *VALUE. If an error occurs, the
- cause of the error is described by the string returned. If no
- error occurs, NULL is returned. */
- const char *(*extract) (const struct ia64_operand *self, ia64_insn code,
- ia64_insn *value);
-
- /* A string whose meaning depends on the operand class. */
-
- const char *str;
-
- struct bit_field
- {
- /* The number of bits in the operand. */
- int bits;
-
- /* How far the operand is left shifted in the instruction. */
- int shift;
- }
- field[4]; /* no operand has more than this many bit-fields */
-
- unsigned int flags;
-
- const char *desc; /* brief description */
-};
-
-/* Values defined for the flags field of a struct ia64_operand. */
-
-/* Disassemble as signed decimal (instead of hex): */
-#define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0)
-/* Disassemble as unsigned decimal (instead of hex): */
-#define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1)
-
-extern const struct ia64_templ_desc ia64_templ_desc[16];
-
-/* The tables are sorted by major opcode number and are otherwise in
- the order in which the disassembler should consider instructions. */
-extern struct ia64_opcode ia64_opcodes_a[];
-extern struct ia64_opcode ia64_opcodes_i[];
-extern struct ia64_opcode ia64_opcodes_m[];
-extern struct ia64_opcode ia64_opcodes_b[];
-extern struct ia64_opcode ia64_opcodes_f[];
-extern struct ia64_opcode ia64_opcodes_d[];
-
-
-extern struct ia64_opcode *ia64_find_opcode (const char *name);
-extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent);
-
-extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn,
- enum ia64_insn_type type);
-
-extern void ia64_free_opcode (struct ia64_opcode *ent);
-extern const struct ia64_dependency *ia64_find_dependency (int index);
-
-/* To avoid circular library dependencies, this array is implemented
- in bfd/cpu-ia64-opc.c: */
-extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT];
-
-#endif /* opcode_ia64_h */
ia64.h
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: mips.h
===================================================================
--- mips.h (revision 816)
+++ mips.h (nonexistent)
@@ -1,1109 +0,0 @@
-/* mips.h. Mips opcode list for GDB, the GNU debugger.
- Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
- 2003, 2004, 2005, 2008, 2009
- Free Software Foundation, Inc.
- Contributed by Ralph Campbell and OSF
- Commented and modified by Ian Lance Taylor, Cygnus Support
-
-This file is part of GDB, GAS, and the GNU binutils.
-
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
-
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
-#ifndef _MIPS_H_
-#define _MIPS_H_
-
-/* These are bit masks and shift counts to use to access the various
- fields of an instruction. To retrieve the X field of an
- instruction, use the expression
- (i >> OP_SH_X) & OP_MASK_X
- To set the same field (to j), use
- i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
-
- Make sure you use fields that are appropriate for the instruction,
- of course.
-
- The 'i' format uses OP, RS, RT and IMMEDIATE.
-
- The 'j' format uses OP and TARGET.
-
- The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
-
- The 'b' format uses OP, RS, RT and DELTA.
-
- The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
-
- The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
-
- A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
- breakpoint instruction are not defined; Kane says the breakpoint
- code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
- only use ten bits). An optional two-operand form of break/sdbbp
- allows the lower ten bits to be set too, and MIPS32 and later
- architectures allow 20 bits to be set with a signal operand
- (using CODE20).
-
- The syscall instruction uses CODE20.
-
- The general coprocessor instructions use COPZ. */
-
-#define OP_MASK_OP 0x3f
-#define OP_SH_OP 26
-#define OP_MASK_RS 0x1f
-#define OP_SH_RS 21
-#define OP_MASK_FR 0x1f
-#define OP_SH_FR 21
-#define OP_MASK_FMT 0x1f
-#define OP_SH_FMT 21
-#define OP_MASK_BCC 0x7
-#define OP_SH_BCC 18
-#define OP_MASK_CODE 0x3ff
-#define OP_SH_CODE 16
-#define OP_MASK_CODE2 0x3ff
-#define OP_SH_CODE2 6
-#define OP_MASK_RT 0x1f
-#define OP_SH_RT 16
-#define OP_MASK_FT 0x1f
-#define OP_SH_FT 16
-#define OP_MASK_CACHE 0x1f
-#define OP_SH_CACHE 16
-#define OP_MASK_RD 0x1f
-#define OP_SH_RD 11
-#define OP_MASK_FS 0x1f
-#define OP_SH_FS 11
-#define OP_MASK_PREFX 0x1f
-#define OP_SH_PREFX 11
-#define OP_MASK_CCC 0x7
-#define OP_SH_CCC 8
-#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
-#define OP_SH_CODE20 6
-#define OP_MASK_SHAMT 0x1f
-#define OP_SH_SHAMT 6
-#define OP_MASK_FD 0x1f
-#define OP_SH_FD 6
-#define OP_MASK_TARGET 0x3ffffff
-#define OP_SH_TARGET 0
-#define OP_MASK_COPZ 0x1ffffff
-#define OP_SH_COPZ 0
-#define OP_MASK_IMMEDIATE 0xffff
-#define OP_SH_IMMEDIATE 0
-#define OP_MASK_DELTA 0xffff
-#define OP_SH_DELTA 0
-#define OP_MASK_FUNCT 0x3f
-#define OP_SH_FUNCT 0
-#define OP_MASK_SPEC 0x3f
-#define OP_SH_SPEC 0
-#define OP_SH_LOCC 8 /* FP condition code. */
-#define OP_SH_HICC 18 /* FP condition code. */
-#define OP_MASK_CC 0x7
-#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
-#define OP_MASK_COP1NORM 0x1 /* a single bit. */
-#define OP_SH_COP1SPEC 21 /* COP1 encodings. */
-#define OP_MASK_COP1SPEC 0xf
-#define OP_MASK_COP1SCLR 0x4
-#define OP_MASK_COP1CMP 0x3
-#define OP_SH_COP1CMP 4
-#define OP_SH_FORMAT 21 /* FP short format field. */
-#define OP_MASK_FORMAT 0x7
-#define OP_SH_TRUE 16
-#define OP_MASK_TRUE 0x1
-#define OP_SH_GE 17
-#define OP_MASK_GE 0x01
-#define OP_SH_UNSIGNED 16
-#define OP_MASK_UNSIGNED 0x1
-#define OP_SH_HINT 16
-#define OP_MASK_HINT 0x1f
-#define OP_SH_MMI 0 /* Multimedia (parallel) op. */
-#define OP_MASK_MMI 0x3f
-#define OP_SH_MMISUB 6
-#define OP_MASK_MMISUB 0x1f
-#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
-#define OP_SH_PERFREG 1
-#define OP_SH_SEL 0 /* Coprocessor select field. */
-#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
-#define OP_SH_CODE19 6 /* 19 bit wait code. */
-#define OP_MASK_CODE19 0x7ffff
-#define OP_SH_ALN 21
-#define OP_MASK_ALN 0x7
-#define OP_SH_VSEL 21
-#define OP_MASK_VSEL 0x1f
-#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
- but 0x8-0xf don't select bytes. */
-#define OP_SH_VECBYTE 22
-#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
-#define OP_SH_VECALIGN 21
-#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
-#define OP_SH_INSMSB 11
-#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
-#define OP_SH_EXTMSBD 11
-
-/* MIPS DSP ASE */
-#define OP_SH_DSPACC 11
-#define OP_MASK_DSPACC 0x3
-#define OP_SH_DSPACC_S 21
-#define OP_MASK_DSPACC_S 0x3
-#define OP_SH_DSPSFT 20
-#define OP_MASK_DSPSFT 0x3f
-#define OP_SH_DSPSFT_7 19
-#define OP_MASK_DSPSFT_7 0x7f
-#define OP_SH_SA3 21
-#define OP_MASK_SA3 0x7
-#define OP_SH_SA4 21
-#define OP_MASK_SA4 0xf
-#define OP_SH_IMM8 16
-#define OP_MASK_IMM8 0xff
-#define OP_SH_IMM10 16
-#define OP_MASK_IMM10 0x3ff
-#define OP_SH_WRDSP 11
-#define OP_MASK_WRDSP 0x3f
-#define OP_SH_RDDSP 16
-#define OP_MASK_RDDSP 0x3f
-#define OP_SH_BP 11
-#define OP_MASK_BP 0x3
-
-/* MIPS MT ASE */
-#define OP_SH_MT_U 5
-#define OP_MASK_MT_U 0x1
-#define OP_SH_MT_H 4
-#define OP_MASK_MT_H 0x1
-#define OP_SH_MTACC_T 18
-#define OP_MASK_MTACC_T 0x3
-#define OP_SH_MTACC_D 13
-#define OP_MASK_MTACC_D 0x3
-
-#define OP_OP_COP0 0x10
-#define OP_OP_COP1 0x11
-#define OP_OP_COP2 0x12
-#define OP_OP_COP3 0x13
-#define OP_OP_LWC1 0x31
-#define OP_OP_LWC2 0x32
-#define OP_OP_LWC3 0x33 /* a.k.a. pref */
-#define OP_OP_LDC1 0x35
-#define OP_OP_LDC2 0x36
-#define OP_OP_LDC3 0x37 /* a.k.a. ld */
-#define OP_OP_SWC1 0x39
-#define OP_OP_SWC2 0x3a
-#define OP_OP_SWC3 0x3b
-#define OP_OP_SDC1 0x3d
-#define OP_OP_SDC2 0x3e
-#define OP_OP_SDC3 0x3f /* a.k.a. sd */
-
-/* Values in the 'VSEL' field. */
-#define MDMX_FMTSEL_IMM_QH 0x1d
-#define MDMX_FMTSEL_IMM_OB 0x1e
-#define MDMX_FMTSEL_VEC_QH 0x15
-#define MDMX_FMTSEL_VEC_OB 0x16
-
-/* UDI */
-#define OP_SH_UDI1 6
-#define OP_MASK_UDI1 0x1f
-#define OP_SH_UDI2 6
-#define OP_MASK_UDI2 0x3ff
-#define OP_SH_UDI3 6
-#define OP_MASK_UDI3 0x7fff
-#define OP_SH_UDI4 6
-#define OP_MASK_UDI4 0xfffff
-
-/* Octeon */
-#define OP_SH_BBITIND 16
-#define OP_MASK_BBITIND 0x1f
-#define OP_SH_CINSPOS 6
-#define OP_MASK_CINSPOS 0x1f
-#define OP_SH_CINSLM1 11
-#define OP_MASK_CINSLM1 0x1f
-#define OP_SH_SEQI 6
-#define OP_MASK_SEQI 0x3ff
-
-/* This structure holds information for a particular instruction. */
-
-struct mips_opcode
-{
- /* The name of the instruction. */
- const char *name;
- /* A string describing the arguments for this instruction. */
- const char *args;
- /* The basic opcode for the instruction. When assembling, this
- opcode is modified by the arguments to produce the actual opcode
- that is used. If pinfo is INSN_MACRO, then this is 0. */
- unsigned long match;
- /* If pinfo is not INSN_MACRO, then this is a bit mask for the
- relevant portions of the opcode when disassembling. If the
- actual opcode anded with the match field equals the opcode field,
- then we have found the correct instruction. If pinfo is
- INSN_MACRO, then this field is the macro identifier. */
- unsigned long mask;
- /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
- of bits describing the instruction, notably any relevant hazard
- information. */
- unsigned long pinfo;
- /* A collection of additional bits describing the instruction. */
- unsigned long pinfo2;
- /* A collection of bits describing the instruction sets of which this
- instruction or macro is a member. */
- unsigned long membership;
-};
-
-/* These are the characters which may appear in the args field of an
- instruction. They appear in the order in which the fields appear
- when the instruction is used. Commas and parentheses in the args
- string are ignored when assembling, and written into the output
- when disassembling.
-
- Each of these characters corresponds to a mask field defined above.
-
- "1" 5 bit sync type (OP_*_SHAMT)
- "<" 5 bit shift amount (OP_*_SHAMT)
- ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
- "a" 26 bit target address (OP_*_TARGET)
- "b" 5 bit base register (OP_*_RS)
- "c" 10 bit breakpoint code (OP_*_CODE)
- "d" 5 bit destination register specifier (OP_*_RD)
- "h" 5 bit prefx hint (OP_*_PREFX)
- "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
- "j" 16 bit signed immediate (OP_*_DELTA)
- "k" 5 bit cache opcode in target register position (OP_*_CACHE)
- Also used for immediate operands in vr5400 vector insns.
- "o" 16 bit signed offset (OP_*_DELTA)
- "p" 16 bit PC relative branch target address (OP_*_DELTA)
- "q" 10 bit extra breakpoint code (OP_*_CODE2)
- "r" 5 bit same register used as both source and target (OP_*_RS)
- "s" 5 bit source register specifier (OP_*_RS)
- "t" 5 bit target register (OP_*_RT)
- "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
- "v" 5 bit same register used as both source and destination (OP_*_RS)
- "w" 5 bit same register used as both target and destination (OP_*_RT)
- "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
- (used by clo and clz)
- "C" 25 bit coprocessor function code (OP_*_COPZ)
- "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
- "J" 19 bit wait function code (OP_*_CODE19)
- "x" accept and ignore register name
- "z" must be zero register
- "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
- "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
- LSB (OP_*_SHAMT).
- Enforces: 0 <= pos < 32.
- "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
- Requires that "+A" or "+E" occur first to set position.
- Enforces: 0 < (pos+size) <= 32.
- "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
- Requires that "+A" or "+E" occur first to set position.
- Enforces: 0 < (pos+size) <= 32.
- (Also used by "dext" w/ different limits, but limits for
- that are checked by the M_DEXT macro.)
- "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
- Enforces: 32 <= pos < 64.
- "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
- Requires that "+A" or "+E" occur first to set position.
- Enforces: 32 < (pos+size) <= 64.
- "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
- Requires that "+A" or "+E" occur first to set position.
- Enforces: 32 < (pos+size) <= 64.
- "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
- Requires that "+A" or "+E" occur first to set position.
- Enforces: 32 < (pos+size) <= 64.
-
- Floating point instructions:
- "D" 5 bit destination register (OP_*_FD)
- "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
- "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
- "S" 5 bit fs source 1 register (OP_*_FS)
- "T" 5 bit ft source 2 register (OP_*_FT)
- "R" 5 bit fr source 3 register (OP_*_FR)
- "V" 5 bit same register used as floating source and destination (OP_*_FS)
- "W" 5 bit same register used as floating target and destination (OP_*_FT)
-
- Coprocessor instructions:
- "E" 5 bit target register (OP_*_RT)
- "G" 5 bit destination register (OP_*_RD)
- "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
- "P" 5 bit performance-monitor register (OP_*_PERFREG)
- "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
- "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
- see also "k" above
- "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
- for pretty-printing in disassembly only.
-
- Macro instructions:
- "A" General 32 bit expression
- "I" 32 bit immediate (value placed in imm_expr).
- "+I" 32 bit immediate (value placed in imm2_expr).
- "F" 64 bit floating point constant in .rdata
- "L" 64 bit floating point constant in .lit8
- "f" 32 bit floating point constant
- "l" 32 bit floating point constant in .lit4
-
- MDMX instruction operands (note that while these use the FP register
- fields, they accept both $fN and $vN names for the registers):
- "O" MDMX alignment offset (OP_*_ALN)
- "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
- "X" MDMX destination register (OP_*_FD)
- "Y" MDMX source register (OP_*_FS)
- "Z" MDMX source register (OP_*_FT)
-
- DSP ASE usage:
- "2" 2 bit unsigned immediate for byte align (OP_*_BP)
- "3" 3 bit unsigned immediate (OP_*_SA3)
- "4" 4 bit unsigned immediate (OP_*_SA4)
- "5" 8 bit unsigned immediate (OP_*_IMM8)
- "6" 5 bit unsigned immediate (OP_*_RS)
- "7" 2 bit dsp accumulator register (OP_*_DSPACC)
- "8" 6 bit unsigned immediate (OP_*_WRDSP)
- "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
- "0" 6 bit signed immediate (OP_*_DSPSFT)
- ":" 7 bit signed immediate (OP_*_DSPSFT_7)
- "'" 6 bit unsigned immediate (OP_*_RDDSP)
- "@" 10 bit signed immediate (OP_*_IMM10)
-
- MT ASE usage:
- "!" 1 bit usermode flag (OP_*_MT_U)
- "$" 1 bit load high flag (OP_*_MT_H)
- "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
- "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
- "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
- "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
- "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
-
- UDI immediates:
- "+1" UDI immediate bits 6-10
- "+2" UDI immediate bits 6-15
- "+3" UDI immediate bits 6-20
- "+4" UDI immediate bits 6-25
-
- Octeon:
- "+x" Bit index field of bbit. Enforces: 0 <= index < 32.
- "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64,
- otherwise skips to next candidate.
- "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
- "+P" Position field of cins/exts aliasing cins32/exts32. Matches if
- 32 <= pos < 64, otherwise skips to next candidate.
- "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512.
- "+s" Length-minus-one field of cins/exts. Enforces: 0 <= lenm1 < 32.
- "+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing
- cint32/exts32. Enforces non-negative value and that
- pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous
- position field is "+p" or "+P".
-
- Other:
- "()" parens surrounding optional value
- "," separates operands
- "[]" brackets around index for vector-op scalar operand specifier (vr5400)
- "+" Start of extension sequence.
-
- Characters used so far, for quick reference when adding more:
- "1234567890"
- "%[]<>(),+:'@!$*&"
- "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
- "abcdefghijklopqrstuvwxz"
-
- Extension character sequences used so far ("+" followed by the
- following), for quick reference when adding more:
- "1234"
- "ABCDEFGHIPQSTX"
- "pstx"
-*/
-
-/* These are the bits which may be set in the pinfo field of an
- instructions, if it is not equal to INSN_MACRO. */
-
-/* Modifies the general purpose register in OP_*_RD. */
-#define INSN_WRITE_GPR_D 0x00000001
-/* Modifies the general purpose register in OP_*_RT. */
-#define INSN_WRITE_GPR_T 0x00000002
-/* Modifies general purpose register 31. */
-#define INSN_WRITE_GPR_31 0x00000004
-/* Modifies the floating point register in OP_*_FD. */
-#define INSN_WRITE_FPR_D 0x00000008
-/* Modifies the floating point register in OP_*_FS. */
-#define INSN_WRITE_FPR_S 0x00000010
-/* Modifies the floating point register in OP_*_FT. */
-#define INSN_WRITE_FPR_T 0x00000020
-/* Reads the general purpose register in OP_*_RS. */
-#define INSN_READ_GPR_S 0x00000040
-/* Reads the general purpose register in OP_*_RT. */
-#define INSN_READ_GPR_T 0x00000080
-/* Reads the floating point register in OP_*_FS. */
-#define INSN_READ_FPR_S 0x00000100
-/* Reads the floating point register in OP_*_FT. */
-#define INSN_READ_FPR_T 0x00000200
-/* Reads the floating point register in OP_*_FR. */
-#define INSN_READ_FPR_R 0x00000400
-/* Modifies coprocessor condition code. */
-#define INSN_WRITE_COND_CODE 0x00000800
-/* Reads coprocessor condition code. */
-#define INSN_READ_COND_CODE 0x00001000
-/* TLB operation. */
-#define INSN_TLB 0x00002000
-/* Reads coprocessor register other than floating point register. */
-#define INSN_COP 0x00004000
-/* Instruction loads value from memory, requiring delay. */
-#define INSN_LOAD_MEMORY_DELAY 0x00008000
-/* Instruction loads value from coprocessor, requiring delay. */
-#define INSN_LOAD_COPROC_DELAY 0x00010000
-/* Instruction has unconditional branch delay slot. */
-#define INSN_UNCOND_BRANCH_DELAY 0x00020000
-/* Instruction has conditional branch delay slot. */
-#define INSN_COND_BRANCH_DELAY 0x00040000
-/* Conditional branch likely: if branch not taken, insn nullified. */
-#define INSN_COND_BRANCH_LIKELY 0x00080000
-/* Moves to coprocessor register, requiring delay. */
-#define INSN_COPROC_MOVE_DELAY 0x00100000
-/* Loads coprocessor register from memory, requiring delay. */
-#define INSN_COPROC_MEMORY_DELAY 0x00200000
-/* Reads the HI register. */
-#define INSN_READ_HI 0x00400000
-/* Reads the LO register. */
-#define INSN_READ_LO 0x00800000
-/* Modifies the HI register. */
-#define INSN_WRITE_HI 0x01000000
-/* Modifies the LO register. */
-#define INSN_WRITE_LO 0x02000000
-/* Takes a trap (easier to keep out of delay slot). */
-#define INSN_TRAP 0x04000000
-/* Instruction stores value into memory. */
-#define INSN_STORE_MEMORY 0x08000000
-/* Instruction uses single precision floating point. */
-#define FP_S 0x10000000
-/* Instruction uses double precision floating point. */
-#define FP_D 0x20000000
-/* Instruction is part of the tx39's integer multiply family. */
-#define INSN_MULT 0x40000000
-/* Instruction synchronize shared memory. */
-#define INSN_SYNC 0x80000000
-/* Instruction is actually a macro. It should be ignored by the
- disassembler, and requires special treatment by the assembler. */
-#define INSN_MACRO 0xffffffff
-
-/* These are the bits which may be set in the pinfo2 field of an
- instruction. */
-
-/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
-#define INSN2_ALIAS 0x00000001
-/* Instruction reads MDMX accumulator. */
-#define INSN2_READ_MDMX_ACC 0x00000002
-/* Instruction writes MDMX accumulator. */
-#define INSN2_WRITE_MDMX_ACC 0x00000004
-/* Macro uses single-precision floating-point instructions. This should
- only be set for macros. For instructions, FP_S in pinfo carries the
- same information. */
-#define INSN2_M_FP_S 0x00000008
-/* Macro uses double-precision floating-point instructions. This should
- only be set for macros. For instructions, FP_D in pinfo carries the
- same information. */
-#define INSN2_M_FP_D 0x00000010
-
-/* Masks used to mark instructions to indicate which MIPS ISA level
- they were introduced in. INSN_ISA_MASK masks an enumeration that
- specifies the base ISA level(s). The remainder of a 32-bit
- word constructed using these macros is a bitmask of the remaining
- INSN_* values below. */
-
-#define INSN_ISA_MASK 0x0000000ful
-
-/* We cannot start at zero due to ISA_UNKNOWN below. */
-#define INSN_ISA1 1
-#define INSN_ISA2 2
-#define INSN_ISA3 3
-#define INSN_ISA4 4
-#define INSN_ISA5 5
-#define INSN_ISA32 6
-#define INSN_ISA32R2 7
-#define INSN_ISA64 8
-#define INSN_ISA64R2 9
-/* Below this point the INSN_* values correspond to combinations of ISAs.
- They are only for use in the opcodes table to indicate membership of
- a combination of ISAs that cannot be expressed using the usual inclusion
- ordering on the above INSN_* values. */
-#define INSN_ISA3_32 10
-#define INSN_ISA3_32R2 11
-#define INSN_ISA4_32 12
-#define INSN_ISA4_32R2 13
-#define INSN_ISA5_32R2 14
-
-/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
- INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
- this table describes whether at least one of the ISAs described by X
- is/are implemented by ISA Y. (Think of Y as the ISA level supported by
- a particular core and X as the ISA level(s) at which a certain instruction
- is defined.) The ISA(s) described by X is/are implemented by Y iff
- (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
- is non-zero. */
-static const unsigned int mips_isa_table[] =
- { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
-
-/* Masks used for Chip specific instructions. */
-#define INSN_CHIP_MASK 0xc3ff0820
-
-/* Cavium Networks Octeon instructions. */
-#define INSN_OCTEON 0x00000800
-
-/* Masks used for MIPS-defined ASEs. */
-#define INSN_ASE_MASK 0x3c00f000
-
-/* DSP ASE */
-#define INSN_DSP 0x00001000
-#define INSN_DSP64 0x00002000
-/* MIPS 16 ASE */
-#define INSN_MIPS16 0x00004000
-/* MIPS-3D ASE */
-#define INSN_MIPS3D 0x00008000
-
-/* MIPS R4650 instruction. */
-#define INSN_4650 0x00010000
-/* LSI R4010 instruction. */
-#define INSN_4010 0x00020000
-/* NEC VR4100 instruction. */
-#define INSN_4100 0x00040000
-/* Toshiba R3900 instruction. */
-#define INSN_3900 0x00080000
-/* MIPS R10000 instruction. */
-#define INSN_10000 0x00100000
-/* Broadcom SB-1 instruction. */
-#define INSN_SB1 0x00200000
-/* NEC VR4111/VR4181 instruction. */
-#define INSN_4111 0x00400000
-/* NEC VR4120 instruction. */
-#define INSN_4120 0x00800000
-/* NEC VR5400 instruction. */
-#define INSN_5400 0x01000000
-/* NEC VR5500 instruction. */
-#define INSN_5500 0x02000000
-
-/* MDMX ASE */
-#define INSN_MDMX 0x04000000
-/* MT ASE */
-#define INSN_MT 0x08000000
-/* SmartMIPS ASE */
-#define INSN_SMARTMIPS 0x10000000
-/* DSP R2 ASE */
-#define INSN_DSPR2 0x20000000
-/* ST Microelectronics Loongson 2E. */
-#define INSN_LOONGSON_2E 0x40000000
-/* ST Microelectronics Loongson 2F. */
-#define INSN_LOONGSON_2F 0x80000000
-/* RMI Xlr instruction */
-#define INSN_XLR 0x00000020
-
-/* MIPS ISA defines, use instead of hardcoding ISA level. */
-
-#define ISA_UNKNOWN 0 /* Gas internal use. */
-#define ISA_MIPS1 INSN_ISA1
-#define ISA_MIPS2 INSN_ISA2
-#define ISA_MIPS3 INSN_ISA3
-#define ISA_MIPS4 INSN_ISA4
-#define ISA_MIPS5 INSN_ISA5
-
-#define ISA_MIPS32 INSN_ISA32
-#define ISA_MIPS64 INSN_ISA64
-
-#define ISA_MIPS32R2 INSN_ISA32R2
-#define ISA_MIPS64R2 INSN_ISA64R2
-
-
-/* CPU defines, use instead of hardcoding processor number. Keep this
- in sync with bfd/archures.c in order for machine selection to work. */
-#define CPU_UNKNOWN 0 /* Gas internal use. */
-#define CPU_R3000 3000
-#define CPU_R3900 3900
-#define CPU_R4000 4000
-#define CPU_R4010 4010
-#define CPU_VR4100 4100
-#define CPU_R4111 4111
-#define CPU_VR4120 4120
-#define CPU_R4300 4300
-#define CPU_R4400 4400
-#define CPU_R4600 4600
-#define CPU_R4650 4650
-#define CPU_R5000 5000
-#define CPU_VR5400 5400
-#define CPU_VR5500 5500
-#define CPU_R6000 6000
-#define CPU_RM7000 7000
-#define CPU_R8000 8000
-#define CPU_RM9000 9000
-#define CPU_R10000 10000
-#define CPU_R12000 12000
-#define CPU_R14000 14000
-#define CPU_R16000 16000
-#define CPU_MIPS16 16
-#define CPU_MIPS32 32
-#define CPU_MIPS32R2 33
-#define CPU_MIPS5 5
-#define CPU_MIPS64 64
-#define CPU_MIPS64R2 65
-#define CPU_SB1 12310201 /* octal 'SB', 01. */
-#define CPU_LOONGSON_2E 3001
-#define CPU_LOONGSON_2F 3002
-#define CPU_OCTEON 6501
-#define CPU_XLR 887682 /* decimal 'XLR' */
-
-/* Test for membership in an ISA including chip specific ISAs. INSN
- is pointer to an element of the opcode table; ISA is the specified
- ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
- test, or zero if no CPU specific ISA test is desired. */
-
-#define OPCODE_IS_MEMBER(insn, isa, cpu) \
- (((isa & INSN_ISA_MASK) != 0 \
- && ((insn)->membership & INSN_ISA_MASK) != 0 \
- && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >> \
- (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) \
- || ((isa & ~INSN_ISA_MASK) \
- & ((insn)->membership & ~INSN_ISA_MASK)) != 0 \
- || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
- || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
- || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
- || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
- || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
- || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
- || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000 \
- || cpu == CPU_R16000) \
- && ((insn)->membership & INSN_10000) != 0) \
- || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
- || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
- || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
- || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
- || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
- || (cpu == CPU_LOONGSON_2E \
- && ((insn)->membership & INSN_LOONGSON_2E) != 0) \
- || (cpu == CPU_LOONGSON_2F \
- && ((insn)->membership & INSN_LOONGSON_2F) != 0) \
- || (cpu == CPU_OCTEON \
- && ((insn)->membership & INSN_OCTEON) != 0) \
- || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
- || 0) /* Please keep this term for easier source merging. */
-
-/* This is a list of macro expanded instructions.
-
- _I appended means immediate
- _A appended means address
- _AB appended means address with base register
- _D appended means 64 bit floating point constant
- _S appended means 32 bit floating point constant. */
-
-enum
-{
- M_ABS,
- M_ADD_I,
- M_ADDU_I,
- M_AND_I,
- M_BALIGN,
- M_BEQ,
- M_BEQ_I,
- M_BEQL_I,
- M_BGE,
- M_BGEL,
- M_BGE_I,
- M_BGEL_I,
- M_BGEU,
- M_BGEUL,
- M_BGEU_I,
- M_BGEUL_I,
- M_BGT,
- M_BGTL,
- M_BGT_I,
- M_BGTL_I,
- M_BGTU,
- M_BGTUL,
- M_BGTU_I,
- M_BGTUL_I,
- M_BLE,
- M_BLEL,
- M_BLE_I,
- M_BLEL_I,
- M_BLEU,
- M_BLEUL,
- M_BLEU_I,
- M_BLEUL_I,
- M_BLT,
- M_BLTL,
- M_BLT_I,
- M_BLTL_I,
- M_BLTU,
- M_BLTUL,
- M_BLTU_I,
- M_BLTUL_I,
- M_BNE,
- M_BNE_I,
- M_BNEL_I,
- M_CACHE_AB,
- M_DABS,
- M_DADD_I,
- M_DADDU_I,
- M_DDIV_3,
- M_DDIV_3I,
- M_DDIVU_3,
- M_DDIVU_3I,
- M_DEXT,
- M_DINS,
- M_DIV_3,
- M_DIV_3I,
- M_DIVU_3,
- M_DIVU_3I,
- M_DLA_AB,
- M_DLCA_AB,
- M_DLI,
- M_DMUL,
- M_DMUL_I,
- M_DMULO,
- M_DMULO_I,
- M_DMULOU,
- M_DMULOU_I,
- M_DREM_3,
- M_DREM_3I,
- M_DREMU_3,
- M_DREMU_3I,
- M_DSUB_I,
- M_DSUBU_I,
- M_DSUBU_I_2,
- M_J_A,
- M_JAL_1,
- M_JAL_2,
- M_JAL_A,
- M_L_DOB,
- M_L_DAB,
- M_LA_AB,
- M_LB_A,
- M_LB_AB,
- M_LBU_A,
- M_LBU_AB,
- M_LCA_AB,
- M_LD_A,
- M_LD_OB,
- M_LD_AB,
- M_LDC1_AB,
- M_LDC2_AB,
- M_LDC3_AB,
- M_LDL_AB,
- M_LDR_AB,
- M_LH_A,
- M_LH_AB,
- M_LHU_A,
- M_LHU_AB,
- M_LI,
- M_LI_D,
- M_LI_DD,
- M_LI_S,
- M_LI_SS,
- M_LL_AB,
- M_LLD_AB,
- M_LS_A,
- M_LW_A,
- M_LW_AB,
- M_LWC0_A,
- M_LWC0_AB,
- M_LWC1_A,
- M_LWC1_AB,
- M_LWC2_A,
- M_LWC2_AB,
- M_LWC3_A,
- M_LWC3_AB,
- M_LWL_A,
- M_LWL_AB,
- M_LWR_A,
- M_LWR_AB,
- M_LWU_AB,
- M_MSGSND,
- M_MSGLD,
- M_MSGLD_T,
- M_MSGWAIT,
- M_MSGWAIT_T,
- M_MOVE,
- M_MUL,
- M_MUL_I,
- M_MULO,
- M_MULO_I,
- M_MULOU,
- M_MULOU_I,
- M_NOR_I,
- M_OR_I,
- M_REM_3,
- M_REM_3I,
- M_REMU_3,
- M_REMU_3I,
- M_DROL,
- M_ROL,
- M_DROL_I,
- M_ROL_I,
- M_DROR,
- M_ROR,
- M_DROR_I,
- M_ROR_I,
- M_S_DA,
- M_S_DOB,
- M_S_DAB,
- M_S_S,
- M_SC_AB,
- M_SCD_AB,
- M_SD_A,
- M_SD_OB,
- M_SD_AB,
- M_SDC1_AB,
- M_SDC2_AB,
- M_SDC3_AB,
- M_SDL_AB,
- M_SDR_AB,
- M_SEQ,
- M_SEQ_I,
- M_SGE,
- M_SGE_I,
- M_SGEU,
- M_SGEU_I,
- M_SGT,
- M_SGT_I,
- M_SGTU,
- M_SGTU_I,
- M_SLE,
- M_SLE_I,
- M_SLEU,
- M_SLEU_I,
- M_SLT_I,
- M_SLTU_I,
- M_SNE,
- M_SNE_I,
- M_SB_A,
- M_SB_AB,
- M_SH_A,
- M_SH_AB,
- M_SW_A,
- M_SW_AB,
- M_SWC0_A,
- M_SWC0_AB,
- M_SWC1_A,
- M_SWC1_AB,
- M_SWC2_A,
- M_SWC2_AB,
- M_SWC3_A,
- M_SWC3_AB,
- M_SWL_A,
- M_SWL_AB,
- M_SWR_A,
- M_SWR_AB,
- M_SUB_I,
- M_SUBU_I,
- M_SUBU_I_2,
- M_TEQ_I,
- M_TGE_I,
- M_TGEU_I,
- M_TLT_I,
- M_TLTU_I,
- M_TNE_I,
- M_TRUNCWD,
- M_TRUNCWS,
- M_ULD,
- M_ULD_A,
- M_ULH,
- M_ULH_A,
- M_ULHU,
- M_ULHU_A,
- M_ULW,
- M_ULW_A,
- M_USH,
- M_USH_A,
- M_USW,
- M_USW_A,
- M_USD,
- M_USD_A,
- M_XOR_I,
- M_COP0,
- M_COP1,
- M_COP2,
- M_COP3,
- M_NUM_MACROS
-};
-
-
-/* The order of overloaded instructions matters. Label arguments and
- register arguments look the same. Instructions that can have either
- for arguments must apear in the correct order in this table for the
- assembler to pick the right one. In other words, entries with
- immediate operands must apear after the same instruction with
- registers.
-
- Many instructions are short hand for other instructions (i.e., The
- jal instruction is short for jalr ). */
-
-extern const struct mips_opcode mips_builtin_opcodes[];
-extern const int bfd_mips_num_builtin_opcodes;
-extern struct mips_opcode *mips_opcodes;
-extern int bfd_mips_num_opcodes;
-#define NUMOPCODES bfd_mips_num_opcodes
-
-
-/* The rest of this file adds definitions for the mips16 TinyRISC
- processor. */
-
-/* These are the bitmasks and shift counts used for the different
- fields in the instruction formats. Other than OP, no masks are
- provided for the fixed portions of an instruction, since they are
- not needed.
-
- The I format uses IMM11.
-
- The RI format uses RX and IMM8.
-
- The RR format uses RX, and RY.
-
- The RRI format uses RX, RY, and IMM5.
-
- The RRR format uses RX, RY, and RZ.
-
- The RRI_A format uses RX, RY, and IMM4.
-
- The SHIFT format uses RX, RY, and SHAMT.
-
- The I8 format uses IMM8.
-
- The I8_MOVR32 format uses RY and REGR32.
-
- The IR_MOV32R format uses REG32R and MOV32Z.
-
- The I64 format uses IMM8.
-
- The RI64 format uses RY and IMM5.
- */
-
-#define MIPS16OP_MASK_OP 0x1f
-#define MIPS16OP_SH_OP 11
-#define MIPS16OP_MASK_IMM11 0x7ff
-#define MIPS16OP_SH_IMM11 0
-#define MIPS16OP_MASK_RX 0x7
-#define MIPS16OP_SH_RX 8
-#define MIPS16OP_MASK_IMM8 0xff
-#define MIPS16OP_SH_IMM8 0
-#define MIPS16OP_MASK_RY 0x7
-#define MIPS16OP_SH_RY 5
-#define MIPS16OP_MASK_IMM5 0x1f
-#define MIPS16OP_SH_IMM5 0
-#define MIPS16OP_MASK_RZ 0x7
-#define MIPS16OP_SH_RZ 2
-#define MIPS16OP_MASK_IMM4 0xf
-#define MIPS16OP_SH_IMM4 0
-#define MIPS16OP_MASK_REGR32 0x1f
-#define MIPS16OP_SH_REGR32 0
-#define MIPS16OP_MASK_REG32R 0x1f
-#define MIPS16OP_SH_REG32R 3
-#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
-#define MIPS16OP_MASK_MOVE32Z 0x7
-#define MIPS16OP_SH_MOVE32Z 0
-#define MIPS16OP_MASK_IMM6 0x3f
-#define MIPS16OP_SH_IMM6 5
-
-/* These are the characters which may appears in the args field of a MIPS16
- instruction. They appear in the order in which the fields appear when the
- instruction is used. Commas and parentheses in the args string are ignored
- when assembling, and written into the output when disassembling.
-
- "y" 3 bit register (MIPS16OP_*_RY)
- "x" 3 bit register (MIPS16OP_*_RX)
- "z" 3 bit register (MIPS16OP_*_RZ)
- "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
- "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
- "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
- "0" zero register ($0)
- "S" stack pointer ($sp or $29)
- "P" program counter
- "R" return address register ($ra or $31)
- "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
- "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
- "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
- "a" 26 bit jump address
- "e" 11 bit extension value
- "l" register list for entry instruction
- "L" register list for exit instruction
-
- The remaining codes may be extended. Except as otherwise noted,
- the full extended operand is a 16 bit signed value.
- "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
- ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
- "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
- "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
- "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
- "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
- "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
- "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
- "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
- "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
- "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
- "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
- "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
- "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
- "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
- "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
- "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
- "q" 11 bit branch address (MIPS16OP_*_IMM11)
- "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
- "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
- "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
- "m" 7 bit register list for save instruction (18 bit extended)
- "M" 7 bit register list for restore instruction (18 bit extended)
- */
-
-/* Save/restore encoding for the args field when all 4 registers are
- either saved as arguments or saved/restored as statics. */
-#define MIPS16_ALL_ARGS 0xe
-#define MIPS16_ALL_STATICS 0xb
-
-/* For the mips16, we use the same opcode table format and a few of
- the same flags. However, most of the flags are different. */
-
-/* Modifies the register in MIPS16OP_*_RX. */
-#define MIPS16_INSN_WRITE_X 0x00000001
-/* Modifies the register in MIPS16OP_*_RY. */
-#define MIPS16_INSN_WRITE_Y 0x00000002
-/* Modifies the register in MIPS16OP_*_RZ. */
-#define MIPS16_INSN_WRITE_Z 0x00000004
-/* Modifies the T ($24) register. */
-#define MIPS16_INSN_WRITE_T 0x00000008
-/* Modifies the SP ($29) register. */
-#define MIPS16_INSN_WRITE_SP 0x00000010
-/* Modifies the RA ($31) register. */
-#define MIPS16_INSN_WRITE_31 0x00000020
-/* Modifies the general purpose register in MIPS16OP_*_REG32R. */
-#define MIPS16_INSN_WRITE_GPR_Y 0x00000040
-/* Reads the register in MIPS16OP_*_RX. */
-#define MIPS16_INSN_READ_X 0x00000080
-/* Reads the register in MIPS16OP_*_RY. */
-#define MIPS16_INSN_READ_Y 0x00000100
-/* Reads the register in MIPS16OP_*_MOVE32Z. */
-#define MIPS16_INSN_READ_Z 0x00000200
-/* Reads the T ($24) register. */
-#define MIPS16_INSN_READ_T 0x00000400
-/* Reads the SP ($29) register. */
-#define MIPS16_INSN_READ_SP 0x00000800
-/* Reads the RA ($31) register. */
-#define MIPS16_INSN_READ_31 0x00001000
-/* Reads the program counter. */
-#define MIPS16_INSN_READ_PC 0x00002000
-/* Reads the general purpose register in MIPS16OP_*_REGR32. */
-#define MIPS16_INSN_READ_GPR_X 0x00004000
-/* Is a branch insn. */
-#define MIPS16_INSN_BRANCH 0x00010000
-
-/* The following flags have the same value for the mips16 opcode
- table:
- INSN_UNCOND_BRANCH_DELAY
- INSN_COND_BRANCH_DELAY
- INSN_COND_BRANCH_LIKELY (never used)
- INSN_READ_HI
- INSN_READ_LO
- INSN_WRITE_HI
- INSN_WRITE_LO
- INSN_TRAP
- INSN_ISA3
- */
-
-extern const struct mips_opcode mips16_opcodes[];
-extern const int bfd_mips16_num_opcodes;
-
-#endif /* _MIPS_H_ */
mips.h
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: tic30.h
===================================================================
--- tic30.h (revision 816)
+++ tic30.h (nonexistent)
@@ -1,691 +0,0 @@
-/* tic30.h -- Header file for TI TMS320C30 opcode table
- Copyright 1998, 2005, 2009 Free Software Foundation, Inc.
- Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
-
-This file is part of GDB, GAS, and the GNU binutils.
-
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
-
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
-02110-1301, USA. */
-
-/* FIXME: The opcode table should be in opcodes/tic30-opc.c, not in a
- header file. */
-
-#ifndef _TMS320_H_
-#define _TMS320_H_
-
-struct _register
-{
- char *name;
- unsigned char opcode;
- unsigned char regtype;
-};
-
-typedef struct _register reg;
-
-#define REG_Rn 0x01
-#define REG_ARn 0x02
-#define REG_DP 0x03
-#define REG_OTHER 0x04
-
-static const reg tic30_regtab[] = {
- { "r0", 0x00, REG_Rn },
- { "r1", 0x01, REG_Rn },
- { "r2", 0x02, REG_Rn },
- { "r3", 0x03, REG_Rn },
- { "r4", 0x04, REG_Rn },
- { "r5", 0x05, REG_Rn },
- { "r6", 0x06, REG_Rn },
- { "r7", 0x07, REG_Rn },
- { "ar0",0x08, REG_ARn },
- { "ar1",0x09, REG_ARn },
- { "ar2",0x0A, REG_ARn },
- { "ar3",0x0B, REG_ARn },
- { "ar4",0x0C, REG_ARn },
- { "ar5",0x0D, REG_ARn },
- { "ar6",0x0E, REG_ARn },
- { "ar7",0x0F, REG_ARn },
- { "dp", 0x10, REG_DP },
- { "ir0",0x11, REG_OTHER },
- { "ir1",0x12, REG_OTHER },
- { "bk", 0x13, REG_OTHER },
- { "sp", 0x14, REG_OTHER },
- { "st", 0x15, REG_OTHER },
- { "ie", 0x16, REG_OTHER },
- { "if", 0x17, REG_OTHER },
- { "iof",0x18, REG_OTHER },
- { "rs", 0x19, REG_OTHER },
- { "re", 0x1A, REG_OTHER },
- { "rc", 0x1B, REG_OTHER },
- { "R0", 0x00, REG_Rn },
- { "R1", 0x01, REG_Rn },
- { "R2", 0x02, REG_Rn },
- { "R3", 0x03, REG_Rn },
- { "R4", 0x04, REG_Rn },
- { "R5", 0x05, REG_Rn },
- { "R6", 0x06, REG_Rn },
- { "R7", 0x07, REG_Rn },
- { "AR0",0x08, REG_ARn },
- { "AR1",0x09, REG_ARn },
- { "AR2",0x0A, REG_ARn },
- { "AR3",0x0B, REG_ARn },
- { "AR4",0x0C, REG_ARn },
- { "AR5",0x0D, REG_ARn },
- { "AR6",0x0E, REG_ARn },
- { "AR7",0x0F, REG_ARn },
- { "DP", 0x10, REG_DP },
- { "IR0",0x11, REG_OTHER },
- { "IR1",0x12, REG_OTHER },
- { "BK", 0x13, REG_OTHER },
- { "SP", 0x14, REG_OTHER },
- { "ST", 0x15, REG_OTHER },
- { "IE", 0x16, REG_OTHER },
- { "IF", 0x17, REG_OTHER },
- { "IOF",0x18, REG_OTHER },
- { "RS", 0x19, REG_OTHER },
- { "RE", 0x1A, REG_OTHER },
- { "RC", 0x1B, REG_OTHER },
- { "", 0, 0 }
-};
-
-static const reg *const tic30_regtab_end
- = tic30_regtab + sizeof(tic30_regtab)/sizeof(tic30_regtab[0]);
-
-/* Indirect Addressing Modes Modification Fields */
-/* Indirect Addressing with Displacement */
-#define PreDisp_Add 0x00
-#define PreDisp_Sub 0x01
-#define PreDisp_Add_Mod 0x02
-#define PreDisp_Sub_Mod 0x03
-#define PostDisp_Add_Mod 0x04
-#define PostDisp_Sub_Mod 0x05
-#define PostDisp_Add_Circ 0x06
-#define PostDisp_Sub_Circ 0x07
-/* Indirect Addressing with Index Register IR0 */
-#define PreIR0_Add 0x08
-#define PreIR0_Sub 0x09
-#define PreIR0_Add_Mod 0x0A
-#define PreIR0_Sub_Mod 0x0B
-#define PostIR0_Add_Mod 0x0C
-#define PostIR0_Sub_Mod 0x0D
-#define PostIR0_Add_Circ 0x0E
-#define PostIR0_Sub_Circ 0x0F
-/* Indirect Addressing with Index Register IR1 */
-#define PreIR1_Add 0x10
-#define PreIR1_Sub 0x11
-#define PreIR1_Add_Mod 0x12
-#define PreIR1_Sub_Mod 0x13
-#define PostIR1_Add_Mod 0x14
-#define PostIR1_Sub_Mod 0x15
-#define PostIR1_Add_Circ 0x16
-#define PostIR1_Sub_Circ 0x17
-/* Indirect Addressing (Special Cases) */
-#define IndirectOnly 0x18
-#define PostIR0_Add_BitRev 0x19
-
-typedef struct {
- char *syntax;
- unsigned char modfield;
- unsigned char displacement;
-} ind_addr_type;
-
-#define IMPLIED_DISP 0x01
-#define DISP_REQUIRED 0x02
-#define NO_DISP 0x03
-
-static const ind_addr_type tic30_indaddr_tab[] = {
- { "*+ar", PreDisp_Add, IMPLIED_DISP },
- { "*-ar", PreDisp_Sub, IMPLIED_DISP },
- { "*++ar", PreDisp_Add_Mod, IMPLIED_DISP },
- { "*--ar", PreDisp_Sub_Mod, IMPLIED_DISP },
- { "*ar++", PostDisp_Add_Mod, IMPLIED_DISP },
- { "*ar--", PostDisp_Sub_Mod, IMPLIED_DISP },
- { "*ar++%", PostDisp_Add_Circ, IMPLIED_DISP },
- { "*ar--%", PostDisp_Sub_Circ, IMPLIED_DISP },
- { "*+ar()", PreDisp_Add, DISP_REQUIRED },
- { "*-ar()", PreDisp_Sub, DISP_REQUIRED },
- { "*++ar()", PreDisp_Add_Mod, DISP_REQUIRED },
- { "*--ar()", PreDisp_Sub_Mod, DISP_REQUIRED },
- { "*ar++()", PostDisp_Add_Mod, DISP_REQUIRED },
- { "*ar--()", PostDisp_Sub_Mod, DISP_REQUIRED },
- { "*ar++()%", PostDisp_Add_Circ, DISP_REQUIRED },
- { "*ar--()%", PostDisp_Sub_Circ, DISP_REQUIRED },
- { "*+ar(ir0)", PreIR0_Add, NO_DISP },
- { "*-ar(ir0)", PreIR0_Sub, NO_DISP },
- { "*++ar(ir0)", PreIR0_Add_Mod, NO_DISP },
- { "*--ar(ir0)", PreIR0_Sub_Mod, NO_DISP },
- { "*ar++(ir0)", PostIR0_Add_Mod, NO_DISP },
- { "*ar--(ir0)", PostIR0_Sub_Mod, NO_DISP },
- { "*ar++(ir0)%",PostIR0_Add_Circ, NO_DISP },
- { "*ar--(ir0)%",PostIR0_Sub_Circ, NO_DISP },
- { "*+ar(ir1)", PreIR1_Add, NO_DISP },
- { "*-ar(ir1)", PreIR1_Sub, NO_DISP },
- { "*++ar(ir1)", PreIR1_Add_Mod, NO_DISP },
- { "*--ar(ir1)", PreIR1_Sub_Mod, NO_DISP },
- { "*ar++(ir1)", PostIR1_Add_Mod, NO_DISP },
- { "*ar--(ir1)", PostIR1_Sub_Mod, NO_DISP },
- { "*ar++(ir1)%",PostIR1_Add_Circ, NO_DISP },
- { "*ar--(ir1)%",PostIR1_Sub_Circ, NO_DISP },
- { "*ar", IndirectOnly, NO_DISP },
- { "*ar++(ir0)b",PostIR0_Add_BitRev, NO_DISP },
- { "", 0,0 }
-};
-
-static const ind_addr_type *const tic30_indaddrtab_end
- = tic30_indaddr_tab + sizeof(tic30_indaddr_tab)/sizeof(tic30_indaddr_tab[0]);
-
-/* Possible operand types */
-/* Register types */
-#define Rn 0x0001
-#define ARn 0x0002
-#define DPReg 0x0004
-#define OtherReg 0x0008
-/* Addressing mode types */
-#define Direct 0x0010
-#define Indirect 0x0020
-#define Imm16 0x0040
-#define Disp 0x0080
-#define Imm24 0x0100
-#define Abs24 0x0200
-/* 3 operand addressing mode types */
-#define op3T1 0x0400
-#define op3T2 0x0800
-/* Interrupt vector */
-#define IVector 0x1000
-/* Not required */
-#define NotReq 0x2000
-
-#define GAddr1 Rn | Direct | Indirect | Imm16
-#define GAddr2 GAddr1 | AllReg
-#define TAddr1 op3T1 | Rn | Indirect
-#define TAddr2 op3T2 | Rn | Indirect
-#define Reg Rn | ARn
-#define AllReg Reg | DPReg | OtherReg
-
-typedef struct _template
-{
- char *name;
- unsigned int operands; /* how many operands */
- unsigned int base_opcode; /* base_opcode is the fundamental opcode byte */
- /* the bits in opcode_modifier are used to generate the final opcode from
- the base_opcode. These bits also are used to detect alternate forms of
- the same instruction */
- unsigned int opcode_modifier;
-
- /* opcode_modifier bits: */
-#define AddressMode 0x00600000
-#define PCRel 0x02000000
-#define StackOp 0x001F0000
-#define Rotate StackOp
-
- /* operand_types[i] describes the type of operand i. This is made
- by OR'ing together all of the possible type masks. (e.g.
- 'operand_types[i] = Reg|Imm' specifies that operand i can be
- either a register or an immediate operand */
- unsigned int operand_types[3];
- /* This defines the number type of an immediate argument to an instruction. */
- int imm_arg_type;
-#define Imm_None 0
-#define Imm_Float 1
-#define Imm_SInt 2
-#define Imm_UInt 3
-}
-insn_template;
-
-static const insn_template tic30_optab[] = {
- { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "absi" ,2,0x00800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "addc" ,2,0x01000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "addc3" ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
- { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
- { "addi" ,2,0x02000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "addi3" ,3,0x21000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
- { "and" ,2,0x02800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
- { "and3" ,3,0x21800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
- { "andn" ,2,0x03000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
- { "andn3" ,3,0x22000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
- { "ash" ,2,0x03800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ash3" ,3,0x22800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
- { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "ble" ,1,0x68080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bgt" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bge" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bz" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bnz" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bp" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bn" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bnn" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bnv" ,1,0x680C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bv" ,1,0x680D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bnuf" ,1,0x680E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "buf" ,1,0x680F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bnc" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bc" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bnlv" ,1,0x68100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "blv" ,1,0x68110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bnluf" ,1,0x68120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bluf" ,1,0x68130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bzuf" ,1,0x68140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bd" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bud" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "blod" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "blsd" ,1,0x68220000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bhid" ,1,0x68230000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bhsd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "beqd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bned" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bltd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bled" ,1,0x68280000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bgtd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bged" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bzd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bnzd" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bpd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bnd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bnnd" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bnvd" ,1,0x682C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bvd" ,1,0x682D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bnufd" ,1,0x682E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bufd" ,1,0x682F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bncd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bcd" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bnlvd" ,1,0x68300000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "blvd" ,1,0x68310000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bnlufd" ,1,0x68320000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "blufd" ,1,0x68330000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "bzufd" ,1,0x68340000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
- { "br" ,1,0x60000000,0, { Imm24, 0, 0 }, Imm_UInt },
- { "brd" ,1,0x61000000,0, { Imm24, 0, 0 }, Imm_UInt },
- { "call" ,1,0x62000000,0, { Imm24, 0, 0 }, Imm_UInt },
- { "callu" ,1,0x70000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "calllo" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callls" ,1,0x70020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callhi" ,1,0x70030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callhs" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "calleq" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callne" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "calllt" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callle" ,1,0x70080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callgt" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callge" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callz" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callnz" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callp" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "calln" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callnn" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callnv" ,1,0x700C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callv" ,1,0x700D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callnuf",1,0x700E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "calluf" ,1,0x700F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callnc" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callc" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callnlv",1,0x70100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "calllv" ,1,0x70110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callnluf",1,0x70120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callluf",1,0x70130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "callzuf",1,0x70140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
- { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "cmpf3" ,2,0x23000000,AddressMode, { TAddr1, TAddr2, 0 }, Imm_None },
- { "cmpi" ,2,0x04800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "cmpi3" ,2,0x23800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None },
- { "db" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbu" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dblo" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbls" ,2,0x6C020000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbhi" ,2,0x6C030000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbhs" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbeq" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbne" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dblt" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dble" ,2,0x6C080000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbgt" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbge" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbz" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbnz" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbp" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbn" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbnn" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbnv" ,2,0x6C0C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbv" ,2,0x6C0D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbnuf" ,2,0x6C0E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbuf" ,2,0x6C0F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbnc" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbc" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbnlv" ,2,0x6C100000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dblv" ,2,0x6C110000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbnluf" ,2,0x6C120000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbluf" ,2,0x6C130000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbzuf" ,2,0x6C140000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbd" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbud" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dblod" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dblsd" ,2,0x6C220000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbhid" ,2,0x6C230000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbhsd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbeqd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbned" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbltd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbled" ,2,0x6C280000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbgtd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbged" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbzd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbnzd" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbpd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbnd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbnnd" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbnvd" ,2,0x6C2C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbvd" ,2,0x6C2D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbnufd" ,2,0x6C2E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbufd" ,2,0x6C2F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbncd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbcd" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbnlvd" ,2,0x6C300000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dblvd" ,2,0x6C310000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbnlufd",2,0x6C320000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dblufd" ,2,0x6C330000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "dbzufd" ,2,0x6C340000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
- { "fix" ,2,0x05000000,AddressMode, { GAddr1, AllReg, 0 }, Imm_Float },
- { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt },
- { "iack" ,1,0x1B000000,AddressMode, { Direct|Indirect, 0, 0 }, Imm_None },
- { "idle" ,0,0x06000000,0, { 0, 0, 0 }, Imm_None },
- { "idle2" ,0,0x06000001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */
- { "lde" ,2,0x06800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldf" ,2,0x07000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfu" ,2,0x40000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldflo" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfls" ,2,0x41000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfhi" ,2,0x41800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfhs" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfeq" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfne" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldflt" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfle" ,2,0x44000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfgt" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfge" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfz" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfnz" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfp" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfn" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfnn" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfnv" ,2,0x46000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfv" ,2,0x46800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfnuf" ,2,0x47000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfuf" ,2,0x47800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfnc" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfc" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfnlv" ,2,0x48000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldflv" ,2,0x48800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfnluf",2,0x49000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfluf" ,2,0x49800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfzuf" ,2,0x4A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldfi" ,2,0x07800000,AddressMode, { Direct|Indirect, Rn, 0 }, Imm_None },
- { "ldi" ,2,0x08000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldiu" ,2,0x50000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldilo" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldils" ,2,0x51000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldihi" ,2,0x51800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldihs" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldieq" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldine" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldilt" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldile" ,2,0x54000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldigt" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldige" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldiz" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldinz" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldip" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldin" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldinn" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldinv" ,2,0x56000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldiv" ,2,0x56800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldinuf" ,2,0x57000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldiuf" ,2,0x57800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldinc" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldic" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldinlv" ,2,0x58000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldilv" ,2,0x58800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldinluf",2,0x59000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldiluf" ,2,0x59800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldizuf" ,2,0x5A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "ldii" ,2,0x08800000,AddressMode, { Direct|Indirect, AllReg, 0 }, Imm_None },
- { "ldm" ,2,0x09000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "ldp" ,2,0x08700000,0, { Abs24|Direct, DPReg|NotReq, 0 }, Imm_UInt },
- { "lopower",0,0x10800001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */
- { "lsh" ,2,0x09800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
- { "lsh3" ,3,0x24000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
- { "maxspeed",0,0x10800000,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */
- { "mpyf" ,2,0x0A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "mpyf3" ,3,0x24800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
- { "mpyi" ,2,0x0A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "mpyi3" ,3,0x25000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
- { "negb" ,2,0x0B000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "negf" ,2,0x0B800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "negi" ,2,0x0C000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "nop" ,1,0x0C800000,AddressMode, { AllReg|Indirect|NotReq, 0, 0 }, Imm_None },
- { "norm" ,2,0x0D000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, /*Check another source*/
- { "not" ,2,0x0D800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
- { "or" ,2,0x10000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
- { "or3" ,3,0x25800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
- { "pop" ,1,0x0E200000,StackOp, { AllReg, 0, 0 }, Imm_None },
- { "popf" ,1,0x0EA00000,StackOp, { Rn, 0, 0 }, Imm_None },
- { "push" ,1,0x0F200000,StackOp, { AllReg, 0, 0 }, Imm_None },
- { "pushf" ,1,0x0FA00000,StackOp, { Rn, 0, 0 }, Imm_None },
- { "reti" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None },
- { "retiu" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None },
- { "retilo" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None },
- { "retils" ,0,0x78020000,0, { 0, 0, 0 }, Imm_None },
- { "retihi" ,0,0x78030000,0, { 0, 0, 0 }, Imm_None },
- { "retihs" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None },
- { "retieq" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None },
- { "retine" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None },
- { "retilt" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None },
- { "retile" ,0,0x78080000,0, { 0, 0, 0 }, Imm_None },
- { "retigt" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None },
- { "retige" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None },
- { "retiz" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None },
- { "retinz" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None },
- { "retip" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None },
- { "retin" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None },
- { "retinn" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None },
- { "retinv" ,0,0x780C0000,0, { 0, 0, 0 }, Imm_None },
- { "retiv" ,0,0x780D0000,0, { 0, 0, 0 }, Imm_None },
- { "retinuf",0,0x780E0000,0, { 0, 0, 0 }, Imm_None },
- { "retiuf" ,0,0x780F0000,0, { 0, 0, 0 }, Imm_None },
- { "retinc" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None },
- { "retic" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None },
- { "retinlv",0,0x78100000,0, { 0, 0, 0 }, Imm_None },
- { "retilv" ,0,0x78110000,0, { 0, 0, 0 }, Imm_None },
- { "retinluf",0,0x78120000,0, { 0, 0, 0 }, Imm_None },
- { "retiluf",0,0x78130000,0, { 0, 0, 0 }, Imm_None },
- { "retizuf",0,0x78140000,0, { 0, 0, 0 }, Imm_None },
- { "rets" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None },
- { "retsu" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None },
- { "retslo" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None },
- { "retsls" ,0,0x78820000,0, { 0, 0, 0 }, Imm_None },
- { "retshi" ,0,0x78830000,0, { 0, 0, 0 }, Imm_None },
- { "retshs" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None },
- { "retseq" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None },
- { "retsne" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None },
- { "retslt" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None },
- { "retsle" ,0,0x78880000,0, { 0, 0, 0 }, Imm_None },
- { "retsgt" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None },
- { "retsge" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None },
- { "retsz" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None },
- { "retsnz" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None },
- { "retsp" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None },
- { "retsn" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None },
- { "retsnn" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None },
- { "retsnv" ,0,0x788C0000,0, { 0, 0, 0 }, Imm_None },
- { "retsv" ,0,0x788D0000,0, { 0, 0, 0 }, Imm_None },
- { "retsnuf",0,0x788E0000,0, { 0, 0, 0 }, Imm_None },
- { "retsuf" ,0,0x788F0000,0, { 0, 0, 0 }, Imm_None },
- { "retsnc" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None },
- { "retsc" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None },
- { "retsnlv",0,0x78900000,0, { 0, 0, 0 }, Imm_None },
- { "retslv" ,0,0x78910000,0, { 0, 0, 0 }, Imm_None },
- { "retsnluf",0,0x78920000,0, { 0, 0, 0 }, Imm_None },
- { "retsluf",0,0x78930000,0, { 0, 0, 0 }, Imm_None },
- { "retszuf",0,0x78940000,0, { 0, 0, 0 }, Imm_None },
- { "rnd" ,2,0x11000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "rol" ,1,0x11E00001,Rotate, { AllReg, 0, 0 }, Imm_None },
- { "rolc" ,1,0x12600001,Rotate, { AllReg, 0, 0 }, Imm_None },
- { "ror" ,1,0x12E0FFFF,Rotate, { AllReg, 0, 0 }, Imm_None },
- { "rorc" ,1,0x1360FFFF,Rotate, { AllReg, 0, 0 }, Imm_None },
- { "rptb" ,1,0x64000000,0, { Imm24, 0, 0 }, Imm_UInt },
- { "rpts" ,1,0x139B0000,AddressMode, { GAddr2, 0, 0 }, Imm_UInt },
- { "sigi" ,0,0x16000000,0, { 0, 0, 0 }, Imm_None },
- { "stf" ,2,0x14000000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float },
- { "stfi" ,2,0x14800000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float },
- { "sti" ,2,0x15000000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt },
- { "stii" ,2,0x15800000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt },
- { "subb" ,2,0x16800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "subb3" ,3,0x26000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
- { "subc" ,2,0x17000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
- { "subf" ,2,0x17800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "subf3" ,3,0x26800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
- { "subi" ,2,0x18000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "subi3" ,3,0x27000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
- { "subrb" ,2,0x18800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "subrf" ,2,0x19000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
- { "subri" ,2,0x19800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
- { "swi" ,0,0x66000000,0, { 0, 0, 0 }, Imm_None },
- { "trap" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None },
- { "trapu" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None },
- { "traplo" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None },
- { "trapls" ,1,0x74820020,0, { IVector, 0, 0 }, Imm_None },
- { "traphi" ,1,0x74830020,0, { IVector, 0, 0 }, Imm_None },
- { "traphs" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None },
- { "trapeq" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None },
- { "trapne" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None },
- { "traplt" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None },
- { "traple" ,1,0x74880020,0, { IVector, 0, 0 }, Imm_None },
- { "trapgt" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None },
- { "trapge" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None },
- { "trapz" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None },
- { "trapnz" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None },
- { "trapp" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None },
- { "trapn" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None },
- { "trapnn" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None },
- { "trapnv" ,1,0x748C0020,0, { IVector, 0, 0 }, Imm_None },
- { "trapv" ,1,0x748D0020,0, { IVector, 0, 0 }, Imm_None },
- { "trapnuf",1,0x748E0020,0, { IVector, 0, 0 }, Imm_None },
- { "trapuf" ,1,0x748F0020,0, { IVector, 0, 0 }, Imm_None },
- { "trapnc" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None },
- { "trapc" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None },
- { "trapnlv",1,0x74900020,0, { IVector, 0, 0 }, Imm_None },
- { "traplv" ,1,0x74910020,0, { IVector, 0, 0 }, Imm_None },
- { "trapnluf",1,0x74920020,0, { IVector, 0, 0 }, Imm_None },
- { "trapluf",1,0x74930020,0, { IVector, 0, 0 }, Imm_None },
- { "trapzuf",1,0x74940020,0, { IVector, 0, 0 }, Imm_None },
- { "tstb" ,2,0x1A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
- { "tstb3" ,2,0x27800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None },
- { "xor" ,2,0x1A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
- { "xor3" ,3,0x28000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
- { "" ,0,0x00000000,0, { 0, 0, 0 }, 0 }
-};
-
-static const insn_template *const tic30_optab_end =
- tic30_optab + sizeof(tic30_optab)/sizeof(tic30_optab[0]);
-
-typedef struct {
- char *name;
- unsigned int operands_1;
- unsigned int operands_2;
- unsigned int base_opcode;
- unsigned int operand_types[2][3];
- /* Which operand fits into which part of the final opcode word. */
- int oporder;
-} partemplate;
-
-/* oporder defines - not very descriptive. */
-#define OO_4op1 0
-#define OO_4op2 1
-#define OO_4op3 2
-#define OO_5op1 3
-#define OO_5op2 4
-#define OO_PField 5
-
-static const partemplate tic30_paroptab[] = {
- { "q_absf_stf", 2,2,0xC8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
- OO_4op1 },
- { "q_absi_sti", 2,2,0xCA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
- OO_4op1 },
- { "q_addf3_stf", 3,2,0xCC000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
- OO_5op1 },
- { "q_addi3_sti", 3,2,0xCE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
- OO_5op1 },
- { "q_and3_sti", 3,2,0xD0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
- OO_5op1 },
- { "q_ash3_sti", 3,2,0xD2000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
- OO_5op2 },
- { "q_fix_sti", 2,2,0xD4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
- OO_4op1 },
- { "q_float_stf", 2,2,0xD6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
- OO_4op1 },
- { "q_ldf_ldf", 2,2,0xC4000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } },
- OO_4op2 },
- { "q_ldf_stf", 2,2,0xD8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
- OO_4op1 },
- { "q_ldi_ldi", 2,2,0xC6000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } },
- OO_4op2 },
- { "q_ldi_sti", 2,2,0xDA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
- OO_4op1 },
- { "q_lsh3_sti", 3,2,0xDC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
- OO_5op2 },
- { "q_mpyf3_addf3",3,3,0x80000000, { { Rn | Indirect, Rn | Indirect, Rn },
- { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
- { "q_mpyf3_stf", 3,2,0xDE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
- OO_5op1 },
- { "q_mpyf3_subf3",3,3,0x84000000, { { Rn | Indirect, Rn | Indirect, Rn },
- { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
- { "q_mpyi3_addi3",3,3,0x88000000, { { Rn | Indirect, Rn | Indirect, Rn },
- { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
- { "q_mpyi3_sti", 3,2,0xE0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
- OO_5op1 },
- { "q_mpyi3_subi3",3,3,0x8C000000, { { Rn | Indirect, Rn | Indirect, Rn },
- { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
- { "q_negf_stf", 2,2,0xE2000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
- OO_4op1 },
- { "q_negi_sti", 2,2,0xE4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
- OO_4op1 },
- { "q_not_sti", 2,2,0xE6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
- OO_4op1 },
- { "q_or3_sti", 3,2,0xE8000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
- OO_5op1 },
- { "q_stf_stf", 2,2,0xC0000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } },
- OO_4op3 },
- { "q_sti_sti", 2,2,0xC2000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } },
- OO_4op3 },
- { "q_subf3_stf", 3,2,0xEA000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
- OO_5op2 },
- { "q_subi3_sti", 3,2,0xEC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
- OO_5op2 },
- { "q_xor3_sti", 3,2,0xEE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
- OO_5op1 },
- { "", 0,0,0x00000000, { { 0, 0, 0 }, { 0, 0, 0 } }, 0 }
-};
-
-static const partemplate *const tic30_paroptab_end =
- tic30_paroptab + sizeof(tic30_paroptab)/sizeof(tic30_paroptab[0]);
-
-#endif
tic30.h
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: score-inst.h
===================================================================
--- score-inst.h (revision 816)
+++ score-inst.h (nonexistent)
@@ -1,236 +0,0 @@
-/* score-inst.h -- Score Instructions Table
- Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
- Contributed by:
- Brain.lin (brain.lin@sunplusct.com)
- Mei Ligang (ligang@sunnorth.com.cn)
- Pei-Lin Tsai (pltsai@sunplus.com)
-
- This file is part of GAS, the GNU Assembler.
-
- GAS is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- GAS is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GAS; see the file COPYING. If not, write to the Free
- Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
- 02110-1301, USA. */
-
-#ifndef SCORE_INST_H
-#define SCORE_INST_H
-
-#define LDST_UNALIGN_MASK 0x0000007f
-#define UA_LCB 0x00000060
-#define UA_LCW 0x00000062
-#define UA_LCE 0x00000066
-#define UA_SCB 0x00000068
-#define UA_SCW 0x0000006a
-#define UA_SCE 0x0000006e
-#define UA_LL 0x0000000c
-#define UA_SC 0x0000000e
-#define LDST16_RR_MASK 0x0000000f
-#define N16_LW 8
-#define N16_LH 9
-#define N16_POP 10
-#define N16_LBU 11
-#define N16_SW 12
-#define N16_SH 13
-#define N16_PUSH 14
-#define N16_SB 15
-#define LDST16_RI_MASK 0x7007
-#define N16_LWP 0x7000
-#define N16_LHP 0x7001
-#define N16_LBUP 0x7003
-#define N16_SWP 0x7004
-#define N16_SHP 0x7005
-#define N16_SBP 0x7007
-#define N16_LIU 0x5000
-
-#define OPC_PSEUDOLDST_MASK 0x00000007
-
-enum
-{
- INSN_LW = 0,
- INSN_LH = 1,
- INSN_LHU = 2,
- INSN_LB = 3,
- INSN_SW = 4,
- INSN_SH = 5,
- INSN_LBU = 6,
- INSN_SB = 7,
-};
-
-/* Sub opcdoe opcode. */
-enum
-{
- INSN16_LBU = 11,
- INSN16_LH = 9,
- INSN16_LW = 8,
- INSN16_SB = 15,
- INSN16_SH = 13,
- INSN16_SW = 12,
-};
-
-enum
-{
- LDST_NOUPDATE = 0,
- LDST_PRE = 1,
- LDST_POST = 2,
-};
-
-enum score_insn_type
-{
- Rd_I4,
- Rd_I5,
- Rd_rvalueBP_I5,
- Rd_lvalueBP_I5,
- Rd_Rs_I5,
- x_Rs_I5,
- x_I5_x,
- Rd_I8,
- Rd_Rs_I14,
- I15,
- Rd_I16,
- Rd_I30,
- Rd_I32,
- Rd_rvalueRs_SI10,
- Rd_lvalueRs_SI10,
- Rd_rvalueRs_preSI12,
- Rd_rvalueRs_postSI12,
- Rd_lvalueRs_preSI12,
- Rd_lvalueRs_postSI12,
- Rd_Rs_SI14,
- Rd_rvalueRs_SI15,
- Rd_lvalueRs_SI15,
- Rd_SI5,
- Rd_SI6,
- Rd_SI16,
- PC_DISP8div2,
- PC_DISP11div2,
- PC_DISP19div2,
- PC_DISP24div2,
- Rd_Rs_Rs,
- x_Rs_x,
- x_Rs_Rs,
- Rd_Rs_x,
- Rd_x_Rs,
- Rd_x_x,
- Rd_Rs,
- Rd_HighRs,
- Rd_lvalueRs,
- Rd_rvalueRs,
- Rd_lvalue32Rs,
- Rd_rvalue32Rs,
- x_Rs,
- NO_OPD,
- NO16_OPD,
- OP5_rvalueRs_SI15,
- I5_Rs_Rs_I5_OP5,
- x_rvalueRs_post4,
- Rd_rvalueRs_post4,
- Rd_x_I5,
- Rd_lvalueRs_post4,
- x_lvalueRs_post4,
- Rd_LowRs,
- Rd_Rs_Rs_imm,
- Insn_Type_PCE,
- Insn_Type_SYN,
- Insn_GP,
- Insn_PIC,
- Insn_internal,
- Insn_BCMP,
- Ra_I9_I5,
-};
-
-enum score_data_type
-{
- _IMM4 = 0,
- _IMM5,
- _IMM8,
- _IMM14,
- _IMM15,
- _IMM16,
- _SIMM10 = 6,
- _SIMM12,
- _SIMM14,
- _SIMM15,
- _SIMM16,
- _SIMM14_NEG = 11,
- _IMM16_NEG,
- _SIMM16_NEG,
- _IMM20,
- _IMM25,
- _DISP8div2 = 16,
- _DISP11div2,
- _DISP19div2,
- _DISP24div2,
- _VALUE,
- _VALUE_HI16,
- _VALUE_LO16,
- _VALUE_LDST_LO16 = 23,
- _SIMM16_LA,
- _IMM5_RSHIFT_1,
- _IMM5_RSHIFT_2,
- _SIMM16_LA_POS,
- _IMM5_RANGE_8_31,
- _IMM10_RSHIFT_2,
- _GP_IMM15 = 30,
- _GP_IMM14 = 31,
- _SIMM16_pic = 42, /* Index in score_df_range. */
- _IMM16_LO16_pic = 43,
- _IMM16_pic = 44,
-
- _SIMM5 = 45,
- _SIMM6 = 46,
- _IMM32 = 47,
- _SIMM32 = 48,
- _IMM11 = 49,
- _IMM5_MULTI_LOAD = 50,
-};
-
-#define REG_TMP 1
-
-#define OP_REG_TYPE (1 << 6)
-#define OP_IMM_TYPE (1 << 7)
-#define OP_SH_REGD (OP_REG_TYPE |20)
-#define OP_SH_REGS1 (OP_REG_TYPE |15)
-#define OP_SH_REGS2 (OP_REG_TYPE |10)
-#define OP_SH_I (OP_IMM_TYPE | 1)
-#define OP_SH_RI15 (OP_IMM_TYPE | 0)
-#define OP_SH_I12 (OP_IMM_TYPE | 3)
-#define OP_SH_DISP24 (OP_IMM_TYPE | 1)
-#define OP_SH_DISP19_p1 (OP_IMM_TYPE |15)
-#define OP_SH_DISP19_p2 (OP_IMM_TYPE | 1)
-#define OP_SH_I5 (OP_IMM_TYPE |10)
-#define OP_SH_I10 (OP_IMM_TYPE | 5)
-#define OP_SH_COPID (OP_IMM_TYPE | 5)
-#define OP_SH_TRAPI5 (OP_IMM_TYPE |15)
-#define OP_SH_I15 (OP_IMM_TYPE |10)
-
-#define OP16_SH_REGD (OP_REG_TYPE | 8)
-#define OP16_SH_REGS1 (OP_REG_TYPE | 4)
-#define OP16_SH_I45 (OP_IMM_TYPE | 3)
-#define OP16_SH_I8 (OP_IMM_TYPE | 0)
-#define OP16_SH_DISP8 (OP_IMM_TYPE | 0)
-#define OP16_SH_DISP11 (OP_IMM_TYPE | 1)
-
-enum insn_class
-{
- INSN_CLASS_16,
- INSN_CLASS_32,
- INSN_CLASS_48,
- INSN_CLASS_PCE,
- INSN_CLASS_SYN
-};
-
-/* s3_s7: Globals for both tc-score.c and elf32-score.c. */
-extern int score3;
-extern int score7;
-
-#endif
score-inst.h
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: hppa.h
===================================================================
--- hppa.h (revision 816)
+++ hppa.h (nonexistent)
@@ -1,1091 +0,0 @@
-/* Table of opcodes for the PA-RISC.
- Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,
- 2001, 2002, 2003, 2004, 2005, 2006, 2009
- Free Software Foundation, Inc.
-
- Contributed by the Center for Software Science at the
- University of Utah (pa-gdb-bugs@cs.utah.edu).
-
-This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
-
-GAS/GDB is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GAS/GDB is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GAS or GDB; see the file COPYING. If not, write to
-the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
-#if !defined(__STDC__) && !defined(const)
-#define const
-#endif
-
-/*
- * Structure of an opcode table entry.
- */
-
-/* There are two kinds of delay slot nullification: normal which is
- * controled by the nullification bit, and conditional, which depends
- * on the direction of the branch and its success or failure.
- *
- * NONE is unfortunately #defined in the hiux system include files.
- * #undef it away.
- */
-#undef NONE
-struct pa_opcode
-{
- const char *name;
- unsigned long int match; /* Bits that must be set... */
- unsigned long int mask; /* ... in these bits. */
- char *args;
- enum pa_arch arch;
- char flags;
-};
-
-/* Enables strict matching. Opcodes with match errors are skipped
- when this bit is set. */
-#define FLAG_STRICT 0x1
-
-/*
- All hppa opcodes are 32 bits.
-
- The match component is a mask saying which bits must match a
- particular opcode in order for an instruction to be an instance
- of that opcode.
-
- The args component is a string containing one character for each operand of
- the instruction. Characters used as a prefix allow any second character to
- be used without conflicting with the main operand characters.
-
- Bit positions in this description follow HP usage of lsb = 31,
- "at" is lsb of field.
-
- In the args field, the following characters must match exactly:
-
- '+,() '
-
- In the args field, the following characters are unused:
-
- ' " - / 34 6789:; '
- '@ C M [\] '
- '` e g } '
-
- Here are all the characters:
-
- ' !"#$%&'()*+-,./0123456789:;<=>?'
- '@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_'
- '`abcdefghijklmnopqrstuvwxyz{|}~ '
-
-Kinds of operands:
- x integer register field at 15.
- b integer register field at 10.
- t integer register field at 31.
- a integer register field at 10 and 15 (for PERMH)
- 5 5 bit immediate at 15.
- s 2 bit space specifier at 17.
- S 3 bit space specifier at 18.
- V 5 bit immediate value at 31
- i 11 bit immediate value at 31
- j 14 bit immediate value at 31
- k 21 bit immediate value at 31
- l 16 bit immediate value at 31 (wide mode only, unusual encoding).
- n nullification for branch instructions
- N nullification for spop and copr instructions
- w 12 bit branch displacement
- W 17 bit branch displacement (PC relative)
- X 22 bit branch displacement (PC relative)
- z 17 bit branch displacement (just a number, not an address)
-
-Also these:
-
- . 2 bit shift amount at 25
- * 4 bit shift amount at 25
- p 5 bit shift count at 26 (to support the SHD instruction) encoded as
- 31-p
- ~ 6 bit shift count at 20,22:26 encoded as 63-~.
- P 5 bit bit position at 26
- q 6 bit bit position at 20,22:26
- T 5 bit field length at 31 (encoded as 32-T)
- % 6 bit field length at 23,27:31 (variable extract/deposit)
- | 6 bit field length at 19,27:31 (fixed extract/deposit)
- A 13 bit immediate at 18 (to support the BREAK instruction)
- ^ like b, but describes a control register
- ! sar (cr11) register
- D 26 bit immediate at 31 (to support the DIAG instruction)
- $ 9 bit immediate at 28 (to support POPBTS)
-
- v 3 bit Special Function Unit identifier at 25
- O 20 bit Special Function Unit operation split between 15 bits at 20
- and 5 bits at 31
- o 15 bit Special Function Unit operation at 20
- 2 22 bit Special Function Unit operation split between 17 bits at 20
- and 5 bits at 31
- 1 15 bit Special Function Unit operation split between 10 bits at 20
- and 5 bits at 31
- 0 10 bit Special Function Unit operation split between 5 bits at 20
- and 5 bits at 31
- u 3 bit coprocessor unit identifier at 25
- F Source Floating Point Operand Format Completer encoded 2 bits at 20
- I Source Floating Point Operand Format Completer encoded 1 bits at 20
- (for 0xe format FP instructions)
- G Destination Floating Point Operand Format Completer encoded 2 bits at 18
- H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
- (very similar to 'F')
-
- r 5 bit immediate value at 31 (for the break instruction)
- (very similar to V above, except the value is unsigned instead of
- low_sign_ext)
- R 5 bit immediate value at 15 (for the ssm, rsm, probei instructions)
- (same as r above, except the value is in a different location)
- U 10 bit immediate value at 15 (for SSM, RSM on pa2.0)
- Q 5 bit immediate value at 10 (a bit position specified in
- the bb instruction. It's the same as r above, except the
- value is in a different location)
- B 5 bit immediate value at 10 (a bit position specified in
- the bb instruction. Similar to Q, but 64 bit handling is
- different.
- Z %r1 -- implicit target of addil instruction.
- L ,%r2 completer for new syntax branch
- { Source format completer for fcnv
- _ Destination format completer for fcnv
- h cbit for fcmp
- = gfx tests for ftest
- d 14 bit offset for single precision FP long load/store.
- # 14 bit offset for double precision FP load long/store.
- J Yet another 14 bit offset for load/store with ma,mb completers.
- K Yet another 14 bit offset for load/store with ma,mb completers.
- y 16 bit offset for word aligned load/store (PA2.0 wide).
- & 16 bit offset for dword aligned load/store (PA2.0 wide).
- < 16 bit offset for load/store with ma,mb completers (PA2.0 wide).
- > 16 bit offset for load/store with ma,mb completers (PA2.0 wide).
- Y %sr0,%r31 -- implicit target of be,l instruction.
- @ implicit immediate value of 0
-
-Completer operands all have 'c' as the prefix:
-
- cx indexed load and store completer.
- cX indexed load and store completer. Like cx, but emits a space
- after in disassembler.
- cm short load and store completer.
- cM short load and store completer. Like cm, but emits a space
- after in disassembler.
- cq long load and store completer (like cm, but inserted into a
- different location in the target instruction).
- cs store bytes short completer.
- cA store bytes short completer. Like cs, but emits a space
- after in disassembler.
- ce long load/store completer for LDW/STW with a different encoding
- than the others
- cc load cache control hint
- cd load and clear cache control hint
- cC store cache control hint
- co ordered access
-
- cp branch link and push completer
- cP branch pop completer
- cl branch link completer
- cg branch gate completer
-
- cw read/write completer for PROBE
- cW wide completer for MFCTL
- cL local processor completer for cache control
- cZ System Control Completer (to support LPA, LHA, etc.)
-
- ci correction completer for DCOR
- ca add completer
- cy 32 bit add carry completer
- cY 64 bit add carry completer
- cv signed overflow trap completer
- ct trap on condition completer for ADDI, SUB
- cT trap on condition completer for UADDCM
- cb 32 bit borrow completer for SUB
- cB 64 bit borrow completer for SUB
-
- ch left/right half completer
- cH signed/unsigned saturation completer
- cS signed/unsigned completer at 21
- cz zero/sign extension completer.
- c* permutation completer
-
-Condition operands all have '?' as the prefix:
-
- ?f Floating point compare conditions (encoded as 5 bits at 31)
-
- ?a add conditions
- ?A 64 bit add conditions
- ?@ add branch conditions followed by nullify
- ?d non-negated add branch conditions
- ?D negated add branch conditions
- ?w wide mode non-negated add branch conditions
- ?W wide mode negated add branch conditions
-
- ?s compare/subtract conditions
- ?S 64 bit compare/subtract conditions
- ?t non-negated compare and branch conditions
- ?n 32 bit compare and branch conditions followed by nullify
- ?N 64 bit compare and branch conditions followed by nullify
- ?Q 64 bit compare and branch conditions for CMPIB instruction
-
- ?l logical conditions
- ?L 64 bit logical conditions
-
- ?b branch on bit conditions
- ?B 64 bit branch on bit conditions
-
- ?x shift/extract/deposit conditions
- ?X 64 bit shift/extract/deposit conditions
- ?y shift/extract/deposit conditions followed by nullify for conditional
- branches
-
- ?u unit conditions
- ?U 64 bit unit conditions
-
-Floating point registers all have 'f' as a prefix:
-
- ft target register at 31
- fT target register with L/R halves at 31
- fa operand 1 register at 10
- fA operand 1 register with L/R halves at 10
- fX Same as fA, except prints a space before register during disasm
- fb operand 2 register at 15
- fB operand 2 register with L/R halves at 15
- fC operand 3 register with L/R halves at 16:18,21:23
- fe Like fT, but encoding is different.
- fE Same as fe, except prints a space before register during disasm.
- fx target register at 15 (only for PA 2.0 long format FLDD/FSTD).
-
-Float registers for fmpyadd and fmpysub:
-
- fi mult operand 1 register at 10
- fj mult operand 2 register at 15
- fk mult target register at 20
- fl add/sub operand register at 25
- fm add/sub target register at 31
-
-*/
-
-
-#if 0
-/* List of characters not to put a space after. Note that
- "," is included, as the "spopN" operations use literal
- commas in their completer sections. */
-static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}";
-#endif
-
-/* The order of the opcodes in this table is significant:
-
- * The assembler requires that all instances of the same mnemonic be
- consecutive. If they aren't, the assembler will bomb at runtime.
-
- * Immediate fields use pa_get_absolute_expression to parse the
- string. It will generate a "bad expression" error if passed
- a register name. Thus, register index variants of an opcode
- need to precede immediate variants.
-
- * The disassembler does not care about the order of the opcodes
- except in cases where implicit addressing is used.
-
- Here are the rules for ordering the opcodes of a mnemonic:
-
- 1) Opcodes with FLAG_STRICT should precede opcodes without
- FLAG_STRICT.
-
- 2) Opcodes with FLAG_STRICT should be ordered as follows:
- register index opcodes, short immediate opcodes, and finally
- long immediate opcodes. When both pa10 and pa11 variants
- of the same opcode are available, the pa10 opcode should
- come first for correct architectural promotion.
-
- 3) When implicit addressing is available for an opcode, the
- implicit opcode should precede the explicit opcode.
-
- 4) Opcodes without FLAG_STRICT should be ordered as follows:
- register index opcodes, long immediate opcodes, and finally
- short immediate opcodes. */
-
-static const struct pa_opcode pa_opcodes[] =
-{
-
-/* Pseudo-instructions. */
-
-{ "ldi", 0x34000000, 0xffe00000, "l,x", pa20w, 0},/* ldo val(r0),r */
-{ "ldi", 0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */
-
-{ "cmpib", 0xec000000, 0xfc000000, "?Qn5,b,w", pa20, FLAG_STRICT},
-{ "cmpib", 0x84000000, 0xf4000000, "?nn5,b,w", pa10, FLAG_STRICT},
-{ "comib", 0x84000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/
-/* This entry is for the disassembler only. It will never be used by
- assembler. */
-{ "comib", 0x8c000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/
-{ "cmpb", 0x9c000000, 0xdc000000, "?Nnx,b,w", pa20, FLAG_STRICT},
-{ "cmpb", 0x80000000, 0xf4000000, "?nnx,b,w", pa10, FLAG_STRICT},
-{ "comb", 0x80000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */
-/* This entry is for the disassembler only. It will never be used by
- assembler. */
-{ "comb", 0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */
-{ "addb", 0xa0000000, 0xf4000000, "?Wnx,b,w", pa20w, FLAG_STRICT},
-{ "addb", 0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */
-/* This entry is for the disassembler only. It will never be used by
- assembler. */
-{ "addb", 0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0},
-{ "addib", 0xa4000000, 0xf4000000, "?Wn5,b,w", pa20w, FLAG_STRICT},
-{ "addib", 0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/
-/* This entry is for the disassembler only. It will never be used by
- assembler. */
-{ "addib", 0xac000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/
-{ "nop", 0x08000240, 0xffffffff, "", pa10, 0}, /* or 0,0,0 */
-{ "copy", 0x08000240, 0xffe0ffe0, "x,t", pa10, 0}, /* or r,0,t */
-{ "mtsar", 0x01601840, 0xffe0ffff, "x", pa10, 0}, /* mtctl r,cr11 */
-
-/* Loads and Stores for integer registers. */
-
-{ "ldd", 0x0c0000c0, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT},
-{ "ldd", 0x0c0000c0, 0xfc0013c0, "cxccx(s,b),t", pa20, FLAG_STRICT},
-{ "ldd", 0x0c0010e0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
-{ "ldd", 0x0c0010e0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
-{ "ldd", 0x0c0010c0, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT},
-{ "ldd", 0x0c0010c0, 0xfc0013c0, "cmcc5(s,b),t", pa20, FLAG_STRICT},
-{ "ldd", 0x50000000, 0xfc000002, "cq&(b),x", pa20w, FLAG_STRICT},
-{ "ldd", 0x50000000, 0xfc00c002, "cq#(b),x", pa20, FLAG_STRICT},
-{ "ldd", 0x50000000, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT},
-{ "ldw", 0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
-{ "ldw", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
-{ "ldw", 0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
-{ "ldw", 0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
-{ "ldw", 0x0c0010a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
-{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
-{ "ldw", 0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
-{ "ldw", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
-{ "ldw", 0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
-{ "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
-{ "ldw", 0x4c000000, 0xfc000000, "ce<(b),x", pa20w, FLAG_STRICT},
-{ "ldw", 0x5c000004, 0xfc000006, "ce>(b),x", pa20w, FLAG_STRICT},
-{ "ldw", 0x48000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},
-{ "ldw", 0x5c000004, 0xfc00c006, "ceK(b),x", pa20, FLAG_STRICT},
-{ "ldw", 0x5c000004, 0xfc000006, "ceK(s,b),x", pa20, FLAG_STRICT},
-{ "ldw", 0x4c000000, 0xfc00c000, "ceJ(b),x", pa10, FLAG_STRICT},
-{ "ldw", 0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, FLAG_STRICT},
-{ "ldw", 0x48000000, 0xfc00c000, "j(b),x", pa10, 0},
-{ "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10, 0},
-{ "ldh", 0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
-{ "ldh", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
-{ "ldh", 0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
-{ "ldh", 0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
-{ "ldh", 0x0c001060, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
-{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
-{ "ldh", 0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
-{ "ldh", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
-{ "ldh", 0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
-{ "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
-{ "ldh", 0x44000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},
-{ "ldh", 0x44000000, 0xfc00c000, "j(b),x", pa10, 0},
-{ "ldh", 0x44000000, 0xfc000000, "j(s,b),x", pa10, 0},
-{ "ldb", 0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
-{ "ldb", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
-{ "ldb", 0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
-{ "ldb", 0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
-{ "ldb", 0x0c001020, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
-{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
-{ "ldb", 0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
-{ "ldb", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
-{ "ldb", 0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
-{ "ldb", 0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
-{ "ldb", 0x40000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},
-{ "ldb", 0x40000000, 0xfc00c000, "j(b),x", pa10, 0},
-{ "ldb", 0x40000000, 0xfc000000, "j(s,b),x", pa10, 0},
-{ "std", 0x0c0012e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
-{ "std", 0x0c0012e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
-{ "std", 0x0c0012c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT},
-{ "std", 0x0c0012c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT},
-{ "std", 0x70000000, 0xfc000002, "cqx,&(b)", pa20w, FLAG_STRICT},
-{ "std", 0x70000000, 0xfc00c002, "cqx,#(b)", pa20, FLAG_STRICT},
-{ "std", 0x70000000, 0xfc000002, "cqx,#(s,b)", pa20, FLAG_STRICT},
-{ "stw", 0x0c0012a0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
-{ "stw", 0x0c0012a0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
-{ "stw", 0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
-{ "stw", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
-{ "stw", 0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
-{ "stw", 0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
-{ "stw", 0x6c000000, 0xfc000000, "cex,<(b)", pa20w, FLAG_STRICT},
-{ "stw", 0x7c000004, 0xfc000006, "cex,>(b)", pa20w, FLAG_STRICT},
-{ "stw", 0x68000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},
-{ "stw", 0x7c000004, 0xfc00c006, "cex,K(b)", pa20, FLAG_STRICT},
-{ "stw", 0x7c000004, 0xfc000006, "cex,K(s,b)", pa20, FLAG_STRICT},
-{ "stw", 0x6c000000, 0xfc00c000, "cex,J(b)", pa10, FLAG_STRICT},
-{ "stw", 0x6c000000, 0xfc000000, "cex,J(s,b)", pa10, FLAG_STRICT},
-{ "stw", 0x68000000, 0xfc00c000, "x,j(b)", pa10, 0},
-{ "stw", 0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0},
-{ "sth", 0x0c001260, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
-{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
-{ "sth", 0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
-{ "sth", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
-{ "sth", 0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
-{ "sth", 0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
-{ "sth", 0x64000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},
-{ "sth", 0x64000000, 0xfc00c000, "x,j(b)", pa10, 0},
-{ "sth", 0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0},
-{ "stb", 0x0c001220, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
-{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
-{ "stb", 0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
-{ "stb", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
-{ "stb", 0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
-{ "stb", 0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
-{ "stb", 0x60000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},
-{ "stb", 0x60000000, 0xfc00c000, "x,j(b)", pa10, 0},
-{ "stb", 0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0},
-{ "ldwm", 0x4c000000, 0xfc00c000, "j(b),x", pa10, 0},
-{ "ldwm", 0x4c000000, 0xfc000000, "j(s,b),x", pa10, 0},
-{ "stwm", 0x6c000000, 0xfc00c000, "x,j(b)", pa10, 0},
-{ "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0},
-{ "ldwx", 0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
-{ "ldwx", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
-{ "ldwx", 0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
-{ "ldwx", 0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
-{ "ldwx", 0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, 0},
-{ "ldwx", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
-{ "ldhx", 0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
-{ "ldhx", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
-{ "ldhx", 0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
-{ "ldhx", 0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
-{ "ldhx", 0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, 0},
-{ "ldhx", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
-{ "ldbx", 0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
-{ "ldbx", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
-{ "ldbx", 0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
-{ "ldbx", 0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
-{ "ldbx", 0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, 0},
-{ "ldbx", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
-{ "ldwa", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
-{ "ldwa", 0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
-{ "ldwa", 0x0c0011a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
-{ "ldwa", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
-{ "ldwa", 0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
-{ "ldcw", 0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
-{ "ldcw", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
-{ "ldcw", 0x0c0001c0, 0xfc00d3c0, "cxcdx(b),t", pa11, FLAG_STRICT},
-{ "ldcw", 0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa11, FLAG_STRICT},
-{ "ldcw", 0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
-{ "ldcw", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
-{ "ldcw", 0x0c0011c0, 0xfc00d3c0, "cmcd5(b),t", pa11, FLAG_STRICT},
-{ "ldcw", 0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa11, FLAG_STRICT},
-{ "stwa", 0x0c0013a0, 0xfc00d3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
-{ "stwa", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
-{ "stwa", 0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
-{ "stby", 0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, FLAG_STRICT},
-{ "stby", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, FLAG_STRICT},
-{ "stby", 0x0c001300, 0xfc00d3c0, "cscCx,V(b)", pa11, FLAG_STRICT},
-{ "stby", 0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa11, FLAG_STRICT},
-{ "ldda", 0x0c000100, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT},
-{ "ldda", 0x0c001120, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
-{ "ldda", 0x0c001100, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT},
-{ "ldcd", 0x0c000140, 0xfc00d3c0, "cxcdx(b),t", pa20, FLAG_STRICT},
-{ "ldcd", 0x0c000140, 0xfc0013c0, "cxcdx(s,b),t", pa20, FLAG_STRICT},
-{ "ldcd", 0x0c001140, 0xfc00d3c0, "cmcd5(b),t", pa20, FLAG_STRICT},
-{ "ldcd", 0x0c001140, 0xfc0013c0, "cmcd5(s,b),t", pa20, FLAG_STRICT},
-{ "stda", 0x0c0013e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
-{ "stda", 0x0c0013c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT},
-{ "ldwax", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
-{ "ldwax", 0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
-{ "ldwax", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, 0},
-{ "ldcwx", 0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
-{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
-{ "ldcwx", 0x0c0001c0, 0xfc00d3c0, "cxcdx(b),t", pa11, FLAG_STRICT},
-{ "ldcwx", 0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa11, FLAG_STRICT},
-{ "ldcwx", 0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, 0},
-{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
-{ "ldws", 0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
-{ "ldws", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
-{ "ldws", 0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
-{ "ldws", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
-{ "ldws", 0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, 0},
-{ "ldws", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
-{ "ldhs", 0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
-{ "ldhs", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
-{ "ldhs", 0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
-{ "ldhs", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
-{ "ldhs", 0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, 0},
-{ "ldhs", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
-{ "ldbs", 0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
-{ "ldbs", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
-{ "ldbs", 0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
-{ "ldbs", 0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
-{ "ldbs", 0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, 0},
-{ "ldbs", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
-{ "ldwas", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
-{ "ldwas", 0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
-{ "ldwas", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, 0},
-{ "ldcws", 0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
-{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
-{ "ldcws", 0x0c0011c0, 0xfc00d3c0, "cmcd5(b),t", pa11, FLAG_STRICT},
-{ "ldcws", 0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa11, FLAG_STRICT},
-{ "ldcws", 0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, 0},
-{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
-{ "stws", 0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
-{ "stws", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
-{ "stws", 0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
-{ "stws", 0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
-{ "stws", 0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
-{ "stws", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
-{ "sths", 0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
-{ "sths", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
-{ "sths", 0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
-{ "sths", 0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
-{ "sths", 0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
-{ "sths", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
-{ "stbs", 0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
-{ "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
-{ "stbs", 0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
-{ "stbs", 0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
-{ "stbs", 0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
-{ "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
-{ "stwas", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
-{ "stwas", 0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
-{ "stwas", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
-{ "stdby", 0x0c001340, 0xfc00d3c0, "cscCx,V(b)", pa20, FLAG_STRICT},
-{ "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(s,b)", pa20, FLAG_STRICT},
-{ "stbys", 0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, FLAG_STRICT},
-{ "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, FLAG_STRICT},
-{ "stbys", 0x0c001300, 0xfc00d3c0, "cscCx,V(b)", pa11, FLAG_STRICT},
-{ "stbys", 0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa11, FLAG_STRICT},
-{ "stbys", 0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, 0},
-{ "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, 0},
-
-/* Immediate instructions. */
-{ "ldo", 0x34000000, 0xfc000000, "l(b),x", pa20w, 0},
-{ "ldo", 0x34000000, 0xfc00c000, "j(b),x", pa10, 0},
-{ "ldil", 0x20000000, 0xfc000000, "k,b", pa10, 0},
-{ "addil", 0x28000000, 0xfc000000, "k,b,Z", pa10, 0},
-{ "addil", 0x28000000, 0xfc000000, "k,b", pa10, 0},
-
-/* Branching instructions. */
-{ "b", 0xe8008000, 0xfc00e000, "cpnXL", pa20, FLAG_STRICT},
-{ "b", 0xe800a000, 0xfc00e000, "clnXL", pa20, FLAG_STRICT},
-{ "b", 0xe8000000, 0xfc00e000, "clnW,b", pa10, FLAG_STRICT},
-{ "b", 0xe8002000, 0xfc00e000, "cgnW,b", pa10, FLAG_STRICT},
-{ "b", 0xe8000000, 0xffe0e000, "nW", pa10, 0}, /* b,l foo,r0 */
-{ "bl", 0xe8000000, 0xfc00e000, "nW,b", pa10, 0},
-{ "gate", 0xe8002000, 0xfc00e000, "nW,b", pa10, 0},
-{ "blr", 0xe8004000, 0xfc00e001, "nx,b", pa10, 0},
-{ "bv", 0xe800c000, 0xfc00fffd, "nx(b)", pa10, 0},
-{ "bv", 0xe800c000, 0xfc00fffd, "n(b)", pa10, 0},
-{ "bve", 0xe800f001, 0xfc1ffffd, "cpn(b)L", pa20, FLAG_STRICT},
-{ "bve", 0xe800f000, 0xfc1ffffd, "cln(b)L", pa20, FLAG_STRICT},
-{ "bve", 0xe800d001, 0xfc1ffffd, "cPn(b)", pa20, FLAG_STRICT},
-{ "bve", 0xe800d000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT},
-{ "be", 0xe4000000, 0xfc000000, "clnz(S,b),Y", pa10, FLAG_STRICT},
-{ "be", 0xe4000000, 0xfc000000, "clnz(b),Y", pa10, FLAG_STRICT},
-{ "be", 0xe0000000, 0xfc000000, "nz(S,b)", pa10, 0},
-{ "be", 0xe0000000, 0xfc000000, "nz(b)", pa10, 0},
-{ "ble", 0xe4000000, 0xfc000000, "nz(S,b)", pa10, 0},
-{ "movb", 0xc8000000, 0xfc000000, "?ynx,b,w", pa10, 0},
-{ "movib", 0xcc000000, 0xfc000000, "?yn5,b,w", pa10, 0},
-{ "combt", 0x80000000, 0xfc000000, "?tnx,b,w", pa10, 0},
-{ "combf", 0x88000000, 0xfc000000, "?tnx,b,w", pa10, 0},
-{ "comibt", 0x84000000, 0xfc000000, "?tn5,b,w", pa10, 0},
-{ "comibf", 0x8c000000, 0xfc000000, "?tn5,b,w", pa10, 0},
-{ "addbt", 0xa0000000, 0xfc000000, "?dnx,b,w", pa10, 0},
-{ "addbf", 0xa8000000, 0xfc000000, "?dnx,b,w", pa10, 0},
-{ "addibt", 0xa4000000, 0xfc000000, "?dn5,b,w", pa10, 0},
-{ "addibf", 0xac000000, 0xfc000000, "?dn5,b,w", pa10, 0},
-{ "bb", 0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT},
-{ "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT},
-{ "bb", 0xc4004000, 0xfc006000, "?bnx,Q,w", pa10, FLAG_STRICT},
-{ "bb", 0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT},
-{ "bb", 0xc4004000, 0xfc006000, "?bnx,Q,w", pa10, 0},
-{ "bvb", 0xc0004000, 0xffe04000, "?bnx,w", pa10, 0},
-{ "clrbts", 0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT},
-{ "popbts", 0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT},
-{ "pushnom", 0xe8004001, 0xffffffff, "", pa20, FLAG_STRICT},
-{ "pushbts", 0xe8004001, 0xffe0ffff, "x", pa20, FLAG_STRICT},
-
-/* Computation Instructions. */
-
-{ "cmpclr", 0x080008a0, 0xfc000fe0, "?Sx,b,t", pa20, FLAG_STRICT},
-{ "cmpclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, FLAG_STRICT},
-{ "comclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, 0},
-{ "or", 0x08000260, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
-{ "or", 0x08000240, 0xfc000fe0, "?lx,b,t", pa10, 0},
-{ "xor", 0x080002a0, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
-{ "xor", 0x08000280, 0xfc000fe0, "?lx,b,t", pa10, 0},
-{ "and", 0x08000220, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
-{ "and", 0x08000200, 0xfc000fe0, "?lx,b,t", pa10, 0},
-{ "andcm", 0x08000020, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
-{ "andcm", 0x08000000, 0xfc000fe0, "?lx,b,t", pa10, 0},
-{ "uxor", 0x080003a0, 0xfc000fe0, "?Ux,b,t", pa20, FLAG_STRICT},
-{ "uxor", 0x08000380, 0xfc000fe0, "?ux,b,t", pa10, 0},
-{ "uaddcm", 0x080009a0, 0xfc000fa0, "cT?Ux,b,t", pa20, FLAG_STRICT},
-{ "uaddcm", 0x08000980, 0xfc000fa0, "cT?ux,b,t", pa10, FLAG_STRICT},
-{ "uaddcm", 0x08000980, 0xfc000fe0, "?ux,b,t", pa10, 0},
-{ "uaddcmt", 0x080009c0, 0xfc000fe0, "?ux,b,t", pa10, 0},
-{ "dcor", 0x08000ba0, 0xfc1f0fa0, "ci?Ub,t", pa20, FLAG_STRICT},
-{ "dcor", 0x08000b80, 0xfc1f0fa0, "ci?ub,t", pa10, FLAG_STRICT},
-{ "dcor", 0x08000b80, 0xfc1f0fe0, "?ub,t", pa10, 0},
-{ "idcor", 0x08000bc0, 0xfc1f0fe0, "?ub,t", pa10, 0},
-{ "addi", 0xb0000000, 0xfc000000, "ct?ai,b,x", pa10, FLAG_STRICT},
-{ "addi", 0xb4000000, 0xfc000000, "cv?ai,b,x", pa10, FLAG_STRICT},
-{ "addi", 0xb4000000, 0xfc000800, "?ai,b,x", pa10, 0},
-{ "addio", 0xb4000800, 0xfc000800, "?ai,b,x", pa10, 0},
-{ "addit", 0xb0000000, 0xfc000800, "?ai,b,x", pa10, 0},
-{ "addito", 0xb0000800, 0xfc000800, "?ai,b,x", pa10, 0},
-{ "add", 0x08000720, 0xfc0007e0, "cY?Ax,b,t", pa20, FLAG_STRICT},
-{ "add", 0x08000700, 0xfc0007e0, "cy?ax,b,t", pa10, FLAG_STRICT},
-{ "add", 0x08000220, 0xfc0003e0, "ca?Ax,b,t", pa20, FLAG_STRICT},
-{ "add", 0x08000200, 0xfc0003e0, "ca?ax,b,t", pa10, FLAG_STRICT},
-{ "add", 0x08000600, 0xfc000fe0, "?ax,b,t", pa10, 0},
-{ "addl", 0x08000a00, 0xfc000fe0, "?ax,b,t", pa10, 0},
-{ "addo", 0x08000e00, 0xfc000fe0, "?ax,b,t", pa10, 0},
-{ "addc", 0x08000700, 0xfc000fe0, "?ax,b,t", pa10, 0},
-{ "addco", 0x08000f00, 0xfc000fe0, "?ax,b,t", pa10, 0},
-{ "sub", 0x080004e0, 0xfc0007e0, "ct?Sx,b,t", pa20, FLAG_STRICT},
-{ "sub", 0x080004c0, 0xfc0007e0, "ct?sx,b,t", pa10, FLAG_STRICT},
-{ "sub", 0x08000520, 0xfc0007e0, "cB?Sx,b,t", pa20, FLAG_STRICT},
-{ "sub", 0x08000500, 0xfc0007e0, "cb?sx,b,t", pa10, FLAG_STRICT},
-{ "sub", 0x08000420, 0xfc0007e0, "cv?Sx,b,t", pa20, FLAG_STRICT},
-{ "sub", 0x08000400, 0xfc0007e0, "cv?sx,b,t", pa10, FLAG_STRICT},
-{ "sub", 0x08000400, 0xfc000fe0, "?sx,b,t", pa10, 0},
-{ "subo", 0x08000c00, 0xfc000fe0, "?sx,b,t", pa10, 0},
-{ "subb", 0x08000500, 0xfc000fe0, "?sx,b,t", pa10, 0},
-{ "subbo", 0x08000d00, 0xfc000fe0, "?sx,b,t", pa10, 0},
-{ "subt", 0x080004c0, 0xfc000fe0, "?sx,b,t", pa10, 0},
-{ "subto", 0x08000cc0, 0xfc000fe0, "?sx,b,t", pa10, 0},
-{ "ds", 0x08000440, 0xfc000fe0, "?sx,b,t", pa10, 0},
-{ "subi", 0x94000000, 0xfc000000, "cv?si,b,x", pa10, FLAG_STRICT},
-{ "subi", 0x94000000, 0xfc000800, "?si,b,x", pa10, 0},
-{ "subio", 0x94000800, 0xfc000800, "?si,b,x", pa10, 0},
-{ "cmpiclr", 0x90000800, 0xfc000800, "?Si,b,x", pa20, FLAG_STRICT},
-{ "cmpiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, FLAG_STRICT},
-{ "comiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, 0},
-{ "shladd", 0x08000220, 0xfc000320, "ca?Ax,.,b,t", pa20, FLAG_STRICT},
-{ "shladd", 0x08000200, 0xfc000320, "ca?ax,.,b,t", pa10, FLAG_STRICT},
-{ "sh1add", 0x08000640, 0xfc000fe0, "?ax,b,t", pa10, 0},
-{ "sh1addl", 0x08000a40, 0xfc000fe0, "?ax,b,t", pa10, 0},
-{ "sh1addo", 0x08000e40, 0xfc000fe0, "?ax,b,t", pa10, 0},
-{ "sh2add", 0x08000680, 0xfc000fe0, "?ax,b,t", pa10, 0},
-{ "sh2addl", 0x08000a80, 0xfc000fe0, "?ax,b,t", pa10, 0},
-{ "sh2addo", 0x08000e80, 0xfc000fe0, "?ax,b,t", pa10, 0},
-{ "sh3add", 0x080006c0, 0xfc000fe0, "?ax,b,t", pa10, 0},
-{ "sh3addl", 0x08000ac0, 0xfc000fe0, "?ax,b,t", pa10, 0},
-{ "sh3addo", 0x08000ec0, 0xfc000fe0, "?ax,b,t", pa10, 0},
-
-/* Subword Operation Instructions. */
-
-{ "hadd", 0x08000300, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT},
-{ "havg", 0x080002c0, 0xfc00ffe0, "x,b,t", pa20, FLAG_STRICT},
-{ "hshl", 0xf8008800, 0xffe0fc20, "x,*,t", pa20, FLAG_STRICT},
-{ "hshladd", 0x08000700, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT},
-{ "hshr", 0xf800c800, 0xfc1ff820, "cSb,*,t", pa20, FLAG_STRICT},
-{ "hshradd", 0x08000500, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT},
-{ "hsub", 0x08000100, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT},
-{ "mixh", 0xf8008400, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT},
-{ "mixw", 0xf8008000, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT},
-{ "permh", 0xf8000000, 0xfc009020, "c*a,t", pa20, FLAG_STRICT},
-
-
-/* Extract and Deposit Instructions. */
-
-{ "shrpd", 0xd0000200, 0xfc001fe0, "?Xx,b,!,t", pa20, FLAG_STRICT},
-{ "shrpd", 0xd0000400, 0xfc001400, "?Xx,b,~,t", pa20, FLAG_STRICT},
-{ "shrpw", 0xd0000000, 0xfc001fe0, "?xx,b,!,t", pa10, FLAG_STRICT},
-{ "shrpw", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, FLAG_STRICT},
-{ "vshd", 0xd0000000, 0xfc001fe0, "?xx,b,t", pa10, 0},
-{ "shd", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, 0},
-{ "extrd", 0xd0001200, 0xfc001ae0, "cS?Xb,!,%,x", pa20, FLAG_STRICT},
-{ "extrd", 0xd8000000, 0xfc000000, "cS?Xb,q,|,x", pa20, FLAG_STRICT},
-{ "extrw", 0xd0001000, 0xfc001be0, "cS?xb,!,T,x", pa10, FLAG_STRICT},
-{ "extrw", 0xd0001800, 0xfc001800, "cS?xb,P,T,x", pa10, FLAG_STRICT},
-{ "vextru", 0xd0001000, 0xfc001fe0, "?xb,T,x", pa10, 0},
-{ "vextrs", 0xd0001400, 0xfc001fe0, "?xb,T,x", pa10, 0},
-{ "extru", 0xd0001800, 0xfc001c00, "?xb,P,T,x", pa10, 0},
-{ "extrs", 0xd0001c00, 0xfc001c00, "?xb,P,T,x", pa10, 0},
-{ "depd", 0xd4000200, 0xfc001ae0, "cz?Xx,!,%,b", pa20, FLAG_STRICT},
-{ "depd", 0xf0000000, 0xfc000000, "cz?Xx,~,|,b", pa20, FLAG_STRICT},
-{ "depdi", 0xd4001200, 0xfc001ae0, "cz?X5,!,%,b", pa20, FLAG_STRICT},
-{ "depdi", 0xf4000000, 0xfc000000, "cz?X5,~,|,b", pa20, FLAG_STRICT},
-{ "depw", 0xd4000000, 0xfc001be0, "cz?xx,!,T,b", pa10, FLAG_STRICT},
-{ "depw", 0xd4000800, 0xfc001800, "cz?xx,p,T,b", pa10, FLAG_STRICT},
-{ "depwi", 0xd4001000, 0xfc001be0, "cz?x5,!,T,b", pa10, FLAG_STRICT},
-{ "depwi", 0xd4001800, 0xfc001800, "cz?x5,p,T,b", pa10, FLAG_STRICT},
-{ "zvdep", 0xd4000000, 0xfc001fe0, "?xx,T,b", pa10, 0},
-{ "vdep", 0xd4000400, 0xfc001fe0, "?xx,T,b", pa10, 0},
-{ "zdep", 0xd4000800, 0xfc001c00, "?xx,p,T,b", pa10, 0},
-{ "dep", 0xd4000c00, 0xfc001c00, "?xx,p,T,b", pa10, 0},
-{ "zvdepi", 0xd4001000, 0xfc001fe0, "?x5,T,b", pa10, 0},
-{ "vdepi", 0xd4001400, 0xfc001fe0, "?x5,T,b", pa10, 0},
-{ "zdepi", 0xd4001800, 0xfc001c00, "?x5,p,T,b", pa10, 0},
-{ "depi", 0xd4001c00, 0xfc001c00, "?x5,p,T,b", pa10, 0},
-
-/* System Control Instructions. */
-
-{ "break", 0x00000000, 0xfc001fe0, "r,A", pa10, 0},
-{ "rfi", 0x00000c00, 0xffffff1f, "cr", pa10, FLAG_STRICT},
-{ "rfi", 0x00000c00, 0xffffffff, "", pa10, 0},
-{ "rfir", 0x00000ca0, 0xffffffff, "", pa11, 0},
-{ "ssm", 0x00000d60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT},
-{ "ssm", 0x00000d60, 0xffe0ffe0, "R,t", pa10, 0},
-{ "rsm", 0x00000e60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT},
-{ "rsm", 0x00000e60, 0xffe0ffe0, "R,t", pa10, 0},
-{ "mtsm", 0x00001860, 0xffe0ffff, "x", pa10, 0},
-{ "ldsid", 0x000010a0, 0xfc1fffe0, "(b),t", pa10, 0},
-{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10, 0},
-{ "mtsp", 0x00001820, 0xffe01fff, "x,S", pa10, 0},
-{ "mtctl", 0x00001840, 0xfc00ffff, "x,^", pa10, 0},
-{ "mtsarcm", 0x016018C0, 0xffe0ffff, "x", pa20, FLAG_STRICT},
-{ "mfia", 0x000014A0, 0xffffffe0, "t", pa20, FLAG_STRICT},
-{ "mfsp", 0x000004a0, 0xffff1fe0, "S,t", pa10, 0},
-{ "mfctl", 0x016048a0, 0xffffffe0, "cW!,t", pa20, FLAG_STRICT},
-{ "mfctl", 0x000008a0, 0xfc1fffe0, "^,t", pa10, 0},
-{ "sync", 0x00000400, 0xffffffff, "", pa10, 0},
-{ "syncdma", 0x00100400, 0xffffffff, "", pa10, 0},
-{ "probe", 0x04001180, 0xfc00ffa0, "cw(b),x,t", pa10, FLAG_STRICT},
-{ "probe", 0x04001180, 0xfc003fa0, "cw(s,b),x,t", pa10, FLAG_STRICT},
-{ "probei", 0x04003180, 0xfc00ffa0, "cw(b),R,t", pa10, FLAG_STRICT},
-{ "probei", 0x04003180, 0xfc003fa0, "cw(s,b),R,t", pa10, FLAG_STRICT},
-{ "prober", 0x04001180, 0xfc00ffe0, "(b),x,t", pa10, 0},
-{ "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t", pa10, 0},
-{ "proberi", 0x04003180, 0xfc00ffe0, "(b),R,t", pa10, 0},
-{ "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t", pa10, 0},
-{ "probew", 0x040011c0, 0xfc00ffe0, "(b),x,t", pa10, 0},
-{ "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10, 0},
-{ "probewi", 0x040031c0, 0xfc00ffe0, "(b),R,t", pa10, 0},
-{ "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10, 0},
-{ "lpa", 0x04001340, 0xfc00ffc0, "cZx(b),t", pa10, 0},
-{ "lpa", 0x04001340, 0xfc003fc0, "cZx(s,b),t", pa10, 0},
-{ "lci", 0x04001300, 0xfc00ffe0, "x(b),t", pa11, 0},
-{ "lci", 0x04001300, 0xfc003fe0, "x(s,b),t", pa11, 0},
-{ "pdtlb", 0x04001600, 0xfc00ffdf, "cLcZx(b)", pa20, FLAG_STRICT},
-{ "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(s,b)", pa20, FLAG_STRICT},
-{ "pdtlb", 0x04001600, 0xfc1fffdf, "cLcZ@(b)", pa20, FLAG_STRICT},
-{ "pdtlb", 0x04001600, 0xfc1f3fdf, "cLcZ@(s,b)", pa20, FLAG_STRICT},
-{ "pdtlb", 0x04001200, 0xfc00ffdf, "cZx(b)", pa10, 0},
-{ "pdtlb", 0x04001200, 0xfc003fdf, "cZx(s,b)", pa10, 0},
-{ "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(S,b)", pa20, FLAG_STRICT},
-{ "pitlb", 0x04000600, 0xfc1f1fdf, "cLcZ@(S,b)", pa20, FLAG_STRICT},
-{ "pitlb", 0x04000200, 0xfc001fdf, "cZx(S,b)", pa10, 0},
-{ "pdtlbe", 0x04001240, 0xfc00ffdf, "cZx(b)", pa10, 0},
-{ "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(s,b)", pa10, 0},
-{ "pitlbe", 0x04000240, 0xfc001fdf, "cZx(S,b)", pa10, 0},
-{ "idtlba", 0x04001040, 0xfc00ffff, "x,(b)", pa10, 0},
-{ "idtlba", 0x04001040, 0xfc003fff, "x,(s,b)", pa10, 0},
-{ "iitlba", 0x04000040, 0xfc001fff, "x,(S,b)", pa10, 0},
-{ "idtlbp", 0x04001000, 0xfc00ffff, "x,(b)", pa10, 0},
-{ "idtlbp", 0x04001000, 0xfc003fff, "x,(s,b)", pa10, 0},
-{ "iitlbp", 0x04000000, 0xfc001fff, "x,(S,b)", pa10, 0},
-{ "pdc", 0x04001380, 0xfc00ffdf, "cZx(b)", pa10, 0},
-{ "pdc", 0x04001380, 0xfc003fdf, "cZx(s,b)", pa10, 0},
-{ "fdc", 0x04001280, 0xfc00ffdf, "cZx(b)", pa10, FLAG_STRICT},
-{ "fdc", 0x04001280, 0xfc003fdf, "cZx(s,b)", pa10, FLAG_STRICT},
-{ "fdc", 0x04003280, 0xfc00ffff, "5(b)", pa20, FLAG_STRICT},
-{ "fdc", 0x04003280, 0xfc003fff, "5(s,b)", pa20, FLAG_STRICT},
-{ "fdc", 0x04001280, 0xfc00ffdf, "cZx(b)", pa10, 0},
-{ "fdc", 0x04001280, 0xfc003fdf, "cZx(s,b)", pa10, 0},
-{ "fic", 0x040013c0, 0xfc00dfdf, "cZx(b)", pa20, FLAG_STRICT},
-{ "fic", 0x04000280, 0xfc001fdf, "cZx(S,b)", pa10, 0},
-{ "fdce", 0x040012c0, 0xfc00ffdf, "cZx(b)", pa10, 0},
-{ "fdce", 0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10, 0},
-{ "fice", 0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10, 0},
-{ "diag", 0x14000000, 0xfc000000, "D", pa10, 0},
-{ "idtlbt", 0x04001800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT},
-{ "iitlbt", 0x04000800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT},
-
-/* These may be specific to certain versions of the PA. Joel claimed
- they were 72000 (7200?) specific. However, I'm almost certain the
- mtcpu/mfcpu were undocumented, but available in the older 700 machines. */
-{ "mtcpu", 0x14001600, 0xfc00ffff, "x,^", pa10, 0},
-{ "mfcpu", 0x14001A00, 0xfc00ffff, "^,x", pa10, 0},
-{ "tocen", 0x14403600, 0xffffffff, "", pa10, 0},
-{ "tocdis", 0x14401620, 0xffffffff, "", pa10, 0},
-{ "shdwgr", 0x14402600, 0xffffffff, "", pa10, 0},
-{ "grshdw", 0x14400620, 0xffffffff, "", pa10, 0},
-
-/* gfw and gfr are not in the HP PA 1.1 manual, but they are in either
- the Timex FPU or the Mustang ERS (not sure which) manual. */
-{ "gfw", 0x04001680, 0xfc00ffdf, "cZx(b)", pa11, 0},
-{ "gfw", 0x04001680, 0xfc003fdf, "cZx(s,b)", pa11, 0},
-{ "gfr", 0x04001a80, 0xfc00ffdf, "cZx(b)", pa11, 0},
-{ "gfr", 0x04001a80, 0xfc003fdf, "cZx(s,b)", pa11, 0},
-
-/* Floating Point Coprocessor Instructions. */
-
-{ "fldw", 0x24000000, 0xfc00df80, "cXx(b),fT", pa10, FLAG_STRICT},
-{ "fldw", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, FLAG_STRICT},
-{ "fldw", 0x24000000, 0xfc00d380, "cxccx(b),fT", pa11, FLAG_STRICT},
-{ "fldw", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa11, FLAG_STRICT},
-{ "fldw", 0x24001020, 0xfc1ff3a0, "cocc@(b),fT", pa20, FLAG_STRICT},
-{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(s,b),fT", pa20, FLAG_STRICT},
-{ "fldw", 0x24001000, 0xfc00df80, "cM5(b),fT", pa10, FLAG_STRICT},
-{ "fldw", 0x24001000, 0xfc001f80, "cM5(s,b),fT", pa10, FLAG_STRICT},
-{ "fldw", 0x24001000, 0xfc00d380, "cmcc5(b),fT", pa11, FLAG_STRICT},
-{ "fldw", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa11, FLAG_STRICT},
-{ "fldw", 0x5c000000, 0xfc000004, "y(b),fe", pa20w, FLAG_STRICT},
-{ "fldw", 0x58000000, 0xfc000000, "cJy(b),fe", pa20w, FLAG_STRICT},
-{ "fldw", 0x5c000000, 0xfc00c004, "d(b),fe", pa20, FLAG_STRICT},
-{ "fldw", 0x5c000000, 0xfc000004, "d(s,b),fe", pa20, FLAG_STRICT},
-{ "fldw", 0x58000000, 0xfc00c000, "cJd(b),fe", pa20, FLAG_STRICT},
-{ "fldw", 0x58000000, 0xfc000000, "cJd(s,b),fe", pa20, FLAG_STRICT},
-{ "fldd", 0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, FLAG_STRICT},
-{ "fldd", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, FLAG_STRICT},
-{ "fldd", 0x2c000000, 0xfc00d3c0, "cxccx(b),ft", pa11, FLAG_STRICT},
-{ "fldd", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa11, FLAG_STRICT},
-{ "fldd", 0x2c001020, 0xfc1ff3e0, "cocc@(b),ft", pa20, FLAG_STRICT},
-{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(s,b),ft", pa20, FLAG_STRICT},
-{ "fldd", 0x2c001000, 0xfc00dfc0, "cM5(b),ft", pa10, FLAG_STRICT},
-{ "fldd", 0x2c001000, 0xfc001fc0, "cM5(s,b),ft", pa10, FLAG_STRICT},
-{ "fldd", 0x2c001000, 0xfc00d3c0, "cmcc5(b),ft", pa11, FLAG_STRICT},
-{ "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa11, FLAG_STRICT},
-{ "fldd", 0x50000002, 0xfc000002, "cq&(b),fx", pa20w, FLAG_STRICT},
-{ "fldd", 0x50000002, 0xfc00c002, "cq#(b),fx", pa20, FLAG_STRICT},
-{ "fldd", 0x50000002, 0xfc000002, "cq#(s,b),fx", pa20, FLAG_STRICT},
-{ "fstw", 0x24000200, 0xfc00df80, "cXfT,x(b)", pa10, FLAG_STRICT},
-{ "fstw", 0x24000200, 0xfc001f80, "cXfT,x(s,b)", pa10, FLAG_STRICT},
-{ "fstw", 0x24000200, 0xfc00d380, "cxcCfT,x(b)", pa11, FLAG_STRICT},
-{ "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa11, FLAG_STRICT},
-{ "fstw", 0x24001220, 0xfc1ff3a0, "cocCfT,@(b)", pa20, FLAG_STRICT},
-{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(s,b)", pa20, FLAG_STRICT},
-{ "fstw", 0x24001200, 0xfc00df80, "cMfT,5(b)", pa10, FLAG_STRICT},
-{ "fstw", 0x24001200, 0xfc001f80, "cMfT,5(s,b)", pa10, FLAG_STRICT},
-{ "fstw", 0x24001200, 0xfc00df80, "cMfT,5(b)", pa10, FLAG_STRICT},
-{ "fstw", 0x24001200, 0xfc001f80, "cMfT,5(s,b)", pa10, FLAG_STRICT},
-{ "fstw", 0x7c000000, 0xfc000004, "fE,y(b)", pa20w, FLAG_STRICT},
-{ "fstw", 0x78000000, 0xfc000000, "cJfE,y(b)", pa20w, FLAG_STRICT},
-{ "fstw", 0x7c000000, 0xfc00c004, "fE,d(b)", pa20, FLAG_STRICT},
-{ "fstw", 0x7c000000, 0xfc000004, "fE,d(s,b)", pa20, FLAG_STRICT},
-{ "fstw", 0x78000000, 0xfc00c000, "cJfE,d(b)", pa20, FLAG_STRICT},
-{ "fstw", 0x78000000, 0xfc000000, "cJfE,d(s,b)", pa20, FLAG_STRICT},
-{ "fstd", 0x2c000200, 0xfc00dfc0, "cXft,x(b)", pa10, FLAG_STRICT},
-{ "fstd", 0x2c000200, 0xfc001fc0, "cXft,x(s,b)", pa10, FLAG_STRICT},
-{ "fstd", 0x2c000200, 0xfc00d3c0, "cxcCft,x(b)", pa11, FLAG_STRICT},
-{ "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa11, FLAG_STRICT},
-{ "fstd", 0x2c001220, 0xfc1ff3e0, "cocCft,@(b)", pa20, FLAG_STRICT},
-{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(s,b)", pa20, FLAG_STRICT},
-{ "fstd", 0x2c001200, 0xfc00dfc0, "cMft,5(b)", pa10, FLAG_STRICT},
-{ "fstd", 0x2c001200, 0xfc001fc0, "cMft,5(s,b)", pa10, FLAG_STRICT},
-{ "fstd", 0x2c001200, 0xfc00d3c0, "cmcCft,5(b)", pa11, FLAG_STRICT},
-{ "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa11, FLAG_STRICT},
-{ "fstd", 0x70000002, 0xfc000002, "cqfx,&(b)", pa20w, FLAG_STRICT},
-{ "fstd", 0x70000002, 0xfc00c002, "cqfx,#(b)", pa20, FLAG_STRICT},
-{ "fstd", 0x70000002, 0xfc000002, "cqfx,#(s,b)", pa20, FLAG_STRICT},
-{ "fldwx", 0x24000000, 0xfc00df80, "cXx(b),fT", pa10, FLAG_STRICT},
-{ "fldwx", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, FLAG_STRICT},
-{ "fldwx", 0x24000000, 0xfc00d380, "cxccx(b),fT", pa11, FLAG_STRICT},
-{ "fldwx", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa11, FLAG_STRICT},
-{ "fldwx", 0x24000000, 0xfc00df80, "cXx(b),fT", pa10, 0},
-{ "fldwx", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, 0},
-{ "flddx", 0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, FLAG_STRICT},
-{ "flddx", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, FLAG_STRICT},
-{ "flddx", 0x2c000000, 0xfc00d3c0, "cxccx(b),ft", pa11, FLAG_STRICT},
-{ "flddx", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa11, FLAG_STRICT},
-{ "flddx", 0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, 0},
-{ "flddx", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, 0},
-{ "fstwx", 0x24000200, 0xfc00df80, "cxfT,x(b)", pa10, FLAG_STRICT},
-{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, FLAG_STRICT},
-{ "fstwx", 0x24000200, 0xfc00d380, "cxcCfT,x(b)", pa11, FLAG_STRICT},
-{ "fstwx", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa11, FLAG_STRICT},
-{ "fstwx", 0x24000200, 0xfc00df80, "cxfT,x(b)", pa10, 0},
-{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, 0},
-{ "fstdx", 0x2c000200, 0xfc00dfc0, "cxft,x(b)", pa10, FLAG_STRICT},
-{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, FLAG_STRICT},
-{ "fstdx", 0x2c000200, 0xfc00d3c0, "cxcCft,x(b)", pa11, FLAG_STRICT},
-{ "fstdx", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa11, FLAG_STRICT},
-{ "fstdx", 0x2c000200, 0xfc00dfc0, "cxft,x(b)", pa10, 0},
-{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0},
-{ "fstqx", 0x3c000200, 0xfc00dfc0, "cxft,x(b)", pa10, 0},
-{ "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0},
-{ "fldws", 0x24001000, 0xfc00df80, "cm5(b),fT", pa10, FLAG_STRICT},
-{ "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, FLAG_STRICT},
-{ "fldws", 0x24001000, 0xfc00d380, "cmcc5(b),fT", pa11, FLAG_STRICT},
-{ "fldws", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa11, FLAG_STRICT},
-{ "fldws", 0x24001000, 0xfc00df80, "cm5(b),fT", pa10, 0},
-{ "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, 0},
-{ "fldds", 0x2c001000, 0xfc00dfc0, "cm5(b),ft", pa10, FLAG_STRICT},
-{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, FLAG_STRICT},
-{ "fldds", 0x2c001000, 0xfc00d3c0, "cmcc5(b),ft", pa11, FLAG_STRICT},
-{ "fldds", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa11, FLAG_STRICT},
-{ "fldds", 0x2c001000, 0xfc00dfc0, "cm5(b),ft", pa10, 0},
-{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, 0},
-{ "fstws", 0x24001200, 0xfc00df80, "cmfT,5(b)", pa10, FLAG_STRICT},
-{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, FLAG_STRICT},
-{ "fstws", 0x24001200, 0xfc00d380, "cmcCfT,5(b)", pa11, FLAG_STRICT},
-{ "fstws", 0x24001200, 0xfc001380, "cmcCfT,5(s,b)", pa11, FLAG_STRICT},
-{ "fstws", 0x24001200, 0xfc00df80, "cmfT,5(b)", pa10, 0},
-{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, 0},
-{ "fstds", 0x2c001200, 0xfc00dfc0, "cmft,5(b)", pa10, FLAG_STRICT},
-{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, FLAG_STRICT},
-{ "fstds", 0x2c001200, 0xfc00d3c0, "cmcCft,5(b)", pa11, FLAG_STRICT},
-{ "fstds", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa11, FLAG_STRICT},
-{ "fstds", 0x2c001200, 0xfc00dfc0, "cmft,5(b)", pa10, 0},
-{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0},
-{ "fstqs", 0x3c001200, 0xfc00dfc0, "cmft,5(b)", pa10, 0},
-{ "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0},
-{ "fadd", 0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
-{ "fadd", 0x38000600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
-{ "fsub", 0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
-{ "fsub", 0x38002600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
-{ "fmpy", 0x30004600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
-{ "fmpy", 0x38004600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
-{ "fdiv", 0x30006600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
-{ "fdiv", 0x38006600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
-{ "fsqrt", 0x30008000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
-{ "fsqrt", 0x38008000, 0xfc1fe720, "FfA,fT", pa10, 0},
-{ "fabs", 0x30006000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
-{ "fabs", 0x38006000, 0xfc1fe720, "FfA,fT", pa10, 0},
-{ "frem", 0x30008600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
-{ "frem", 0x38008600, 0xfc00e720, "FfA,fB,fT", pa10, 0},
-{ "frnd", 0x3000a000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
-{ "frnd", 0x3800a000, 0xfc1fe720, "FfA,fT", pa10, 0},
-{ "fcpy", 0x30004000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
-{ "fcpy", 0x38004000, 0xfc1fe720, "FfA,fT", pa10, 0},
-{ "fcnvff", 0x30000200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
-{ "fcnvff", 0x38000200, 0xfc1f8720, "FGfA,fT", pa10, 0},
-{ "fcnvxf", 0x30008200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
-{ "fcnvxf", 0x38008200, 0xfc1f8720, "FGfA,fT", pa10, 0},
-{ "fcnvfx", 0x30010200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
-{ "fcnvfx", 0x38010200, 0xfc1f8720, "FGfA,fT", pa10, 0},
-{ "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
-{ "fcnvfxt", 0x38018200, 0xfc1f8720, "FGfA,fT", pa10, 0},
-{ "fmpyfadd", 0xb8000000, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT},
-{ "fmpynfadd", 0xb8000020, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT},
-{ "fneg", 0x3000c000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT},
-{ "fneg", 0x3800c000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT},
-{ "fnegabs", 0x3000e000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT},
-{ "fnegabs", 0x3800e000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT},
-{ "fcnv", 0x30000200, 0xfc1c0720, "{_fa,fT", pa20, FLAG_STRICT},
-{ "fcnv", 0x38000200, 0xfc1c0720, "FGfA,fT", pa20, FLAG_STRICT},
-{ "fcmp", 0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10, FLAG_STRICT},
-{ "fcmp", 0x38000400, 0xfc00e720, "I?ffA,fB", pa10, FLAG_STRICT},
-{ "fcmp", 0x30000400, 0xfc0007e0, "F?ffa,fb,h", pa20, FLAG_STRICT},
-{ "fcmp", 0x38000400, 0xfc000720, "I?ffA,fB,h", pa20, FLAG_STRICT},
-{ "fcmp", 0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10, 0},
-{ "fcmp", 0x38000400, 0xfc00e720, "I?ffA,fB", pa10, 0},
-{ "xmpyu", 0x38004700, 0xfc00e720, "fX,fB,fT", pa11, 0},
-{ "fmpyadd", 0x18000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0},
-{ "fmpysub", 0x98000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0},
-{ "ftest", 0x30002420, 0xffffffff, "", pa10, FLAG_STRICT},
-{ "ftest", 0x30002420, 0xffffffe0, ",=", pa20, FLAG_STRICT},
-{ "ftest", 0x30000420, 0xffff1fff, "m", pa20, FLAG_STRICT},
-{ "fid", 0x30000000, 0xffffffff, "", pa11, 0},
-
-/* Performance Monitor Instructions. */
-
-{ "pmdis", 0x30000280, 0xffffffdf, "N", pa20, FLAG_STRICT},
-{ "pmenb", 0x30000680, 0xffffffff, "", pa20, FLAG_STRICT},
-
-/* Assist Instructions. */
-
-{ "spop0", 0x10000000, 0xfc000600, "v,ON", pa10, 0},
-{ "spop1", 0x10000200, 0xfc000600, "v,oNt", pa10, 0},
-{ "spop2", 0x10000400, 0xfc000600, "v,1Nb", pa10, 0},
-{ "spop3", 0x10000600, 0xfc000600, "v,0Nx,b", pa10, 0},
-{ "copr", 0x30000000, 0xfc000000, "u,2N", pa10, 0},
-{ "cldw", 0x24000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT},
-{ "cldw", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT},
-{ "cldw", 0x24000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT},
-{ "cldw", 0x24000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT},
-{ "cldw", 0x24001000, 0xfc00d200, "ucocc@(b),t", pa20, FLAG_STRICT},
-{ "cldw", 0x24001000, 0xfc001200, "ucocc@(s,b),t", pa20, FLAG_STRICT},
-{ "cldw", 0x24001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT},
-{ "cldw", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT},
-{ "cldw", 0x24001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT},
-{ "cldw", 0x24001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT},
-{ "cldd", 0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT},
-{ "cldd", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT},
-{ "cldd", 0x2c000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT},
-{ "cldd", 0x2c000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT},
-{ "cldd", 0x2c001000, 0xfc00d200, "ucocc@(b),t", pa20, FLAG_STRICT},
-{ "cldd", 0x2c001000, 0xfc001200, "ucocc@(s,b),t", pa20, FLAG_STRICT},
-{ "cldd", 0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT},
-{ "cldd", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT},
-{ "cldd", 0x2c001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT},
-{ "cldd", 0x2c001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT},
-{ "cstw", 0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT},
-{ "cstw", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT},
-{ "cstw", 0x24000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT},
-{ "cstw", 0x24000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT},
-{ "cstw", 0x24001200, 0xfc00d200, "ucocCt,@(b)", pa20, FLAG_STRICT},
-{ "cstw", 0x24001200, 0xfc001200, "ucocCt,@(s,b)", pa20, FLAG_STRICT},
-{ "cstw", 0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT},
-{ "cstw", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT},
-{ "cstw", 0x24001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT},
-{ "cstw", 0x24001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT},
-{ "cstd", 0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT},
-{ "cstd", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT},
-{ "cstd", 0x2c000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT},
-{ "cstd", 0x2c000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT},
-{ "cstd", 0x2c001200, 0xfc00d200, "ucocCt,@(b)", pa20, FLAG_STRICT},
-{ "cstd", 0x2c001200, 0xfc001200, "ucocCt,@(s,b)", pa20, FLAG_STRICT},
-{ "cstd", 0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT},
-{ "cstd", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT},
-{ "cstd", 0x2c001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT},
-{ "cstd", 0x2c001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT},
-{ "cldwx", 0x24000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT},
-{ "cldwx", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT},
-{ "cldwx", 0x24000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT},
-{ "cldwx", 0x24000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT},
-{ "cldwx", 0x24000000, 0xfc00de00, "ucXx(b),t", pa10, 0},
-{ "cldwx", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0},
-{ "clddx", 0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT},
-{ "clddx", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT},
-{ "clddx", 0x2c000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT},
-{ "clddx", 0x2c000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT},
-{ "clddx", 0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, 0},
-{ "clddx", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0},
-{ "cstwx", 0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT},
-{ "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT},
-{ "cstwx", 0x24000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT},
-{ "cstwx", 0x24000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT},
-{ "cstwx", 0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, 0},
-{ "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0},
-{ "cstdx", 0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT},
-{ "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT},
-{ "cstdx", 0x2c000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT},
-{ "cstdx", 0x2c000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT},
-{ "cstdx", 0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, 0},
-{ "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0},
-{ "cldws", 0x24001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT},
-{ "cldws", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT},
-{ "cldws", 0x24001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT},
-{ "cldws", 0x24001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT},
-{ "cldws", 0x24001000, 0xfc00de00, "ucM5(b),t", pa10, 0},
-{ "cldws", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0},
-{ "cldds", 0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT},
-{ "cldds", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT},
-{ "cldds", 0x2c001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT},
-{ "cldds", 0x2c001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT},
-{ "cldds", 0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, 0},
-{ "cldds", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0},
-{ "cstws", 0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT},
-{ "cstws", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT},
-{ "cstws", 0x24001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT},
-{ "cstws", 0x24001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT},
-{ "cstws", 0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, 0},
-{ "cstws", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0},
-{ "cstds", 0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT},
-{ "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT},
-{ "cstds", 0x2c001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT},
-{ "cstds", 0x2c001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT},
-{ "cstds", 0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, 0},
-{ "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0},
-
-/* More pseudo instructions which must follow the main table. */
-{ "call", 0xe800f000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT},
-{ "call", 0xe800a000, 0xffe0e000, "nW", pa10, FLAG_STRICT},
-{ "ret", 0xe840d000, 0xfffffffd, "n", pa20, FLAG_STRICT},
-
-};
-
-#define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0]))
-
-/* SKV 12/18/92. Added some denotations for various operands. */
-
-#define PA_IMM11_AT_31 'i'
-#define PA_IMM14_AT_31 'j'
-#define PA_IMM21_AT_31 'k'
-#define PA_DISP12 'w'
-#define PA_DISP17 'W'
-
-#define N_HPPA_OPERAND_FORMATS 5
hppa.h
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: ChangeLog-9103
===================================================================
--- ChangeLog-9103 (revision 816)
+++ ChangeLog-9103 (nonexistent)
@@ -1,3121 +0,0 @@
-2005-04-13 H.J. Lu
-
- 2003-11-18 Maciej W. Rozycki
- * mips.h: Define new enum members, M_LCA_AB and M_DLCA_AB.
-
- 2003-04-04 Svein E. Seldal
- * tic4x.h: Namespace cleanup. Replace s/c4x/tic4x
-
- 2002-11-16 Klee Dienes
- * m88k.h (INSTAB): Remove 'next' field.
- (instruction): Remove definition; replace with extern declaration
- and mark as const.
-
- 2002-08-28 Michael Hayes
- * tic4x.h: New file.
-
- 2002-07-25 Richard Sandiford
- * mips.h (CPU_R2000): Remove.
-
-2003-10-21 Peter Barada
- Bernardo Innocenti
-
- * m68k.h: Add MCFv4/MCF5528x support.
-
-2003-10-19 Hans-Peter Nilsson
-
- * mmix.h (JMP_INSN_BYTE): Define.
-
-2003-09-30 Chris Demetriou
-
- * mips.h: Document +E, +F, +G, +H, and +I operand types.
- Update documentation of I, +B and +C operand types.
- (INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
- (M_DEXT, M_DINS): New enum values.
-
-2003-09-04 Nick Clifton
-
- * v850.h (PROCESSOR_V850E1): Define.
-
-2003-08-19 Alan Modra
-
- * ppc.h (PPC_OPCODE_440): Define. Formatting. Use hex for other
- PPC_OPCODE_* defines.
-
-2003-08-16 Jason Eckhardt
-
- * i860.h (fmov.ds): Expand as famov.ds.
- (fmov.sd): Expand as famov.sd.
- (pfmov.ds): Expand as pfamov.ds.
-
-2003-08-07 Michael Meissner
-
- * cgen.h: Remove PARAM macro usage in all prototypes.
- (CGEN_EXTRACT_INFO): Use void * instead of PTR.
- (cgen_print_fn): Ditto.
- (CGEN_HW_ENTRY): Ditto.
- (CGEN_MAYBE_MULTI_IFLD): Ditto.
- (struct cgen_insn): Ditto.
- (CGEN_CPU_TABLE): Ditto.
-
-2003-08-07 Alan Modra
-
- * alpha.h: Remove PARAMS macro.
- * arc.h: Likewise.
- * d10v.h: Likewise.
- * d30v.h: Likewise.
- * i370.h: Likewise.
- * or32.h: Likewise.
- * pj.h: Likewise.
- * ppc.h: Likewise.
- * sparc.h: Likewise.
- * tic80.h: Likewise.
- * v850.h: Likewise.
-
-2003-07-18 Michael Snyder
-
- * include/opcode/h8sx.h (DO_MOVA1, DO_MOVA2): Reformatting.
-
-2003-07-15 Richard Sandiford
-
- * mips.h (CPU_RM7000): New macro.
- (OPCODE_IS_MEMBER): Match CPU_RM7000 against 4650 insns.
-
-2003-07-09 Alexandre Oliva
-
- 2000-04-01 Alexandre Oliva
- * mn10300.h (AM33_2): Renamed from AM33.
- 2000-03-31 Alexandre Oliva
- * mn10300.h (AM332, FMT_D3): Defined.
- (MN10300_OPERAND_FSREG, MN10300_OPERAND_FDREG): Likewise.
- (MN10300_OPERAND_FPCR): Likewise.
-
-2003-07-01 Martin Schwidefsky
-
- * s390.h (s390_opcode_cpu_val): Add enum for cpu type z990.
-
-2003-06-25 Richard Sandiford
-
- * h8300.h (IMM2_NS, IMM8_NS, IMM16_NS): Remove.
- (IMM8U, IMM8U_NS): Define.
- (h8_opcodes): Use IMM8U_NS for mov.[wl] #xx:8,@yy.
-
-2003-06-25 Richard Sandiford
-
- * h8300.h (h8_opcodes): Fix the mov.l @(dd:32,ERs),ERd and
- mov.l ERs,@(dd:32,ERd) entries.
-
-2003-06-23 H.J. Lu
-
- * i386.h (i386_optab): Support Intel Precott New Instructions.
-
-2003-06-10 Gary Hade
-
- * ppc.h (PPC_OPERAND_DQ): Define.
-
-2003-06-10 Richard Sandiford
-
- * h8300.h (IMM4_NS, IMM8_NS): New.
- (h8_opcodes): Replace IMM4 with IMM4_NS in mov.b and mov.w entries.
- Likewise IMM8 for mov.w and mov.l. Likewise IMM16U for mov.l.
-
-2003-06-03 Michael Snyder
-
- * h8300.h (enum h8_model): Add AV_H8S to distinguish from H8H.
- (ldc): Split ccr ops from exr ops (which are only available
- on H8S or H8SX).
- (stc): Ditto.
- (andc, orc, xorc): Ditto.
- (ldmac, stmac, clrmac, mac): Change access to AV_H8S.
-
-2003-06-03 Michael Snyder
- and Bernd Schmidt
- and Alexandre Oliva
- * h8300.h: Add support for h8300sx instruction set.
-
-2003-05-23 Jason Eckhardt
-
- * i860.h (expand_type): Add XP_ONLY.
- (scyc.b): New XP instruction.
- (ldio.l): Likewise.
- (ldio.s): Likewise.
- (ldio.b): Likewise.
- (ldint.l): Likewise.
- (ldint.s): Likewise.
- (ldint.b): Likewise.
- (stio.l): Likewise.
- (stio.s): Likewise.
- (stio.b): Likewise.
- (pfld.q): Likewise.
-
-2003-05-20 Jason Eckhardt
-
- * i860.h (flush): Set lower 3 bits properly and use 'L'
- for the immediate operand type instead of 'i'.
-
-2003-05-20 Jason Eckhardt
-
- * i860.h (fzchks): Both S and R bits must be set.
- (pfzchks): Likewise.
- (faddp): Likewise.
- (pfaddp): Likewise.
- (fix.ss): Remove (invalid instruction).
- (pfix.ss): Likewise.
- (ftrunc.ss): Likewise.
- (pftrunc.ss): Likewise.
-
-2003-05-18 Jason Eckhardt
-
- * i860.h (form, pform): Add missing .dd suffix.
-
-2003-05-13 Stephane Carrez
-
- * m68hc11.h (M68HC12_BANK_VIRT): Define to 0x010000
-
-2003-04-07 Michael Snyder
-
- * h8300.h (ldc/stc): Fix up src/dst swaps.
-
-2003-04-09 J. Grant
-
- * mips.h: Correct comment typo.
-
-2003-03-21 Martin Schwidefsky
-
- * s390.h (s390_opcode_arch_val): Rename to s390_opcode_mode_val.
- (S390_OPCODE_ESAME): Rename to S390_OPCODE_ZARCH.
- (s390_opcode): Remove architecture. Add modes and min_cpu.
-
-2003-03-17 D.Venkatasubramanian
-
- * h8300.h (O_SYS_CMDLINE): New pseudo opcode for command line
- processing.
-
-2003-02-21 Noida D.Venkatasubramanian
-
- * h8300.h (ldmac, stmac): Replace MACREG with MS32 and MD32.
-
-2003-01-23 Alan Modra
-
- * m68hc11.h (cpu6812s): Define.
-
-2003-01-07 Chris Demetriou
-
- * mips.h: Fix missing space in comment.
- (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, INSN_ISA5)
- (INSN_ISA32, INSN_ISA32R2, INSN_ISA64): Shift values right
- by four bits.
-
-2003-01-02 Chris Demetriou
-
- * mips.h: Update copyright years to include 2002 (which had
- been missed previously) and 2003. Make comments about "+A",
- "+B", and "+C" operand types more descriptive.
-
-2002-12-31 Chris Demetriou
-
- * mips.h: Note that the "+D" operand type name is now used.
-
-2002-12-30 Chris Demetriou
-
- * mips.h: Document "+" as the start of two-character operand
- type names, and add new "K", "+A", "+B", and "+C" operand types.
- (OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
- (OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
- defines.
-
-2002-12-24 Dmitry Diky
-
- * msp430.h: New file. Defines msp430 opcodes.
-
-2002-12-30 D.Venkatasubramanian
-
- * h8300.h: Added some more pseudo opcodes for system call
- processing.
-
-2002-12-19 Chris Demetriou
-
- * mips.h (OP_OP_COP0, OP_OP_COP1, OP_OP_COP2, OP_OP_COP3)
- (OP_OP_LWC1, OP_OP_LWC2, OP_OP_LWC3, OP_OP_LDC1, OP_OP_LDC2)
- (OP_OP_LDC3, OP_OP_SWC1, OP_OP_SWC2, OP_OP_SWC3, OP_OP_SDC1)
- (OP_OP_SDC2, OP_OP_SDC3): Define.
-
-2002-12-16 Alan Modra
-
- * hppa.h (completer_chars): #if 0 out.
-
- * ns32k.h (struct ns32k_opcode): Constify "name", "operands" and
- "default_args".
- (struct not_wot): Constify "args".
- (struct not): Constify "name".
- (numopcodes): Delete.
- (endop): Delete.
-
-2002-12-13 Alan Modra
-
- * pj.h (pj_opc_info_t): Add union.
-
-2002-12-04 David Mosberger
-
- * ia64.h: Fix copyright message.
- (IA64_OPND_AR_CSD): New operand kind.
-
-2002-12-03 Richard Henderson
-
- * ia64.h (enum ia64_opnd): Add IA64_OPND_LDXMOV.
-
-2002-12-03 Alan Modra
-
- * cgen.h (struct cgen_maybe_multi_ifield): Add "const PTR p" to union.
- Constify "leaf" and "multi".
-
-2002-11-19 Klee Dienes
-
- * h8300.h (h8_opcode): Remove 'noperands', 'idx', and 'size'
- fields.
- (h8_opcodes). Modify initializer and initializer macros to no
- longer initialize the removed fields.
-
-2002-11-19 Svein E. Seldal
-
- * tic4x.h (c4x_insts): Fixed LDHI constraint
-
-2002-11-18 Klee Dienes
-
- * h8300.h (h8_opcode): Remove 'length' field.
- (h8_opcodes): Mark as 'const' (both the declaration and
- definition). Modify initializer and initializer macros to no
- longer initialize the length field.
-
-2002-11-18 Klee Dienes
-
- * arc.h (arc_ext_opcodes): Declare as extern.
- (arc_ext_operands): Declare as extern.
- * i860.h (i860_opcodes): Declare as const.
-
-2002-11-18 Svein E. Seldal
-
- * tic4x.h: File reordering. Added enhanced opcodes.
-
-2002-11-16 Svein E. Seldal
-
- * tic4x.h: Major rewrite of entire file. Define instruction
- classes, and put each instruction into a class.
-
-2002-11-11 Svein E. Seldal
-
- * tic4x.h: Added new opcodes and corrected some bugs. Add support
- for new DSP types.
-
-2002-10-14 Alan Modra
-
- * cgen.h: Test __BFD_H_SEEN__ rather than BFD_VERSION_DATE.
-
-2002-09-30 Gavin Romig-Koch
- Ken Raeburn
- Aldy Hernandez
- Eric Christopher
- Richard Sandiford
-
- * mips.h: Update comment for new opcodes.
- (OP_MASK_VECBYTE, OP_SH_VECBYTE): New.
- (OP_MASK_VECALIGN, OP_SH_VECALIGN): New.
- (INSN_4111, INSN_4120, INSN_5400, INSN_5500): New.
- (CPU_VR4120, CPU_VR5400, CPU_VR5500): New.
- (OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags.
- Don't match CPU_R4111 with INSN_4100.
-
-2002-08-19 Elena Zannoni
-
- From matthew green
-
- * ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500
- instructions.
- (PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR,
- PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the
- e500x2 Integer select, branch locking, performance monitor,
- cache locking and machine check APUs, respectively.
- (PPC_OPCODE_EFS): New opcode type for efs* instructions.
- (PPC_OPCODE_CLASSIC): New opcode type for Classic PowerPC instructions.
-
-2002-08-13 Stephane Carrez
-
- * m68hc11.h (M6812_OP_PAGE): Define to identify call operand.
- (M68HC12_BANK_VIRT, M68HC12_BANK_MASK, M68HC12_BANK_BASE,
- M68HC12_BANK_SHIFT, M68HC12_BANK_PAGE_MASK): Define for 68HC12
- memory banks.
- (M6811_OC1M5, M6811_OC1M4, M6811_MODF): Fix value.
-
-2002-07-09 Thiemo Seufer
-
- * mips.h (INSN_MIPS16): New define.
-
-2002-07-08 Alan Modra
-
- * i386.h: Remove IgnoreSize from movsx and movzx.
-
-2002-06-08 Alan Modra
-
- * a29k.h: Replace CONST with const.
- (CONST): Don't define.
- * convex.h: Replace CONST with const.
- (CONST): Don't define.
- * dlx.h: Replace CONST with const.
- * or32.h (CONST): Don't define.
-
-2002-05-30 Chris G. Demetriou
-
- * mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
- (MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
- (MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
- (INSN_MDMX): New constants, for MDMX support.
- (opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
-
-2002-05-28 Kuang Hwa Lin
-
- * dlx.h: New file.
-
-2002-05-25 Alan Modra
-
- * ia64.h: Use #include "" instead of <> for local header files.
- * sparc.h: Likewise.
-
-2002-05-22 Thiemo Seufer
-
- * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
-
-2002-05-17 Andrey Volkov
-
- * h8300.h: Corrected defs of all control regs
- and eepmov instr.
-
-2002-04-11 Alan Modra
-
- * i386.h: Add intel mode cmpsd and movsd.
- Put them before SSE2 insns, so that rep prefix works.
-
-2002-03-15 Chris G. Demetriou
-
- * mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D
- instructions.
- (OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks
- may be passed along with the ISA bitmask.
-
-2002-03-05 Paul Koning
-
- * pdp11.h: Add format codes for float instruction formats.
-
-2002-02-25 Alan Modra
-
- * ppc.h (PPC_OPCODE_POWER4, PPC_OPCODE_NOPOWER4): Define.
-
-Mon Feb 18 17:31:48 CET 2002 Jan Hubicka
-
- * i386.h (push,pop): Fix Reg64 to WordReg to allow 16bit operands.
-
-Mon Feb 11 12:53:19 CET 2002 Jan Hubicka
-
- * i386.h (push,pop): Allow 16bit operands in 64bit mode.
- (xchg): Fix.
- (in, out): Disable 64bit operands.
- (call, jmp): Avoid REX prefixes.
- (jcxz): Prohibit in 64bit mode
- (jrcxz, loop): Add 64bit variants.
- (movq): Fix patterns.
- (movmskps, pextrw, pinstrw): Add 64bit variants.
-
-2002-01-31 Ivan Guzvinec
-
- * or32.h: New file.
-
-2002-01-22 Graydon Hoare
-
- * cgen.h (CGEN_MAYBE_MULTI_IFLD): New structure.
- (CGEN_OPERAND): Add CGEN_MAYBE_MULTI_IFLD field.
-
-2002-01-21 Thomas Klausner
-
- * h8300.h: Comment typo fix.
-
-2002-01-03 matthew green
-
- * ppc.h (PPC_OPCODE_BOOKE): BookE is not Motorola specific.
- (PPC_OPCODE_BOOKE64): Likewise.
-
-Mon Dec 31 16:45:41 2001 Jeffrey A Law (law@cygnus.com)
-
- * hppa.h (call, ret): Move to end of table.
- (addb, addib): PA2.0 variants should have been PA2.0W.
- (ldw, ldh, ldb, stw, sth, stb, stwa): Reorder to keep disassembler
- happy.
- (fldw, fldd, fstw, fstd, bb): Likewise.
- (short loads/stores): Tweak format specifier slightly to keep
- disassembler happy.
- (indexed loads/stores): Likewise.
- (absolute loads/stores): Likewise.
-
-2001-12-04 Alexandre Oliva
-
- * d10v.h (OPERAND_NOSP): New macro.
-
-2001-11-29 Alexandre Oliva
-
- * d10v.h (OPERAND_SP): New macro.
-
-2001-11-15 Alan Modra
-
- * ppc.h (struct powerpc_operand ): Add dialect param.
-
-2001-11-11 Timothy Wall
-
- * tic54x.h: Revise opcode layout; don't really need a separate
- structure for parallel opcodes.
-
-2001-11-13 Zack Weinberg
- Alan Modra
-
- * i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to
- accept WordReg.
-
-2001-11-04 Chris Demetriou
-
- * mips.h (OPCODE_IS_MEMBER): Remove extra space.
-
-2001-10-30 Hans-Peter Nilsson
-
- * mmix.h: New file.
-
-2001-10-18 Chris Demetriou
-
- * mips.h (OPCODE_IS_MEMBER): Add a no-op term to the end
- of the expression, to make source code merging easier.
-
-2001-10-17 Chris Demetriou
-
- * mips.h: Sort coprocessor instruction argument characters
- in comment, add a few more words of description for "H".
-
-2001-10-17 Chris Demetriou
-
- * mips.h (INSN_SB1): New cpu-specific instruction bit.
- (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1
- if cpu is CPU_SB1.
-
-2001-10-17 matthew green
-
- * ppc.h (PPC_OPCODE_BOOKE64): Fix typo.
-
-2001-10-12 matthew green
-
- * ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_BOOKE64, PPC_OPCODE_403): New
- opcode flags for BookE 32-bit, BookE 64-bit and PowerPC 403
- instructions, respectively.
-
-2001-09-27 Nick Clifton
-
- * v850.h: Remove spurious comment.
-
-2001-09-21 Nick Clifton
-
- * h8300.h: Fix compile time warning messages
-
-2001-09-04 Richard Henderson
-
- * alpha.h (struct alpha_operand): Pack elements into bitfields.
-
-2001-08-31 Eric Christopher
-
- * mips.h: Remove CPU_MIPS32_4K.
-
-2001-08-27 Torbjorn Granlund
-
- * ppc.h (PPC_OPERAND_DS): Define.
-
-2001-08-25 Andreas Jaeger
-
- * d30v.h: Fix declaration of reg_name_cnt.
-
- * d10v.h: Fix declaration of d10v_reg_name_cnt.
-
- * arc.h: Add prototypes from opcodes/arc-opc.c.
-
-2001-08-16 Thiemo Seufer
-
- * mips.h (INSN_10000): Define.
- (OPCODE_IS_MEMBER): Check for INSN_10000.
-
-2001-08-10 Alan Modra
-
- * ppc.h: Revert 2001-08-08.
-
-2001-08-10 Richard Sandiford
-
- * mips.h (INSN_GP32): Remove.
- (OPCODE_IS_MEMBER): Remove gp32 parameter.
- (M_MOVE): New macro identifier.
-
-2001-08-08 Alan Modra
-
- 1999-10-25 Torbjorn Granlund
- * ppc.h (struct powerpc_operand): New field `reloc'.
-
-2001-08-01 Aldy Hernandez
-
- * mips.h (INSN_ISA_MASK): Nuke bits 12-15.
-
-2001-07-12 Jeff Johnston
-
- * cgen.h (CGEN_INSN): Add regex support.
- (build_insn_regex): Declare.
-
-2001-07-11 Frank Ch. Eigler
-
- * cgen.h (CGEN_MACH): Add insn_chunk_bitsize field.
- (cgen_cpu_desc): Ditto.
-
-2001-07-07 Ben Elliston
-
- * m88k.h: Clean up and reformat. Remove unused code.
-
-2001-06-14 Geoffrey Keating
-
- * cgen.h (cgen_keyword): Add nonalpha_chars field.
-
-2001-05-23 Thiemo Seufer
-
- * mips.h (CPU_R12000): Define.
-
-2001-05-23 John Healy
-
- * cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48.
-
-2001-05-15 Thiemo Seufer
-
- * mips.h (INSN_ISA_MASK): Define.
-
-2001-05-12 Alan Modra
-
- * i386.h (i386_optab): Second operand of cvtps2dq is an xmm reg,
- not an mmx reg. Swap xmm/mmx regs on both movdq2q and movq2dq,
- and use InvMem as these insns must have register operands.
-
-2001-05-04 Alan Modra
-
- * i386.h (i386_optab): Move InvMem to first operand of pmovmskb
- and pextrw to swap reg/rm assignments.
-
-2001-04-05 Hans-Peter Nilsson
-
- * cris.h (enum cris_insn_version_usage): Correct comment for
- cris_ver_v3p.
-
-2001-03-24 Alan Modra
-
- * i386.h (i386_optab): Correct entry for "movntdq". Add "punpcklqdq".
- Add InvMem to first operand of "maskmovdqu".
-
-2001-03-22 Hans-Peter Nilsson
-
- * cris.h (ADD_PC_INCR_OPCODE): New macro.
-
-2001-03-21 Kazu Hirata
-
- * h8300.h: Fix formatting.
-
-2001-03-22 Alan Modra
-
- * i386.h (i386_optab): Add paddq, psubq.
-
-2001-03-19 Alan Modra
-
- * i386.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Define.
-
-2001-02-28 Igor Shevlyakov
-
- * m68k.h: new defines for Coldfire V4. Update mcf to know
- about mcf5407.
-
-2001-02-18 lars brinkhoff
-
- * pdp11.h: New file.
-
-2001-02-12 Jan Hubicka
-
- * i386.h (i386_optab): SSE integer converison instructions have
- 64bit versions on x86-64.
-
-2001-02-10 Nick Clifton
-
- * mips.h: Remove extraneous whitespace. Formating change to allow
- for future contribution.
-
-2001-02-09 Martin Schwidefsky
-
- * s390.h: New file.
-
-2001-02-02 Patrick Macdonald
-
- * cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short.
- (CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES.
- (CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS.
-
-2001-01-24 Karsten Keil
-
- * i386.h (i386_optab): Fix swapgs
-
-2001-01-14 Alan Modra
-
- * hppa.h: Describe new '<' and '>' operand types, and tidy
- existing comments.
- (pa_opcodes): Add entries for missing wide mode ldi,ldo,ldw,stw.
- Remove duplicate "ldw j(s,b),x". Sort some entries.
-
-2001-01-13 Jan Hubicka
-
- * i386.h (i386_optab): Fix pusha and ret templates.
-
-2001-01-11 Peter Targett
-
- * arc.h (ARC_MACH_5, ARC_MACH_6, ARC_MACH_7, ARC_MACH_8): New
- definitions for masking cpu type.
- (arc_ext_operand_value) New structure for storing extended
- operands.
- (ARC_OPERAND_*) Flags for operand values.
-
-2001-01-10 Jan Hubicka
-
- * i386.h (pinsrw): Add.
- (pshufw): Remove.
- (cvttpd2dq): Fix operands.
- (cvttps2dq): Likewise.
- (movq2q): Rename to movdq2q.
-
-2001-01-10 Richard Schaal
-
- * i386.h: Correct movnti instruction.
-
-2001-01-09 Jeff Johnston
-
- * cgen.h (CGEN_SYNTAX_CHAR_TYPE): New typedef based on max number
- of operands (unsigned char or unsigned short).
- (CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE.
- (CGEN_SYNTAX_CHAR): Changed to cast to unsigned char.
-
-2001-01-05 Jan Hubicka
-
- * i386.h (i386_optab): Make [sml]fence template to use immext field.
-
-2001-01-03 Jan Hubicka
-
- * i386.h (i386_optab): Fix 64bit pushf template; Add instructions
- introduced by Pentium4
-
-2000-12-30 Jan Hubicka
-
- * i386.h (i386_optab): Add "rex*" instructions;
- add swapgs; disable jmp/call far direct instructions for
- 64bit mode; add syscall and sysret; disable registers for 0xc6
- template. Add 'q' suffixes to extendable instructions, disable
- obsolete instructions, add new sign/zero extension ones.
- (i386_regtab): Add extended registers.
- (*Suf): Add No_qSuf.
- (q_Suf, wlq_Suf, bwlq_Suf): New.
-
-2000-12-20 Jan Hubicka
-
- * i386.h (i386_optab): Replace "Imm" with "EncImm".
- (i386_regtab): Add flags field.
-
-2000-12-12 Nick Clifton
-
- * mips.h: Fix formatting.
-
-2000-12-01 Chris Demetriou
-
- mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete.
- (OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old
- OP_*_SYSCALL definitions.
- (OP_SH_CODE19, OP_MASK_CODE19): Define, for use as
- 19 bit wait codes.
- (MIPS operand specifier comments): Remove 'm', add 'U' and
- 'J', and update the meaning of 'B' so that it's more general.
-
- * mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4,
- INSN_ISA5): Renumber, redefine to mean the ISA at which the
- instruction was added.
- (INSN_ISA32): New constant.
- (INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32):
- Renumber to avoid new and/or renumbered INSN_* constants.
- (INSN_MIPS32): Delete.
- (ISA_UNKNOWN): New constant to indicate unknown ISA.
- (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5,
- ISA_MIPS32): New constants, defined to be the mask of INSN_*
- constants available at that ISA level.
- (CPU_UNKNOWN): New constant to indicate unknown CPU.
- (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter,
- define it with a unique value.
- (OPCODE_IS_MEMBER): Update for new ISA membership-related
- constant meanings.
-
- * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New
- definitions.
-
- * mips.h (CPU_SB1): New constant.
-
-2000-10-20 Jakub Jelinek
-
- * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
- Note that '3' is used for siam operand.
-
-2000-09-22 Jim Wilson
-
- * ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP.
-
-2000-09-13 Anders Norlander
-
- * mips.h: Use defines instead of hard-coded processor numbers.
- (CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010,
- CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650,
- CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K,
- CPU_4KC, CPU_4KM, CPU_4KP): Define..
- (OPCODE_IS_MEMBER): Use new defines.
- (OP_MASK_SEL, OP_SH_SEL): Define.
- (OP_MASK_CODE20, OP_SH_CODE20): Define.
- Add 'P' to used characters.
- Use 'H' for coprocessor select field.
- Use 'm' for 20 bit breakpoint code.
- Document new arg characters and add to used characters.
- (INSN_MIPS32): New define for MIPS32 extensions.
- (OPCODE_IS_MEMBER): Recognize MIPS32 instructions.
-
-2000-09-05 Alan Modra
-
- * hppa.h: Mention cz completer.
-
-2000-08-16 Jim Wilson
-
- * ia64.h (IA64_OPCODE_POSTINC): New.
-
-2000-08-15 H.J. Lu
-
- * i386.h: Swap the Intel syntax "movsx"/"movzx" due to the
- IgnoreSize change.
-
-2000-08-08 Jason Eckhardt
-
- * i860.h: Small formatting adjustments.
-
-2000-07-29 Marek Michalkiewicz
-
- * avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros.
- Move related opcodes closer to each other.
- Minor changes in comments, list undefined opcodes.
-
-2000-07-26 Dave Brolley
-
- * cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned.
-
-2000-07-22 Jason Eckhardt
-
- * i860.h (btne, bte, bla): Changed these opcodes
- to use sbroff ('r') instead of split16 ('s').
- (J, K, L, M): New operand types for 16-bit aligned fields.
- (ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to
- use I, J, K, L, M instead of just I.
- (T, U): New operand types for split 16-bit aligned fields.
- (st.x): Changed these opcodes to use S, T, U instead of just S.
- (andh, andnoth, orh, xorh): Deleted 3-register forms as they do not
- exist on the i860.
- (pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860.
- (pfeq.ss, pfeq.dd): New opcodes.
- (st.s): Fixed incorrect mask bits.
- (fmlow): Fixed incorrect mask bits.
- (fzchkl, pfzchkl): Fixed incorrect mask bits.
- (faddz, pfaddz): Fixed incorrect mask bits.
- (form, pform): Fixed incorrect mask bits.
- (pfld.l): Fixed incorrect mask bits.
- (fst.q): Fixed incorrect mask bits.
- (all floating point opcodes): Fixed incorrect mask bits for
- handling of dual bit.
-
-2000-07-20 Hans-Peter Nilsson
-
- cris.h: New file.
-
-2000-06-26 Marek Michalkiewicz
-
- * avr.h (AVR_ISA_WRAP): Remove, now assumed if not AVR_ISA_MEGA.
- (AVR_ISA_ESPM): Remove, because ESPM removed in databook update.
- (AVR_ISA_85xx): Remove, all uses changed back to AVR_ISA_2xxx.
- (AVR_ISA_M83): Define for ATmega83, ATmega85.
- (espm): Remove, because ESPM removed in databook update.
- (eicall, eijmp): Move to the end of opcode table.
-
-2000-06-18 Stephane Carrez
-
- * m68hc11.h: New file for support of Motorola 68hc11.
-
-Fri Jun 9 21:51:50 2000 Denis Chertykov
-
- * avr.h: clr,lsl,rol, ... moved after add,adc, ...
-
-Wed Jun 7 21:39:54 2000 Denis Chertykov
-
- * avr.h: New file with AVR opcodes.
-
-Wed Apr 12 17:11:20 2000 Donald Lindsay
-
- * d10v.h: added ALONE attribute for d10v_opcode.exec_type.
-
-2000-05-23 Maciej W. Rozycki
-
- * i386.h: Allow d suffix on iret, and add DefaultSize modifier.
-
-2000-05-17 Maciej W. Rozycki
-
- * i386.h: Use sl_FP, not sl_Suf for fild.
-
-2000-05-16 Frank Ch. Eigler
-
- * cgen.h (CGEN_MAX_SYNTAX_BYTES): Increase to 32. Check that
- it exceeds CGEN_ACTUAL_MAX_SYNTAX_BYTES, if set.
- (CGEN_MAX_IFMT_OPERANDS): Increase to 16. Check that it exceeds
- CGEN_ACTUAL_MAX_IFMT_OPERANDS, if set.
-
-2000-05-13 Alan Modra ,
-
- * i386.h (i386_optab): Cpu686 for sysenter,sysexit,fxsave,fxrestore.
-
-2000-05-13 Alan Modra ,
- Alexander Sokolov
-
- * i386.h (i386_optab): Add cpu_flags for all instructions.
-
-2000-05-13 Alan Modra
-
- From Gavin Romig-Koch
- * i386.h (wld_Suf): Define. Use on pushf, popf, pusha, popa.
-
-2000-05-04 Timothy Wall
-
- * tic54x.h: New.
-
-2000-05-03 J.T. Conklin
-
- * ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit.
- (PPC_OPERAND_VR): New operand flag for vector registers.
-
-2000-05-01 Kazu Hirata
-
- * h8300.h (EOP): Add missing initializer.
-
-Fri Apr 21 15:03:37 2000 Jason Eckhardt
-
- * hppa.h (pa_opcodes): New opcodes for PA2.0 wide mode
- forms of ld/st{b,h,w,d} and fld/fst{w,d} (16-bit displacements).
- New operand types l,y,&,fe,fE,fx added to support above forms.
- (pa_opcodes): Replaced usage of 'x' as source/target for
- floating point double-word loads/stores with 'fx'.
-
-Fri Apr 21 13:20:53 2000 Richard Henderson
- David Mosberger
- Timothy Wall
- Jim Wilson
-
- * ia64.h: New file.
-
-2000-03-27 Nick Clifton
-
- * d30v.h (SHORT_A1): Fix value.
- (SHORT_AR): Renumber so that it is at the end of the list of short
- instructions, not the end of the list of long instructions.
-
-2000-03-26 Alan Modra
-
- * i386.h: (UNIXWARE_COMPAT): Rename to SYSV386_COMPAT as the
- problem isn't really specific to Unixware.
- (OLDGCC_COMPAT): Define.
- (i386_optab): If !OLDGCC_COMPAT, don't handle fsubp etc. with
- destination %st(0).
- Fix lots of comments.
-
-2000-03-02 J"orn Rennecke
-
- * d30v.h:
- (SHORT_B2r, SHORT_B3, SHORT_B3r, SHORT_B3b, SHORT_B3br): Updated.
- (SHORT_D1r, SHORT_D2, SHORT_D2r, SHORT_D2Br, SHORT_U): Updated.
- (SHORT_F, SHORT_AF, SHORT_T, SHORT_A5, SHORT_CMP, SHORT_CMPU): Updated.
- (SHORT_A1, SHORT_AA, SHORT_RA, SHORT_MODINC, SHORT_MODDEC): Updated.
- (SHORT_C1, SHORT_C2, SHORT_UF, SHORT_A2, SHORT_NONE, LONG): Updated.
- (LONG_U, LONG_Ur, LONG_CMP, LONG_M, LONG_M2, LONG_2, LONG_2r): Updated.
- (LONG_2b, LONG_2br, LONG_D, LONG_Dr, LONG_Dbr): Updated.
-
-2000-02-25 Alan Modra
-
- * i386.h (fild, fistp): Change intel d_Suf form to fildd and
- fistpd without suffix.
-
-2000-02-24 Nick Clifton
-
- * cgen.h (cgen_cpu_desc): Rename field 'flags' to
- 'signed_overflow_ok_p'.
- Delete prototypes for cgen_set_flags() and cgen_get_flags().
-
-2000-02-24 Andrew Haley
-
- * cgen.h (CGEN_INSN_MACH_HAS_P): New macro.
- (CGEN_CPU_TABLE): flags: new field.
- Add prototypes for new functions.
-
-2000-02-24 Alan Modra
-
- * i386.h: Add some more UNIXWARE_COMPAT comments.
-
-2000-02-23 Linas Vepstas
-
- * i370.h: New file.
-
-2000-02-22 Chandra Chavva
-
- * d30v.h (FLAG_NOT_WITH_ADDSUBppp): Redefined as operation
- cannot be combined in parallel with ADD/SUBppp.
-
-2000-02-22 Andrew Haley
-
- * mips.h: (OPCODE_IS_MEMBER): Add comment.
-
-1999-12-30 Andrew Haley
-
- * mips.h (OPCODE_IS_MEMBER): Add gp32 arg, which determines
- whether synthetic opcodes (e.g. move) generate 32-bit or 64-bit
- insns.
-
-2000-01-15 Alan Modra
-
- * i386.h: Qualify intel mode far call and jmp with x_Suf.
-
-1999-12-27 Alan Modra
-
- * i386.h: Add JumpAbsolute qualifier to all non-intel mode
- indirect jumps and calls. Add FF/3 call for intel mode.
-
-Wed Dec 1 03:05:25 1999 Jeffrey A Law (law@cygnus.com)
-
- * mn10300.h: Add new operand types. Add new instruction formats.
-
-Wed Nov 24 20:28:58 1999 Jeffrey A Law (law@cygnus.com)
-
- * hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb"
- instruction.
-
-1999-11-18 Gavin Romig-Koch
-
- * mips.h (INSN_ISA5): New.
-
-1999-11-01 Gavin Romig-Koch
-
- * mips.h (OPCODE_IS_MEMBER): New.
-
-1999-10-29 Nick Clifton
-
- * d30v.h (SHORT_AR): Define.
-
-1999-10-18 Michael Meissner
-
- * alpha.h (alpha_num_opcodes): Convert to unsigned.
- (alpha_num_operands): Ditto.
-
-Sun Oct 10 01:46:56 1999 Jerry Quinn
-
- * hppa.h (pa_opcodes): Add load and store cache control to
- instructions. Add ordered access load and store.
-
- * hppa.h (pa_opcode): Add new entries for addb and addib.
-
- * hppa.h (pa_opcodes): Fix cmpb and cmpib entries.
-
- * hppa.h (pa_opcodes): Add entries for cmpb and cmpib.
-
-Thu Oct 7 00:12:25 MDT 1999 Diego Novillo
-
- * d10v.h: Add flag RESTRICTED_NUM3 for imm3 operands.
-
-Thu Sep 23 07:08:38 1999 Jerry Quinn
-
- * hppa.h (pa_opcodes): Add "call" and "ret". Clean up "b", "bve"
- and "be" using completer prefixes.
-
- * hppa.h (pa_opcodes): Add initializers to silence compiler.
-
- * hppa.h: Update comments about character usage.
-
-Mon Sep 20 03:55:31 1999 Jeffrey A Law (law@cygnus.com)
-
- * hppa.h (pa_opcodes): Fix minor thinkos introduced while cleaning
- up the new fstw & bve instructions.
-
-Sun Sep 19 10:40:59 1999 Jeffrey A Law (law@cygnus.com)
-
- * hppa.h (pa_opcodes): Add remaining PA2.0 integer load/store
- instructions.
-
- * hppa.h (pa_opcodes): Add remaining PA2.0 FP load/store instructions.
-
- * hppa.h (pa_opcodes): Add long offset double word load/store
- instructions.
-
- * hppa.h (pa_opcodes): Add FLAG_STRICT variants of FP loads and
- stores.
-
- * hppa.h (pa_opcodes): Handle PA2.0 fcnv, fcmp and ftest insns.
-
- * hppa.h (pa_opcodes): Finish support for PA2.0 "b" instructions.
-
- * hppa.h (pa_opcodes): Handle PA2.0 "bve" instructions.
-
- * hppa.h (pa_opcodes): Add new syntax "be" instructions.
-
- * hppa.h (pa_opcodes): Note use of 'M' and 'L'.
-
- * hppa.h (pa_opcodes): Add support for "b,l".
-
- * hppa.h (pa_opcodes): Add support for "b,gate".
-
-Sat Sep 18 11:41:16 1999 Jeffrey A Law (law@cygnus.com)
-
- * hppa.h (pa_opcodes): Use 'fX' for first register operand
- in xmpyu.
-
- * hppa.h (pa_opcodes): Fix mask for probe and probei.
-
- * hppa.h (pa_opcodes): Fix mask for depwi.
-
-Tue Sep 7 13:44:25 1999 Jeffrey A Law (law@cygnus.com)
-
- * hppa.h (pa_opcodes): Add "addil" variant which has the %r1 as
- an explicit output argument.
-
-Mon Sep 6 04:41:42 1999 Jeffrey A Law (law@cygnus.com)
-
- * hppa.h: Add strict variants of PA1.0/PA1.1 loads and stores.
- Add a few PA2.0 loads and store variants.
-
-1999-09-04 Steve Chamberlain
-
- * pj.h: New file.
-
-1999-08-29 Alan Modra
-
- * i386.h (i386_regtab): Move %st to top of table, and split off
- other fp reg entries.
- (i386_float_regtab): To here.
-
-Sat Aug 28 00:25:25 1999 Jerry Quinn
-
- * hppa.h (pa_opcodes): Replace 'f' by 'v'. Prefix float register args
- by 'f'.
-
- * hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi.
- Add supporting args.
-
- * hppa.h: Document new completers and args.
- * hppa.h (pa_opcodes): Add 64 bit patterns and pa2.0 syntax for uxor,
- uaddcm, dcor, addi, add, sub, subi, shladd, rfi, and probe. Add pa2.0
- extensions for ssm, rsm, pdtlb, pitlb. Add performance instructions
- pmenb and pmdis.
-
- * hppa.h (pa_opcodes): Add pa2.0 instructions hadd, hshl,
- hshr, hsub, mixh, mixw, permh.
-
- * hppa.h (pa_opcodes): Change completers in instructions to
- use 'c' prefix.
-
- * hppa.h (pa_opcodes): Add popbts, new forms of bb, havg,
- hshladd, hshradd, shrpd, and shrpw instructions. Update arg comments.
-
- * hppa.h (pa_opcodes): Change fmpyfadd, fmpynfadd, fneg,
- fnegabs to use 'I' instead of 'F'.
-
-1999-08-21 Alan Modra
-
- * i386.h: Add AMD athlon instructions, pfnacc, pfpnacc, pswapd.
- Document pf2iw and pi2fw as athlon insns. Remove pswapw.
- Alphabetically sort PIII insns.
-
-Wed Aug 18 18:14:40 1999 Doug Evans
-
- * cgen.h (CGEN_INSN_MACH_HAS_P): New macro.
-
-Fri Aug 6 09:46:35 1999 Jerry Quinn
-
- * hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and,
- and andcm. Add 32 and 64 bit version of cmpclr, cmpiclr.
-
- * hppa.h: Document 64 bit condition completers.
-
-Thu Aug 5 16:56:07 1999 Jerry Quinn
-
- * hppa.h (pa_opcodes): Change condition args to use '?' prefix.
-
-1999-08-04 Alan Modra
-
- * i386.h (i386_optab): Add DefaultSize modifier to all insns
- that implicitly modify %esp. #undef d_Suf, x_suf, sld_suf,
- sldx_suf, bwld_Suf, d_FP, x_FP, sld_FP, sldx_FP at end of table.
-
-Wed Jul 28 02:04:24 1999 Jerry Quinn
- Jeff Law
-
- * hppa.h (pa_opcodes): Add "pushnom" and "pushbts".
-
- * hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT.
-
- * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd,
- and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'.
-
-1999-07-13 Alan Modra
-
- * i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw insns.
-
-Thu Jul 1 00:17:24 1999 Jeffrey A Law (law@cygnus.com)
-
- * hppa.h (struct pa_opcode): Add new field "flags".
- (FLAGS_STRICT): Define.
-
-Fri Jun 25 04:22:04 1999 Jerry Quinn
- Jeff Law
-
- * hppa.h (pa_opcodes): Add pa2.0 clrbts instruction.
-
- * hppa.h (pa_opcodes): Add entries for mfia and mtsarcm instructions.
-
-1999-06-23 Alan Modra
-
- * i386.h: Allow `l' suffix on bswap. Allow `w' suffix on arpl,
- lldt, lmsw, ltr, str, verr, verw. Add FP flag to fcmov*. Add FP
- flag to fcomi and friends.
-
-Fri May 28 15:26:11 1999 Jeffrey A Law (law@cygnus.com)
-
- * hppa.h (pa_opcodes): Move integer arithmetic instructions after
- integer logical instructions.
-
-1999-05-28 Linus Nordberg
-
- * m68k.h: Document new formats `E', `G', `H' and new places `N',
- `n', `o'.
-
- * m68k.h: Define mcf5206e, mcf5307, mcf. Document new format `u'
- and new places `m', `M', `h'.
-
-Thu May 27 04:13:54 1999 Joel Sherrill (joel@OARcorp.com
-
- * hppa.h (pa_opcodes): Add several processor specific system
- instructions.
-
-Wed May 26 16:57:44 1999 Jeffrey A Law (law@cygnus.com)
-
- * hppa.h (pa_opcodes): Add second entry for "comb", "comib",
- "addb", and "addib" to be used by the disassembler.
-
-1999-05-12 Alan Modra
-
- * i386.h (ReverseModrm): Remove all occurences.
- (InvMem): Add to control/debug/test mov insns, movhlps, movlhps,
- movmskps, pextrw, pmovmskb, maskmovq.
- Change NoSuf to FP on all MMX, XMM and AMD insns as these all
- ignore the data size prefix.
-
- * i386.h (i386_optab, i386_regtab): Add support for PIII SIMD.
- Mostly stolen from Doug Ledford
-
-Sat May 8 23:27:35 1999 Richard Henderson
-
- * ppc.h (PPC_OPCODE_64_BRIDGE): New.
-
-1999-04-14 Doug Evans
-
- * cgen.h (CGEN_ATTR): Delete member num_nonbools.
- (CGEN_ATTR_TYPE): Update.
- (CGEN_ATTR_MASK): Number booleans starting at 0.
- (CGEN_ATTR_VALUE): Update.
- (CGEN_INSN_ATTR): Update.
-
-Mon Apr 12 23:43:27 1999 Jeffrey A Law (law@cygnus.com)
-
- * hppa.h (fmpyfadd, fmpynfadd, fneg, fnegabs): New PA2.0
- instructions.
-
-Tue Mar 23 11:24:38 1999 Jeffrey A Law (law@cygnus.com)
-
- * hppa.h (bb, bvb): Tweak opcode/mask.
-
-
-1999-03-22 Doug Evans
-
- * cgen.h (CGEN_ISA,CGEN_MACH): New typedefs.
- (struct cgen_cpu_desc): Rename member mach to machs. New member isas.
- New members word_bitsize,default_insn_bitsize,base_insn-bitsize,
- min_insn_bitsize,max_insn_bitsize,isa_table,mach_table,rebuild_tables.
- Delete member max_insn_size.
- (enum cgen_cpu_open_arg): New enum.
- (cpu_open): Update prototype.
- (cpu_open_1): Declare.
- (cgen_set_cpu): Delete.
-
-1999-03-11 Doug Evans
-
- * cgen.h (CGEN_HW_TABLE): Delete `num_init_entries' member.
- (CGEN_OPERAND_NIL): New macro.
- (CGEN_OPERAND): New member `type'.
- (@arch@_cgen_operand_table): Delete decl.
- (CGEN_OPERAND_INDEX,CGEN_OPERAND_TYPE,CGEN_OPERAND_ENTRY): Delete.
- (CGEN_OPERAND_TABLE): New struct.
- (cgen_operand_lookup_by_name,cgen_operand_lookup_by_num): Declare.
- (CGEN_OPINST): Pointer to operand table entry replaced with enum.
- (CGEN_CPU_TABLE): New member `isa'. Change member `operand_table',
- now a CGEN_OPERAND_TABLE. Add CGEN_CPU_DESC arg to
- {get,set}_{int,vma}_operand.
- (@arch@_cgen_cpu_open): New arg `isa'.
- (cgen_set_cpu): Ditto.
-
-Fri Feb 26 02:36:45 1999 Richard Henderson
-
- * i386.h: Fill in cmov and fcmov alternates. Add fcomi short forms.
-
-1999-02-25 Doug Evans
-
- * cgen.h (enum cgen_asm_type): Add CGEN_ASM_NONE.
- (CGEN_HW_ENTRY): Delete member `next'. Change type of `type' to
- enum cgen_hw_type.
- (CGEN_HW_TABLE): New struct.
- (hw_table): Delete declaration.
- (CGEN_OPERAND): Change member hw to hw_type, change type from pointer
- to table entry to enum.
- (CGEN_OPINST): Ditto.
- (CGEN_CPU_TABLE): Change member hw_list to hw_table.
-
-Sat Feb 13 14:13:44 1999 Richard Henderson
-
- * alpha.h (AXP_OPCODE_EV6): New.
- (AXP_OPCODE_NOPAL): Include it.
-
-1999-02-09 Doug Evans
-
- * cgen.h (CGEN_CPU_DESC): Renamed from CGEN_OPCODE_DESC.
- All uses updated. New members int_insn_p, max_insn_size,
- parse_operand,insert_operand,extract_operand,print_operand,
- sizeof_fields,set_fields_bitsize,get_int_operand,set_int_operand,
- get_vma_operand,set_vma_operand,parse_handlers,insert_handlers,
- extract_handlers,print_handlers.
- (CGEN_ATTR): Change type of num_nonbools to unsigned int.
- (CGEN_ATTR_BOOL_OFFSET): New macro.
- (CGEN_ATTR_MASK): Subtract it to compute bit number.
- (CGEN_ATTR_VALUE): Redo bool/nonbool attr calculation.
- (cgen_opcode_handler): Renamed from cgen_base.
- (CGEN_HW_ATTR_VALUE): Renamed from CGEN_HW_ATTR, all uses updated.
- (CGEN_OPERAND_ATTR_VALUE): Renamed from CGEN_OPERAND_ATTR,
- all uses updated.
- (CGEN_OPERAND_INDEX): Rewrite to use table entry, not global.
- (enum cgen_opinst_type): Renamed from cgen_operand_instance_type.
- (CGEN_IFLD_ATTR_VALUE): Renamed from CGEN_IFLD_ATTR, all uses updated.
- (CGEN_OPCODE,CGEN_IBASE): New types.
- (CGEN_INSN): Rewrite.
- (CGEN_{ASM,DIS}_HASH*): Delete.
- (init_opcode_table,init_ibld_table): Declare.
- (CGEN_INSN_ATTR): New type.
-
-Mon Feb 1 21:09:14 1999 Catherine Moore
-
- * i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf): Define.
- (x_FP, d_FP, dls_FP, sldx_FP): Define.
- Change *Suf definitions to include x and d suffixes.
- (movsx): Use w_Suf and b_Suf.
- (movzx): Likewise.
- (movs): Use bwld_Suf.
- (fld): Change ordering. Use sld_FP.
- (fild): Add Intel Syntax equivalent of fildq.
- (fst): Use sld_FP.
- (fist): Use sld_FP.
- (fstp): Use sld_FP. Add x_FP version.
- (fistp): LLongMem version for Intel Syntax.
- (fcom, fcomp): Use sld_FP.
- (fadd, fiadd, fsub): Use sld_FP.
- (fsubr): Use sld_FP.
- (fmul, fimul, fdvi, fidiv, fdivr): Use sld_FP.
-
-1999-01-27 Doug Evans
-
- * cgen.h (enum cgen_mode): Add CGEN_MODE_TARGET_MAX, CGEN_MODE_INT,
- CGEN_MODE_UINT.
-
-1999-01-16 Jeffrey A Law (law@cygnus.com)
-
- * hppa.h (bv): Fix mask.
-
-1999-01-05 Doug Evans
-
- * cgen.h (CGEN_ATTR_VALUE_TYPE): New typedef.
- (CGEN_ATTR): Use it.
- (CGEN_ATTR_TYPE,CGEN_ATTR_ENTRY): Ditto.
- (CGEN_ATTR_TABLE): New member dfault.
-
-1998-12-30 Gavin Romig-Koch
-
- * mips.h (MIPS16_INSN_BRANCH): New.
-
-Wed Dec 9 10:38:48 1998 David Taylor
-
- The following is part of a change made by Edith Epstein
- as part of a project to merge in
- changes by HP; HP did not create ChangeLog entries.
-
- * hppa.h (completer_chars): list of chars to not put a space
- after.
-
-Sun Dec 6 13:21:34 1998 Ian Lance Taylor
-
- * i386.h (i386_optab): Permit w suffix on processor control and
- status word instructions.
-
-1998-11-30 Doug Evans
-
- * cgen.h (struct cgen_hw_entry): Delete const on attrs member.
- (struct cgen_keyword_entry): Ditto.
- (struct cgen_operand): Ditto.
- (CGEN_IFLD): New typedef, with associated access macros.
- (CGEN_IFMT): New typedef, with associated access macros.
- (CGEN_IFMT): Renamed from CGEN_FORMAT. New member `iflds'.
- (CGEN_IVALUE): New typedef.
- (struct cgen_insn): Delete const on syntax,attrs members.
- `format' now points to format data. Type of `value' is now
- CGEN_IVALUE.
- (struct cgen_opcode_table): New member ifld_table.
-
-1998-11-18 Doug Evans
-
- * cgen.h (cgen_extract_fn): Update type of `base_insn' arg.
- (CGEN_OPERAND_INSTANCE): New member `attrs'.
- (CGEN_OPERAND_INSTANCE_{ATTRS,ATTR}): New macros.
- (cgen_dis_lookup_insn): Update type of `base_insn' arg.
- (cgen_opcode_table): Update type of dis_hash fn.
- (extract_operand): Update type of `insn_value' arg.
-
-Thu Oct 29 11:38:36 1998 Doug Evans
-
- * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Delete.
-
-Tue Oct 27 08:57:59 1998 Gavin Romig-Koch
-
- * mips.h (INSN_MULT): Added.
-
-Tue Oct 20 11:31:34 1998 Alan Modra
-
- * i386.h (MAX_MNEM_SIZE): Rename from MAX_OPCODE_SIZE.
-
-Mon Oct 19 12:50:00 1998 Doug Evans
-
- * cgen.h (CGEN_INSN_INT): New typedef.
- (CGEN_INT_INSN_P): Renamed from CGEN_INT_INSN.
- (CGEN_INSN_BYTES): Renamed from cgen_insn_t.
- (CGEN_INSN_BYTES_PTR): New typedef.
- (CGEN_EXTRACT_INFO): New typedef.
- (cgen_insert_fn,cgen_extract_fn): Update.
- (cgen_opcode_table): New member `insn_endian'.
- (assemble_insn,lookup_insn,lookup_get_insn_operands): Update.
- (insert_operand,extract_operand): Update.
- (cgen_get_insn_value,cgen_put_insn_value): Add prototypes.
-
-Fri Oct 9 13:38:13 1998 Doug Evans
-
- * cgen.h (CGEN_ATTR_BOOLS): New macro.
- (struct CGEN_HW_ENTRY): New member `attrs'.
- (CGEN_HW_ATTR): New macro.
- (struct CGEN_OPERAND_INSTANCE): New member `name'.
- (CGEN_INSN_INVALID_P): New macro.
-
-Mon Oct 5 00:21:07 1998 Jeffrey A Law (law@cygnus.com)
-
- * hppa.h: Add "fid".
-
-Sun Oct 4 21:00:00 1998 Alan Modra
-
- From Robert Andrew Dale
- * i386.h (i386_optab): Add AMD 3DNow! instructions.
- (AMD_3DNOW_OPCODE): Define.
-
-Tue Sep 22 17:53:47 1998 Nick Clifton
-
- * d30v.h (EITHER_BUT_PREFER_MU): Define.
-
-Mon Aug 10 14:09:38 1998 Doug Evans
-
- * cgen.h (cgen_insn): #if 0 out element `cdx'.
-
-Mon Aug 3 12:21:57 1998 Doug Evans
-
- Move all global state data into opcode table struct, and treat
- opcode table as something that is "opened/closed".
- * cgen.h (CGEN_OPCODE_DESC): New type.
- (all fns): New first arg of opcode table descriptor.
- (cgen_set_parse_operand_fn): Add prototype.
- (cgen_current_machine,cgen_current_endian): Delete.
- (CGEN_OPCODE_TABLE): New members mach,endian,operand_table,
- parse_operand_fn,asm_hash_table,asm_hash_table_entries,
- dis_hash_table,dis_hash_table_entries.
- (opcode_open,opcode_close): Add prototypes.
-
- * cgen.h (cgen_insn): New element `cdx'.
-
-Thu Jul 30 21:44:25 1998 Frank Ch. Eigler
-
- * d30v.h (FLAG_LKR): New flag for "left-kills-right" instructions.
-
-Tue Jul 28 10:59:07 1998 Jeffrey A Law (law@cygnus.com)
-
- * mn10300.h: Add "no_match_operands" field for instructions.
- (MN10300_MAX_OPERANDS): Define.
-
-Fri Jul 24 11:44:24 1998 Doug Evans
-
- * cgen.h (cgen_macro_insn_count): Declare.
-
-Tue Jul 21 13:12:13 1998 Doug Evans
-
- * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Define.
- (cgen_insert_fn,cgen_extract_fn): New arg `pc'.
- (get_operand,put_operand): Replaced with get_{int,vma}_operand,
- set_{int,vma}_operand.
-
-Fri Jun 26 11:09:06 1998 Jeffrey A Law (law@cygnus.com)
-
- * mn10300.h: Add "machine" field for instructions.
- (MN103, AM30): Define machine types.
-
-Fri Jun 19 16:09:09 1998 Alan Modra
-
- * i386.h: Use FP, not sl_Suf, for fxsave and fxrstor.
-
-1998-06-18 Ulrich Drepper
-
- * i386.h: Add support for fxsave, fxrstor, sysenter and sysexit.
-
-Sat Jun 13 11:31:35 1998 Alan Modra
-
- * i386.h (i386_optab): Add general form of aad and aam. Add ud2a
- and ud2b.
- (i386_regtab): Allow cr0..7, db0..7, dr0..7, tr0..7, not just
- those that happen to be implemented on pentiums.
-
-Tue Jun 9 12:16:01 1998 Alan Modra