URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/gnu-old/gdb-6.8/sim/erc32
- from Rev 816 to Rev 827
- ↔ Reverse comparison
Rev 816 → Rev 827
/configure
File deleted
configure
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: Makefile.in
===================================================================
--- Makefile.in (revision 816)
+++ Makefile.in (nonexistent)
@@ -1,74 +0,0 @@
-# Makefile template for Configure for the erc32sim library.
-# Copyright (C) 1993, 1996, 1997, 2007, 2008 Free Software Foundation, Inc.
-# Written by Cygnus Support
-# Modified by J.Gaisler ESA/ESTEC
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see
-#include
-#ifdef HAVE_STDLIB_H
-#include
-#endif
-#include
-#include
-#include
-#include "sis.h"
-#include
-#include "sim-config.h"
-
-#define VAL(x) strtol(x,(char **)NULL,0)
-
-/* Structures and functions from readline library */
-
-typedef struct {
- char *line;
- char *data;
-} HIST_ENTRY;
-
-extern char * readline PARAMS ((char *prompt));
-extern void using_history PARAMS ((void));
-extern void add_history PARAMS ((char *string));
-extern HIST_ENTRY *remove_history PARAMS ((int which));
-
-
-
-/* Command history buffer length - MUST be binary */
-#define HIST_LEN 64
-
-extern struct disassemble_info dinfo;
-extern struct pstate sregs;
-extern struct estate ebase;
-
-extern int ctrl_c;
-extern int nfp;
-extern int ift;
-extern int wrp;
-extern int rom8;
-extern int uben;
-extern int sis_verbose;
-extern char *sis_version;
-extern struct estate ebase;
-extern struct evcell evbuf[];
-extern struct irqcell irqarr[];
-extern int irqpend, ext_irl;
-extern int termsave;
-extern int sparclite;
-extern int dumbio;
-extern char uart_dev1[];
-extern char uart_dev2[];
-extern uint32 last_load_addr;
-
-#ifdef ERA
-extern int era;
-#endif
-
-int
-run_sim(sregs, icount, dis)
- struct pstate *sregs;
- unsigned int icount;
- int dis;
-{
- int irq, mexc, deb, asi;
-
- sregs->starttime = time(NULL);
- init_stdio();
- if (sregs->err_mode) icount = 0;
- deb = dis || sregs->histlen || sregs->bptnum;
- irq = 0;
- while (icount > 0) {
-
- if (sregs->psr & 0x080)
- asi = 9;
- else
- asi = 8;
- mexc = memory_read(asi, sregs->pc, &sregs->inst, 2, &sregs->hold);
- sregs->icnt = 1;
- if (sregs->annul) {
- sregs->annul = 0;
- sregs->pc = sregs->npc;
- sregs->npc = sregs->npc + 4;
- } else {
- sregs->fhold = 0;
- if (ext_irl) irq = check_interrupts(sregs);
- if (!irq) {
- if (mexc) {
- sregs->trap = I_ACC_EXC;
- } else {
- if (deb) {
- if ((sregs->bphit = check_bpt(sregs)) != 0) {
- restore_stdio();
- return (BPT_HIT);
- }
- if (sregs->histlen) {
- sregs->histbuf[sregs->histind].addr = sregs->pc;
- sregs->histbuf[sregs->histind].time = ebase.simtime;
- sregs->histind++;
- if (sregs->histind >= sregs->histlen)
- sregs->histind = 0;
- }
- if (dis) {
- printf(" %8u ", ebase.simtime);
- dis_mem(sregs->pc, 1, &dinfo);
- }
- }
- dispatch_instruction(sregs);
- icount--;
- }
- }
- if (sregs->trap) {
- irq = 0;
- sregs->err_mode = execute_trap(sregs);
- if (sregs->err_mode) {
- error_mode(sregs->pc);
- icount = 0;
- }
- }
- }
- advance_time(sregs);
- if (ctrl_c || (sregs->tlimit <= ebase.simtime)) {
- icount = 0;
- if (sregs->tlimit <= ebase.simtime) sregs->tlimit = -1;
- }
- }
- sregs->tottime += time(NULL) - sregs->starttime;
- restore_stdio();
- if (sregs->err_mode)
- return (ERROR);
- if (ctrl_c) {
- ctrl_c = 0;
- return (CTRL_C);
- }
- return (TIME_OUT);
-}
-
-int
-main(argc, argv)
- int argc;
- char **argv;
-{
-
- int cont = 1;
- int stat = 1;
- int freq = 14;
- int copt = 0;
-
- char *cfile, *bacmd;
- char *cmdq[HIST_LEN];
- int cmdi = 0;
- int i;
-
- cfile = 0;
- for (i = 0; i < 64; i++)
- cmdq[i] = 0;
- printf("\n SIS - SPARC intruction simulator %s, copyright Jiri Gaisler 1995\n", sis_version);
- printf(" Bug-reports to jgais@wd.estec.esa.nl\n\n");
- while (stat < argc) {
- if (argv[stat][0] == '-') {
- if (strcmp(argv[stat], "-v") == 0) {
- sis_verbose = 1;
- } else if (strcmp(argv[stat], "-c") == 0) {
- if ((stat + 1) < argc) {
- copt = 1;
- cfile = argv[++stat];
- }
- } else if (strcmp(argv[stat], "-nfp") == 0)
- nfp = 1;
- else if (strcmp(argv[stat], "-ift") == 0)
- ift = 1;
- else if (strcmp(argv[stat], "-wrp") == 0)
- wrp = 1;
- else if (strcmp(argv[stat], "-rom8") == 0)
- rom8 = 1;
- else if (strcmp(argv[stat], "-uben") == 0)
- uben = 1;
- else if (strcmp(argv[stat], "-uart1") == 0) {
- if ((stat + 1) < argc)
- strcpy(uart_dev1, argv[++stat]);
- } else if (strcmp(argv[stat], "-uart2") == 0) {
- if ((stat + 1) < argc)
- strcpy(uart_dev2, argv[++stat]);
- } else if (strcmp(argv[stat], "-freq") == 0) {
- if ((stat + 1) < argc)
- freq = VAL(argv[++stat]);
- } else if (strcmp(argv[stat], "-sparclite") == 0) {
- sparclite = 1;
-#ifdef ERA
- } else if (strcmp(argv[stat], "-era") == 0) {
- era = 1;
-#endif
- } else if (strcmp(argv[stat], "-dumbio") == 0) {
- dumbio = 1;
- } else {
- printf("unknown option %s\n", argv[stat]);
- usage();
- exit(1);
- }
- } else {
- last_load_addr = bfd_load(argv[stat]);
- }
- stat++;
- }
- if (nfp)
- printf("FPU disabled\n");
-#ifdef ERA
- if (era)
- printf("ERA ECC emulation enabled\n");
-#endif
- sregs.freq = freq;
-
- INIT_DISASSEMBLE_INFO(dinfo, stdout, (fprintf_ftype) fprintf);
- dinfo.endian = BFD_ENDIAN_BIG;
-
- termsave = fcntl(0, F_GETFL, 0);
- using_history();
- init_signals();
- ebase.simtime = 0;
- reset_all();
- init_bpt(&sregs);
- init_sim();
-#ifdef STAT
- reset_stat(&sregs);
-#endif
-
- if (copt) {
- bacmd = (char *) malloc(256);
- strcpy(bacmd, "batch ");
- strcat(bacmd, cfile);
- exec_cmd(&sregs, bacmd);
- }
- while (cont) {
-
- if (cmdq[cmdi] != 0) {
-#if 0
- remove_history(cmdq[cmdi]);
-#else
- remove_history(cmdi);
-#endif
- free(cmdq[cmdi]);
- cmdq[cmdi] = 0;
- }
- cmdq[cmdi] = readline("sis> ");
- if (cmdq[cmdi] && *cmdq[cmdi])
- add_history(cmdq[cmdi]);
- if (cmdq[cmdi])
- stat = exec_cmd(&sregs, cmdq[cmdi]);
- else {
- puts("\n");
- exit(0);
- }
- switch (stat) {
- case OK:
- break;
- case CTRL_C:
- printf("\b\bInterrupt!\n");
- case TIME_OUT:
- printf(" Stopped at time %d (%.3f ms)\n", ebase.simtime,
- ((double) ebase.simtime / (double) sregs.freq) / 1000.0);
- break;
- case BPT_HIT:
- printf("breakpoint at 0x%08x reached\n", sregs.pc);
- sregs.bphit = 1;
- break;
- case ERROR:
- printf("IU in error mode (%d)\n", sregs.trap);
- stat = 0;
- printf(" %8d ", ebase.simtime);
- dis_mem(sregs.pc, 1, &dinfo);
- break;
- default:
- break;
- }
- ctrl_c = 0;
- stat = OK;
-
- cmdi = (cmdi + 1) & (HIST_LEN - 1);
-
- }
- return 0;
-}
-
sis.c
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: sis.h
===================================================================
--- sis.h (revision 816)
+++ sis.h (nonexistent)
@@ -1,217 +0,0 @@
-/*
- * This file is part of SIS.
- *
- * ERC32SIM, SPARC instruction simulator. Copyright (C) 1995 Jiri Gaisler,
- * European Space Agency
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 675
- * Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include "ansidecl.h"
-#include "gdb/callback.h"
-#include "gdb/remote-sim.h"
-
-#include "end.h"
-
-#define I_ACC_EXC 1
-
-/* Maximum events in event queue */
-#define EVENT_MAX 256
-
-/* Maximum # of floating point queue */
-#define FPUQN 1
-
-/* Maximum # of breakpoints */
-#define BPT_MAX 256
-
-struct histype {
- unsigned addr;
- unsigned time;
-};
-
-/* type definitions */
-
-typedef short int int16; /* 16-bit signed int */
-typedef unsigned short int uint16; /* 16-bit unsigned int */
-typedef int int32; /* 32-bit signed int */
-typedef unsigned int uint32; /* 32-bit unsigned int */
-typedef float float32; /* 32-bit float */
-typedef double float64; /* 64-bit float */
-
-/* FIXME: what about host compilers that don't support 64-bit ints? */
-typedef unsigned long long uint64; /* 64-bit unsigned int */
-typedef long long int64; /* 64-bit signed int */
-
-struct pstate {
-
- float64 fd[16]; /* FPU registers */
-#ifdef HOST_LITTLE_ENDIAN_FLOAT
- float32 fs[32];
- float32 *fdp;
-#else
- float32 *fs;
-#endif
- int32 *fsi;
- uint32 fsr;
- int32 fpstate;
- uint32 fpq[FPUQN * 2];
- uint32 fpqn;
- uint32 ftime;
- uint32 flrd;
- uint32 frd;
- uint32 frs1;
- uint32 frs2;
- uint32 fpu_pres; /* FPU present (0 = No, 1 = Yes) */
-
- uint32 psr; /* IU registers */
- uint32 tbr;
- uint32 wim;
- uint32 g[8];
- uint32 r[128];
- uint32 y;
- uint32 asr17; /* Single vector trapping */
- uint32 pc, npc;
-
-
- uint32 trap; /* Current trap type */
- uint32 annul; /* Instruction annul */
- uint32 data; /* Loaded data */
- uint32 inst; /* Current instruction */
- uint32 asi; /* Current ASI */
- uint32 err_mode; /* IU error mode */
- uint32 breakpoint;
- uint32 bptnum;
- uint32 bphit;
- uint32 bpts[BPT_MAX]; /* Breakpoints */
-
- uint32 ltime; /* Load interlock time */
- uint32 hold; /* IU hold cycles in current inst */
- uint32 fhold; /* FPU hold cycles in current inst */
- uint32 icnt; /* Instruction cycles in curr inst */
-
- uint32 histlen; /* Trace history management */
- uint32 histind;
- struct histype *histbuf;
- float32 freq; /* Simulated processor frequency */
-
-
- uint32 tottime;
- uint32 ninst;
- uint32 fholdt;
- uint32 holdt;
- uint32 icntt;
- uint32 finst;
- uint32 simstart;
- uint32 starttime;
- uint32 tlimit; /* Simulation time limit */
- uint32 pwdtime; /* Cycles in power-down mode */
- uint32 nstore; /* Number of load instructions */
- uint32 nload; /* Number of store instructions */
- uint32 nannul; /* Number of annuled instructions */
- uint32 nbranch; /* Number of branch instructions */
- uint32 ildreg; /* Destination of last load instruction */
- uint32 ildtime; /* Last time point for load dependency */
-
- int rett_err; /* IU in jmpl/restore error state (Rev.0) */
- int jmpltime;
-};
-
-struct evcell {
- void (*cfunc) ();
- int32 arg;
- uint32 time;
- struct evcell *nxt;
-};
-
-struct estate {
- struct evcell eq;
- struct evcell *freeq;
- uint32 simtime;
-};
-
-struct irqcell {
- void (*callback) ();
- int32 arg;
-};
-
-
-#define OK 0
-#define TIME_OUT 1
-#define BPT_HIT 2
-#define ERROR 3
-#define CTRL_C 4
-
-/* Prototypes */
-
-/* erc32.c */
-extern void init_sim PARAMS ((void));
-extern void reset PARAMS ((void));
-extern void error_mode PARAMS ((uint32 pc));
-extern void sim_halt PARAMS ((void));
-extern void exit_sim PARAMS ((void));
-extern void init_stdio PARAMS ((void));
-extern void restore_stdio PARAMS ((void));
-extern int memory_read PARAMS ((int32 asi, uint32 addr, uint32 *data,
- int32 sz, int32 *ws));
-extern int memory_write PARAMS ((int32 asi, uint32 addr, uint32 *data,
- int32 sz, int32 *ws));
-extern int sis_memory_write PARAMS ((uint32 addr, char *data,
- uint32 length));
-extern int sis_memory_read PARAMS ((uint32 addr, char *data,
- uint32 length));
-
-/* func.c */
-extern void set_regi PARAMS ((struct pstate *sregs, int32 reg,
- uint32 rval));
-extern void get_regi PARAMS ((struct pstate *sregs, int32 reg, char *buf));
-extern int exec_cmd PARAMS ((struct pstate *sregs, char *cmd));
-extern void reset_stat PARAMS ((struct pstate *sregs));
-extern void show_stat PARAMS ((struct pstate *sregs));
-extern void init_bpt PARAMS ((struct pstate *sregs));
-extern void init_signals PARAMS ((void));
-
-struct disassemble_info;
-extern void dis_mem PARAMS ((uint32 addr, uint32 len,
- struct disassemble_info *info));
-extern void event PARAMS ((void (*cfunc) (), int32 arg, uint32 delta));
-extern void set_int PARAMS ((int32 level, void (*callback) (), int32 arg));
-extern void advance_time PARAMS ((struct pstate *sregs));
-extern uint32 now PARAMS ((void));
-extern int wait_for_irq PARAMS ((void));
-extern int check_bpt PARAMS ((struct pstate *sregs));
-extern void reset_all PARAMS ((void));
-extern void sys_reset PARAMS ((void));
-extern void sys_halt PARAMS ((void));
-extern int bfd_load PARAMS ((char *fname));
-
-/* exec.c */
-extern int dispatch_instruction PARAMS ((struct pstate *sregs));
-extern int execute_trap PARAMS ((struct pstate *sregs));
-extern int check_interrupts PARAMS ((struct pstate *sregs));
-extern void init_regs PARAMS ((struct pstate *sregs));
-
-/* interf.c */
-extern int run_sim PARAMS ((struct pstate *sregs,
- unsigned int icount, int dis));
-
-/* float.c */
-extern int get_accex PARAMS ((void));
-extern void clear_accex PARAMS ((void));
-extern void set_fsr PARAMS ((uint32 fsr));
-
-/* help.c */
-extern void usage PARAMS ((void));
-extern void gen_help PARAMS ((void));
sis.h
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
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Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: float.c
===================================================================
--- float.c (revision 816)
+++ float.c (nonexistent)
@@ -1,212 +0,0 @@
-/*
- * This file is part of SIS.
- *
- * SIS, SPARC instruction simulator. Copyright (C) 1995 Jiri Gaisler, European
- * Space Agency
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 675
- * Mass Ave, Cambridge, MA 02139, USA.
- *
- *
- * This file implements the interface between the host and the simulated
- * FPU. IEEE trap handling is done as follows:
- * 1. In the host, all IEEE traps are masked
- * 2. After each simulated FPU instruction, check if any exception occured
- * by reading the exception bits from the host FPU status register
- * (get_accex()).
- * 3. Propagate any exceptions to the simulated FSR.
- * 4. Clear host exception bits
- *
- *
- * This can also be done using ieee_flags() library routine on sun.
- */
-
-#include "sis.h"
-
-/* Forward declarations */
-
-extern uint32 _get_sw PARAMS ((void));
-extern uint32 _get_cw PARAMS ((void));
-static void __setfpucw PARAMS ((unsigned short fpu_control));
-
-/* This host dependent routine should return the accrued exceptions */
-int
-get_accex()
-{
-#ifdef sparc
- return ((_get_fsr_raw() >> 5) & 0x1F);
-#elif i386
- uint32 accx;
-
- accx = _get_sw() & 0x3f;
- accx = ((accx & 1) << 4) | ((accx & 2) >> 1) | ((accx & 4) >> 1) |
- (accx & 8) | ((accx & 16) >> 2) | ((accx & 32) >> 5);
- return(accx);
-#else
- return(0);
-#warning no fpu trap support for this target
-#endif
-
-}
-
-/* How to clear the accrued exceptions */
-void
-clear_accex()
-{
-#ifdef sparc
- set_fsr((_get_fsr_raw() & ~0x3e0));
-#elif i386
- asm("\n"
-".text\n"
-" fnclex\n"
-"\n"
-" ");
-#else
-#warning no fpu trap support for this target
-#endif
-}
-
-/* How to map SPARC FSR onto the host */
-void
-set_fsr(fsr)
-uint32 fsr;
-{
-#ifdef sparc
- _set_fsr_raw(fsr & ~0x0f800000);
-#elif i386
- void __setfpucw(unsigned short fpu_control);
- uint32 rawfsr;
-
- fsr >>= 30;
- switch (fsr) {
- case 0:
- case 2: break;
- case 1: fsr = 3;
- case 3: fsr = 1;
- }
- rawfsr = _get_cw();
- rawfsr |= (fsr << 10) | 0x3ff;
- __setfpucw(rawfsr);
-#else
-#warning no fpu trap support for this target
-#endif
-}
-
-
-/* Host dependent support functions */
-
-#ifdef sparc
-
- asm("\n"
-"\n"
-".text\n"
-" .align 4\n"
-" .global __set_fsr_raw,_set_fsr_raw\n"
-"__set_fsr_raw:\n"
-"_set_fsr_raw:\n"
-" save %sp,-104,%sp\n"
-" st %i0,[%fp+68]\n"
-" ld [%fp+68], %fsr\n"
-" mov 0,%i0\n"
-" ret\n"
-" restore\n"
-"\n"
-" .align 4\n"
-" .global __get_fsr_raw\n"
-" .global _get_fsr_raw\n"
-"__get_fsr_raw:\n"
-"_get_fsr_raw:\n"
-" save %sp,-104,%sp\n"
-" st %fsr,[%fp+68]\n"
-" ld [%fp+68], %i0\n"
-" ret\n"
-" restore\n"
-"\n"
-" ");
-
-#elif i386
-
- asm("\n"
-"\n"
-".text\n"
-" .align 8\n"
-".globl _get_sw,__get_sw\n"
-"__get_sw:\n"
-"_get_sw:\n"
-" pushl %ebp\n"
-" movl %esp,%ebp\n"
-" movl $0,%eax\n"
-" fnstsw %ax\n"
-" movl %ebp,%esp\n"
-" popl %ebp\n"
-" ret\n"
-"\n"
-" .align 8\n"
-".globl _get_cw,__get_cw\n"
-"__get_cw:\n"
-"_get_cw:\n"
-" pushl %ebp\n"
-" movl %esp,%ebp\n"
-" subw $2,%esp\n"
-" fnstcw -2(%ebp)\n"
-" movw -2(%ebp),%eax\n"
-" movl %ebp,%esp\n"
-" popl %ebp\n"
-" ret\n"
-"\n"
-"\n"
-" ");
-
-
-#else
-#warning no fpu trap support for this target
-#endif
-
-#if i386
-/* #if defined _WIN32 || defined __GO32__ */
-/* This is so floating exception handling works on NT
- These definitions are from the linux fpu_control.h, which
- doesn't exist on NT.
-
- default to:
- - extended precision
- - rounding to nearest
- - exceptions on overflow, zero divide and NaN
-*/
-#define _FPU_DEFAULT 0x1372
-#define _FPU_RESERVED 0xF0C0 /* Reserved bits in cw */
-
-static void
-__setfpucw(unsigned short fpu_control)
-{
- volatile unsigned short cw;
-
- /* If user supplied _fpu_control, use it ! */
- if (!fpu_control)
- {
- /* use defaults */
- fpu_control = _FPU_DEFAULT;
- }
- /* Get Control Word */
- __asm__ volatile ("fnstcw %0" : "=m" (cw) : );
-
- /* mask in */
- cw &= _FPU_RESERVED;
- cw = cw | (fpu_control & ~_FPU_RESERVED);
-
- /* set cw */
- __asm__ volatile ("fldcw %0" :: "m" (cw));
-}
-/* #endif */
-#endif
float.c
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Index: ChangeLog
===================================================================
--- ChangeLog (revision 816)
+++ ChangeLog (nonexistent)
@@ -1,704 +0,0 @@
-2006-12-21 Hans-Peter Nilsson
-
- * acconfig.h: Remove.
- * config.in: Regenerate.
-
-2006-12-20 Hans-Peter Nilsson
-
- * configure.ac: Add test for readline, substitute READLINE.
- * Makefile.in (READLINE_LIB): New substituted-contents variable.
- (SIM_EXTRA_LIBDEPS): Don't set.
- (SIM_EXTRA_LIBS): Use $(READLINE_LIB) instead of
- ../../readline/libreadline.a.
- * configure: Regenerate.
-
-2006-08-08 Daniel Jacobowitz
-
- * Makefile.in (func.o, help.o): Correct dependencies.
-
-2006-08-08 Joel Sherrill
-
- * Makefile.in (install-sis): Honor DESTDIR.
-
-2006-06-13 Richard Earnshaw
-
- * configure: Regenerated.
-
-2006-06-05 Daniel Jacobowitz
-
- * configure: Regenerated.
-
-2006-05-31 Daniel Jacobowitz
-
- * configure: Regenerated.
-
-2005-11-28 Mark Mitchell
-
- * interf.c: (gdb/signals.h): Include it.
- (sim_stop_reason): Use TARGET_SIGNAL_*.
-
-2005-07-08 Ben Elliston
-
- * func.c: Remove ANSI_PROTOTYPES conditional code.
-
-2005-03-23 Mark Kettenis
-
- * configure: Regenerate.
-
-2005-03-07 Jerome Guitton
-
- * sim/erc32/float.c (set_fsr): Do not use deprecated multi-line
- strings.
- (clear_accex): Ditto.
- * sim/erc32/interf.c: Remove the redeclaration of fprintf.
- * sim/erc32/sis.c: Ditto.
- * sim/erc32/exec.c: Add missing semicolon.
- * sim/erc32/func.c: Remove definitions of generic_print_address,
- generic_symbol_at_address, buffer_read_memory and perror_memory, as
- they are already defined in opcodes/dis-buf.c.
-
-2005-01-14 Andrew Cagney
-
- * configure.ac: Sinclude aclocal.m4 before common.m4. Add
- explicit call to AC_CONFIG_HEADER.
- * configure: Regenerate.
-
-2005-01-12 Andrew Cagney
-
- * configure.ac: Update to use ../common/common.m4.
- * configure: Re-generate.
-
-2005-01-11 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-2005-01-07 Andrew Cagney
-
- * configure.ac: Rename configure.in, require autoconf 2.59.
- * configure: Re-generate.
-
-2004-12-08 Hans-Peter Nilsson
-
- * configure: Regenerate for ../common/aclocal.m4 update.
-
-2004-11-11 Andreas Schwab
-
- * interf.c: Include "libiberty.h" instead of declaring buildargv
- ourselves.
-
-2003-02-27 Andrew Cagney
-
- * interf.c (sim_open, sim_create_inferior): Rename _bfd to bfd.
-
-2002-06-16 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-2002-06-08 Andrew Cagney
-
- * sis.h: Include "gdb/remote-sim.h" and "gdb/callback.h".
- * interf.c: Include "gdb/remote-sim.h".
-
-Tue May 23 21:39:23 2000 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-2000-03-07 Frank Ch. Eigler
-
- From John Dallaway :
- * Makefile.in (install-sis): Add $(EXEEXT) for Windows host.
-
-2000-03-03 Jonathan Larmour
-
- * func.c (buffer_read_memory): Change type of size to unsigned to
- match prototype
-
-Thu Sep 2 18:15:53 1999 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-1999-05-08 Felix Lee
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-1999-03-03 DJ Delorie
-
- * configure.in: add termcap and -luser32 for host=cygwin
- * configure: regenerate
-
-1999-02-11 Hugo Tyson
-
- * exec.c (dispatch_instruction):
- Correct the sense of the
- if (!sparclite) {
- sregs->trap = TRAP_UNIMP;
- break;
- }
- clause that has been pasted around: it's correct in the SCAN and
- DIVScc (divide step) cases (where it was probably originally
- written?), but reversed in the SDIV, SDIVcc, UDIV, UDIVcc cases
- ie. instructions only in the SPARC V8 or SPARClite 86x
- architectures. It was also present when not required for SMUL,
- SMULcc, UMUL, UMULcc instructions that are present in all
- architectures.
-
-1999-01-25 Hugo Tyson
-
- * interf.c (run_sim): Fix a bug in the main loop's handling of
- annulled delay slot instructions. There is precedent for this
- change; the _other_ main loop in sis.c gets it right according to
- my reading of the code.
-
- The bug is: if an interrupt happens when the next instruction
- (at sregs->pc) is annulled, the trap is taken (by execute_trap())
- with the current values of PC and NPC, so when the trap returns,
- the annulled instruction is indeed executed. Another giveaway is
- that the annul flag is cleared in execute_trap(): the information
- is demonstrably discarded.
-
- The solution is: perform annulling before looking for traps, in
- fact it's neater to do annulling, see if there's an interrupt and
- if not, do the instruction, then handle traps be they generated by
- interrupts pending or by the instruction we might just have done.
- That's what the sis.c one does.
-
-1999-01-20 Hugo Tyson
-
- * sis.h: Add asr17 register for support of SparcLITE (at least the
- Hitachi ones I find before me)
-
- * exec.c (dispatch_instruction): Case WRY: Allow write of asr17 if
- sparclite. Other ASR numbers than 17 or 0 (Y) trap out.
- Case RDY: Allow read of asr17 if sparclite. Other ASRs ditto.
- (execute_trap): Do single-vector-trapping if asr17 bit 0 is set.
- (init_regs): Initialize y and asr17.
- NB: In instruction-set space, the Y register is asr0; the
- instructions have different names for human reasons only.
-
- * sis.c:
- * interf.c: Set boolean mode variable dumbio if invoked with
- argument "-dumbio" and mention it of verbose.
- * erc32.c: if "dumbio" is set, do not assume that there is a
- terminal type device attached to stdin/stdout. Do not set
- buffering or mess with tcsetattr or do any read operations in
- order to make UART interrupts; not input data is supported.
- This is necessary to allow the sim to be used within the eCos
- testing infrastructure where stdin/stdout are pipes to a TCL
- program; the sim hangs otherwise.
-
-Thu Jul 23 07:17:03 1998 Mark Alexander
-
- * exec.c (dispatch_instruction): Add SPARClite 'scan' instruction.
-
-Tue Jul 7 21:12:41 1998 Mark Alexander
-
- * func.c (bfd_load): Add special handling of a.out executables.
-
-Sat Jun 13 08:33:25 1998 Mark Alexander
-
- * func.c (bfd_load): Print correct endianness.
- * interf.c (run_sim): Print debugging information if verbosity level
- is greater than 2.
- (sim_open): Repeated -v options now increment verbosity level.
- (sim_store_register): Handle little-endian case.
- (flush_window): Print debugging information if verbosity level
- is greater then 2.
-
-Tue Jun 2 15:20:35 1998 Mark Alexander
-
- * interf.c (sim_open): Use revamped memory_read, which makes
- byte-swapping unnecessary. Add -sparclite-board option for
- emulating RAM found on typical SPARClite boards. Print
- error message for unrecognized option.
- * erc32.c: Change RAM address and size from constants to variables,
- to allow emulation of SPARClite board RAM.
- (fetch_bytes, store_bytes): New helper functions for revamped
- mememory_read and memory_write.
- (memory_read, memory_write): Rewrite to store bytes in target
- byte order instead of storing words in host byte order; this
- greatly simplifies support of little-endian programs.
- (get_mem_ptr): Remove unnecessary byte parameter.
- (sis_memory_write, sis_memory_read): Store words in target
- byte order instead of host byte order.
- (byte_swap_words): Remove, no longer needed.
- * sis.h ((byte_swap_words): Remove declaration, no longer needed.
- (memory_read): Add new sz parameter.
- * sis.c (run_sim): Use revamped memory_read, which makes
- byte-swapping unnecessary.
- * exec.c (dispatch_instruction): Use revamped memory_read, which
- makes byte-swapping and double-word fetching unnecessary.
- * func.c (sparclite_board): Declare new variable.
- (get_regi): Handle little-endian data.
- (bfd_load): Recognize little-endian SPARClite as having
- little-endian data.
-
-Fri May 22 14:23:16 1998 Mark Alexander
-
- * erc32.c (port_init): Print messages only if sis_verbose is true.
- * func.c (bfd_load): Ditto.
- * interf.c (sim_open): Ditto.
-
-Thu May 14 23:10:48 1998 Mark Alexander
-
- * sis.h (uint64, int64): Define.
- * exec.c (SDIV, SDIVCC, UDIV, UDIVCC): Define new opcodes.
- * (mul64): Simplify calculation of negative result.
- * (div64): New helper function for 64-bit division.
- * (dispatch_instruction): Add emulation of SDIV, SDIVCC, UDIV,
- and UDIVCC.
-
-Wed May 13 14:59:54 1998 Mark Alexander
-
- * erc32.c (close_port): Don't close stdin; it kills GDB.
- (byte_swap_words): New function.
- * sis.h: (byte_swap_words): Declare.
- * interf.c (run_sim): Always fetch instructions as big-endian.
- * sis.c (run_sim): Ditto.
-
-Tue Apr 28 18:33:31 1998 Geoffrey Noer
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Sun Apr 26 15:31:55 1998 Tom Tromey
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
- * config.in: Ditto.
-
-Sun Apr 26 15:20:17 1998 Tom Tromey
-
- * acconfig.h: New file.
- * configure.in: Reverted change of Apr 24; use sinclude again.
-
-Fri Apr 24 14:16:40 1998 Tom Tromey
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
- * config.in: Ditto.
-
-Fri Apr 24 11:19:52 1998 Tom Tromey
-
- * configure.in: Don't call sinclude.
-
-Sat Apr 18 12:00:16 1998 Mark Alexander
-
- * func.c (disp_fpu): Fix build problem on big-endian hosts.
-
-Wed Apr 8 19:33:34 1998 Mark Alexander
-
- * erc32.c (sim_stop): Handle SIGINT gracefully.
- * interf.c (sim_open): Don't catch SIGINT; GDB will do that for us.
-
-Wed Apr 8 18:29:40 1998 Mark Alexander
-
- * exec.c (dispatch_instruction): Change how carry out is calculated
- in DIVSCC. Add emulation of SMULCC, UMUL, and UMULCC.
-
-Sat Apr 4 20:36:25 1998 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Apr 1 21:19:18 1998 Mark Alexander
-
- * end.c: Update to version 2.7.5, fix compiler warnings and bugs.
- * erc32.c: Ditto.
- * exec.c: Ditto.
- * float.c: Ditto.
- * func.c: Ditto.
- * help.c: Ditto.
- * interf.c: Ditto.
- * sis.c: Ditto.
- * sis.h: Ditto.
-
-Fri Mar 27 16:15:52 1998 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Mar 25 12:35:29 1998 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Mar 18 12:38:12 1998 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Tue Feb 17 12:41:11 1998 Andrew Cagney
-
- * interf.c (sim_store_register, sim_fetch_register): Pass in
- length parameter. Return -1.
-
-Sun Feb 1 16:47:51 1998 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Sat Jan 31 18:15:41 1998 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Mon Jan 19 22:26:29 1998 Doug Evans
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Mon Dec 15 23:17:11 1997 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
- * config.in: Ditto.
-
-Thu Dec 4 09:21:05 1997 Doug Evans
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Fri Oct 3 09:28:00 1997 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Sep 24 17:38:57 1997 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Tue Sep 23 11:04:38 1997 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Mon Sep 22 11:46:20 1997 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Fri Sep 19 17:45:25 1997 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Mon Sep 15 17:36:15 1997 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Aug 27 18:13:22 1997 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
- * config.in: Ditto.
-
-Tue Aug 26 10:38:20 1997 Andrew Cagney
-
- * float.c (__setfpucw): Compile on any i386 target. Not just NT.
-
- * interf.c (sim_kill): Delete.
- (sim_create_inferior): Add ABFD argument. Initialize PC from ABFD
- argument.
- (sim_load): Don't save start address.
- (start_address): Delete variable.
-
-Mon Aug 25 17:50:22 1997 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
- * config.in: Ditto.
-
-Mon Aug 25 16:19:49 1997 Andrew Cagney
-
- * interf.c (sim_open): Add ABFD argument. Change ARGV to PARGV.
-
-Mon Jun 30 11:45:25 1997 Doug Evans
-
- * Makefile.in (install-sis): Change $(srcdir)/sis to sis.
-
-Wed May 28 09:46:13 1997 Andrew Cagney
-
- * interf.c (sim_set_callbacks): Drop SD argument - not applicable.
- (sim_open): Add callback arg, save it.
-
-Thu Apr 24 00:39:51 1997 Doug Evans
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Tue Apr 22 11:05:01 1997 Doug Evans
-
- * interf.c (sim_open): Undo patch to add -E support.
-
-Thu Apr 17 03:03:56 1997 Doug Evans
-
- * interf.c (sim_open): Ignore -E arg.
- (start_address): New static local.
- (sim_load): Return SIM_RC. New arg abfd. Set start_address from bfd.
- (sim_create_inferior): Return SIM_RC. Delete arg start_address.
-
-Tue Apr 15 15:16:11 1997 Ian Lance Taylor
-
- * Makefile.in (install-sis): Depend upon installdirs. Use
- $(program_transform_name) directly, rather than using
- $(INSTALL_XFORM).
-
-Mon Apr 7 15:45:02 1997 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
- * config.in: Ditto.
-
-Wed Apr 2 15:06:28 1997 Doug Evans
-
- * interf.c (sim_open): New arg `kind'.
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Apr 2 14:34:19 1997 Andrew Cagney
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Mon Mar 17 15:10:07 1997 Andrew Cagney
-
- * configure: Re-generate.
-
-Thu Mar 13 12:46:04 1997 Doug Evans
-
- * interf.c (sim_open): New SIM_DESC result. Argument is now in
- argv form.
- (other sim_*): New SIM_DESC argument.
-
-Tue Feb 4 13:35:20 1997 Doug Evans
-
- * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
- COMMON_{PRE,POST}_CONFIG_FRAG instead.
- * configure.in: sinclude ../common/aclocal.m4.
- * configure: Regenerated.
-
-Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
-
- * configure configure.in Makefile.in: Update to new configure
- scheme which is more compatible with WinGDB builds.
- * configure.in: Improve comment on how to run autoconf.
- * configure: Re-run autoconf to get new ../common/aclocal.m4.
- * Makefile.in: Use autoconf substitution to install common
- makefile fragment.
-
-Wed Dec 4 18:25:04 1996 Rob Savoye
-
- * interf.c (run_sim): Stop the simulator and reset the stdio after
- breakpoints.
-
-Tue Dec 3 11:54:37 1996 Rob Savoye
-
- * configure.in: Look for libtermcap.a.
- * Makefile.in: Only link in -ltermcap if it exists.
- * erc32.c: Update to version 2.6a. Fix uart handling.
- * exec.c: Update to version 2.6a. Add sparclite support.
- * float.c: Update to version 2.6a. Convert comments to
- preprocessor warnings. Add __setfpucw() for i385 hosts so floating
- point exceptions work on win32.
- * func.c: Update to version 2.6a. Fix uart handling, add support
- for user error traps.
- * help.c: Update to version 2.6a. Add help note on user error
- traps.
- * interf.c: Update to version 2.6a. Fix uart handling, and add
- sparclite support.
- * examples/gccx: Use sparclite cross compiler, not native gcc.
- * examples/srt0.S: Use "mov" rather than "wr" for manipulating
- the psr register.
-
-Mon Nov 25 08:28:10 1996 Fred Fish
-
- * Makefile.in (run.o): Remove this rule, it hides the one in
- ../common/Make-common.in that correctly references the source
- in the sibling ../common directory.
-
-Wed Nov 20 01:30:12 1996 Doug Evans
-
- * Makefile.in: Delete stuff moved to ../common/Make-common.in.
- (SIM_{OBJS,EXTRA_LIBS,EXTRA_LIBDEPS,EXTRA_ALL,EXTRA_INSTALL}): Define.
- (SIM_{EXTRA_CLEAN,EXTRA_CFLAGS}): Define.
- * configure.in: Simplify using macros in ../common/aclocal.m4.
- Call AC_CHECK_HEADERS(stdlib.h).
- * configure: Regenerated.
- * config.in: New file.
- * func.c (sim_set_callbacks): Delete, moved to
- * interf.c (sim_set_callbacks): here.
- (sim_callback): New global.
- Rewrite all calls to printf_filtered to go through callback.
- (sim_size,sim_trace): New functions.
- (sim_{insert,remove}_breakpoint): #if 0 out.
- * sis.c: #include "config.h". #include if present.
- (main): Coerce fprintf arg to INIT_DISASSEMBLE_INFO to fprintf_ftype.
- * sis.h: #include "callback.h".
- * run.c: Deleted, using one in ../common now.
-
-Thu Oct 3 16:12:03 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
-
- * Makefile.in (clean): Move config.log to distclean.
-
-Wed Oct 2 16:57:57 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
-
- * Makefile.in (clean): Also remove config.log.
-
-Sat Sep 14 00:00:46 1996 Ian Lance Taylor
-
- * Makefile.in (CC_FOR_BUILD): New variable.
- (AR, AR_FLAGS, BISON, MAKEINFO): Remove duplicate variables.
- (RANLIB, CC): Likewise.
- (end): Use $(CC_FOR_BUILD), not $(CC).
- * configure.in: Set CC_FOR_BUILD.
- * configure: Rebuild.
-
-Sun Sep 8 14:04:37 1996 Stu Grossman (grossman@critters.cygnus.com)
-
- * erc32.c (port_init): Disable this for __GO32__ (got no pty's
- there either...).
-
-Mon Aug 12 17:04:58 1996 Stu Grossman (grossman@critters.cygnus.com)
-
- * erc32.c: Don't include sys/ioctl.h or sys/file.h. They aren't
- necessary.
- * (port_init): Don't even *try* to open pty's under _WIN32.
- * Use SIM_ADDR, not caddr_t for declaring vars that hold addresses.
- * float.c: Get rid of #warning. Makes Microsoft C barf.
- * interf.c (sim_open): Cast fprintf to (fprintf_ftype) to fix
- compiler warning.
- * (sim_load sim_create_inferior sim_read): Use prototypes only in
- decls, not defs.
- * Get rid of enum sim_stop. It's defined in remote-sim.h.
- * (sim_stop_reason): Define SIGTRAP if _WIN32.
- * sis.h: Include ansidecl.h and remote-sim.h.
-
-Wed Jul 3 16:05:23 1996 Stu Grossman (grossman@critters.cygnus.com)
-
- * erc32.c (mec_reset mec_read mec_write memory_read memory_write),
- sis.h: Get rid of all uses of long long's.
- * (close_port read_uart write_uart uarta_tx): Don't seg fault
- when can't open pty's.
- * exec.c: Add two new instructions: smul, and divscc.
- * interf.c (flush_windows): New routine to flush the register
- windows out to the stack just before returning to GDB. Makes
- backtraces work much better.
-
-Wed Jun 26 12:19:11 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
-
- * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
- INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
- (docdir, oldincludedir): Removed.
- * configure.in (AC_PREREQ): autoconf 2.5 or higher.
- (AC_PROG_INSTALL): Added.
- * configure: Rebuilt.
-
-Mon Jun 24 14:19:07 1996 Ian Lance Taylor
-
- * configure.in: Call AC_PROG_CC before running configure.host.
- * configure: Rebuild with autoconf 2.10.
-
-Tue Jun 4 10:37:12 1996 Tom Tromey
-
- * Makefile.in (install): Don't check to see if tooldir exists.
- Make $(tooldir) and $(tooldir)/bin.
-
-Mon Jun 3 12:33:38 1996 Ian Lance Taylor
-
- * Makefile.in (end.h): Use explicit ./ when running end.
-
-Sun May 19 21:05:31 1996 Rob Savoye
-
- * func.c(bfd_load): Don't try to print the filename if the pfbd is
- NULL.
- * interf.c(sim_load): Pass the whole string, not just the first
- byte.
-
-Version 2.1 26-02-96
---------------------
-
-* Fixed bug in "go" command.
-
-version 2.0 05-02-96
---------------------
-
-* Fixed bug in interrupt force register (erc32.c).
-
-* Change file load function to use bfd_openr.
-
-* SIS should now be endian independent.
-
-version 1.8 24-11-95
---------------------
-
-* Fixed FPU timing - some sequences of FPU instructions did not calculate
- the resource dependencies right.
-
-* Corrected STDFQ when qne = 0 (again!). The ftt is set to sequence_error
- but no FPU trap is generated.
-
-version 1.7.1 31-10-95
---------------------
-
-* Corrected STDFQ when qne = 0. Now, a trap is immidiately generated but
- the FPU stays in execute mode.
-
-* Corrected JMPL and RETT timing (these instructions takes two cycles).
-
-
-version 1.7 25-10-95
---------------------
-
-* Interrupt during annuled instruction corrupted return address - fixed.
-
-
-version 1.6.2 25-10-95
---------------------
-
-* Added -DFAST_UART to Makefile
-
-
-version 1.6.1 24-10-95
---------------------
-
-* Fixed bug in STDFQ which caused bus error
-
-
-version 1.6 02-10-95
---------------------
-
-* Modified srt0.s to include code that initiates registers in IU and FPU
- and initializes the data segment. The simulator 'load' command does not
- longer initialize the data segment!
-
-* Corrected MEC timer operation; scalers now divide the frequency by
- (scaler_value + 1).
-
-* MEC breakpoints are not checked during store operation
-
-
-version 1.5 14-09-95
---------------------
-
-* Fixed some bugs in the cycle counting for IU & FPU instructions.
-
-* Fixed bug that allowed an annuled instruction to cause memory exception.
-
-* The *ws parameter in mem.c should now contain the number of waitstates
- required by the memory access (was total number of cycles).
-
-* The supplied srt0.s now clears the BSS (thanks Joel).
-
-version 1.4 22-08-95
---------------------
-
-* Added a '-g' switch to enable/disable the GNU readline(), which cause
-some problems on solaris 2.x machines.
-
-* Enabled MEC watchpoint and breakpoint function to mem.c. Performance
-may suffer a bit ...
-
-NOTE: The UARTs are now connected to /dev/ttypc and /dev/ttypd.
-
-version 1.3 26-07-95
---------------------
-
-* Fixed bug in mulscc instruction (how could that ever have worked?)
-
-* Fixed bug in UART B (flushed characters on UART A), thanks Paul.
-
-version 1.2 13-07-95
---------------------
-
-* Fixed bug in interrupt handling (wrong interrupt selected when more that
-one interrupt pending)
-
-* Fixed updating of condition codes during logical instructions (carry and
-overflow were not reset)
-
-* Fixed bug in WRTBR (tt field was wrongly over-written)
-
-version 1.1 07-07-95
---------------------
-
-* Fixed several bugs in the interrupt handler and callback routines.
-(reported by Paul Warren, Alsys)
ChangeLog
Property changes :
Deleted: svn:eol-style
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Index: end.c
===================================================================
--- end.c (revision 816)
+++ end.c (nonexistent)
@@ -1,26 +0,0 @@
-#include
-
-int
-main()
-{
-
- unsigned int u1;
- char *c;
- double d1;
- float *f1;
-
- c = (char *) &u1;
- u1 = 0x0F;
- if (c[0] == 0x0F)
- puts("#define HOST_LITTLE_ENDIAN\n");
- else
- puts("#define HOST_BIG_ENDIAN\n");
-
- d1 = 1.0;
- f1 = (float *) &d1;
- if (*((int *) f1) != 0x3ff00000)
- puts("#define HOST_LITTLE_ENDIAN_FLOAT\n");
- else
- puts("#define HOST_BIG_ENDIAN_FLOAT\n");
- return 0;
-}
end.c
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Index: README.gdb
===================================================================
--- README.gdb (revision 816)
+++ README.gdb (nonexistent)
@@ -1,67 +0,0 @@
-How to use SIS with GDB
------------------------
-
-1. Building GDB with SIS
-
-To build GDB with the SIS/ERC32 simulator, configure with option
-'--target sparc-erc32-aout' and build as usual.
-
-2. Attaching the simulator
-
-To attach GDB to the simulator, use:
-
-target sim [options] [files]
-
-The following options are supported:
-
- -nfp Disable FPU. FPops will cause an FPU disabled trap.
-
- -freq Set the simulated "system clock" to MHz.
-
- -v Verbose mode.
-
- -nogdb Disable GDB breakpoint handling (see below)
-
-The listed [files] are expected to be in aout format and will be
-loaded in the simulator memory prior. This could be used to load
-a boot block at address 0x0 if the application is linked to run
-from RAM (0x2000000).
-
-To start debugging a program type 'load ' and debug as
-usual.
-
-The native simulator commands can be reached using the GDB 'sim'
-command:
-
-sim
-
-Direct simulator commands during a GDB session must be issued
-with care not to disturb GDB's operation ...
-
-For info on supported ERC32 functionality, see README.sis.
-
-
-3. Loading aout files
-
-The GDB load command loads an aout file into the simulator
-memory with the data section starting directly after the text
-section regardless of wich start address was specified for the data
-at link time! This means that your applications either has to include
-a routine that initialise the data segment at the proper address or
-link with the data placed directly after the text section.
-
-A copying routine is fairly simple, just copy all data between
-_etext and _data to a memory loaction starting at _environ. This
-should be done at the same time as the bss is cleared (in srt0.s).
-
-
-4. GDB breakpoint handling
-
-GDB inserts breakpoint in the form of the 'ta 1' instruction. The
-GDB-integrated simulator will therefore recognize the breakpoint
-instruction and return control to GDB. If the application uses
-'ta 1', the breakpoint detection can be disabled with the -nogdb
-switch. In this case however, GDB breakpoints will not work.
-
-
-Report problems to Jiri Gaisler ESA/ESTEC (jgais@wd.estec.esa.nl)
README.gdb
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Index: README.sis
===================================================================
--- README.sis (revision 816)
+++ README.sis (nonexistent)
@@ -1,356 +0,0 @@
-
-SIS - Sparc Instruction Simulator README file (v2.0, 05-02-1996)
--------------------------------------------------------------------
-
-1. Introduction
-
-The SIS is a SPARC V7 architecture simulator. It consist of two parts,
-the simulator core and a user defined memory module. The simulator
-core executes the instructions while the memory module emulates memory
-and peripherals.
-
-2. Usage
-
-The simulator is started as follows:
-
-sis [-uart1 uart_device1] [-uart2 uart_device2]
- [-nfp] [-freq frequency] [-c batch_file] [files]
-
-The default uart devices for SIS are /dev/ptypc and /dev/ptypd. The
--uart[1,2] switch can be used to connect the uarts to other devices.
-Use 'tip /dev/ttypc' to connect a terminal emulator to the uarts.
-The '-nfp' will disable the simulated FPU, so each FPU instruction will
-generate a FPU disabled trap. The '-freq' switch can be used to define
-which "frequency" the simulator runs at. This is used by the 'perf'
-command to calculated the MIPS figure for a particular configuration.
-The give frequency must be an integer indicating the frequency in MHz.
-
-The -c option indicates that sis commands should be read from 'batch_file'
-at startup.
-
-Files to be loaded must be in one of the supported formats (see INSTALLATION),
-and will be loaded into the simulated memory. The file formats are
-automatically recognised.
-
-The script 'startsim' will start the simulator in one xterm window and
-open a terminal emulator (tip) connected to the UART A in a second
-xterm window. Below is description of commands that are recognized by
-the simulator. The command-line is parsed using GNU readline. A command
-history of 64 commands is maintained. Use the up/down arrows to recall
-previous commands. For more details, see the readline documentation.
-
-batch
-
-Execute a batch file of SIS commands.
-
-+bp
-
-Adds an breakpoint at address .
-
-bp
-
-Prints all breakpoints
-
--bp
-
-Deletes breakpoint . Use 'bp' to see which number is assigned to the
-breakpoints.
-
-cont [inst_count]
-
-Continue execution at present position, optionally for [inst_count]
-instructions.
-
-dis [addr] [count]
-
-Disassemble [count] instructions at address [addr]. Default values for
-count is 16 and addr is the present address.
-
-echo
-
-Print to the simulator window.
-
-float
-
-Prints the FPU registers
-
-go [inst_count]
-
-The go command will set pc to and npc to + 4, and start
-execution. No other initialisation will be done. If inst_count is given,
-execution will stop after the specified number of instructions.
-
-help
-
-Print a small help menu for the SIS commands.
-
-hist [trace_length]
-
-Enable the instruction trace buffer. The 'trace_length' last executed
-instructions will be placed in the trace buffer. A 'hist' command without
-a trace_length will display the trace buffer. Specifying a zero trace
-length will disable the trace buffer.
-
-load
-
-Loads a file into simulator memory.
-
-mem [addr] [count]
-
-Display memory at [addr] for [count] bytes. Same default values as above.
-
-quit
-
-Exits the simulator.
-
-perf [reset]
-
-The 'perf' command will display various execution statistics. A 'perf reset'
-command will reset the statistics. This can be used if statistics shall
-be calculated only over a part of the program. The 'run' and 'reset'
-command also resets the statistic information.
-
-reg [reg_name] [value]
-
-Prints and sets the IU regiters. 'reg' without parameters prints the IU
-registers. 'reg [reg_name] [value]' sets the corresponding register to
-[value]. Valid register names are psr, tbr, wim, y, g1-g7, o0-o7 and
-l0-l7.
-
-reset
-
-Performs a power-on reset. This command is equal to 'run 0'.
-
-run [inst_count]
-
-Resets the simulator and starts execution from address 0. If an instruction
-count is given (inst_count), the simulator will stop after the specified
-number of instructions. The event queue is emptied but any set breakpoints
-remain.
-
-step
-
-Equal to 'trace 1'
-
-tra [inst_count]
-
-Starts the simulator at the present position and prints each instruction
-it executes. If an instruction count is given (inst_count), the simulator
-will stop after the specified number of instructions.
-
-Typing a 'Ctrl-C' will interrupt a running simulator.
-
-Short forms of the commands are allowed, e.g 'c' 'co' or 'con' are all
-interpreted as 'cont'.
-
-
-3. Simulator core
-
-The SIS emulates the behavior of the 90C601E and 90C602E sparc IU and
-FPU from Matra MHS. These are roughly equivalent to the Cypress C601
-and C602. The simulator is cycle true, i.e a simulator time is
-maintained and inremented according the IU and FPU instruction timing.
-The parallel execution between the IU and FPU is modelled, as well as
-stalls due to operand dependencies (FPU). The core interacts with the
-user-defined memory modules through a number of functions. The memory
-module must provide the following functions:
-
-int memory_read(asi,addr,data,ws)
-int asi;
-unsigned int addr;
-unsigned int *data;
-int *ws;
-
-int memory_write(asi,addr,data,sz,ws)
-int asi;
-unsigned int addr;
-unsigned int *data;
-int sz;
-int *ws;
-
-int sis_memory_read(addr, data, length)
-unsigned int addr;
-char *data;
-unsigned int length;
-
-int sis_memory_write(addr, data, length)
-unsigned int addr;
-char *data;
-unsigned int length;
-
-int init_sim()
-
-int reset()
-
-int error_mode(pc)
-unsigned int pc;
-
-memory_read() is used by the simulator to fetch instructions and
-operands. The address space identifier (asi) and address is passed as
-parameters. The read data should be assigned to the data pointer
-(*data) and the number of waitstate to *ws. 'memory_read' should return
-0 on success and 1 on failure. A failure will cause a data or
-instruction fetch trap. memory_read() always reads one 32-bit word.
-
-sis_memory_read() is used by the simulator to display and disassemble
-memory contants. The function should copy 'length' bytes of the simulated
-memory starting at 'addr' to '*data'.
-The sis_memory_read() should return 1 on success and 0 on failure.
-Failure should only be indicated if access to unimplemented memory is attempted.
-
-memory_write() is used to write to memory. In addition to the asi
-and address parameters, the size of the written data is given by 'sz'.
-The pointer *data points to the data to be written. The 'sz' is coded
-as follows:
-
- sz access type
- 0 byte
- 1 halfword
- 2 word
- 3 double-word
-
-If a double word is written, the most significant word is in data[0] and
-the least significant in data[1].
-
-sis_memory_write() is used by the simulator during loading of programs.
-The function should copy 'length' bytes from *data to the simulated
-memory starting at 'addr'. sis_memory_write() should return 1 on
-success and 0 on failure. Failure should only be indicated if access
-to unimplemented memory is attempted. See erc32.c for more details
-on how to define the memory emulation functions.
-
-The 'init_sim' is called once when the simulator is started. This function
-should be used to perform initialisations of user defined memory or
-peripherals that only have to be done once, such as opening files etc.
-
-The 'reset' is called every time the simulator is reset, i.e. when a
-'run' command is given. This function should be used to simulate a power
-on reset of memory and peripherals.
-
-error_mode() is called by the simulator when the IU goes into error mode,
-typically if a trap is caused when traps are disabled. The memory module
-can then take actions, such as issue a reset.
-
-sys_reset() can be called by the memory module to reset the simulator. A
-reset will empty the event queue and perform a power-on reset.
-
-4. Events and interrupts
-
-The simulator supports an event queue and the generation of processor
-interrupts. The following functions are available to the user-defined
-memory module:
-
-event(cfunc,arg,delta)
-void (*cfunc)();
-int arg;
-unsigned int delta;
-
-set_int(level,callback,arg)
-int level;
-void (*callback)();
-int arg;
-
-clear_int(level)
-int level;
-
-sim_stop()
-
-The 'event' functions will schedule the execution of the function 'cfunc'
-at time 'now + delta' clock cycles. The parameter 'arg' is passed as a
-parameter to 'cfunc'.
-
-The 'set_int' function set the processor interrupt 'level'. When the interrupt
-is taken, the function 'callback' is called with the argument 'arg'. This
-will also clear the interrupt. An interrupt can be cleared before it is
-taken by calling 'clear_int' with the appropriate interrupt level.
-
-The sim_stop function is called each time the simulator stops execution.
-It can be used to flush buffered devices to get a clean state during
-single stepping etc.
-
-See 'erc32.c' for examples on how to use events and interrupts.
-
-5. Memory module
-
-The supplied memory module (erc32.c) emulates the functions of memory and
-the MEC asic developed for the 90C601/2. It includes the following functions:
-
-* UART A & B
-* Real-time clock
-* General purpose timer
-* Interrupt controller
-* Breakpoint register
-* Watchpoint register
-* 512 Kbyte ROM
-* 4 Mbyte RAM
-
-See README.erc32 on how the MEC functions are emulated. For a detailed MEC
-specification, look at the ERC32 home page at URL:
-
-http://www.estec.esa.nl/wsmwww/erc32
-
-6. Compile and linking programs
-
-The directory 'examples' contain some code fragments for SIS.
-The script gccx indicates how the native sunos gcc and linker can be used
-to produce executables for the simulator. To compile and link the provided
-'hello.c', type 'gccx hello.c'. This will build the executable 'hello'.
-Start the simulator by running 'startsim hello', and issue the command 'run.
-After the program is terminated, the IU will be force to error mode through
-a software trap and halt.
-
-The programs are linked with a start-up file, srt0.S. This file includes
-the traptable and window underflow/overflow trap routines.
-
-7. IU and FPU instruction timing.
-
-The simulator provides cycle true simulation. The following table shows
-the emulated instruction timing for 90C601E & 90C602E:
-
-Instructions Cycles
-
-jmpl, rett 2
-load 2
-store 3
-load double 3
-store double 4
-other integer ops 1
-fabs 2
-fadds 4
-faddd 4
-fcmps 4
-fcmpd 4
-fdivs 20
-fdivd 35
-fmovs 2
-fmuls 5
-fmuld 9
-fnegs 2
-fsqrts 37
-fsqrtd 65
-fsubs 4
-fsubd 4
-fdtoi 7
-fdots 3
-fitos 6
-fitod 6
-fstoi 6
-fstod 2
-
-The parallel operation between the IU and FPU is modelled. This means
-that a FPU instruction will execute in parallel with other instructions as
-long as no data or resource dependency is detected. See the 90C602E data
-sheet for the various types of dependencies. Tracing using the 'trace'
-command will display the current simulator time in the left column. This
-time indicates when the instruction is fetched. If a dependency is detetected,
-the following fetch will be delayed until the conflict is resolved.
-
-The load dependency in the 90C601E is also modelled - if the destination
-register of a load instruction is used by the following instruction, an
-idle cycle is inserted.
-
-8. FPU implementation
-
-The simulator maps floating-point operations on the hosts floating point
-capabilities. This means that accuracy and generation of IEEE exceptions is
-host dependent.
README.sis
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Index: erc32.c
===================================================================
--- erc32.c (revision 816)
+++ erc32.c (nonexistent)
@@ -1,1888 +0,0 @@
-/*
- * This file is part of SIS.
- *
- * SIS, SPARC instruction simulator V2.5 Copyright (C) 1995 Jiri Gaisler,
- * European Space Agency
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 675
- * Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-/* The control space devices */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include "sis.h"
-#include "end.h"
-#include "sim-config.h"
-
-extern int ctrl_c;
-extern int32 sis_verbose;
-extern int32 sparclite, sparclite_board;
-extern int rom8,wrp,uben;
-extern char uart_dev1[], uart_dev2[];
-
-int dumbio = 0; /* normal, smart, terminal oriented IO by default */
-
-/* MEC registers */
-#define MEC_START 0x01f80000
-#define MEC_END 0x01f80100
-
-/* Memory exception waitstates */
-#define MEM_EX_WS 1
-
-/* ERC32 always adds one waitstate during RAM std */
-#define STD_WS 1
-
-#ifdef ERRINJ
-extern int errmec;
-#endif
-
-/* The target's byte order is big-endian by default until we load a
- little-endian program. */
-
-int current_target_byte_order = BIG_ENDIAN;
-
-#define MEC_WS 0 /* Waitstates per MEC access (0 ws) */
-#define MOK 0
-
-/* MEC register addresses */
-
-#define MEC_MCR 0x000
-#define MEC_SFR 0x004
-#define MEC_PWDR 0x008
-#define MEC_MEMCFG 0x010
-#define MEC_IOCR 0x014
-#define MEC_WCR 0x018
-
-#define MEC_MAR0 0x020
-#define MEC_MAR1 0x024
-
-#define MEC_SSA1 0x020
-#define MEC_SEA1 0x024
-#define MEC_SSA2 0x028
-#define MEC_SEA2 0x02C
-#define MEC_ISR 0x044
-#define MEC_IPR 0x048
-#define MEC_IMR 0x04C
-#define MEC_ICR 0x050
-#define MEC_IFR 0x054
-#define MEC_WDOG 0x060
-#define MEC_TRAPD 0x064
-#define MEC_RTC_COUNTER 0x080
-#define MEC_RTC_RELOAD 0x080
-#define MEC_RTC_SCALER 0x084
-#define MEC_GPT_COUNTER 0x088
-#define MEC_GPT_RELOAD 0x088
-#define MEC_GPT_SCALER 0x08C
-#define MEC_TIMER_CTRL 0x098
-#define MEC_SFSR 0x0A0
-#define MEC_FFAR 0x0A4
-#define MEC_ERSR 0x0B0
-#define MEC_DBG 0x0C0
-#define MEC_TCR 0x0D0
-
-#define MEC_BRK 0x0C4
-#define MEC_WPR 0x0C8
-
-#define MEC_UARTA 0x0E0
-#define MEC_UARTB 0x0E4
-#define MEC_UART_CTRL 0x0E8
-#define SIM_LOAD 0x0F0
-
-/* Memory exception causes */
-#define PROT_EXC 0x3
-#define UIMP_ACC 0x4
-#define MEC_ACC 0x6
-#define WATCH_EXC 0xa
-#define BREAK_EXC 0xb
-
-/* Size of UART buffers (bytes) */
-#define UARTBUF 1024
-
-/* Number of simulator ticks between flushing the UARTS. */
-/* For good performance, keep above 1000 */
-#define UART_FLUSH_TIME 3000
-
-/* MEC timer control register bits */
-#define TCR_GACR 1
-#define TCR_GACL 2
-#define TCR_GASE 4
-#define TCR_GASL 8
-#define TCR_TCRCR 0x100
-#define TCR_TCRCL 0x200
-#define TCR_TCRSE 0x400
-#define TCR_TCRSL 0x800
-
-/* New uart defines */
-#define UART_TX_TIME 1000
-#define UART_RX_TIME 1000
-#define UARTA_DR 0x1
-#define UARTA_SRE 0x2
-#define UARTA_HRE 0x4
-#define UARTA_OR 0x40
-#define UARTA_CLR 0x80
-#define UARTB_DR 0x10000
-#define UARTB_SRE 0x20000
-#define UARTB_HRE 0x40000
-#define UARTB_OR 0x400000
-#define UARTB_CLR 0x800000
-
-#define UART_DR 0x100
-#define UART_TSE 0x200
-#define UART_THE 0x400
-
-/* MEC registers */
-
-static char fname[256];
-static int32 find = 0;
-static uint32 mec_ssa[2]; /* Write protection start address */
-static uint32 mec_sea[2]; /* Write protection end address */
-static uint32 mec_wpr[2]; /* Write protection control fields */
-static uint32 mec_sfsr;
-static uint32 mec_ffar;
-static uint32 mec_ipr;
-static uint32 mec_imr;
-static uint32 mec_isr;
-static uint32 mec_icr;
-static uint32 mec_ifr;
-static uint32 mec_mcr; /* MEC control register */
-static uint32 mec_memcfg; /* Memory control register */
-static uint32 mec_wcr; /* MEC waitstate register */
-static uint32 mec_iocr; /* MEC IO control register */
-static uint32 posted_irq;
-static uint32 mec_ersr; /* MEC error and status register */
-static uint32 mec_tcr; /* MEC test comtrol register */
-
-static uint32 rtc_counter;
-static uint32 rtc_reload;
-static uint32 rtc_scaler;
-static uint32 rtc_scaler_start;
-static uint32 rtc_enabled;
-static uint32 rtc_cr;
-static uint32 rtc_se;
-
-static uint32 gpt_counter;
-static uint32 gpt_reload;
-static uint32 gpt_scaler;
-static uint32 gpt_scaler_start;
-static uint32 gpt_enabled;
-static uint32 gpt_cr;
-static uint32 gpt_se;
-
-static uint32 wdog_scaler;
-static uint32 wdog_counter;
-static uint32 wdog_rst_delay;
-static uint32 wdog_rston;
-
-enum wdog_type {
- init, disabled, enabled, stopped
-};
-
-static enum wdog_type wdog_status;
-
-
-/* ROM size 1024 Kbyte */
-#define ROM_SZ 0x100000
-#define ROM_MASK 0x0fffff
-
-/* RAM size 4 Mbyte */
-#define RAM_START 0x02000000
-#define RAM_END 0x02400000
-#define RAM_MASK 0x003fffff
-
-/* SPARClite boards all seem to have RAM at the same place. */
-#define RAM_START_SLITE 0x40000000
-#define RAM_END_SLITE 0x40400000
-#define RAM_MASK_SLITE 0x003fffff
-
-/* Memory support variables */
-
-static uint32 mem_ramr_ws; /* RAM read waitstates */
-static uint32 mem_ramw_ws; /* RAM write waitstates */
-static uint32 mem_romr_ws; /* ROM read waitstates */
-static uint32 mem_romw_ws; /* ROM write waitstates */
-static uint32 mem_ramstart; /* RAM start */
-static uint32 mem_ramend; /* RAM end */
-static uint32 mem_rammask; /* RAM address mask */
-static uint32 mem_ramsz; /* RAM size */
-static uint32 mem_romsz; /* ROM size */
-static uint32 mem_accprot; /* RAM write protection enabled */
-static uint32 mem_blockprot; /* RAM block write protection enabled */
-
-static unsigned char romb[ROM_SZ];
-static unsigned char ramb[RAM_END - RAM_START];
-
-
-/* UART support variables */
-
-static int32 fd1, fd2; /* file descriptor for input file */
-static int32 Ucontrol; /* UART status register */
-static unsigned char aq[UARTBUF], bq[UARTBUF];
-static int32 anum, aind = 0;
-static int32 bnum, bind = 0;
-static char wbufa[UARTBUF], wbufb[UARTBUF];
-static unsigned wnuma;
-static unsigned wnumb;
-static FILE *f1in, *f1out, *f2in, *f2out;
-static struct termios ioc1, ioc2, iocold1, iocold2;
-static int f1open = 0, f2open = 0;
-
-static char uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
-static uint32 uart_stat_reg;
-static uint32 uarta_data, uartb_data;
-
-#ifdef ERA
-int era = 0;
-int erareg;
-#endif
-
-/* Forward declarations */
-
-static void decode_ersr PARAMS ((void));
-#ifdef ERRINJ
-static void iucomperr PARAMS ((void));
-#endif
-static void mecparerror PARAMS ((void));
-static void decode_memcfg PARAMS ((void));
-static void decode_wcr PARAMS ((void));
-static void decode_mcr PARAMS ((void));
-static void close_port PARAMS ((void));
-static void mec_reset PARAMS ((void));
-static void mec_intack PARAMS ((int32 level));
-static void chk_irq PARAMS ((void));
-static void mec_irq PARAMS ((int32 level));
-static void set_sfsr PARAMS ((uint32 fault, uint32 addr,
- uint32 asi, uint32 read));
-static int32 mec_read PARAMS ((uint32 addr, uint32 asi, uint32 *data));
-static int mec_write PARAMS ((uint32 addr, uint32 data));
-static void port_init PARAMS ((void));
-static uint32 read_uart PARAMS ((uint32 addr));
-static void write_uart PARAMS ((uint32 addr, uint32 data));
-static void flush_uart PARAMS ((void));
-static void uarta_tx PARAMS ((void));
-static void uartb_tx PARAMS ((void));
-static void uart_rx PARAMS ((caddr_t arg));
-static void uart_intr PARAMS ((caddr_t arg));
-static void uart_irq_start PARAMS ((void));
-static void wdog_intr PARAMS ((caddr_t arg));
-static void wdog_start PARAMS ((void));
-static void rtc_intr PARAMS ((caddr_t arg));
-static void rtc_start PARAMS ((void));
-static uint32 rtc_counter_read PARAMS ((void));
-static void rtc_scaler_set PARAMS ((uint32 val));
-static void rtc_reload_set PARAMS ((uint32 val));
-static void gpt_intr PARAMS ((caddr_t arg));
-static void gpt_start PARAMS ((void));
-static uint32 gpt_counter_read PARAMS ((void));
-static void gpt_scaler_set PARAMS ((uint32 val));
-static void gpt_reload_set PARAMS ((uint32 val));
-static void timer_ctrl PARAMS ((uint32 val));
-static unsigned char *
- get_mem_ptr PARAMS ((uint32 addr, uint32 size));
-
-static void fetch_bytes PARAMS ((int asi, unsigned char *mem,
- uint32 *data, int sz));
-
-static void store_bytes PARAMS ((unsigned char *mem, uint32 *data, int sz));
-
-extern int ext_irl;
-
-
-/* One-time init */
-
-void
-init_sim()
-{
- port_init();
-}
-
-/* Power-on reset init */
-
-void
-reset()
-{
- mec_reset();
- uart_irq_start();
- wdog_start();
-}
-
-static void
-decode_ersr()
-{
- if (mec_ersr & 0x01) {
- if (!(mec_mcr & 0x20)) {
- if (mec_mcr & 0x40) {
- sys_reset();
- mec_ersr = 0x8000;
- if (sis_verbose)
- printf("Error manager reset - IU in error mode\n");
- } else {
- sys_halt();
- mec_ersr |= 0x2000;
- if (sis_verbose)
- printf("Error manager halt - IU in error mode\n");
- }
- } else
- mec_irq(1);
- }
- if (mec_ersr & 0x04) {
- if (!(mec_mcr & 0x200)) {
- if (mec_mcr & 0x400) {
- sys_reset();
- mec_ersr = 0x8000;
- if (sis_verbose)
- printf("Error manager reset - IU comparison error\n");
- } else {
- sys_halt();
- mec_ersr |= 0x2000;
- if (sis_verbose)
- printf("Error manager halt - IU comparison error\n");
- }
- } else
- mec_irq(1);
- }
- if (mec_ersr & 0x20) {
- if (!(mec_mcr & 0x2000)) {
- if (mec_mcr & 0x4000) {
- sys_reset();
- mec_ersr = 0x8000;
- if (sis_verbose)
- printf("Error manager reset - MEC hardware error\n");
- } else {
- sys_halt();
- mec_ersr |= 0x2000;
- if (sis_verbose)
- printf("Error manager halt - MEC hardware error\n");
- }
- } else
- mec_irq(1);
- }
-}
-
-#ifdef ERRINJ
-static void
-iucomperr()
-{
- mec_ersr |= 0x04;
- decode_ersr();
-}
-#endif
-
-static void
-mecparerror()
-{
- mec_ersr |= 0x20;
- decode_ersr();
-}
-
-
-/* IU error mode manager */
-
-void
-error_mode(pc)
- uint32 pc;
-{
-
- mec_ersr |= 0x1;
- decode_ersr();
-}
-
-
-/* Check memory settings */
-
-static void
-decode_memcfg()
-{
- if (rom8) mec_memcfg &= ~0x20000;
- else mec_memcfg |= 0x20000;
-
- mem_ramsz = (256 * 1024) << ((mec_memcfg >> 10) & 7);
- mem_romsz = (128 * 1024) << ((mec_memcfg >> 18) & 7);
-
- if (sparclite_board) {
- mem_ramstart = RAM_START_SLITE;
- mem_ramend = RAM_END_SLITE;
- mem_rammask = RAM_MASK_SLITE;
- }
- else {
- mem_ramstart = RAM_START;
- mem_ramend = RAM_END;
- mem_rammask = RAM_MASK;
- }
- if (sis_verbose)
- printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
- mem_ramstart, mem_ramsz >> 10, mem_romsz >> 10);
-}
-
-static void
-decode_wcr()
-{
- mem_ramr_ws = mec_wcr & 3;
- mem_ramw_ws = (mec_wcr >> 2) & 3;
- mem_romr_ws = (mec_wcr >> 4) & 0x0f;
- if (rom8) {
- if (mem_romr_ws > 0 ) mem_romr_ws--;
- mem_romr_ws = 5 + (4*mem_romr_ws);
- }
- mem_romw_ws = (mec_wcr >> 8) & 0x0f;
- if (sis_verbose)
- printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
- mem_ramr_ws, mem_ramw_ws, mem_romr_ws, mem_romw_ws);
-}
-
-static void
-decode_mcr()
-{
- mem_accprot = (mec_wpr[0] | mec_wpr[1]);
- mem_blockprot = (mec_mcr >> 3) & 1;
- if (sis_verbose && mem_accprot)
- printf("Memory block write protection enabled\n");
- if (mec_mcr & 0x08000) {
- mec_ersr |= 0x20;
- decode_ersr();
- }
- if (sis_verbose && (mec_mcr & 2))
- printf("Software reset enabled\n");
- if (sis_verbose && (mec_mcr & 1))
- printf("Power-down mode enabled\n");
-}
-
-/* Flush ports when simulator stops */
-
-void
-sim_halt()
-{
-#ifdef FAST_UART
- flush_uart();
-#endif
-}
-
-int
-sim_stop(SIM_DESC sd)
-{
- ctrl_c = 1;
- return 1;
-}
-
-static void
-close_port()
-{
- if (f1open && f1in != stdin)
- fclose(f1in);
- if (f2open && f2in != stdin)
- fclose(f2in);
-}
-
-void
-exit_sim()
-{
- close_port();
-}
-
-static void
-mec_reset()
-{
- int i;
-
- find = 0;
- for (i = 0; i < 2; i++)
- mec_ssa[i] = mec_sea[i] = mec_wpr[i] = 0;
- mec_mcr = 0x01350014;
- mec_iocr = 0;
- mec_sfsr = 0x078;
- mec_ffar = 0;
- mec_ipr = 0;
- mec_imr = 0x7ffe;
- mec_isr = 0;
- mec_icr = 0;
- mec_ifr = 0;
- mec_memcfg = 0x10000;
- mec_wcr = -1;
- mec_ersr = 0; /* MEC error and status register */
- mec_tcr = 0; /* MEC test comtrol register */
-
- decode_memcfg();
- decode_wcr();
- decode_mcr();
-
- posted_irq = 0;
- wnuma = wnumb = 0;
- anum = aind = bnum = bind = 0;
-
- uart_stat_reg = UARTA_SRE | UARTA_HRE | UARTB_SRE | UARTB_HRE;
- uarta_data = uartb_data = UART_THE | UART_TSE;
-
- rtc_counter = 0xffffffff;
- rtc_reload = 0xffffffff;
- rtc_scaler = 0xff;
- rtc_enabled = 0;
- rtc_cr = 0;
- rtc_se = 0;
-
- gpt_counter = 0xffffffff;
- gpt_reload = 0xffffffff;
- gpt_scaler = 0xffff;
- gpt_enabled = 0;
- gpt_cr = 0;
- gpt_se = 0;
-
- wdog_scaler = 255;
- wdog_rst_delay = 255;
- wdog_counter = 0xffff;
- wdog_rston = 0;
- wdog_status = init;
-
-#ifdef ERA
- erareg = 0;
-#endif
-
-}
-
-
-
-static void
-mec_intack(level)
- int32 level;
-{
- int irq_test;
-
- if (sis_verbose)
- printf("interrupt %d acknowledged\n", level);
- irq_test = mec_tcr & 0x80000;
- if ((irq_test) && (mec_ifr & (1 << level)))
- mec_ifr &= ~(1 << level);
- else
- mec_ipr &= ~(1 << level);
- chk_irq();
-}
-
-static void
-chk_irq()
-{
- int32 i;
- uint32 itmp;
- int old_irl;
-
- old_irl = ext_irl;
- if (mec_tcr & 0x80000) itmp = mec_ifr;
- else itmp = 0;
- itmp = ((mec_ipr | itmp) & ~mec_imr) & 0x0fffe;
- ext_irl = 0;
- if (itmp != 0) {
- for (i = 15; i > 0; i--) {
- if (((itmp >> i) & 1) != 0) {
- if ((sis_verbose) && (i > old_irl))
- printf("IU irl: %d\n", i);
- ext_irl = i;
- set_int(i, mec_intack, i);
- break;
- }
- }
- }
-}
-
-static void
-mec_irq(level)
- int32 level;
-{
- mec_ipr |= (1 << level);
- chk_irq();
-}
-
-static void
-set_sfsr(fault, addr, asi, read)
- uint32 fault;
- uint32 addr;
- uint32 asi;
- uint32 read;
-{
- if ((asi == 0xa) || (asi == 0xb)) {
- mec_ffar = addr;
- mec_sfsr = (fault << 3) | (!read << 15);
- mec_sfsr |= ((mec_sfsr & 1) ^ 1) | (mec_sfsr & 1);
- switch (asi) {
- case 0xa:
- mec_sfsr |= 0x0004;
- break;
- case 0xb:
- mec_sfsr |= 0x1004;
- break;
- }
- }
-}
-
-static int32
-mec_read(addr, asi, data)
- uint32 addr;
- uint32 asi;
- uint32 *data;
-{
-
- switch (addr & 0x0ff) {
-
- case MEC_MCR: /* 0x00 */
- *data = mec_mcr;
- break;
-
- case MEC_MEMCFG: /* 0x10 */
- *data = mec_memcfg;
- break;
-
- case MEC_IOCR:
- *data = mec_iocr; /* 0x14 */
- break;
-
- case MEC_SSA1: /* 0x20 */
- *data = mec_ssa[0] | (mec_wpr[0] << 23);
- break;
- case MEC_SEA1: /* 0x24 */
- *data = mec_sea[0];
- break;
- case MEC_SSA2: /* 0x28 */
- *data = mec_ssa[1] | (mec_wpr[1] << 23);
- break;
- case MEC_SEA2: /* 0x2c */
- *data = mec_sea[1];
- break;
-
- case MEC_ISR: /* 0x44 */
- *data = mec_isr;
- break;
-
- case MEC_IPR: /* 0x48 */
- *data = mec_ipr;
- break;
-
- case MEC_IMR: /* 0x4c */
- *data = mec_imr;
- break;
-
- case MEC_IFR: /* 0x54 */
- *data = mec_ifr;
- break;
-
- case MEC_RTC_COUNTER: /* 0x80 */
- *data = rtc_counter_read();
- break;
- case MEC_RTC_SCALER: /* 0x84 */
- if (rtc_enabled)
- *data = rtc_scaler - (now() - rtc_scaler_start);
- else
- *data = rtc_scaler;
- break;
-
- case MEC_GPT_COUNTER: /* 0x88 */
- *data = gpt_counter_read();
- break;
-
- case MEC_GPT_SCALER: /* 0x8c */
- if (rtc_enabled)
- *data = gpt_scaler - (now() - gpt_scaler_start);
- else
- *data = gpt_scaler;
- break;
-
-
- case MEC_SFSR: /* 0xA0 */
- *data = mec_sfsr;
- break;
-
- case MEC_FFAR: /* 0xA4 */
- *data = mec_ffar;
- break;
-
- case SIM_LOAD:
- fname[find] = 0;
- if (find == 0)
- strcpy(fname, "simload");
- find = bfd_load(fname);
- if (find == -1)
- *data = 0;
- else
- *data = 1;
- find = 0;
- break;
-
- case MEC_ERSR: /* 0xB0 */
- *data = mec_ersr;
- break;
-
- case MEC_TCR: /* 0xD0 */
- *data = mec_tcr;
- break;
-
- case MEC_UARTA: /* 0xE0 */
- case MEC_UARTB: /* 0xE4 */
- if (asi != 0xb) {
- set_sfsr(MEC_ACC, addr, asi, 1);
- return (1);
- }
- *data = read_uart(addr);
- break;
-
- case MEC_UART_CTRL: /* 0xE8 */
-
- *data = read_uart(addr);
- break;
-
- default:
- set_sfsr(MEC_ACC, addr, asi, 1);
- return (1);
- break;
- }
- return (MOK);
-}
-
-static int
-mec_write(addr, data)
- uint32 addr;
- uint32 data;
-{
- if (sis_verbose > 1)
- printf("MEC write a: %08x, d: %08x\n",addr,data);
- switch (addr & 0x0ff) {
-
- case MEC_MCR:
- mec_mcr = data;
- decode_mcr();
- if (mec_mcr & 0x08000) mecparerror();
- break;
-
- case MEC_SFR:
- if (mec_mcr & 0x2) {
- sys_reset();
- mec_ersr = 0x4000;
- if (sis_verbose)
- printf(" Software reset issued\n");
- }
- break;
-
- case MEC_IOCR:
- mec_iocr = data;
- if (mec_iocr & 0xC0C0C0C0) mecparerror();
- break;
-
- case MEC_SSA1: /* 0x20 */
- if (data & 0xFE000000) mecparerror();
- mec_ssa[0] = data & 0x7fffff;
- mec_wpr[0] = (data >> 23) & 0x03;
- mem_accprot = mec_wpr[0] || mec_wpr[1];
- if (sis_verbose && mec_wpr[0])
- printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
- mec_ssa[0] << 2, mec_sea[0] << 2);
- break;
- case MEC_SEA1: /* 0x24 */
- if (data & 0xFF800000) mecparerror();
- mec_sea[0] = data & 0x7fffff;
- break;
- case MEC_SSA2: /* 0x28 */
- if (data & 0xFE000000) mecparerror();
- mec_ssa[1] = data & 0x7fffff;
- mec_wpr[1] = (data >> 23) & 0x03;
- mem_accprot = mec_wpr[0] || mec_wpr[1];
- if (sis_verbose && mec_wpr[1])
- printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
- mec_ssa[1] << 2, mec_sea[1] << 2);
- break;
- case MEC_SEA2: /* 0x2c */
- if (data & 0xFF800000) mecparerror();
- mec_sea[1] = data & 0x7fffff;
- break;
-
- case MEC_UARTA:
- case MEC_UARTB:
- if (data & 0xFFFFFF00) mecparerror();
- case MEC_UART_CTRL:
- if (data & 0xFF00FF00) mecparerror();
- write_uart(addr, data);
- break;
-
- case MEC_GPT_RELOAD:
- gpt_reload_set(data);
- break;
-
- case MEC_GPT_SCALER:
- if (data & 0xFFFF0000) mecparerror();
- gpt_scaler_set(data);
- break;
-
- case MEC_TIMER_CTRL:
- if (data & 0xFFFFF0F0) mecparerror();
- timer_ctrl(data);
- break;
-
- case MEC_RTC_RELOAD:
- rtc_reload_set(data);
- break;
-
- case MEC_RTC_SCALER:
- if (data & 0xFFFFFF00) mecparerror();
- rtc_scaler_set(data);
- break;
-
- case MEC_SFSR: /* 0xA0 */
- if (data & 0xFFFF0880) mecparerror();
- mec_sfsr = 0x78;
- break;
-
- case MEC_ISR:
- if (data & 0xFFFFE000) mecparerror();
- mec_isr = data;
- break;
-
- case MEC_IMR: /* 0x4c */
-
- if (data & 0xFFFF8001) mecparerror();
- mec_imr = data & 0x7ffe;
- chk_irq();
- break;
-
- case MEC_ICR: /* 0x50 */
-
- if (data & 0xFFFF0001) mecparerror();
- mec_ipr &= ~data & 0x0fffe;
- chk_irq();
- break;
-
- case MEC_IFR: /* 0x54 */
-
- if (mec_tcr & 0x080000) {
- if (data & 0xFFFF0001) mecparerror();
- mec_ifr = data & 0xfffe;
- chk_irq();
- }
- break;
- case SIM_LOAD:
- fname[find++] = (char) data;
- break;
-
-
- case MEC_MEMCFG: /* 0x10 */
- if (data & 0xC0E08000) mecparerror();
- mec_memcfg = data;
- decode_memcfg();
- if (mec_memcfg & 0xc0e08000)
- mecparerror();
- break;
-
- case MEC_WCR: /* 0x18 */
- mec_wcr = data;
- decode_wcr();
- break;
-
- case MEC_ERSR: /* 0xB0 */
- if (mec_tcr & 0x100000)
- if (data & 0xFFFFEFC0) mecparerror();
- mec_ersr = data & 0x103f;
- break;
-
- case MEC_TCR: /* 0xD0 */
- if (data & 0xFFE1FFC0) mecparerror();
- mec_tcr = data & 0x1e003f;
- break;
-
- case MEC_WDOG: /* 0x60 */
- wdog_scaler = (data >> 16) & 0x0ff;
- wdog_counter = data & 0x0ffff;
- wdog_rst_delay = data >> 24;
- wdog_rston = 0;
- if (wdog_status == stopped)
- wdog_start();
- wdog_status = enabled;
- break;
-
- case MEC_TRAPD: /* 0x64 */
- if (wdog_status == init) {
- wdog_status = disabled;
- if (sis_verbose)
- printf("Watchdog disabled\n");
- }
- break;
-
- case MEC_PWDR:
- if (mec_mcr & 1)
- wait_for_irq();
- break;
-
- default:
- set_sfsr(MEC_ACC, addr, 0xb, 0);
- return (1);
- break;
- }
- return (MOK);
-}
-
-
-/* MEC UARTS */
-
-static int ifd1 = -1, ifd2 = -1, ofd1 = -1, ofd2 = -1;
-
-void
-init_stdio()
-{
- if (dumbio)
- return; /* do nothing */
- if (!ifd1)
- tcsetattr(0, TCSANOW, &ioc1);
- if (!ifd2)
- tcsetattr(0, TCSANOW, &ioc2);
-}
-
-void
-restore_stdio()
-{
- if (dumbio)
- return; /* do nothing */
- if (!ifd1)
- tcsetattr(0, TCSANOW, &iocold1);
- if (!ifd2)
- tcsetattr(0, TCSANOW, &iocold2);
-}
-
-#define DO_STDIO_READ( _fd_, _buf_, _len_ ) \
- ( dumbio \
- ? (0) /* no bytes read, no delay */ \
- : read( _fd_, _buf_, _len_ ) )
-
-
-static void
-port_init()
-{
-
- if (uben) {
- f2in = stdin;
- f1in = NULL;
- f2out = stdout;
- f1out = NULL;
- } else {
- f1in = stdin;
- f2in = NULL;
- f1out = stdout;
- f2out = NULL;
- }
- if (uart_dev1[0] != 0)
- if ((fd1 = open(uart_dev1, O_RDWR | O_NONBLOCK)) < 0) {
- printf("Warning, couldn't open output device %s\n", uart_dev1);
- } else {
- if (sis_verbose)
- printf("serial port A on %s\n", uart_dev1);
- f1in = f1out = fdopen(fd1, "r+");
- setbuf(f1out, NULL);
- f1open = 1;
- }
- if (f1in) ifd1 = fileno(f1in);
- if (ifd1 == 0) {
- if (sis_verbose)
- printf("serial port A on stdin/stdout\n");
- if (!dumbio) {
- tcgetattr(ifd1, &ioc1);
- iocold1 = ioc1;
- ioc1.c_lflag &= ~(ICANON | ECHO);
- ioc1.c_cc[VMIN] = 0;
- ioc1.c_cc[VTIME] = 0;
- }
- f1open = 1;
- }
-
- if (f1out) {
- ofd1 = fileno(f1out);
- if (!dumbio && ofd1 == 1) setbuf(f1out, NULL);
- }
-
- if (uart_dev2[0] != 0)
- if ((fd2 = open(uart_dev2, O_RDWR | O_NONBLOCK)) < 0) {
- printf("Warning, couldn't open output device %s\n", uart_dev2);
- } else {
- if (sis_verbose)
- printf("serial port B on %s\n", uart_dev2);
- f2in = f2out = fdopen(fd2, "r+");
- setbuf(f2out, NULL);
- f2open = 1;
- }
- if (f2in) ifd2 = fileno(f2in);
- if (ifd2 == 0) {
- if (sis_verbose)
- printf("serial port B on stdin/stdout\n");
- if (!dumbio) {
- tcgetattr(ifd2, &ioc2);
- iocold2 = ioc2;
- ioc2.c_lflag &= ~(ICANON | ECHO);
- ioc2.c_cc[VMIN] = 0;
- ioc2.c_cc[VTIME] = 0;
- }
- f2open = 1;
- }
-
- if (f2out) {
- ofd2 = fileno(f2out);
- if (!dumbio && ofd2 == 1) setbuf(f2out, NULL);
- }
-
- wnuma = wnumb = 0;
-
-}
-
-static uint32
-read_uart(addr)
- uint32 addr;
-{
-
- unsigned tmp;
-
- tmp = 0;
- switch (addr & 0xff) {
-
- case 0xE0: /* UART 1 */
-#ifndef _WIN32
-#ifdef FAST_UART
-
- if (aind < anum) {
- if ((aind + 1) < anum)
- mec_irq(4);
- return (0x700 | (uint32) aq[aind++]);
- } else {
- if (f1open) {
- anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
- }
- if (anum > 0) {
- aind = 0;
- if ((aind + 1) < anum)
- mec_irq(4);
- return (0x700 | (uint32) aq[aind++]);
- } else {
- return (0x600 | (uint32) aq[aind]);
- }
-
- }
-#else
- tmp = uarta_data;
- uarta_data &= ~UART_DR;
- uart_stat_reg &= ~UARTA_DR;
- return tmp;
-#endif
-#else
- return(0);
-#endif
- break;
-
- case 0xE4: /* UART 2 */
-#ifndef _WIN32
-#ifdef FAST_UART
- if (bind < bnum) {
- if ((bind + 1) < bnum)
- mec_irq(5);
- return (0x700 | (uint32) bq[bind++]);
- } else {
- if (f2open) {
- bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
- }
- if (bnum > 0) {
- bind = 0;
- if ((bind + 1) < bnum)
- mec_irq(5);
- return (0x700 | (uint32) bq[bind++]);
- } else {
- return (0x600 | (uint32) bq[bind]);
- }
-
- }
-#else
- tmp = uartb_data;
- uartb_data &= ~UART_DR;
- uart_stat_reg &= ~UARTB_DR;
- return tmp;
-#endif
-#else
- return(0);
-#endif
- break;
-
- case 0xE8: /* UART status register */
-#ifndef _WIN32
-#ifdef FAST_UART
-
- Ucontrol = 0;
- if (aind < anum) {
- Ucontrol |= 0x00000001;
- } else {
- if (f1open) {
- anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
- }
- if (anum > 0) {
- Ucontrol |= 0x00000001;
- aind = 0;
- mec_irq(4);
- }
- }
- if (bind < bnum) {
- Ucontrol |= 0x00010000;
- } else {
- if (f2open) {
- bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
- }
- if (bnum > 0) {
- Ucontrol |= 0x00010000;
- bind = 0;
- mec_irq(5);
- }
- }
-
- Ucontrol |= 0x00060006;
- return (Ucontrol);
-#else
- return (uart_stat_reg);
-#endif
-#else
- return(0x00060006);
-#endif
- break;
- default:
- if (sis_verbose)
- printf("Read from unimplemented MEC register (%x)\n", addr);
-
- }
- return (0);
-}
-
-static void
-write_uart(addr, data)
- uint32 addr;
- uint32 data;
-{
- unsigned char c;
-
- c = (unsigned char) data;
- switch (addr & 0xff) {
-
- case 0xE0: /* UART A */
-#ifdef FAST_UART
- if (f1open) {
- if (wnuma < UARTBUF)
- wbufa[wnuma++] = c;
- else {
- while (wnuma)
- wnuma -= fwrite(wbufa, 1, wnuma, f1out);
- wbufa[wnuma++] = c;
- }
- }
- mec_irq(4);
-#else
- if (uart_stat_reg & UARTA_SRE) {
- uarta_sreg = c;
- uart_stat_reg &= ~UARTA_SRE;
- event(uarta_tx, 0, UART_TX_TIME);
- } else {
- uarta_hreg = c;
- uart_stat_reg &= ~UARTA_HRE;
- }
-#endif
- break;
-
- case 0xE4: /* UART B */
-#ifdef FAST_UART
- if (f2open) {
- if (wnumb < UARTBUF)
- wbufb[wnumb++] = c;
- else {
- while (wnumb)
- wnumb -= fwrite(wbufb, 1, wnumb, f2out);
- wbufb[wnumb++] = c;
- }
- }
- mec_irq(5);
-#else
- if (uart_stat_reg & UARTB_SRE) {
- uartb_sreg = c;
- uart_stat_reg &= ~UARTB_SRE;
- event(uartb_tx, 0, UART_TX_TIME);
- } else {
- uartb_hreg = c;
- uart_stat_reg &= ~UARTB_HRE;
- }
-#endif
- break;
- case 0xE8: /* UART status register */
-#ifndef FAST_UART
- if (data & UARTA_CLR) {
- uart_stat_reg &= 0xFFFF0000;
- uart_stat_reg |= UARTA_SRE | UARTA_HRE;
- }
- if (data & UARTB_CLR) {
- uart_stat_reg &= 0x0000FFFF;
- uart_stat_reg |= UARTB_SRE | UARTB_HRE;
- }
-#endif
- break;
- default:
- if (sis_verbose)
- printf("Write to unimplemented MEC register (%x)\n", addr);
-
- }
-}
-
-static void
-flush_uart()
-{
- while (wnuma && f1open)
- wnuma -= fwrite(wbufa, 1, wnuma, f1out);
- while (wnumb && f2open)
- wnumb -= fwrite(wbufb, 1, wnumb, f2out);
-}
-
-
-
-static void
-uarta_tx()
-{
-
- while (f1open && fwrite(&uarta_sreg, 1, 1, f1out) != 1);
- if (uart_stat_reg & UARTA_HRE) {
- uart_stat_reg |= UARTA_SRE;
- } else {
- uarta_sreg = uarta_hreg;
- uart_stat_reg |= UARTA_HRE;
- event(uarta_tx, 0, UART_TX_TIME);
- }
- mec_irq(4);
-}
-
-static void
-uartb_tx()
-{
- while (f2open && fwrite(&uartb_sreg, 1, 1, f2out) != 1);
- if (uart_stat_reg & UARTB_HRE) {
- uart_stat_reg |= UARTB_SRE;
- } else {
- uartb_sreg = uartb_hreg;
- uart_stat_reg |= UARTB_HRE;
- event(uartb_tx, 0, UART_TX_TIME);
- }
- mec_irq(5);
-}
-
-static void
-uart_rx(arg)
- caddr_t arg;
-{
- int32 rsize;
- char rxd;
-
-
- rsize = 0;
- if (f1open)
- rsize = DO_STDIO_READ(ifd1, &rxd, 1);
- if (rsize > 0) {
- uarta_data = UART_DR | rxd;
- if (uart_stat_reg & UARTA_HRE)
- uarta_data |= UART_THE;
- if (uart_stat_reg & UARTA_SRE)
- uarta_data |= UART_TSE;
- if (uart_stat_reg & UARTA_DR) {
- uart_stat_reg |= UARTA_OR;
- mec_irq(7); /* UART error interrupt */
- }
- uart_stat_reg |= UARTA_DR;
- mec_irq(4);
- }
- rsize = 0;
- if (f2open)
- rsize = DO_STDIO_READ(ifd2, &rxd, 1);
- if (rsize) {
- uartb_data = UART_DR | rxd;
- if (uart_stat_reg & UARTB_HRE)
- uartb_data |= UART_THE;
- if (uart_stat_reg & UARTB_SRE)
- uartb_data |= UART_TSE;
- if (uart_stat_reg & UARTB_DR) {
- uart_stat_reg |= UARTB_OR;
- mec_irq(7); /* UART error interrupt */
- }
- uart_stat_reg |= UARTB_DR;
- mec_irq(5);
- }
- event(uart_rx, 0, UART_RX_TIME);
-}
-
-static void
-uart_intr(arg)
- caddr_t arg;
-{
- read_uart(0xE8); /* Check for UART interrupts every 1000 clk */
- flush_uart(); /* Flush UART ports */
- event(uart_intr, 0, UART_FLUSH_TIME);
-}
-
-
-static void
-uart_irq_start()
-{
-#ifdef FAST_UART
- event(uart_intr, 0, UART_FLUSH_TIME);
-#else
-#ifndef _WIN32
- event(uart_rx, 0, UART_RX_TIME);
-#endif
-#endif
-}
-
-/* Watch-dog */
-
-static void
-wdog_intr(arg)
- caddr_t arg;
-{
- if (wdog_status == disabled) {
- wdog_status = stopped;
- } else {
-
- if (wdog_counter) {
- wdog_counter--;
- event(wdog_intr, 0, wdog_scaler + 1);
- } else {
- if (wdog_rston) {
- printf("Watchdog reset!\n");
- sys_reset();
- mec_ersr = 0xC000;
- } else {
- mec_irq(15);
- wdog_rston = 1;
- wdog_counter = wdog_rst_delay;
- event(wdog_intr, 0, wdog_scaler + 1);
- }
- }
- }
-}
-
-static void
-wdog_start()
-{
- event(wdog_intr, 0, wdog_scaler + 1);
- if (sis_verbose)
- printf("Watchdog started, scaler = %d, counter = %d\n",
- wdog_scaler, wdog_counter);
-}
-
-
-/* MEC timers */
-
-
-static void
-rtc_intr(arg)
- caddr_t arg;
-{
- if (rtc_counter == 0) {
-
- mec_irq(13);
- if (rtc_cr)
- rtc_counter = rtc_reload;
- else
- rtc_se = 0;
- } else
- rtc_counter -= 1;
- if (rtc_se) {
- event(rtc_intr, 0, rtc_scaler + 1);
- rtc_scaler_start = now();
- rtc_enabled = 1;
- } else {
- if (sis_verbose)
- printf("RTC stopped\n\r");
- rtc_enabled = 0;
- }
-}
-
-static void
-rtc_start()
-{
- if (sis_verbose)
- printf("RTC started (period %d)\n\r", rtc_scaler + 1);
- event(rtc_intr, 0, rtc_scaler + 1);
- rtc_scaler_start = now();
- rtc_enabled = 1;
-}
-
-static uint32
-rtc_counter_read()
-{
- return (rtc_counter);
-}
-
-static void
-rtc_scaler_set(val)
- uint32 val;
-{
- rtc_scaler = val & 0x0ff; /* eight-bit scaler only */
-}
-
-static void
-rtc_reload_set(val)
- uint32 val;
-{
- rtc_reload = val;
-}
-
-static void
-gpt_intr(arg)
- caddr_t arg;
-{
- if (gpt_counter == 0) {
- mec_irq(12);
- if (gpt_cr)
- gpt_counter = gpt_reload;
- else
- gpt_se = 0;
- } else
- gpt_counter -= 1;
- if (gpt_se) {
- event(gpt_intr, 0, gpt_scaler + 1);
- gpt_scaler_start = now();
- gpt_enabled = 1;
- } else {
- if (sis_verbose)
- printf("GPT stopped\n\r");
- gpt_enabled = 0;
- }
-}
-
-static void
-gpt_start()
-{
- if (sis_verbose)
- printf("GPT started (period %d)\n\r", gpt_scaler + 1);
- event(gpt_intr, 0, gpt_scaler + 1);
- gpt_scaler_start = now();
- gpt_enabled = 1;
-}
-
-static uint32
-gpt_counter_read()
-{
- return (gpt_counter);
-}
-
-static void
-gpt_scaler_set(val)
- uint32 val;
-{
- gpt_scaler = val & 0x0ffff; /* 16-bit scaler */
-}
-
-static void
-gpt_reload_set(val)
- uint32 val;
-{
- gpt_reload = val;
-}
-
-static void
-timer_ctrl(val)
- uint32 val;
-{
-
- rtc_cr = ((val & TCR_TCRCR) != 0);
- if (val & TCR_TCRCL) {
- rtc_counter = rtc_reload;
- }
- if (val & TCR_TCRSL) {
- }
- rtc_se = ((val & TCR_TCRSE) != 0);
- if (rtc_se && (rtc_enabled == 0))
- rtc_start();
-
- gpt_cr = (val & TCR_GACR);
- if (val & TCR_GACL) {
- gpt_counter = gpt_reload;
- }
- if (val & TCR_GACL) {
- }
- gpt_se = (val & TCR_GASE) >> 2;
- if (gpt_se && (gpt_enabled == 0))
- gpt_start();
-}
-
-
-/* Retrieve data from target memory. MEM points to location from which
- to read the data; DATA points to words where retrieved data will be
- stored in host byte order. SZ contains log(2) of the number of bytes
- to retrieve, and can be 0 (1 byte), 1 (one half-word), 2 (one word),
- or 3 (two words). */
-
-static void
-fetch_bytes (asi, mem, data, sz)
- int asi;
- unsigned char *mem;
- uint32 *data;
- int sz;
-{
- if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN
- || asi == 8 || asi == 9) {
- switch (sz) {
- case 3:
- data[1] = (((uint32) mem[7]) & 0xff) |
- ((((uint32) mem[6]) & 0xff) << 8) |
- ((((uint32) mem[5]) & 0xff) << 16) |
- ((((uint32) mem[4]) & 0xff) << 24);
- /* Fall through to 2 */
- case 2:
- data[0] = (((uint32) mem[3]) & 0xff) |
- ((((uint32) mem[2]) & 0xff) << 8) |
- ((((uint32) mem[1]) & 0xff) << 16) |
- ((((uint32) mem[0]) & 0xff) << 24);
- break;
- case 1:
- data[0] = (((uint32) mem[1]) & 0xff) |
- ((((uint32) mem[0]) & 0xff) << 8);
- break;
- case 0:
- data[0] = mem[0] & 0xff;
- break;
-
- }
- } else {
- switch (sz) {
- case 3:
- data[1] = ((((uint32) mem[7]) & 0xff) << 24) |
- ((((uint32) mem[6]) & 0xff) << 16) |
- ((((uint32) mem[5]) & 0xff) << 8) |
- (((uint32) mem[4]) & 0xff);
- /* Fall through to 4 */
- case 2:
- data[0] = ((((uint32) mem[3]) & 0xff) << 24) |
- ((((uint32) mem[2]) & 0xff) << 16) |
- ((((uint32) mem[1]) & 0xff) << 8) |
- (((uint32) mem[0]) & 0xff);
- break;
- case 1:
- data[0] = ((((uint32) mem[1]) & 0xff) << 8) |
- (((uint32) mem[0]) & 0xff);
- break;
- case 0:
- data[0] = mem[0] & 0xff;
- break;
- }
- }
-}
-
-
-/* Store data in target byte order. MEM points to location to store data;
- DATA points to words in host byte order to be stored. SZ contains log(2)
- of the number of bytes to retrieve, and can be 0 (1 byte), 1 (one half-word),
- 2 (one word), or 3 (two words). */
-
-static void
-store_bytes (mem, data, sz)
- unsigned char *mem;
- uint32 *data;
- int sz;
-{
- if (CURRENT_TARGET_BYTE_ORDER == LITTLE_ENDIAN) {
- switch (sz) {
- case 3:
- mem[7] = (data[1] >> 24) & 0xff;
- mem[6] = (data[1] >> 16) & 0xff;
- mem[5] = (data[1] >> 8) & 0xff;
- mem[4] = data[1] & 0xff;
- /* Fall through to 2 */
- case 2:
- mem[3] = (data[0] >> 24) & 0xff;
- mem[2] = (data[0] >> 16) & 0xff;
- /* Fall through to 1 */
- case 1:
- mem[1] = (data[0] >> 8) & 0xff;
- /* Fall through to 0 */
- case 0:
- mem[0] = data[0] & 0xff;
- break;
- }
- } else {
- switch (sz) {
- case 3:
- mem[7] = data[1] & 0xff;
- mem[6] = (data[1] >> 8) & 0xff;
- mem[5] = (data[1] >> 16) & 0xff;
- mem[4] = (data[1] >> 24) & 0xff;
- /* Fall through to 2 */
- case 2:
- mem[3] = data[0] & 0xff;
- mem[2] = (data[0] >> 8) & 0xff;
- mem[1] = (data[0] >> 16) & 0xff;
- mem[0] = (data[0] >> 24) & 0xff;
- break;
- case 1:
- mem[1] = data[0] & 0xff;
- mem[0] = (data[0] >> 8) & 0xff;
- break;
- case 0:
- mem[0] = data[0] & 0xff;
- break;
-
- }
- }
-}
-
-
-/* Memory emulation */
-
-int
-memory_read(asi, addr, data, sz, ws)
- int32 asi;
- uint32 addr;
- uint32 *data;
- int32 sz;
- int32 *ws;
-{
- int32 mexc;
-
-#ifdef ERRINJ
- if (errmec) {
- if (sis_verbose)
- printf("Inserted MEC error %d\n",errmec);
- set_sfsr(errmec, addr, asi, 1);
- if (errmec == 5) mecparerror();
- if (errmec == 6) iucomperr();
- errmec = 0;
- return(1);
- }
-#endif;
-
- if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
- fetch_bytes (asi, &ramb[addr & mem_rammask], data, sz);
- *ws = mem_ramr_ws;
- return (0);
- } else if ((addr >= MEC_START) && (addr < MEC_END)) {
- mexc = mec_read(addr, asi, data);
- if (mexc) {
- set_sfsr(MEC_ACC, addr, asi, 1);
- *ws = MEM_EX_WS;
- } else {
- *ws = 0;
- }
- return (mexc);
-
-#ifdef ERA
-
- } else if (era) {
- if ((addr < 0x100000) ||
- ((addr>= 0x80000000) && (addr < 0x80100000))) {
- fetch_bytes (asi, &romb[addr & ROM_MASK], data, sz);
- *ws = 4;
- return (0);
- } else if ((addr >= 0x10000000) &&
- (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
- (mec_iocr & 0x10)) {
- *data = erareg;
- return (0);
- }
-
- } else if (addr < mem_romsz) {
- fetch_bytes (asi, &romb[addr], data, sz);
- *ws = mem_romr_ws;
- return (0);
-
-#else
- } else if (addr < mem_romsz) {
- fetch_bytes (asi, &romb[addr], data, sz);
- *ws = mem_romr_ws;
- return (0);
-#endif
-
- }
-
- printf("Memory exception at %x (illegal address)\n", addr);
- set_sfsr(UIMP_ACC, addr, asi, 1);
- *ws = MEM_EX_WS;
- return (1);
-}
-
-int
-memory_write(asi, addr, data, sz, ws)
- int32 asi;
- uint32 addr;
- uint32 *data;
- int32 sz;
- int32 *ws;
-{
- uint32 byte_addr;
- uint32 byte_mask;
- uint32 waddr;
- uint32 *ram;
- int32 mexc;
- int i;
- int wphit[2];
-
-#ifdef ERRINJ
- if (errmec) {
- if (sis_verbose)
- printf("Inserted MEC error %d\n",errmec);
- set_sfsr(errmec, addr, asi, 0);
- if (errmec == 5) mecparerror();
- if (errmec == 6) iucomperr();
- errmec = 0;
- return(1);
- }
-#endif;
-
- if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
- if (mem_accprot) {
-
- waddr = (addr & 0x7fffff) >> 2;
- for (i = 0; i < 2; i++)
- wphit[i] =
- (((asi == 0xa) && (mec_wpr[i] & 1)) ||
- ((asi == 0xb) && (mec_wpr[i] & 2))) &&
- ((waddr >= mec_ssa[i]) && ((waddr | (sz == 3)) < mec_sea[i]));
-
- if (((mem_blockprot) && (wphit[0] || wphit[1])) ||
- ((!mem_blockprot) &&
- !((mec_wpr[0] && wphit[0]) || (mec_wpr[1] && wphit[1]))
- )) {
- if (sis_verbose)
- printf("Memory access protection error at 0x%08x\n", addr);
- set_sfsr(PROT_EXC, addr, asi, 0);
- *ws = MEM_EX_WS;
- return (1);
- }
- }
-
- store_bytes (&ramb[addr & mem_rammask], data, sz);
-
- switch (sz) {
- case 0:
- case 1:
- *ws = mem_ramw_ws + 3;
- break;
- case 2:
- *ws = mem_ramw_ws;
- break;
- case 3:
- *ws = 2 * mem_ramw_ws + STD_WS;
- break;
- }
- return (0);
- } else if ((addr >= MEC_START) && (addr < MEC_END)) {
- if ((sz != 2) || (asi != 0xb)) {
- set_sfsr(MEC_ACC, addr, asi, 0);
- *ws = MEM_EX_WS;
- return (1);
- }
- mexc = mec_write(addr, *data);
- if (mexc) {
- set_sfsr(MEC_ACC, addr, asi, 0);
- *ws = MEM_EX_WS;
- } else {
- *ws = 0;
- }
- return (mexc);
-
-#ifdef ERA
-
- } else if (era) {
- if ((erareg & 2) &&
- ((addr < 0x100000) || ((addr >= 0x80000000) && (addr < 0x80100000)))) {
- addr &= ROM_MASK;
- *ws = sz == 3 ? 8 : 4;
- store_bytes (&romb[addr], data, sz);
- return (0);
- } else if ((addr >= 0x10000000) &&
- (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
- (mec_iocr & 0x10)) {
- erareg = *data & 0x0e;
- return (0);
- }
-
- } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
- (((mec_memcfg & 0x20000) && (sz > 1)) ||
- (!(mec_memcfg & 0x20000) && (sz == 0)))) {
-
- *ws = mem_romw_ws + 1;
- if (sz == 3)
- *ws += mem_romw_ws + STD_WS;
- store_bytes (&romb[addr], data, sz);
- return (0);
-
-#else
- } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
- (((mec_memcfg & 0x20000) && (sz > 1)) ||
- (!(mec_memcfg & 0x20000) && (sz == 0)))) {
-
- *ws = mem_romw_ws + 1;
- if (sz == 3)
- *ws += mem_romw_ws + STD_WS;
- store_bytes (&romb[addr], data, sz);
- return (0);
-
-#endif
-
- }
-
- *ws = MEM_EX_WS;
- set_sfsr(UIMP_ACC, addr, asi, 0);
- return (1);
-}
-
-static unsigned char *
-get_mem_ptr(addr, size)
- uint32 addr;
- uint32 size;
-{
- if ((addr + size) < ROM_SZ) {
- return (&romb[addr]);
- } else if ((addr >= mem_ramstart) && ((addr + size) < mem_ramend)) {
- return (&ramb[addr & mem_rammask]);
- }
-
-#ifdef ERA
- else if ((era) && ((addr <0x100000) ||
- ((addr >= (unsigned) 0x80000000) && ((addr + size) < (unsigned) 0x80100000)))) {
- return (&romb[addr & ROM_MASK]);
- }
-#endif
-
- return ((char *) -1);
-}
-
-int
-sis_memory_write(addr, data, length)
- uint32 addr;
- char *data;
- uint32 length;
-{
- char *mem;
-
- if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
- return (0);
-
- memcpy(mem, data, length);
- return (length);
-}
-
-int
-sis_memory_read(addr, data, length)
- uint32 addr;
- char *data;
- uint32 length;
-{
- char *mem;
-
- if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
- return (0);
-
- memcpy(data, mem, length);
- return (length);
-}
erc32.c
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: configure.ac
===================================================================
--- configure.ac (revision 816)
+++ configure.ac (nonexistent)
@@ -1,37 +0,0 @@
-dnl Process this file with autoconf to produce a configure script.
-AC_PREREQ(2.59)dnl
-AC_INIT(Makefile.in)
-AC_CONFIG_HEADER(config.h:config.in)
-
-sinclude(../common/aclocal.m4)
-
-# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around
-# it by inlining the macro's contents.
-sinclude(../common/common.m4)
-
-AC_CHECK_HEADERS(stdlib.h)
-
-# In the Cygwin environment, we need some additional flags.
-AC_CACHE_CHECK([for cygwin], sim_cv_os_cygwin,
-[AC_EGREP_CPP(lose, [
-#ifdef __CYGWIN__
-lose
-#endif],[sim_cv_os_cygwin=yes],[sim_cv_os_cygwin=no])])
-
-if test x$sim_cv_os_cygwin = xyes; then
- TERMCAP='`if test -r ../../libtermcap/libtermcap.a; then echo ../../libtermcap/libtermcap.a; else echo -ltermcap; fi` -luser32'
-else
- AC_CHECK_LIB(termcap, main, TERMCAP=-ltermcap, TERMCAP="")
-fi
-AC_SUBST(TERMCAP)
-
-# We prefer the in-tree readline. Top-level dependencies make sure
-# src/readline (if it's there) is configured before src/sim.
-if test -r ../../readline/Makefile; then
- READLINE=../../readline/libreadline.a
-else
- AC_CHECK_LIB(readline, readline, READLINE=-lreadline,
- AC_ERROR([the required "readline" library is missing]), $TERMCAP)
-fi
-AC_SUBST(READLINE)
-SIM_AC_OUTPUT
configure.ac
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: exec.c
===================================================================
--- exec.c (revision 816)
+++ exec.c (nonexistent)
@@ -1,2043 +0,0 @@
-/*
- * This file is part of SIS.
- *
- * SIS, SPARC instruction simulator V1.8 Copyright (C) 1995 Jiri Gaisler,
- * European Space Agency
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 675
- * Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include "sis.h"
-#include "end.h"
-#include
-#include
-
-extern int32 sis_verbose, sparclite;
-int ext_irl = 0;
-
-/* Load/store interlock delay */
-#define FLSTHOLD 1
-
-/* Load delay (delete if unwanted - speeds up simulation) */
-#define LOAD_DEL 1
-
-#define T_LD 2
-#define T_LDD 3
-#define T_ST 3
-#define T_STD 4
-#define T_LDST 4
-#define T_JMPL 2
-#define T_RETT 2
-
-#define FSR_QNE 0x2000
-#define FP_EXE_MODE 0
-#define FP_EXC_PE 1
-#define FP_EXC_MODE 2
-
-#define FBA 8
-#define FBN 0
-#define FBNE 1
-#define FBLG 2
-#define FBUL 3
-#define FBL 4
-#define FBUG 5
-#define FBG 6
-#define FBU 7
-#define FBA 8
-#define FBE 9
-#define FBUE 10
-#define FBGE 11
-#define FBUGE 12
-#define FBLE 13
-#define FBULE 14
-#define FBO 15
-
-#define FCC_E 0
-#define FCC_L 1
-#define FCC_G 2
-#define FCC_U 3
-
-#define PSR_ET 0x20
-#define PSR_EF 0x1000
-#define PSR_PS 0x40
-#define PSR_S 0x80
-#define PSR_N 0x0800000
-#define PSR_Z 0x0400000
-#define PSR_V 0x0200000
-#define PSR_C 0x0100000
-#define PSR_CC 0x0F00000
-#define PSR_CWP 0x7
-#define PSR_PIL 0x0f00
-
-#define ICC_N (icc >> 3)
-#define ICC_Z (icc >> 2)
-#define ICC_V (icc >> 1)
-#define ICC_C (icc)
-
-#define FP_PRES (sregs->fpu_pres)
-
-#define TRAP_IEXC 1
-#define TRAP_UNIMP 2
-#define TRAP_PRIVI 3
-#define TRAP_FPDIS 4
-#define TRAP_WOFL 5
-#define TRAP_WUFL 6
-#define TRAP_UNALI 7
-#define TRAP_FPEXC 8
-#define TRAP_DEXC 9
-#define TRAP_TAG 10
-#define TRAP_DIV0 0x2a
-
-#define FSR_TT 0x1C000
-#define FP_IEEE 0x04000
-#define FP_UNIMP 0x0C000
-#define FP_SEQ_ERR 0x10000
-
-#define BICC_BN 0
-#define BICC_BE 1
-#define BICC_BLE 2
-#define BICC_BL 3
-#define BICC_BLEU 4
-#define BICC_BCS 5
-#define BICC_NEG 6
-#define BICC_BVS 7
-#define BICC_BA 8
-#define BICC_BNE 9
-#define BICC_BG 10
-#define BICC_BGE 11
-#define BICC_BGU 12
-#define BICC_BCC 13
-#define BICC_POS 14
-#define BICC_BVC 15
-
-#define INST_SIMM13 0x1fff
-#define INST_RS2 0x1f
-#define INST_I 0x2000
-#define ADD 0x00
-#define ADDCC 0x10
-#define ADDX 0x08
-#define ADDXCC 0x18
-#define TADDCC 0x20
-#define TSUBCC 0x21
-#define TADDCCTV 0x22
-#define TSUBCCTV 0x23
-#define IAND 0x01
-#define IANDCC 0x11
-#define IANDN 0x05
-#define IANDNCC 0x15
-#define MULScc 0x24
-#define DIVScc 0x1D
-#define SMUL 0x0B
-#define SMULCC 0x1B
-#define UMUL 0x0A
-#define UMULCC 0x1A
-#define SDIV 0x0F
-#define SDIVCC 0x1F
-#define UDIV 0x0E
-#define UDIVCC 0x1E
-#define IOR 0x02
-#define IORCC 0x12
-#define IORN 0x06
-#define IORNCC 0x16
-#define SLL 0x25
-#define SRA 0x27
-#define SRL 0x26
-#define SUB 0x04
-#define SUBCC 0x14
-#define SUBX 0x0C
-#define SUBXCC 0x1C
-#define IXNOR 0x07
-#define IXNORCC 0x17
-#define IXOR 0x03
-#define IXORCC 0x13
-#define SETHI 0x04
-#define BICC 0x02
-#define FPBCC 0x06
-#define RDY 0x28
-#define RDPSR 0x29
-#define RDWIM 0x2A
-#define RDTBR 0x2B
-#define SCAN 0x2C
-#define WRY 0x30
-#define WRPSR 0x31
-#define WRWIM 0x32
-#define WRTBR 0x33
-#define JMPL 0x38
-#define RETT 0x39
-#define TICC 0x3A
-#define SAVE 0x3C
-#define RESTORE 0x3D
-#define LDD 0x03
-#define LDDA 0x13
-#define LD 0x00
-#define LDA 0x10
-#define LDF 0x20
-#define LDDF 0x23
-#define LDSTUB 0x0D
-#define LDSTUBA 0x1D
-#define LDUB 0x01
-#define LDUBA 0x11
-#define LDSB 0x09
-#define LDSBA 0x19
-#define LDUH 0x02
-#define LDUHA 0x12
-#define LDSH 0x0A
-#define LDSHA 0x1A
-#define LDFSR 0x21
-#define ST 0x04
-#define STA 0x14
-#define STB 0x05
-#define STBA 0x15
-#define STD 0x07
-#define STDA 0x17
-#define STF 0x24
-#define STDFQ 0x26
-#define STDF 0x27
-#define STFSR 0x25
-#define STH 0x06
-#define STHA 0x16
-#define SWAP 0x0F
-#define SWAPA 0x1F
-#define FLUSH 0x3B
-
-#define SIGN_BIT 0x80000000
-
-/* # of cycles overhead when a trap is taken */
-#define TRAP_C 3
-
-/* Forward declarations */
-
-static uint32 sub_cc PARAMS ((uint32 psr, int32 operand1, int32 operand2,
- int32 result));
-static uint32 add_cc PARAMS ((uint32 psr, int32 operand1, int32 operand2,
- int32 result));
-static void log_cc PARAMS ((int32 result, struct pstate *sregs));
-static int fpexec PARAMS ((uint32 op3, uint32 rd, uint32 rs1, uint32 rs2,
- struct pstate *sregs));
-static int chk_asi PARAMS ((struct pstate *sregs, uint32 *asi, uint32 op3));
-
-
-extern struct estate ebase;
-extern int32 nfp,ift;
-
-#ifdef ERRINJ
-extern uint32 errtt, errftt;
-#endif
-
-static uint32
-sub_cc(psr, operand1, operand2, result)
- uint32 psr;
- int32 operand1;
- int32 operand2;
- int32 result;
-{
- psr = ((psr & ~PSR_N) | ((result >> 8) & PSR_N));
- if (result)
- psr &= ~PSR_Z;
- else
- psr |= PSR_Z;
- psr = (psr & ~PSR_V) | ((((operand1 & ~operand2 & ~result) |
- (~operand1 & operand2 & result)) >> 10) & PSR_V);
- psr = (psr & ~PSR_C) | ((((~operand1 & operand2) |
- ((~operand1 | operand2) & result)) >> 11) & PSR_C);
- return (psr);
-}
-
-uint32
-add_cc(psr, operand1, operand2, result)
- uint32 psr;
- int32 operand1;
- int32 operand2;
- int32 result;
-{
- psr = ((psr & ~PSR_N) | ((result >> 8) & PSR_N));
- if (result)
- psr &= ~PSR_Z;
- else
- psr |= PSR_Z;
- psr = (psr & ~PSR_V) | ((((operand1 & operand2 & ~result) |
- (~operand1 & ~operand2 & result)) >> 10) & PSR_V);
- psr = (psr & ~PSR_C) | ((((operand1 & operand2) |
- ((operand1 | operand2) & ~result)) >> 11) & PSR_C);
- return(psr);
-}
-
-static void
-log_cc(result, sregs)
- int32 result;
- struct pstate *sregs;
-{
- sregs->psr &= ~(PSR_CC); /* Zero CC bits */
- sregs->psr = (sregs->psr | ((result >> 8) & PSR_N));
- if (result == 0)
- sregs->psr |= PSR_Z;
-}
-
-/* Add two unsigned 32-bit integers, and calculate the carry out. */
-
-static uint32
-add32 (uint32 n1, uint32 n2, int *carry)
-{
- uint32 result = n1 + n2;
-
- *carry = result < n1 || result < n1;
- return(result);
-}
-
-/* Multiply two 32-bit integers. */
-
-static void
-mul64 (uint32 n1, uint32 n2, uint32 *result_hi, uint32 *result_lo, int msigned)
-{
- uint32 lo, mid1, mid2, hi, reg_lo, reg_hi;
- int carry;
- int sign = 0;
-
- /* If this is a signed multiply, calculate the sign of the result
- and make the operands positive. */
- if (msigned)
- {
- sign = (n1 ^ n2) & SIGN_BIT;
- if (n1 & SIGN_BIT)
- n1 = -n1;
- if (n2 & SIGN_BIT)
- n2 = -n2;
-
- }
-
- /* We can split the 32x32 into four 16x16 operations. This ensures
- that we do not lose precision on 32bit only hosts: */
- lo = ((n1 & 0xFFFF) * (n2 & 0xFFFF));
- mid1 = ((n1 & 0xFFFF) * ((n2 >> 16) & 0xFFFF));
- mid2 = (((n1 >> 16) & 0xFFFF) * (n2 & 0xFFFF));
- hi = (((n1 >> 16) & 0xFFFF) * ((n2 >> 16) & 0xFFFF));
-
- /* We now need to add all of these results together, taking care
- to propogate the carries from the additions: */
- reg_lo = add32 (lo, (mid1 << 16), &carry);
- reg_hi = carry;
- reg_lo = add32 (reg_lo, (mid2 << 16), &carry);
- reg_hi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
-
- /* Negate result if necessary. */
- if (sign)
- {
- reg_hi = ~ reg_hi;
- reg_lo = - reg_lo;
- if (reg_lo == 0)
- reg_hi++;
- }
-
- *result_lo = reg_lo;
- *result_hi = reg_hi;
-}
-
-
-/* Divide a 64-bit integer by a 32-bit integer. We cheat and assume
- that the host compiler supports long long operations. */
-
-static void
-div64 (uint32 n1_hi, uint32 n1_low, uint32 n2, uint32 *result, int msigned)
-{
- uint64 n1;
-
- n1 = ((uint64) n1_hi) << 32;
- n1 |= ((uint64) n1_low) & 0xffffffff;
-
- if (msigned)
- {
- int64 n1_s = (int64) n1;
- int32 n2_s = (int32) n2;
- n1_s = n1_s / n2_s;
- n1 = (uint64) n1_s;
- }
- else
- n1 = n1 / n2;
-
- *result = (uint32) (n1 & 0xffffffff);
-}
-
-
-int
-dispatch_instruction(sregs)
- struct pstate *sregs;
-{
-
- uint32 cwp, op, op2, op3, asi, rd, cond, rs1,
- rs2;
- uint32 ldep, icc;
- int32 operand1, operand2, *rdd, result, eicc,
- new_cwp;
- int32 pc, npc, data, address, ws, mexc, fcc;
- int32 ddata[2];
-
- sregs->ninst++;
- cwp = ((sregs->psr & PSR_CWP) << 4);
- op = sregs->inst >> 30;
- pc = sregs->npc;
- npc = sregs->npc + 4;
- op3 = rd = rs1 = operand2 = eicc = 0;
- rdd = 0;
- if (op & 2) {
-
- op3 = (sregs->inst >> 19) & 0x3f;
- rs1 = (sregs->inst >> 14) & 0x1f;
- rd = (sregs->inst >> 25) & 0x1f;
-
-#ifdef LOAD_DEL
-
- /* Check if load dependecy is possible */
- if (ebase.simtime <= sregs->ildtime)
- ldep = (((op3 & 0x38) != 0x28) && ((op3 & 0x3e) != 0x34) && (sregs->ildreg != 0));
- else
- ldep = 0;
- if (sregs->inst & INST_I) {
- if (ldep && (sregs->ildreg == rs1))
- sregs->hold++;
- operand2 = sregs->inst;
- operand2 = ((operand2 << 19) >> 19); /* sign extend */
- } else {
- rs2 = sregs->inst & INST_RS2;
- if (rs2 > 7)
- operand2 = sregs->r[(cwp + rs2) & 0x7f];
- else
- operand2 = sregs->g[rs2];
- if (ldep && ((sregs->ildreg == rs1) || (sregs->ildreg == rs2)))
- sregs->hold++;
- }
-#else
- if (sregs->inst & INST_I) {
- operand2 = sregs->inst;
- operand2 = ((operand2 << 19) >> 19); /* sign extend */
- } else {
- rs2 = sregs->inst & INST_RS2;
- if (rs2 > 7)
- operand2 = sregs->r[(cwp + rs2) & 0x7f];
- else
- operand2 = sregs->g[rs2];
- }
-#endif
-
- if (rd > 7)
- rdd = &(sregs->r[(cwp + rd) & 0x7f]);
- else
- rdd = &(sregs->g[rd]);
- if (rs1 > 7)
- rs1 = sregs->r[(cwp + rs1) & 0x7f];
- else
- rs1 = sregs->g[rs1];
- }
- switch (op) {
- case 0:
- op2 = (sregs->inst >> 22) & 0x7;
- switch (op2) {
- case SETHI:
- rd = (sregs->inst >> 25) & 0x1f;
- if (rd > 7)
- rdd = &(sregs->r[(cwp + rd) & 0x7f]);
- else
- rdd = &(sregs->g[rd]);
- *rdd = sregs->inst << 10;
- break;
- case BICC:
-#ifdef STAT
- sregs->nbranch++;
-#endif
- icc = sregs->psr >> 20;
- cond = ((sregs->inst >> 25) & 0x0f);
- switch (cond) {
- case BICC_BN:
- eicc = 0;
- break;
- case BICC_BE:
- eicc = ICC_Z;
- break;
- case BICC_BLE:
- eicc = ICC_Z | (ICC_N ^ ICC_V);
- break;
- case BICC_BL:
- eicc = (ICC_N ^ ICC_V);
- break;
- case BICC_BLEU:
- eicc = ICC_C | ICC_Z;
- break;
- case BICC_BCS:
- eicc = ICC_C;
- break;
- case BICC_NEG:
- eicc = ICC_N;
- break;
- case BICC_BVS:
- eicc = ICC_V;
- break;
- case BICC_BA:
- eicc = 1;
- if (sregs->inst & 0x20000000)
- sregs->annul = 1;
- break;
- case BICC_BNE:
- eicc = ~(ICC_Z);
- break;
- case BICC_BG:
- eicc = ~(ICC_Z | (ICC_N ^ ICC_V));
- break;
- case BICC_BGE:
- eicc = ~(ICC_N ^ ICC_V);
- break;
- case BICC_BGU:
- eicc = ~(ICC_C | ICC_Z);
- break;
- case BICC_BCC:
- eicc = ~(ICC_C);
- break;
- case BICC_POS:
- eicc = ~(ICC_N);
- break;
- case BICC_BVC:
- eicc = ~(ICC_V);
- break;
- }
- if (eicc & 1) {
- operand1 = sregs->inst;
- operand1 = ((operand1 << 10) >> 8); /* sign extend */
- npc = sregs->pc + operand1;
- } else {
- if (sregs->inst & 0x20000000)
- sregs->annul = 1;
- }
- break;
- case FPBCC:
-#ifdef STAT
- sregs->nbranch++;
-#endif
- if (!((sregs->psr & PSR_EF) && FP_PRES)) {
- sregs->trap = TRAP_FPDIS;
- break;
- }
- if (ebase.simtime < sregs->ftime) {
- sregs->ftime = ebase.simtime + sregs->hold;
- }
- cond = ((sregs->inst >> 25) & 0x0f);
- fcc = (sregs->fsr >> 10) & 0x3;
- switch (cond) {
- case FBN:
- eicc = 0;
- break;
- case FBNE:
- eicc = (fcc != FCC_E);
- break;
- case FBLG:
- eicc = (fcc == FCC_L) || (fcc == FCC_G);
- break;
- case FBUL:
- eicc = (fcc == FCC_L) || (fcc == FCC_U);
- break;
- case FBL:
- eicc = (fcc == FCC_L);
- break;
- case FBUG:
- eicc = (fcc == FCC_G) || (fcc == FCC_U);
- break;
- case FBG:
- eicc = (fcc == FCC_G);
- break;
- case FBU:
- eicc = (fcc == FCC_U);
- break;
- case FBA:
- eicc = 1;
- if (sregs->inst & 0x20000000)
- sregs->annul = 1;
- break;
- case FBE:
- eicc = !(fcc != FCC_E);
- break;
- case FBUE:
- eicc = !((fcc == FCC_L) || (fcc == FCC_G));
- break;
- case FBGE:
- eicc = !((fcc == FCC_L) || (fcc == FCC_U));
- break;
- case FBUGE:
- eicc = !(fcc == FCC_L);
- break;
- case FBLE:
- eicc = !((fcc == FCC_G) || (fcc == FCC_U));
- break;
- case FBULE:
- eicc = !(fcc == FCC_G);
- break;
- case FBO:
- eicc = !(fcc == FCC_U);
- break;
- }
- if (eicc) {
- operand1 = sregs->inst;
- operand1 = ((operand1 << 10) >> 8); /* sign extend */
- npc = sregs->pc + operand1;
- } else {
- if (sregs->inst & 0x20000000)
- sregs->annul = 1;
- }
- break;
-
- default:
- sregs->trap = TRAP_UNIMP;
- break;
- }
- break;
- case 1: /* CALL */
-#ifdef STAT
- sregs->nbranch++;
-#endif
- sregs->r[(cwp + 15) & 0x7f] = sregs->pc;
- npc = sregs->pc + (sregs->inst << 2);
- break;
-
- case 2:
- if ((op3 >> 1) == 0x1a) {
- if (!((sregs->psr & PSR_EF) && FP_PRES)) {
- sregs->trap = TRAP_FPDIS;
- } else {
- rs1 = (sregs->inst >> 14) & 0x1f;
- rs2 = sregs->inst & 0x1f;
- sregs->trap = fpexec(op3, rd, rs1, rs2, sregs);
- }
- } else {
-
- switch (op3) {
- case TICC:
- icc = sregs->psr >> 20;
- cond = ((sregs->inst >> 25) & 0x0f);
- switch (cond) {
- case BICC_BN:
- eicc = 0;
- break;
- case BICC_BE:
- eicc = ICC_Z;
- break;
- case BICC_BLE:
- eicc = ICC_Z | (ICC_N ^ ICC_V);
- break;
- case BICC_BL:
- eicc = (ICC_N ^ ICC_V);
- break;
- case BICC_BLEU:
- eicc = ICC_C | ICC_Z;
- break;
- case BICC_BCS:
- eicc = ICC_C;
- break;
- case BICC_NEG:
- eicc = ICC_N;
- break;
- case BICC_BVS:
- eicc = ICC_V;
- break;
- case BICC_BA:
- eicc = 1;
- break;
- case BICC_BNE:
- eicc = ~(ICC_Z);
- break;
- case BICC_BG:
- eicc = ~(ICC_Z | (ICC_N ^ ICC_V));
- break;
- case BICC_BGE:
- eicc = ~(ICC_N ^ ICC_V);
- break;
- case BICC_BGU:
- eicc = ~(ICC_C | ICC_Z);
- break;
- case BICC_BCC:
- eicc = ~(ICC_C);
- break;
- case BICC_POS:
- eicc = ~(ICC_N);
- break;
- case BICC_BVC:
- eicc = ~(ICC_V);
- break;
- }
- if (eicc & 1) {
- sregs->trap = (0x80 | ((rs1 + operand2) & 0x7f));
- }
- break;
-
- case MULScc:
- operand1 =
- (((sregs->psr & PSR_V) ^ ((sregs->psr & PSR_N) >> 2))
- << 10) | (rs1 >> 1);
- if ((sregs->y & 1) == 0)
- operand2 = 0;
- *rdd = operand1 + operand2;
- sregs->y = (rs1 << 31) | (sregs->y >> 1);
- sregs->psr = add_cc(sregs->psr, operand1, operand2, *rdd);
- break;
- case DIVScc:
- {
- int sign;
- uint32 result, remainder;
- int c0, y31;
-
- if (!sparclite) {
- sregs->trap = TRAP_UNIMP;
- break;
- }
-
- sign = ((sregs->psr & PSR_V) != 0) ^ ((sregs->psr & PSR_N) != 0);
-
- remainder = (sregs->y << 1) | (rs1 >> 31);
-
- /* If true sign is positive, calculate remainder - divisor.
- Otherwise, calculate remainder + divisor. */
- if (sign == 0)
- operand2 = ~operand2 + 1;
- result = remainder + operand2;
-
- /* The SPARClite User's Manual is not clear on how
- the "carry out" of the above ALU operation is to
- be calculated. From trial and error tests
- on the the chip itself, it appears that it is
- a normal addition carry, and not a subtraction borrow,
- even in cases where the divisor is subtracted
- from the remainder. FIXME: get the true story
- from Fujitsu. */
- c0 = result < (uint32) remainder
- || result < (uint32) operand2;
-
- if (result & 0x80000000)
- sregs->psr |= PSR_N;
- else
- sregs->psr &= ~PSR_N;
-
- y31 = (sregs->y & 0x80000000) == 0x80000000;
-
- if (result == 0 && sign == y31)
- sregs->psr |= PSR_Z;
- else
- sregs->psr &= ~PSR_Z;
-
- sign = (sign && !y31) || (!c0 && (sign || !y31));
-
- if (sign ^ (result >> 31))
- sregs->psr |= PSR_V;
- else
- sregs->psr &= ~PSR_V;
-
- if (!sign)
- sregs->psr |= PSR_C;
- else
- sregs->psr &= ~PSR_C;
-
- sregs->y = result;
-
- if (rd != 0)
- *rdd = (rs1 << 1) | !sign;
- }
- break;
- case SMUL:
- {
- mul64 (rs1, operand2, &sregs->y, rdd, 1);
- }
- break;
- case SMULCC:
- {
- uint32 result;
-
- mul64 (rs1, operand2, &sregs->y, &result, 1);
-
- if (result & 0x80000000)
- sregs->psr |= PSR_N;
- else
- sregs->psr &= ~PSR_N;
-
- if (result == 0)
- sregs->psr |= PSR_Z;
- else
- sregs->psr &= ~PSR_Z;
-
- *rdd = result;
- }
- break;
- case UMUL:
- {
- mul64 (rs1, operand2, &sregs->y, rdd, 0);
- }
- break;
- case UMULCC:
- {
- uint32 result;
-
- mul64 (rs1, operand2, &sregs->y, &result, 0);
-
- if (result & 0x80000000)
- sregs->psr |= PSR_N;
- else
- sregs->psr &= ~PSR_N;
-
- if (result == 0)
- sregs->psr |= PSR_Z;
- else
- sregs->psr &= ~PSR_Z;
-
- *rdd = result;
- }
- break;
- case SDIV:
- {
- if (sparclite) {
- sregs->trap = TRAP_UNIMP;
- break;
- }
-
- if (operand2 == 0) {
- sregs->trap = TRAP_DIV0;
- break;
- }
-
- div64 (sregs->y, rs1, operand2, rdd, 1);
- }
- break;
- case SDIVCC:
- {
- uint32 result;
-
- if (sparclite) {
- sregs->trap = TRAP_UNIMP;
- break;
- }
-
- if (operand2 == 0) {
- sregs->trap = TRAP_DIV0;
- break;
- }
-
- div64 (sregs->y, rs1, operand2, &result, 1);
-
- if (result & 0x80000000)
- sregs->psr |= PSR_N;
- else
- sregs->psr &= ~PSR_N;
-
- if (result == 0)
- sregs->psr |= PSR_Z;
- else
- sregs->psr &= ~PSR_Z;
-
- /* FIXME: should set overflow flag correctly. */
- sregs->psr &= ~(PSR_C | PSR_V);
-
- *rdd = result;
- }
- break;
- case UDIV:
- {
- if (sparclite) {
- sregs->trap = TRAP_UNIMP;
- break;
- }
-
- if (operand2 == 0) {
- sregs->trap = TRAP_DIV0;
- break;
- }
-
- div64 (sregs->y, rs1, operand2, rdd, 0);
- }
- break;
- case UDIVCC:
- {
- uint32 result;
-
- if (sparclite) {
- sregs->trap = TRAP_UNIMP;
- break;
- }
-
- if (operand2 == 0) {
- sregs->trap = TRAP_DIV0;
- break;
- }
-
- div64 (sregs->y, rs1, operand2, &result, 0);
-
- if (result & 0x80000000)
- sregs->psr |= PSR_N;
- else
- sregs->psr &= ~PSR_N;
-
- if (result == 0)
- sregs->psr |= PSR_Z;
- else
- sregs->psr &= ~PSR_Z;
-
- /* FIXME: should set overflow flag correctly. */
- sregs->psr &= ~(PSR_C | PSR_V);
-
- *rdd = result;
- }
- break;
- case IXNOR:
- *rdd = rs1 ^ ~operand2;
- break;
- case IXNORCC:
- *rdd = rs1 ^ ~operand2;
- log_cc(*rdd, sregs);
- break;
- case IXOR:
- *rdd = rs1 ^ operand2;
- break;
- case IXORCC:
- *rdd = rs1 ^ operand2;
- log_cc(*rdd, sregs);
- break;
- case IOR:
- *rdd = rs1 | operand2;
- break;
- case IORCC:
- *rdd = rs1 | operand2;
- log_cc(*rdd, sregs);
- break;
- case IORN:
- *rdd = rs1 | ~operand2;
- break;
- case IORNCC:
- *rdd = rs1 | ~operand2;
- log_cc(*rdd, sregs);
- break;
- case IANDNCC:
- *rdd = rs1 & ~operand2;
- log_cc(*rdd, sregs);
- break;
- case IANDN:
- *rdd = rs1 & ~operand2;
- break;
- case IAND:
- *rdd = rs1 & operand2;
- break;
- case IANDCC:
- *rdd = rs1 & operand2;
- log_cc(*rdd, sregs);
- break;
- case SUB:
- *rdd = rs1 - operand2;
- break;
- case SUBCC:
- *rdd = rs1 - operand2;
- sregs->psr = sub_cc(sregs->psr, rs1, operand2, *rdd);
- break;
- case SUBX:
- *rdd = rs1 - operand2 - ((sregs->psr >> 20) & 1);
- break;
- case SUBXCC:
- *rdd = rs1 - operand2 - ((sregs->psr >> 20) & 1);
- sregs->psr = sub_cc(sregs->psr, rs1, operand2, *rdd);
- break;
- case ADD:
- *rdd = rs1 + operand2;
- break;
- case ADDCC:
- *rdd = rs1 + operand2;
- sregs->psr = add_cc(sregs->psr, rs1, operand2, *rdd);
- break;
- case ADDX:
- *rdd = rs1 + operand2 + ((sregs->psr >> 20) & 1);
- break;
- case ADDXCC:
- *rdd = rs1 + operand2 + ((sregs->psr >> 20) & 1);
- sregs->psr = add_cc(sregs->psr, rs1, operand2, *rdd);
- break;
- case TADDCC:
- *rdd = rs1 + operand2;
- sregs->psr = add_cc(sregs->psr, rs1, operand2, *rdd);
- if ((rs1 | operand2) & 0x3)
- sregs->psr |= PSR_V;
- break;
- case TSUBCC:
- *rdd = rs1 - operand2;
- sregs->psr = sub_cc (sregs->psr, rs1, operand2, *rdd);
- if ((rs1 | operand2) & 0x3)
- sregs->psr |= PSR_V;
- break;
- case TADDCCTV:
- *rdd = rs1 + operand2;
- result = add_cc(0, rs1, operand2, *rdd);
- if ((rs1 | operand2) & 0x3)
- result |= PSR_V;
- if (result & PSR_V) {
- sregs->trap = TRAP_TAG;
- } else {
- sregs->psr = (sregs->psr & ~PSR_CC) | result;
- }
- break;
- case TSUBCCTV:
- *rdd = rs1 - operand2;
- result = add_cc (0, rs1, operand2, *rdd);
- if ((rs1 | operand2) & 0x3)
- result |= PSR_V;
- if (result & PSR_V)
- {
- sregs->trap = TRAP_TAG;
- }
- else
- {
- sregs->psr = (sregs->psr & ~PSR_CC) | result;
- }
- break;
- case SLL:
- *rdd = rs1 << (operand2 & 0x1f);
- break;
- case SRL:
- *rdd = rs1 >> (operand2 & 0x1f);
- break;
- case SRA:
- *rdd = ((int) rs1) >> (operand2 & 0x1f);
- break;
- case FLUSH:
- if (ift) sregs->trap = TRAP_UNIMP;
- break;
- case SAVE:
- new_cwp = ((sregs->psr & PSR_CWP) - 1) & PSR_CWP;
- if (sregs->wim & (1 << new_cwp)) {
- sregs->trap = TRAP_WOFL;
- break;
- }
- if (rd > 7)
- rdd = &(sregs->r[((new_cwp << 4) + rd) & 0x7f]);
- *rdd = rs1 + operand2;
- sregs->psr = (sregs->psr & ~PSR_CWP) | new_cwp;
- break;
- case RESTORE:
-
- new_cwp = ((sregs->psr & PSR_CWP) + 1) & PSR_CWP;
- if (sregs->wim & (1 << new_cwp)) {
- sregs->trap = TRAP_WUFL;
- break;
- }
- if (rd > 7)
- rdd = &(sregs->r[((new_cwp << 4) + rd) & 0x7f]);
- *rdd = rs1 + operand2;
- sregs->psr = (sregs->psr & ~PSR_CWP) | new_cwp;
- break;
- case RDPSR:
- if (!(sregs->psr & PSR_S)) {
- sregs->trap = TRAP_PRIVI;
- break;
- }
- *rdd = sregs->psr;
- break;
- case RDY:
- if (!sparclite)
- *rdd = sregs->y;
- else {
- int rs1_is_asr = (sregs->inst >> 14) & 0x1f;
- if ( 0 == rs1_is_asr )
- *rdd = sregs->y;
- else if ( 17 == rs1_is_asr )
- *rdd = sregs->asr17;
- else {
- sregs->trap = TRAP_UNIMP;
- break;
- }
- }
- break;
- case RDWIM:
- if (!(sregs->psr & PSR_S)) {
- sregs->trap = TRAP_PRIVI;
- break;
- }
- *rdd = sregs->wim;
- break;
- case RDTBR:
- if (!(sregs->psr & PSR_S)) {
- sregs->trap = TRAP_PRIVI;
- break;
- }
- *rdd = sregs->tbr;
- break;
- case WRPSR:
- if ((sregs->psr & 0x1f) > 7) {
- sregs->trap = TRAP_UNIMP;
- break;
- }
- if (!(sregs->psr & PSR_S)) {
- sregs->trap = TRAP_PRIVI;
- break;
- }
- sregs->psr = (rs1 ^ operand2) & 0x00f03fff;
- break;
- case WRWIM:
- if (!(sregs->psr & PSR_S)) {
- sregs->trap = TRAP_PRIVI;
- break;
- }
- sregs->wim = (rs1 ^ operand2) & 0x0ff;
- break;
- case WRTBR:
- if (!(sregs->psr & PSR_S)) {
- sregs->trap = TRAP_PRIVI;
- break;
- }
- sregs->tbr = (sregs->tbr & 0x00000ff0) |
- ((rs1 ^ operand2) & 0xfffff000);
- break;
- case WRY:
- if (!sparclite)
- sregs->y = (rs1 ^ operand2);
- else {
- if ( 0 == rd )
- sregs->y = (rs1 ^ operand2);
- else if ( 17 == rd )
- sregs->asr17 = (rs1 ^ operand2);
- else {
- sregs->trap = TRAP_UNIMP;
- break;
- }
- }
- break;
- case JMPL:
-
-#ifdef STAT
- sregs->nbranch++;
-#endif
- sregs->icnt = T_JMPL; /* JMPL takes two cycles */
- if (rs1 & 0x3) {
- sregs->trap = TRAP_UNALI;
- break;
- }
- *rdd = sregs->pc;
- npc = rs1 + operand2;
- break;
- case RETT:
- address = rs1 + operand2;
- new_cwp = ((sregs->psr & PSR_CWP) + 1) & PSR_CWP;
- sregs->icnt = T_RETT; /* RETT takes two cycles */
- if (sregs->psr & PSR_ET) {
- sregs->trap = TRAP_UNIMP;
- break;
- }
- if (!(sregs->psr & PSR_S)) {
- sregs->trap = TRAP_PRIVI;
- break;
- }
- if (sregs->wim & (1 << new_cwp)) {
- sregs->trap = TRAP_WUFL;
- break;
- }
- if (address & 0x3) {
- sregs->trap = TRAP_UNALI;
- break;
- }
- sregs->psr = (sregs->psr & ~PSR_CWP) | new_cwp | PSR_ET;
- sregs->psr =
- (sregs->psr & ~PSR_S) | ((sregs->psr & PSR_PS) << 1);
- npc = address;
- break;
-
- case SCAN:
- {
- uint32 result, mask;
- int i;
-
- if (!sparclite) {
- sregs->trap = TRAP_UNIMP;
- break;
- }
- mask = (operand2 & 0x80000000) | (operand2 >> 1);
- result = rs1 ^ mask;
-
- for (i = 0; i < 32; i++) {
- if (result & 0x80000000)
- break;
- result <<= 1;
- }
-
- *rdd = i == 32 ? 63 : i;
- }
- break;
-
- default:
- sregs->trap = TRAP_UNIMP;
- break;
- }
- }
- break;
- case 3: /* Load/store instructions */
-
- address = rs1 + operand2;
-
- if (sregs->psr & PSR_S)
- asi = 11;
- else
- asi = 10;
-
- if (op3 & 4) {
- sregs->icnt = T_ST; /* Set store instruction count */
-#ifdef STAT
- sregs->nstore++;
-#endif
- } else {
- sregs->icnt = T_LD; /* Set load instruction count */
-#ifdef STAT
- sregs->nload++;
-#endif
- }
-
- /* Decode load/store instructions */
-
- switch (op3) {
- case LDDA:
- if (!chk_asi(sregs, &asi, op3)) break;
- case LDD:
- if (address & 0x7) {
- sregs->trap = TRAP_UNALI;
- break;
- }
- if (rd & 1) {
- rd &= 0x1e;
- if (rd > 7)
- rdd = &(sregs->r[(cwp + rd) & 0x7f]);
- else
- rdd = &(sregs->g[rd]);
- }
- mexc = memory_read(asi, address, ddata, 3, &ws);
- sregs->hold += ws * 2;
- sregs->icnt = T_LDD;
- if (mexc) {
- sregs->trap = TRAP_DEXC;
- } else {
- rdd[0] = ddata[0];
- rdd[1] = ddata[1];
-#ifdef STAT
- sregs->nload++; /* Double load counts twice */
-#endif
- }
- break;
-
- case LDA:
- if (!chk_asi(sregs, &asi, op3)) break;
- case LD:
- if (address & 0x3) {
- sregs->trap = TRAP_UNALI;
- break;
- }
- mexc = memory_read(asi, address, &data, 2, &ws);
- sregs->hold += ws;
- if (mexc) {
- sregs->trap = TRAP_DEXC;
- } else {
- *rdd = data;
- }
- break;
- case LDSTUBA:
- if (!chk_asi(sregs, &asi, op3)) break;
- case LDSTUB:
- mexc = memory_read(asi, address, &data, 0, &ws);
- sregs->hold += ws;
- sregs->icnt = T_LDST;
- if (mexc) {
- sregs->trap = TRAP_DEXC;
- break;
- }
- *rdd = data;
- data = 0x0ff;
- mexc = memory_write(asi, address, &data, 0, &ws);
- sregs->hold += ws;
- if (mexc) {
- sregs->trap = TRAP_DEXC;
- }
-#ifdef STAT
- sregs->nload++;
-#endif
- break;
- case LDSBA:
- case LDUBA:
- if (!chk_asi(sregs, &asi, op3)) break;
- case LDSB:
- case LDUB:
- mexc = memory_read(asi, address, &data, 0, &ws);
- sregs->hold += ws;
- if (mexc) {
- sregs->trap = TRAP_DEXC;
- break;
- }
- if ((op3 == LDSB) && (data & 0x80))
- data |= 0xffffff00;
- *rdd = data;
- break;
- case LDSHA:
- case LDUHA:
- if (!chk_asi(sregs, &asi, op3)) break;
- case LDSH:
- case LDUH:
- if (address & 0x1) {
- sregs->trap = TRAP_UNALI;
- break;
- }
- mexc = memory_read(asi, address, &data, 1, &ws);
- sregs->hold += ws;
- if (mexc) {
- sregs->trap = TRAP_DEXC;
- break;
- }
- if ((op3 == LDSH) && (data & 0x8000))
- data |= 0xffff0000;
- *rdd = data;
- break;
- case LDF:
- if (!((sregs->psr & PSR_EF) && FP_PRES)) {
- sregs->trap = TRAP_FPDIS;
- break;
- }
- if (address & 0x3) {
- sregs->trap = TRAP_UNALI;
- break;
- }
- if (ebase.simtime < sregs->ftime) {
- if ((sregs->frd == rd) || (sregs->frs1 == rd) ||
- (sregs->frs2 == rd))
- sregs->fhold += (sregs->ftime - ebase.simtime);
- }
- mexc = memory_read(asi, address, &data, 2, &ws);
- sregs->hold += ws;
- sregs->flrd = rd;
- sregs->ltime = ebase.simtime + sregs->icnt + FLSTHOLD +
- sregs->hold + sregs->fhold;
- if (mexc) {
- sregs->trap = TRAP_DEXC;
- } else {
- sregs->fs[rd] = *((float32 *) & data);
- }
- break;
- case LDDF:
- if (!((sregs->psr & PSR_EF) && FP_PRES)) {
- sregs->trap = TRAP_FPDIS;
- break;
- }
- if (address & 0x7) {
- sregs->trap = TRAP_UNALI;
- break;
- }
- if (ebase.simtime < sregs->ftime) {
- if (((sregs->frd >> 1) == (rd >> 1)) ||
- ((sregs->frs1 >> 1) == (rd >> 1)) ||
- ((sregs->frs2 >> 1) == (rd >> 1)))
- sregs->fhold += (sregs->ftime - ebase.simtime);
- }
- mexc = memory_read(asi, address, ddata, 3, &ws);
- sregs->hold += ws * 2;
- sregs->icnt = T_LDD;
- if (mexc) {
- sregs->trap = TRAP_DEXC;
- } else {
- rd &= 0x1E;
- sregs->flrd = rd;
- sregs->fs[rd] = *((float32 *) & ddata[0]);
-#ifdef STAT
- sregs->nload++; /* Double load counts twice */
-#endif
- sregs->fs[rd + 1] = *((float32 *) & ddata[1]);
- sregs->ltime = ebase.simtime + sregs->icnt + FLSTHOLD +
- sregs->hold + sregs->fhold;
- }
- break;
- case LDFSR:
- if (ebase.simtime < sregs->ftime) {
- sregs->fhold += (sregs->ftime - ebase.simtime);
- }
- if (!((sregs->psr & PSR_EF) && FP_PRES)) {
- sregs->trap = TRAP_FPDIS;
- break;
- }
- if (address & 0x3) {
- sregs->trap = TRAP_UNALI;
- break;
- }
- mexc = memory_read(asi, address, &data, 2, &ws);
- sregs->hold += ws;
- if (mexc) {
- sregs->trap = TRAP_DEXC;
- } else {
- sregs->fsr =
- (sregs->fsr & 0x7FF000) | (data & ~0x7FF000);
- set_fsr(sregs->fsr);
- }
- break;
- case STFSR:
- if (!((sregs->psr & PSR_EF) && FP_PRES)) {
- sregs->trap = TRAP_FPDIS;
- break;
- }
- if (address & 0x3) {
- sregs->trap = TRAP_UNALI;
- break;
- }
- if (ebase.simtime < sregs->ftime) {
- sregs->fhold += (sregs->ftime - ebase.simtime);
- }
- mexc = memory_write(asi, address, &sregs->fsr, 2, &ws);
- sregs->hold += ws;
- if (mexc) {
- sregs->trap = TRAP_DEXC;
- }
- break;
-
- case STA:
- if (!chk_asi(sregs, &asi, op3)) break;
- case ST:
- if (address & 0x3) {
- sregs->trap = TRAP_UNALI;
- break;
- }
- mexc = memory_write(asi, address, rdd, 2, &ws);
- sregs->hold += ws;
- if (mexc) {
- sregs->trap = TRAP_DEXC;
- }
- break;
- case STBA:
- if (!chk_asi(sregs, &asi, op3)) break;
- case STB:
- mexc = memory_write(asi, address, rdd, 0, &ws);
- sregs->hold += ws;
- if (mexc) {
- sregs->trap = TRAP_DEXC;
- }
- break;
- case STDA:
- if (!chk_asi(sregs, &asi, op3)) break;
- case STD:
- if (address & 0x7) {
- sregs->trap = TRAP_UNALI;
- break;
- }
- if (rd & 1) {
- rd &= 0x1e;
- if (rd > 7)
- rdd = &(sregs->r[(cwp + rd) & 0x7f]);
- else
- rdd = &(sregs->g[rd]);
- }
- mexc = memory_write(asi, address, rdd, 3, &ws);
- sregs->hold += ws;
- sregs->icnt = T_STD;
-#ifdef STAT
- sregs->nstore++; /* Double store counts twice */
-#endif
- if (mexc) {
- sregs->trap = TRAP_DEXC;
- break;
- }
- break;
- case STDFQ:
- if ((sregs->psr & 0x1f) > 7) {
- sregs->trap = TRAP_UNIMP;
- break;
- }
- if (!((sregs->psr & PSR_EF) && FP_PRES)) {
- sregs->trap = TRAP_FPDIS;
- break;
- }
- if (address & 0x7) {
- sregs->trap = TRAP_UNALI;
- break;
- }
- if (!(sregs->fsr & FSR_QNE)) {
- sregs->fsr = (sregs->fsr & ~FSR_TT) | FP_SEQ_ERR;
- break;
- }
- rdd = &(sregs->fpq[0]);
- mexc = memory_write(asi, address, rdd, 3, &ws);
- sregs->hold += ws;
- sregs->icnt = T_STD;
-#ifdef STAT
- sregs->nstore++; /* Double store counts twice */
-#endif
- if (mexc) {
- sregs->trap = TRAP_DEXC;
- break;
- } else {
- sregs->fsr &= ~FSR_QNE;
- sregs->fpstate = FP_EXE_MODE;
- }
- break;
- case STHA:
- if (!chk_asi(sregs, &asi, op3)) break;
- case STH:
- if (address & 0x1) {
- sregs->trap = TRAP_UNALI;
- break;
- }
- mexc = memory_write(asi, address, rdd, 1, &ws);
- sregs->hold += ws;
- if (mexc) {
- sregs->trap = TRAP_DEXC;
- }
- break;
- case STF:
- if (!((sregs->psr & PSR_EF) && FP_PRES)) {
- sregs->trap = TRAP_FPDIS;
- break;
- }
- if (address & 0x3) {
- sregs->trap = TRAP_UNALI;
- break;
- }
- if (ebase.simtime < sregs->ftime) {
- if (sregs->frd == rd)
- sregs->fhold += (sregs->ftime - ebase.simtime);
- }
- mexc = memory_write(asi, address, &sregs->fsi[rd], 2, &ws);
- sregs->hold += ws;
- if (mexc) {
- sregs->trap = TRAP_DEXC;
- }
- break;
- case STDF:
- if (!((sregs->psr & PSR_EF) && FP_PRES)) {
- sregs->trap = TRAP_FPDIS;
- break;
- }
- if (address & 0x7) {
- sregs->trap = TRAP_UNALI;
- break;
- }
- rd &= 0x1E;
- if (ebase.simtime < sregs->ftime) {
- if ((sregs->frd == rd) || (sregs->frd + 1 == rd))
- sregs->fhold += (sregs->ftime - ebase.simtime);
- }
- mexc = memory_write(asi, address, &sregs->fsi[rd], 3, &ws);
- sregs->hold += ws;
- sregs->icnt = T_STD;
-#ifdef STAT
- sregs->nstore++; /* Double store counts twice */
-#endif
- if (mexc) {
- sregs->trap = TRAP_DEXC;
- }
- break;
- case SWAPA:
- if (!chk_asi(sregs, &asi, op3)) break;
- case SWAP:
- if (address & 0x3) {
- sregs->trap = TRAP_UNALI;
- break;
- }
- mexc = memory_read(asi, address, &data, 2, &ws);
- sregs->hold += ws;
- if (mexc) {
- sregs->trap = TRAP_DEXC;
- break;
- }
- mexc = memory_write(asi, address, rdd, 2, &ws);
- sregs->hold += ws;
- sregs->icnt = T_LDST;
- if (mexc) {
- sregs->trap = TRAP_DEXC;
- break;
- } else
- *rdd = data;
-#ifdef STAT
- sregs->nload++;
-#endif
- break;
-
-
- default:
- sregs->trap = TRAP_UNIMP;
- break;
- }
-
-#ifdef LOAD_DEL
-
- if (!(op3 & 4)) {
- sregs->ildtime = ebase.simtime + sregs->hold + sregs->icnt;
- sregs->ildreg = rd;
- if ((op3 | 0x10) == 0x13)
- sregs->ildreg |= 1; /* Double load, odd register loaded
- * last */
- }
-#endif
- break;
-
- default:
- sregs->trap = TRAP_UNIMP;
- break;
- }
- sregs->g[0] = 0;
- if (!sregs->trap) {
- sregs->pc = pc;
- sregs->npc = npc;
- }
- return (0);
-}
-
-#define T_FABSs 2
-#define T_FADDs 4
-#define T_FADDd 4
-#define T_FCMPs 4
-#define T_FCMPd 4
-#define T_FDIVs 20
-#define T_FDIVd 35
-#define T_FMOVs 2
-#define T_FMULs 5
-#define T_FMULd 9
-#define T_FNEGs 2
-#define T_FSQRTs 37
-#define T_FSQRTd 65
-#define T_FSUBs 4
-#define T_FSUBd 4
-#define T_FdTOi 7
-#define T_FdTOs 3
-#define T_FiTOs 6
-#define T_FiTOd 6
-#define T_FsTOi 6
-#define T_FsTOd 2
-
-#define FABSs 0x09
-#define FADDs 0x41
-#define FADDd 0x42
-#define FCMPs 0x51
-#define FCMPd 0x52
-#define FCMPEs 0x55
-#define FCMPEd 0x56
-#define FDIVs 0x4D
-#define FDIVd 0x4E
-#define FMOVs 0x01
-#define FMULs 0x49
-#define FMULd 0x4A
-#define FNEGs 0x05
-#define FSQRTs 0x29
-#define FSQRTd 0x2A
-#define FSUBs 0x45
-#define FSUBd 0x46
-#define FdTOi 0xD2
-#define FdTOs 0xC6
-#define FiTOs 0xC4
-#define FiTOd 0xC8
-#define FsTOi 0xD1
-#define FsTOd 0xC9
-
-
-static int
-fpexec(op3, rd, rs1, rs2, sregs)
- uint32 op3, rd, rs1, rs2;
- struct pstate *sregs;
-{
- uint32 opf, tem, accex;
- int32 fcc;
- uint32 ldadj;
-
- if (sregs->fpstate == FP_EXC_MODE) {
- sregs->fsr = (sregs->fsr & ~FSR_TT) | FP_SEQ_ERR;
- sregs->fpstate = FP_EXC_PE;
- return (0);
- }
- if (sregs->fpstate == FP_EXC_PE) {
- sregs->fpstate = FP_EXC_MODE;
- return (TRAP_FPEXC);
- }
- opf = (sregs->inst >> 5) & 0x1ff;
-
- /*
- * Check if we already have an FPop in the pipe. If so, halt until it is
- * finished by incrementing fhold with the remaining execution time
- */
-
- if (ebase.simtime < sregs->ftime) {
- sregs->fhold = (sregs->ftime - ebase.simtime);
- } else {
- sregs->fhold = 0;
-
- /* Check load dependencies. */
-
- if (ebase.simtime < sregs->ltime) {
-
- /* Don't check rs1 if single operand instructions */
-
- if (((opf >> 6) == 0) || ((opf >> 6) == 3))
- rs1 = 32;
-
- /* Adjust for double floats */
-
- ldadj = opf & 1;
- if (!(((sregs->flrd - rs1) >> ldadj) && ((sregs->flrd - rs2) >> ldadj)))
- sregs->fhold++;
- }
- }
-
- sregs->finst++;
-
- sregs->frs1 = rs1; /* Store src and dst for dependecy check */
- sregs->frs2 = rs2;
- sregs->frd = rd;
-
- sregs->ftime = ebase.simtime + sregs->hold + sregs->fhold;
-
- /* SPARC is big-endian - swap double floats if host is little-endian */
- /* This is ugly - I know ... */
-
- /* FIXME: should use (CURRENT_HOST_BYTE_ORDER == CURRENT_TARGET_BYTE_ORDER)
- but what about machines where float values are different endianness
- from integer values? */
-
-#ifdef HOST_LITTLE_ENDIAN_FLOAT
- rs1 &= 0x1f;
- switch (opf) {
- case FADDd:
- case FDIVd:
- case FMULd:
- case FSQRTd:
- case FSUBd:
- case FCMPd:
- case FCMPEd:
- case FdTOi:
- case FdTOs:
- sregs->fdp[rs1 | 1] = sregs->fs[rs1 & ~1];
- sregs->fdp[rs1 & ~1] = sregs->fs[rs1 | 1];
- sregs->fdp[rs2 | 1] = sregs->fs[rs2 & ~1];
- sregs->fdp[rs2 & ~1] = sregs->fs[rs2 | 1];
- default:
- ;
- }
-#endif
-
- clear_accex();
-
- switch (opf) {
- case FABSs:
- sregs->fs[rd] = fabs(sregs->fs[rs2]);
- sregs->ftime += T_FABSs;
- sregs->frs1 = 32; /* rs1 ignored */
- break;
- case FADDs:
- sregs->fs[rd] = sregs->fs[rs1] + sregs->fs[rs2];
- sregs->ftime += T_FADDs;
- break;
- case FADDd:
- sregs->fd[rd >> 1] = sregs->fd[rs1 >> 1] + sregs->fd[rs2 >> 1];
- sregs->ftime += T_FADDd;
- break;
- case FCMPs:
- case FCMPEs:
- if (sregs->fs[rs1] == sregs->fs[rs2])
- fcc = 3;
- else if (sregs->fs[rs1] < sregs->fs[rs2])
- fcc = 2;
- else if (sregs->fs[rs1] > sregs->fs[rs2])
- fcc = 1;
- else
- fcc = 0;
- sregs->fsr |= 0x0C00;
- sregs->fsr &= ~(fcc << 10);
- sregs->ftime += T_FCMPs;
- sregs->frd = 32; /* rd ignored */
- if ((fcc == 0) && (opf == FCMPEs)) {
- sregs->fpstate = FP_EXC_PE;
- sregs->fsr = (sregs->fsr & ~0x1C000) | (1 << 14);
- }
- break;
- case FCMPd:
- case FCMPEd:
- if (sregs->fd[rs1 >> 1] == sregs->fd[rs2 >> 1])
- fcc = 3;
- else if (sregs->fd[rs1 >> 1] < sregs->fd[rs2 >> 1])
- fcc = 2;
- else if (sregs->fd[rs1 >> 1] > sregs->fd[rs2 >> 1])
- fcc = 1;
- else
- fcc = 0;
- sregs->fsr |= 0x0C00;
- sregs->fsr &= ~(fcc << 10);
- sregs->ftime += T_FCMPd;
- sregs->frd = 32; /* rd ignored */
- if ((fcc == 0) && (opf == FCMPEd)) {
- sregs->fpstate = FP_EXC_PE;
- sregs->fsr = (sregs->fsr & ~FSR_TT) | FP_IEEE;
- }
- break;
- case FDIVs:
- sregs->fs[rd] = sregs->fs[rs1] / sregs->fs[rs2];
- sregs->ftime += T_FDIVs;
- break;
- case FDIVd:
- sregs->fd[rd >> 1] = sregs->fd[rs1 >> 1] / sregs->fd[rs2 >> 1];
- sregs->ftime += T_FDIVd;
- break;
- case FMOVs:
- sregs->fs[rd] = sregs->fs[rs2];
- sregs->ftime += T_FMOVs;
- sregs->frs1 = 32; /* rs1 ignored */
- break;
- case FMULs:
- sregs->fs[rd] = sregs->fs[rs1] * sregs->fs[rs2];
- sregs->ftime += T_FMULs;
- break;
- case FMULd:
- sregs->fd[rd >> 1] = sregs->fd[rs1 >> 1] * sregs->fd[rs2 >> 1];
- sregs->ftime += T_FMULd;
- break;
- case FNEGs:
- sregs->fs[rd] = -sregs->fs[rs2];
- sregs->ftime += T_FNEGs;
- sregs->frs1 = 32; /* rs1 ignored */
- break;
- case FSQRTs:
- if (sregs->fs[rs2] < 0.0) {
- sregs->fpstate = FP_EXC_PE;
- sregs->fsr = (sregs->fsr & ~FSR_TT) | FP_IEEE;
- sregs->fsr = (sregs->fsr & 0x1f) | 0x10;
- break;
- }
- sregs->fs[rd] = sqrt(sregs->fs[rs2]);
- sregs->ftime += T_FSQRTs;
- sregs->frs1 = 32; /* rs1 ignored */
- break;
- case FSQRTd:
- if (sregs->fd[rs2 >> 1] < 0.0) {
- sregs->fpstate = FP_EXC_PE;
- sregs->fsr = (sregs->fsr & ~FSR_TT) | FP_IEEE;
- sregs->fsr = (sregs->fsr & 0x1f) | 0x10;
- break;
- }
- sregs->fd[rd >> 1] = sqrt(sregs->fd[rs2 >> 1]);
- sregs->ftime += T_FSQRTd;
- sregs->frs1 = 32; /* rs1 ignored */
- break;
- case FSUBs:
- sregs->fs[rd] = sregs->fs[rs1] - sregs->fs[rs2];
- sregs->ftime += T_FSUBs;
- break;
- case FSUBd:
- sregs->fd[rd >> 1] = sregs->fd[rs1 >> 1] - sregs->fd[rs2 >> 1];
- sregs->ftime += T_FSUBd;
- break;
- case FdTOi:
- sregs->fsi[rd] = (int) sregs->fd[rs2 >> 1];
- sregs->ftime += T_FdTOi;
- sregs->frs1 = 32; /* rs1 ignored */
- break;
- case FdTOs:
- sregs->fs[rd] = (float32) sregs->fd[rs2 >> 1];
- sregs->ftime += T_FdTOs;
- sregs->frs1 = 32; /* rs1 ignored */
- break;
- case FiTOs:
- sregs->fs[rd] = (float32) sregs->fsi[rs2];
- sregs->ftime += T_FiTOs;
- sregs->frs1 = 32; /* rs1 ignored */
- break;
- case FiTOd:
- sregs->fd[rd >> 1] = (float64) sregs->fsi[rs2];
- sregs->ftime += T_FiTOd;
- sregs->frs1 = 32; /* rs1 ignored */
- break;
- case FsTOi:
- sregs->fsi[rd] = (int) sregs->fs[rs2];
- sregs->ftime += T_FsTOi;
- sregs->frs1 = 32; /* rs1 ignored */
- break;
- case FsTOd:
- sregs->fd[rd >> 1] = sregs->fs[rs2];
- sregs->ftime += T_FsTOd;
- sregs->frs1 = 32; /* rs1 ignored */
- break;
-
- default:
- sregs->fsr = (sregs->fsr & ~FSR_TT) | FP_UNIMP;
- sregs->fpstate = FP_EXC_PE;
- }
-
-#ifdef ERRINJ
- if (errftt) {
- sregs->fsr = (sregs->fsr & ~FSR_TT) | (errftt << 14);
- sregs->fpstate = FP_EXC_PE;
- if (sis_verbose) printf("Inserted fpu error %X\n",errftt);
- errftt = 0;
- }
-#endif
-
- accex = get_accex();
-
-#ifdef HOST_LITTLE_ENDIAN_FLOAT
- switch (opf) {
- case FADDd:
- case FDIVd:
- case FMULd:
- case FSQRTd:
- case FSUBd:
- case FiTOd:
- case FsTOd:
- sregs->fs[rd & ~1] = sregs->fdp[rd | 1];
- sregs->fs[rd | 1] = sregs->fdp[rd & ~1];
- default:
- ;
- }
-#endif
- if (sregs->fpstate == FP_EXC_PE) {
- sregs->fpq[0] = sregs->pc;
- sregs->fpq[1] = sregs->inst;
- sregs->fsr |= FSR_QNE;
- } else {
- tem = (sregs->fsr >> 23) & 0x1f;
- if (tem & accex) {
- sregs->fpstate = FP_EXC_PE;
- sregs->fsr = (sregs->fsr & ~FSR_TT) | FP_IEEE;
- sregs->fsr = ((sregs->fsr & ~0x1f) | accex);
- } else {
- sregs->fsr = ((((sregs->fsr >> 5) | accex) << 5) | accex);
- }
- if (sregs->fpstate == FP_EXC_PE) {
- sregs->fpq[0] = sregs->pc;
- sregs->fpq[1] = sregs->inst;
- sregs->fsr |= FSR_QNE;
- }
- }
- clear_accex();
-
- return (0);
-
-
-}
-
-static int
-chk_asi(sregs, asi, op3)
- struct pstate *sregs;
- uint32 *asi, op3;
-
-{
- if (!(sregs->psr & PSR_S)) {
- sregs->trap = TRAP_PRIVI;
- return (0);
- } else if (sregs->inst & INST_I) {
- sregs->trap = TRAP_UNIMP;
- return (0);
- } else
- *asi = (sregs->inst >> 5) & 0x0ff;
- return(1);
-}
-
-int
-execute_trap(sregs)
- struct pstate *sregs;
-{
- int32 cwp;
-
- if (sregs->trap == 256) {
- sregs->pc = 0;
- sregs->npc = 4;
- sregs->trap = 0;
- } else if (sregs->trap == 257) {
- return (ERROR);
- } else {
-
- if ((sregs->psr & PSR_ET) == 0)
- return (ERROR);
-
- sregs->tbr = (sregs->tbr & 0xfffff000) | (sregs->trap << 4);
- sregs->trap = 0;
- sregs->psr &= ~PSR_ET;
- sregs->psr |= ((sregs->psr & PSR_S) >> 1);
- sregs->annul = 0;
- sregs->psr = (((sregs->psr & PSR_CWP) - 1) & 0x7) | (sregs->psr & ~PSR_CWP);
- cwp = ((sregs->psr & PSR_CWP) << 4);
- sregs->r[(cwp + 17) & 0x7f] = sregs->pc;
- sregs->r[(cwp + 18) & 0x7f] = sregs->npc;
- sregs->psr |= PSR_S;
- sregs->pc = sregs->tbr;
- sregs->npc = sregs->tbr + 4;
-
- if ( 0 != (1 & sregs->asr17) ) {
- /* single vector trapping! */
- sregs->pc = sregs->tbr & 0xfffff000;
- sregs->npc = sregs->pc + 4;
- }
-
- /* Increase simulator time */
- sregs->icnt = TRAP_C;
-
- }
-
-
- return (0);
-
-}
-
-extern struct irqcell irqarr[16];
-
-int
-check_interrupts(sregs)
- struct pstate *sregs;
-{
-#ifdef ERRINJ
- if (errtt) {
- sregs->trap = errtt;
- if (sis_verbose) printf("Inserted error trap 0x%02X\n",errtt);
- errtt = 0;
- }
-#endif
-
- if ((ext_irl) && (sregs->psr & PSR_ET) &&
- ((ext_irl == 15) || (ext_irl > (int) ((sregs->psr & PSR_PIL) >> 8)))) {
- if (sregs->trap == 0) {
- sregs->trap = 16 + ext_irl;
- irqarr[ext_irl & 0x0f].callback(irqarr[ext_irl & 0x0f].arg);
- return(1);
- }
- }
- return(0);
-}
-
-void
-init_regs(sregs)
- struct pstate *sregs;
-{
- sregs->pc = 0;
- sregs->npc = 4;
- sregs->trap = 0;
- sregs->psr &= 0x00f03fdf;
- sregs->psr |= 0x080; /* Set supervisor bit */
- sregs->breakpoint = 0;
- sregs->annul = 0;
- sregs->fpstate = FP_EXE_MODE;
- sregs->fpqn = 0;
- sregs->ftime = 0;
- sregs->ltime = 0;
- sregs->err_mode = 0;
- ext_irl = 0;
- sregs->g[0] = 0;
-#ifdef HOST_LITTLE_ENDIAN_FLOAT
- sregs->fdp = (float32 *) sregs->fd;
- sregs->fsi = (int32 *) sregs->fs;
-#else
- sregs->fs = (float32 *) sregs->fd;
- sregs->fsi = (int32 *) sregs->fd;
-#endif
- sregs->fsr = 0;
- sregs->fpu_pres = !nfp;
- set_fsr(sregs->fsr);
- sregs->bphit = 0;
- sregs->ildreg = 0;
- sregs->ildtime = 0;
-
- sregs->y = 0;
- sregs->asr17 = 0;
-
- sregs->rett_err = 0;
- sregs->jmpltime = 0;
-}
exec.c
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: startsim
===================================================================
--- startsim (revision 816)
+++ startsim (nonexistent)
@@ -1,4 +0,0 @@
-#
-xterm -e sis $* &
-xterm -e tip /dev/ttypc &
-
Index: interf.c
===================================================================
--- interf.c (revision 816)
+++ interf.c (nonexistent)
@@ -1,519 +0,0 @@
-/*
- * This file is part of SIS.
- *
- * SIS, SPARC instruction simulator V1.6 Copyright (C) 1995 Jiri Gaisler,
- * European Space Agency
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 675
- * Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include "sis.h"
-#include "libiberty.h"
-#include "bfd.h"
-#include
-#include "sim-config.h"
-
-#include "gdb/remote-sim.h"
-#include "gdb/signals.h"
-
-#define PSR_CWP 0x7
-
-#define VAL(x) strtol(x,(char **)NULL,0)
-
-extern struct disassemble_info dinfo;
-extern struct pstate sregs;
-extern struct estate ebase;
-
-extern int current_target_byte_order;
-extern int ctrl_c;
-extern int nfp;
-extern int ift;
-extern int rom8;
-extern int wrp;
-extern int uben;
-extern int sis_verbose;
-extern char *sis_version;
-extern struct estate ebase;
-extern struct evcell evbuf[];
-extern struct irqcell irqarr[];
-extern int irqpend, ext_irl;
-extern int sparclite;
-extern int dumbio;
-extern int sparclite_board;
-extern int termsave;
-extern char uart_dev1[], uart_dev2[];
-
-int sis_gdb_break = 1;
-
-host_callback *sim_callback;
-
-int
-run_sim(sregs, icount, dis)
- struct pstate *sregs;
- unsigned int icount;
- int dis;
-{
- int mexc, irq;
-
- if (sis_verbose)
- (*sim_callback->printf_filtered) (sim_callback, "resuming at %x\n",
- sregs->pc);
- init_stdio();
- sregs->starttime = time(NULL);
- irq = 0;
- while (!sregs->err_mode & (icount > 0)) {
-
- sregs->fhold = 0;
- sregs->hold = 0;
- sregs->icnt = 1;
-
- if (sregs->psr & 0x080)
- sregs->asi = 8;
- else
- sregs->asi = 9;
-
-#if 0 /* DELETE ME! for debugging purposes only */
- if (sis_verbose > 1)
- if (sregs->pc == 0 || sregs->npc == 0)
- printf ("bogus pc or npc\n");
-#endif
- mexc = memory_read(sregs->asi, sregs->pc, &sregs->inst,
- 2, &sregs->hold);
-#if 1 /* DELETE ME! for debugging purposes only */
- if (sis_verbose > 2)
- printf("pc %x, np %x, sp %x, fp %x, wm %x, cw %x, i %08x\n",
- sregs->pc, sregs->npc,
- sregs->r[(((sregs->psr & 7) << 4) + 14) & 0x7f],
- sregs->r[(((sregs->psr & 7) << 4) + 30) & 0x7f],
- sregs->wim,
- sregs->psr & 7,
- sregs->inst);
-#endif
- if (sregs->annul) {
- sregs->annul = 0;
- sregs->icnt = 1;
- sregs->pc = sregs->npc;
- sregs->npc = sregs->npc + 4;
- } else {
- if (ext_irl) irq = check_interrupts(sregs);
- if (!irq) {
- if (mexc) {
- sregs->trap = I_ACC_EXC;
- } else {
- if ((sis_gdb_break) && (sregs->inst == 0x91d02001)) {
- if (sis_verbose)
- (*sim_callback->printf_filtered) (sim_callback,
- "SW BP hit at %x\n", sregs->pc);
- sim_halt();
- restore_stdio();
- clearerr(stdin);
- return (BPT_HIT);
- } else
- dispatch_instruction(sregs);
- }
- icount--;
- }
- if (sregs->trap) {
- irq = 0;
- sregs->err_mode = execute_trap(sregs);
- }
- }
- advance_time(sregs);
- if (ctrl_c) {
- icount = 0;
- }
- }
- sim_halt();
- sregs->tottime += time(NULL) - sregs->starttime;
- restore_stdio();
- clearerr(stdin);
- if (sregs->err_mode)
- error_mode(sregs->pc);
- if (sregs->err_mode)
- return (ERROR);
- if (sregs->bphit) {
- if (sis_verbose)
- (*sim_callback->printf_filtered) (sim_callback,
- "HW BP hit at %x\n", sregs->pc);
- return (BPT_HIT);
- }
- if (ctrl_c) {
- ctrl_c = 0;
- return (CTRL_C);
- }
- return (TIME_OUT);
-}
-
-void
-sim_set_callbacks (ptr)
- host_callback *ptr;
-{
- sim_callback = ptr;
-}
-
-void
-sim_size (memsize)
- int memsize;
-{
-}
-
-SIM_DESC
-sim_open (kind, callback, abfd, argv)
- SIM_OPEN_KIND kind;
- struct host_callback_struct *callback;
- struct bfd *abfd;
- char **argv;
-{
-
- int argc = 0;
- int stat = 1;
- int freq = 0;
-
- sim_callback = callback;
-
- while (argv[argc])
- argc++;
- while (stat < argc) {
- if (argv[stat][0] == '-') {
- if (strcmp(argv[stat], "-v") == 0) {
- sis_verbose++;
- } else
- if (strcmp(argv[stat], "-nfp") == 0) {
- nfp = 1;
- } else
- if (strcmp(argv[stat], "-ift") == 0) {
- ift = 1;
- } else
- if (strcmp(argv[stat], "-sparclite") == 0) {
- sparclite = 1;
- } else
- if (strcmp(argv[stat], "-sparclite-board") == 0) {
- sparclite_board = 1;
- } else
- if (strcmp(argv[stat], "-dumbio") == 0) {
- dumbio = 1;
- } else
- if (strcmp(argv[stat], "-wrp") == 0) {
- wrp = 1;
- } else
- if (strcmp(argv[stat], "-rom8") == 0) {
- rom8 = 1;
- } else
- if (strcmp(argv[stat], "-uben") == 0) {
- uben = 1;
- } else
- if (strcmp(argv[stat], "-uart1") == 0) {
- if ((stat + 1) < argc)
- strcpy(uart_dev1, argv[++stat]);
- } else
- if (strcmp(argv[stat], "-uart2") == 0) {
- if ((stat + 1) < argc)
- strcpy(uart_dev2, argv[++stat]);
- } else
- if (strcmp(argv[stat], "-nogdb") == 0) {
- sis_gdb_break = 0;
- } else
- if (strcmp(argv[stat], "-freq") == 0) {
- if ((stat + 1) < argc) {
- freq = VAL(argv[++stat]);
- }
- } else {
- (*sim_callback->printf_filtered) (sim_callback,
- "unknown option %s\n",
- argv[stat]);
- }
- } else
- bfd_load(argv[stat]);
- stat++;
- }
-
- if (sis_verbose) {
- (*sim_callback->printf_filtered) (sim_callback, "\n SIS - SPARC instruction simulator %s\n", sis_version);
- (*sim_callback->printf_filtered) (sim_callback, " Bug-reports to Jiri Gaisler ESA/ESTEC (jgais@wd.estec.esa.nl)\n");
- if (nfp)
- (*sim_callback->printf_filtered) (sim_callback, "no FPU\n");
- if (sparclite)
- (*sim_callback->printf_filtered) (sim_callback, "simulating Sparclite\n");
- if (dumbio)
- (*sim_callback->printf_filtered) (sim_callback, "dumb IO (no input, dumb output)\n");
- if (sis_gdb_break == 0)
- (*sim_callback->printf_filtered) (sim_callback, "disabling GDB trap handling for breakpoints\n");
- if (freq)
- (*sim_callback->printf_filtered) (sim_callback, " ERC32 freq %d Mhz\n", freq);
- }
-
- sregs.freq = freq ? freq : 15;
- termsave = fcntl(0, F_GETFL, 0);
- INIT_DISASSEMBLE_INFO(dinfo, stdout,(fprintf_ftype)fprintf);
- dinfo.endian = BFD_ENDIAN_BIG;
- reset_all();
- ebase.simtime = 0;
- init_sim();
- init_bpt(&sregs);
- reset_stat(&sregs);
-
- /* Fudge our descriptor for now. */
- return (SIM_DESC) 1;
-}
-
-void
-sim_close(sd, quitting)
- SIM_DESC sd;
- int quitting;
-{
-
- exit_sim();
- fcntl(0, F_SETFL, termsave);
-
-};
-
-SIM_RC
-sim_load(sd, prog, abfd, from_tty)
- SIM_DESC sd;
- char *prog;
- bfd *abfd;
- int from_tty;
-{
- bfd_load (prog);
- return SIM_RC_OK;
-}
-
-SIM_RC
-sim_create_inferior(sd, abfd, argv, env)
- SIM_DESC sd;
- struct bfd *abfd;
- char **argv;
- char **env;
-{
- bfd_vma start_address = 0;
- if (abfd != NULL)
- start_address = bfd_get_start_address (abfd);
-
- ebase.simtime = 0;
- reset_all();
- reset_stat(&sregs);
- sregs.pc = start_address & ~3;
- sregs.npc = sregs.pc + 4;
- return SIM_RC_OK;
-}
-
-int
-sim_store_register(sd, regno, value, length)
- SIM_DESC sd;
- int regno;
- unsigned char *value;
- int length;
-{
- /* FIXME: Review the computation of regval. */
- int regval;
- if (current_target_byte_order == BIG_ENDIAN)
- regval = (value[0] << 24) | (value[1] << 16)
- | (value[2] << 8) | value[3];
- else
- regval = (value[3] << 24) | (value[2] << 16)
- | (value[1] << 8) | value[0];
- set_regi(&sregs, regno, regval);
- return -1;
-}
-
-
-int
-sim_fetch_register(sd, regno, buf, length)
- SIM_DESC sd;
- int regno;
- unsigned char *buf;
- int length;
-{
- get_regi(&sregs, regno, buf);
- return -1;
-}
-
-int
-sim_write(sd, mem, buf, length)
- SIM_DESC sd;
- SIM_ADDR mem;
- unsigned char *buf;
- int length;
-{
- return (sis_memory_write(mem, buf, length));
-}
-
-int
-sim_read(sd, mem, buf, length)
- SIM_DESC sd;
- SIM_ADDR mem;
- unsigned char *buf;
- int length;
-{
- return (sis_memory_read(mem, buf, length));
-}
-
-void
-sim_info(sd, verbose)
- SIM_DESC sd;
- int verbose;
-{
- show_stat(&sregs);
-}
-
-int simstat = OK;
-
-void
-sim_stop_reason(sd, reason, sigrc)
- SIM_DESC sd;
- enum sim_stop * reason;
- int *sigrc;
-{
-
- switch (simstat) {
- case CTRL_C:
- *reason = sim_stopped;
- *sigrc = TARGET_SIGNAL_INT;
- break;
- case OK:
- case TIME_OUT:
- case BPT_HIT:
- *reason = sim_stopped;
- *sigrc = TARGET_SIGNAL_TRAP;
- break;
- case ERROR:
- *sigrc = 0;
- *reason = sim_exited;
- }
- ctrl_c = 0;
- simstat = OK;
-}
-
-/* Flush all register windows out to the stack. Starting after the invalid
- window, flush all windows up to, and including the current window. This
- allows GDB to do backtraces and look at local variables for frames that
- are still in the register windows. Note that strictly speaking, this
- behavior is *wrong* for several reasons. First, it doesn't use the window
- overflow handlers. It therefore assumes standard frame layouts and window
- handling policies. Second, it changes system state behind the back of the
- target program. I expect this to mainly pose problems when debugging trap
- handlers.
-*/
-
-static void
-flush_windows ()
-{
- int invwin;
- int cwp;
- int win;
- int ws;
-
- /* Keep current window handy */
-
- cwp = sregs.psr & PSR_CWP;
-
- /* Calculate the invalid window from the wim. */
-
- for (invwin = 0; invwin <= PSR_CWP; invwin++)
- if ((sregs.wim >> invwin) & 1)
- break;
-
- /* Start saving with the window after the invalid window. */
-
- invwin = (invwin - 1) & PSR_CWP;
-
- for (win = invwin; ; win = (win - 1) & PSR_CWP)
- {
- uint32 sp;
- int i;
-
- sp = sregs.r[(win * 16 + 14) & 0x7f];
-#if 1
- if (sis_verbose > 2) {
- uint32 fp = sregs.r[(win * 16 + 30) & 0x7f];
- printf("flush_window: win %d, sp %x, fp %x\n", win, sp, fp);
- }
-#endif
-
- for (i = 0; i < 16; i++)
- memory_write (11, sp + 4 * i, &sregs.r[(win * 16 + 16 + i) & 0x7f], 2,
- &ws);
-
- if (win == cwp)
- break;
- }
-}
-
-void
-sim_resume(SIM_DESC sd, int step, int siggnal)
-{
- simstat = run_sim(&sregs, -1, 0);
-
- if (sis_gdb_break) flush_windows ();
-}
-
-int
-sim_trace (sd)
- SIM_DESC sd;
-{
- /* FIXME: unfinished */
- sim_resume (sd, 0, 0);
- return 1;
-}
-
-void
-sim_do_command(sd, cmd)
- SIM_DESC sd;
- char *cmd;
-{
- exec_cmd(&sregs, cmd);
-}
-
-#if 0 /* FIXME: These shouldn't exist. */
-
-int
-sim_insert_breakpoint(int addr)
-{
- if (sregs.bptnum < BPT_MAX) {
- sregs.bpts[sregs.bptnum] = addr & ~0x3;
- sregs.bptnum++;
- if (sis_verbose)
- (*sim_callback->printf_filtered) (sim_callback, "inserted HW BP at %x\n", addr);
- return 0;
- } else
- return 1;
-}
-
-int
-sim_remove_breakpoint(int addr)
-{
- int i = 0;
-
- while ((i < sregs.bptnum) && (sregs.bpts[i] != addr))
- i++;
- if (addr == sregs.bpts[i]) {
- for (; i < sregs.bptnum - 1; i++)
- sregs.bpts[i] = sregs.bpts[i + 1];
- sregs.bptnum -= 1;
- if (sis_verbose)
- (*sim_callback->printf_filtered) (sim_callback, "removed HW BP at %x\n", addr);
- return 0;
- }
- return 1;
-}
-
-#endif
interf.c
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: help.c
===================================================================
--- help.c (revision 816)
+++ help.c (nonexistent)
@@ -1,40 +0,0 @@
-#include
-#include "sis.h"
-
-void
-usage()
-{
-
- printf("usage: sis [-uart1 uart_device1] [-uart2 uart_device2]\n");
- printf("[-nfp] [-freq frequency] [-c batch_file] [files]\n");
- printf("[-sparclite] [-dumbio]\n");
-}
-
-void
-gen_help()
-{
-
- printf("\n batch execute a batch file of SIS commands\n");
- printf(" +bp add a breakpoint at \n");
- printf(" -bp delete breakpoint \n");
- printf(" bp print all breakpoints\n");
- printf(" cont [icnt] continue execution for [icnt] instructions\n");
- printf(" deb set debug level\n");
- printf(" dis [addr] [count] disassemble [count] instructions at address [addr]\n");
- printf(" echo print to the simulator window\n");
-#ifdef ERRINJ
- printf(" error inject error traps in IU and FPU\n");
-#endif
- printf(" float print the FPU registers\n");
- printf(" go [icnt] start execution at for [icnt] instructions\n");
- printf(" hist [trace_length] enable/show trace history\n");
- printf(" load load a file into simulator memory\n");
- printf(" mem [addr] [count] display memory at [addr] for [count] bytes\n");
- printf(" quit exit the simulator\n");
- printf(" perf [reset] show/reset performance statistics\n");
- printf(" reg [w<0-7>] show integer registers (or windows, eg 're w2')\n");
- printf(" run [inst_count] reset and start execution for [icnt] instruction\n");
- printf(" step single step\n");
- printf(" tra [inst_count] trace [inst_count] instructions\n");
- printf("\n type Ctrl-C to interrupt execution\n\n");
-}
help.c
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: README.erc32
===================================================================
--- README.erc32 (revision 816)
+++ README.erc32 (nonexistent)
@@ -1,130 +0,0 @@
-
-1. MEC and ERC32 emulation
-
-The file 'erc32.c' contains a model of the MEC, 512 K rom and 4 M ram.
-
-The following paragraphs outline the implemented MEC functions.
-
-1.1 UARTs
-
-The UARTs are connected to two pseudo-devices, /dev/ttypc and /dev/ttypd.
-The following registers are implemeted:
-
-- UART A RX and TX register (0x01f800e0)
-- UART B RX and TX register (0x01f800e4)
-- UART status register (0x01f800e8)
-
-To speed up simulation, the UARTs operate at approximately 115200 baud.
-The UARTs generate interrupt 4 and 5 after each received or transmitted
-character. The error interrupt is generated if overflow occurs - other
-errors cannot occure.
-
-1.2 Real-time clock and general pupose timer A
-
-The following registers are implemeted:
-
-- Real-time clock timer (0x01f80080, read-only)
-- Real-time clock scaler program register (0x01f80084, write-only)
-- Real-time clock counter program register (0x01f80080, write-only)
-
-- Genearl pupose timer (0x01f80088, read-only)
-- Real-time clock scaler program register (0x01f8008c, write-only)
-- General purpose timer counter prog. register (0x01f80088, write-only)
-
-- Timer control register (0x01f80098, write-only)
-
-1.3 Interrupt controller
-
-The interrupt controller is implemented as in the MEC specification with
-the exception of the interrupt shape register. Since external interrupts
-are not possible, the interrupt shape register is not implemented. The
-only internal interrupts that are generated are the real-time clock,
-the general purpose timer and UARTs. However, all 15 interrupts
-can be tested via the interrupt force register.
-
-The following registers are implemeted:
-
-- Interrupt pending register (0x01f80048, read-only)
-- Interrupt mask register (0x01f8004c, read-write)
-- Interrupt clear register (0x01f80050, write-only)
-- Interrupt force register (0x01f80054, read-write)
-
-1.4 Breakpoint and watchpoint register
-
-The breakpoint and watchpoint functions are implemented as in the MEC
-specification. Traps are correctly generated, and the system fault status
-register is updated accordingly. Implemeted registers are:
-
-- Debug control register (0x01f800c0, read-write)
-- Breakpoint register (0x01f800c4, write-only)
-- Watchpoint register (0x01f800c8, write-only)
-- System fault status register (0x01f800a0, read-write)
-- Firts failing address register (0x01f800a4, read-write)
-
-
-1.5 Memory interface
-
-The following memory areas are valid for the ERC32 simulator:
-
-0x00000000 - 0x00080000 ROM (512 Kbyte, loaded at start-up)
-0x02000000 - 0x02400000 RAM (4 Mbyte, initialised to 0x0)
-0x01f80000 - 0x01f800ff MEC registers
-
-Access to unimplemented MEC registers or non-existing memory will result
-in a memory exception trap. However, access to unimplemented MEC registers
-in the area 0x01f80000 - 0x01f80100 will not cause a memory exception trap.
-The written value will be stored in a register and can be read back. It
-does however not affect the function in any way.
-
-The memory configuartion register is used to define available memory
-in the system. The fields RSIZ and PSIZ are used to set RAM and ROM
-size, the remaining fields are not used. NOTE: after reset, the MEC
-is set to decode 4 Kbyte of ROM and 256 Kbyte of RAM. The memory
-configuration register has to be updated to reflect the available memory.
-
-The waitstate configuration register is used to generate waitstates.
-This register must also be updated with the correct configuration after
-reset.
-
-The memory protection scheme is implemented - it is enabled through bit 3
-in the MEC control register.
-
-The following registers are implemeted:
-
-- MEC control register (bit 3 only) (0x01f80000, read-write)
-- Memory control register (0x01f80010, read-write)
-- Waitstate configuration register (0x01f80018, read-write)
-- Memory access register 0 (0x01f80020, read-write)
-- Memory access register 1 (0x01f80024, read-write)
-
-1.6 Watchdog
-
-The watchdog is implemented as in the specification. The input clock is
-always the system clock regardsless of WDCS bit in mec configuration
-register.
-
-The following registers are implemeted:
-
-- Watchdog program and acknowledge register (0x01f80060, write-only)
-- Watchdog trap door set register (0x01f80064, write-only)
-
-1.7 Software reset register
-
-Implemented as in the specification (0x01f800004, write-only).
-
-1.8 Power-down mode
-
-The power-down register (0x01f800008) is implemented as in the specification.
-However, if the simulator event queue is empty, power-down mode is not
-entered since no interrupt would be generated to exit from the mode. A
-Ctrl-C in the simulator window will exit the power-down mode.
-
-1.9 MEC control register
-
-The following bits are implemented in the MEC control register:
-
-Bit Name Function
-0 PRD Power-down mode enable
-1 SWR Soft reset enable
-3 APR Access protection enable
-
README.erc32
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: config.in
===================================================================
--- config.in (revision 816)
+++ config.in (nonexistent)
@@ -1,92 +0,0 @@
-/* config.in. Generated from configure.ac by autoheader. */
-
-/* Define to 1 if translation of program messages to the user's native
- language is requested. */
-#undef ENABLE_NLS
-
-/* Define to 1 if you have the header file. */
-#undef HAVE_DLFCN_H
-
-/* Define to 1 if you have the header file. */
-#undef HAVE_ERRNO_H
-
-/* Define to 1 if you have the header file. */
-#undef HAVE_FCNTL_H
-
-/* Define to 1 if you have the header file. */
-#undef HAVE_FPU_CONTROL_H
-
-/* Define to 1 if you have the `getrusage' function. */
-#undef HAVE_GETRUSAGE
-
-/* Define to 1 if you have the header file. */
-#undef HAVE_INTTYPES_H
-
-/* Define to 1 if you have the `nsl' library (-lnsl). */
-#undef HAVE_LIBNSL
-
-/* Define to 1 if you have the `socket' library (-lsocket). */
-#undef HAVE_LIBSOCKET
-
-/* Define to 1 if you have the header file. */
-#undef HAVE_MEMORY_H
-
-/* Define to 1 if you have the `sigaction' function. */
-#undef HAVE_SIGACTION
-
-/* Define to 1 if you have the header file. */
-#undef HAVE_STDINT_H
-
-/* Define to 1 if you have the header file. */
-#undef HAVE_STDLIB_H
-
-/* Define to 1 if you have the header file. */
-#undef HAVE_STRINGS_H
-
-/* Define to 1 if you have the header file. */
-#undef HAVE_STRING_H
-
-/* Define to 1 if you have the header file. */
-#undef HAVE_SYS_RESOURCE_H
-
-/* Define to 1 if you have the header file. */
-#undef HAVE_SYS_STAT_H
-
-/* Define to 1 if you have the header file. */
-#undef HAVE_SYS_TIME_H
-
-/* Define to 1 if you have the header file. */
-#undef HAVE_SYS_TYPES_H
-
-/* Define to 1 if you have the `time' function. */
-#undef HAVE_TIME
-
-/* Define to 1 if you have the header file. */
-#undef HAVE_TIME_H
-
-/* Define to 1 if you have the header file. */
-#undef HAVE_UNISTD_H
-
-/* Define to 1 if you have the `__setfpucw' function. */
-#undef HAVE___SETFPUCW
-
-/* Define to the address where bug reports for this package should be sent. */
-#undef PACKAGE_BUGREPORT
-
-/* Define to the full name of this package. */
-#undef PACKAGE_NAME
-
-/* Define to the full name and version of this package. */
-#undef PACKAGE_STRING
-
-/* Define to the one symbol short name of this package. */
-#undef PACKAGE_TARNAME
-
-/* Define to the version of this package. */
-#undef PACKAGE_VERSION
-
-/* Define as the return type of signal handlers (`int' or `void'). */
-#undef RETSIGTYPE
-
-/* Define to 1 if you have the ANSI C header files. */
-#undef STDC_HEADERS
Index: func.c
===================================================================
--- func.c (revision 816)
+++ func.c (nonexistent)
@@ -1,1115 +0,0 @@
-/*
- * func.c, misc simulator functions. This file is part of SIS.
- *
- * SIS, SPARC instruction simulator V1.8 Copyright (C) 1995 Jiri Gaisler,
- * European Space Agency
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 675
- * Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include
-#include
-#include
-#include
-#include
-#include "sis.h"
-#include "end.h"
-#include
-#include "sim-config.h"
-
-
-#define VAL(x) strtoul(x,(char **)NULL,0)
-
-extern int current_target_byte_order;
-struct disassemble_info dinfo;
-struct pstate sregs;
-extern struct estate ebase;
-int ctrl_c = 0;
-int sis_verbose = 0;
-char *sis_version = "2.7.5";
-int nfp = 0;
-int ift = 0;
-int wrp = 0;
-int rom8 = 0;
-int uben = 0;
-int termsave;
-int sparclite = 0; /* emulating SPARClite instructions? */
-int sparclite_board = 0; /* emulating SPARClite board RAM? */
-char uart_dev1[128] = "";
-char uart_dev2[128] = "";
-extern int ext_irl;
-uint32 last_load_addr = 0;
-
-#ifdef ERRINJ
-uint32 errcnt = 0;
-uint32 errper = 0;
-uint32 errtt = 0;
-uint32 errftt = 0;
-uint32 errmec = 0;
-#endif
-
-/* Forward declarations */
-
-static int batch PARAMS ((struct pstate *sregs, char *fname));
-static void set_rega PARAMS ((struct pstate *sregs, char *reg, uint32 rval));
-static void disp_reg PARAMS ((struct pstate *sregs, char *reg));
-static uint32 limcalc PARAMS ((float32 freq));
-static void int_handler PARAMS ((int32 sig));
-static void init_event PARAMS ((void));
-static int disp_fpu PARAMS ((struct pstate *sregs));
-static void disp_regs PARAMS ((struct pstate *sregs, int cwp));
-static void disp_ctrl PARAMS ((struct pstate *sregs));
-static void disp_mem PARAMS ((uint32 addr, uint32 len));
-
-static int
-batch(sregs, fname)
- struct pstate *sregs;
- char *fname;
-{
- FILE *fp;
- char lbuf[1024];
-
- if ((fp = fopen(fname, "r")) == NULL) {
- fprintf(stderr, "couldn't open batch file %s\n", fname);
- return (0);
- }
- while (!feof(fp)) {
- lbuf[0] = 0;
- fgets(lbuf, 1023, fp);
- if ((strlen(lbuf) > 0) && (lbuf[strlen(lbuf) - 1] == '\n'))
- lbuf[strlen(lbuf) - 1] = 0;
- printf("sis> %s\n", lbuf);
- exec_cmd(sregs, lbuf);
- }
- fclose(fp);
- return (1);
-}
-
-void
-set_regi(sregs, reg, rval)
- struct pstate *sregs;
- int32 reg;
- uint32 rval;
-{
- uint32 cwp;
-
- cwp = ((sregs->psr & 0x7) << 4);
- if ((reg > 0) && (reg < 8)) {
- sregs->g[reg] = rval;
- } else if ((reg >= 8) && (reg < 32)) {
- sregs->r[(cwp + reg) & 0x7f] = rval;
- } else if ((reg >= 32) && (reg < 64)) {
- sregs->fsi[reg - 32] = rval;
- } else {
- switch (reg) {
- case 64:
- sregs->y = rval;
- break;
- case 65:
- sregs->psr = rval;
- break;
- case 66:
- sregs->wim = rval;
- break;
- case 67:
- sregs->tbr = rval;
- break;
- case 68:
- sregs->pc = rval;
- break;
- case 69:
- sregs->npc = rval;
- break;
- case 70:
- sregs->fsr = rval;
- set_fsr(rval);
- break;
- default:break;
- }
- }
-}
-
-void
-get_regi(struct pstate * sregs, int32 reg, char *buf)
-{
- uint32 cwp;
- uint32 rval = 0;
-
- cwp = ((sregs->psr & 0x7) << 4);
- if ((reg >= 0) && (reg < 8)) {
- rval = sregs->g[reg];
- } else if ((reg >= 8) && (reg < 32)) {
- rval = sregs->r[(cwp + reg) & 0x7f];
- } else if ((reg >= 32) && (reg < 64)) {
- rval = sregs->fsi[reg - 32];
- } else {
- switch (reg) {
- case 64:
- rval = sregs->y;
- break;
- case 65:
- rval = sregs->psr;
- break;
- case 66:
- rval = sregs->wim;
- break;
- case 67:
- rval = sregs->tbr;
- break;
- case 68:
- rval = sregs->pc;
- break;
- case 69:
- rval = sregs->npc;
- break;
- case 70:
- rval = sregs->fsr;
- break;
- default:break;
- }
- }
- if (current_target_byte_order == BIG_ENDIAN) {
- buf[0] = (rval >> 24) & 0x0ff;
- buf[1] = (rval >> 16) & 0x0ff;
- buf[2] = (rval >> 8) & 0x0ff;
- buf[3] = rval & 0x0ff;
- }
- else {
- buf[3] = (rval >> 24) & 0x0ff;
- buf[2] = (rval >> 16) & 0x0ff;
- buf[1] = (rval >> 8) & 0x0ff;
- buf[0] = rval & 0x0ff;
- }
-}
-
-
-static void
-set_rega(sregs, reg, rval)
- struct pstate *sregs;
- char *reg;
- uint32 rval;
-{
- uint32 cwp;
- int32 err = 0;
-
- cwp = ((sregs->psr & 0x7) << 4);
- if (strcmp(reg, "psr") == 0)
- sregs->psr = (rval = (rval & 0x00f03fff));
- else if (strcmp(reg, "tbr") == 0)
- sregs->tbr = (rval = (rval & 0xfffffff0));
- else if (strcmp(reg, "wim") == 0)
- sregs->wim = (rval = (rval & 0x0ff));
- else if (strcmp(reg, "y") == 0)
- sregs->y = rval;
- else if (strcmp(reg, "pc") == 0)
- sregs->pc = rval;
- else if (strcmp(reg, "npc") == 0)
- sregs->npc = rval;
- else if (strcmp(reg, "fsr") == 0) {
- sregs->fsr = rval;
- set_fsr(rval);
- } else if (strcmp(reg, "g0") == 0)
- err = 2;
- else if (strcmp(reg, "g1") == 0)
- sregs->g[1] = rval;
- else if (strcmp(reg, "g2") == 0)
- sregs->g[2] = rval;
- else if (strcmp(reg, "g3") == 0)
- sregs->g[3] = rval;
- else if (strcmp(reg, "g4") == 0)
- sregs->g[4] = rval;
- else if (strcmp(reg, "g5") == 0)
- sregs->g[5] = rval;
- else if (strcmp(reg, "g6") == 0)
- sregs->g[6] = rval;
- else if (strcmp(reg, "g7") == 0)
- sregs->g[7] = rval;
- else if (strcmp(reg, "o0") == 0)
- sregs->r[(cwp + 8) & 0x7f] = rval;
- else if (strcmp(reg, "o1") == 0)
- sregs->r[(cwp + 9) & 0x7f] = rval;
- else if (strcmp(reg, "o2") == 0)
- sregs->r[(cwp + 10) & 0x7f] = rval;
- else if (strcmp(reg, "o3") == 0)
- sregs->r[(cwp + 11) & 0x7f] = rval;
- else if (strcmp(reg, "o4") == 0)
- sregs->r[(cwp + 12) & 0x7f] = rval;
- else if (strcmp(reg, "o5") == 0)
- sregs->r[(cwp + 13) & 0x7f] = rval;
- else if (strcmp(reg, "o6") == 0)
- sregs->r[(cwp + 14) & 0x7f] = rval;
- else if (strcmp(reg, "o7") == 0)
- sregs->r[(cwp + 15) & 0x7f] = rval;
- else if (strcmp(reg, "l0") == 0)
- sregs->r[(cwp + 16) & 0x7f] = rval;
- else if (strcmp(reg, "l1") == 0)
- sregs->r[(cwp + 17) & 0x7f] = rval;
- else if (strcmp(reg, "l2") == 0)
- sregs->r[(cwp + 18) & 0x7f] = rval;
- else if (strcmp(reg, "l3") == 0)
- sregs->r[(cwp + 19) & 0x7f] = rval;
- else if (strcmp(reg, "l4") == 0)
- sregs->r[(cwp + 20) & 0x7f] = rval;
- else if (strcmp(reg, "l5") == 0)
- sregs->r[(cwp + 21) & 0x7f] = rval;
- else if (strcmp(reg, "l6") == 0)
- sregs->r[(cwp + 22) & 0x7f] = rval;
- else if (strcmp(reg, "l7") == 0)
- sregs->r[(cwp + 23) & 0x7f] = rval;
- else if (strcmp(reg, "i0") == 0)
- sregs->r[(cwp + 24) & 0x7f] = rval;
- else if (strcmp(reg, "i1") == 0)
- sregs->r[(cwp + 25) & 0x7f] = rval;
- else if (strcmp(reg, "i2") == 0)
- sregs->r[(cwp + 26) & 0x7f] = rval;
- else if (strcmp(reg, "i3") == 0)
- sregs->r[(cwp + 27) & 0x7f] = rval;
- else if (strcmp(reg, "i4") == 0)
- sregs->r[(cwp + 28) & 0x7f] = rval;
- else if (strcmp(reg, "i5") == 0)
- sregs->r[(cwp + 29) & 0x7f] = rval;
- else if (strcmp(reg, "i6") == 0)
- sregs->r[(cwp + 30) & 0x7f] = rval;
- else if (strcmp(reg, "i7") == 0)
- sregs->r[(cwp + 31) & 0x7f] = rval;
- else
- err = 1;
- switch (err) {
- case 0:
- printf("%s = %d (0x%08x)\n", reg, rval, rval);
- break;
- case 1:
- printf("no such regiser: %s\n", reg);
- break;
- case 2:
- printf("cannot set g0\n");
- break;
- default:
- break;
- }
-
-}
-
-static void
-disp_reg(sregs, reg)
- struct pstate *sregs;
- char *reg;
-{
- if (strncmp(reg, "w",1) == 0)
- disp_regs(sregs, VAL(®[1]));
-}
-
-#ifdef ERRINJ
-
-void
-errinj()
-{
- int err;
-
- switch (err = (random() % 12)) {
- case 0: errtt = 0x61; break;
- case 1: errtt = 0x62; break;
- case 2: errtt = 0x63; break;
- case 3: errtt = 0x64; break;
- case 4: errtt = 0x65; break;
- case 5:
- case 6:
- case 7: errftt = err;
- break;
- case 8: errmec = 1; break;
- case 9: errmec = 2; break;
- case 10: errmec = 5; break;
- case 11: errmec = 6; break;
- }
- errcnt++;
- if (errper) event(errinj, 0, (random()%errper));
-}
-
-void
-errinjstart()
-{
- if (errper) event(errinj, 0, (random()%errper));
-}
-
-#endif
-
-static uint32
-limcalc (freq)
- float32 freq;
-{
- uint32 unit, lim;
- double flim;
- char *cmd1, *cmd2;
-
- unit = 1;
- lim = -1;
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- lim = VAL(cmd1);
- if ((cmd2 = strtok(NULL, " \t\n\r")) != NULL) {
- if (strcmp(cmd2,"us")==0) unit = 1;
- if (strcmp(cmd2,"ms")==0) unit = 1000;
- if (strcmp(cmd2,"s")==0) unit = 1000000;
- }
- flim = (double) lim * (double) unit * (double) freq +
- (double) ebase.simtime;
- if ((flim > ebase.simtime) && (flim < 4294967296.0)) {
- lim = (uint32) flim;
- } else {
- printf("error in expression\n");
- lim = -1;
- }
- }
- return (lim);
-}
-
-int
-exec_cmd(sregs, cmd)
- char *cmd;
- struct pstate *sregs;
-{
- char *cmd1, *cmd2;
- int32 stat;
- uint32 len, i, clen, j;
- static uint32 daddr = 0;
- char *cmdsave;
-
- stat = OK;
- cmdsave = strdup(cmd);
- if ((cmd1 = strtok(cmd, " \t")) != NULL) {
- clen = strlen(cmd1);
- if (strncmp(cmd1, "bp", clen) == 0) {
- for (i = 0; i < sregs->bptnum; i++) {
- printf(" %d : 0x%08x\n", i + 1, sregs->bpts[i]);
- }
- } else if (strncmp(cmd1, "+bp", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- sregs->bpts[sregs->bptnum] = VAL(cmd1) & ~0x3;
- printf("added breakpoint %d at 0x%08x\n",
- sregs->bptnum + 1, sregs->bpts[sregs->bptnum]);
- sregs->bptnum += 1;
- }
- } else if (strncmp(cmd1, "-bp", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- i = VAL(cmd1) - 1;
- if ((i >= 0) && (i < sregs->bptnum)) {
- printf("deleted breakpoint %d at 0x%08x\n", i + 1,
- sregs->bpts[i]);
- for (; i < sregs->bptnum - 1; i++) {
- sregs->bpts[i] = sregs->bpts[i + 1];
- }
- sregs->bptnum -= 1;
- }
- }
- } else if (strncmp(cmd1, "batch", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) == NULL) {
- printf("no file specified\n");
- } else {
- batch(sregs, cmd1);
- }
- } else if (strncmp(cmd1, "cont", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) == NULL) {
- stat = run_sim(sregs, -1, 0);
- } else {
- stat = run_sim(sregs, VAL(cmd1), 0);
- }
- daddr = sregs->pc;
- sim_halt();
- } else if (strncmp(cmd1, "debug", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- sis_verbose = VAL(cmd1);
- }
- printf("Debug level = %d\n",sis_verbose);
- } else if (strncmp(cmd1, "dis", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- daddr = VAL(cmd1);
- }
- if ((cmd2 = strtok(NULL, " \t\n\r")) != NULL) {
- len = VAL(cmd2);
- } else
- len = 16;
- printf("\n");
- dis_mem(daddr, len, &dinfo);
- printf("\n");
- daddr += len * 4;
- } else if (strncmp(cmd1, "echo", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- printf("%s\n", (&cmdsave[clen+1]));
- }
-#ifdef ERRINJ
- } else if (strncmp(cmd1, "error", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- errper = VAL(cmd1);
- if (errper) {
- event(errinj, 0, (len = (random()%errper)));
- printf("Error injection started with period %d\n",len);
- }
- } else printf("Injected errors: %d\n",errcnt);
-#endif
- } else if (strncmp(cmd1, "float", clen) == 0) {
- stat = disp_fpu(sregs);
- } else if (strncmp(cmd1, "go", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) == NULL) {
- len = last_load_addr;
- } else {
- len = VAL(cmd1);
- }
- sregs->pc = len & ~3;
- sregs->npc = sregs->pc + 4;
- printf("resuming at 0x%08x\n",sregs->pc);
- if ((cmd2 = strtok(NULL, " \t\n\r")) != NULL) {
- stat = run_sim(sregs, VAL(cmd2), 0);
- } else {
- stat = run_sim(sregs, -1, 0);
- }
- daddr = sregs->pc;
- sim_halt();
- } else if (strncmp(cmd1, "help", clen) == 0) {
- gen_help();
- } else if (strncmp(cmd1, "history", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- sregs->histlen = VAL(cmd1);
- if (sregs->histbuf != NULL)
- free(sregs->histbuf);
- sregs->histbuf = (struct histype *) calloc(sregs->histlen, sizeof(struct histype));
- printf("trace history length = %d\n\r", sregs->histlen);
- sregs->histind = 0;
-
- } else {
- j = sregs->histind;
- for (i = 0; i < sregs->histlen; i++) {
- if (j >= sregs->histlen)
- j = 0;
- printf(" %8d ", sregs->histbuf[j].time);
- dis_mem(sregs->histbuf[j].addr, 1, &dinfo);
- j++;
- }
- }
-
- } else if (strncmp(cmd1, "load", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- last_load_addr = bfd_load(cmd1);
- while ((cmd1 = strtok(NULL, " \t\n\r")) != NULL)
- last_load_addr = bfd_load(cmd1);
- } else {
- printf("load: no file specified\n");
- }
- } else if (strncmp(cmd1, "mem", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL)
- daddr = VAL(cmd1);
- if ((cmd2 = strtok(NULL, " \t\n\r")) != NULL)
- len = VAL(cmd2);
- else
- len = 64;
- disp_mem(daddr, len);
- daddr += len;
- } else if (strncmp(cmd1, "perf", clen) == 0) {
- cmd1 = strtok(NULL, " \t\n\r");
- if ((cmd1 != NULL) &&
- (strncmp(cmd1, "reset", strlen(cmd1)) == 0)) {
- reset_stat(sregs);
- } else
- show_stat(sregs);
- } else if (strncmp(cmd1, "quit", clen) == 0) {
- exit(0);
- } else if (strncmp(cmd1, "reg", clen) == 0) {
- cmd1 = strtok(NULL, " \t\n\r");
- cmd2 = strtok(NULL, " \t\n\r");
- if (cmd2 != NULL)
- set_rega(sregs, cmd1, VAL(cmd2));
- else if (cmd1 != NULL)
- disp_reg(sregs, cmd1);
- else {
- disp_regs(sregs,sregs->psr);
- disp_ctrl(sregs);
- }
- } else if (strncmp(cmd1, "reset", clen) == 0) {
- ebase.simtime = 0;
- reset_all();
- reset_stat(sregs);
- } else if (strncmp(cmd1, "run", clen) == 0) {
- ebase.simtime = 0;
- reset_all();
- reset_stat(sregs);
- if ((cmd1 = strtok(NULL, " \t\n\r")) == NULL) {
- stat = run_sim(sregs, -1, 0);
- } else {
- stat = run_sim(sregs, VAL(cmd1), 0);
- }
- daddr = sregs->pc;
- sim_halt();
- } else if (strncmp(cmd1, "shell", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- system(&cmdsave[clen]);
- }
- } else if (strncmp(cmd1, "step", clen) == 0) {
- stat = run_sim(sregs, 1, 1);
- daddr = sregs->pc;
- sim_halt();
- } else if (strncmp(cmd1, "tcont", clen) == 0) {
- sregs->tlimit = limcalc(sregs->freq);
- stat = run_sim(sregs, -1, 0);
- daddr = sregs->pc;
- sim_halt();
- } else if (strncmp(cmd1, "tgo", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) == NULL) {
- len = last_load_addr;
- } else {
- len = VAL(cmd1);
- sregs->tlimit = limcalc(sregs->freq);
- }
- sregs->pc = len & ~3;
- sregs->npc = sregs->pc + 4;
- printf("resuming at 0x%08x\n",sregs->pc);
- stat = run_sim(sregs, -1, 0);
- daddr = sregs->pc;
- sim_halt();
- } else if (strncmp(cmd1, "tlimit", clen) == 0) {
- sregs->tlimit = limcalc(sregs->freq);
- if (sregs->tlimit != (uint32) -1)
- printf("simulation limit = %u (%.3f ms)\n",(uint32) sregs->tlimit,
- sregs->tlimit / sregs->freq / 1000);
- } else if (strncmp(cmd1, "tra", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) == NULL) {
- stat = run_sim(sregs, -1, 1);
- } else {
- stat = run_sim(sregs, VAL(cmd1), 1);
- }
- printf("\n");
- daddr = sregs->pc;
- sim_halt();
- } else if (strncmp(cmd1, "trun", clen) == 0) {
- ebase.simtime = 0;
- reset_all();
- reset_stat(sregs);
- sregs->tlimit = limcalc(sregs->freq);
- stat = run_sim(sregs, -1, 0);
- daddr = sregs->pc;
- sim_halt();
- } else
- printf("syntax error\n");
- }
- if (cmdsave != NULL)
- free(cmdsave);
- return (stat);
-}
-
-
-void
-reset_stat(sregs)
- struct pstate *sregs;
-{
- sregs->tottime = 0;
- sregs->pwdtime = 0;
- sregs->ninst = 0;
- sregs->fholdt = 0;
- sregs->holdt = 0;
- sregs->icntt = 0;
- sregs->finst = 0;
- sregs->nstore = 0;
- sregs->nload = 0;
- sregs->nbranch = 0;
- sregs->simstart = ebase.simtime;
-
-}
-
-void
-show_stat(sregs)
- struct pstate *sregs;
-{
- uint32 iinst;
- uint32 stime, tottime;
-
- if (sregs->tottime == 0) tottime = 1; else tottime = sregs->tottime;
- stime = ebase.simtime - sregs->simstart; /* Total simulated time */
-#ifdef STAT
-
- iinst = sregs->ninst - sregs->finst - sregs->nload - sregs->nstore -
- sregs->nbranch;
-#endif
-
- printf("\n Cycles : %9d\n\r", ebase.simtime - sregs->simstart);
- printf(" Instructions : %9d\n", sregs->ninst);
-
-#ifdef STAT
- printf(" integer : %9.2f %%\n", 100.0 * (float) iinst / (float) sregs->ninst);
- printf(" load : %9.2f %%\n",
- 100.0 * (float) sregs->nload / (float) sregs->ninst);
- printf(" store : %9.2f %%\n",
- 100.0 * (float) sregs->nstore / (float) sregs->ninst);
- printf(" branch : %9.2f %%\n",
- 100.0 * (float) sregs->nbranch / (float) sregs->ninst);
- printf(" float : %9.2f %%\n",
- 100.0 * (float) sregs->finst / (float) sregs->ninst);
- printf(" Integer CPI : %9.2f\n",
- ((float) (stime - sregs->pwdtime - sregs->fholdt - sregs->finst))
- /
- (float) (sregs->ninst - sregs->finst));
- printf(" Float CPI : %9.2f\n",
- ((float) sregs->fholdt / (float) sregs->finst) + 1.0);
-#endif
- printf(" Overall CPI : %9.2f\n",
- (float) (stime - sregs->pwdtime) / (float) sregs->ninst);
- printf("\n ERC32 performance (%4.1f MHz): %5.2f MOPS (%5.2f MIPS, %5.2f MFLOPS)\n",
- sregs->freq, sregs->freq * (float) sregs->ninst / (float) (stime - sregs->pwdtime),
- sregs->freq * (float) (sregs->ninst - sregs->finst) /
- (float) (stime - sregs->pwdtime),
- sregs->freq * (float) sregs->finst / (float) (stime - sregs->pwdtime));
- printf(" Simulated ERC32 time : %5.2f ms\n", (float) (ebase.simtime - sregs->simstart) / 1000.0 / sregs->freq);
- printf(" Processor utilisation : %5.2f %%\n", 100.0 * (1.0 - ((float) sregs->pwdtime / (float) stime)));
- printf(" Real-time / simulator-time : 1/%.2f \n",
- ((float) sregs->tottime) / ((float) (stime) / (sregs->freq * 1.0E6)));
- printf(" Simulator performance : %d KIPS\n",sregs->ninst/tottime/1000);
- printf(" Used time (sys + user) : %3d s\n\n", sregs->tottime);
-}
-
-
-
-void
-init_bpt(sregs)
- struct pstate *sregs;
-{
- sregs->bptnum = 0;
- sregs->histlen = 0;
- sregs->histind = 0;
- sregs->histbuf = NULL;
- sregs->tlimit = -1;
-}
-
-static void
-int_handler(sig)
- int32 sig;
-{
- if (sig != 2)
- printf("\n\n Signal handler error (%d)\n\n", sig);
- ctrl_c = 1;
-}
-
-void
-init_signals()
-{
- typedef void (*PFI) ();
- static PFI int_tab[2];
-
- int_tab[0] = signal(SIGTERM, int_handler);
- int_tab[1] = signal(SIGINT, int_handler);
-}
-
-
-extern struct disassemble_info dinfo;
-
-struct estate ebase;
-struct evcell evbuf[EVENT_MAX];
-struct irqcell irqarr[16];
-
-static int
-disp_fpu(sregs)
- struct pstate *sregs;
-{
-
- int i;
- float t;
-
- printf("\n fsr: %08X\n\n", sregs->fsr);
-
-#ifdef HOST_LITTLE_ENDIAN_FLOAT
- for (i = 0; i < 32; i++)
- sregs->fdp[i ^ 1] = sregs->fs[i];
-#endif
-
- for (i = 0; i < 32; i++) {
- t = sregs->fs[i];
- printf(" f%02d %08x %14e ", i, sregs->fsi[i], sregs->fs[i]);
- if (!(i & 1))
- printf("%14e\n", sregs->fd[i >> 1]);
- else
- printf("\n");
- }
- printf("\n");
- return (OK);
-}
-
-static void
-disp_regs(sregs,cwp)
- struct pstate *sregs;
- int cwp;
-{
-
- int i;
-
- cwp = ((cwp & 0x7) << 4);
- printf("\n\t INS LOCALS OUTS GLOBALS\n");
- for (i = 0; i < 8; i++) {
- printf(" %d: %08X %08X %08X %08X\n", i,
- sregs->r[(cwp + i + 24) & 0x7f],
- sregs->r[(cwp + i + 16) & 0x7f], sregs->r[(cwp + i + 8) & 0x7f],
- sregs->g[i]);
- }
-}
-
-static void
-disp_ctrl(sregs)
- struct pstate *sregs;
-{
-
- unsigned char i[4];
-
- printf("\n psr: %08X wim: %08X tbr: %08X y: %08X\n",
- sregs->psr, sregs->wim, sregs->tbr, sregs->y);
- sis_memory_read(sregs->pc, i, 4);
- printf("\n pc: %08X = %02X%02X%02X%02X ", sregs->pc,i[0],i[1],i[2],i[3]);
- print_insn_sparc(sregs->pc, &dinfo);
- sis_memory_read(sregs->npc, i, 4);
- printf("\n npc: %08X = %02X%02X%02X%02X ",sregs->npc,i[0],i[1],i[2],i[3]);
- print_insn_sparc(sregs->npc, &dinfo);
- if (sregs->err_mode)
- printf("\n IU in error mode");
- printf("\n\n");
-}
-
-static void
-disp_mem(addr, len)
- uint32 addr;
- uint32 len;
-{
-
- uint32 i;
- unsigned char data[4];
- uint32 mem[4], j;
- char *p;
-
- for (i = addr & ~3; i < ((addr + len) & ~3); i += 16) {
- printf("\n %8X ", i);
- for (j = 0; j < 4; j++) {
- sis_memory_read((i + (j * 4)), data, 4);
- printf("%02x%02x%02x%02x ", data[0],data[1],data[2],data[3]);
- mem[j] = *((int *) &data);
- }
- printf(" ");
- p = (char *) mem;
- for (j = 0; j < 16; j++) {
- if (isprint(p[j]))
- putchar(p[j]);
- else
- putchar('.');
- }
- }
- printf("\n\n");
-}
-
-void
-dis_mem(addr, len, info)
- uint32 addr;
- uint32 len;
- struct disassemble_info *info;
-{
- uint32 i;
- unsigned char data[4];
-
- for (i = addr & -3; i < ((addr & -3) + (len << 2)); i += 4) {
- sis_memory_read(i, data, 4);
- printf(" %08x %02x%02x%02x%02x ", i, data[0],data[1],data[2],data[3]);
- print_insn_sparc(i, info);
- if (i >= 0xfffffffc) break;
- printf("\n");
- }
-}
-
-/* Add event to event queue */
-
-void
-event(cfunc, arg, delta)
- void (*cfunc) ();
- int32 arg;
- uint32 delta;
-{
- struct evcell *ev1, *evins;
-
- if (ebase.freeq == NULL) {
- printf("Error, too many events in event queue\n");
- return;
- }
- ev1 = &ebase.eq;
- delta += ebase.simtime;
- while ((ev1->nxt != NULL) && (ev1->nxt->time <= delta)) {
- ev1 = ev1->nxt;
- }
- if (ev1->nxt == NULL) {
- ev1->nxt = ebase.freeq;
- ebase.freeq = ebase.freeq->nxt;
- ev1->nxt->nxt = NULL;
- } else {
- evins = ebase.freeq;
- ebase.freeq = ebase.freeq->nxt;
- evins->nxt = ev1->nxt;
- ev1->nxt = evins;
- }
- ev1->nxt->time = delta;
- ev1->nxt->cfunc = cfunc;
- ev1->nxt->arg = arg;
-}
-
-#if 0 /* apparently not used */
-void
-stop_event()
-{
-}
-#endif
-
-void
-init_event()
-{
- int32 i;
-
- ebase.eq.nxt = NULL;
- ebase.freeq = evbuf;
- for (i = 0; i < EVENT_MAX; i++) {
- evbuf[i].nxt = &evbuf[i + 1];
- }
- evbuf[EVENT_MAX - 1].nxt = NULL;
-}
-
-void
-set_int(level, callback, arg)
- int32 level;
- void (*callback) ();
- int32 arg;
-{
- irqarr[level & 0x0f].callback = callback;
- irqarr[level & 0x0f].arg = arg;
-}
-
-/* Advance simulator time */
-
-void
-advance_time(sregs)
- struct pstate *sregs;
-{
-
- struct evcell *evrem;
- void (*cfunc) ();
- uint32 arg, endtime;
-
-#ifdef STAT
- sregs->fholdt += sregs->fhold;
- sregs->holdt += sregs->hold;
- sregs->icntt += sregs->icnt;
-#endif
-
- endtime = ebase.simtime + sregs->icnt + sregs->hold + sregs->fhold;
-
- while ((ebase.eq.nxt->time <= (endtime)) && (ebase.eq.nxt != NULL)) {
- ebase.simtime = ebase.eq.nxt->time;
- cfunc = ebase.eq.nxt->cfunc;
- arg = ebase.eq.nxt->arg;
- evrem = ebase.eq.nxt;
- ebase.eq.nxt = ebase.eq.nxt->nxt;
- evrem->nxt = ebase.freeq;
- ebase.freeq = evrem;
- cfunc(arg);
- }
- ebase.simtime = endtime;
-
-}
-
-uint32
-now()
-{
- return(ebase.simtime);
-}
-
-
-/* Advance time until an external interrupt is seen */
-
-int
-wait_for_irq()
-{
- struct evcell *evrem;
- void (*cfunc) ();
- int32 arg, endtime;
-
- if (ebase.eq.nxt == NULL)
- printf("Warning: event queue empty - power-down mode not entered\n");
- endtime = ebase.simtime;
- while (!ext_irl && (ebase.eq.nxt != NULL)) {
- ebase.simtime = ebase.eq.nxt->time;
- cfunc = ebase.eq.nxt->cfunc;
- arg = ebase.eq.nxt->arg;
- evrem = ebase.eq.nxt;
- ebase.eq.nxt = ebase.eq.nxt->nxt;
- evrem->nxt = ebase.freeq;
- ebase.freeq = evrem;
- cfunc(arg);
- if (ctrl_c) {
- printf("\bwarning: power-down mode interrupted\n");
- break;
- }
- }
- sregs.pwdtime += ebase.simtime - endtime;
- return (ebase.simtime - endtime);
-}
-
-int
-check_bpt(sregs)
- struct pstate *sregs;
-{
- int32 i;
-
- if ((sregs->bphit) || (sregs->annul))
- return (0);
- for (i = 0; i < (int32) sregs->bptnum; i++) {
- if (sregs->pc == sregs->bpts[i])
- return (BPT_HIT);
- }
- return (0);
-}
-
-void
-reset_all()
-{
- init_event(); /* Clear event queue */
- init_regs(&sregs);
- reset();
-#ifdef ERRINJ
- errinjstart();
-#endif
-}
-
-void
-sys_reset()
-{
- reset_all();
- sregs.trap = 256; /* Force fake reset trap */
-}
-
-void
-sys_halt()
-{
- sregs.trap = 257; /* Force fake halt trap */
-}
-
-#include "ansidecl.h"
-
-#include
-
-#include "libiberty.h"
-#include "bfd.h"
-
-#define min(A, B) (((A) < (B)) ? (A) : (B))
-#define LOAD_ADDRESS 0
-
-int
-bfd_load(fname)
- char *fname;
-{
- asection *section;
- bfd *pbfd;
- const bfd_arch_info_type *arch;
-
- pbfd = bfd_openr(fname, 0);
-
- if (pbfd == NULL) {
- printf("open of %s failed\n", fname);
- return (-1);
- }
- if (!bfd_check_format(pbfd, bfd_object)) {
- printf("file %s doesn't seem to be an object file\n", fname);
- return (-1);
- }
-
- arch = bfd_get_arch_info (pbfd);
- if (bfd_little_endian (pbfd) || arch->mach == bfd_mach_sparc_sparclite_le)
- current_target_byte_order = LITTLE_ENDIAN;
- else
- current_target_byte_order = BIG_ENDIAN;
- if (sis_verbose)
- printf("file %s is %s-endian.\n", fname,
- current_target_byte_order == BIG_ENDIAN ? "big" : "little");
-
- if (sis_verbose)
- printf("loading %s:", fname);
- for (section = pbfd->sections; section; section = section->next) {
- if (bfd_get_section_flags(pbfd, section) & SEC_ALLOC) {
- bfd_vma section_address;
- unsigned long section_size;
- const char *section_name;
-
- section_name = bfd_get_section_name(pbfd, section);
-
- section_address = bfd_get_section_vma(pbfd, section);
- /*
- * Adjust sections from a.out files, since they don't carry their
- * addresses with.
- */
- if (bfd_get_flavour(pbfd) == bfd_target_aout_flavour) {
- if (strcmp (section_name, ".text") == 0)
- section_address = bfd_get_start_address (pbfd);
- else if (strcmp (section_name, ".data") == 0) {
- /* Read the first 8 bytes of the data section.
- There should be the string 'DaTa' followed by
- a word containing the actual section address. */
- struct data_marker
- {
- char signature[4]; /* 'DaTa' */
- unsigned char sdata[4]; /* &sdata */
- } marker;
- bfd_get_section_contents (pbfd, section, &marker, 0,
- sizeof (marker));
- if (strncmp (marker.signature, "DaTa", 4) == 0)
- {
- if (current_target_byte_order == BIG_ENDIAN)
- section_address = bfd_getb32 (marker.sdata);
- else
- section_address = bfd_getl32 (marker.sdata);
- }
- }
- }
-
- section_size = bfd_section_size(pbfd, section);
-
- if (sis_verbose)
- printf("\nsection %s at 0x%08lx (0x%lx bytes)",
- section_name, section_address, section_size);
-
- /* Text, data or lit */
- if (bfd_get_section_flags(pbfd, section) & SEC_LOAD) {
- file_ptr fptr;
-
- fptr = 0;
-
- while (section_size > 0) {
- char buffer[1024];
- int count;
-
- count = min(section_size, 1024);
-
- bfd_get_section_contents(pbfd, section, buffer, fptr, count);
-
- sis_memory_write(section_address, buffer, count);
-
- section_address += count;
- fptr += count;
- section_size -= count;
- }
- } else /* BSS */
- if (sis_verbose)
- printf("(not loaded)");
- }
- }
- if (sis_verbose)
- printf("\n");
-
- return(bfd_get_start_address (pbfd));
-}
func.c
Property changes :
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Index: NEWS
===================================================================
--- NEWS (revision 816)
+++ NEWS (nonexistent)
@@ -1,108 +0,0 @@
-
-version 2.0 05-02-96
---------------------
-
-* Switched to bfd library. Any supported format (elf, coff, ...) can be used.
-* The UART devices can be set through -uart1 and -uart2 switches.
-* Switched to GNU readline.
-* Added -c option to run batch files at startup
-* 'reg' command can show different register windows (eg 'reg w3').
-* Use 'help' for online help on simulator commands
-
-version 1.8.1 20-01-96
---------------------
-
-* added -mevrev0 switch to simulate MEC rev.0 bugs in timer and uart
-
-* added -iurev0 switch to simulate IU rev.0 jmpl/restore bug
-
-* Added sis command 'batch' to run batch files
-
-
-version 1.8 30-10-95
---------------------
-
-* Added s-record support. Use the '-s' switch with sis or the 'load' command.
-
-* IU load dependencies are now modelled
-
-version 1.7 30-10-95
---------------------
-
-* Power-down mode implemented in erc32.c.
-
-* Performance display shows the ratio between simulator-time and real-time.
-
-
-version 1.6.2 25-10-95
---------------------
-
-* The UARTs can now be run at a given speed (simulator time) to better
- simulate the behaviour of interrupt routines. The "true mode" is
- selected through a compile switch in the makefile.
-
-
-version 1.6 28-09-95
---------------------
-
-* Major reorganisation of the code. mec.c and mem.c merged into erc32.c.
-
-* The load command does NOT longer load the initialised data at an address
- defined by .bdata. This is done in srt0.s using _environ.
-
-* Additional MEC functionallity added - software reset, memory access
- protection and waitstate configuration register.
-
-* interf.c - a GDB interface added
-
-* -v switch (verbose) added
-
-version 1.5 14-09-95
---------------------
-
-* Added a instruction trace buffer, enabled through the 'hist' command.
-
-* Added a 'perf' command to display statistics such as instruction mix,
- CPI, FPU holds etc.
-
-* Added -nfp switch to disable FPU.
-
-* Added -freq switch to set simulated frequency.
-
-version 1.4 22-08-95
---------------------
-
-* A -g is provided for those who have problems with GNU readline().
-
-version 1.3 26-07-95
---------------------
-
-* No major news, just a bug fix release ...
-
-
-version 1.2 13-07-95
---------------------
-
-* Added setting of IU registers through the 'reg' command. See README.
-
-* The GNU readline() function is used for command input. However, a
-ctrl-D still kills the simulator ...
-
-
-version 1.1 07-07-95
---------------------
-
-
-* Added a 'go' command
-
-* Added cycle counting for interrupt overhead.
-
-* Function 'get_mem_ptr' takes one more parameter to avoid segmentation
- faults if a.out files are loaded outside the simulated memory. See README.
-
-* Added user-defined function sim_stop().
-
-* Added a reset command. See README.
-
-* Implemented buffered output for MEC uarts to improve output speed.
-
NEWS
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
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Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property