URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/gnu-old/gdb-7.1/sim/mn10300
- from Rev 834 to Rev 842
- ↔ Reverse comparison
Rev 834 → Rev 842
/op_utils.c
0,0 → 1,227
#include "sim-main.h" |
#include "targ-vals.h" |
|
#ifdef HAVE_UTIME_H |
#include <utime.h> |
#endif |
|
#ifdef HAVE_TIME_H |
#include <time.h> |
#endif |
|
#ifdef HAVE_UNISTD_H |
#include <unistd.h> |
#endif |
|
#ifdef HAVE_STRING_H |
#include <string.h> |
#else |
#ifdef HAVE_STRINGS_H |
#include <strings.h> |
#endif |
#endif |
#include <sys/stat.h> |
#include <sys/times.h> |
#include <sys/time.h> |
|
|
|
#define REG0(X) ((X) & 0x3) |
#define REG1(X) (((X) & 0xc) >> 2) |
#define REG0_4(X) (((X) & 0x30) >> 4) |
#define REG0_8(X) (((X) & 0x300) >> 8) |
#define REG1_8(X) (((X) & 0xc00) >> 10) |
#define REG0_16(X) (((X) & 0x30000) >> 16) |
#define REG1_16(X) (((X) & 0xc0000) >> 18) |
|
|
INLINE_SIM_MAIN (void) |
genericAdd(unsigned32 source, unsigned32 destReg) |
{ |
int z, c, n, v; |
unsigned32 dest, sum; |
|
dest = State.regs[destReg]; |
sum = source + dest; |
State.regs[destReg] = sum; |
|
z = (sum == 0); |
n = (sum & 0x80000000); |
c = (sum < source) || (sum < dest); |
v = ((dest & 0x80000000) == (source & 0x80000000) |
&& (dest & 0x80000000) != (sum & 0x80000000)); |
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) |
| (c ? PSW_C : 0) | (v ? PSW_V : 0)); |
} |
|
|
|
|
INLINE_SIM_MAIN (void) |
genericSub(unsigned32 source, unsigned32 destReg) |
{ |
int z, c, n, v; |
unsigned32 dest, difference; |
|
dest = State.regs[destReg]; |
difference = dest - source; |
State.regs[destReg] = difference; |
|
z = (difference == 0); |
n = (difference & 0x80000000); |
c = (source > dest); |
v = ((dest & 0x80000000) != (source & 0x80000000) |
&& (dest & 0x80000000) != (difference & 0x80000000)); |
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) |
| (c ? PSW_C : 0) | (v ? PSW_V : 0)); |
} |
|
INLINE_SIM_MAIN (void) |
genericCmp(unsigned32 leftOpnd, unsigned32 rightOpnd) |
{ |
int z, c, n, v; |
unsigned32 value; |
|
value = rightOpnd - leftOpnd; |
|
z = (value == 0); |
n = (value & 0x80000000); |
c = (leftOpnd > rightOpnd); |
v = ((rightOpnd & 0x80000000) != (leftOpnd & 0x80000000) |
&& (rightOpnd & 0x80000000) != (value & 0x80000000)); |
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) |
| (c ? PSW_C : 0) | (v ? PSW_V : 0)); |
} |
|
|
INLINE_SIM_MAIN (void) |
genericOr(unsigned32 source, unsigned32 destReg) |
{ |
int n, z; |
|
State.regs[destReg] |= source; |
z = (State.regs[destReg] == 0); |
n = (State.regs[destReg] & 0x80000000) != 0; |
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
} |
|
|
INLINE_SIM_MAIN (void) |
genericXor(unsigned32 source, unsigned32 destReg) |
{ |
int n, z; |
|
State.regs[destReg] ^= source; |
z = (State.regs[destReg] == 0); |
n = (State.regs[destReg] & 0x80000000) != 0; |
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); |
} |
|
|
INLINE_SIM_MAIN (void) |
genericBtst(unsigned32 leftOpnd, unsigned32 rightOpnd) |
{ |
unsigned32 temp; |
int z, n; |
|
temp = rightOpnd; |
temp &= leftOpnd; |
n = (temp & 0x80000000) != 0; |
z = (temp == 0); |
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); |
PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); |
} |
|
/* Read/write functions for system call interface. */ |
INLINE_SIM_MAIN (int) |
syscall_read_mem (host_callback *cb, struct cb_syscall *sc, |
unsigned long taddr, char *buf, int bytes) |
{ |
SIM_DESC sd = (SIM_DESC) sc->p1; |
sim_cpu *cpu = STATE_CPU(sd, 0); |
|
return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes); |
} |
|
INLINE_SIM_MAIN (int) |
syscall_write_mem (host_callback *cb, struct cb_syscall *sc, |
unsigned long taddr, const char *buf, int bytes) |
{ |
SIM_DESC sd = (SIM_DESC) sc->p1; |
sim_cpu *cpu = STATE_CPU(sd, 0); |
|
return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); |
} |
|
|
/* syscall */ |
INLINE_SIM_MAIN (void) |
do_syscall (void) |
{ |
|
/* We use this for simulated system calls; we may need to change |
it to a reserved instruction if we conflict with uses at |
Matsushita. */ |
int save_errno = errno; |
errno = 0; |
|
/* Registers passed to trap 0 */ |
|
/* Function number. */ |
#define FUNC (State.regs[0]) |
|
/* Parameters. */ |
#define PARM1 (State.regs[1]) |
#define PARM2 (load_word (State.regs[REG_SP] + 12)) |
#define PARM3 (load_word (State.regs[REG_SP] + 16)) |
|
/* Registers set by trap 0 */ |
|
#define RETVAL State.regs[0] /* return value */ |
#define RETERR State.regs[1] /* return error code */ |
|
/* Turn a pointer in a register into a pointer into real memory. */ |
#define MEMPTR(x) (State.mem + x) |
|
if ( FUNC == TARGET_SYS_exit ) |
{ |
/* EXIT - caller can look in PARM1 to work out the reason */ |
if (PARM1 == 0xdead) |
State.exception = SIGABRT; |
else |
{ |
sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, |
sim_exited, PARM1); |
State.exception = SIGQUIT; |
} |
State.exited = 1; |
} |
else |
{ |
CB_SYSCALL syscall; |
|
CB_SYSCALL_INIT (&syscall); |
syscall.arg1 = PARM1; |
syscall.arg2 = PARM2; |
syscall.arg3 = PARM3; |
syscall.func = FUNC; |
syscall.p1 = (PTR) simulator; |
syscall.read_mem = syscall_read_mem; |
syscall.write_mem = syscall_write_mem; |
cb_syscall (STATE_CALLBACK (simulator), &syscall); |
RETERR = syscall.errcode; |
RETVAL = syscall.result; |
} |
|
|
errno = save_errno; |
} |
|
op_utils.c
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: mn10300.igen
===================================================================
--- mn10300.igen (nonexistent)
+++ mn10300.igen (revision 842)
@@ -0,0 +1,4593 @@
+// -*- C -*-
+:option:::insn-bit-size:8
+:option:::insn-specifying-widths:true
+:option:::hi-bit-nr:7
+:model:::mn10300:mn10300:
+:model:::am33:am33:
+:model:::am33_2:am33_2:
+
+// What do we do with an illegal instruction?
+:internal::::illegal:
+{
+ PC = cia;
+ program_interrupt(SD, CPU, cia, SIM_SIGILL);
+}
+
+// 1000 DnDn imm8....; mov imm8,Dn (imm8 is sign extended)
+4.0x8,2.DM1,2.DN0=DM1+8.IMM8:S0i:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_8000 (); */
+ signed32 immed = EXTEND8 (IMM8);
+ State.regs[REG_D0+DN0] = immed;
+ PC = cia;
+}
+
+// 1000 DmDn; mov Dm,Dn (Dm != Dn, see above when Dm == Dn)
+4.0x8,2.DM1,2.DN0!DM1:S0:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ PC = cia;
+ /* OP_80 (); */
+ State.regs[REG_D0+DN0] = State.regs[REG_D0+DM1];
+}
+
+
+// 1111 0001 1110 DmAn; mov Dm,An
+8.0xf1+1110,2.DM1,2.AN0:D0:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_F1E0 (); */
+ PC = cia;
+ State.regs[REG_A0 + AN0] = State.regs[REG_D0 + DM1];
+}
+
+
+// 1111 0001 1101 AmDn; mov Am,Dn
+8.0xf1+1101,2.AM1,2.DN0:D0a:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_F1D0 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0] = State.regs[REG_A0 + AM1];
+}
+
+
+// 1001 AnAn imm8....; mov imm8,An (imm8 is zero-extended)
+4.0x9,2.AM1,2.AN0=AM1+8.IMM8:S0ai:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ PC = cia;
+ /* OP_9000 (); */
+ State.regs[REG_A0+AN0] = IMM8;
+}
+
+
+// 1001 AmAn; mov Am,An (Am != An, save above when Am == An)
+4.0x9,2.AM1,2.AN0!AM1:S0a:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ PC = cia;
+ /* OP_90 (); */
+ State.regs[REG_A0+AN0] = State.regs[REG_A0+AM1];
+}
+
+
+// 0011 11An; mov SP,An
+4.0x3,11,2.AN0:S0b:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_3C (); */
+ PC = cia;
+ State.regs[REG_A0 + AN0] = State.regs[REG_SP];
+}
+
+
+// 1111 0010 1111 Am00; mov Am,SP
+8.0xf2+4.0xf,2.AM1,00:D0b:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_F2F0 (); */
+ PC = cia;
+ State.regs[REG_SP] = State.regs[REG_A0 + AM1];
+}
+
+
+// 1111 0010 1110 01Dn; mov PSW,Dn
+8.0xf2+4.0xe,01,2.DN0:D0c:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_F2E4 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0] = PSW;
+}
+
+
+// 1111 0010 1111 Dm11; mov Dm,PSW
+8.0xf2+4.0xf,2.DM1,11:D0d:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_F2F3 (); */
+ PC = cia;
+ PSW = State.regs[REG_D0 + DM1];
+}
+
+
+// 1111 0010 1110 00Dn; mov MDR,Dn
+8.0xf2+4.0xe,00,2.DN0:D0e:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_F2E0 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0] = State.regs[REG_MDR];
+}
+
+
+// 1111 0010 1111 Dm10; mov Dm,MDR
+8.0xf2+4.0xf,2.DM1,10:D0f:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_F2F2 (); */
+ PC = cia;
+ State.regs[REG_MDR] = State.regs[REG_D0 + DM1];
+}
+
+
+// 0111 DnAm; mov (Am),Dn
+4.0x7,2.DN1,2.AM0:S0c:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_70 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN1] = load_word (State.regs[REG_A0 + AM0]);
+}
+
+
+// 1111 1000 0000 DnAm d8......; mov (d8,Am),Dn (d8 is sign-extended)
+8.0xf8+4.0x0,2.DN1,2.AM0+8.D8:D1:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_F80000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN1]
+ = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
+}
+
+
+// 1111 1010 0000 DnAm d16.....; mov (d16,Am),Dn (d16 is sign-extended.)
+8.0xfa+4.0x0,2.DN1,2.AM0+8.D16A+8.D16B:D2:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_FA000000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN1]
+ = load_word ((State.regs[REG_A0 + AM0] + EXTEND16 (FETCH16(D16A, D16B))));
+}
+
+
+// 1111 1100 0000 DnAm d32.....; mov (d32,Am),Dn
+8.0xfc+4.0x0,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_FC000000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN1]
+ = load_word ((State.regs[REG_A0 + AM0]
+ + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
+}
+
+
+// 0101 10Dn d8......; mov (d8,SP),Dn (d8 is zero-extended)
+4.0x5,10,2.DN0+8.D8:S1:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_5800 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0] = load_word (State.regs[REG_SP] + D8);
+}
+
+
+// 1111 1010 1011 01Dn d16.....; mov (d16,SP),Dn (d16 is zero-extended.)
+8.0xfa+4.0xb,01,2.DN0+8.IMM16A+8.IMM16B:D2a:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_FAB40000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0]
+ = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
+}
+
+
+// 1111 1010 1011 01Dn d32.....; mov (d32,SP),Dn
+8.0xfc+4.0xb,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_FCB40000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0]
+ = load_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+
+// 1111 0011 00Dn DiAm; mov (Di,Am),Dn
+8.0xf3+00,2.DN2,2.DI,2.AM0:D0g:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_F300 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN2]
+ = load_word ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
+}
+
+
+// 0011 00Dn abs16...; mov (abs16),Dn (abs16 is zero-extended)
+4.0x3,00,2.DN0+8.IMM16A+8.IMM16B:S2:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_300000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0] = load_word (FETCH16(IMM16A, IMM16B));
+}
+
+// 1111 1100 1010 01Dn abs32...; mov (abs32),Dn
+8.0xfc+4.0xa,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_FCA40000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0] = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+
+// 1111 0000 0000 AnAm; mov (Am),An
+8.0xf0+4.0x0,2.AN1,2.AM0:D0h:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_F000 (); */
+ PC = cia;
+ State.regs[REG_A0 + AN1] = load_word (State.regs[REG_A0 + AM0]);
+}
+
+
+// 1111 1000 0010 AnAm d8......; mov (d8,Am),An (d8 is sign-extended)
+8.0xf8+4.0x2,2.AN1,2.AM0+8.D8:D1a:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_F82000 (); */
+ PC = cia;
+ State.regs[REG_A0 + AN1]
+ = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
+}
+
+
+// 1111 1010 0010 AnAm d16.....; mov (d16,Am),An (d16 is sign-extended.)
+8.0xfa+4.0x2,2.AN1,2.AM0+8.D16A+8.D16B:D2b:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_FA200000 (); */
+ PC = cia;
+ State.regs[REG_A0 + AN1]
+ = load_word ((State.regs[REG_A0 + AM0]
+ + EXTEND16 (FETCH16(D16A, D16B))));
+}
+
+
+// 1111 1100 0010 AnAm d32.....; mov (d32,Am),An
+8.0xfc+4.0x2,2.AN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_FC200000 (); */
+ PC = cia;
+ State.regs[REG_A0 + AN1]
+ = load_word ((State.regs[REG_A0 + AM0]
+ + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
+}
+
+
+// 0101 11An d8......; mov (d8,SP),An (d8 is zero-extended)
+4.0x5,11,2.AN0+8.D8:S1a:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_5C00 (); */
+ PC = cia;
+ State.regs[REG_A0 + AN0]
+ = load_word (State.regs[REG_SP] + D8);
+}
+
+
+// 1111 1010 1011 00An d16.....; mov (d16,SP),An (d16 is zero-extended.)
+8.0xfa+4.0xb,00,2.AN0+8.IMM16A+8.IMM16B:D2c:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_FAB00000 (); */
+ PC = cia;
+ State.regs[REG_A0 + AN0]
+ = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
+}
+
+
+// 1111 1100 1011 00An d32.....; mov (d32,SP),An
+8.0xfc+4.0xb,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_FCB00000 (); */
+ PC = cia;
+ State.regs[REG_A0 + AN0]
+ = load_word (State.regs[REG_SP]
+ + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+
+// 1111 0011 10An DiAm; mov (Di,Am),An
+8.0xf3+10,2.AN2,2.DI,2.AM0:D0i:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_F380 (); */
+ PC = cia;
+ State.regs[REG_A0 + AN2]
+ = load_word ((State.regs[REG_A0 + AM0]
+ + State.regs[REG_D0 + DI]));
+}
+
+
+// 1111 1010 1010 00An abs16...; mov (abs16),An (abs16 is zero-extended)
+8.0xfa+4.0xa,00,2.AN0+8.IMM16A+8.IMM16B:D2d:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_FAA00000 (); */
+ PC = cia;
+ State.regs[REG_A0 + AN0] = load_word (FETCH16(IMM16A, IMM16B));
+}
+
+
+// 1111 1100 1010 00An abs32...; mov (abs32),An
+8.0xfc+4.0xa,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_FCA00000 (); */
+ PC = cia;
+ State.regs[REG_A0 + AN0]
+ = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+
+// 1111 1000 1111 00Am d8......; mov (d8,Am),SP (d8 is sign-extended)
+8.0xf8+4.0xf,00,2.AM0+8.D8:D1b:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_F8F000 (); */
+ PC = cia;
+ State.regs[REG_SP]
+ = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
+}
+
+
+// 0110 DmAn; mov Dm,(An)
+4.0x6,2.DM1,2.AN0:S0d:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_60 (); */
+ PC = cia;
+ store_word (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1000 0001 DmAn d8......; mov Dm,(d8,An) (d8 is sign-extended)
+8.0xf8+4.0x1,2.DM1,2.AN0+8.D8:D1c:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_F81000 (); */
+ PC = cia;
+ store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1010 0001 DmAn d16.....; mov Dm,(d16,An) (d16 is sign-extended.)
+8.0xfa+4.0x1,2.DM1,2.AN0+8.D16A+8.D16B:D2e:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_FA100000 (); */
+ PC = cia;
+ store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1100 0001 DmAn d32.....; mov Dm,(d32,An)
+8.0xfc+4.0x1,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4f:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_FC100000 (); */
+ PC = cia;
+ store_word ((State.regs[REG_A0 + AN0]
+ + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 0100 Dm10 d8......; mov Dm,(d8,SP) (d8 is zero-extended)
+4.0x4,2.DM1,10+8.D8:S1b:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_4200 (); */
+ PC = cia;
+ store_word (State.regs[REG_SP] + D8, State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1010 1001 Dm01 d16.....; mov Dm,(d16,SP) (d16 is zero-extended.)
+8.0xfa+4.0x9,2.DM1,01+8.IMM16A+8.IMM16B:D2f:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_FA910000 (); */
+ PC = cia;
+ store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1100 1001 Dm01 d32.....; mov Dm,(d32,SP)
+8.0xfc+4.0x9,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4g:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_FC910000 (); */
+ PC = cia;
+ store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 0011 01Dm DiAn; mov Dm,(Di,An)
+8.0xf3+01,2.DM2,2.DI,2.AN0:D0j:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_F340 (); */
+ PC = cia;
+ store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
+ State.regs[REG_D0 + DM2]);
+}
+
+
+// 0000 Dm01 abs16..., mov Dm,(abs16) (abs16 is zero-extended).
+4.0x0,2.DM1,01+8.IMM16A+8.IMM16B:S2a:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_10000 (); */
+ PC = cia;
+ store_word (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1100 1000 Dm01 abs32...; mov Dm,(abs32)
+8.0xfc+4.0x8,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4h:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_FC810000 (); */
+ PC = cia;
+ store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 0000 0001 AmAn; mov Am,(An)
+8.0xf0+4.0x1,2.AM1,2.AN0:D0k:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_F010 (); */
+ PC = cia;
+ store_word (State.regs[REG_A0 + AN0], State.regs[REG_A0 + AM1]);
+}
+
+
+// 1111 1000 0011 AmAn d8......; mov Am,(d8,An) (d8 is sign-extended)
+8.0xf8+4.0x3,2.AM1,2.AN0+8.D8:D1d:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_F83000 (); */
+ PC = cia;
+ store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
+ State.regs[REG_A0 + AM1]);
+}
+
+
+// 1111 1010 0011 AmAn d16.....; mov Am,(d16,An) (d16 is sign-extended.)
+8.0xfa+4.0x3,2.AM1,2.AN0+8.D16A+8.D16B:D2g:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_FA300000 (); */
+ PC = cia;
+ store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
+ State.regs[REG_A0 + AM1]);
+}
+
+
+// 1111 1100 0011 AmAn d32.....; mov Am,(d32,An)
+8.0xfc+4.0x3,2.AM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4i:::mov
+"mov"
+*mn10300
+*am33
+*am33_2
+{
+ /* OP_FC300000 (); */
+ PC = cia;
+ store_word ((State.regs[REG_A0 + AN0]
+ + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
+ State.regs[REG_A0 + AM1]);
+}
+
+
+// 0100 Am11 d8......; mov Am,(d8,SP) (d8 is zero-extended)
+4.0x4,2.AM1,11+8.D8:S1c:::mov
+"mov"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_4300 (); */
+ PC = cia;
+ store_word (State.regs[REG_SP] + (D8), State.regs[REG_A0 + (AM1)]);
+}
+
+
+// 1111 1010 1001 Am00 d16.....; mov Am,(d16,SP) (d16 is zero-extended.)
+8.0xfa+4.0x9,2.AM1,00+8.IMM16A+8.IMM16B:D2h:::mov
+"mov"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FA900000 (); */
+ PC = cia;
+ store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
+ State.regs[REG_A0 + AM1]);
+}
+
+
+// 1111 1100 1001 Am00 d32.....; mov Am,(d32,SP)
+8.0xfc+4.0x9,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4j:::mov
+"mov"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FC900000 (); */
+ PC = cia;
+ store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[REG_A0 + AM1]);
+}
+
+
+// 1111 0011 11Am DiAn; mov Am,(Di,An)
+8.0xf3+11,2.AM2,2.DI,2.AN0:D0l:::mov
+"mov"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F3C0 (); */
+ PC = cia;
+ store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
+ State.regs[REG_A0 + AM2]);
+}
+
+
+// 1111 1010 1000 Am00 abs16...; mov Am,(abs16) (abs16 is zero-extended)
+8.0xfa+4.0x8,2.AM1,00+8.IMM16A+8.IMM16B:D2i:::mov
+"mov"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FA800000 (); */
+ PC = cia;
+ store_word (FETCH16(IMM16A, IMM16B),
+ State.regs[REG_A0 + AM1]);
+}
+
+
+// 1111 1100 1000 Am00 abs32...; mov Am,(abs32)
+8.0xfc+4.0x8,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4k:::mov
+"mov"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FC800000 (); */
+ PC = cia;
+ store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[REG_A0 + AM1]);
+}
+
+
+// 1111 1000 1111 01An d8......; mov SP,(d8,An) (d8 is sign-extended)
+8.0xf8+4.0xf,01,2.AN0+8.D8:D1e:::mov
+"mov"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F8F400 (); */
+ PC = cia;
+ store_word (State.regs[REG_A0 + AN0] + EXTEND8 (D8),
+ State.regs[REG_SP]);
+}
+
+
+// 0010 11Dn imm16...; mov imm16,Dn (imm16 is sign-extended)
+4.0x2,11,2.DN0+8.IMM16A+8.IMM16B:S2b:::mov
+"mov"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_2C0000 (); */
+ unsigned32 value;
+
+ PC = cia;
+ value = EXTEND16 (FETCH16(IMM16A, IMM16B));
+ State.regs[REG_D0 + DN0] = value;
+}
+
+
+// 1111 1100 1100 11Dn imm32...; mov imm32,Dn
+8.0xfc+4.0xc,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4l:::mov
+"mov"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FCCC0000 (); */
+ unsigned32 value;
+
+ PC = cia;
+ value = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
+ State.regs[REG_D0 + DN0] = value;
+}
+
+
+// 0010 01An imm16...; mov imm16,An (imm16 is zero-extended)
+4.0x2,01,2.AN0+8.IMM16A+8.IMM16B:S2c:::mov
+"mov"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_240000 (); */
+ unsigned32 value;
+
+ PC = cia;
+ value = FETCH16(IMM16A, IMM16B);
+ State.regs[REG_A0 + AN0] = value;
+}
+
+
+// 1111 1100 1101 11An imm32...; mov imm32,An
+8.0xfc+4.0xd,11,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4m:::mov
+"mov"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FCDC0000 (); */
+ PC = cia;
+ State.regs[REG_A0 + AN0] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+
+// 1111 0000 0100 DnAm; movbu (Am),Dn
+8.0xf0+4.0x4,2.DN1,2.AM0:D0:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F040 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN1]
+ = load_byte (State.regs[REG_A0 + AM0]);
+}
+
+
+// 1111 1000 0100 DnAm d8......; movbu (d8,Am),Dn (d8 is sign-extended)
+8.0xf8+4.0x4,2.DN1,2.AM0+8.D8:D1f:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F84000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN1]
+ = load_byte ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
+}
+
+
+// 1111 1010 0100 DnAm d16.....; movbu (d16,Am),Dn (d16 is sign-extended.)
+8.0xfa+4.0x4,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FA400000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN1]
+ = load_byte ((State.regs[REG_A0 + AM0]
+ + EXTEND16 (FETCH16(D16A, D16B))));
+}
+
+
+// 1111 1100 0100 DnAm d32.....; movbu (d32,Am),Dn
+8.0xfc+4.0x4,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FC400000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN1]
+ = load_byte ((State.regs[REG_A0 + AM0]
+ + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
+}
+
+
+// 1111 1000 1011 10Dn d8......; movbu (d8,SP),Dn (d8 is zero-extended)
+8.0xf8+4.0xb,10,2.DN0+8.D8:D1a:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F8B800 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0]
+ = load_byte ((State.regs[REG_SP] + (D8)));
+}
+
+
+// 1111 1010 1011 10Dn d16.....; movbu (d16,SP),Dn (d16 is zero-extended.)
+8.0xfa+4.0xb,10,2.DN0+8.IMM16A+8.IMM16B:D2a:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FAB80000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0]
+ = load_byte ((State.regs[REG_SP]
+ + FETCH16(IMM16A, IMM16B)));
+}
+
+
+// 1111 1100 1011 10Dn d32.....; movbu (d32,SP),Dn
+8.0xfc+4.0xb,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FCB80000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0]
+ = load_byte (State.regs[REG_SP]
+ + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+
+// 1111 0100 00Dn DiAm; movbu (Di,Am),Dn
+8.0xf4+00,2.DN2,2.DI,2.AM0:D0a:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F400 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN2]
+ = load_byte ((State.regs[REG_A0 + AM0]
+ + State.regs[REG_D0 + DI]));
+}
+
+
+// 0011 01Dn abs16...; movbu (abs16),Dn (abs16 is zero-extended)
+4.0x3,01,2.DN0+8.IMM16A+8.IMM16B:S2:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_340000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0] = load_byte (FETCH16(IMM16A, IMM16B));
+}
+
+
+// 1111 1100 1010 10Dn abs32...; movbu (abs32),Dn
+8.0xfc+4.0xa,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FCA80000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0]
+ = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+
+// 1111 0000 0101 DmAn; movbu Dm,(An)
+8.0xf0+4.0x5,2.DM1,2.AN0:D0b:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F050 (); */
+ PC = cia;
+ store_byte (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1000 0101 DmAn d8......; movbu Dm,(d8,An) (d8 is sign-extended)
+8.0xf8+4.0x5,2.DM1,2.AN0+8.D8:D1b:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F85000 (); */
+ PC = cia;
+ store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1010 0101 DmAn d16.....; movbu Dm,(d16,An) (d16 is sign-extended.)
+8.0xfa+4.0x5,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FA500000 (); */
+ PC = cia;
+ store_byte ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1100 0101 DmAn d32.....; movbu Dm,(d32,An)
+8.0xfc+4.0x5,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FC500000 (); */
+ PC = cia;
+ store_byte ((State.regs[REG_A0 + AN0]
+ + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1000 1001 Dm10 d8......; movbu Dm,(d8,SP) (d8 is zero-extended)
+8.0xf8+4.0x9,2.DM1,10+8.D8:D1c:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F89200 (); */
+ PC = cia;
+ store_byte (State.regs[REG_SP] + (D8), State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1010 1001 Dm10 d16.....; movbu Dm,(d16,SP) (d16 is zero-extended.)
+8.0xfa+4.0x9,2.DM1,10+8.IMM16A+8.IMM16B:D2c:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FA920000 (); */
+ PC = cia;
+ store_byte (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1100 1001 Dm10 d32.....; movbu Dm,(d32,SP)
+8.0xfc+4.0x9,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FC920000 (); */
+ PC = cia;
+ store_byte (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 0100 01Dm DiAn; movbu Dm,(Di,An)
+8.0xf4+01,2.DM2,2.DI,2.AN0:D0c:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F440 (); */
+ PC = cia;
+ store_byte ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
+ State.regs[REG_D0 + DM2]);
+}
+
+
+// 0000 Dm10 abs16...; movbu Dm,(abs16) (abs16 is zero-extended)
+4.0x0,2.DM1,10+8.IMM16A+8.IMM16B:S2a:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_20000 (); */
+ PC = cia;
+ store_byte (FETCH16(IMM16A, IMM16B),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1100 1000 Dm10 abs32...; movbu Dm,(abs32)
+8.0xfc+4.0x8,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movbu
+"movbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FC820000 (); */
+ PC = cia;
+ store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 0000 0110 DnAm; movhu (Am),Dn
+8.0xf0+4.0x6,2.DN1,2.AM0:D0:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F060 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN1]
+ = load_half (State.regs[REG_A0 + AM0]);
+}
+
+
+// 1111 1000 0110 DnAm d8......; movhu (d8,Am),Dn (d8 is sign-extended)
+8.0xf8+4.0x6,2.DN1,2.AM0+8.D8:D1d:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F86000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN1]
+ = load_half ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
+}
+
+
+// 1111 1010 0110 DnAm d16.....; movhu (d16,Am),Dn (d16 is sign-extended.)
+8.0xfa+4.0x6,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FA600000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN1]
+ = load_half ((State.regs[REG_A0 + AM0]
+ + EXTEND16 (FETCH16(D16A, D16B))));
+}
+
+
+// 1111 1100 0110 DnAm d32.....; movhu (d32,Am),Dn
+8.0xfc+4.0x6,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FC600000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN1]
+ = load_half ((State.regs[REG_A0 + AM0]
+ + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
+}
+
+
+// 1111 1000 1011 11Dn d8.....; movhu (d8,SP),Dn (d8 is zero-extended)
+8.0xf8+4.0xb,11,2.DN0+8.D8:D1a:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F8BC00 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0]
+ = load_half ((State.regs[REG_SP] + (D8)));
+}
+
+
+// 1111 1010 1011 11Dn d16.....; movhu (d16,SP),Dn (d16 is zero-extended.)
+8.0xfa+4.0xb,11,2.DN0+8.IMM16A+8.IMM16B:D2a:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FABC0000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0]
+ = load_half ((State.regs[REG_SP] + FETCH16(IMM16A, IMM16B)));
+}
+
+
+// 1111 1100 1011 11Dn d32.....; movhu (d32,SP),Dn
+8.0xfc+4.0xb,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FCBC0000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0]
+ = load_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+
+// 1111 0100 10Dn DiAm; movhu (Di,Am),Dn
+8.0xf4+10,2.DN2,2.DI,2.AM0:D0a:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F480 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN2]
+ = load_half ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
+}
+
+
+// 0011 10Dn abs16...; movhu (abs16),Dn (abs16 is zero-extended)
+4.0x3,10,2.DN0+8.IMM16A+8.IMM16B:S2:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_380000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0] = load_half (FETCH16(IMM16A, IMM16B));
+}
+
+
+// 1111 1100 1010 11Dn abs32...; movhu (abs32),Dn
+8.0xfc+4.0xa,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FCAC0000 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0]
+ = load_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+
+// 1111 0000 0111 DmAn; movhu Dm,(An)
+8.0xf0+4.0x7,2.DM1,2.AN0:D0b:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F070 (); */
+ PC = cia;
+ store_half (State.regs[REG_A0 + AN0],
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1000 0111 DmAn d8......; movhu Dm,(d8,An) (d8 is sign-extended)
+8.0xf8+4.0x7,2.DM1,2.AN0+8.D8:D1b:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F87000 (); */
+ PC = cia;
+ store_half ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1010 0111 DnAm d16.....; movhu Dm,(d16,An) (d16 is sign-extended.)
+8.0xfa+4.0x7,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FA700000 (); */
+ PC = cia;
+ store_half ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1100 0111 DmAn d32.....; movhu Dm,(d32,An)
+8.0xfc+4.0x7,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FC700000 (); */
+ PC = cia;
+ store_half ((State.regs[REG_A0 + AN0]
+ + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1000 1001 Dm11 d8....; movhu Dm,(d8,SP) (d8 is zero-extended)
+8.0xf8+4.0x9,2.DM1,11+8.D8:D1c:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F89300 (); */
+ PC = cia;
+ store_half (State.regs[REG_SP] + (D8),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1010 1001 Dm11 d16.....; movhu Dm,(d16,SP) (d16 is zero-extended.)
+8.0xfa+4.0x9,2.DM1,11+8.IMM16A+8.IMM16B:D2c:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FA930000 (); */
+ PC = cia;
+ store_half (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1100 1001 Dm11 d32.....; movhu Dm,(d32,SP)
+8.0xfc+4.0x9,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FC930000 (); */
+ PC = cia;
+ store_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 0100 11Dm DiAn; movhu Dm,(Di,An)
+8.0xf4+11,2.DM2,2.DI,2.AN0:D0c:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F4C0 (); */
+ PC = cia;
+ store_half ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
+ State.regs[REG_D0 + DM2]);
+}
+
+
+// 0000 Dm11 abs16...; movhu Dm,(abs16) (abs16 is zero-extended)
+4.0x0,2.DM1,11+8.IMM16A+8.IMM16B:S2a:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_30000 (); */
+ PC = cia;
+ store_half (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 1100 1000 Dm11 abs32...; movhu Dm,(abs32)
+8.0xfc+4.0x8,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movhu
+"movhu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FC830000 (); */
+ PC = cia;
+ store_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[REG_D0 + DM1]);
+}
+
+
+// 1111 0010 1101 00Dn; ext Dn
+8.0xf2+4.0xd,00,2.DN0:D0:::ext
+"ext"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F2D0 (); */
+ PC = cia;
+ if (State.regs[REG_D0 + DN0] & 0x80000000)
+ State.regs[REG_MDR] = -1;
+ else
+ State.regs[REG_MDR] = 0;
+}
+
+
+// 0001 00Dn; extb Dn
+4.0x1,00,2.DN0:S0:::extb
+"extb"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_10 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0] = EXTEND8 (State.regs[REG_D0 + DN0]);
+}
+
+
+// 0001 01Dn; extbu Dn
+4.0x1,01,2.DN0:S0:::extbu
+"extbu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_14 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0] &= 0xff;
+}
+
+
+// 0001 10Dn; exth Dn
+4.0x1,10,2.DN0:S0:::exth
+"exth"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_18 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0] = EXTEND16 (State.regs[REG_D0 + DN0]);
+}
+
+
+// 0001 11Dn; exthu Dn
+4.0x1,11,2.DN0:S0:::exthu
+"exthu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_1C (); */
+ PC = cia;
+ State.regs[REG_D0 + DN0] &= 0xffff;
+}
+
+
+// 0000 Dn00; clr Dn
+4.0x0,2.DN1,00:S0:::clr
+"clr"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_0 (); */
+ PC = cia;
+ State.regs[REG_D0 + DN1] = 0;
+
+ PSW |= PSW_Z;
+ PSW &= ~(PSW_V | PSW_C | PSW_N);
+}
+
+
+// 1110 DmDn; add Dm,Dn
+4.0xe,2.DM1,2.DN0:S0:::add
+"add"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_E0 (); */
+ PC = cia;
+ genericAdd(State.regs[REG_D0 + DM1], REG_D0 + DN0);
+}
+
+// 1111 0001 0110 DmAn; add Dm,An
+8.0xf1+4.0x6,2.DM1,2.AN0:D0:::add
+"add"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F160 (); */
+ PC = cia;
+ genericAdd(State.regs[REG_D0 + DM1], REG_A0 + AN0);
+}
+
+
+// 1111 0001 0101 AmDn; add Am,Dn
+8.0xf1+4.0x5,2.AM1,2.DN0:D0a:::add
+"add"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F150 (); */
+ PC = cia;
+ genericAdd(State.regs[REG_A0 + AM1], REG_D0 + DN0);
+}
+
+
+// 1111 0001 0111 AmAn; add Am,An
+8.0xf1+4.0x7,2.AM1,2.AN0:D0b:::add
+"add"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F170 (); */
+ PC = cia;
+ genericAdd(State.regs[REG_A0 + AM1], REG_A0 + AN0);
+}
+
+
+// 0010 10Dn imm8....; add imm8,Dn (imm8 is sign-extended)
+4.0x2,10,2.DN0+8.IMM8:S1:::add
+"add"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_2800 (); */
+ PC = cia;
+ genericAdd(EXTEND8(IMM8), REG_D0 + DN0);
+}
+
+
+// 1111 1010 1100 00Dn imm16...; add imm16,Dn
+8.0xfa+4.0xc,00,2.DN0+8.IMM16A+8.IMM16B:D2:::add
+"add"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FAC00000 (); */
+ PC = cia;
+ genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_D0 + DN0);
+}
+
+
+// 1111 1100 1100 00Dn imm32...; add imm32,Dn
+8.0xfc+4.0xc,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::add
+"add"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FCC00000 (); */
+ PC = cia;
+ genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
+}
+
+
+// 0010 00An imm8....; add imm8,An (imm8 is sign-extended)
+4.0x2,00,2.AN0+8.IMM8:S1a:::add
+"add"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_2000 (); */
+ PC = cia;
+ genericAdd(EXTEND8(IMM8), REG_A0 + AN0);
+}
+
+
+// 1111 1010 1101 00An imm16...; add imm16,An (imm16 is sign-extended.)
+8.0xfa+4.0xd,00,2.AN0+8.IMM16A+8.IMM16B:D2a:::add
+"add"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FAD00000 (); */
+ PC = cia;
+ genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_A0 + AN0);
+}
+
+
+// 1111 1100 1101 00An imm32...; add imm32,An
+8.0xfc+4.0xd,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::add
+"add"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FCD00000 (); */
+ PC = cia;
+ genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
+}
+
+
+// 1111 1000 1111 1110 imm8....; add imm8,SP (imm8 is sign-extended.)
+8.0xf8+8.0xfe+8.IMM8:D1:::add
+"add"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F8FE00 (); */
+ unsigned32 imm;
+
+ /* Note: no PSW changes. */
+ PC = cia;
+ imm = EXTEND8 (IMM8);
+ State.regs[REG_SP] += imm;
+}
+
+
+// 1111 1010 1111 1110 imm16...; add imm16,SP (imm16 is sign-extended.)
+8.0xfa+8.0xfe+8.IMM16A+8.IMM16B:D2b:::add
+"add"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FAFE0000 (); */
+ unsigned32 imm;
+
+ /* Note: no PSW changes. */
+ PC = cia;
+ imm = EXTEND16 (FETCH16(IMM16A, IMM16B));
+ State.regs[REG_SP] += imm;
+}
+
+
+// 1111 1100 1111 1110 imm32...; add imm32,SP
+8.0xfc+8.0xfe+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::add
+"add"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FCFE0000 (); */
+ unsigned32 imm;
+
+ /* Note: no PSW changes. */
+ PC = cia;
+ imm = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
+ State.regs[REG_SP] += imm;
+}
+
+
+// 1111 0001 0100 DmDn; addc Dm,Dn
+8.0xf1+4.0x4,2.DM1,2.DN0:D0:::addc
+"addc"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F140 (); */
+ int z, c, n, v;
+ unsigned32 reg1, reg2, sum;
+
+ PC = cia;
+ reg1 = State.regs[REG_D0 + DM1];
+ reg2 = State.regs[REG_D0 + DN0];
+ sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
+ State.regs[REG_D0 + DN0] = sum;
+
+ z = ((PSW & PSW_Z) != 0) && (sum == 0);
+ n = (sum & 0x80000000);
+ c = (sum < reg1) || (sum < reg2);
+ v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
+ && (reg2 & 0x80000000) != (sum & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+
+// 1111 0001 0000 DmDn; sub Dm,Dn
+8.0xf1+4.0x0,2.DM1,2.DN0:D0:::sub
+"sub"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F100 (); */
+ PC = cia;
+ genericSub(State.regs[REG_D0 + DM1], REG_D0 + DN0);
+}
+
+// 1111 0001 0010 DmAn; sub DmAn
+8.0xf1+4.0x2,2.DM1,2.AN0:D0a:::sub
+"sub"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F120 (); */
+ PC = cia;
+ genericSub(State.regs[REG_D0 + DM1], REG_A0 + AN0);
+}
+
+
+// 1111 0001 0001 AmDn; sub AmDn
+8.0xf1+4.0x1,2.AM1,2.DN0:D0b:::sub
+"sub"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F110 (); */
+ PC = cia;
+ genericSub(State.regs[REG_A0 + AM1], REG_D0 + DN0);
+}
+
+
+// 1111 0001 0011 AmAn; sub Am,An
+8.0xf1+4.0x3,2.AM1,2.AN0:D0c:::sub
+"sub"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F130 (); */
+ PC = cia;
+ genericSub(State.regs[REG_A0 + AM1], REG_A0 + AN0);
+}
+
+
+// 1111 1100 1100 01Dn imm32...; sub imm32,Dn
+8.0xfc+4.0xc,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::sub
+"sub"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FCC40000 (); */
+ PC = cia;
+ genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
+}
+
+
+// 1111 1100 1101 01An imm32...; sub imm32,An
+8.0xfc+4.0xd,01,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::sub
+"sub"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FCD40000 (); */
+ PC = cia;
+ genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
+}
+
+
+// 1111 0001 1000 DmDn; subc Dm,Dn
+8.0xf1+4.0x8,2.DM1,2.DN0:D0:::subc
+"subc"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F180 (); */
+ int z, c, n, v;
+ unsigned32 reg1, reg2, difference;
+
+ PC = cia;
+ reg1 = State.regs[REG_D0 + DM1];
+ reg2 = State.regs[REG_D0 + DN0];
+ difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
+ State.regs[REG_D0 + DN0] = difference;
+
+ z = ((PSW & PSW_Z) != 0) && (difference == 0);
+ n = (difference & 0x80000000);
+ c = (reg1 > reg2);
+ v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
+ && (reg2 & 0x80000000) != (difference & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+
+// 1111 0010 0100 DmDn; mul Dm,Dn
+8.0xf2+4.0x4,2.DM1,2.DN0:D0:::mul
+"mul"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F240 (); */
+ unsigned64 temp;
+ int n, z;
+
+ PC = cia;
+ temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
+ * (signed64)(signed32)State.regs[REG_D0 + DM1]);
+ State.regs[REG_D0 + DN0] = temp & 0xffffffff;
+ State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 1111 0010 0101 DmDn; mulu Dm,Dn
+8.0xf2+4.0x5,2.DM1,2.DN0:D0:::mulu
+"mulu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F250 (); */
+ unsigned64 temp;
+ int n, z;
+
+ PC = cia;
+ temp = ((unsigned64)State.regs[REG_D0 + DN0]
+ * (unsigned64)State.regs[REG_D0 + DM1]);
+ State.regs[REG_D0 + DN0] = temp & 0xffffffff;
+ State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 1111 0010 0110 DmDn; div Dm,Dn
+8.0xf2+4.0x6,2.DM1,2.DN0:D0:::div
+"div"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F260 (); */
+ signed64 temp;
+ signed32 denom;
+ int n, z, v;
+
+ PC = cia;
+ denom = (signed32)State.regs[REG_D0 + DM1];
+
+ temp = State.regs[REG_MDR];
+ temp <<= 32;
+ temp |= State.regs[REG_D0 + DN0];
+ if ( !(v = (0 == denom)) )
+ {
+ State.regs[REG_MDR] = temp % (signed32)State.regs[REG_D0 + DM1];
+ temp /= (signed32)State.regs[REG_D0 + DM1];
+ State.regs[REG_D0 + DN0] = temp & 0xffffffff;
+ }
+ else
+ {
+ State.regs[REG_MDR] = temp;
+ State.regs[REG_D0 + DN0] = 0xff;
+ }
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
+}
+
+
+// 1111 0010 0111 DmDn; divu Dm,Dn
+8.0xf2+4.0x7,2.DM1,2.DN0:D0:::divu
+"divu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F270 (); */
+ unsigned64 temp;
+ unsigned32 denom;
+ int n, z, v;
+
+ PC = cia;
+ denom = (unsigned32)State.regs[REG_D0 + DM1];
+ temp = State.regs[REG_MDR];
+ temp <<= 32;
+ temp |= State.regs[REG_D0 + DN0];
+ if ( !(v = (0 == denom)) )
+ {
+ State.regs[REG_MDR] = temp % State.regs[REG_D0 + DM1];
+ temp /= State.regs[REG_D0 + DM1];
+ State.regs[REG_D0 + DN0] = temp & 0xffffffff;
+ }
+ else
+ {
+ State.regs[REG_MDR] = temp;
+ State.regs[REG_D0 + DN0] = 0xff;
+ }
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
+}
+
+
+// 0100 Dn00; inc Dn
+4.0x4,2.DN1,00:S0:::inc
+"inc"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_40 (); */
+ unsigned32 imm;
+
+ PC = cia;
+ imm = 1;
+ genericAdd(imm, REG_D0 + DN1);
+}
+
+
+// 0100 An01
+4.0x4,2.AN1,01:S0a:::inc
+"inc"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_41 (); */
+ PC = cia;
+ State.regs[REG_A0 + AN1] += 1;
+}
+
+
+// 0101 00An; inc4 An
+4.0x5,00,2.AN0:S0:::inc4
+"inc4"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_50 (); */
+ PC = cia;
+ State.regs[REG_A0 + AN0] += 4;
+}
+
+
+// 1010 DnDn imm8....; cmp imm8,Dn (imm8 is sign-extended.)
+4.0xa,2.DM1,2.DN0=DM1+IMM8:S0i:::cmp
+"cmp"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ PC = cia;
+ /* OP_A000 (); */
+ genericCmp(EXTEND8 (IMM8), State.regs[REG_D0 + DN0]);
+}
+
+
+// 1010 DmDn; cmp Dm,Dn (Dm != Dn, see above when Dm == Dn)
+4.0xa,2.DM1,2.DN0!DM1:S0:::cmp
+"cmp"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ PC = cia;
+ /* OP_A0 (); */
+ genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_D0 + DN0]);
+}
+
+
+// 1111 0001 1010 DmAn; cmp Dm,An
+8.0xf1+4.0xa,2.DM1,2.AN0:D0:::cmp
+"cmp"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F1A0 (); */
+ PC = cia;
+ genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_A0 + AN0]);
+}
+
+
+// 1111 0001 1001 AmDn; cmp Am,Dn
+8.0xf1+4.0x9,2.AM1,2.DN0:D0a:::cmp
+"cmp"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F190 (); */
+ PC = cia;
+ genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_D0 + DN0]);
+}
+
+
+// 1011 AnAn imm8....; cmp imm8,An (imm8 is zero-extended.)
+4.0xb,2.AM1,2.AN0=AM1+IMM8:S0ai:::cmp
+"cmp"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ PC = cia;
+ /* OP_B000 (); */
+ genericCmp(IMM8,
+ State.regs[REG_A0 + AN0]);
+}
+
+
+// 1011 AmAn; cmp Am,An (Dm != Dn, see above when Dm == Dn)
+4.0xb,2.AM1,2.AN0!AM1:S0a:::cmp
+"cmp"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ PC = cia;
+ /* OP_B0 (); */
+ genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_A0 + AN0]);
+}
+
+
+// 1111 1010 1100 10Dn imm16...; cmp imm16,Dn (imm16 is sign-extended.)
+8.0xfa+4.0xc,10,2.DN0+8.IMM16A+8.IMM16B:D2:::cmp
+"cmp"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FAC80000 (); */
+ PC = cia;
+ genericCmp(EXTEND16(FETCH16(IMM16A, IMM16B)),
+ State.regs[REG_D0 + DN0]);
+}
+
+
+// 1111 1100 1100 10Dn imm32...; cmp imm32,Dn
+8.0xfc+4.0xc,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::cmp
+"cmp"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FCC80000 (); */
+ PC = cia;
+ genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[REG_D0 + DN0]);
+}
+
+
+// 1111 1010 1101 10An imm16...; cmp imm16,An (imm16 is zero-extended.)
+8.0xfa+4.0xd,10,2.AN0+8.IMM16A+8.IMM16B:D2a:::cmp
+"cmp"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FAD80000 (); */
+ PC = cia;
+ genericCmp(FETCH16(IMM16A, IMM16B),
+ State.regs[REG_A0 + AN0]);
+}
+
+
+// 1111 1100 1101 10An imm32...; cmp imm32,An
+8.0xfc+4.0xd,10,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::cmp
+"cmp"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FCD80000 (); */
+ PC = cia;
+ genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[REG_A0 + AN0]);
+}
+
+
+// 1111 0010 0000 DmDn; and Dm,Dn
+8.0xf2+4.0x0,2.DM1,2.DN0:D0:::and
+"and"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F200 (); */
+ int n, z;
+
+ PC = cia;
+ State.regs[REG_D0 + DN0] &= State.regs[REG_D0 + DM1];
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 1111 1000 1110 00Dn imm8....; and imm8,Dn (imm8 is zero-extended.)
+8.0xf8+4.0xe,00,2.DN0+8.IMM8:D1:::and
+"and"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F8E000 (); */
+ int n, z;
+
+ PC = cia;
+ State.regs[REG_D0 + DN0] &= IMM8;
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 1111 1010 1110 00Dn imm16...; and imm16,Dn (imm16 is zero-extended.)
+8.0xfa+4.0xe,00,2.DN0+8.IMM16A+8.IMM16B:D2:::and
+"and"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FAE00000 (); */
+ int n, z;
+
+ PC = cia;
+ State.regs[REG_D0 + DN0] &= FETCH16(IMM16A, IMM16B);
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 1111 1100 1110 00Dn imm32...; and imm32,Dn
+8.0xfc+4.0xe,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::and
+"and"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FCE00000 (); */
+ int n, z;
+
+ PC = cia;
+ State.regs[REG_D0 + DN0]
+ &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 1111 1010 1111 1100 imm16...; and imm16,PSW (imm16 is zero-extended.)
+8.0xfa+8.0xfc+8.IMM16A+8.IMM16B:D2a:::and
+"and"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FAFC0000 (); */
+ PC = cia;
+ PSW &= FETCH16(IMM16A, IMM16B);
+}
+
+
+
+// 1111 0010 0001 DmDn; or DmDn
+8.0xf2+4.0x1,2.DM1,2.DN0:D0:::or
+"or"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F210 (); */
+ PC = cia;
+ genericOr(State.regs[REG_D0 + DM1], REG_D0 + DN0);
+}
+
+
+// 1111 1000 1110 01Dn imm8....; or imm8,Dn (imm8 is zero-extended.)n
+8.0xf8+4.0xe,01,2.DN0+8.IMM8:D1:::or
+"or"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F8E400 (); */
+ PC = cia;
+ genericOr(IMM8, REG_D0 + DN0);
+}
+
+
+// 1111 1010 1110 01Dn imm16...; or imm16,DN (imm16 is zero-extended.)
+8.0xfa+4.0xe,01,2.DN0+8.IMM16A+8.IMM16B:D2:::or
+"or"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FAE40000 (); */
+ PC = cia;
+ genericOr(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
+}
+
+
+// 1111 1100 1110 01Dn imm32...; or imm32,Dn
+8.0xfc+4.0xe,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::or
+"or"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FCE40000 (); */
+ PC = cia;
+ genericOr(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
+}
+
+
+// 1111 1010 1111 1101 imm16...; or imm16,PSW (imm16 is zero-extended.)
+8.0xfa+8.0xfd+8.IMM16A+8.IMM16B:D2a:::or
+"or"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FAFD0000 (); */
+ PC = cia;
+ PSW |= FETCH16(IMM16A, IMM16B);
+}
+
+
+// 1111 0010 0010 DmDn; xor Dm,Dn
+8.0xf2+4.0x2,2.DM1,2.DN0:D0:::xor
+"xor"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F220 (); */
+ PC = cia;
+ genericXor(State.regs[REG_D0 + DM1], REG_D0 + DN0);
+}
+
+
+// 1111 1010 1110 10Dn imm16...; xor imm16,Dn (imm16 is zero-extended.)
+8.0xfa+4.0xe,10,2.DN0+8.IMM16A+8.IMM16B:D2:::xor
+"xor"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FAE80000 (); */
+ PC = cia;
+ genericXor(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
+}
+
+
+// 1111 1100 1110 10Dn imm32...; xor imm32,Dn
+8.0xfc+4.0xe,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::xor
+"xor"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FCE80000 (); */
+ PC = cia;
+ genericXor(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
+}
+
+
+// 1111 0010 0011 00Dn; not Dn
+8.0xf2+4.0x3,00,2.DN0:D0:::not
+"not"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F230 (); */
+ int n, z;
+
+ PC = cia;
+ State.regs[REG_D0 + DN0] = ~State.regs[REG_D0 + DN0];
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 1111 1000 1110 11Dn imm8....; btst imm8,Dn (imm8 is zero-extended.)
+8.0xf8+4.0xe,11,2.DN0+8.IMM8:D1:::btst
+"btst"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F8EC00 (); */
+ PC = cia;
+ genericBtst(IMM8, State.regs[REG_D0 + DN0]);
+}
+
+
+// 1111 1010 1110 11Dn imm16.....; btst imm16,Dn (imm16 is zero-extended.)
+8.0xfa+4.0xe,11,2.DN0+8.IMM16A+8.IMM16B:D2:::btst
+"btst"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FAEC0000 (); */
+ PC = cia;
+ genericBtst(FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DN0]);
+}
+
+
+// 1111 1100 1110 11Dn imm32...; btst imm32,Dn
+8.0xfc+4.0xe,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::btst
+"btst"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FCEC0000 (); */
+ PC = cia;
+ genericBtst(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[REG_D0 + DN0]);
+}
+
+
+// 1111 1110 0000 0010 abs32... imm8....; btst imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
+8.0xfe+8.0x02+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::btst
+"btst"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FE020000 (); */
+ PC = cia;
+ genericBtst(IMM8,
+ load_byte(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
+}
+
+
+// 1111 1010 1111 10An d8...... imm8....;
+// btst imm8,(d8,An) (d8 is sign-extended,imm8 is zero-extended., processing unit: byte)
+8.0xfa+4.0xf,10,2.AN0+8.D8+8.IMM8:D2a:::btst
+"btst"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FAF80000 (); */
+ PC = cia;
+ genericBtst(IMM8,
+ load_byte(State.regs[REG_A0 + AN0] + EXTEND8(D8)));
+}
+
+
+// 1111 0000 1000 DmAn; bset Dm,(An) (Processing unit byte)
+8.0xf0+4.8,2.DM1,2.AN0:D0:::bset
+"bset"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F080 (); */
+ unsigned32 temp;
+ int z;
+
+ PC = cia;
+ temp = load_byte (State.regs[REG_A0 + AN0]);
+ z = (temp & State.regs[REG_D0 + DM1]) == 0;
+ temp |= State.regs[REG_D0 + DM1];
+ store_byte (State.regs[REG_A0 + AN0], temp);
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= (z ? PSW_Z : 0);
+}
+
+
+// 1111 1110 0000 0000 abs32... imm8....;
+// bset imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
+8.0xfe+8.0x00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bset
+"bset"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FE000000 (); */
+ unsigned32 temp;
+ int z;
+
+ PC = cia;
+ temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
+ z = (temp & IMM8) == 0;
+ temp |= IMM8;
+ store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= (z ? PSW_Z : 0);
+}
+
+
+// 1111 1010 1111 00AnAn d8...... imm8....;
+// bset imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
+8.0xfa+4.0xf,00,2.AN0+8.D8+8.IMM8:D2:::bset
+"bset"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FAF00000 (); */
+ unsigned32 temp;
+ int z;
+
+ PC = cia;
+ temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
+ z = (temp & (IMM8)) == 0;
+ temp |= (IMM8);
+ store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= (z ? PSW_Z : 0);
+}
+
+
+// 1111 0000 1001 DmAn; bclr Dm,(An) (Processing unit byte)
+8.0xf0+4.0x9,2.DM1,2.AN0:D0:::bclr
+"bclr"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F090 (); */
+ unsigned32 temp;
+ int z;
+
+ PC = cia;
+ temp = load_byte (State.regs[REG_A0 + AN0]);
+ z = (temp & State.regs[REG_D0 + DM1]) == 0;
+ temp = temp & ~State.regs[REG_D0 + DM1];
+ store_byte (State.regs[REG_A0 + AN0], temp);
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= (z ? PSW_Z : 0);
+}
+
+
+// 1111 1110 0000 0001 abs32... imm8....;
+// bclr imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
+8.0xfe+8.0x01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bclr
+"bclr"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FE010000 (); */
+ unsigned32 temp;
+ int z;
+
+ PC = cia;
+ temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
+ z = (temp & IMM8) == 0;
+ temp = temp & ~(IMM8);
+ store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= (z ? PSW_Z : 0);
+}
+
+
+// 1111 1010 1111 01An d8...... imm8....;
+// bclr imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
+8.0xfa+4.0xf,01,2.AN0+8.D8+8.IMM8:D2:::bclr
+"bclr"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FAF40000 (); */
+ unsigned32 temp;
+ int z;
+
+ PC = cia;
+ temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
+ z = (temp & (IMM8)) == 0;
+ temp = temp & ~(IMM8);
+ store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= (z ? PSW_Z : 0);
+}
+
+
+// 1111 0010 1011 DmDn; asr Dm,Dn
+8.0xf2+4.0xb,2.DM1,2.DN0:D0:::asr
+"asr"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F2B0 (); */
+ signed32 temp;
+ int z, n, c;
+
+ PC = cia;
+ temp = State.regs[REG_D0 + DN0];
+ c = temp & 1;
+ temp >>= State.regs[REG_D0 + DM1];
+ State.regs[REG_D0 + DN0] = temp;
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+
+// 1111 1000 1100 10Dn imm8...; asr imm8,Dn (imm8 is zero-extended.)
+8.0xf8+4.0xc,10,2.DN0+8.IMM8:D1:::asr
+"asr"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F8C800 (); */
+ signed32 temp;
+ int z, n, c;
+
+ PC = cia;
+ temp = State.regs[REG_D0 + DN0];
+ c = temp & 1;
+ temp >>= IMM8;
+ State.regs[REG_D0 + DN0] = temp;
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+
+// 1111 0010 1010 DmDn; lsr Dm,Dn
+8.0xf2+4.0xa,2.DM1,2.DN0:D0:::lsr
+"lsr"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F2A0 (); */
+ int z, n, c;
+
+ PC = cia;
+ c = State.regs[REG_D0 + DN0] & 1;
+ State.regs[REG_D0 + DN0]
+ >>= State.regs[REG_D0 + DM1];
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+
+// 1111 1000 1100 01Dn imm8...; lsr imm8,Dn (imm8 is zero-extended.)
+8.0xf8+4.0xc,01,2.DN0+8.IMM8:D1:::lsr
+"lsr"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F8C400 (); */
+ int z, n, c;
+
+ PC = cia;
+ c = State.regs[REG_D0 + DN0] & 1;
+ State.regs[REG_D0 + DN0] >>= IMM8;
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+
+// 1111 0010 1001 DmDn; asl Dm,Dn
+8.0xf2+4.0x9,2.DM1,2.DN0:D0:::asl
+"asl"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F290 (); */
+ int n, z;
+
+ PC = cia;
+ State.regs[REG_D0 + DN0]
+ <<= State.regs[REG_D0 + DM1];
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 1111 1000 1100 00Dn imm8...; asl imm8,Dn (imm8 is zero-extended.)
+8.0xf8+4.0xc,00,2.DN0+8.IMM8:D1:::asl
+"asl"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F8C000 (); */
+ int n, z;
+
+ PC = cia;
+ State.regs[REG_D0 + DN0] <<= IMM8;
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 0101 01Dn; als2 Dn
+4.0x5,01,2.DN0:S0:::asl2
+"asl2"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_54 (); */
+ int n, z;
+ PC = cia;
+
+ State.regs[REG_D0 + DN0] <<= 2;
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 1111 0010 1000 01Dn; ror Dn
+8.0xf2+4.0x8,01,2.DN0:D0:::ror
+"ror"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F284 (); */
+ unsigned32 value;
+ int c,n,z;
+
+ PC = cia;
+ value = State.regs[REG_D0 + DN0];
+ c = (value & 0x1);
+
+ value >>= 1;
+ value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
+ State.regs[REG_D0 + DN0] = value;
+ z = (value == 0);
+ n = (value & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+
+// 1111 0010 1000 00Dn; rol Dn
+8.0xf2+4.0x8,00,2.DN0:D0:::rol
+"rol"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F280 (); */
+ unsigned32 value;
+ int c,n,z;
+
+ PC = cia;
+ value = State.regs[REG_D0 + DN0];
+ c = (value & 0x80000000) ? 1 : 0;
+
+ value <<= 1;
+ value |= ((PSW & PSW_C) != 0);
+ State.regs[REG_D0 + DN0] = value;
+ z = (value == 0);
+ n = (value & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+
+// 1100 1000 d8......; beq (d8,PC) (d8 is sign-extended)
+8.0xc8+8.D8:S1:::beq
+"beq"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_C800 (); */
+ PC = cia;
+ if ((PSW & PSW_Z))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+
+// 1100 1001 d8......; bne (d8,PC) (d8 is sign-extended)
+8.0xc9+8.D8:S1:::bne
+"bne"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_C900 (); */
+ PC = cia;
+ if (!(PSW & PSW_Z))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+
+// 1100 0001 d8......; bgt (d8,PC) (d8 is sign-extended)
+8.0xc1+8.D8:S1:::bgt
+"bgt"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_C100 (); */
+ PC = cia;
+ if (!((PSW & PSW_Z)
+ || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+
+// 1100 0010 d8......; bge (d8,PC) (d8 is sign-extended)
+8.0xc2+8.D8:S1:::bge
+"bge"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_C200 (); */
+ PC = cia;
+ if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+
+// 1100 0011 d8......; ble (d8,PC) (d8 is sign-extended)
+8.0xc3+8.D8:S1:::ble
+"ble"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_C300 (); */
+ PC = cia;
+ if ((PSW & PSW_Z)
+ || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+
+// 1100 0000 d8......; blt (d8,PC) (d8 is sign-extended)
+8.0xc0+8.D8:S1:::blt
+"blt"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_C000 (); */
+ PC = cia;
+ if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+
+// 1100 0101 d8......; bhi (d8,PC) (d8 is sign-extended)
+8.0xc5+8.D8:S1:::bhi
+"bhi"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_C500 (); */
+ PC = cia;
+ if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+
+// 1100 0110 d8......; bcc (d8,PC) (d8 is sign-extended)
+8.0xc6+8.D8:S1:::bcc
+"bcc"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_C600 (); */
+ PC = cia;
+ if (!(PSW & PSW_C))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+
+// 1100 0101 d8......; bls (d8,PC) (d8 is sign-extended)
+8.0xc7+8.D8:S1:::bls
+"bls"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_C700 (); */
+ PC = cia;
+ if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+
+// 1100 0100 d8......; bcs (d8,PC) (d8 is sign-extended)
+8.0xc4+8.D8:S1:::bcs
+"bcs"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_C400 (); */
+ PC = cia;
+ if (PSW & PSW_C)
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+
+// 1111 1000 1110 1000 d8......; bvc (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xe8+8.D8:D1:::bvc
+"bvc"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F8E800 (); */
+ PC = cia;
+ if (!(PSW & PSW_V))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+
+// 1111 1000 1110 1001 d8......; bvs (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xe9+8.D8:D1:::bvs
+"bvs"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F8E900 (); */
+ PC = cia;
+ if (PSW & PSW_V)
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+
+// 1111 1000 1110 1010 d8......; bnc (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xea+8.D8:D1:::bnc
+"bnc"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F8EA00 (); */
+ PC = cia;
+ if (!(PSW & PSW_N))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+
+// 1111 1000 1110 1010 d8......; bns (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xeb+8.D8:D1:::bns
+"bns"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F8EB00 (); */
+ PC = cia;
+ if (PSW & PSW_N)
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+
+// 1100 1010 d8......; bra (d8,PC) (d8 is sign-extended)
+8.0xca+8.D8:S1:::bra
+"bra"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_CA00 (); */
+ PC = cia;
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+}
+
+
+// 1101 1000; leq
+8.0xd8:S0:::leq
+"leq"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_D8 (); */
+ PC = cia;
+ if (PSW & PSW_Z)
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+
+// 1101 1001; lne
+8.0xd9:S0:::lne
+"lne"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_D9 (); */
+ PC = cia;
+ if (!(PSW & PSW_Z))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+
+// 1101 0001; lgt
+8.0xd1:S0:::lgt
+"lgt"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_D1 (); */
+ PC = cia;
+ if (!((PSW & PSW_Z)
+ || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+
+// 1101 0010; lge
+8.0xd2:S0:::lge
+"lge"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_D2 (); */
+ PC = cia;
+ if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+
+// 1101 0011; lle
+8.0xd3:S0:::lle
+"lle"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_D3 (); */
+ PC = cia;
+ if ((PSW & PSW_Z)
+ || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+
+// 1101 0000; llt
+8.0xd0:S0:::llt
+"llt"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_D0 (); */
+ PC = cia;
+ if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+
+// 1101 0101; lhi
+8.0xd5:S0:::lhi
+"lhi"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_D5 (); */
+ PC = cia;
+ if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+
+// 1101 0110; lcc
+8.0xd6:S0:::lcc
+"lcc"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_D6 (); */
+ PC = cia;
+ if (!(PSW & PSW_C))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+
+// 1101 0111; lls
+8.0xd7:S0:::lls
+"lls"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_D7 (); */
+ PC = cia;
+ if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+
+// 1101 0100; lcs
+8.0xd4:S0:::lcs
+"lcs"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_D4 (); */
+ PC = cia;
+ if (PSW & PSW_C)
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+
+// 1101 1010; lra
+8.0xda:S0:::lra
+"lra"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_DA (); */
+ PC = cia;
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+}
+
+
+// 1101 1010; setlb
+8.0xdb:S0:::setlb
+"setlb"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_DB (); */
+ PC = cia;
+ State.regs[REG_LIR] = load_word (State.regs[REG_PC] + 1);
+ State.regs[REG_LAR] = State.regs[REG_PC] + 5;
+}
+
+
+// 1111 0000 1111 01An; jmp (An)
+8.0xf0+4.0xf,01,2.AN0:D0:::jmp
+"jmp"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F0F4 (); */
+ PC = State.regs[REG_A0 + AN0];
+ nia = PC;
+}
+
+
+// 1100 1100 d16.....; jmp (d16,PC) (d16 is sign-extended.)
+8.0xcc+8.D16A+8.D16B:S2:::jmp
+"jmp"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_CC0000 (); */
+ PC = cia + EXTEND16(FETCH16(D16A, D16B));
+ nia = PC;
+}
+
+
+// 1101 1100 d32........; jmp (d32, PC)
+8.0xdc+8.D32A+8.D32B+8.D32C+8.D32D:S4:::jmp
+"jmp"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_DC000000 (); */
+ PC = cia + FETCH32(D32A, D32B, D32C, D32D);
+ nia = PC;
+}
+
+
+// 1111 0000 1111 00An; calls (An)
+8.0xf0+4.0xf,00,2.AN0:D0:::calls
+"calls"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F0F0 (); */
+ unsigned32 next_pc, sp;
+
+ PC = cia;
+ sp = State.regs[REG_SP];
+ next_pc = State.regs[REG_PC] + 2;
+ store_word(sp, next_pc);
+ State.regs[REG_MDR] = next_pc;
+ State.regs[REG_PC] = State.regs[REG_A0 + AN0];
+ nia = PC;
+}
+
+
+// 1111 1010 1111 1111 d16.....; calls (d16,PC) (d16 is sign-extended.)
+8.0xfa+8.0xff+8.D16A+8.D16B:D2:::calls
+"calls"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FAFF0000 (); */
+ unsigned32 next_pc, sp;
+
+ PC = cia;
+ sp = State.regs[REG_SP];
+ next_pc = State.regs[REG_PC] + 4;
+ store_word(sp, next_pc);
+ State.regs[REG_MDR] = next_pc;
+ State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
+ nia = PC;
+}
+
+
+// 1111 1100 1111 1111 d32.....; calls (d32,PC)
+8.0xfc+8.0xff+8.D32A+8.D32B+8.D32C+8.D32D:D4:::calls
+"calls"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FCFF0000 (); */
+ unsigned32 next_pc, sp;
+
+ PC = cia;
+ sp = State.regs[REG_SP];
+ next_pc = State.regs[REG_PC] + 6;
+ store_word(sp, next_pc);
+ State.regs[REG_MDR] = next_pc;
+ State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
+ nia = PC;
+}
+
+
+// 1111 0000 1111 1100; rets
+8.0xf0+8.0xfc:D0:::rets
+"rets"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F0FC (); */
+ unsigned32 sp;
+
+ sp = State.regs[REG_SP];
+ State.regs[REG_PC] = load_word(sp);
+ nia = PC;
+}
+
+
+// 1111 0000 1111 1101; rti
+8.0xf0+8.0xfd:D0:::rti
+"rti"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F0FD (); */
+ unsigned32 sp;
+
+ sp = State.regs[REG_SP];
+ PSW = load_half(sp);
+ State.regs[REG_PC] = load_word(sp+4);
+ State.regs[REG_SP] +=8;
+ nia = PC;
+}
+
+
+// 1111 0000 1111 1110; trap
+8.0xf0+8.0xfe:D0:::trap
+"trap"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F0FE (); */
+ unsigned32 sp, next_pc;
+
+ PC = cia;
+ sp = State.regs[REG_SP];
+ next_pc = State.regs[REG_PC] + 2;
+ store_word(sp, next_pc);
+ nia = PC;
+}
+
+
+// 1111 0000 1111 1111; rtm
+8.0xf0+8.0xff:D0:::rtm
+"rtm"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F0FF (); */
+ PC = cia;
+ abort ();
+}
+
+
+// 1100 1011; nop
+8.0xcb:S0:::nop
+"nop"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_CB (); */
+ PC = cia;
+}
+
+
+// 1111 0101 0000 DmDn; udf20 Dm,Dn
+8.0xf5+4.0x0,2.DM1,2.DN0:D0:::putx
+"putx"
+*mn10300
+{
+ /* OP_F500 (); */
+ PC = cia;
+ State.regs[REG_MDRQ] = State.regs[REG_D0 + DN0];
+}
+
+
+// 1111 0110 1111 DmDn; udf15 Dm,Dn
+8.0xf6+4.0xf,2.DM1,2.DN0:D0:::getx
+"getx"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F6F0 (); */
+ int z, n;
+
+ PC = cia;
+ z = (State.regs[REG_MDRQ] == 0);
+ n = ((State.regs[REG_MDRQ] & 0x80000000) != 0);
+ State.regs[REG_D0 + DN0] = State.regs[REG_MDRQ];
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
+}
+
+
+// 1111 0110 0000 DmDn; udf00 Dm,Dn
+8.0xf6+4.0x0,2.DM1,2.DN0:D0:::mulq
+"mulq"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F600 (); */
+ unsigned64 temp;
+ int n, z;
+
+ PC = cia;
+ temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
+ * (signed64)(signed32)State.regs[REG_D0 + DM1]);
+ State.regs[REG_D0 + DN0] = temp & 0xffffffff;
+ State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 1111 1001 0000 00Dn imm8....; udf00 imm8,Dn (imm8 is sign-extended.)
+8.0xf9+4.0x,00,2.DN0+8.IMM8:D1:::mulq
+"mulq"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F90000 (); */
+ unsigned64 temp;
+ int n, z;
+
+ PC = cia;
+ temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
+ * (signed64)(signed32)EXTEND8 (IMM8));
+ State.regs[REG_D0 + DN0] = temp & 0xffffffff;
+ State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 1111 1011 0000 00Dn imm16...; udf00 imm16,Dn (imm16 is sign-extended.)
+8.0xfb+4.0x0,00,2.DN0+8.IMM16A+8.IMM16B:D2:::mulq
+"mulq"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FB000000 (); */
+ unsigned64 temp;
+ int n, z;
+
+ PC = cia;
+ temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
+ * (signed64)(signed32)EXTEND16 (FETCH16(IMM16A, IMM16B)));
+ State.regs[REG_D0 + DN0] = temp & 0xffffffff;
+ State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 1111 1101 0000 00Dn imm32...; udf00 imm32,Dn
+8.0xfd+4.0x0,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulq
+"mulq"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FD000000 (); */
+ unsigned64 temp;
+ int n, z;
+
+ PC = cia;
+ temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
+ * (signed64)(signed32)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
+ State.regs[REG_D0 + DN0] = temp & 0xffffffff;
+ State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 1111 0110 0001 DmDn; udf01 Dm,Dn
+8.0xf6+4.0x1,2.DM1,2.DN0:D0:::mulqu
+"mulqu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F610 (); */
+ unsigned64 temp;
+ int n, z;
+
+ PC = cia;
+ temp = ((unsigned64) State.regs[REG_D0 + DN0]
+ * (unsigned64) State.regs[REG_D0 + DM1]);
+ State.regs[REG_D0 + DN0] = temp & 0xffffffff;
+ State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 1111 1001 0001 01Dn imm8....; udfu01 imm8,Dn (imm8 is zero-extended.)
+8.0xf9+4.0x1,01,2.DN0+8.IMM8:D1:::mulqu
+"mulqu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F91400 (); */
+ unsigned64 temp;
+ int n, z;
+
+ PC = cia;
+ temp = ((unsigned64)State.regs[REG_D0 + DN0]
+ * (unsigned64)EXTEND8 (IMM8));
+ State.regs[REG_D0 + DN0] = temp & 0xffffffff;
+ State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 1111 1011 0001 01Dn imm16...; udfu01 imm16,Dn (imm16 is zero-extended.)
+8.0xfb+4.0x1,01,2.DN0+8.IMM16A+8.IMM16B:D2:::mulqu
+"mulqu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FB140000 (); */
+ unsigned64 temp;
+ int n, z;
+
+ PC = cia;
+ temp = ((unsigned64)State.regs[REG_D0 + DN0]
+ * (unsigned64) EXTEND16 (FETCH16(IMM16A, IMM16B)));
+ State.regs[REG_D0 + DN0] = temp & 0xffffffff;
+ State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 1111 1101 0001 01Dn imm32...; udfu01 imm32,Dn
+8.0xfd+4.0x1,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulqu
+"mulqu"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FD140000 (); */
+ unsigned64 temp;
+ int n, z;
+
+ PC = cia;
+ temp = ((unsigned64)State.regs[REG_D0 + DN0]
+ * (unsigned64)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
+ State.regs[REG_D0 + DN0] = temp & 0xffffffff;
+ State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
+ z = (State.regs[REG_D0 + DN0] == 0);
+ n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 1111 0110 0100 DmDn; udf04 Dm,Dn
+8.0xf6+4.0x4,2.DM1,2.DN0:D0:::sat16
+"sat16"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F640 (); */
+ int temp;
+
+ PC = cia;
+ temp = State.regs[REG_D0 + DM1];
+ temp = (temp > 0x7fff ? 0x7fff : temp);
+ temp = (temp < -0x8000 ? -0x8000 : temp);
+ State.regs[REG_D0 + DN0] = temp;
+}
+
+
+// 1111 0110 0101 DmDn; udf05 Dm,Dn
+8.0xf6+4.0x5,2.DM1,2.DN0:D0:::sat24
+"sat24"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F650 (); */
+ int temp;
+
+ PC = cia;
+ temp = State.regs[REG_D0 + DM1];
+ temp = (temp > 0x7fffff ? 0x7fffff : temp);
+ temp = (temp < -0x800000 ? -0x800000 : temp);
+ State.regs[REG_D0 + DN0] = temp;
+}
+
+
+// 1111 0110 0111 DmDn; udf07 Dm,Dn
+8.0xf6+4.0x7,2.DM1,2.DN0:D0:::bsch
+"bsch"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F670 (); */
+ int temp, c;
+
+ PC = cia;
+ temp = State.regs[REG_D0 + DM1];
+ temp <<= (State.regs[REG_D0 + DN0] & 0x1f);
+ c = (temp != 0 ? 1 : 0);
+ PSW &= ~(PSW_C);
+ PSW |= (c ? PSW_C : 0);
+}
+
+
+// 1111 0000 1100 0000; syscall
+8.0xf0+8.0xc0:D0:::syscall
+"syscall"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_F0C0 (); */
+ PC = cia;
+ do_syscall ();
+}
+
+
+// 1111 1111; break
+8.0xff:S0:::break
+"break"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_FF (); */
+ PC = cia;
+ program_interrupt(SD, CPU, cia, SIM_SIGTRAP);
+}
+
+// 1100 1110 regs....; movm (SP),regs
+8.0xce+8.REGS:S1:::movm
+"movm"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_CE00 (); */
+ unsigned32 sp = State.regs[REG_SP];
+ unsigned32 mask;
+
+ PC = cia;
+ mask = REGS;
+
+ if (mask & 0x8)
+ {
+ sp += 4;
+ State.regs[REG_LAR] = load_word (sp);
+ sp += 4;
+ State.regs[REG_LIR] = load_word (sp);
+ sp += 4;
+ State.regs[REG_MDR] = load_word (sp);
+ sp += 4;
+ State.regs[REG_A0 + 1] = load_word (sp);
+ sp += 4;
+ State.regs[REG_A0] = load_word (sp);
+ sp += 4;
+ State.regs[REG_D0 + 1] = load_word (sp);
+ sp += 4;
+ State.regs[REG_D0] = load_word (sp);
+ sp += 4;
+ }
+
+ if (mask & 0x10)
+ {
+ State.regs[REG_A0 + 3] = load_word (sp);
+ sp += 4;
+ }
+
+ if (mask & 0x20)
+ {
+ State.regs[REG_A0 + 2] = load_word (sp);
+ sp += 4;
+ }
+
+ if (mask & 0x40)
+ {
+ State.regs[REG_D0 + 3] = load_word (sp);
+ sp += 4;
+ }
+
+ if (mask & 0x80)
+ {
+ State.regs[REG_D0 + 2] = load_word (sp);
+ sp += 4;
+ }
+
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+ )
+ {
+ if (mask & 0x1)
+ {
+ /* Need to restore MDRQ, MCRH, MCRL, and MCVF */
+ sp += 16;
+ State.regs[REG_E0 + 1] = load_word (sp);
+ sp += 4;
+ State.regs[REG_E0 + 0] = load_word (sp);
+ sp += 4;
+ }
+
+ if (mask & 0x2)
+ {
+ State.regs[REG_E0 + 7] = load_word (sp);
+ sp += 4;
+ State.regs[REG_E0 + 6] = load_word (sp);
+ sp += 4;
+ State.regs[REG_E0 + 5] = load_word (sp);
+ sp += 4;
+ State.regs[REG_E0 + 4] = load_word (sp);
+ sp += 4;
+ }
+
+ if (mask & 0x4)
+ {
+ State.regs[REG_E0 + 3] = load_word (sp);
+ sp += 4;
+ State.regs[REG_E0 + 2] = load_word (sp);
+ sp += 4;
+ }
+ }
+
+ /* And make sure to update the stack pointer. */
+ State.regs[REG_SP] = sp;
+}
+
+
+// 1100 1111 regs....; movm regs,(SP)
+8.0xcf+8.REGS:S1a:::movm
+"movm"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_CF00 (); */
+ unsigned32 sp = State.regs[REG_SP];
+ unsigned32 mask;
+
+ PC = cia;
+ mask = REGS;
+
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+ )
+ {
+ if (mask & 0x4)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 2]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 3]);
+ }
+
+ if (mask & 0x2)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 4]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 5]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 6]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 7]);
+ }
+
+ if (mask & 0x1)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 0]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 1]);
+ sp -= 16;
+ /* Need to save MDRQ, MCRH, MCRL, and MCVF */
+ }
+ }
+
+ if (mask & 0x80)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_D0 + 2]);
+ }
+
+ if (mask & 0x40)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_D0 + 3]);
+ }
+
+ if (mask & 0x20)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_A0 + 2]);
+ }
+
+ if (mask & 0x10)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_A0 + 3]);
+ }
+
+ if (mask & 0x8)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_D0]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_D0 + 1]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_A0]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_A0 + 1]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_MDR]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_LIR]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_LAR]);
+ sp -= 4;
+ }
+
+ /* And make sure to update the stack pointer. */
+ State.regs[REG_SP] = sp;
+}
+
+// 1100 1101 d16..... regs.... imm8....;
+// call (d16,PC),regs,imm8 (d16 is sign-extended., imm8 is zero-extended.)
+8.0xcd+8.D16A+8.D16B+8.REGS+8.IMM8:S4:::call
+"call"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_CD000000 (); */
+ unsigned32 next_pc, sp;
+ unsigned32 mask;
+
+ PC = cia;
+ sp = State.regs[REG_SP];
+ next_pc = PC + 5;
+ store_word(sp, next_pc);
+
+ mask = REGS;
+
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+ )
+ {
+ if (mask & 0x4)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 2]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 3]);
+ }
+
+ if (mask & 0x2)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 4]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 5]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 6]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 7]);
+ }
+
+ if (mask & 0x1)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 0]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 1]);
+ sp -= 16;
+ /* Need to save MDRQ, MCRH, MCRL, and MCVF */
+ }
+ }
+
+ if (mask & 0x80)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_D0 + 2]);
+ }
+
+ if (mask & 0x40)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_D0 + 3]);
+ }
+
+ if (mask & 0x20)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_A0 + 2]);
+ }
+
+ if (mask & 0x10)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_A0 + 3]);
+ }
+
+ if (mask & 0x8)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_D0]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_D0 + 1]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_A0]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_A0 + 1]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_MDR]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_LIR]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_LAR]);
+ sp -= 4;
+ }
+
+ /* Update the stack pointer, note that the register saves to do not
+ modify SP. The SP adjustment is derived totally from the imm8
+ field. */
+ State.regs[REG_SP] -= IMM8;
+ State.regs[REG_MDR] = next_pc;
+ State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
+ nia = PC;
+}
+
+
+// 1101 1101 d32..... regs.... imm8....;
+// call (d32,PC),regs,imm8 (imm8 is zero-extended.)
+8.0xdd+8.D32A+8.D32B+8.D32C+8.D32D+8.REGS+8.IMM8:S6:::call
+"call"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_DD000000 (); */
+ unsigned32 next_pc, sp;
+ unsigned32 mask;
+
+ PC = cia;
+ sp = State.regs[REG_SP];
+ next_pc = State.regs[REG_PC] + 7;
+ /* could assert that nia == next_pc here */
+ store_word(sp, next_pc);
+
+ mask = REGS;
+
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+ )
+ {
+ if (mask & 0x4)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 2]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 3]);
+ }
+
+ if (mask & 0x2)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 4]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 5]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 6]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 7]);
+ }
+
+ if (mask & 0x1)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 0]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_E0 + 1]);
+ sp -= 16;
+ /* Need to save MDRQ, MCRH, MCRL, and MCVF */
+ }
+ }
+
+ if (mask & 0x80)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_D0 + 2]);
+ }
+
+ if (mask & 0x40)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_D0 + 3]);
+ }
+
+ if (mask & 0x20)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_A0 + 2]);
+ }
+
+ if (mask & 0x10)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_A0 + 3]);
+ }
+
+ if (mask & 0x8)
+ {
+ sp -= 4;
+ store_word (sp, State.regs[REG_D0]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_D0 + 1]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_A0]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_A0 + 1]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_MDR]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_LIR]);
+ sp -= 4;
+ store_word (sp, State.regs[REG_LAR]);
+ sp -= 4;
+ }
+
+ /* Update the stack pointer, note that the register saves to do not
+ modify SP. The SP adjustment is derived totally from the imm8
+ field. */
+ State.regs[REG_SP] -= IMM8;
+ State.regs[REG_MDR] = next_pc;
+ State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
+ nia = PC;
+}
+
+
+// 1101 1111 regs.... imm8....; ret regs,imm8 (imm8 is zero-extended.)
+8.0xdf+8.REGS+8.IMM8:S2:::ret
+"ret"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_DF0000 (); */
+ unsigned32 sp, offset;
+ unsigned32 mask;
+
+ PC = cia;
+ State.regs[REG_SP] += IMM8;
+ sp = State.regs[REG_SP];
+
+ offset = -4;
+ mask = REGS;
+
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+ )
+ {
+
+ if (mask & 0x4)
+ {
+ State.regs[REG_E0 + 2] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 3] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ if (mask & 0x2)
+ {
+ State.regs[REG_E0 + 4] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 5] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 6] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 7] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ if (mask & 0x1)
+ {
+ /* Need to restore MDRQ, MCRH, MCRL, and MCVF */
+ offset -= 16;
+ State.regs[REG_E0 + 0] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 1] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ }
+
+ if (mask & 0x80)
+ {
+ State.regs[REG_D0 + 2] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ if (mask & 0x40)
+ {
+ State.regs[REG_D0 + 3] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ if (mask & 0x20)
+ {
+ State.regs[REG_A0 + 2] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ if (mask & 0x10)
+ {
+ State.regs[REG_A0 + 3] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ if (mask & 0x8)
+ {
+ State.regs[REG_D0] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_D0 + 1] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_A0] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_A0 + 1] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_MDR] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_LIR] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_LAR] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ /* Restore the PC value. */
+ State.regs[REG_PC] = load_word(sp);
+ nia = PC;
+}
+
+
+// 1101 1110 regs.... imm8....; retf regs,imm8 (imm8 is zero-extended.)
+8.0xde+8.REGS+8.IMM8:S2:::retf
+"retf"
+*mn10300
+
+*am33
+*am33_2
+
+{
+ /* OP_DE0000 (); */
+ unsigned32 sp, offset;
+ unsigned32 mask;
+
+ PC = cia;
+ State.regs[REG_SP] += IMM8;
+ sp = State.regs[REG_SP];
+ State.regs[REG_PC] = State.regs[REG_MDR];
+
+ offset = -4;
+ mask = REGS;
+
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+ )
+ {
+
+ if (mask & 0x4)
+ {
+ State.regs[REG_E0 + 2] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 3] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ if (mask & 0x2)
+ {
+ State.regs[REG_E0 + 4] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 5] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 6] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 7] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ if (mask & 0x1)
+ {
+ /* Need to restore MDRQ, MCRH, MCRL, and MCVF */
+ offset -= 16;
+ State.regs[REG_E0 + 0] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_E0 + 1] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ }
+
+ if (mask & 0x80)
+ {
+ State.regs[REG_D0 + 2] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ if (mask & 0x40)
+ {
+ State.regs[REG_D0 + 3] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ if (mask & 0x20)
+ {
+ State.regs[REG_A0 + 2] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ if (mask & 0x10)
+ {
+ State.regs[REG_A0 + 3] = load_word (sp + offset);
+ offset -= 4;
+ }
+
+ if (mask & 0x8)
+ {
+ State.regs[REG_D0] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_D0 + 1] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_A0] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_A0 + 1] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_MDR] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_LIR] = load_word (sp + offset);
+ offset -= 4;
+ State.regs[REG_LAR] = load_word (sp + offset);
+ offset -= 4;
+ }
+ nia = PC;
+}
+
+
+:include::am33:am33.igen
+
Index: configure
===================================================================
--- configure (nonexistent)
+++ configure (revision 842)
@@ -0,0 +1,6515 @@
+#! /bin/sh
+# Guess values for system-dependent variables and create Makefiles.
+# Generated by GNU Autoconf 2.64.
+#
+# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
+# 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software
+# Foundation, Inc.
+#
+# This configure script is free software; the Free Software Foundation
+# gives unlimited permission to copy, distribute and modify it.
+## -------------------- ##
+## M4sh Initialization. ##
+## -------------------- ##
+
+# Be more Bourne compatible
+DUALCASE=1; export DUALCASE # for MKS sh
+if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then :
+ emulate sh
+ NULLCMD=:
+ # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which
+ # is contrary to our usage. Disable this feature.
+ alias -g '${1+"$@"}'='"$@"'
+ setopt NO_GLOB_SUBST
+else
+ case `(set -o) 2>/dev/null` in #(
+ *posix*) :
+ set -o posix ;; #(
+ *) :
+ ;;
+esac
+fi
+
+
+as_nl='
+'
+export as_nl
+# Printing a long string crashes Solaris 7 /usr/bin/printf.
+as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
+as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo
+as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo
+# Prefer a ksh shell builtin over an external printf program on Solaris,
+# but without wasting forks for bash or zsh.
+if test -z "$BASH_VERSION$ZSH_VERSION" \
+ && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then
+ as_echo='print -r --'
+ as_echo_n='print -rn --'
+elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then
+ as_echo='printf %s\n'
+ as_echo_n='printf %s'
+else
+ if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then
+ as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"'
+ as_echo_n='/usr/ucb/echo -n'
+ else
+ as_echo_body='eval expr "X$1" : "X\\(.*\\)"'
+ as_echo_n_body='eval
+ arg=$1;
+ case $arg in #(
+ *"$as_nl"*)
+ expr "X$arg" : "X\\(.*\\)$as_nl";
+ arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;;
+ esac;
+ expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl"
+ '
+ export as_echo_n_body
+ as_echo_n='sh -c $as_echo_n_body as_echo'
+ fi
+ export as_echo_body
+ as_echo='sh -c $as_echo_body as_echo'
+fi
+
+# The user is always right.
+if test "${PATH_SEPARATOR+set}" != set; then
+ PATH_SEPARATOR=:
+ (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && {
+ (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 ||
+ PATH_SEPARATOR=';'
+ }
+fi
+
+
+# IFS
+# We need space, tab and new line, in precisely that order. Quoting is
+# there to prevent editors from complaining about space-tab.
+# (If _AS_PATH_WALK were called with IFS unset, it would disable word
+# splitting by setting IFS to empty value.)
+IFS=" "" $as_nl"
+
+# Find who we are. Look in the path if we contain no directory separator.
+case $0 in #((
+ *[\\/]* ) as_myself=$0 ;;
+ *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
+ done
+IFS=$as_save_IFS
+
+ ;;
+esac
+# We did not find ourselves, most probably we were run as `sh COMMAND'
+# in which case we are not to be found in the path.
+if test "x$as_myself" = x; then
+ as_myself=$0
+fi
+if test ! -f "$as_myself"; then
+ $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2
+ exit 1
+fi
+
+# Unset variables that we do not need and which cause bugs (e.g. in
+# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1"
+# suppresses any "Segmentation fault" message there. '((' could
+# trigger a bug in pdksh 5.2.14.
+for as_var in BASH_ENV ENV MAIL MAILPATH
+do eval test x\${$as_var+set} = xset \
+ && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || :
+done
+PS1='$ '
+PS2='> '
+PS4='+ '
+
+# NLS nuisances.
+LC_ALL=C
+export LC_ALL
+LANGUAGE=C
+export LANGUAGE
+
+# CDPATH.
+(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
+
+if test "x$CONFIG_SHELL" = x; then
+ as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then :
+ emulate sh
+ NULLCMD=:
+ # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which
+ # is contrary to our usage. Disable this feature.
+ alias -g '\${1+\"\$@\"}'='\"\$@\"'
+ setopt NO_GLOB_SUBST
+else
+ case \`(set -o) 2>/dev/null\` in #(
+ *posix*) :
+ set -o posix ;; #(
+ *) :
+ ;;
+esac
+fi
+"
+ as_required="as_fn_return () { (exit \$1); }
+as_fn_success () { as_fn_return 0; }
+as_fn_failure () { as_fn_return 1; }
+as_fn_ret_success () { return 0; }
+as_fn_ret_failure () { return 1; }
+
+exitcode=0
+as_fn_success || { exitcode=1; echo as_fn_success failed.; }
+as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; }
+as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; }
+as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; }
+if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then :
+
+else
+ exitcode=1; echo positional parameters were not saved.
+fi
+test x\$exitcode = x0 || exit 1"
+ as_suggested=" as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO
+ as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO
+ eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" &&
+ test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1
+test \$(( 1 + 1 )) = 2 || exit 1"
+ if (eval "$as_required") 2>/dev/null; then :
+ as_have_required=yes
+else
+ as_have_required=no
+fi
+ if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then :
+
+else
+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+as_found=false
+for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ as_found=:
+ case $as_dir in #(
+ /*)
+ for as_base in sh bash ksh sh5; do
+ # Try only shells that exist, to save several forks.
+ as_shell=$as_dir/$as_base
+ if { test -f "$as_shell" || test -f "$as_shell.exe"; } &&
+ { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then :
+ CONFIG_SHELL=$as_shell as_have_required=yes
+ if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then :
+ break 2
+fi
+fi
+ done;;
+ esac
+ as_found=false
+done
+$as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } &&
+ { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then :
+ CONFIG_SHELL=$SHELL as_have_required=yes
+fi; }
+IFS=$as_save_IFS
+
+
+ if test "x$CONFIG_SHELL" != x; then :
+ # We cannot yet assume a decent shell, so we have to provide a
+ # neutralization value for shells without unset; and this also
+ # works around shells that cannot unset nonexistent variables.
+ BASH_ENV=/dev/null
+ ENV=/dev/null
+ (unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV
+ export CONFIG_SHELL
+ exec "$CONFIG_SHELL" "$as_myself" ${1+"$@"}
+fi
+
+ if test x$as_have_required = xno; then :
+ $as_echo "$0: This script requires a shell more modern than all"
+ $as_echo "$0: the shells that I found on your system."
+ if test x${ZSH_VERSION+set} = xset ; then
+ $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should"
+ $as_echo "$0: be upgraded to zsh 4.3.4 or later."
+ else
+ $as_echo "$0: Please tell bug-autoconf@gnu.org about your system,
+$0: including any error possibly output before this
+$0: message. Then install a modern shell, or manually run
+$0: the script under such a shell if you do have one."
+ fi
+ exit 1
+fi
+fi
+fi
+SHELL=${CONFIG_SHELL-/bin/sh}
+export SHELL
+# Unset more variables known to interfere with behavior of common tools.
+CLICOLOR_FORCE= GREP_OPTIONS=
+unset CLICOLOR_FORCE GREP_OPTIONS
+
+## --------------------- ##
+## M4sh Shell Functions. ##
+## --------------------- ##
+# as_fn_unset VAR
+# ---------------
+# Portably unset VAR.
+as_fn_unset ()
+{
+ { eval $1=; unset $1;}
+}
+as_unset=as_fn_unset
+
+# as_fn_set_status STATUS
+# -----------------------
+# Set $? to STATUS, without forking.
+as_fn_set_status ()
+{
+ return $1
+} # as_fn_set_status
+
+# as_fn_exit STATUS
+# -----------------
+# Exit the shell with STATUS, even in a "trap 0" or "set -e" context.
+as_fn_exit ()
+{
+ set +e
+ as_fn_set_status $1
+ exit $1
+} # as_fn_exit
+
+# as_fn_mkdir_p
+# -------------
+# Create "$as_dir" as a directory, including parents if necessary.
+as_fn_mkdir_p ()
+{
+
+ case $as_dir in #(
+ -*) as_dir=./$as_dir;;
+ esac
+ test -d "$as_dir" || eval $as_mkdir_p || {
+ as_dirs=
+ while :; do
+ case $as_dir in #(
+ *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'(
+ *) as_qdir=$as_dir;;
+ esac
+ as_dirs="'$as_qdir' $as_dirs"
+ as_dir=`$as_dirname -- "$as_dir" ||
+$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$as_dir" : 'X\(//\)[^/]' \| \
+ X"$as_dir" : 'X\(//\)$' \| \
+ X"$as_dir" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X"$as_dir" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
+ s//\1/
+ q
+ }
+ /^X\(\/\/\)[^/].*/{
+ s//\1/
+ q
+ }
+ /^X\(\/\/\)$/{
+ s//\1/
+ q
+ }
+ /^X\(\/\).*/{
+ s//\1/
+ q
+ }
+ s/.*/./; q'`
+ test -d "$as_dir" && break
+ done
+ test -z "$as_dirs" || eval "mkdir $as_dirs"
+ } || test -d "$as_dir" || as_fn_error "cannot create directory $as_dir"
+
+
+} # as_fn_mkdir_p
+# as_fn_append VAR VALUE
+# ----------------------
+# Append the text in VALUE to the end of the definition contained in VAR. Take
+# advantage of any shell optimizations that allow amortized linear growth over
+# repeated appends, instead of the typical quadratic growth present in naive
+# implementations.
+if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then :
+ eval 'as_fn_append ()
+ {
+ eval $1+=\$2
+ }'
+else
+ as_fn_append ()
+ {
+ eval $1=\$$1\$2
+ }
+fi # as_fn_append
+
+# as_fn_arith ARG...
+# ------------------
+# Perform arithmetic evaluation on the ARGs, and store the result in the
+# global $as_val. Take advantage of shells that can avoid forks. The arguments
+# must be portable across $(()) and expr.
+if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then :
+ eval 'as_fn_arith ()
+ {
+ as_val=$(( $* ))
+ }'
+else
+ as_fn_arith ()
+ {
+ as_val=`expr "$@" || test $? -eq 1`
+ }
+fi # as_fn_arith
+
+
+# as_fn_error ERROR [LINENO LOG_FD]
+# ---------------------------------
+# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are
+# provided, also output the error to LOG_FD, referencing LINENO. Then exit the
+# script with status $?, using 1 if that was 0.
+as_fn_error ()
+{
+ as_status=$?; test $as_status -eq 0 && as_status=1
+ if test "$3"; then
+ as_lineno=${as_lineno-"$2"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+ $as_echo "$as_me:${as_lineno-$LINENO}: error: $1" >&$3
+ fi
+ $as_echo "$as_me: error: $1" >&2
+ as_fn_exit $as_status
+} # as_fn_error
+
+if expr a : '\(a\)' >/dev/null 2>&1 &&
+ test "X`expr 00001 : '.*\(...\)'`" = X001; then
+ as_expr=expr
+else
+ as_expr=false
+fi
+
+if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then
+ as_basename=basename
+else
+ as_basename=false
+fi
+
+if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then
+ as_dirname=dirname
+else
+ as_dirname=false
+fi
+
+as_me=`$as_basename -- "$0" ||
+$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
+ X"$0" : 'X\(//\)$' \| \
+ X"$0" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X/"$0" |
+ sed '/^.*\/\([^/][^/]*\)\/*$/{
+ s//\1/
+ q
+ }
+ /^X\/\(\/\/\)$/{
+ s//\1/
+ q
+ }
+ /^X\/\(\/\).*/{
+ s//\1/
+ q
+ }
+ s/.*/./; q'`
+
+# Avoid depending upon Character Ranges.
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+as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
+as_cr_Letters=$as_cr_letters$as_cr_LETTERS
+as_cr_digits='0123456789'
+as_cr_alnum=$as_cr_Letters$as_cr_digits
+
+
+ as_lineno_1=$LINENO as_lineno_1a=$LINENO
+ as_lineno_2=$LINENO as_lineno_2a=$LINENO
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+ # Blame Lee E. McMahon (1931-1989) for sed's syntax. :-)
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+ p
+ /[$]LINENO/=
+ ' <$as_myself |
+ sed '
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+ t lineno
+ b
+ :lineno
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+ t loop
+ s/-\n.*//
+ ' >$as_me.lineno &&
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+ { $as_echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2; as_fn_exit 1; }
+
+ # Don't try to exec as it changes $[0], causing all sort of problems
+ # (the dirname of $[0] is not the place where we might find the
+ # original and so on. Autoconf is especially sensitive to this).
+ . "./$as_me.lineno"
+ # Exit status is that of the last command.
+ exit
+}
+
+ECHO_C= ECHO_N= ECHO_T=
+case `echo -n x` in #(((((
+-n*)
+ case `echo 'xy\c'` in
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+ xy) ECHO_C='\c';;
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+*)
+ ECHO_N='-n';;
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+
+rm -f conf$$ conf$$.exe conf$$.file
+if test -d conf$$.dir; then
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+else
+ rm -f conf$$.dir
+ mkdir conf$$.dir 2>/dev/null
+fi
+if (echo >conf$$.file) 2>/dev/null; then
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+ as_ln_s='ln -s'
+ # ... but there are two gotchas:
+ # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail.
+ # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable.
+ # In both cases, we have to default to `cp -p'.
+ ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe ||
+ as_ln_s='cp -p'
+ elif ln conf$$.file conf$$ 2>/dev/null; then
+ as_ln_s=ln
+ else
+ as_ln_s='cp -p'
+ fi
+else
+ as_ln_s='cp -p'
+fi
+rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file
+rmdir conf$$.dir 2>/dev/null
+
+if mkdir -p . 2>/dev/null; then
+ as_mkdir_p='mkdir -p "$as_dir"'
+else
+ test -d ./-p && rmdir ./-p
+ as_mkdir_p=false
+fi
+
+if test -x / >/dev/null 2>&1; then
+ as_test_x='test -x'
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+ if ls -dL / >/dev/null 2>&1; then
+ as_ls_L_option=L
+ else
+ as_ls_L_option=
+ fi
+ as_test_x='
+ eval sh -c '\''
+ if test -d "$1"; then
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+ else
+ case $1 in #(
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+ esac;
+ case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #((
+ ???[sx]*):;;*)false;;esac;fi
+ '\'' sh
+ '
+fi
+as_executable_p=$as_test_x
+
+# Sed expression to map a string onto a valid CPP name.
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+
+# Sed expression to map a string onto a valid variable name.
+as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
+
+
+exec 7<&0 &1
+
+# Name of the host.
+# hostname on some systems (SVR3.2, Linux) returns a bogus exit status,
+# so uname gets run too.
+ac_hostname=`(hostname || uname -n) 2>/dev/null | sed 1q`
+
+#
+# Initializations.
+#
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+ac_config_libobj_dir=.
+LIBOBJS=
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+
+ac_unique_file="Makefile.in"
+# Factoring default headers for most tests.
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+#ifdef HAVE_SYS_TYPES_H
+# include
+#endif
+#ifdef HAVE_SYS_STAT_H
+# include
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+#ifdef STDC_HEADERS
+# include
+# include
+#else
+# ifdef HAVE_STDLIB_H
+# include
+# endif
+#endif
+#ifdef HAVE_STRING_H
+# if !defined STDC_HEADERS && defined HAVE_MEMORY_H
+# include
+# endif
+# include
+#endif
+#ifdef HAVE_STRINGS_H
+# include
+#endif
+#ifdef HAVE_INTTYPES_H
+# include
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+#ifdef HAVE_STDINT_H
+# include
+#endif
+#ifdef HAVE_UNISTD_H
+# include
+#endif"
+
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+LIBOBJS
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+REPORT_BUGS_TEXI
+REPORT_BUGS_TO
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+sim_stdio
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+sim_cflags
+sim_bswap
+MAINT
+EGREP
+GREP
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+CATOBJEXT
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+DATADIRNAME
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+build_cpu
+build
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+WARN_CFLAGS
+sim_xor_endian
+sim_stdcall
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+sim_packages
+sim_inline
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+sim_hw_objs
+sim_hw_cflags
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+sim_endian
+sim_bitsize
+sim_assert
+sim_alignment
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+build_alias
+LIBS
+ECHO_T
+ECHO_N
+ECHO_C
+DEFS
+mandir
+localedir
+libdir
+psdir
+pdfdir
+dvidir
+htmldir
+infodir
+docdir
+oldincludedir
+includedir
+localstatedir
+sharedstatedir
+sysconfdir
+datadir
+datarootdir
+libexecdir
+sbindir
+bindir
+program_transform_name
+prefix
+exec_prefix
+PACKAGE_URL
+PACKAGE_BUGREPORT
+PACKAGE_STRING
+PACKAGE_VERSION
+PACKAGE_TARNAME
+PACKAGE_NAME
+PATH_SEPARATOR
+SHELL'
+ac_subst_files=''
+ac_user_opts='
+enable_option_checking
+with_zlib
+enable_maintainer_mode
+enable_sim_bswap
+enable_sim_cflags
+enable_sim_debug
+enable_sim_stdio
+enable_sim_trace
+enable_sim_profile
+with_pkgversion
+with_bugurl
+enable_sim_endian
+enable_sim_alignment
+enable_sim_hostendian
+enable_build_warnings
+enable_sim_build_warnings
+enable_sim_reserved_bits
+enable_sim_bitsize
+enable_sim_inline
+enable_sim_hardware
+'
+ ac_precious_vars='build_alias
+host_alias
+target_alias
+CC
+CFLAGS
+LDFLAGS
+LIBS
+CPPFLAGS
+CPP'
+
+
+# Initialize some variables set by options.
+ac_init_help=
+ac_init_version=false
+ac_unrecognized_opts=
+ac_unrecognized_sep=
+# The variables have the same names as the options, with
+# dashes changed to underlines.
+cache_file=/dev/null
+exec_prefix=NONE
+no_create=
+no_recursion=
+prefix=NONE
+program_prefix=NONE
+program_suffix=NONE
+program_transform_name=s,x,x,
+silent=
+site=
+srcdir=
+verbose=
+x_includes=NONE
+x_libraries=NONE
+
+# Installation directory options.
+# These are left unexpanded so users can "make install exec_prefix=/foo"
+# and all the variables that are supposed to be based on exec_prefix
+# by default will actually change.
+# Use braces instead of parens because sh, perl, etc. also accept them.
+# (The list follows the same order as the GNU Coding Standards.)
+bindir='${exec_prefix}/bin'
+sbindir='${exec_prefix}/sbin'
+libexecdir='${exec_prefix}/libexec'
+datarootdir='${prefix}/share'
+datadir='${datarootdir}'
+sysconfdir='${prefix}/etc'
+sharedstatedir='${prefix}/com'
+localstatedir='${prefix}/var'
+includedir='${prefix}/include'
+oldincludedir='/usr/include'
+docdir='${datarootdir}/doc/${PACKAGE}'
+infodir='${datarootdir}/info'
+htmldir='${docdir}'
+dvidir='${docdir}'
+pdfdir='${docdir}'
+psdir='${docdir}'
+libdir='${exec_prefix}/lib'
+localedir='${datarootdir}/locale'
+mandir='${datarootdir}/man'
+
+ac_prev=
+ac_dashdash=
+for ac_option
+do
+ # If the previous option needs an argument, assign it.
+ if test -n "$ac_prev"; then
+ eval $ac_prev=\$ac_option
+ ac_prev=
+ continue
+ fi
+
+ case $ac_option in
+ *=*) ac_optarg=`expr "X$ac_option" : '[^=]*=\(.*\)'` ;;
+ *) ac_optarg=yes ;;
+ esac
+
+ # Accept the important Cygnus configure options, so we can diagnose typos.
+
+ case $ac_dashdash$ac_option in
+ --)
+ ac_dashdash=yes ;;
+
+ -bindir | --bindir | --bindi | --bind | --bin | --bi)
+ ac_prev=bindir ;;
+ -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*)
+ bindir=$ac_optarg ;;
+
+ -build | --build | --buil | --bui | --bu)
+ ac_prev=build_alias ;;
+ -build=* | --build=* | --buil=* | --bui=* | --bu=*)
+ build_alias=$ac_optarg ;;
+
+ -cache-file | --cache-file | --cache-fil | --cache-fi \
+ | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
+ ac_prev=cache_file ;;
+ -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \
+ | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*)
+ cache_file=$ac_optarg ;;
+
+ --config-cache | -C)
+ cache_file=config.cache ;;
+
+ -datadir | --datadir | --datadi | --datad)
+ ac_prev=datadir ;;
+ -datadir=* | --datadir=* | --datadi=* | --datad=*)
+ datadir=$ac_optarg ;;
+
+ -datarootdir | --datarootdir | --datarootdi | --datarootd | --dataroot \
+ | --dataroo | --dataro | --datar)
+ ac_prev=datarootdir ;;
+ -datarootdir=* | --datarootdir=* | --datarootdi=* | --datarootd=* \
+ | --dataroot=* | --dataroo=* | --dataro=* | --datar=*)
+ datarootdir=$ac_optarg ;;
+
+ -disable-* | --disable-*)
+ ac_useropt=`expr "x$ac_option" : 'x-*disable-\(.*\)'`
+ # Reject names that are not valid shell variable names.
+ expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
+ as_fn_error "invalid feature name: $ac_useropt"
+ ac_useropt_orig=$ac_useropt
+ ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
+ case $ac_user_opts in
+ *"
+"enable_$ac_useropt"
+"*) ;;
+ *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--disable-$ac_useropt_orig"
+ ac_unrecognized_sep=', ';;
+ esac
+ eval enable_$ac_useropt=no ;;
+
+ -docdir | --docdir | --docdi | --doc | --do)
+ ac_prev=docdir ;;
+ -docdir=* | --docdir=* | --docdi=* | --doc=* | --do=*)
+ docdir=$ac_optarg ;;
+
+ -dvidir | --dvidir | --dvidi | --dvid | --dvi | --dv)
+ ac_prev=dvidir ;;
+ -dvidir=* | --dvidir=* | --dvidi=* | --dvid=* | --dvi=* | --dv=*)
+ dvidir=$ac_optarg ;;
+
+ -enable-* | --enable-*)
+ ac_useropt=`expr "x$ac_option" : 'x-*enable-\([^=]*\)'`
+ # Reject names that are not valid shell variable names.
+ expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
+ as_fn_error "invalid feature name: $ac_useropt"
+ ac_useropt_orig=$ac_useropt
+ ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
+ case $ac_user_opts in
+ *"
+"enable_$ac_useropt"
+"*) ;;
+ *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--enable-$ac_useropt_orig"
+ ac_unrecognized_sep=', ';;
+ esac
+ eval enable_$ac_useropt=\$ac_optarg ;;
+
+ -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \
+ | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \
+ | --exec | --exe | --ex)
+ ac_prev=exec_prefix ;;
+ -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \
+ | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \
+ | --exec=* | --exe=* | --ex=*)
+ exec_prefix=$ac_optarg ;;
+
+ -gas | --gas | --ga | --g)
+ # Obsolete; use --with-gas.
+ with_gas=yes ;;
+
+ -help | --help | --hel | --he | -h)
+ ac_init_help=long ;;
+ -help=r* | --help=r* | --hel=r* | --he=r* | -hr*)
+ ac_init_help=recursive ;;
+ -help=s* | --help=s* | --hel=s* | --he=s* | -hs*)
+ ac_init_help=short ;;
+
+ -host | --host | --hos | --ho)
+ ac_prev=host_alias ;;
+ -host=* | --host=* | --hos=* | --ho=*)
+ host_alias=$ac_optarg ;;
+
+ -htmldir | --htmldir | --htmldi | --htmld | --html | --htm | --ht)
+ ac_prev=htmldir ;;
+ -htmldir=* | --htmldir=* | --htmldi=* | --htmld=* | --html=* | --htm=* \
+ | --ht=*)
+ htmldir=$ac_optarg ;;
+
+ -includedir | --includedir | --includedi | --included | --include \
+ | --includ | --inclu | --incl | --inc)
+ ac_prev=includedir ;;
+ -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \
+ | --includ=* | --inclu=* | --incl=* | --inc=*)
+ includedir=$ac_optarg ;;
+
+ -infodir | --infodir | --infodi | --infod | --info | --inf)
+ ac_prev=infodir ;;
+ -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*)
+ infodir=$ac_optarg ;;
+
+ -libdir | --libdir | --libdi | --libd)
+ ac_prev=libdir ;;
+ -libdir=* | --libdir=* | --libdi=* | --libd=*)
+ libdir=$ac_optarg ;;
+
+ -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \
+ | --libexe | --libex | --libe)
+ ac_prev=libexecdir ;;
+ -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \
+ | --libexe=* | --libex=* | --libe=*)
+ libexecdir=$ac_optarg ;;
+
+ -localedir | --localedir | --localedi | --localed | --locale)
+ ac_prev=localedir ;;
+ -localedir=* | --localedir=* | --localedi=* | --localed=* | --locale=*)
+ localedir=$ac_optarg ;;
+
+ -localstatedir | --localstatedir | --localstatedi | --localstated \
+ | --localstate | --localstat | --localsta | --localst | --locals)
+ ac_prev=localstatedir ;;
+ -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \
+ | --localstate=* | --localstat=* | --localsta=* | --localst=* | --locals=*)
+ localstatedir=$ac_optarg ;;
+
+ -mandir | --mandir | --mandi | --mand | --man | --ma | --m)
+ ac_prev=mandir ;;
+ -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*)
+ mandir=$ac_optarg ;;
+
+ -nfp | --nfp | --nf)
+ # Obsolete; use --without-fp.
+ with_fp=no ;;
+
+ -no-create | --no-create | --no-creat | --no-crea | --no-cre \
+ | --no-cr | --no-c | -n)
+ no_create=yes ;;
+
+ -no-recursion | --no-recursion | --no-recursio | --no-recursi \
+ | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r)
+ no_recursion=yes ;;
+
+ -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \
+ | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \
+ | --oldin | --oldi | --old | --ol | --o)
+ ac_prev=oldincludedir ;;
+ -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \
+ | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \
+ | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*)
+ oldincludedir=$ac_optarg ;;
+
+ -prefix | --prefix | --prefi | --pref | --pre | --pr | --p)
+ ac_prev=prefix ;;
+ -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*)
+ prefix=$ac_optarg ;;
+
+ -program-prefix | --program-prefix | --program-prefi | --program-pref \
+ | --program-pre | --program-pr | --program-p)
+ ac_prev=program_prefix ;;
+ -program-prefix=* | --program-prefix=* | --program-prefi=* \
+ | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*)
+ program_prefix=$ac_optarg ;;
+
+ -program-suffix | --program-suffix | --program-suffi | --program-suff \
+ | --program-suf | --program-su | --program-s)
+ ac_prev=program_suffix ;;
+ -program-suffix=* | --program-suffix=* | --program-suffi=* \
+ | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*)
+ program_suffix=$ac_optarg ;;
+
+ -program-transform-name | --program-transform-name \
+ | --program-transform-nam | --program-transform-na \
+ | --program-transform-n | --program-transform- \
+ | --program-transform | --program-transfor \
+ | --program-transfo | --program-transf \
+ | --program-trans | --program-tran \
+ | --progr-tra | --program-tr | --program-t)
+ ac_prev=program_transform_name ;;
+ -program-transform-name=* | --program-transform-name=* \
+ | --program-transform-nam=* | --program-transform-na=* \
+ | --program-transform-n=* | --program-transform-=* \
+ | --program-transform=* | --program-transfor=* \
+ | --program-transfo=* | --program-transf=* \
+ | --program-trans=* | --program-tran=* \
+ | --progr-tra=* | --program-tr=* | --program-t=*)
+ program_transform_name=$ac_optarg ;;
+
+ -pdfdir | --pdfdir | --pdfdi | --pdfd | --pdf | --pd)
+ ac_prev=pdfdir ;;
+ -pdfdir=* | --pdfdir=* | --pdfdi=* | --pdfd=* | --pdf=* | --pd=*)
+ pdfdir=$ac_optarg ;;
+
+ -psdir | --psdir | --psdi | --psd | --ps)
+ ac_prev=psdir ;;
+ -psdir=* | --psdir=* | --psdi=* | --psd=* | --ps=*)
+ psdir=$ac_optarg ;;
+
+ -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+ | -silent | --silent | --silen | --sile | --sil)
+ silent=yes ;;
+
+ -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
+ ac_prev=sbindir ;;
+ -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
+ | --sbi=* | --sb=*)
+ sbindir=$ac_optarg ;;
+
+ -sharedstatedir | --sharedstatedir | --sharedstatedi \
+ | --sharedstated | --sharedstate | --sharedstat | --sharedsta \
+ | --sharedst | --shareds | --shared | --share | --shar \
+ | --sha | --sh)
+ ac_prev=sharedstatedir ;;
+ -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \
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+ { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: accepted by the compiler, rejected by the preprocessor!" >&5
+$as_echo "$as_me: WARNING: $2: accepted by the compiler, rejected by the preprocessor!" >&2;}
+ { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: proceeding with the compiler's result" >&5
+$as_echo "$as_me: WARNING: $2: proceeding with the compiler's result" >&2;}
+ ;;
+ no:yes:* )
+ { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: present but cannot be compiled" >&5
+$as_echo "$as_me: WARNING: $2: present but cannot be compiled" >&2;}
+ { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: check for missing prerequisite headers?" >&5
+$as_echo "$as_me: WARNING: $2: check for missing prerequisite headers?" >&2;}
+ { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: see the Autoconf documentation" >&5
+$as_echo "$as_me: WARNING: $2: see the Autoconf documentation" >&2;}
+ { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: section \"Present But Cannot Be Compiled\"" >&5
+$as_echo "$as_me: WARNING: $2: section \"Present But Cannot Be Compiled\"" >&2;}
+ { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: proceeding with the compiler's result" >&5
+$as_echo "$as_me: WARNING: $2: proceeding with the compiler's result" >&2;}
+ ;;
+esac
+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5
+$as_echo_n "checking for $2... " >&6; }
+if { as_var=$3; eval "test \"\${$as_var+set}\" = set"; }; then :
+ $as_echo_n "(cached) " >&6
+else
+ eval "$3=\$ac_header_compiler"
+fi
+eval ac_res=\$$3
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+fi
+ eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;}
+
+} # ac_fn_c_check_header_mongrel
+
+# ac_fn_c_try_run LINENO
+# ----------------------
+# Try to link conftest.$ac_ext, and return whether this succeeded. Assumes
+# that executables *can* be run.
+ac_fn_c_try_run ()
+{
+ as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+ if { { ac_try="$ac_link"
+case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+ (eval "$ac_link") 2>&5
+ ac_status=$?
+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+ test $ac_status = 0; } && { ac_try='./conftest$ac_exeext'
+ { { case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+ (eval "$ac_try") 2>&5
+ ac_status=$?
+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+ test $ac_status = 0; }; }; then :
+ ac_retval=0
+else
+ $as_echo "$as_me: program exited with status $ac_status" >&5
+ $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_retval=$ac_status
+fi
+ rm -rf conftest.dSYM conftest_ipa8_conftest.oo
+ eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;}
+ return $ac_retval
+
+} # ac_fn_c_try_run
+
+# ac_fn_c_check_header_compile LINENO HEADER VAR INCLUDES
+# -------------------------------------------------------
+# Tests whether HEADER exists and can be compiled using the include files in
+# INCLUDES, setting the cache variable VAR accordingly.
+ac_fn_c_check_header_compile ()
+{
+ as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5
+$as_echo_n "checking for $2... " >&6; }
+if { as_var=$3; eval "test \"\${$as_var+set}\" = set"; }; then :
+ $as_echo_n "(cached) " >&6
+else
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+$4
+#include <$2>
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+ eval "$3=yes"
+else
+ eval "$3=no"
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+eval ac_res=\$$3
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+ eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;}
+
+} # ac_fn_c_check_header_compile
+
+# ac_fn_c_try_link LINENO
+# -----------------------
+# Try to link conftest.$ac_ext, and return whether this succeeded.
+ac_fn_c_try_link ()
+{
+ as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+ rm -f conftest.$ac_objext conftest$ac_exeext
+ if { { ac_try="$ac_link"
+case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+ (eval "$ac_link") 2>conftest.err
+ ac_status=$?
+ if test -s conftest.err; then
+ grep -v '^ *+' conftest.err >conftest.er1
+ cat conftest.er1 >&5
+ mv -f conftest.er1 conftest.err
+ fi
+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+ test $ac_status = 0; } && {
+ test -z "$ac_c_werror_flag" ||
+ test ! -s conftest.err
+ } && test -s conftest$ac_exeext && {
+ test "$cross_compiling" = yes ||
+ $as_test_x conftest$ac_exeext
+ }; then :
+ ac_retval=0
+else
+ $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_retval=1
+fi
+ # Delete the IPA/IPO (Inter Procedural Analysis/Optimization) information
+ # created by the PGI compiler (conftest_ipa8_conftest.oo), as it would
+ # interfere with the next link command; also delete a directory that is
+ # left behind by Apple's compiler. We do this before executing the actions.
+ rm -rf conftest.dSYM conftest_ipa8_conftest.oo
+ eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;}
+ return $ac_retval
+
+} # ac_fn_c_try_link
+
+# ac_fn_c_check_func LINENO FUNC VAR
+# ----------------------------------
+# Tests whether FUNC exists, setting the cache variable VAR accordingly
+ac_fn_c_check_func ()
+{
+ as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5
+$as_echo_n "checking for $2... " >&6; }
+if { as_var=$3; eval "test \"\${$as_var+set}\" = set"; }; then :
+ $as_echo_n "(cached) " >&6
+else
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+/* Define $2 to an innocuous variant, in case declares $2.
+ For example, HP-UX 11i declares gettimeofday. */
+#define $2 innocuous_$2
+
+/* System header to define __stub macros and hopefully few prototypes,
+ which can conflict with char $2 (); below.
+ Prefer to if __STDC__ is defined, since
+ exists even on freestanding compilers. */
+
+#ifdef __STDC__
+# include
+#else
+# include
+#endif
+
+#undef $2
+
+/* Override any GCC internal prototype to avoid an error.
+ Use char because int might match the return type of a GCC
+ builtin and then its argument prototype would still apply. */
+#ifdef __cplusplus
+extern "C"
+#endif
+char $2 ();
+/* The GNU C library defines this for functions which it implements
+ to always fail with ENOSYS. Some functions are actually named
+ something starting with __ and the normal name is an alias. */
+#if defined __stub_$2 || defined __stub___$2
+choke me
+#endif
+
+int
+main ()
+{
+return $2 ();
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_link "$LINENO"; then :
+ eval "$3=yes"
+else
+ eval "$3=no"
+fi
+rm -f core conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+fi
+eval ac_res=\$$3
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+ eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;}
+
+} # ac_fn_c_check_func
+cat >config.log <<_ACEOF
+This file contains any messages produced by compilers while
+running configure, to aid debugging if configure makes a mistake.
+
+It was created by $as_me, which was
+generated by GNU Autoconf 2.64. Invocation command line was
+
+ $ $0 $@
+
+_ACEOF
+exec 5>>config.log
+{
+cat <<_ASUNAME
+## --------- ##
+## Platform. ##
+## --------- ##
+
+hostname = `(hostname || uname -n) 2>/dev/null | sed 1q`
+uname -m = `(uname -m) 2>/dev/null || echo unknown`
+uname -r = `(uname -r) 2>/dev/null || echo unknown`
+uname -s = `(uname -s) 2>/dev/null || echo unknown`
+uname -v = `(uname -v) 2>/dev/null || echo unknown`
+
+/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null || echo unknown`
+/bin/uname -X = `(/bin/uname -X) 2>/dev/null || echo unknown`
+
+/bin/arch = `(/bin/arch) 2>/dev/null || echo unknown`
+/usr/bin/arch -k = `(/usr/bin/arch -k) 2>/dev/null || echo unknown`
+/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null || echo unknown`
+/usr/bin/hostinfo = `(/usr/bin/hostinfo) 2>/dev/null || echo unknown`
+/bin/machine = `(/bin/machine) 2>/dev/null || echo unknown`
+/usr/bin/oslevel = `(/usr/bin/oslevel) 2>/dev/null || echo unknown`
+/bin/universe = `(/bin/universe) 2>/dev/null || echo unknown`
+
+_ASUNAME
+
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ $as_echo "PATH: $as_dir"
+ done
+IFS=$as_save_IFS
+
+} >&5
+
+cat >&5 <<_ACEOF
+
+
+## ----------- ##
+## Core tests. ##
+## ----------- ##
+
+_ACEOF
+
+
+# Keep a trace of the command line.
+# Strip out --no-create and --no-recursion so they do not pile up.
+# Strip out --silent because we don't want to record it for future runs.
+# Also quote any args containing shell meta-characters.
+# Make two passes to allow for proper duplicate-argument suppression.
+ac_configure_args=
+ac_configure_args0=
+ac_configure_args1=
+ac_must_keep_next=false
+for ac_pass in 1 2
+do
+ for ac_arg
+ do
+ case $ac_arg in
+ -no-create | --no-c* | -n | -no-recursion | --no-r*) continue ;;
+ -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+ | -silent | --silent | --silen | --sile | --sil)
+ continue ;;
+ *\'*)
+ ac_arg=`$as_echo "$ac_arg" | sed "s/'/'\\\\\\\\''/g"` ;;
+ esac
+ case $ac_pass in
+ 1) as_fn_append ac_configure_args0 " '$ac_arg'" ;;
+ 2)
+ as_fn_append ac_configure_args1 " '$ac_arg'"
+ if test $ac_must_keep_next = true; then
+ ac_must_keep_next=false # Got value, back to normal.
+ else
+ case $ac_arg in
+ *=* | --config-cache | -C | -disable-* | --disable-* \
+ | -enable-* | --enable-* | -gas | --g* | -nfp | --nf* \
+ | -q | -quiet | --q* | -silent | --sil* | -v | -verb* \
+ | -with-* | --with-* | -without-* | --without-* | --x)
+ case "$ac_configure_args0 " in
+ "$ac_configure_args1"*" '$ac_arg' "* ) continue ;;
+ esac
+ ;;
+ -* ) ac_must_keep_next=true ;;
+ esac
+ fi
+ as_fn_append ac_configure_args " '$ac_arg'"
+ ;;
+ esac
+ done
+done
+{ ac_configure_args0=; unset ac_configure_args0;}
+{ ac_configure_args1=; unset ac_configure_args1;}
+
+# When interrupted or exit'd, cleanup temporary files, and complete
+# config.log. We remove comments because anyway the quotes in there
+# would cause problems or look ugly.
+# WARNING: Use '\'' to represent an apostrophe within the trap.
+# WARNING: Do not start the trap code with a newline, due to a FreeBSD 4.0 bug.
+trap 'exit_status=$?
+ # Save into config.log some information that might help in debugging.
+ {
+ echo
+
+ cat <<\_ASBOX
+## ---------------- ##
+## Cache variables. ##
+## ---------------- ##
+_ASBOX
+ echo
+ # The following way of writing the cache mishandles newlines in values,
+(
+ for ac_var in `(set) 2>&1 | sed -n '\''s/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'\''`; do
+ eval ac_val=\$$ac_var
+ case $ac_val in #(
+ *${as_nl}*)
+ case $ac_var in #(
+ *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5
+$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;;
+ esac
+ case $ac_var in #(
+ _ | IFS | as_nl) ;; #(
+ BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #(
+ *) { eval $ac_var=; unset $ac_var;} ;;
+ esac ;;
+ esac
+ done
+ (set) 2>&1 |
+ case $as_nl`(ac_space='\'' '\''; set) 2>&1` in #(
+ *${as_nl}ac_space=\ *)
+ sed -n \
+ "s/'\''/'\''\\\\'\'''\''/g;
+ s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\''\\2'\''/p"
+ ;; #(
+ *)
+ sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p"
+ ;;
+ esac |
+ sort
+)
+ echo
+
+ cat <<\_ASBOX
+## ----------------- ##
+## Output variables. ##
+## ----------------- ##
+_ASBOX
+ echo
+ for ac_var in $ac_subst_vars
+ do
+ eval ac_val=\$$ac_var
+ case $ac_val in
+ *\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;;
+ esac
+ $as_echo "$ac_var='\''$ac_val'\''"
+ done | sort
+ echo
+
+ if test -n "$ac_subst_files"; then
+ cat <<\_ASBOX
+## ------------------- ##
+## File substitutions. ##
+## ------------------- ##
+_ASBOX
+ echo
+ for ac_var in $ac_subst_files
+ do
+ eval ac_val=\$$ac_var
+ case $ac_val in
+ *\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;;
+ esac
+ $as_echo "$ac_var='\''$ac_val'\''"
+ done | sort
+ echo
+ fi
+
+ if test -s confdefs.h; then
+ cat <<\_ASBOX
+## ----------- ##
+## confdefs.h. ##
+## ----------- ##
+_ASBOX
+ echo
+ cat confdefs.h
+ echo
+ fi
+ test "$ac_signal" != 0 &&
+ $as_echo "$as_me: caught signal $ac_signal"
+ $as_echo "$as_me: exit $exit_status"
+ } >&5
+ rm -f core *.core core.conftest.* &&
+ rm -f -r conftest* confdefs* conf$$* $ac_clean_files &&
+ exit $exit_status
+' 0
+for ac_signal in 1 2 13 15; do
+ trap 'ac_signal='$ac_signal'; as_fn_exit 1' $ac_signal
+done
+ac_signal=0
+
+# confdefs.h avoids OS command line length limits that DEFS can exceed.
+rm -f -r conftest* confdefs.h
+
+$as_echo "/* confdefs.h */" > confdefs.h
+
+# Predefined preprocessor variables.
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_NAME "$PACKAGE_NAME"
+_ACEOF
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_TARNAME "$PACKAGE_TARNAME"
+_ACEOF
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_VERSION "$PACKAGE_VERSION"
+_ACEOF
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_STRING "$PACKAGE_STRING"
+_ACEOF
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_BUGREPORT "$PACKAGE_BUGREPORT"
+_ACEOF
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_URL "$PACKAGE_URL"
+_ACEOF
+
+
+# Let the site file select an alternate cache file if it wants to.
+# Prefer an explicitly selected file to automatically selected ones.
+ac_site_file1=NONE
+ac_site_file2=NONE
+if test -n "$CONFIG_SITE"; then
+ ac_site_file1=$CONFIG_SITE
+elif test "x$prefix" != xNONE; then
+ ac_site_file1=$prefix/share/config.site
+ ac_site_file2=$prefix/etc/config.site
+else
+ ac_site_file1=$ac_default_prefix/share/config.site
+ ac_site_file2=$ac_default_prefix/etc/config.site
+fi
+for ac_site_file in "$ac_site_file1" "$ac_site_file2"
+do
+ test "x$ac_site_file" = xNONE && continue
+ if test -r "$ac_site_file"; then
+ { $as_echo "$as_me:${as_lineno-$LINENO}: loading site script $ac_site_file" >&5
+$as_echo "$as_me: loading site script $ac_site_file" >&6;}
+ sed 's/^/| /' "$ac_site_file" >&5
+ . "$ac_site_file"
+ fi
+done
+
+if test -r "$cache_file"; then
+ # Some versions of bash will fail to source /dev/null (special
+ # files actually), so we avoid doing that.
+ if test -f "$cache_file"; then
+ { $as_echo "$as_me:${as_lineno-$LINENO}: loading cache $cache_file" >&5
+$as_echo "$as_me: loading cache $cache_file" >&6;}
+ case $cache_file in
+ [\\/]* | ?:[\\/]* ) . "$cache_file";;
+ *) . "./$cache_file";;
+ esac
+ fi
+else
+ { $as_echo "$as_me:${as_lineno-$LINENO}: creating cache $cache_file" >&5
+$as_echo "$as_me: creating cache $cache_file" >&6;}
+ >$cache_file
+fi
+
+# Check that the precious variables saved in the cache have kept the same
+# value.
+ac_cache_corrupted=false
+for ac_var in $ac_precious_vars; do
+ eval ac_old_set=\$ac_cv_env_${ac_var}_set
+ eval ac_new_set=\$ac_env_${ac_var}_set
+ eval ac_old_val=\$ac_cv_env_${ac_var}_value
+ eval ac_new_val=\$ac_env_${ac_var}_value
+ case $ac_old_set,$ac_new_set in
+ set,)
+ { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&5
+$as_echo "$as_me: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&2;}
+ ac_cache_corrupted=: ;;
+ ,set)
+ { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was not set in the previous run" >&5
+$as_echo "$as_me: error: \`$ac_var' was not set in the previous run" >&2;}
+ ac_cache_corrupted=: ;;
+ ,);;
+ *)
+ if test "x$ac_old_val" != "x$ac_new_val"; then
+ # differences in whitespace do not lead to failure.
+ ac_old_val_w=`echo x $ac_old_val`
+ ac_new_val_w=`echo x $ac_new_val`
+ if test "$ac_old_val_w" != "$ac_new_val_w"; then
+ { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' has changed since the previous run:" >&5
+$as_echo "$as_me: error: \`$ac_var' has changed since the previous run:" >&2;}
+ ac_cache_corrupted=:
+ else
+ { $as_echo "$as_me:${as_lineno-$LINENO}: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&5
+$as_echo "$as_me: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&2;}
+ eval $ac_var=\$ac_old_val
+ fi
+ { $as_echo "$as_me:${as_lineno-$LINENO}: former value: \`$ac_old_val'" >&5
+$as_echo "$as_me: former value: \`$ac_old_val'" >&2;}
+ { $as_echo "$as_me:${as_lineno-$LINENO}: current value: \`$ac_new_val'" >&5
+$as_echo "$as_me: current value: \`$ac_new_val'" >&2;}
+ fi;;
+ esac
+ # Pass precious variables to config.status.
+ if test "$ac_new_set" = set; then
+ case $ac_new_val in
+ *\'*) ac_arg=$ac_var=`$as_echo "$ac_new_val" | sed "s/'/'\\\\\\\\''/g"` ;;
+ *) ac_arg=$ac_var=$ac_new_val ;;
+ esac
+ case " $ac_configure_args " in
+ *" '$ac_arg' "*) ;; # Avoid dups. Use of quotes ensures accuracy.
+ *) as_fn_append ac_configure_args " '$ac_arg'" ;;
+ esac
+ fi
+done
+if $ac_cache_corrupted; then
+ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+ { $as_echo "$as_me:${as_lineno-$LINENO}: error: changes in the environment can compromise the build" >&5
+$as_echo "$as_me: error: changes in the environment can compromise the build" >&2;}
+ as_fn_error "run \`make distclean' and/or \`rm $cache_file' and start over" "$LINENO" 5
+fi
+## -------------------- ##
+## Main body of script. ##
+## -------------------- ##
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+
+ac_config_headers="$ac_config_headers config.h:config.in"
+
+
+# This file contains common code used by all simulators.
+#
+# SIM_AC_COMMON invokes AC macros used by all simulators and by the common
+# directory. It is intended to be invoked before any target specific stuff.
+# SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate the Makefile.
+# It is intended to be invoked last.
+#
+# The simulator's configure.in should look like:
+#
+# dnl Process this file with autoconf to produce a configure script.
+# sinclude(../common/aclocal.m4)
+# AC_PREREQ(2.5)dnl
+# AC_INIT(Makefile.in)
+#
+# SIM_AC_COMMON
+#
+# ... target specific stuff ...
+#
+# SIM_AC_OUTPUT
+
+# Include global overrides and fixes for Autoconf.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+sim_inline="-DDEFAULT_INLINE=0"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+# intl sister-directory configuration rules.
+#
+
+# The idea behind this macro is that there's no need to repeat all the
+# autoconf probes done by the intl directory - it's already done them
+# for us. In fact, there's no need even to look at the cache for the
+# answers. All we need to do is nab a few pieces of information.
+# The intl directory is set up to make this easy, by generating a
+# small file which can be sourced as a shell script; then we produce
+# the necessary substitutions and definitions for this directory.
+
+
+
+# Autoconf M4 include file defining utility macros for complex Canadian
+# cross builds.
+
+
+
+
+
+
+
+
+
+####
+# _NCN_TOOL_PREFIXES: Some stuff that oughtta be done in AC_CANONICAL_SYSTEM
+# or AC_INIT.
+# These demand that AC_CANONICAL_SYSTEM be called beforehand.
+
+####
+# NCN_STRICT_CHECK_TOOLS(variable, progs-to-check-for,[value-if-not-found],[path])
+# Like plain AC_CHECK_TOOLS, but require prefix if build!=host.
+
+
+####
+# NCN_STRICT_CHECK_TARGET_TOOLS(variable, progs-to-check-for,[value-if-not-found],[path])
+# Like CVS Autoconf AC_CHECK_TARGET_TOOLS, but require prefix if build!=target.
+
+
+
+# Backported from Autoconf 2.5x; can go away when and if
+# we switch. Put the OS path separator in $PATH_SEPARATOR.
+
+
+
+
+# ACX_HAVE_GCC_FOR_TARGET
+# Check if the variable GCC_FOR_TARGET really points to a GCC binary.
+
+
+# ACX_CHECK_INSTALLED_TARGET_TOOL(VAR, PROG)
+# Searching for installed target binutils. We need to take extra care,
+# else we may find the wrong assembler, linker, etc., and lose.
+#
+# First try --with-build-time-tools, if specified.
+#
+# For build != host, we ask the installed GCC for the name of the tool it
+# uses, and accept it if it is an absolute path. This is because the
+# only good choice for a compiler is the same GCC version that is being
+# installed (or we couldn't make target libraries), and we assume that
+# on the host system we'll have not only the same GCC version, but also
+# the same binutils version.
+#
+# For build == host, search the same directories that the installed
+# compiler will search. We used to do this for the assembler, linker,
+# and nm only; for simplicity of configuration, however, we extend this
+# criterion to tools (such as ar and ranlib) that are never invoked by
+# the compiler, to avoid mismatches.
+#
+# Also note we have to check MD_EXEC_PREFIX before checking the user's path
+# if build == target. This makes the most sense only when bootstrapping,
+# but we also do so when build != host. In this case, we hope that the
+# build and host systems will have similar contents of MD_EXEC_PREFIX.
+#
+# If we do not find a suitable binary, then try the user's path.
+
+
+###
+# AC_PROG_CPP_WERROR
+# Used for autoconf 2.5x to force AC_PREPROC_IFELSE to reject code which
+# triggers warnings from the preprocessor. Will be in autoconf 2.58.
+# For now, using this also overrides header checks to use only the
+# preprocessor (matches 2.13 behavior; matching 2.58's behavior is a
+# bit harder from here).
+# Eventually autoconf will default to checking headers with the compiler
+# instead, and we'll have to do this differently.
+
+# AC_PROG_CPP_WERROR
+
+# Test for GNAT.
+# We require the gnatbind program, and a compiler driver that
+# understands Ada. We use the user's CC setting, already found,
+# and possibly add $1 to the command-line parameters.
+#
+# Sets the shell variable have_gnat to yes or no as appropriate, and
+# substitutes GNATBIND and GNATMAKE.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around
+# it by inlining the macro's contents.
+# This file contains common code used by all simulators.
+#
+# common.m4 invokes AC macros used by all simulators and by the common
+# directory. It is intended to be included before any target specific
+# stuff. SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate
+# the Makefile. It is intended to be invoked last.
+#
+# The simulator's configure.in should look like:
+#
+# dnl Process this file with autoconf to produce a configure script.
+# AC_PREREQ(2.5)dnl
+# AC_INIT(Makefile.in)
+# AC_CONFIG_HEADER(config.h:config.in)
+#
+# sinclude(../common/aclocal.m4)
+# sinclude(../common/common.m4)
+#
+# ... target specific stuff ...
+
+ac_aux_dir=
+for ac_dir in "$srcdir" "$srcdir/.." "$srcdir/../.."; do
+ for ac_t in install-sh install.sh shtool; do
+ if test -f "$ac_dir/$ac_t"; then
+ ac_aux_dir=$ac_dir
+ ac_install_sh="$ac_aux_dir/$ac_t -c"
+ break 2
+ fi
+ done
+done
+if test -z "$ac_aux_dir"; then
+ as_fn_error "cannot find install-sh, install.sh, or shtool in \"$srcdir\" \"$srcdir/..\" \"$srcdir/../..\"" "$LINENO" 5
+fi
+
+# These three variables are undocumented and unsupported,
+# and are intended to be withdrawn in a future Autoconf release.
+# They can cause serious problems if a builder's source tree is in a directory
+# whose full name contains unusual characters.
+ac_config_guess="$SHELL $ac_aux_dir/config.guess" # Please don't use this var.
+ac_config_sub="$SHELL $ac_aux_dir/config.sub" # Please don't use this var.
+ac_configure="$SHELL $ac_aux_dir/configure" # Please don't use this var.
+
+
+# Make sure we can run config.sub.
+$SHELL "$ac_aux_dir/config.sub" sun4 >/dev/null 2>&1 ||
+ as_fn_error "cannot run $SHELL $ac_aux_dir/config.sub" "$LINENO" 5
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking build system type" >&5
+$as_echo_n "checking build system type... " >&6; }
+if test "${ac_cv_build+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ ac_build_alias=$build_alias
+test "x$ac_build_alias" = x &&
+ ac_build_alias=`$SHELL "$ac_aux_dir/config.guess"`
+test "x$ac_build_alias" = x &&
+ as_fn_error "cannot guess build type; you must specify one" "$LINENO" 5
+ac_cv_build=`$SHELL "$ac_aux_dir/config.sub" $ac_build_alias` ||
+ as_fn_error "$SHELL $ac_aux_dir/config.sub $ac_build_alias failed" "$LINENO" 5
+
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_build" >&5
+$as_echo "$ac_cv_build" >&6; }
+case $ac_cv_build in
+*-*-*) ;;
+*) as_fn_error "invalid value of canonical build" "$LINENO" 5;;
+esac
+build=$ac_cv_build
+ac_save_IFS=$IFS; IFS='-'
+set x $ac_cv_build
+shift
+build_cpu=$1
+build_vendor=$2
+shift; shift
+# Remember, the first character of IFS is used to create $*,
+# except with old shells:
+build_os=$*
+IFS=$ac_save_IFS
+case $build_os in *\ *) build_os=`echo "$build_os" | sed 's/ /-/g'`;; esac
+
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking host system type" >&5
+$as_echo_n "checking host system type... " >&6; }
+if test "${ac_cv_host+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ if test "x$host_alias" = x; then
+ ac_cv_host=$ac_cv_build
+else
+ ac_cv_host=`$SHELL "$ac_aux_dir/config.sub" $host_alias` ||
+ as_fn_error "$SHELL $ac_aux_dir/config.sub $host_alias failed" "$LINENO" 5
+fi
+
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_host" >&5
+$as_echo "$ac_cv_host" >&6; }
+case $ac_cv_host in
+*-*-*) ;;
+*) as_fn_error "invalid value of canonical host" "$LINENO" 5;;
+esac
+host=$ac_cv_host
+ac_save_IFS=$IFS; IFS='-'
+set x $ac_cv_host
+shift
+host_cpu=$1
+host_vendor=$2
+shift; shift
+# Remember, the first character of IFS is used to create $*,
+# except with old shells:
+host_os=$*
+IFS=$ac_save_IFS
+case $host_os in *\ *) host_os=`echo "$host_os" | sed 's/ /-/g'`;; esac
+
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking target system type" >&5
+$as_echo_n "checking target system type... " >&6; }
+if test "${ac_cv_target+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ if test "x$target_alias" = x; then
+ ac_cv_target=$ac_cv_host
+else
+ ac_cv_target=`$SHELL "$ac_aux_dir/config.sub" $target_alias` ||
+ as_fn_error "$SHELL $ac_aux_dir/config.sub $target_alias failed" "$LINENO" 5
+fi
+
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_target" >&5
+$as_echo "$ac_cv_target" >&6; }
+case $ac_cv_target in
+*-*-*) ;;
+*) as_fn_error "invalid value of canonical target" "$LINENO" 5;;
+esac
+target=$ac_cv_target
+ac_save_IFS=$IFS; IFS='-'
+set x $ac_cv_target
+shift
+target_cpu=$1
+target_vendor=$2
+shift; shift
+# Remember, the first character of IFS is used to create $*,
+# except with old shells:
+target_os=$*
+IFS=$ac_save_IFS
+case $target_os in *\ *) target_os=`echo "$target_os" | sed 's/ /-/g'`;; esac
+
+
+# The aliases save the names the user supplied, while $host etc.
+# will get canonicalized.
+test -n "$target_alias" &&
+ test "$program_prefix$program_suffix$program_transform_name" = \
+ NONENONEs,x,x, &&
+ program_prefix=${target_alias}-
+
+test "$program_prefix" != NONE &&
+ program_transform_name="s&^&$program_prefix&;$program_transform_name"
+# Use a double $ so make ignores it.
+test "$program_suffix" != NONE &&
+ program_transform_name="s&\$&$program_suffix&;$program_transform_name"
+# Double any \ or $.
+# By default was `s,x,x', remove it if useless.
+ac_script='s/[\\$]/&&/g;s/;s,x,x,$//'
+program_transform_name=`$as_echo "$program_transform_name" | sed "$ac_script"`
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+if test -n "$ac_tool_prefix"; then
+ # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args.
+set dummy ${ac_tool_prefix}gcc; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if test "${ac_cv_prog_CC+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then
+ ac_cv_prog_CC="${ac_tool_prefix}gcc"
+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+ done
+IFS=$as_save_IFS
+
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5
+$as_echo "$CC" >&6; }
+else
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+fi
+if test -z "$ac_cv_prog_CC"; then
+ ac_ct_CC=$CC
+ # Extract the first word of "gcc", so it can be a program name with args.
+set dummy gcc; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if test "${ac_cv_prog_ac_ct_CC+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ if test -n "$ac_ct_CC"; then
+ ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then
+ ac_cv_prog_ac_ct_CC="gcc"
+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+ done
+IFS=$as_save_IFS
+
+fi
+fi
+ac_ct_CC=$ac_cv_prog_ac_ct_CC
+if test -n "$ac_ct_CC"; then
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5
+$as_echo "$ac_ct_CC" >&6; }
+else
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+ if test "x$ac_ct_CC" = x; then
+ CC=""
+ else
+ case $cross_compiling:$ac_tool_warned in
+yes:)
+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
+ac_tool_warned=yes ;;
+esac
+ CC=$ac_ct_CC
+ fi
+else
+ CC="$ac_cv_prog_CC"
+fi
+
+if test -z "$CC"; then
+ if test -n "$ac_tool_prefix"; then
+ # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args.
+set dummy ${ac_tool_prefix}cc; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if test "${ac_cv_prog_CC+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then
+ ac_cv_prog_CC="${ac_tool_prefix}cc"
+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+ done
+IFS=$as_save_IFS
+
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5
+$as_echo "$CC" >&6; }
+else
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+ fi
+fi
+if test -z "$CC"; then
+ # Extract the first word of "cc", so it can be a program name with args.
+set dummy cc; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if test "${ac_cv_prog_CC+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+ ac_prog_rejected=no
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then
+ if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then
+ ac_prog_rejected=yes
+ continue
+ fi
+ ac_cv_prog_CC="cc"
+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+ done
+IFS=$as_save_IFS
+
+if test $ac_prog_rejected = yes; then
+ # We found a bogon in the path, so make sure we never use it.
+ set dummy $ac_cv_prog_CC
+ shift
+ if test $# != 0; then
+ # We chose a different compiler from the bogus one.
+ # However, it has the same basename, so the bogon will be chosen
+ # first if we set CC to just the basename; use the full file name.
+ shift
+ ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@"
+ fi
+fi
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5
+$as_echo "$CC" >&6; }
+else
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+fi
+if test -z "$CC"; then
+ if test -n "$ac_tool_prefix"; then
+ for ac_prog in cl.exe
+ do
+ # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args.
+set dummy $ac_tool_prefix$ac_prog; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if test "${ac_cv_prog_CC+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then
+ ac_cv_prog_CC="$ac_tool_prefix$ac_prog"
+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+ done
+IFS=$as_save_IFS
+
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5
+$as_echo "$CC" >&6; }
+else
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+ test -n "$CC" && break
+ done
+fi
+if test -z "$CC"; then
+ ac_ct_CC=$CC
+ for ac_prog in cl.exe
+do
+ # Extract the first word of "$ac_prog", so it can be a program name with args.
+set dummy $ac_prog; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if test "${ac_cv_prog_ac_ct_CC+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ if test -n "$ac_ct_CC"; then
+ ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then
+ ac_cv_prog_ac_ct_CC="$ac_prog"
+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+ done
+IFS=$as_save_IFS
+
+fi
+fi
+ac_ct_CC=$ac_cv_prog_ac_ct_CC
+if test -n "$ac_ct_CC"; then
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5
+$as_echo "$ac_ct_CC" >&6; }
+else
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+ test -n "$ac_ct_CC" && break
+done
+
+ if test "x$ac_ct_CC" = x; then
+ CC=""
+ else
+ case $cross_compiling:$ac_tool_warned in
+yes:)
+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
+ac_tool_warned=yes ;;
+esac
+ CC=$ac_ct_CC
+ fi
+fi
+
+fi
+
+
+test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error "no acceptable C compiler found in \$PATH
+See \`config.log' for more details." "$LINENO" 5; }
+
+# Provide some information about the compiler.
+$as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5
+set X $ac_compile
+ac_compiler=$2
+for ac_option in --version -v -V -qversion; do
+ { { ac_try="$ac_compiler $ac_option >&5"
+case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+ (eval "$ac_compiler $ac_option >&5") 2>conftest.err
+ ac_status=$?
+ if test -s conftest.err; then
+ sed '10a\
+... rest of stderr output deleted ...
+ 10q' conftest.err >conftest.er1
+ cat conftest.er1 >&5
+ rm -f conftest.er1 conftest.err
+ fi
+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+ test $ac_status = 0; }
+done
+
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ ;
+ return 0;
+}
+_ACEOF
+ac_clean_files_save=$ac_clean_files
+ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out conftest.out"
+# Try to create an executable without -o first, disregard a.out.
+# It will help us diagnose broken compilers, and finding out an intuition
+# of exeext.
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler default output file name" >&5
+$as_echo_n "checking for C compiler default output file name... " >&6; }
+ac_link_default=`$as_echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'`
+
+# The possible output files:
+ac_files="a.out conftest.exe conftest a.exe a_out.exe b.out conftest.*"
+
+ac_rmfiles=
+for ac_file in $ac_files
+do
+ case $ac_file in
+ *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;;
+ * ) ac_rmfiles="$ac_rmfiles $ac_file";;
+ esac
+done
+rm -f $ac_rmfiles
+
+if { { ac_try="$ac_link_default"
+case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+ (eval "$ac_link_default") 2>&5
+ ac_status=$?
+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+ test $ac_status = 0; }; then :
+ # Autoconf-2.13 could set the ac_cv_exeext variable to `no'.
+# So ignore a value of `no', otherwise this would lead to `EXEEXT = no'
+# in a Makefile. We should not override ac_cv_exeext if it was cached,
+# so that the user can short-circuit this test for compilers unknown to
+# Autoconf.
+for ac_file in $ac_files ''
+do
+ test -f "$ac_file" || continue
+ case $ac_file in
+ *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj )
+ ;;
+ [ab].out )
+ # We found the default executable, but exeext='' is most
+ # certainly right.
+ break;;
+ *.* )
+ if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no;
+ then :; else
+ ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
+ fi
+ # We set ac_cv_exeext here because the later test for it is not
+ # safe: cross compilers may not add the suffix if given an `-o'
+ # argument, so we may need to know it at that point already.
+ # Even if this section looks crufty: it has the advantage of
+ # actually working.
+ break;;
+ * )
+ break;;
+ esac
+done
+test "$ac_cv_exeext" = no && ac_cv_exeext=
+
+else
+ ac_file=''
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_file" >&5
+$as_echo "$ac_file" >&6; }
+if test -z "$ac_file"; then :
+ $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+{ as_fn_set_status 77
+as_fn_error "C compiler cannot create executables
+See \`config.log' for more details." "$LINENO" 5; }; }
+fi
+ac_exeext=$ac_cv_exeext
+
+# Check that the compiler produces executables we can run. If not, either
+# the compiler is broken, or we cross compile.
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler works" >&5
+$as_echo_n "checking whether the C compiler works... " >&6; }
+# If not cross compiling, check that we can run a simple program.
+if test "$cross_compiling" != yes; then
+ if { ac_try='./$ac_file'
+ { { case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+ (eval "$ac_try") 2>&5
+ ac_status=$?
+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+ test $ac_status = 0; }; }; then
+ cross_compiling=no
+ else
+ if test "$cross_compiling" = maybe; then
+ cross_compiling=yes
+ else
+ { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error "cannot run C compiled programs.
+If you meant to cross compile, use \`--host'.
+See \`config.log' for more details." "$LINENO" 5; }
+ fi
+ fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
+
+rm -f -r a.out a.out.dSYM a.exe conftest$ac_cv_exeext b.out conftest.out
+ac_clean_files=$ac_clean_files_save
+# Check that the compiler produces executables we can run. If not, either
+# the compiler is broken, or we cross compile.
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5
+$as_echo_n "checking whether we are cross compiling... " >&6; }
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5
+$as_echo "$cross_compiling" >&6; }
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of executables" >&5
+$as_echo_n "checking for suffix of executables... " >&6; }
+if { { ac_try="$ac_link"
+case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+ (eval "$ac_link") 2>&5
+ ac_status=$?
+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+ test $ac_status = 0; }; then :
+ # If both `conftest.exe' and `conftest' are `present' (well, observable)
+# catch `conftest.exe'. For instance with Cygwin, `ls conftest' will
+# work properly (i.e., refer to `conftest.exe'), while it won't with
+# `rm'.
+for ac_file in conftest.exe conftest conftest.*; do
+ test -f "$ac_file" || continue
+ case $ac_file in
+ *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;;
+ *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
+ break;;
+ * ) break;;
+ esac
+done
+else
+ { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error "cannot compute suffix of executables: cannot compile and link
+See \`config.log' for more details." "$LINENO" 5; }
+fi
+rm -f conftest$ac_cv_exeext
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5
+$as_echo "$ac_cv_exeext" >&6; }
+
+rm -f conftest.$ac_ext
+EXEEXT=$ac_cv_exeext
+ac_exeext=$EXEEXT
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of object files" >&5
+$as_echo_n "checking for suffix of object files... " >&6; }
+if test "${ac_cv_objext+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.o conftest.obj
+if { { ac_try="$ac_compile"
+case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+ (eval "$ac_compile") 2>&5
+ ac_status=$?
+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+ test $ac_status = 0; }; then :
+ for ac_file in conftest.o conftest.obj conftest.*; do
+ test -f "$ac_file" || continue;
+ case $ac_file in
+ *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM ) ;;
+ *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'`
+ break;;
+ esac
+done
+else
+ $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error "cannot compute suffix of object files: cannot compile
+See \`config.log' for more details." "$LINENO" 5; }
+fi
+rm -f conftest.$ac_cv_objext conftest.$ac_ext
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_objext" >&5
+$as_echo "$ac_cv_objext" >&6; }
+OBJEXT=$ac_cv_objext
+ac_objext=$OBJEXT
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5
+$as_echo_n "checking whether we are using the GNU C compiler... " >&6; }
+if test "${ac_cv_c_compiler_gnu+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+
+int
+main ()
+{
+#ifndef __GNUC__
+ choke me
+#endif
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+ ac_compiler_gnu=yes
+else
+ ac_compiler_gnu=no
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+ac_cv_c_compiler_gnu=$ac_compiler_gnu
+
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5
+$as_echo "$ac_cv_c_compiler_gnu" >&6; }
+if test $ac_compiler_gnu = yes; then
+ GCC=yes
+else
+ GCC=
+fi
+ac_test_CFLAGS=${CFLAGS+set}
+ac_save_CFLAGS=$CFLAGS
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5
+$as_echo_n "checking whether $CC accepts -g... " >&6; }
+if test "${ac_cv_prog_cc_g+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ ac_save_c_werror_flag=$ac_c_werror_flag
+ ac_c_werror_flag=yes
+ ac_cv_prog_cc_g=no
+ CFLAGS="-g"
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+ ac_cv_prog_cc_g=yes
+else
+ CFLAGS=""
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+
+else
+ ac_c_werror_flag=$ac_save_c_werror_flag
+ CFLAGS="-g"
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+ ac_cv_prog_cc_g=yes
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+ ac_c_werror_flag=$ac_save_c_werror_flag
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5
+$as_echo "$ac_cv_prog_cc_g" >&6; }
+if test "$ac_test_CFLAGS" = set; then
+ CFLAGS=$ac_save_CFLAGS
+elif test $ac_cv_prog_cc_g = yes; then
+ if test "$GCC" = yes; then
+ CFLAGS="-g -O2"
+ else
+ CFLAGS="-g"
+ fi
+else
+ if test "$GCC" = yes; then
+ CFLAGS="-O2"
+ else
+ CFLAGS=
+ fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5
+$as_echo_n "checking for $CC option to accept ISO C89... " >&6; }
+if test "${ac_cv_prog_cc_c89+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ ac_cv_prog_cc_c89=no
+ac_save_CC=$CC
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+#include
+#include
+#include
+#include
+/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */
+struct buf { int x; };
+FILE * (*rcsopen) (struct buf *, struct stat *, int);
+static char *e (p, i)
+ char **p;
+ int i;
+{
+ return p[i];
+}
+static char *f (char * (*g) (char **, int), char **p, ...)
+{
+ char *s;
+ va_list v;
+ va_start (v,p);
+ s = g (p, va_arg (v,int));
+ va_end (v);
+ return s;
+}
+
+/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has
+ function prototypes and stuff, but not '\xHH' hex character constants.
+ These don't provoke an error unfortunately, instead are silently treated
+ as 'x'. The following induces an error, until -std is added to get
+ proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an
+ array size at least. It's necessary to write '\x00'==0 to get something
+ that's true only with -std. */
+int osf4_cc_array ['\x00' == 0 ? 1 : -1];
+
+/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters
+ inside strings and character constants. */
+#define FOO(x) 'x'
+int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1];
+
+int test (int i, double x);
+struct s1 {int (*f) (int a);};
+struct s2 {int (*f) (double a);};
+int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int);
+int argc;
+char **argv;
+int
+main ()
+{
+return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1];
+ ;
+ return 0;
+}
+_ACEOF
+for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \
+ -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__"
+do
+ CC="$ac_save_CC $ac_arg"
+ if ac_fn_c_try_compile "$LINENO"; then :
+ ac_cv_prog_cc_c89=$ac_arg
+fi
+rm -f core conftest.err conftest.$ac_objext
+ test "x$ac_cv_prog_cc_c89" != "xno" && break
+done
+rm -f conftest.$ac_ext
+CC=$ac_save_CC
+
+fi
+# AC_CACHE_VAL
+case "x$ac_cv_prog_cc_c89" in
+ x)
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5
+$as_echo "none needed" >&6; } ;;
+ xno)
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5
+$as_echo "unsupported" >&6; } ;;
+ *)
+ CC="$CC $ac_cv_prog_cc_c89"
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5
+$as_echo "$ac_cv_prog_cc_c89" >&6; } ;;
+esac
+if test "x$ac_cv_prog_cc_c89" != xno; then :
+
+fi
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+# Find a good install program. We prefer a C program (faster),
+# so one script is as good as another. But avoid the broken or
+# incompatible versions:
+# SysV /etc/install, /usr/sbin/install
+# SunOS /usr/etc/install
+# IRIX /sbin/install
+# AIX /bin/install
+# AmigaOS /C/install, which installs bootblocks on floppy discs
+# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag
+# AFS /usr/afsws/bin/install, which mishandles nonexistent args
+# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
+# OS/2's system install, which has a completely different semantic
+# ./install, which can be erroneously created by make from ./install.sh.
+# Reject install programs that cannot install multiple files.
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a BSD-compatible install" >&5
+$as_echo_n "checking for a BSD-compatible install... " >&6; }
+if test -z "$INSTALL"; then
+if test "${ac_cv_path_install+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ # Account for people who put trailing slashes in PATH elements.
+case $as_dir/ in #((
+ ./ | .// | /[cC]/* | \
+ /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \
+ ?:[\\/]os2[\\/]install[\\/]* | ?:[\\/]OS2[\\/]INSTALL[\\/]* | \
+ /usr/ucb/* ) ;;
+ *)
+ # OSF1 and SCO ODT 3.0 have their own names for install.
+ # Don't use installbsd from OSF since it installs stuff as root
+ # by default.
+ for ac_prog in ginstall scoinst install; do
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if { test -f "$as_dir/$ac_prog$ac_exec_ext" && $as_test_x "$as_dir/$ac_prog$ac_exec_ext"; }; then
+ if test $ac_prog = install &&
+ grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then
+ # AIX install. It has an incompatible calling convention.
+ :
+ elif test $ac_prog = install &&
+ grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then
+ # program-specific install script used by HP pwplus--don't use.
+ :
+ else
+ rm -rf conftest.one conftest.two conftest.dir
+ echo one > conftest.one
+ echo two > conftest.two
+ mkdir conftest.dir
+ if "$as_dir/$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir" &&
+ test -s conftest.one && test -s conftest.two &&
+ test -s conftest.dir/conftest.one &&
+ test -s conftest.dir/conftest.two
+ then
+ ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c"
+ break 3
+ fi
+ fi
+ fi
+ done
+ done
+ ;;
+esac
+
+ done
+IFS=$as_save_IFS
+
+rm -rf conftest.one conftest.two conftest.dir
+
+fi
+ if test "${ac_cv_path_install+set}" = set; then
+ INSTALL=$ac_cv_path_install
+ else
+ # As a last resort, use the slow shell script. Don't cache a
+ # value for INSTALL within a source directory, because that will
+ # break other packages using the cache if that directory is
+ # removed, or if the value is a relative name.
+ INSTALL=$ac_install_sh
+ fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $INSTALL" >&5
+$as_echo "$INSTALL" >&6; }
+
+# Use test -z because SunOS4 sh mishandles braces in ${var-val}.
+# It thinks the first close brace ends the variable substitution.
+test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}'
+
+test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}'
+
+test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
+
+
+# Put a plausible default for CC_FOR_BUILD in Makefile.
+if test "x$cross_compiling" = "xno"; then
+ CC_FOR_BUILD='$(CC)'
+else
+ CC_FOR_BUILD=gcc
+fi
+
+
+
+
+AR=${AR-ar}
+
+if test -n "$ac_tool_prefix"; then
+ # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
+set dummy ${ac_tool_prefix}ranlib; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if test "${ac_cv_prog_RANLIB+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ if test -n "$RANLIB"; then
+ ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then
+ ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib"
+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+ done
+IFS=$as_save_IFS
+
+fi
+fi
+RANLIB=$ac_cv_prog_RANLIB
+if test -n "$RANLIB"; then
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5
+$as_echo "$RANLIB" >&6; }
+else
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+fi
+if test -z "$ac_cv_prog_RANLIB"; then
+ ac_ct_RANLIB=$RANLIB
+ # Extract the first word of "ranlib", so it can be a program name with args.
+set dummy ranlib; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ if test -n "$ac_ct_RANLIB"; then
+ ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then
+ ac_cv_prog_ac_ct_RANLIB="ranlib"
+ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+ done
+IFS=$as_save_IFS
+
+fi
+fi
+ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB
+if test -n "$ac_ct_RANLIB"; then
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5
+$as_echo "$ac_ct_RANLIB" >&6; }
+else
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+ if test "x$ac_ct_RANLIB" = x; then
+ RANLIB=":"
+ else
+ case $cross_compiling:$ac_tool_warned in
+yes:)
+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
+ac_tool_warned=yes ;;
+esac
+ RANLIB=$ac_ct_RANLIB
+ fi
+else
+ RANLIB="$ac_cv_prog_RANLIB"
+fi
+
+
+ALL_LINGUAS=
+# If we haven't got the data from the intl directory,
+# assume NLS is disabled.
+USE_NLS=no
+LIBINTL=
+LIBINTL_DEP=
+INCINTL=
+XGETTEXT=
+GMSGFMT=
+POSUB=
+
+if test -f ../../intl/config.intl; then
+ . ../../intl/config.intl
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether NLS is requested" >&5
+$as_echo_n "checking whether NLS is requested... " >&6; }
+if test x"$USE_NLS" != xyes; then
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+else
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
+
+$as_echo "#define ENABLE_NLS 1" >>confdefs.h
+
+
+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking for catalogs to be installed" >&5
+$as_echo_n "checking for catalogs to be installed... " >&6; }
+ # Look for .po and .gmo files in the source directory.
+ CATALOGS=
+ XLINGUAS=
+ for cat in $srcdir/po/*.gmo $srcdir/po/*.po; do
+ # If there aren't any .gmo files the shell will give us the
+ # literal string "../path/to/srcdir/po/*.gmo" which has to be
+ # weeded out.
+ case "$cat" in *\**)
+ continue;;
+ esac
+ # The quadruple backslash is collapsed to a double backslash
+ # by the backticks, then collapsed again by the double quotes,
+ # leaving us with one backslash in the sed expression (right
+ # before the dot that mustn't act as a wildcard).
+ cat=`echo $cat | sed -e "s!$srcdir/po/!!" -e "s!\\\\.po!.gmo!"`
+ lang=`echo $cat | sed -e "s!\\\\.gmo!!"`
+ # The user is allowed to set LINGUAS to a list of languages to
+ # install catalogs for. If it's empty that means "all of them."
+ if test "x$LINGUAS" = x; then
+ CATALOGS="$CATALOGS $cat"
+ XLINGUAS="$XLINGUAS $lang"
+ else
+ case "$LINGUAS" in *$lang*)
+ CATALOGS="$CATALOGS $cat"
+ XLINGUAS="$XLINGUAS $lang"
+ ;;
+ esac
+ fi
+ done
+ LINGUAS="$XLINGUAS"
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $LINGUAS" >&5
+$as_echo "$LINGUAS" >&6; }
+
+
+ DATADIRNAME=share
+
+ INSTOBJEXT=.mo
+
+ GENCAT=gencat
+
+ CATOBJEXT=.gmo
+
+fi
+
+# Check for common headers.
+# FIXME: Seems to me this can cause problems for i386-windows hosts.
+# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*.
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to run the C preprocessor" >&5
+$as_echo_n "checking how to run the C preprocessor... " >&6; }
+# On Suns, sometimes $CPP names a directory.
+if test -n "$CPP" && test -d "$CPP"; then
+ CPP=
+fi
+if test -z "$CPP"; then
+ if test "${ac_cv_prog_CPP+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ # Double quotes because CPP needs to be expanded
+ for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp"
+ do
+ ac_preproc_ok=false
+for ac_c_preproc_warn_flag in '' yes
+do
+ # Use a header file that comes with gcc, so configuring glibc
+ # with a fresh cross-compiler works.
+ # Prefer to if __STDC__ is defined, since
+ # exists even on freestanding compilers.
+ # On the NeXT, cc -E runs the code through the compiler's parser,
+ # not just through cpp. "Syntax error" is here to catch this case.
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+#ifdef __STDC__
+# include
+#else
+# include
+#endif
+ Syntax error
+_ACEOF
+if ac_fn_c_try_cpp "$LINENO"; then :
+
+else
+ # Broken: fails on valid input.
+continue
+fi
+rm -f conftest.err conftest.$ac_ext
+
+ # OK, works on sane cases. Now check whether nonexistent headers
+ # can be detected and how.
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+#include
+_ACEOF
+if ac_fn_c_try_cpp "$LINENO"; then :
+ # Broken: success on invalid input.
+continue
+else
+ # Passes both tests.
+ac_preproc_ok=:
+break
+fi
+rm -f conftest.err conftest.$ac_ext
+
+done
+# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
+rm -f conftest.err conftest.$ac_ext
+if $ac_preproc_ok; then :
+ break
+fi
+
+ done
+ ac_cv_prog_CPP=$CPP
+
+fi
+ CPP=$ac_cv_prog_CPP
+else
+ ac_cv_prog_CPP=$CPP
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $CPP" >&5
+$as_echo "$CPP" >&6; }
+ac_preproc_ok=false
+for ac_c_preproc_warn_flag in '' yes
+do
+ # Use a header file that comes with gcc, so configuring glibc
+ # with a fresh cross-compiler works.
+ # Prefer to if __STDC__ is defined, since
+ # exists even on freestanding compilers.
+ # On the NeXT, cc -E runs the code through the compiler's parser,
+ # not just through cpp. "Syntax error" is here to catch this case.
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+#ifdef __STDC__
+# include
+#else
+# include
+#endif
+ Syntax error
+_ACEOF
+if ac_fn_c_try_cpp "$LINENO"; then :
+
+else
+ # Broken: fails on valid input.
+continue
+fi
+rm -f conftest.err conftest.$ac_ext
+
+ # OK, works on sane cases. Now check whether nonexistent headers
+ # can be detected and how.
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+#include
+_ACEOF
+if ac_fn_c_try_cpp "$LINENO"; then :
+ # Broken: success on invalid input.
+continue
+else
+ # Passes both tests.
+ac_preproc_ok=:
+break
+fi
+rm -f conftest.err conftest.$ac_ext
+
+done
+# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
+rm -f conftest.err conftest.$ac_ext
+if $ac_preproc_ok; then :
+
+else
+ { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error "C preprocessor \"$CPP\" fails sanity check
+See \`config.log' for more details." "$LINENO" 5; }
+fi
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for grep that handles long lines and -e" >&5
+$as_echo_n "checking for grep that handles long lines and -e... " >&6; }
+if test "${ac_cv_path_GREP+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ if test -z "$GREP"; then
+ ac_path_GREP_found=false
+ # Loop through the user's path and test for each of PROGNAME-LIST
+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_prog in grep ggrep; do
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext"
+ { test -f "$ac_path_GREP" && $as_test_x "$ac_path_GREP"; } || continue
+# Check for GNU ac_path_GREP and select it if it is found.
+ # Check for GNU $ac_path_GREP
+case `"$ac_path_GREP" --version 2>&1` in
+*GNU*)
+ ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;;
+*)
+ ac_count=0
+ $as_echo_n 0123456789 >"conftest.in"
+ while :
+ do
+ cat "conftest.in" "conftest.in" >"conftest.tmp"
+ mv "conftest.tmp" "conftest.in"
+ cp "conftest.in" "conftest.nl"
+ $as_echo 'GREP' >> "conftest.nl"
+ "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break
+ diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break
+ as_fn_arith $ac_count + 1 && ac_count=$as_val
+ if test $ac_count -gt ${ac_path_GREP_max-0}; then
+ # Best one so far, save it but keep looking for a better one
+ ac_cv_path_GREP="$ac_path_GREP"
+ ac_path_GREP_max=$ac_count
+ fi
+ # 10*(2^10) chars as input seems more than enough
+ test $ac_count -gt 10 && break
+ done
+ rm -f conftest.in conftest.tmp conftest.nl conftest.out;;
+esac
+
+ $ac_path_GREP_found && break 3
+ done
+ done
+ done
+IFS=$as_save_IFS
+ if test -z "$ac_cv_path_GREP"; then
+ as_fn_error "no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5
+ fi
+else
+ ac_cv_path_GREP=$GREP
+fi
+
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_GREP" >&5
+$as_echo "$ac_cv_path_GREP" >&6; }
+ GREP="$ac_cv_path_GREP"
+
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for egrep" >&5
+$as_echo_n "checking for egrep... " >&6; }
+if test "${ac_cv_path_EGREP+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ if echo a | $GREP -E '(a|b)' >/dev/null 2>&1
+ then ac_cv_path_EGREP="$GREP -E"
+ else
+ if test -z "$EGREP"; then
+ ac_path_EGREP_found=false
+ # Loop through the user's path and test for each of PROGNAME-LIST
+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_prog in egrep; do
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext"
+ { test -f "$ac_path_EGREP" && $as_test_x "$ac_path_EGREP"; } || continue
+# Check for GNU ac_path_EGREP and select it if it is found.
+ # Check for GNU $ac_path_EGREP
+case `"$ac_path_EGREP" --version 2>&1` in
+*GNU*)
+ ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;;
+*)
+ ac_count=0
+ $as_echo_n 0123456789 >"conftest.in"
+ while :
+ do
+ cat "conftest.in" "conftest.in" >"conftest.tmp"
+ mv "conftest.tmp" "conftest.in"
+ cp "conftest.in" "conftest.nl"
+ $as_echo 'EGREP' >> "conftest.nl"
+ "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break
+ diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break
+ as_fn_arith $ac_count + 1 && ac_count=$as_val
+ if test $ac_count -gt ${ac_path_EGREP_max-0}; then
+ # Best one so far, save it but keep looking for a better one
+ ac_cv_path_EGREP="$ac_path_EGREP"
+ ac_path_EGREP_max=$ac_count
+ fi
+ # 10*(2^10) chars as input seems more than enough
+ test $ac_count -gt 10 && break
+ done
+ rm -f conftest.in conftest.tmp conftest.nl conftest.out;;
+esac
+
+ $ac_path_EGREP_found && break 3
+ done
+ done
+ done
+IFS=$as_save_IFS
+ if test -z "$ac_cv_path_EGREP"; then
+ as_fn_error "no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5
+ fi
+else
+ ac_cv_path_EGREP=$EGREP
+fi
+
+ fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_EGREP" >&5
+$as_echo "$ac_cv_path_EGREP" >&6; }
+ EGREP="$ac_cv_path_EGREP"
+
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for ANSI C header files" >&5
+$as_echo_n "checking for ANSI C header files... " >&6; }
+if test "${ac_cv_header_stdc+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+#include
+#include
+#include
+#include
+
+int
+main ()
+{
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+ ac_cv_header_stdc=yes
+else
+ ac_cv_header_stdc=no
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+
+if test $ac_cv_header_stdc = yes; then
+ # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+#include
+
+_ACEOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+ $EGREP "memchr" >/dev/null 2>&1; then :
+
+else
+ ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+ # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+#include
+
+_ACEOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+ $EGREP "free" >/dev/null 2>&1; then :
+
+else
+ ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+ # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
+ if test "$cross_compiling" = yes; then :
+ :
+else
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+#include
+#include
+#if ((' ' & 0x0FF) == 0x020)
+# define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
+# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
+#else
+# define ISLOWER(c) \
+ (('a' <= (c) && (c) <= 'i') \
+ || ('j' <= (c) && (c) <= 'r') \
+ || ('s' <= (c) && (c) <= 'z'))
+# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c))
+#endif
+
+#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
+int
+main ()
+{
+ int i;
+ for (i = 0; i < 256; i++)
+ if (XOR (islower (i), ISLOWER (i))
+ || toupper (i) != TOUPPER (i))
+ return 2;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_run "$LINENO"; then :
+
+else
+ ac_cv_header_stdc=no
+fi
+rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \
+ conftest.$ac_objext conftest.beam conftest.$ac_ext
+fi
+
+fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_stdc" >&5
+$as_echo "$ac_cv_header_stdc" >&6; }
+if test $ac_cv_header_stdc = yes; then
+
+$as_echo "#define STDC_HEADERS 1" >>confdefs.h
+
+fi
+
+# On IRIX 5.3, sys/types and inttypes.h are conflicting.
+for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \
+ inttypes.h stdint.h unistd.h
+do :
+ as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
+ac_fn_c_check_header_compile "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default
+"
+eval as_val=\$$as_ac_Header
+ if test "x$as_val" = x""yes; then :
+ cat >>confdefs.h <<_ACEOF
+#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+for ac_header in stdlib.h string.h strings.h unistd.h time.h
+do :
+ as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
+ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default"
+eval as_val=\$$as_ac_Header
+ if test "x$as_val" = x""yes; then :
+ cat >>confdefs.h <<_ACEOF
+#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+for ac_header in sys/time.h sys/resource.h
+do :
+ as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
+ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default"
+eval as_val=\$$as_ac_Header
+ if test "x$as_val" = x""yes; then :
+ cat >>confdefs.h <<_ACEOF
+#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+for ac_header in fcntl.h fpu_control.h
+do :
+ as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
+ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default"
+eval as_val=\$$as_ac_Header
+ if test "x$as_val" = x""yes; then :
+ cat >>confdefs.h <<_ACEOF
+#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+for ac_header in dlfcn.h errno.h sys/stat.h
+do :
+ as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
+ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default"
+eval as_val=\$$as_ac_Header
+ if test "x$as_val" = x""yes; then :
+ cat >>confdefs.h <<_ACEOF
+#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+for ac_func in getrusage time sigaction __setfpucw
+do :
+ as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh`
+ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var"
+eval as_val=\$$as_ac_var
+ if test "x$as_val" = x""yes; then :
+ cat >>confdefs.h <<_ACEOF
+#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+done
+
+
+# Check for socket libraries
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for bind in -lsocket" >&5
+$as_echo_n "checking for bind in -lsocket... " >&6; }
+if test "${ac_cv_lib_socket_bind+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ ac_check_lib_save_LIBS=$LIBS
+LIBS="-lsocket $LIBS"
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+
+/* Override any GCC internal prototype to avoid an error.
+ Use char because int might match the return type of a GCC
+ builtin and then its argument prototype would still apply. */
+#ifdef __cplusplus
+extern "C"
+#endif
+char bind ();
+int
+main ()
+{
+return bind ();
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_link "$LINENO"; then :
+ ac_cv_lib_socket_bind=yes
+else
+ ac_cv_lib_socket_bind=no
+fi
+rm -f core conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_socket_bind" >&5
+$as_echo "$ac_cv_lib_socket_bind" >&6; }
+if test "x$ac_cv_lib_socket_bind" = x""yes; then :
+ cat >>confdefs.h <<_ACEOF
+#define HAVE_LIBSOCKET 1
+_ACEOF
+
+ LIBS="-lsocket $LIBS"
+
+fi
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for gethostbyname in -lnsl" >&5
+$as_echo_n "checking for gethostbyname in -lnsl... " >&6; }
+if test "${ac_cv_lib_nsl_gethostbyname+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ ac_check_lib_save_LIBS=$LIBS
+LIBS="-lnsl $LIBS"
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+
+/* Override any GCC internal prototype to avoid an error.
+ Use char because int might match the return type of a GCC
+ builtin and then its argument prototype would still apply. */
+#ifdef __cplusplus
+extern "C"
+#endif
+char gethostbyname ();
+int
+main ()
+{
+return gethostbyname ();
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_link "$LINENO"; then :
+ ac_cv_lib_nsl_gethostbyname=yes
+else
+ ac_cv_lib_nsl_gethostbyname=no
+fi
+rm -f core conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_nsl_gethostbyname" >&5
+$as_echo "$ac_cv_lib_nsl_gethostbyname" >&6; }
+if test "x$ac_cv_lib_nsl_gethostbyname" = x""yes; then :
+ cat >>confdefs.h <<_ACEOF
+#define HAVE_LIBNSL 1
+_ACEOF
+
+ LIBS="-lnsl $LIBS"
+
+fi
+
+
+# BFD conditionally uses zlib, so we must link it in if libbfd does, by
+# using the same condition.
+
+ # See if the user specified whether he wants zlib support or not.
+
+# Check whether --with-zlib was given.
+if test "${with_zlib+set}" = set; then :
+ withval=$with_zlib;
+else
+ with_zlib=auto
+fi
+
+
+ if test "$with_zlib" != "no"; then
+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing zlibVersion" >&5
+$as_echo_n "checking for library containing zlibVersion... " >&6; }
+if test "${ac_cv_search_zlibVersion+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ ac_func_search_save_LIBS=$LIBS
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+
+/* Override any GCC internal prototype to avoid an error.
+ Use char because int might match the return type of a GCC
+ builtin and then its argument prototype would still apply. */
+#ifdef __cplusplus
+extern "C"
+#endif
+char zlibVersion ();
+int
+main ()
+{
+return zlibVersion ();
+ ;
+ return 0;
+}
+_ACEOF
+for ac_lib in '' z; do
+ if test -z "$ac_lib"; then
+ ac_res="none required"
+ else
+ ac_res=-l$ac_lib
+ LIBS="-l$ac_lib $ac_func_search_save_LIBS"
+ fi
+ if ac_fn_c_try_link "$LINENO"; then :
+ ac_cv_search_zlibVersion=$ac_res
+fi
+rm -f core conftest.err conftest.$ac_objext \
+ conftest$ac_exeext
+ if test "${ac_cv_search_zlibVersion+set}" = set; then :
+ break
+fi
+done
+if test "${ac_cv_search_zlibVersion+set}" = set; then :
+
+else
+ ac_cv_search_zlibVersion=no
+fi
+rm conftest.$ac_ext
+LIBS=$ac_func_search_save_LIBS
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_zlibVersion" >&5
+$as_echo "$ac_cv_search_zlibVersion" >&6; }
+ac_res=$ac_cv_search_zlibVersion
+if test "$ac_res" != no; then :
+ test "$ac_res" = "none required" || LIBS="$ac_res $LIBS"
+ for ac_header in zlib.h
+do :
+ ac_fn_c_check_header_mongrel "$LINENO" "zlib.h" "ac_cv_header_zlib_h" "$ac_includes_default"
+if test "x$ac_cv_header_zlib_h" = x""yes; then :
+ cat >>confdefs.h <<_ACEOF
+#define HAVE_ZLIB_H 1
+_ACEOF
+
+fi
+
+done
+
+fi
+
+ if test "$with_zlib" = "yes" -a "$ac_cv_header_zlib_h" != "yes"; then
+ as_fn_error "zlib (libz) library was explicitly requested but not found" "$LINENO" 5
+ fi
+ fi
+
+
+. ${srcdir}/../../bfd/configure.host
+
+
+
+USE_MAINTAINER_MODE=no
+# Check whether --enable-maintainer-mode was given.
+if test "${enable_maintainer_mode+set}" = set; then :
+ enableval=$enable_maintainer_mode; case "${enableval}" in
+ yes) MAINT="" USE_MAINTAINER_MODE=yes ;;
+ no) MAINT="#" ;;
+ *) as_fn_error "\"--enable-maintainer-mode does not take a value\"" "$LINENO" 5; MAINT="#" ;;
+esac
+if test x"$silent" != x"yes" && test x"$MAINT" = x""; then
+ echo "Setting maintainer mode" 6>&1
+fi
+else
+ MAINT="#"
+fi
+
+
+
+# Check whether --enable-sim-bswap was given.
+if test "${enable_sim_bswap+set}" = set; then :
+ enableval=$enable_sim_bswap; case "${enableval}" in
+ yes) sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";;
+ no) sim_bswap="-DWITH_BSWAP=0";;
+ *) as_fn_error "\"--enable-sim-bswap does not take a value\"" "$LINENO" 5; sim_bswap="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then
+ echo "Setting bswap flags = $sim_bswap" 6>&1
+fi
+else
+ sim_bswap=""
+fi
+
+
+
+# Check whether --enable-sim-cflags was given.
+if test "${enable_sim_cflags+set}" = set; then :
+ enableval=$enable_sim_cflags; case "${enableval}" in
+ yes) sim_cflags="-O2 -fomit-frame-pointer";;
+ trace) as_fn_error "\"Please use --enable-sim-debug instead.\"" "$LINENO" 5; sim_cflags="";;
+ no) sim_cflags="";;
+ *) sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then
+ echo "Setting sim cflags = $sim_cflags" 6>&1
+fi
+else
+ sim_cflags=""
+fi
+
+
+
+# Check whether --enable-sim-debug was given.
+if test "${enable_sim_debug+set}" = set; then :
+ enableval=$enable_sim_debug; case "${enableval}" in
+ yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";;
+ no) sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";;
+ *) sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then
+ echo "Setting sim debug = $sim_debug" 6>&1
+fi
+else
+ sim_debug=""
+fi
+
+
+
+# Check whether --enable-sim-stdio was given.
+if test "${enable_sim_stdio+set}" = set; then :
+ enableval=$enable_sim_stdio; case "${enableval}" in
+ yes) sim_stdio="-DWITH_STDIO=DO_USE_STDIO";;
+ no) sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";;
+ *) as_fn_error "\"Unknown value $enableval passed to --enable-sim-stdio\"" "$LINENO" 5; sim_stdio="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then
+ echo "Setting stdio flags = $sim_stdio" 6>&1
+fi
+else
+ sim_stdio=""
+fi
+
+
+
+# Check whether --enable-sim-trace was given.
+if test "${enable_sim_trace+set}" = set; then :
+ enableval=$enable_sim_trace; case "${enableval}" in
+ yes) sim_trace="-DTRACE=1 -DWITH_TRACE=-1";;
+ no) sim_trace="-DTRACE=0 -DWITH_TRACE=0";;
+ [-0-9]*)
+ sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";;
+ [a-z]*)
+ sim_trace=""
+ for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+ if test x"$sim_trace" = x; then
+ sim_trace="-DWITH_TRACE='(TRACE_$x"
+ else
+ sim_trace="${sim_trace}|TRACE_$x"
+ fi
+ done
+ sim_trace="$sim_trace)'" ;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then
+ echo "Setting sim trace = $sim_trace" 6>&1
+fi
+else
+ sim_trace=""
+fi
+
+
+
+# Check whether --enable-sim-profile was given.
+if test "${enable_sim_profile+set}" = set; then :
+ enableval=$enable_sim_profile; case "${enableval}" in
+ yes) sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";;
+ no) sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";;
+ [-0-9]*)
+ sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";;
+ [a-z]*)
+ sim_profile=""
+ for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+ if test x"$sim_profile" = x; then
+ sim_profile="-DWITH_PROFILE='(PROFILE_$x"
+ else
+ sim_profile="${sim_profile}|PROFILE_$x"
+ fi
+ done
+ sim_profile="$sim_profile)'" ;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then
+ echo "Setting sim profile = $sim_profile" 6>&1
+fi
+else
+ sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1"
+fi
+
+
+
+
+# Check whether --with-pkgversion was given.
+if test "${with_pkgversion+set}" = set; then :
+ withval=$with_pkgversion; case "$withval" in
+ yes) as_fn_error "package version not specified" "$LINENO" 5 ;;
+ no) PKGVERSION= ;;
+ *) PKGVERSION="($withval) " ;;
+ esac
+else
+ PKGVERSION="(GDB) "
+
+fi
+
+
+
+
+
+# Check whether --with-bugurl was given.
+if test "${with_bugurl+set}" = set; then :
+ withval=$with_bugurl; case "$withval" in
+ yes) as_fn_error "bug URL not specified" "$LINENO" 5 ;;
+ no) BUGURL=
+ ;;
+ *) BUGURL="$withval"
+ ;;
+ esac
+else
+ BUGURL="http://www.gnu.org/software/gdb/bugs/"
+
+fi
+
+ case ${BUGURL} in
+ "")
+ REPORT_BUGS_TO=
+ REPORT_BUGS_TEXI=
+ ;;
+ *)
+ REPORT_BUGS_TO="<$BUGURL>"
+ REPORT_BUGS_TEXI=@uref{`echo "$BUGURL" | sed 's/@/@@/g'`}
+ ;;
+ esac;
+
+
+
+
+cat >>confdefs.h <<_ACEOF
+#define PKGVERSION "$PKGVERSION"
+_ACEOF
+
+
+cat >>confdefs.h <<_ACEOF
+#define REPORT_BUGS_TO "$REPORT_BUGS_TO"
+_ACEOF
+
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking return type of signal handlers" >&5
+$as_echo_n "checking return type of signal handlers... " >&6; }
+if test "${ac_cv_type_signal+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+#include
+#include
+
+int
+main ()
+{
+return *(signal (0, 0)) (0) == 1;
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+ ac_cv_type_signal=int
+else
+ ac_cv_type_signal=void
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_type_signal" >&5
+$as_echo "$ac_cv_type_signal" >&6; }
+
+cat >>confdefs.h <<_ACEOF
+#define RETSIGTYPE $ac_cv_type_signal
+_ACEOF
+
+
+
+
+
+sim_link_files=
+sim_link_links=
+
+sim_link_links=tconfig.h
+if test -f ${srcdir}/tconfig.in
+then
+ sim_link_files=tconfig.in
+else
+ sim_link_files=../common/tconfig.in
+fi
+
+# targ-vals.def points to the libc macro description file.
+case "${target}" in
+*-*-*) TARG_VALS_DEF=../common/nltvals.def ;;
+esac
+sim_link_files="${sim_link_files} ${TARG_VALS_DEF}"
+sim_link_links="${sim_link_links} targ-vals.def"
+
+
+
+wire_endian="LITTLE_ENDIAN"
+default_endian=""
+# Check whether --enable-sim-endian was given.
+if test "${enable_sim_endian+set}" = set; then :
+ enableval=$enable_sim_endian; case "${enableval}" in
+ b*|B*) sim_endian="-DWITH_TARGET_BYTE_ORDER=BIG_ENDIAN";;
+ l*|L*) sim_endian="-DWITH_TARGET_BYTE_ORDER=LITTLE_ENDIAN";;
+ yes) if test x"$wire_endian" != x; then
+ sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}"
+ else
+ if test x"$default_endian" != x; then
+ sim_endian="-DWITH_TARGET_BYTE_ORDER=${default_endian}"
+ else
+ echo "No hard-wired endian for target $target" 1>&6
+ sim_endian="-DWITH_TARGET_BYTE_ORDER=0"
+ fi
+ fi;;
+ no) if test x"$default_endian" != x; then
+ sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}"
+ else
+ if test x"$wire_endian" != x; then
+ sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${wire_endian}"
+ else
+ echo "No default endian for target $target" 1>&6
+ sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=0"
+ fi
+ fi;;
+ *) as_fn_error "\"Unknown value $enableval for --enable-sim-endian\"" "$LINENO" 5; sim_endian="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_endian" != x""; then
+ echo "Setting endian flags = $sim_endian" 6>&1
+fi
+else
+ if test x"$default_endian" != x; then
+ sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}"
+else
+ if test x"$wire_endian" != x; then
+ sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}"
+ else
+ sim_endian=
+ fi
+fi
+fi
+
+wire_alignment="NONSTRICT_ALIGNMENT"
+default_alignment=""
+
+# Check whether --enable-sim-alignment was given.
+if test "${enable_sim_alignment+set}" = set; then :
+ enableval=$enable_sim_alignment; case "${enableval}" in
+ strict | STRICT) sim_alignment="-DWITH_ALIGNMENT=STRICT_ALIGNMENT";;
+ nonstrict | NONSTRICT) sim_alignment="-DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT";;
+ forced | FORCED) sim_alignment="-DWITH_ALIGNMENT=FORCED_ALIGNMENT";;
+ yes) if test x"$wire_alignment" != x; then
+ sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
+ else
+ if test x"$default_alignment" != x; then
+ sim_alignment="-DWITH_ALIGNMENT=${default_alignment}"
+ else
+ echo "No hard-wired alignment for target $target" 1>&6
+ sim_alignment="-DWITH_ALIGNMENT=0"
+ fi
+ fi;;
+ no) if test x"$default_alignment" != x; then
+ sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
+ else
+ if test x"$wire_alignment" != x; then
+ sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${wire_alignment}"
+ else
+ echo "No default alignment for target $target" 1>&6
+ sim_alignment="-DWITH_DEFAULT_ALIGNMENT=0"
+ fi
+ fi;;
+ *) as_fn_error "\"Unknown value $enableval passed to --enable-sim-alignment\"" "$LINENO" 5; sim_alignment="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_alignment" != x""; then
+ echo "Setting alignment flags = $sim_alignment" 6>&1
+fi
+else
+ if test x"$default_alignment" != x; then
+ sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
+else
+ if test x"$wire_alignment" != x; then
+ sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
+ else
+ sim_alignment=
+ fi
+fi
+fi
+
+
+# Check whether --enable-sim-hostendian was given.
+if test "${enable_sim_hostendian+set}" = set; then :
+ enableval=$enable_sim_hostendian; case "${enableval}" in
+ no) sim_hostendian="-DWITH_HOST_BYTE_ORDER=0";;
+ b*|B*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN";;
+ l*|L*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN";;
+ *) as_fn_error "\"Unknown value $enableval for --enable-sim-hostendian\"" "$LINENO" 5; sim_hostendian="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_hostendian" != x""; then
+ echo "Setting hostendian flags = $sim_hostendian" 6>&1
+fi
+else
+
+if test "x$cross_compiling" = "xno"; then
+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether byte ordering is bigendian" >&5
+$as_echo_n "checking whether byte ordering is bigendian... " >&6; }
+if test "${ac_cv_c_bigendian+set}" = set; then :
+ $as_echo_n "(cached) " >&6
+else
+ ac_cv_c_bigendian=unknown
+ # See if we're dealing with a universal compiler.
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+#ifndef __APPLE_CC__
+ not a universal capable compiler
+ #endif
+ typedef int dummy;
+
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+
+ # Check for potential -arch flags. It is not universal unless
+ # there are at least two -arch flags with different values.
+ ac_arch=
+ ac_prev=
+ for ac_word in $CC $CFLAGS $CPPFLAGS $LDFLAGS; do
+ if test -n "$ac_prev"; then
+ case $ac_word in
+ i?86 | x86_64 | ppc | ppc64)
+ if test -z "$ac_arch" || test "$ac_arch" = "$ac_word"; then
+ ac_arch=$ac_word
+ else
+ ac_cv_c_bigendian=universal
+ break
+ fi
+ ;;
+ esac
+ ac_prev=
+ elif test "x$ac_word" = "x-arch"; then
+ ac_prev=arch
+ fi
+ done
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+ if test $ac_cv_c_bigendian = unknown; then
+ # See if sys/param.h defines the BYTE_ORDER macro.
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+#include
+ #include
+
+int
+main ()
+{
+#if ! (defined BYTE_ORDER && defined BIG_ENDIAN \
+ && defined LITTLE_ENDIAN && BYTE_ORDER && BIG_ENDIAN \
+ && LITTLE_ENDIAN)
+ bogus endian macros
+ #endif
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+ # It does; now see whether it defined to BIG_ENDIAN or not.
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+#include
+ #include
+
+int
+main ()
+{
+#if BYTE_ORDER != BIG_ENDIAN
+ not big endian
+ #endif
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+ ac_cv_c_bigendian=yes
+else
+ ac_cv_c_bigendian=no
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+ fi
+ if test $ac_cv_c_bigendian = unknown; then
+ # See if defines _LITTLE_ENDIAN or _BIG_ENDIAN (e.g., Solaris).
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+#include
+
+int
+main ()
+{
+#if ! (defined _LITTLE_ENDIAN || defined _BIG_ENDIAN)
+ bogus endian macros
+ #endif
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+ # It does; now see whether it defined to _BIG_ENDIAN or not.
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+#include
+
+int
+main ()
+{
+#ifndef _BIG_ENDIAN
+ not big endian
+ #endif
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+ ac_cv_c_bigendian=yes
+else
+ ac_cv_c_bigendian=no
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+ fi
+ if test $ac_cv_c_bigendian = unknown; then
+ # Compile a test program.
+ if test "$cross_compiling" = yes; then :
+ # Try to guess by grepping values from an object file.
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+short int ascii_mm[] =
+ { 0x4249, 0x4765, 0x6E44, 0x6961, 0x6E53, 0x7953, 0 };
+ short int ascii_ii[] =
+ { 0x694C, 0x5454, 0x656C, 0x6E45, 0x6944, 0x6E61, 0 };
+ int use_ascii (int i) {
+ return ascii_mm[i] + ascii_ii[i];
+ }
+ short int ebcdic_ii[] =
+ { 0x89D3, 0xE3E3, 0x8593, 0x95C5, 0x89C4, 0x9581, 0 };
+ short int ebcdic_mm[] =
+ { 0xC2C9, 0xC785, 0x95C4, 0x8981, 0x95E2, 0xA8E2, 0 };
+ int use_ebcdic (int i) {
+ return ebcdic_mm[i] + ebcdic_ii[i];
+ }
+ extern int foo;
+
+int
+main ()
+{
+return use_ascii (foo) == use_ebcdic (foo);
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+ if grep BIGenDianSyS conftest.$ac_objext >/dev/null; then
+ ac_cv_c_bigendian=yes
+ fi
+ if grep LiTTleEnDian conftest.$ac_objext >/dev/null ; then
+ if test "$ac_cv_c_bigendian" = unknown; then
+ ac_cv_c_bigendian=no
+ else
+ # finding both strings is unlikely to happen, but who knows?
+ ac_cv_c_bigendian=unknown
+ fi
+ fi
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+else
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+$ac_includes_default
+int
+main ()
+{
+
+ /* Are we little or big endian? From Harbison&Steele. */
+ union
+ {
+ long int l;
+ char c[sizeof (long int)];
+ } u;
+ u.l = 1;
+ return u.c[sizeof (long int) - 1] == 1;
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_run "$LINENO"; then :
+ ac_cv_c_bigendian=no
+else
+ ac_cv_c_bigendian=yes
+fi
+rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \
+ conftest.$ac_objext conftest.beam conftest.$ac_ext
+fi
+
+ fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_bigendian" >&5
+$as_echo "$ac_cv_c_bigendian" >&6; }
+ case $ac_cv_c_bigendian in #(
+ yes)
+ $as_echo "#define WORDS_BIGENDIAN 1" >>confdefs.h
+;; #(
+ no)
+ ;; #(
+ universal)
+
+$as_echo "#define AC_APPLE_UNIVERSAL_BUILD 1" >>confdefs.h
+
+ ;; #(
+ *)
+ as_fn_error "unknown endianness
+ presetting ac_cv_c_bigendian=no (or yes) will help" "$LINENO" 5 ;;
+ esac
+
+ if test $ac_cv_c_bigendian = yes; then
+ sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN"
+ else
+ sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN"
+ fi
+else
+ sim_hostendian="-DWITH_HOST_BYTE_ORDER=0"
+fi
+fi
+
+
+# NOTE: Don't add -Wall or -Wunused, they both include
+# -Wunused-parameter which reports bogus warnings.
+# NOTE: If you add to this list, remember to update
+# gdb/doc/gdbint.texinfo.
+build_warnings="-Wimplicit -Wreturn-type -Wcomment -Wtrigraphs \
+-Wformat -Wparentheses -Wpointer-arith"
+# GCC supports -Wuninitialized only with -O or -On, n != 0.
+if test x${CFLAGS+set} = xset; then
+ case "${CFLAGS}" in
+ *"-O0"* ) ;;
+ *"-O"* )
+ build_warnings="${build_warnings} -Wuninitialized"
+ ;;
+ esac
+else
+ build_warnings="${build_warnings} -Wuninitialized"
+fi
+# Up for debate: -Wswitch -Wcomment -trigraphs -Wtrigraphs
+# -Wunused-function -Wunused-label -Wunused-variable -Wunused-value
+# -Wchar-subscripts -Wtraditional -Wshadow -Wcast-qual
+# -Wcast-align -Wwrite-strings -Wconversion -Wstrict-prototypes
+# -Wmissing-prototypes -Wmissing-declarations -Wredundant-decls
+# -Woverloaded-virtual -Winline -Werror"
+# Check whether --enable-build-warnings was given.
+if test "${enable_build_warnings+set}" = set; then :
+ enableval=$enable_build_warnings; case "${enableval}" in
+ yes) ;;
+ no) build_warnings="-w";;
+ ,*) t=`echo "${enableval}" | sed -e "s/,/ /g"`
+ build_warnings="${build_warnings} ${t}";;
+ *,) t=`echo "${enableval}" | sed -e "s/,/ /g"`
+ build_warnings="${t} ${build_warnings}";;
+ *) build_warnings=`echo "${enableval}" | sed -e "s/,/ /g"`;;
+esac
+if test x"$silent" != x"yes" && test x"$build_warnings" != x""; then
+ echo "Setting compiler warning flags = $build_warnings" 6>&1
+fi
+fi
+# Check whether --enable-sim-build-warnings was given.
+if test "${enable_sim_build_warnings+set}" = set; then :
+ enableval=$enable_sim_build_warnings; case "${enableval}" in
+ yes) ;;
+ no) build_warnings="-w";;
+ ,*) t=`echo "${enableval}" | sed -e "s/,/ /g"`
+ build_warnings="${build_warnings} ${t}";;
+ *,) t=`echo "${enableval}" | sed -e "s/,/ /g"`
+ build_warnings="${t} ${build_warnings}";;
+ *) build_warnings=`echo "${enableval}" | sed -e "s/,/ /g"`;;
+esac
+if test x"$silent" != x"yes" && test x"$build_warnings" != x""; then
+ echo "Setting GDB specific compiler warning flags = $build_warnings" 6>&1
+fi
+fi
+WARN_CFLAGS=""
+WERROR_CFLAGS=""
+if test "x${build_warnings}" != x -a "x$GCC" = xyes
+then
+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking compiler warning flags" >&5
+$as_echo_n "checking compiler warning flags... " >&6; }
+ # Separate out the -Werror flag as some files just cannot be
+ # compiled with it enabled.
+ for w in ${build_warnings}; do
+ case $w in
+ -Werr*) WERROR_CFLAGS=-Werror ;;
+ *) # Check that GCC accepts it
+ saved_CFLAGS="$CFLAGS"
+ CFLAGS="$CFLAGS $w"
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+ WARN_CFLAGS="${WARN_CFLAGS} $w"
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+ CFLAGS="$saved_CFLAGS"
+ esac
+ done
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: ${WARN_CFLAGS}${WERROR_CFLAGS}" >&5
+$as_echo "${WARN_CFLAGS}${WERROR_CFLAGS}" >&6; }
+fi
+
+
+default_sim_reserved_bits="1"
+# Check whether --enable-sim-reserved-bits was given.
+if test "${enable_sim_reserved_bits+set}" = set; then :
+ enableval=$enable_sim_reserved_bits; case "${enableval}" in
+ yes) sim_reserved_bits="-DWITH_RESERVED_BITS=1";;
+ no) sim_reserved_bits="-DWITH_RESERVED_BITS=0";;
+ *) as_fn_error "\"--enable-sim-reserved-bits does not take a value\"" "$LINENO" 5; sim_reserved_bits="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_reserved_bits" != x""; then
+ echo "Setting reserved flags = $sim_reserved_bits" 6>&1
+fi
+else
+ sim_reserved_bits="-DWITH_RESERVED_BITS=${default_sim_reserved_bits}"
+fi
+
+wire_word_bitsize="32"
+wire_word_msb="31"
+wire_address_bitsize=""
+wire_cell_bitsize=""
+# Check whether --enable-sim-bitsize was given.
+if test "${enable_sim_bitsize+set}" = set; then :
+ enableval=$enable_sim_bitsize; sim_bitsize=
+case "${enableval}" in
+ 64,63 | 64,63,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=63";;
+ 32,31 | 32,31,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31";;
+ 64,0 | 64,0,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0";;
+ 32,0 | 64,0,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0";;
+ 32) if test x"$wire_word_msb" != x -a x"$wire_word_msb" != x0; then
+ sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31"
+ else
+ sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0"
+ fi ;;
+ 64) if test x"$wire_word_msb" != x -a x"$wire_word_msb" != x0; then
+ sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=63"
+ else
+ sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=0"
+ fi ;;
+ *) as_fn_error "\"--enable-sim-bitsize was given $enableval. Expected 32 or 64\"" "$LINENO" 5 ;;
+esac
+# address bitsize
+tmp=`echo "${enableval}" | sed -e "s/^[0-9]*,*[0-9]*,*//"`
+case x"${tmp}" in
+ x ) ;;
+ x32 | x32,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_ADDRESS_BITSIZE=32" ;;
+ x64 | x64,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_ADDRESS_BITSIZE=64" ;;
+ * ) as_fn_error "\"--enable-sim-bitsize was given address size $enableval. Expected 32 or 64\"" "$LINENO" 5 ;;
+esac
+# cell bitsize
+tmp=`echo "${enableval}" | sed -e "s/^[0-9]*,*[0-9*]*,*[0-9]*,*//"`
+case x"${tmp}" in
+ x ) ;;
+ x32 | x32,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_CELL_BITSIZE=32" ;;
+ x64 | x64,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_CELL_BITSIZE=64" ;;
+ * ) as_fn_error "\"--enable-sim-bitsize was given cell size $enableval. Expected 32 or 64\"" "$LINENO" 5 ;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_bitsize" != x""; then
+ echo "Setting bitsize flags = $sim_bitsize" 6>&1
+fi
+else
+ sim_bitsize=""
+if test x"$wire_word_bitsize" != x; then
+ sim_bitsize="$sim_bitsize -DWITH_TARGET_WORD_BITSIZE=$wire_word_bitsize"
+fi
+if test x"$wire_word_msb" != x; then
+ sim_bitsize="$sim_bitsize -DWITH_TARGET_WORD_MSB=$wire_word_msb"
+fi
+if test x"$wire_address_bitsize" != x; then
+ sim_bitsize="$sim_bitsize -DWITH_TARGET_ADDRESS_BITSIZE=$wire_address_bitsize"
+fi
+if test x"$wire_cell_bitsize" != x; then
+ sim_bitsize="$sim_bitsize -DWITH_TARGET_CELL_BITSIZE=$wire_cell_bitsize"
+fi
+fi
+
+
+default_sim_inline=""
+# Check whether --enable-sim-inline was given.
+if test "${enable_sim_inline+set}" = set; then :
+ enableval=$enable_sim_inline; sim_inline=""
+case "$enableval" in
+ no) sim_inline="-DDEFAULT_INLINE=0";;
+ 0) sim_inline="-DDEFAULT_INLINE=0";;
+ yes | 2) sim_inline="-DDEFAULT_INLINE=ALL_C_INLINE";;
+ 1) sim_inline="-DDEFAULT_INLINE=INLINE_LOCALS";;
+ *) for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+ new_flag=""
+ case "$x" in
+ *_INLINE=*) new_flag="-D$x";;
+ *=*) new_flag=`echo "$x" | sed -e "s/=/_INLINE=/" -e "s/^/-D/"`;;
+ *_INLINE) new_flag="-D$x=ALL_C_INLINE";;
+ *) new_flag="-D$x""_INLINE=ALL_C_INLINE";;
+ esac
+ if test x"$sim_inline" = x""; then
+ sim_inline="$new_flag"
+ else
+ sim_inline="$sim_inline $new_flag"
+ fi
+ done;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_inline" != x""; then
+ echo "Setting inline flags = $sim_inline" 6>&1
+fi
+else
+
+if test "x$cross_compiling" = "xno"; then
+ if test x"$GCC" != "x" -a x"${default_sim_inline}" != "x" ; then
+ sim_inline="${default_sim_inline}"
+ if test x"$silent" != x"yes"; then
+ echo "Setting inline flags = $sim_inline" 6>&1
+ fi
+ else
+ sim_inline=""
+ fi
+else
+ sim_inline="-DDEFAULT_INLINE=0"
+fi
+fi
+
+
+if test x"yes" = x"yes"; then
+ sim_hw_p=yes
+else
+ sim_hw_p=no
+fi
+if test ""; then
+ hardware="core pal glue"
+else
+ hardware="core pal glue mn103cpu mn103int mn103tim mn103ser mn103iop"
+fi
+sim_hw_cflags="-DWITH_HW=1"
+sim_hw="$hardware"
+sim_hw_objs="\$(SIM_COMMON_HW_OBJS) `echo $sim_hw | sed -e 's/\([^ ][^ ]*\)/dv-\1.o/g'`"
+# Check whether --enable-sim-hardware was given.
+if test "${enable_sim_hardware+set}" = set; then :
+ enableval=$enable_sim_hardware;
+case "${enableval}" in
+ yes) sim_hw_p=yes;;
+ no) sim_hw_p=no;;
+ ,*) sim_hw_p=yes; hardware="${hardware} `echo ${enableval} | sed -e 's/,/ /'`";;
+ *,) sim_hw_p=yes; hardware="`echo ${enableval} | sed -e 's/,/ /'` ${hardware}";;
+ *) sim_hw_p=yes; hardware="`echo ${enableval} | sed -e 's/,/ /'`"'';;
+esac
+if test "$sim_hw_p" != yes; then
+ sim_hw_objs=
+ sim_hw_cflags="-DWITH_HW=0"
+ sim_hw=
+else
+ sim_hw_cflags="-DWITH_HW=1"
+ # remove duplicates
+ sim_hw=""
+ sim_hw_objs="\$(SIM_COMMON_HW_OBJS)"
+ for i in $hardware ; do
+ case " $sim_hw " in
+ *" $i "*) ;;
+ *) sim_hw="$sim_hw $i" ; sim_hw_objs="$sim_hw_objs dv-$i.o";;
+ esac
+ done
+fi
+if test x"$silent" != x"yes" && test "$sim_hw_p" = "yes"; then
+ echo "Setting hardware to $sim_hw_cflags, $sim_hw, $sim_hw_objs"
+fi
+else
+
+if test "$sim_hw_p" != yes; then
+ sim_hw_objs=
+ sim_hw_cflags="-DWITH_HW=0"
+ sim_hw=
+fi
+if test x"$silent" != x"yes"; then
+ echo "Setting hardware to $sim_hw_cflags, $sim_hw, $sim_hw_objs"
+fi
+fi
+
+
+for ac_func in time chmod utime fork execve execv chown
+do :
+ as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh`
+ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var"
+eval as_val=\$$as_ac_var
+ if test "x$as_val" = x""yes; then :
+ cat >>confdefs.h <<_ACEOF
+#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+done
+
+for ac_header in unistd.h stdlib.h string.h strings.h utime.h time.h
+do :
+ as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
+ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default"
+eval as_val=\$$as_ac_Header
+ if test "x$as_val" = x""yes; then :
+ cat >>confdefs.h <<_ACEOF
+#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+ac_sources="$sim_link_files"
+ac_dests="$sim_link_links"
+while test -n "$ac_sources"; do
+ set $ac_dests; ac_dest=$1; shift; ac_dests=$*
+ set $ac_sources; ac_source=$1; shift; ac_sources=$*
+ ac_config_links_1="$ac_config_links_1 $ac_dest:$ac_source"
+done
+ac_config_links="$ac_config_links $ac_config_links_1"
+
+cgen_breaks=""
+if grep CGEN_MAINT $srcdir/Makefile.in >/dev/null; then
+cgen_breaks="break cgen_rtx_error";
+fi
+
+ac_config_files="$ac_config_files Makefile.sim:Makefile.in"
+
+ac_config_files="$ac_config_files Make-common.sim:../common/Make-common.in"
+
+ac_config_files="$ac_config_files .gdbinit:../common/gdbinit.in"
+
+ac_config_commands="$ac_config_commands Makefile"
+
+ac_config_commands="$ac_config_commands stamp-h"
+
+cat >confcache <<\_ACEOF
+# This file is a shell script that caches the results of configure
+# tests run on this system so they can be shared between configure
+# scripts and configure runs, see configure's option --config-cache.
+# It is not useful on other systems. If it contains results you don't
+# want to keep, you may remove or edit it.
+#
+# config.status only pays attention to the cache file if you give it
+# the --recheck option to rerun configure.
+#
+# `ac_cv_env_foo' variables (set or unset) will be overridden when
+# loading this file, other *unset* `ac_cv_foo' will be assigned the
+# following values.
+
+_ACEOF
+
+# The following way of writing the cache mishandles newlines in values,
+# but we know of no workaround that is simple, portable, and efficient.
+# So, we kill variables containing newlines.
+# Ultrix sh set writes to stderr and can't be redirected directly,
+# and sets the high bit in the cache file unless we assign to the vars.
+(
+ for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do
+ eval ac_val=\$$ac_var
+ case $ac_val in #(
+ *${as_nl}*)
+ case $ac_var in #(
+ *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5
+$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;;
+ esac
+ case $ac_var in #(
+ _ | IFS | as_nl) ;; #(
+ BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #(
+ *) { eval $ac_var=; unset $ac_var;} ;;
+ esac ;;
+ esac
+ done
+
+ (set) 2>&1 |
+ case $as_nl`(ac_space=' '; set) 2>&1` in #(
+ *${as_nl}ac_space=\ *)
+ # `set' does not quote correctly, so add quotes: double-quote
+ # substitution turns \\\\ into \\, and sed turns \\ into \.
+ sed -n \
+ "s/'/'\\\\''/g;
+ s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p"
+ ;; #(
+ *)
+ # `set' quotes correctly as required by POSIX, so do not add quotes.
+ sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p"
+ ;;
+ esac |
+ sort
+) |
+ sed '
+ /^ac_cv_env_/b end
+ t clear
+ :clear
+ s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/
+ t end
+ s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/
+ :end' >>confcache
+if diff "$cache_file" confcache >/dev/null 2>&1; then :; else
+ if test -w "$cache_file"; then
+ test "x$cache_file" != "x/dev/null" &&
+ { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5
+$as_echo "$as_me: updating cache $cache_file" >&6;}
+ cat confcache >$cache_file
+ else
+ { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5
+$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;}
+ fi
+fi
+rm -f confcache
+
+test "x$prefix" = xNONE && prefix=$ac_default_prefix
+# Let make expand exec_prefix.
+test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
+
+DEFS=-DHAVE_CONFIG_H
+
+ac_libobjs=
+ac_ltlibobjs=
+for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue
+ # 1. Remove the extension, and $U if already installed.
+ ac_script='s/\$U\././;s/\.o$//;s/\.obj$//'
+ ac_i=`$as_echo "$ac_i" | sed "$ac_script"`
+ # 2. Prepend LIBOBJDIR. When used with automake>=1.10 LIBOBJDIR
+ # will be set to the directory where LIBOBJS objects are built.
+ as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext"
+ as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo'
+done
+LIBOBJS=$ac_libobjs
+
+LTLIBOBJS=$ac_ltlibobjs
+
+
+
+
+: ${CONFIG_STATUS=./config.status}
+ac_write_fail=0
+ac_clean_files_save=$ac_clean_files
+ac_clean_files="$ac_clean_files $CONFIG_STATUS"
+{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5
+$as_echo "$as_me: creating $CONFIG_STATUS" >&6;}
+as_write_fail=0
+cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1
+#! $SHELL
+# Generated by $as_me.
+# Run this file to recreate the current configuration.
+# Compiler output produced by configure, useful for debugging
+# configure, is in config.log if it exists.
+
+debug=false
+ac_cs_recheck=false
+ac_cs_silent=false
+
+SHELL=\${CONFIG_SHELL-$SHELL}
+export SHELL
+_ASEOF
+cat >>$CONFIG_STATUS <<\_ASEOF || as_write_fail=1
+## -------------------- ##
+## M4sh Initialization. ##
+## -------------------- ##
+
+# Be more Bourne compatible
+DUALCASE=1; export DUALCASE # for MKS sh
+if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then :
+ emulate sh
+ NULLCMD=:
+ # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which
+ # is contrary to our usage. Disable this feature.
+ alias -g '${1+"$@"}'='"$@"'
+ setopt NO_GLOB_SUBST
+else
+ case `(set -o) 2>/dev/null` in #(
+ *posix*) :
+ set -o posix ;; #(
+ *) :
+ ;;
+esac
+fi
+
+
+as_nl='
+'
+export as_nl
+# Printing a long string crashes Solaris 7 /usr/bin/printf.
+as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
+as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo
+as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo
+# Prefer a ksh shell builtin over an external printf program on Solaris,
+# but without wasting forks for bash or zsh.
+if test -z "$BASH_VERSION$ZSH_VERSION" \
+ && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then
+ as_echo='print -r --'
+ as_echo_n='print -rn --'
+elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then
+ as_echo='printf %s\n'
+ as_echo_n='printf %s'
+else
+ if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then
+ as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"'
+ as_echo_n='/usr/ucb/echo -n'
+ else
+ as_echo_body='eval expr "X$1" : "X\\(.*\\)"'
+ as_echo_n_body='eval
+ arg=$1;
+ case $arg in #(
+ *"$as_nl"*)
+ expr "X$arg" : "X\\(.*\\)$as_nl";
+ arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;;
+ esac;
+ expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl"
+ '
+ export as_echo_n_body
+ as_echo_n='sh -c $as_echo_n_body as_echo'
+ fi
+ export as_echo_body
+ as_echo='sh -c $as_echo_body as_echo'
+fi
+
+# The user is always right.
+if test "${PATH_SEPARATOR+set}" != set; then
+ PATH_SEPARATOR=:
+ (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && {
+ (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 ||
+ PATH_SEPARATOR=';'
+ }
+fi
+
+
+# IFS
+# We need space, tab and new line, in precisely that order. Quoting is
+# there to prevent editors from complaining about space-tab.
+# (If _AS_PATH_WALK were called with IFS unset, it would disable word
+# splitting by setting IFS to empty value.)
+IFS=" "" $as_nl"
+
+# Find who we are. Look in the path if we contain no directory separator.
+case $0 in #((
+ *[\\/]* ) as_myself=$0 ;;
+ *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
+ done
+IFS=$as_save_IFS
+
+ ;;
+esac
+# We did not find ourselves, most probably we were run as `sh COMMAND'
+# in which case we are not to be found in the path.
+if test "x$as_myself" = x; then
+ as_myself=$0
+fi
+if test ! -f "$as_myself"; then
+ $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2
+ exit 1
+fi
+
+# Unset variables that we do not need and which cause bugs (e.g. in
+# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1"
+# suppresses any "Segmentation fault" message there. '((' could
+# trigger a bug in pdksh 5.2.14.
+for as_var in BASH_ENV ENV MAIL MAILPATH
+do eval test x\${$as_var+set} = xset \
+ && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || :
+done
+PS1='$ '
+PS2='> '
+PS4='+ '
+
+# NLS nuisances.
+LC_ALL=C
+export LC_ALL
+LANGUAGE=C
+export LANGUAGE
+
+# CDPATH.
+(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
+
+
+# as_fn_error ERROR [LINENO LOG_FD]
+# ---------------------------------
+# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are
+# provided, also output the error to LOG_FD, referencing LINENO. Then exit the
+# script with status $?, using 1 if that was 0.
+as_fn_error ()
+{
+ as_status=$?; test $as_status -eq 0 && as_status=1
+ if test "$3"; then
+ as_lineno=${as_lineno-"$2"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+ $as_echo "$as_me:${as_lineno-$LINENO}: error: $1" >&$3
+ fi
+ $as_echo "$as_me: error: $1" >&2
+ as_fn_exit $as_status
+} # as_fn_error
+
+
+# as_fn_set_status STATUS
+# -----------------------
+# Set $? to STATUS, without forking.
+as_fn_set_status ()
+{
+ return $1
+} # as_fn_set_status
+
+# as_fn_exit STATUS
+# -----------------
+# Exit the shell with STATUS, even in a "trap 0" or "set -e" context.
+as_fn_exit ()
+{
+ set +e
+ as_fn_set_status $1
+ exit $1
+} # as_fn_exit
+
+# as_fn_unset VAR
+# ---------------
+# Portably unset VAR.
+as_fn_unset ()
+{
+ { eval $1=; unset $1;}
+}
+as_unset=as_fn_unset
+# as_fn_append VAR VALUE
+# ----------------------
+# Append the text in VALUE to the end of the definition contained in VAR. Take
+# advantage of any shell optimizations that allow amortized linear growth over
+# repeated appends, instead of the typical quadratic growth present in naive
+# implementations.
+if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then :
+ eval 'as_fn_append ()
+ {
+ eval $1+=\$2
+ }'
+else
+ as_fn_append ()
+ {
+ eval $1=\$$1\$2
+ }
+fi # as_fn_append
+
+# as_fn_arith ARG...
+# ------------------
+# Perform arithmetic evaluation on the ARGs, and store the result in the
+# global $as_val. Take advantage of shells that can avoid forks. The arguments
+# must be portable across $(()) and expr.
+if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then :
+ eval 'as_fn_arith ()
+ {
+ as_val=$(( $* ))
+ }'
+else
+ as_fn_arith ()
+ {
+ as_val=`expr "$@" || test $? -eq 1`
+ }
+fi # as_fn_arith
+
+
+if expr a : '\(a\)' >/dev/null 2>&1 &&
+ test "X`expr 00001 : '.*\(...\)'`" = X001; then
+ as_expr=expr
+else
+ as_expr=false
+fi
+
+if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then
+ as_basename=basename
+else
+ as_basename=false
+fi
+
+if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then
+ as_dirname=dirname
+else
+ as_dirname=false
+fi
+
+as_me=`$as_basename -- "$0" ||
+$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
+ X"$0" : 'X\(//\)$' \| \
+ X"$0" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X/"$0" |
+ sed '/^.*\/\([^/][^/]*\)\/*$/{
+ s//\1/
+ q
+ }
+ /^X\/\(\/\/\)$/{
+ s//\1/
+ q
+ }
+ /^X\/\(\/\).*/{
+ s//\1/
+ q
+ }
+ s/.*/./; q'`
+
+# Avoid depending upon Character Ranges.
+as_cr_letters='abcdefghijklmnopqrstuvwxyz'
+as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
+as_cr_Letters=$as_cr_letters$as_cr_LETTERS
+as_cr_digits='0123456789'
+as_cr_alnum=$as_cr_Letters$as_cr_digits
+
+ECHO_C= ECHO_N= ECHO_T=
+case `echo -n x` in #(((((
+-n*)
+ case `echo 'xy\c'` in
+ *c*) ECHO_T=' ';; # ECHO_T is single tab character.
+ xy) ECHO_C='\c';;
+ *) echo `echo ksh88 bug on AIX 6.1` > /dev/null
+ ECHO_T=' ';;
+ esac;;
+*)
+ ECHO_N='-n';;
+esac
+
+rm -f conf$$ conf$$.exe conf$$.file
+if test -d conf$$.dir; then
+ rm -f conf$$.dir/conf$$.file
+else
+ rm -f conf$$.dir
+ mkdir conf$$.dir 2>/dev/null
+fi
+if (echo >conf$$.file) 2>/dev/null; then
+ if ln -s conf$$.file conf$$ 2>/dev/null; then
+ as_ln_s='ln -s'
+ # ... but there are two gotchas:
+ # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail.
+ # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable.
+ # In both cases, we have to default to `cp -p'.
+ ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe ||
+ as_ln_s='cp -p'
+ elif ln conf$$.file conf$$ 2>/dev/null; then
+ as_ln_s=ln
+ else
+ as_ln_s='cp -p'
+ fi
+else
+ as_ln_s='cp -p'
+fi
+rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file
+rmdir conf$$.dir 2>/dev/null
+
+
+# as_fn_mkdir_p
+# -------------
+# Create "$as_dir" as a directory, including parents if necessary.
+as_fn_mkdir_p ()
+{
+
+ case $as_dir in #(
+ -*) as_dir=./$as_dir;;
+ esac
+ test -d "$as_dir" || eval $as_mkdir_p || {
+ as_dirs=
+ while :; do
+ case $as_dir in #(
+ *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'(
+ *) as_qdir=$as_dir;;
+ esac
+ as_dirs="'$as_qdir' $as_dirs"
+ as_dir=`$as_dirname -- "$as_dir" ||
+$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$as_dir" : 'X\(//\)[^/]' \| \
+ X"$as_dir" : 'X\(//\)$' \| \
+ X"$as_dir" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X"$as_dir" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
+ s//\1/
+ q
+ }
+ /^X\(\/\/\)[^/].*/{
+ s//\1/
+ q
+ }
+ /^X\(\/\/\)$/{
+ s//\1/
+ q
+ }
+ /^X\(\/\).*/{
+ s//\1/
+ q
+ }
+ s/.*/./; q'`
+ test -d "$as_dir" && break
+ done
+ test -z "$as_dirs" || eval "mkdir $as_dirs"
+ } || test -d "$as_dir" || as_fn_error "cannot create directory $as_dir"
+
+
+} # as_fn_mkdir_p
+if mkdir -p . 2>/dev/null; then
+ as_mkdir_p='mkdir -p "$as_dir"'
+else
+ test -d ./-p && rmdir ./-p
+ as_mkdir_p=false
+fi
+
+if test -x / >/dev/null 2>&1; then
+ as_test_x='test -x'
+else
+ if ls -dL / >/dev/null 2>&1; then
+ as_ls_L_option=L
+ else
+ as_ls_L_option=
+ fi
+ as_test_x='
+ eval sh -c '\''
+ if test -d "$1"; then
+ test -d "$1/.";
+ else
+ case $1 in #(
+ -*)set "./$1";;
+ esac;
+ case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #((
+ ???[sx]*):;;*)false;;esac;fi
+ '\'' sh
+ '
+fi
+as_executable_p=$as_test_x
+
+# Sed expression to map a string onto a valid CPP name.
+as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
+
+# Sed expression to map a string onto a valid variable name.
+as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
+
+
+exec 6>&1
+## ----------------------------------- ##
+## Main body of $CONFIG_STATUS script. ##
+## ----------------------------------- ##
+_ASEOF
+test $as_write_fail = 0 && chmod +x $CONFIG_STATUS || ac_write_fail=1
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+# Save the log message, to keep $0 and so on meaningful, and to
+# report actual input values of CONFIG_FILES etc. instead of their
+# values after options handling.
+ac_log="
+This file was extended by $as_me, which was
+generated by GNU Autoconf 2.64. Invocation command line was
+
+ CONFIG_FILES = $CONFIG_FILES
+ CONFIG_HEADERS = $CONFIG_HEADERS
+ CONFIG_LINKS = $CONFIG_LINKS
+ CONFIG_COMMANDS = $CONFIG_COMMANDS
+ $ $0 $@
+
+on `(hostname || uname -n) 2>/dev/null | sed 1q`
+"
+
+_ACEOF
+
+case $ac_config_files in *"
+"*) set x $ac_config_files; shift; ac_config_files=$*;;
+esac
+
+case $ac_config_headers in *"
+"*) set x $ac_config_headers; shift; ac_config_headers=$*;;
+esac
+
+
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+# Files that config.status was made for.
+config_files="$ac_config_files"
+config_headers="$ac_config_headers"
+config_links="$ac_config_links"
+config_commands="$ac_config_commands"
+
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+ac_cs_usage="\
+\`$as_me' instantiates files and other configuration actions
+from templates according to the current configuration. Unless the files
+and actions are specified as TAGs, all are instantiated by default.
+
+Usage: $0 [OPTION]... [TAG]...
+
+ -h, --help print this help, then exit
+ -V, --version print version number and configuration settings, then exit
+ -q, --quiet, --silent
+ do not print progress messages
+ -d, --debug don't remove temporary files
+ --recheck update $as_me by reconfiguring in the same conditions
+ --file=FILE[:TEMPLATE]
+ instantiate the configuration file FILE
+ --header=FILE[:TEMPLATE]
+ instantiate the configuration header FILE
+
+Configuration files:
+$config_files
+
+Configuration headers:
+$config_headers
+
+Configuration links:
+$config_links
+
+Configuration commands:
+$config_commands
+
+Report bugs to the package provider."
+
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ac_cs_version="\\
+config.status
+configured by $0, generated by GNU Autoconf 2.64,
+ with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\"
+
+Copyright (C) 2009 Free Software Foundation, Inc.
+This config.status script is free software; the Free Software Foundation
+gives unlimited permission to copy, distribute and modify it."
+
+ac_pwd='$ac_pwd'
+srcdir='$srcdir'
+INSTALL='$INSTALL'
+test -n "\$AWK" || AWK=awk
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+# The default lists apply if the user does not specify any file.
+ac_need_defaults=:
+while test $# != 0
+do
+ case $1 in
+ --*=*)
+ ac_option=`expr "X$1" : 'X\([^=]*\)='`
+ ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'`
+ ac_shift=:
+ ;;
+ *)
+ ac_option=$1
+ ac_optarg=$2
+ ac_shift=shift
+ ;;
+ esac
+
+ case $ac_option in
+ # Handling of the options.
+ -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
+ ac_cs_recheck=: ;;
+ --version | --versio | --versi | --vers | --ver | --ve | --v | -V )
+ $as_echo "$ac_cs_version"; exit ;;
+ --debug | --debu | --deb | --de | --d | -d )
+ debug=: ;;
+ --file | --fil | --fi | --f )
+ $ac_shift
+ case $ac_optarg in
+ *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;;
+ esac
+ as_fn_append CONFIG_FILES " '$ac_optarg'"
+ ac_need_defaults=false;;
+ --header | --heade | --head | --hea )
+ $ac_shift
+ case $ac_optarg in
+ *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;;
+ esac
+ as_fn_append CONFIG_HEADERS " '$ac_optarg'"
+ ac_need_defaults=false;;
+ --he | --h)
+ # Conflict between --help and --header
+ as_fn_error "ambiguous option: \`$1'
+Try \`$0 --help' for more information.";;
+ --help | --hel | -h )
+ $as_echo "$ac_cs_usage"; exit ;;
+ -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+ | -silent | --silent | --silen | --sile | --sil | --si | --s)
+ ac_cs_silent=: ;;
+
+ # This is an error.
+ -*) as_fn_error "unrecognized option: \`$1'
+Try \`$0 --help' for more information." ;;
+
+ *) as_fn_append ac_config_targets " $1"
+ ac_need_defaults=false ;;
+
+ esac
+ shift
+done
+
+ac_configure_extra_args=
+
+if $ac_cs_silent; then
+ exec 6>/dev/null
+ ac_configure_extra_args="$ac_configure_extra_args --silent"
+fi
+
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+if \$ac_cs_recheck; then
+ set X '$SHELL' '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion
+ shift
+ \$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6
+ CONFIG_SHELL='$SHELL'
+ export CONFIG_SHELL
+ exec "\$@"
+fi
+
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+exec 5>>config.log
+{
+ echo
+ sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX
+## Running $as_me. ##
+_ASBOX
+ $as_echo "$ac_log"
+} >&5
+
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+
+# Handling of arguments.
+for ac_config_target in $ac_config_targets
+do
+ case $ac_config_target in
+ "config.h") CONFIG_HEADERS="$CONFIG_HEADERS config.h:config.in" ;;
+ "$ac_config_links_1") CONFIG_LINKS="$CONFIG_LINKS $ac_config_links_1" ;;
+ "Makefile.sim") CONFIG_FILES="$CONFIG_FILES Makefile.sim:Makefile.in" ;;
+ "Make-common.sim") CONFIG_FILES="$CONFIG_FILES Make-common.sim:../common/Make-common.in" ;;
+ ".gdbinit") CONFIG_FILES="$CONFIG_FILES .gdbinit:../common/gdbinit.in" ;;
+ "Makefile") CONFIG_COMMANDS="$CONFIG_COMMANDS Makefile" ;;
+ "stamp-h") CONFIG_COMMANDS="$CONFIG_COMMANDS stamp-h" ;;
+
+ *) as_fn_error "invalid argument: \`$ac_config_target'" "$LINENO" 5;;
+ esac
+done
+
+
+# If the user did not use the arguments to specify the items to instantiate,
+# then the envvar interface is used. Set only those that are not.
+# We use the long form for the default assignment because of an extremely
+# bizarre bug on SunOS 4.1.3.
+if $ac_need_defaults; then
+ test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files
+ test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers
+ test "${CONFIG_LINKS+set}" = set || CONFIG_LINKS=$config_links
+ test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands
+fi
+
+# Have a temporary directory for convenience. Make it in the build tree
+# simply because there is no reason against having it here, and in addition,
+# creating and moving files from /tmp can sometimes cause problems.
+# Hook for its removal unless debugging.
+# Note that there is a small window in which the directory will not be cleaned:
+# after its creation but before its name has been assigned to `$tmp'.
+$debug ||
+{
+ tmp=
+ trap 'exit_status=$?
+ { test -z "$tmp" || test ! -d "$tmp" || rm -fr "$tmp"; } && exit $exit_status
+' 0
+ trap 'as_fn_exit 1' 1 2 13 15
+}
+# Create a (secure) tmp directory for tmp files.
+
+{
+ tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` &&
+ test -n "$tmp" && test -d "$tmp"
+} ||
+{
+ tmp=./conf$$-$RANDOM
+ (umask 077 && mkdir "$tmp")
+} || as_fn_error "cannot create a temporary directory in ." "$LINENO" 5
+
+# Set up the scripts for CONFIG_FILES section.
+# No need to generate them if there are no CONFIG_FILES.
+# This happens for instance with `./config.status config.h'.
+if test -n "$CONFIG_FILES"; then
+
+
+ac_cr=`echo X | tr X '\015'`
+# On cygwin, bash can eat \r inside `` if the user requested igncr.
+# But we know of no other shell where ac_cr would be empty at this
+# point, so we can use a bashism as a fallback.
+if test "x$ac_cr" = x; then
+ eval ac_cr=\$\'\\r\'
+fi
+ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' /dev/null`
+if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then
+ ac_cs_awk_cr='\r'
+else
+ ac_cs_awk_cr=$ac_cr
+fi
+
+echo 'BEGIN {' >"$tmp/subs1.awk" &&
+_ACEOF
+
+
+{
+ echo "cat >conf$$subs.awk <<_ACEOF" &&
+ echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' &&
+ echo "_ACEOF"
+} >conf$$subs.sh ||
+ as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5
+ac_delim_num=`echo "$ac_subst_vars" | grep -c '$'`
+ac_delim='%!_!# '
+for ac_last_try in false false false false false :; do
+ . ./conf$$subs.sh ||
+ as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5
+
+ ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X`
+ if test $ac_delim_n = $ac_delim_num; then
+ break
+ elif $ac_last_try; then
+ as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5
+ else
+ ac_delim="$ac_delim!$ac_delim _$ac_delim!! "
+ fi
+done
+rm -f conf$$subs.sh
+
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+cat >>"\$tmp/subs1.awk" <<\\_ACAWK &&
+_ACEOF
+sed -n '
+h
+s/^/S["/; s/!.*/"]=/
+p
+g
+s/^[^!]*!//
+:repl
+t repl
+s/'"$ac_delim"'$//
+t delim
+:nl
+h
+s/\(.\{148\}\).*/\1/
+t more1
+s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/
+p
+n
+b repl
+:more1
+s/["\\]/\\&/g; s/^/"/; s/$/"\\/
+p
+g
+s/.\{148\}//
+t nl
+:delim
+h
+s/\(.\{148\}\).*/\1/
+t more2
+s/["\\]/\\&/g; s/^/"/; s/$/"/
+p
+b
+:more2
+s/["\\]/\\&/g; s/^/"/; s/$/"\\/
+p
+g
+s/.\{148\}//
+t delim
+' >$CONFIG_STATUS || ac_write_fail=1
+rm -f conf$$subs.awk
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+_ACAWK
+cat >>"\$tmp/subs1.awk" <<_ACAWK &&
+ for (key in S) S_is_set[key] = 1
+ FS = ""
+
+}
+{
+ line = $ 0
+ nfields = split(line, field, "@")
+ substed = 0
+ len = length(field[1])
+ for (i = 2; i < nfields; i++) {
+ key = field[i]
+ keylen = length(key)
+ if (S_is_set[key]) {
+ value = S[key]
+ line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3)
+ len += length(value) + length(field[++i])
+ substed = 1
+ } else
+ len += 1 + keylen
+ }
+
+ print line
+}
+
+_ACAWK
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then
+ sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g"
+else
+ cat
+fi < "$tmp/subs1.awk" > "$tmp/subs.awk" \
+ || as_fn_error "could not setup config files machinery" "$LINENO" 5
+_ACEOF
+
+# VPATH may cause trouble with some makes, so we remove $(srcdir),
+# ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and
+# trailing colons and then remove the whole line if VPATH becomes empty
+# (actually we leave an empty line to preserve line numbers).
+if test "x$srcdir" = x.; then
+ ac_vpsub='/^[ ]*VPATH[ ]*=/{
+s/:*\$(srcdir):*/:/
+s/:*\${srcdir}:*/:/
+s/:*@srcdir@:*/:/
+s/^\([^=]*=[ ]*\):*/\1/
+s/:*$//
+s/^[^=]*=[ ]*$//
+}'
+fi
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+fi # test -n "$CONFIG_FILES"
+
+# Set up the scripts for CONFIG_HEADERS section.
+# No need to generate them if there are no CONFIG_HEADERS.
+# This happens for instance with `./config.status Makefile'.
+if test -n "$CONFIG_HEADERS"; then
+cat >"$tmp/defines.awk" <<\_ACAWK ||
+BEGIN {
+_ACEOF
+
+# Transform confdefs.h into an awk script `defines.awk', embedded as
+# here-document in config.status, that substitutes the proper values into
+# config.h.in to produce config.h.
+
+# Create a delimiter string that does not exist in confdefs.h, to ease
+# handling of long lines.
+ac_delim='%!_!# '
+for ac_last_try in false false :; do
+ ac_t=`sed -n "/$ac_delim/p" confdefs.h`
+ if test -z "$ac_t"; then
+ break
+ elif $ac_last_try; then
+ as_fn_error "could not make $CONFIG_HEADERS" "$LINENO" 5
+ else
+ ac_delim="$ac_delim!$ac_delim _$ac_delim!! "
+ fi
+done
+
+# For the awk script, D is an array of macro values keyed by name,
+# likewise P contains macro parameters if any. Preserve backslash
+# newline sequences.
+
+ac_word_re=[_$as_cr_Letters][_$as_cr_alnum]*
+sed -n '
+s/.\{148\}/&'"$ac_delim"'/g
+t rset
+:rset
+s/^[ ]*#[ ]*define[ ][ ]*/ /
+t def
+d
+:def
+s/\\$//
+t bsnl
+s/["\\]/\\&/g
+s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\
+D["\1"]=" \3"/p
+s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2"/p
+d
+:bsnl
+s/["\\]/\\&/g
+s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\
+D["\1"]=" \3\\\\\\n"\\/p
+t cont
+s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2\\\\\\n"\\/p
+t cont
+d
+:cont
+n
+s/.\{148\}/&'"$ac_delim"'/g
+t clear
+:clear
+s/\\$//
+t bsnlc
+s/["\\]/\\&/g; s/^/"/; s/$/"/p
+d
+:bsnlc
+s/["\\]/\\&/g; s/^/"/; s/$/\\\\\\n"\\/p
+b cont
+' >$CONFIG_STATUS || ac_write_fail=1
+
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ for (key in D) D_is_set[key] = 1
+ FS = ""
+}
+/^[\t ]*#[\t ]*(define|undef)[\t ]+$ac_word_re([\t (]|\$)/ {
+ line = \$ 0
+ split(line, arg, " ")
+ if (arg[1] == "#") {
+ defundef = arg[2]
+ mac1 = arg[3]
+ } else {
+ defundef = substr(arg[1], 2)
+ mac1 = arg[2]
+ }
+ split(mac1, mac2, "(") #)
+ macro = mac2[1]
+ prefix = substr(line, 1, index(line, defundef) - 1)
+ if (D_is_set[macro]) {
+ # Preserve the white space surrounding the "#".
+ print prefix "define", macro P[macro] D[macro]
+ next
+ } else {
+ # Replace #undef with comments. This is necessary, for example,
+ # in the case of _POSIX_SOURCE, which is predefined and required
+ # on some systems where configure will not decide to define it.
+ if (defundef == "undef") {
+ print "/*", prefix defundef, macro, "*/"
+ next
+ }
+ }
+}
+{ print }
+_ACAWK
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+ as_fn_error "could not setup config headers machinery" "$LINENO" 5
+fi # test -n "$CONFIG_HEADERS"
+
+
+eval set X " :F $CONFIG_FILES :H $CONFIG_HEADERS :L $CONFIG_LINKS :C $CONFIG_COMMANDS"
+shift
+for ac_tag
+do
+ case $ac_tag in
+ :[FHLC]) ac_mode=$ac_tag; continue;;
+ esac
+ case $ac_mode$ac_tag in
+ :[FHL]*:*);;
+ :L* | :C*:*) as_fn_error "invalid tag \`$ac_tag'" "$LINENO" 5;;
+ :[FH]-) ac_tag=-:-;;
+ :[FH]*) ac_tag=$ac_tag:$ac_tag.in;;
+ esac
+ ac_save_IFS=$IFS
+ IFS=:
+ set x $ac_tag
+ IFS=$ac_save_IFS
+ shift
+ ac_file=$1
+ shift
+
+ case $ac_mode in
+ :L) ac_source=$1;;
+ :[FH])
+ ac_file_inputs=
+ for ac_f
+ do
+ case $ac_f in
+ -) ac_f="$tmp/stdin";;
+ *) # Look for the file first in the build tree, then in the source tree
+ # (if the path is not absolute). The absolute path cannot be DOS-style,
+ # because $ac_f cannot contain `:'.
+ test -f "$ac_f" ||
+ case $ac_f in
+ [\\/$]*) false;;
+ *) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";;
+ esac ||
+ as_fn_error "cannot find input file: \`$ac_f'" "$LINENO" 5;;
+ esac
+ case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac
+ as_fn_append ac_file_inputs " '$ac_f'"
+ done
+
+ # Let's still pretend it is `configure' which instantiates (i.e., don't
+ # use $as_me), people would be surprised to read:
+ # /* config.h. Generated by config.status. */
+ configure_input='Generated from '`
+ $as_echo "$*" | sed 's|^[^:]*/||;s|:[^:]*/|, |g'
+ `' by configure.'
+ if test x"$ac_file" != x-; then
+ configure_input="$ac_file. $configure_input"
+ { $as_echo "$as_me:${as_lineno-$LINENO}: creating $ac_file" >&5
+$as_echo "$as_me: creating $ac_file" >&6;}
+ fi
+ # Neutralize special characters interpreted by sed in replacement strings.
+ case $configure_input in #(
+ *\&* | *\|* | *\\* )
+ ac_sed_conf_input=`$as_echo "$configure_input" |
+ sed 's/[\\\\&|]/\\\\&/g'`;; #(
+ *) ac_sed_conf_input=$configure_input;;
+ esac
+
+ case $ac_tag in
+ *:-:* | *:-) cat >"$tmp/stdin" \
+ || as_fn_error "could not create $ac_file" "$LINENO" 5 ;;
+ esac
+ ;;
+ esac
+
+ ac_dir=`$as_dirname -- "$ac_file" ||
+$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$ac_file" : 'X\(//\)[^/]' \| \
+ X"$ac_file" : 'X\(//\)$' \| \
+ X"$ac_file" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X"$ac_file" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
+ s//\1/
+ q
+ }
+ /^X\(\/\/\)[^/].*/{
+ s//\1/
+ q
+ }
+ /^X\(\/\/\)$/{
+ s//\1/
+ q
+ }
+ /^X\(\/\).*/{
+ s//\1/
+ q
+ }
+ s/.*/./; q'`
+ as_dir="$ac_dir"; as_fn_mkdir_p
+ ac_builddir=.
+
+case "$ac_dir" in
+.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;;
+*)
+ ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'`
+ # A ".." for each directory in $ac_dir_suffix.
+ ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'`
+ case $ac_top_builddir_sub in
+ "") ac_top_builddir_sub=. ac_top_build_prefix= ;;
+ *) ac_top_build_prefix=$ac_top_builddir_sub/ ;;
+ esac ;;
+esac
+ac_abs_top_builddir=$ac_pwd
+ac_abs_builddir=$ac_pwd$ac_dir_suffix
+# for backward compatibility:
+ac_top_builddir=$ac_top_build_prefix
+
+case $srcdir in
+ .) # We are building in place.
+ ac_srcdir=.
+ ac_top_srcdir=$ac_top_builddir_sub
+ ac_abs_top_srcdir=$ac_pwd ;;
+ [\\/]* | ?:[\\/]* ) # Absolute name.
+ ac_srcdir=$srcdir$ac_dir_suffix;
+ ac_top_srcdir=$srcdir
+ ac_abs_top_srcdir=$srcdir ;;
+ *) # Relative name.
+ ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix
+ ac_top_srcdir=$ac_top_build_prefix$srcdir
+ ac_abs_top_srcdir=$ac_pwd/$srcdir ;;
+esac
+ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix
+
+
+ case $ac_mode in
+ :F)
+ #
+ # CONFIG_FILE
+ #
+
+ case $INSTALL in
+ [\\/$]* | ?:[\\/]* ) ac_INSTALL=$INSTALL ;;
+ *) ac_INSTALL=$ac_top_build_prefix$INSTALL ;;
+ esac
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+# If the template does not know about datarootdir, expand it.
+# FIXME: This hack should be removed a few years after 2.60.
+ac_datarootdir_hack=; ac_datarootdir_seen=
+ac_sed_dataroot='
+/datarootdir/ {
+ p
+ q
+}
+/@datadir@/p
+/@docdir@/p
+/@infodir@/p
+/@localedir@/p
+/@mandir@/p'
+case `eval "sed -n \"\$ac_sed_dataroot\" $ac_file_inputs"` in
+*datarootdir*) ac_datarootdir_seen=yes;;
+*@datadir@*|*@docdir@*|*@infodir@*|*@localedir@*|*@mandir@*)
+ { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&5
+$as_echo "$as_me: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&2;}
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ ac_datarootdir_hack='
+ s&@datadir@&$datadir&g
+ s&@docdir@&$docdir&g
+ s&@infodir@&$infodir&g
+ s&@localedir@&$localedir&g
+ s&@mandir@&$mandir&g
+ s&\\\${datarootdir}&$datarootdir&g' ;;
+esac
+_ACEOF
+
+# Neutralize VPATH when `$srcdir' = `.'.
+# Shell code in configure.ac might set extrasub.
+# FIXME: do we really want to maintain this feature?
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ac_sed_extra="$ac_vpsub
+$extrasub
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+:t
+/@[a-zA-Z_][a-zA-Z_0-9]*@/!b
+s|@configure_input@|$ac_sed_conf_input|;t t
+s&@top_builddir@&$ac_top_builddir_sub&;t t
+s&@top_build_prefix@&$ac_top_build_prefix&;t t
+s&@srcdir@&$ac_srcdir&;t t
+s&@abs_srcdir@&$ac_abs_srcdir&;t t
+s&@top_srcdir@&$ac_top_srcdir&;t t
+s&@abs_top_srcdir@&$ac_abs_top_srcdir&;t t
+s&@builddir@&$ac_builddir&;t t
+s&@abs_builddir@&$ac_abs_builddir&;t t
+s&@abs_top_builddir@&$ac_abs_top_builddir&;t t
+s&@INSTALL@&$ac_INSTALL&;t t
+$ac_datarootdir_hack
+"
+eval sed \"\$ac_sed_extra\" "$ac_file_inputs" | $AWK -f "$tmp/subs.awk" >$tmp/out \
+ || as_fn_error "could not create $ac_file" "$LINENO" 5
+
+test -z "$ac_datarootdir_hack$ac_datarootdir_seen" &&
+ { ac_out=`sed -n '/\${datarootdir}/p' "$tmp/out"`; test -n "$ac_out"; } &&
+ { ac_out=`sed -n '/^[ ]*datarootdir[ ]*:*=/p' "$tmp/out"`; test -z "$ac_out"; } &&
+ { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file contains a reference to the variable \`datarootdir'
+which seems to be undefined. Please make sure it is defined." >&5
+$as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir'
+which seems to be undefined. Please make sure it is defined." >&2;}
+
+ rm -f "$tmp/stdin"
+ case $ac_file in
+ -) cat "$tmp/out" && rm -f "$tmp/out";;
+ *) rm -f "$ac_file" && mv "$tmp/out" "$ac_file";;
+ esac \
+ || as_fn_error "could not create $ac_file" "$LINENO" 5
+ ;;
+ :H)
+ #
+ # CONFIG_HEADER
+ #
+ if test x"$ac_file" != x-; then
+ {
+ $as_echo "/* $configure_input */" \
+ && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs"
+ } >"$tmp/config.h" \
+ || as_fn_error "could not create $ac_file" "$LINENO" 5
+ if diff "$ac_file" "$tmp/config.h" >/dev/null 2>&1; then
+ { $as_echo "$as_me:${as_lineno-$LINENO}: $ac_file is unchanged" >&5
+$as_echo "$as_me: $ac_file is unchanged" >&6;}
+ else
+ rm -f "$ac_file"
+ mv "$tmp/config.h" "$ac_file" \
+ || as_fn_error "could not create $ac_file" "$LINENO" 5
+ fi
+ else
+ $as_echo "/* $configure_input */" \
+ && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" \
+ || as_fn_error "could not create -" "$LINENO" 5
+ fi
+ ;;
+ :L)
+ #
+ # CONFIG_LINK
+ #
+
+ if test "$ac_source" = "$ac_file" && test "$srcdir" = '.'; then
+ :
+ else
+ # Prefer the file from the source tree if names are identical.
+ if test "$ac_source" = "$ac_file" || test ! -r "$ac_source"; then
+ ac_source=$srcdir/$ac_source
+ fi
+
+ { $as_echo "$as_me:${as_lineno-$LINENO}: linking $ac_source to $ac_file" >&5
+$as_echo "$as_me: linking $ac_source to $ac_file" >&6;}
+
+ if test ! -r "$ac_source"; then
+ as_fn_error "$ac_source: file not found" "$LINENO" 5
+ fi
+ rm -f "$ac_file"
+
+ # Try a relative symlink, then a hard link, then a copy.
+ case $srcdir in
+ [\\/$]* | ?:[\\/]* ) ac_rel_source=$ac_source ;;
+ *) ac_rel_source=$ac_top_build_prefix$ac_source ;;
+ esac
+ ln -s "$ac_rel_source" "$ac_file" 2>/dev/null ||
+ ln "$ac_source" "$ac_file" 2>/dev/null ||
+ cp -p "$ac_source" "$ac_file" ||
+ as_fn_error "cannot link or copy $ac_source to $ac_file" "$LINENO" 5
+ fi
+ ;;
+ :C) { $as_echo "$as_me:${as_lineno-$LINENO}: executing $ac_file commands" >&5
+$as_echo "$as_me: executing $ac_file commands" >&6;}
+ ;;
+ esac
+
+
+ case $ac_file$ac_mode in
+ "Makefile":C) echo "Merging Makefile.sim+Make-common.sim into Makefile ..."
+ rm -f Makesim1.tmp Makesim2.tmp Makefile
+ sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' Makesim1.tmp
+ sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' Makesim2.tmp
+ sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \
+ -e '/^## COMMON_POST_/ r Makesim2.tmp' \
+ Makefile
+ rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp
+ ;;
+ "stamp-h":C) echo > stamp-h ;;
+
+ esac
+done # for ac_tag
+
+
+as_fn_exit 0
+_ACEOF
+ac_clean_files=$ac_clean_files_save
+
+test $ac_write_fail = 0 ||
+ as_fn_error "write failure creating $CONFIG_STATUS" "$LINENO" 5
+
+
+# configure is writing to config.log, and then calls config.status.
+# config.status does its own redirection, appending to config.log.
+# Unfortunately, on DOS this fails, as config.log is still kept open
+# by configure, so config.status won't be able to write to it; its
+# output is simply discarded. So we exec the FD to /dev/null,
+# effectively closing config.log, so it can be properly (re)opened and
+# appended to by config.status. When coming back to configure, we
+# need to make the FD available again.
+if test "$no_create" != yes; then
+ ac_cs_success=:
+ ac_config_status_args=
+ test "$silent" = yes &&
+ ac_config_status_args="$ac_config_status_args --quiet"
+ exec 5>/dev/null
+ $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false
+ exec 5>>config.log
+ # Use ||, not &&, to avoid exiting from the if with $? = 1, which
+ # would make configure fail if this is the last instruction.
+ $ac_cs_success || as_fn_exit $?
+fi
+if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then
+ { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5
+$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;}
+fi
+
+
configure
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: Makefile.in
===================================================================
--- Makefile.in (nonexistent)
+++ Makefile.in (revision 842)
@@ -0,0 +1,127 @@
+# Makefile template for Configure for the mn10300 sim library.
+# Copyright (C) 1996, 1997, 2000, 2001, 2004, 2007, 2008, 2009, 2010
+# Free Software Foundation, Inc.
+# Written by Cygnus Support.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see
+
+#include "sim-main.h"
+#include "sim-options.h"
+#include "sim-hw.h"
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "sim-assert.h"
+
+
+#ifdef HAVE_STDLIB_H
+#include
+#endif
+
+#ifdef HAVE_STRING_H
+#include
+#else
+#ifdef HAVE_STRINGS_H
+#include
+#endif
+#endif
+
+#include "bfd.h"
+
+#ifndef INLINE
+#ifdef __GNUC__
+#define INLINE inline
+#else
+#define INLINE
+#endif
+#endif
+
+
+host_callback *mn10300_callback;
+int mn10300_debug;
+struct _state State;
+
+
+/* simulation target board. NULL=default configuration */
+static char* board = NULL;
+
+static DECLARE_OPTION_HANDLER (mn10300_option_handler);
+
+enum {
+ OPTION_BOARD = OPTION_START,
+};
+
+static SIM_RC
+mn10300_option_handler (SIM_DESC sd,
+ sim_cpu *cpu,
+ int opt,
+ char *arg,
+ int is_command)
+{
+ int cpu_nr;
+ switch (opt)
+ {
+ case OPTION_BOARD:
+ {
+ if (arg)
+ {
+ board = zalloc(strlen(arg) + 1);
+ strcpy(board, arg);
+ }
+ return SIM_RC_OK;
+ }
+ }
+
+ return SIM_RC_OK;
+}
+
+static const OPTION mn10300_options[] =
+{
+#define BOARD_AM32 "stdeval1"
+ { {"board", required_argument, NULL, OPTION_BOARD},
+ '\0', "none" /* rely on compile-time string concatenation for other options */
+ "|" BOARD_AM32
+ , "Customize simulation for a particular board.", mn10300_option_handler },
+
+ { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
+};
+
+/* For compatibility */
+SIM_DESC simulator;
+
+/* These default values correspond to expected usage for the chip. */
+
+SIM_DESC
+sim_open (SIM_OPEN_KIND kind,
+ host_callback *cb,
+ struct bfd *abfd,
+ char **argv)
+{
+ SIM_DESC sd = sim_state_alloc (kind, cb);
+ mn10300_callback = cb;
+
+ SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
+
+ /* for compatibility */
+ simulator = sd;
+
+ /* FIXME: should be better way of setting up interrupts. For
+ moment, only support watchpoints causing a breakpoint (gdb
+ halt). */
+ STATE_WATCHPOINTS (sd)->pc = &(PC);
+ STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
+ STATE_WATCHPOINTS (sd)->interrupt_handler = NULL;
+ STATE_WATCHPOINTS (sd)->interrupt_names = NULL;
+
+ if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
+ return 0;
+ sim_add_option_table (sd, NULL, mn10300_options);
+
+ /* Allocate core managed memory */
+ sim_do_command (sd, "memory region 0,0x100000");
+ sim_do_command (sd, "memory region 0x40000000,0x200000");
+
+ /* getopt will print the error message so we just have to exit if this fails.
+ FIXME: Hmmm... in the case of gdb we need getopt to call
+ print_filtered. */
+ if (sim_parse_args (sd, argv) != SIM_RC_OK)
+ {
+ /* Uninstall the modules to avoid memory leaks,
+ file descriptor leaks, etc. */
+ sim_module_uninstall (sd);
+ return 0;
+ }
+
+ if ( NULL != board
+ && (strcmp(board, BOARD_AM32) == 0 ) )
+ {
+ /* environment */
+ STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
+
+ sim_do_command (sd, "memory region 0x44000000,0x40000");
+ sim_do_command (sd, "memory region 0x48000000,0x400000");
+
+ /* device support for mn1030002 */
+ /* interrupt controller */
+
+ sim_hw_parse (sd, "/mn103int@0x34000100/reg 0x34000100 0x7C 0x34000200 0x8 0x34000280 0x8");
+
+ /* DEBUG: NMI input's */
+ sim_hw_parse (sd, "/glue@0x30000000/reg 0x30000000 12");
+ sim_hw_parse (sd, "/glue@0x30000000 > int0 nmirq /mn103int");
+ sim_hw_parse (sd, "/glue@0x30000000 > int1 watchdog /mn103int");
+ sim_hw_parse (sd, "/glue@0x30000000 > int2 syserr /mn103int");
+
+ /* DEBUG: ACK input */
+ sim_hw_parse (sd, "/glue@0x30002000/reg 0x30002000 4");
+ sim_hw_parse (sd, "/glue@0x30002000 > int ack /mn103int");
+
+ /* DEBUG: LEVEL output */
+ sim_hw_parse (sd, "/glue@0x30004000/reg 0x30004000 8");
+ sim_hw_parse (sd, "/mn103int > nmi int0 /glue@0x30004000");
+ sim_hw_parse (sd, "/mn103int > level int1 /glue@0x30004000");
+
+ /* DEBUG: A bunch of interrupt inputs */
+ sim_hw_parse (sd, "/glue@0x30006000/reg 0x30006000 32");
+ sim_hw_parse (sd, "/glue@0x30006000 > int0 irq-0 /mn103int");
+ sim_hw_parse (sd, "/glue@0x30006000 > int1 irq-1 /mn103int");
+ sim_hw_parse (sd, "/glue@0x30006000 > int2 irq-2 /mn103int");
+ sim_hw_parse (sd, "/glue@0x30006000 > int3 irq-3 /mn103int");
+ sim_hw_parse (sd, "/glue@0x30006000 > int4 irq-4 /mn103int");
+ sim_hw_parse (sd, "/glue@0x30006000 > int5 irq-5 /mn103int");
+ sim_hw_parse (sd, "/glue@0x30006000 > int6 irq-6 /mn103int");
+ sim_hw_parse (sd, "/glue@0x30006000 > int7 irq-7 /mn103int");
+
+ /* processor interrupt device */
+
+ /* the device */
+ sim_hw_parse (sd, "/mn103cpu@0x20000000");
+ sim_hw_parse (sd, "/mn103cpu@0x20000000/reg 0x20000000 0x42");
+
+ /* DEBUG: ACK output wired upto a glue device */
+ sim_hw_parse (sd, "/glue@0x20002000");
+ sim_hw_parse (sd, "/glue@0x20002000/reg 0x20002000 4");
+ sim_hw_parse (sd, "/mn103cpu > ack int0 /glue@0x20002000");
+
+ /* DEBUG: RESET/NMI/LEVEL wired up to a glue device */
+ sim_hw_parse (sd, "/glue@0x20004000");
+ sim_hw_parse (sd, "/glue@0x20004000/reg 0x20004000 12");
+ sim_hw_parse (sd, "/glue@0x20004000 > int0 reset /mn103cpu");
+ sim_hw_parse (sd, "/glue@0x20004000 > int1 nmi /mn103cpu");
+ sim_hw_parse (sd, "/glue@0x20004000 > int2 level /mn103cpu");
+
+ /* REAL: The processor wired up to the real interrupt controller */
+ sim_hw_parse (sd, "/mn103cpu > ack ack /mn103int");
+ sim_hw_parse (sd, "/mn103int > level level /mn103cpu");
+ sim_hw_parse (sd, "/mn103int > nmi nmi /mn103cpu");
+
+
+ /* PAL */
+
+ /* the device */
+ sim_hw_parse (sd, "/pal@0x31000000");
+ sim_hw_parse (sd, "/pal@0x31000000/reg 0x31000000 64");
+ sim_hw_parse (sd, "/pal@0x31000000/poll? true");
+
+ /* DEBUG: PAL wired up to a glue device */
+ sim_hw_parse (sd, "/glue@0x31002000");
+ sim_hw_parse (sd, "/glue@0x31002000/reg 0x31002000 16");
+ sim_hw_parse (sd, "/pal@0x31000000 > countdown int0 /glue@0x31002000");
+ sim_hw_parse (sd, "/pal@0x31000000 > timer int1 /glue@0x31002000");
+ sim_hw_parse (sd, "/pal@0x31000000 > int int2 /glue@0x31002000");
+ sim_hw_parse (sd, "/glue@0x31002000 > int0 int3 /glue@0x31002000");
+ sim_hw_parse (sd, "/glue@0x31002000 > int1 int3 /glue@0x31002000");
+ sim_hw_parse (sd, "/glue@0x31002000 > int2 int3 /glue@0x31002000");
+
+ /* REAL: The PAL wired up to the real interrupt controller */
+ sim_hw_parse (sd, "/pal@0x31000000 > countdown irq-0 /mn103int");
+ sim_hw_parse (sd, "/pal@0x31000000 > timer irq-1 /mn103int");
+ sim_hw_parse (sd, "/pal@0x31000000 > int irq-2 /mn103int");
+
+ /* 8 and 16 bit timers */
+ sim_hw_parse (sd, "/mn103tim@0x34001000/reg 0x34001000 36 0x34001080 100 0x34004000 16");
+
+ /* Hook timer interrupts up to interrupt controller */
+ sim_hw_parse (sd, "/mn103tim > timer-0-underflow timer-0-underflow /mn103int");
+ sim_hw_parse (sd, "/mn103tim > timer-1-underflow timer-1-underflow /mn103int");
+ sim_hw_parse (sd, "/mn103tim > timer-2-underflow timer-2-underflow /mn103int");
+ sim_hw_parse (sd, "/mn103tim > timer-3-underflow timer-3-underflow /mn103int");
+ sim_hw_parse (sd, "/mn103tim > timer-4-underflow timer-4-underflow /mn103int");
+ sim_hw_parse (sd, "/mn103tim > timer-5-underflow timer-5-underflow /mn103int");
+ sim_hw_parse (sd, "/mn103tim > timer-6-underflow timer-6-underflow /mn103int");
+ sim_hw_parse (sd, "/mn103tim > timer-6-compare-a timer-6-compare-a /mn103int");
+ sim_hw_parse (sd, "/mn103tim > timer-6-compare-b timer-6-compare-b /mn103int");
+
+
+ /* Serial devices 0,1,2 */
+ sim_hw_parse (sd, "/mn103ser@0x34000800/reg 0x34000800 48");
+ sim_hw_parse (sd, "/mn103ser@0x34000800/poll? true");
+
+ /* Hook serial interrupts up to interrupt controller */
+ sim_hw_parse (sd, "/mn103ser > serial-0-receive serial-0-receive /mn103int");
+ sim_hw_parse (sd, "/mn103ser > serial-0-transmit serial-0-transmit /mn103int");
+ sim_hw_parse (sd, "/mn103ser > serial-1-receive serial-1-receive /mn103int");
+ sim_hw_parse (sd, "/mn103ser > serial-1-transmit serial-1-transmit /mn103int");
+ sim_hw_parse (sd, "/mn103ser > serial-2-receive serial-2-receive /mn103int");
+ sim_hw_parse (sd, "/mn103ser > serial-2-transmit serial-2-transmit /mn103int");
+
+ sim_hw_parse (sd, "/mn103iop@0x36008000/reg 0x36008000 8 0x36008020 8 0x36008040 0xc 0x36008060 8 0x36008080 8");
+
+ /* Memory control registers */
+ sim_do_command (sd, "memory region 0x32000020,0x30");
+ /* Cache control register */
+ sim_do_command (sd, "memory region 0x20000070,0x4");
+ /* Cache purge regions */
+ sim_do_command (sd, "memory region 0x28400000,0x800");
+ sim_do_command (sd, "memory region 0x28401000,0x800");
+ /* DMA registers */
+ sim_do_command (sd, "memory region 0x32000100,0xF");
+ sim_do_command (sd, "memory region 0x32000200,0xF");
+ sim_do_command (sd, "memory region 0x32000400,0xF");
+ sim_do_command (sd, "memory region 0x32000800,0xF");
+ }
+ else
+ {
+ if (board != NULL)
+ {
+ sim_io_eprintf (sd, "Error: Board `%s' unknown.\n", board);
+ return 0;
+ }
+ }
+
+
+
+ /* check for/establish the a reference program image */
+ if (sim_analyze_program (sd,
+ (STATE_PROG_ARGV (sd) != NULL
+ ? *STATE_PROG_ARGV (sd)
+ : NULL),
+ abfd) != SIM_RC_OK)
+ {
+ sim_module_uninstall (sd);
+ return 0;
+ }
+
+ /* establish any remaining configuration options */
+ if (sim_config (sd) != SIM_RC_OK)
+ {
+ sim_module_uninstall (sd);
+ return 0;
+ }
+
+ if (sim_post_argv_init (sd) != SIM_RC_OK)
+ {
+ /* Uninstall the modules to avoid memory leaks,
+ file descriptor leaks, etc. */
+ sim_module_uninstall (sd);
+ return 0;
+ }
+
+
+ /* set machine specific configuration */
+/* STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT */
+/* | PSW_CY | PSW_OV | PSW_S | PSW_Z); */
+
+ return sd;
+}
+
+
+void
+sim_close (SIM_DESC sd, int quitting)
+{
+ sim_module_uninstall (sd);
+}
+
+
+SIM_RC
+sim_create_inferior (SIM_DESC sd,
+ struct bfd *prog_bfd,
+ char **argv,
+ char **env)
+{
+ memset (&State, 0, sizeof (State));
+ if (prog_bfd != NULL) {
+ PC = bfd_get_start_address (prog_bfd);
+ } else {
+ PC = 0;
+ }
+ CIA_SET (STATE_CPU (sd, 0), (unsigned64) PC);
+
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2)
+ PSW |= PSW_FE;
+
+ return SIM_RC_OK;
+}
+
+void
+sim_do_command (SIM_DESC sd, char *cmd)
+{
+ char *mm_cmd = "memory-map";
+ char *int_cmd = "interrupt";
+
+ if (sim_args_command (sd, cmd) != SIM_RC_OK)
+ {
+ if (strncmp (cmd, mm_cmd, strlen (mm_cmd) == 0))
+ sim_io_eprintf (sd, "`memory-map' command replaced by `sim memory'\n");
+ else if (strncmp (cmd, int_cmd, strlen (int_cmd)) == 0)
+ sim_io_eprintf (sd, "`interrupt' command replaced by `sim watch'\n");
+ else
+ sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
+ }
+}
+
+/* FIXME These would more efficient to use than load_mem/store_mem,
+ but need to be changed to use the memory map. */
+
+uint8
+get_byte (uint8 *x)
+{
+ return *x;
+}
+
+uint16
+get_half (uint8 *x)
+{
+ uint8 *a = x;
+ return (a[1] << 8) + (a[0]);
+}
+
+uint32
+get_word (uint8 *x)
+{
+ uint8 *a = x;
+ return (a[3]<<24) + (a[2]<<16) + (a[1]<<8) + (a[0]);
+}
+
+void
+put_byte (uint8 *addr, uint8 data)
+{
+ uint8 *a = addr;
+ a[0] = data;
+}
+
+void
+put_half (uint8 *addr, uint16 data)
+{
+ uint8 *a = addr;
+ a[0] = data & 0xff;
+ a[1] = (data >> 8) & 0xff;
+}
+
+void
+put_word (uint8 *addr, uint32 data)
+{
+ uint8 *a = addr;
+ a[0] = data & 0xff;
+ a[1] = (data >> 8) & 0xff;
+ a[2] = (data >> 16) & 0xff;
+ a[3] = (data >> 24) & 0xff;
+}
+
+int
+sim_fetch_register (SIM_DESC sd,
+ int rn,
+ unsigned char *memory,
+ int length)
+{
+ put_word (memory, State.regs[rn]);
+ return -1;
+}
+
+int
+sim_store_register (SIM_DESC sd,
+ int rn,
+ unsigned char *memory,
+ int length)
+{
+ State.regs[rn] = get_word (memory);
+ return -1;
+}
+
+
+void
+mn10300_core_signal (SIM_DESC sd,
+ sim_cpu *cpu,
+ sim_cia cia,
+ unsigned map,
+ int nr_bytes,
+ address_word addr,
+ transfer_type transfer,
+ sim_core_signals sig)
+{
+ const char *copy = (transfer == read_transfer ? "read" : "write");
+ address_word ip = CIA_ADDR (cia);
+
+ switch (sig)
+ {
+ case sim_core_unmapped_signal:
+ sim_io_eprintf (sd, "mn10300-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
+ nr_bytes, copy,
+ (unsigned long) addr, (unsigned long) ip);
+ program_interrupt(sd, cpu, cia, SIM_SIGSEGV);
+ break;
+
+ case sim_core_unaligned_signal:
+ sim_io_eprintf (sd, "mn10300-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
+ nr_bytes, copy,
+ (unsigned long) addr, (unsigned long) ip);
+ program_interrupt(sd, cpu, cia, SIM_SIGBUS);
+ break;
+
+ default:
+ sim_engine_abort (sd, cpu, cia,
+ "mn10300_core_signal - internal error - bad switch");
+ }
+}
+
+
+void
+program_interrupt (SIM_DESC sd,
+ sim_cpu *cpu,
+ sim_cia cia,
+ SIM_SIGNAL sig)
+{
+ int status;
+ struct hw *device;
+ static int in_interrupt = 0;
+
+#ifdef SIM_CPU_EXCEPTION_TRIGGER
+ SIM_CPU_EXCEPTION_TRIGGER(sd,cpu,cia);
+#endif
+
+ /* avoid infinite recursion */
+ if (in_interrupt)
+ {
+ (*mn10300_callback->printf_filtered) (mn10300_callback,
+ "ERROR: recursion in program_interrupt during software exception dispatch.");
+ }
+ else
+ {
+ in_interrupt = 1;
+ /* copy NMI handler code from dv-mn103cpu.c */
+ store_word (SP - 4, CIA_GET (cpu));
+ store_half (SP - 8, PSW);
+
+ /* Set the SYSEF flag in NMICR by backdoor method. See
+ dv-mn103int.c:write_icr(). This is necessary because
+ software exceptions are not modelled by actually talking to
+ the interrupt controller, so it cannot set its own SYSEF
+ flag. */
+ if ((NULL != board) && (strcmp(board, BOARD_AM32) == 0))
+ store_byte (0x34000103, 0x04);
+ }
+
+ PSW &= ~PSW_IE;
+ SP = SP - 8;
+ CIA_SET (cpu, 0x40000008);
+
+ in_interrupt = 0;
+ sim_engine_halt(sd, cpu, NULL, cia, sim_stopped, sig);
+}
+
+
+void
+mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia)
+{
+ ASSERT(cpu != NULL);
+
+ if(State.exc_suspended > 0)
+ sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", State.exc_suspended);
+
+ CIA_SET (cpu, cia);
+ memcpy(State.exc_trigger_regs, State.regs, sizeof(State.exc_trigger_regs));
+ State.exc_suspended = 0;
+}
+
+void
+mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception)
+{
+ ASSERT(cpu != NULL);
+
+ if(State.exc_suspended > 0)
+ sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n",
+ State.exc_suspended, exception);
+
+ memcpy(State.exc_suspend_regs, State.regs, sizeof(State.exc_suspend_regs));
+ memcpy(State.regs, State.exc_trigger_regs, sizeof(State.regs));
+ CIA_SET (cpu, PC); /* copy PC back from new State.regs */
+ State.exc_suspended = exception;
+}
+
+void
+mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception)
+{
+ ASSERT(cpu != NULL);
+
+ if(exception == 0 && State.exc_suspended > 0)
+ {
+ if(State.exc_suspended != SIGTRAP) /* warn not for breakpoints */
+ sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n",
+ State.exc_suspended);
+ }
+ else if(exception != 0 && State.exc_suspended > 0)
+ {
+ if(exception != State.exc_suspended)
+ sim_io_eprintf(sd, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
+ State.exc_suspended, exception);
+
+ memcpy(State.regs, State.exc_suspend_regs, sizeof(State.regs));
+ CIA_SET (cpu, PC); /* copy PC back from new State.regs */
+ }
+ else if(exception != 0 && State.exc_suspended == 0)
+ {
+ sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
+ }
+ State.exc_suspended = 0;
+}
+
+/* This is called when an FP instruction is issued when the FP unit is
+ disabled, i.e., the FE bit of PSW is zero. It raises interrupt
+ code 0x1c0. */
+void
+fpu_disabled_exception (SIM_DESC sd, sim_cpu *cpu, sim_cia cia)
+{
+ sim_io_eprintf(sd, "FPU disabled exception\n");
+ program_interrupt (sd, cpu, cia, SIM_SIGFPE);
+}
+
+/* This is called when the FP unit is enabled but one of the
+ unimplemented insns is issued. It raises interrupt code 0x1c8. */
+void
+fpu_unimp_exception (SIM_DESC sd, sim_cpu *cpu, sim_cia cia)
+{
+ sim_io_eprintf(sd, "Unimplemented FPU instruction exception\n");
+ program_interrupt (sd, cpu, cia, SIM_SIGFPE);
+}
+
+/* This is called at the end of any FP insns that may have triggered
+ FP exceptions. If no exception is enabled, it returns immediately.
+ Otherwise, it raises an exception code 0x1d0. */
+void
+fpu_check_signal_exception (SIM_DESC sd, sim_cpu *cpu, sim_cia cia)
+{
+ if ((FPCR & EC_MASK) == 0)
+ return;
+
+ sim_io_eprintf(sd, "FPU %s%s%s%s%s exception\n",
+ (FPCR & EC_V) ? "V" : "",
+ (FPCR & EC_Z) ? "Z" : "",
+ (FPCR & EC_O) ? "O" : "",
+ (FPCR & EC_U) ? "U" : "",
+ (FPCR & EC_I) ? "I" : "");
+ program_interrupt (sd, cpu, cia, SIM_SIGFPE);
+}
+
+/* Convert a 32-bit single-precision FP value in the target platform
+ format to a sim_fpu value. */
+static void
+reg2val_32 (const void *reg, sim_fpu *val)
+{
+ FS2FPU (*(reg_t *)reg, *val);
+}
+
+/* Round the given sim_fpu value to single precision, following the
+ target platform rounding and denormalization conventions. On
+ AM33/2.0, round_near is the only rounding mode. */
+static int
+round_32 (sim_fpu *val)
+{
+ return sim_fpu_round_32 (val, sim_fpu_round_near, sim_fpu_denorm_zero);
+}
+
+/* Convert a sim_fpu value to the 32-bit single-precision target
+ representation. */
+static void
+val2reg_32 (const sim_fpu *val, void *reg)
+{
+ FPU2FS (*val, *(reg_t *)reg);
+}
+
+/* Define the 32-bit single-precision conversion and rounding uniform
+ interface. */
+const struct fp_prec_t
+fp_single_prec = {
+ reg2val_32, round_32, val2reg_32
+};
+
+/* Convert a 64-bit double-precision FP value in the target platform
+ format to a sim_fpu value. */
+static void
+reg2val_64 (const void *reg, sim_fpu *val)
+{
+ FD2FPU (*(dword *)reg, *val);
+}
+
+/* Round the given sim_fpu value to double precision, following the
+ target platform rounding and denormalization conventions. On
+ AM33/2.0, round_near is the only rounding mode. */
+int
+round_64 (sim_fpu *val)
+{
+ return sim_fpu_round_64 (val, sim_fpu_round_near, sim_fpu_denorm_zero);
+}
+
+/* Convert a sim_fpu value to the 64-bit double-precision target
+ representation. */
+static void
+val2reg_64 (const sim_fpu *val, void *reg)
+{
+ FPU2FD (*val, *(dword *)reg);
+}
+
+/* Define the 64-bit single-precision conversion and rounding uniform
+ interface. */
+const struct fp_prec_t
+fp_double_prec = {
+ reg2val_64, round_64, val2reg_64
+};
+
+/* Define shortcuts to the uniform interface operations. */
+#define REG2VAL(reg,val) (*ops->reg2val) (reg,val)
+#define ROUND(val) (*ops->round) (val)
+#define VAL2REG(val,reg) (*ops->val2reg) (val,reg)
+
+/* Check whether overflow, underflow or inexact exceptions should be
+ raised. */
+int
+fpu_status_ok (sim_fpu_status stat)
+{
+ if ((stat & sim_fpu_status_overflow)
+ && (FPCR & EE_O))
+ FPCR |= EC_O;
+ else if ((stat & (sim_fpu_status_underflow | sim_fpu_status_denorm))
+ && (FPCR & EE_U))
+ FPCR |= EC_U;
+ else if ((stat & (sim_fpu_status_inexact | sim_fpu_status_rounded))
+ && (FPCR & EE_I))
+ FPCR |= EC_I;
+ else if (stat & ~ (sim_fpu_status_overflow
+ | sim_fpu_status_underflow
+ | sim_fpu_status_denorm
+ | sim_fpu_status_inexact
+ | sim_fpu_status_rounded))
+ abort ();
+ else
+ return 1;
+ return 0;
+}
+
+/* Implement a 32/64 bit reciprocal square root, signaling FP
+ exceptions when appropriate. */
+void
+fpu_rsqrt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in, void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu in, med, out;
+
+ REG2VAL (reg_in, &in);
+ ROUND (&in);
+ FPCR &= ~ EC_MASK;
+ switch (sim_fpu_is (&in))
+ {
+ case SIM_FPU_IS_SNAN:
+ case SIM_FPU_IS_NNUMBER:
+ case SIM_FPU_IS_NINF:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ break;
+
+ case SIM_FPU_IS_QNAN:
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ break;
+
+ case SIM_FPU_IS_PINF:
+ VAL2REG (&sim_fpu_zero, reg_out);
+ break;
+
+ case SIM_FPU_IS_PNUMBER:
+ {
+ /* Since we don't have a function to compute rsqrt directly,
+ use sqrt and inv. */
+ sim_fpu_status stat = 0;
+ stat |= sim_fpu_sqrt (&med, &in);
+ stat |= sim_fpu_inv (&out, &med);
+ stat |= ROUND (&out);
+ if (fpu_status_ok (stat))
+ VAL2REG (&out, reg_out);
+ }
+ break;
+
+ case SIM_FPU_IS_NZERO:
+ case SIM_FPU_IS_PZERO:
+ if (FPCR & EE_Z)
+ FPCR |= EC_Z;
+ else
+ {
+ /* Generate an INF with the same sign. */
+ sim_fpu_inv (&out, &in);
+ VAL2REG (&out, reg_out);
+ }
+ break;
+
+ default:
+ abort ();
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+static inline reg_t
+cmp2fcc (int res)
+{
+ switch (res)
+ {
+ case SIM_FPU_IS_SNAN:
+ case SIM_FPU_IS_QNAN:
+ return FCC_U;
+
+ case SIM_FPU_IS_NINF:
+ case SIM_FPU_IS_NNUMBER:
+ case SIM_FPU_IS_NDENORM:
+ return FCC_L;
+
+ case SIM_FPU_IS_PINF:
+ case SIM_FPU_IS_PNUMBER:
+ case SIM_FPU_IS_PDENORM:
+ return FCC_G;
+
+ case SIM_FPU_IS_NZERO:
+ case SIM_FPU_IS_PZERO:
+ return FCC_E;
+
+ default:
+ abort ();
+ }
+}
+
+/* Implement a 32/64 bit FP compare, setting the FPCR status and/or
+ exception bits as specified. */
+void
+fpu_cmp (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2,
+ const struct fp_prec_t *ops)
+{
+ sim_fpu m, n;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ FPCR &= ~ EC_MASK;
+ FPCR &= ~ FCC_MASK;
+ ROUND (&m);
+ ROUND (&n);
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ FPCR |= FCC_U;
+ }
+ else
+ FPCR |= cmp2fcc (sim_fpu_cmp (&m, &n));
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP add, setting FP exception bits when
+ appropriate. */
+void
+fpu_add (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m, n, r;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ ROUND (&m);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is (&m) == SIM_FPU_IS_PINF
+ && sim_fpu_is (&n) == SIM_FPU_IS_NINF)
+ || (sim_fpu_is (&m) == SIM_FPU_IS_NINF
+ && sim_fpu_is (&n) == SIM_FPU_IS_PINF))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_add (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP sub, setting FP exception bits when
+ appropriate. */
+void
+fpu_sub (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m, n, r;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ ROUND (&m);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is (&m) == SIM_FPU_IS_PINF
+ && sim_fpu_is (&n) == SIM_FPU_IS_PINF)
+ || (sim_fpu_is (&m) == SIM_FPU_IS_NINF
+ && sim_fpu_is (&n) == SIM_FPU_IS_NINF))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_sub (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP mul, setting FP exception bits when
+ appropriate. */
+void
+fpu_mul (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m, n, r;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ ROUND (&m);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m) && sim_fpu_is_zero (&n))
+ || (sim_fpu_is_zero (&m) && sim_fpu_is_infinity (&n)))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP div, setting FP exception bits when
+ appropriate. */
+void
+fpu_div (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m, n, r;
+
+ REG2VAL (reg_in1, &m);
+ REG2VAL (reg_in2, &n);
+ ROUND (&m);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n))
+ || (sim_fpu_is_zero (&m) && sim_fpu_is_zero (&n)))
+ {
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else if (sim_fpu_is_number (&m) && sim_fpu_is_zero (&n)
+ && (FPCR & EE_Z))
+ FPCR |= EC_Z;
+ else
+ {
+ sim_fpu_status stat = sim_fpu_div (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP madd, setting FP exception bits when
+ appropriate. */
+void
+fpu_fmadd (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2, const void *reg_in3,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m1, m2, m, n, r;
+
+ REG2VAL (reg_in1, &m1);
+ REG2VAL (reg_in2, &m2);
+ REG2VAL (reg_in3, &n);
+ ROUND (&m1);
+ ROUND (&m2);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+ || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+ {
+ invalid_operands:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+ if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+ && sim_fpu_sign (&m) != sim_fpu_sign (&n))
+ goto invalid_operands;
+
+ stat |= sim_fpu_add (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP msub, setting FP exception bits when
+ appropriate. */
+void
+fpu_fmsub (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2, const void *reg_in3,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m1, m2, m, n, r;
+
+ REG2VAL (reg_in1, &m1);
+ REG2VAL (reg_in2, &m2);
+ REG2VAL (reg_in3, &n);
+ ROUND (&m1);
+ ROUND (&m2);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+ || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+ {
+ invalid_operands:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+ if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+ && sim_fpu_sign (&m) == sim_fpu_sign (&n))
+ goto invalid_operands;
+
+ stat |= sim_fpu_sub (&r, &m, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP nmadd, setting FP exception bits when
+ appropriate. */
+void
+fpu_fnmadd (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2, const void *reg_in3,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m1, m2, m, mm, n, r;
+
+ REG2VAL (reg_in1, &m1);
+ REG2VAL (reg_in2, &m2);
+ REG2VAL (reg_in3, &n);
+ ROUND (&m1);
+ ROUND (&m2);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+ || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+ {
+ invalid_operands:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+ if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+ && sim_fpu_sign (&m) == sim_fpu_sign (&n))
+ goto invalid_operands;
+
+ stat |= sim_fpu_neg (&mm, &m);
+ stat |= sim_fpu_add (&r, &mm, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
+
+/* Implement a 32/64 bit FP nmsub, setting FP exception bits when
+ appropriate. */
+void
+fpu_fnmsub (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
+ const void *reg_in1, const void *reg_in2, const void *reg_in3,
+ void *reg_out, const struct fp_prec_t *ops)
+{
+ sim_fpu m1, m2, m, mm, n, r;
+
+ REG2VAL (reg_in1, &m1);
+ REG2VAL (reg_in2, &m2);
+ REG2VAL (reg_in3, &n);
+ ROUND (&m1);
+ ROUND (&m2);
+ ROUND (&n);
+ FPCR &= ~ EC_MASK;
+ if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
+ || (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
+ || (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
+ {
+ invalid_operands:
+ if (FPCR & EE_V)
+ FPCR |= EC_V;
+ else
+ VAL2REG (&sim_fpu_qnan, reg_out);
+ }
+ else
+ {
+ sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
+
+ if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
+ && sim_fpu_sign (&m) != sim_fpu_sign (&n))
+ goto invalid_operands;
+
+ stat |= sim_fpu_neg (&mm, &m);
+ stat |= sim_fpu_sub (&r, &mm, &n);
+ stat |= ROUND (&r);
+ if (fpu_status_ok (stat))
+ VAL2REG (&r, reg_out);
+ }
+
+ fpu_check_signal_exception (sd, cpu, cia);
+}
interp.c
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: am33-2.igen
===================================================================
--- am33-2.igen (nonexistent)
+++ am33-2.igen (revision 842)
@@ -0,0 +1,2285 @@
+// data cache pre-fetch:
+
+// 1111 1001 1010 0110 Rm.. 0000; dcpf (Rm)
+8.0xf9+8.0xa6+4.RN2,4.0000:D1a:::dcpf
+"dcpf"
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RN2);
+ load_word (State.regs[srcreg]);
+}
+
+// 1111 1001 1010 0111 0000 0000; dcpf (sp)
+8.0xf9+8.0xa7+8.0x00:D1b:::dcpf
+"dcpf"
+*am33_2
+{
+ PC = cia;
+
+ load_word (SP);
+}
+
+// 1111 1011 1010 0110 Ri.. Rm.. 0000 0000; dcpf (Ri,Rm)
+8.0xfb+8.0xa6+4.RN2,4.RN0+8.0x00:D2a:::dcpf
+"dcpf"
+*am33_2
+{
+ int srci, srcm;
+
+ PC = cia;
+
+ srci = translate_rreg (SD_, RN2);
+ srcm = translate_rreg (SD_, RN0);
+
+ load_word (State.regs[srci] + State.regs[srcm]);
+}
+
+// 1111 1011 1010 0111 Rm.. 0000 IMM8; dcpf (d8,Rm)
+8.0xfb+8.0xa7+4.RN2,4.0000+8.IMM8:D2b:::dcpf
+"dcpf"
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RN2);
+
+ load_word (State.regs[srcreg] + EXTEND8 (IMM8));
+}
+
+// 1111 1101 1010 0111 Rm.. 0000 IMM24; dcpf (d24,Rm)
+8.0xfd+8.0xa7+4.RN2,4.0000+8.IMM24A+8.IMM24B+8.IMM24C:D4a:::dcpf
+"dcpf"
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RN2);
+
+ load_word (State.regs[srcreg] + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+}
+
+// 1111 1110 0100 0110 Rm.. 0000 IMM32; dcpf (d32,Rm)
+8.0xfe+8.0x46+4.RN2,4.0000+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::dcpf
+"dcpf"
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RN2);
+
+ load_word (State.regs[srcreg]
+ + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// bit operations with imm8,(abs16) addressing mode:
+
+// 1111 1110 1000 0010 ABS16 IMM8; btst imm8,(abs16)
+8.0xfe+8.0x82+8.IMM16A+8.IMM16B+8.IMM8:D3:::btst
+"btst"
+*am33_2
+{
+ PC = cia;
+ genericBtst (IMM8, FETCH16 (IMM16A, IMM16B));
+}
+
+// 1111 1110 1000 0000 ABS16 IMM8; bset imm8,(abs16)
+8.0xfe+8.0x80+8.IMM16A+8.IMM16B+8.IMM8:D3:::bset
+"bset"
+*am33_2
+{
+ unsigned32 temp;
+ int z;
+
+ PC = cia;
+ temp = load_byte (FETCH16 (IMM16A, IMM16B));
+ z = (temp & IMM8) == 0;
+ temp |= IMM8;
+ store_byte (FETCH16 (IMM16A, IMM16B), temp);
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= (z ? PSW_Z : 0);
+}
+
+// 1111 1110 1000 0001 ABS16 IMM8; bclr imm8,(abs16)
+8.0xfe+8.0x81+8.IMM16A+8.IMM16B+8.IMM8:D3:::bclr
+"bclr"
+*am33_2
+{
+ unsigned32 temp;
+ int z;
+
+ PC = cia;
+ temp = load_byte (FETCH16 (IMM16A, IMM16B));
+ z = (temp & IMM8) == 0;
+ temp = temp & ~(IMM8);
+ store_byte (FETCH16 (IMM16A, IMM16B), temp);
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= (z ? PSW_Z : 0);
+}
+
+// single precision fmov:
+
+// 1111 1001 0010 000X Rm.. Sn..; fmov (Rm),FSn
+8.0xf9+4.2,3.0,1.X+4.Rm,4.Sn:D1a:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X,Sn) = load_word (State.regs[reg]);
+ }
+}
+
+// 1111 1001 0010 001X Rm.. Sn..; fmov (Rm+),FSn
+8.0xf9+4.2,3.1,1.X+4.Rm,4.Sn:D1b:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X,Sn) = load_word (State.regs[reg]);
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1001 0010 010X ---- Sn..; fmov (SP),FSn
+8.0xf9+4.2,3.2,1.X+4.0,4.Sn:D1c:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ XS2FS (X,Sn) = load_word (State.regs[reg]);
+ }
+}
+
+// 1111 1001 0010 011X Rm.. Sn..; fmov Rm,FSn
+8.0xf9+4.2,3.3,1.X+4.Rm,4.Sn:D1d:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X,Sn) = State.regs[reg];
+ }
+}
+
+// 1111 1001 0011 00Y0 Sm.. Rn..; fmov FSm,(Rn)
+8.0xf9+4.3,2.0,1.Y,1.0+4.Sm,4.Rn:D1e:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg], XS2FS (Y,Sm));
+ }
+}
+
+// 1111 1001 0011 00Y1 Sm.. Rn..; fmov FSm,(Rn+)
+8.0xf9+4.3,2.0,1.Y,1.1+4.Sm,4.Rn:D1f:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg], XS2FS (Y,Sm));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1001 0011 01Y0 Sm.. ----; fmov FSm,(SP)
+8.0xf9+4.3,2.1,1.Y,1.0+4.Sm,4.0:D1g:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_word (State.regs[reg], XS2FS (Y,Sm));
+ }
+}
+
+// 1111 1001 0011 01Y1 Sm.. Rn..; fmov FSm,Rn
+8.0xf9+4.3,2.1,1.Y,1.1+4.Sm,4.Rn:D1h:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ State.regs[reg] = XS2FS (Y,Sm);
+ }
+}
+
+// 1111 1001 0100 00YX Sm.. Sn..; fmov FSm,FSn
+8.0xf9+4.4,2.0,1.Y,1.X+4.Sm,4.Sn:D1i:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ XS2FS (X,Sn) = XS2FS (Y,Sm);
+}
+
+// 1111 1011 0010 000X Rm.. Sn.. d8; fmov (d8,Rm),FSn
+8.0xfb+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM8:D2a:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg] + EXTEND8 (IMM8));
+ }
+}
+
+// 1111 1011 0010 001X Rm.. Sn.. d8; fmov (Rm+,imm8),FSn
+8.0xfb+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM8:D2b:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg] + EXTEND8 (IMM8));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1011 0010 010X ---- Sn.. d8; fmov (d8,SP),FSn
+8.0xfb+4.2,3.2,1.X+4.0,4.Sn+8.IMM8:D2c:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ XS2FS (X, Sn) = load_word (State.regs[reg] + IMM8);
+ }
+}
+
+// 1111 1011 0010 0111 Ri.. Rm.. Sn.. --Z-; fmov (Ri,Rm),FSn
+8.0xfb+8.0x27+4.Ri,4.Rm+4.Sn,2.0,1.Z,1.0:D2d:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int ri = translate_rreg (SD_, Ri);
+ int rm = translate_rreg (SD_, Rm);
+ XS2FS (Z, Sn) = load_word (State.regs[ri] + State.regs[rm]);
+ }
+}
+
+// 1111 1011 0011 00Y0 Sm.. Rn.. d8; fmov FSm,(d8,Rn)
+8.0xfb+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM8:D2e:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg] + EXTEND8 (IMM8), XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1011 0011 00Y1 Sm.. Rn.. d8; fmov FSm,(Rn+,d8)
+8.0xfb+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM8:D2f:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg] + EXTEND8 (IMM8), XS2FS (Y, Sm));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1011 0011 01Y0 Sm.. ---- d8; fmov FSm,(d8,SP)
+8.0xfb+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM8:D2g:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_word (State.regs[reg] + IMM8, XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1011 0011 0111 Ri.. Rm.. Sm.. --Z-; fmov FSm,(Ri,Rm)
+8.0xfb+8.0x37+4.Ri,4.Rm+4.Sm,2.0,1.Z,1.0:D2h:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int ri = translate_rreg (SD_, Ri);
+ int rm = translate_rreg (SD_, Rm);
+ store_word (State.regs[ri] + State.regs[rm], XS2FS (Z, Sm));
+ }
+}
+
+// 1111 1101 0010 000X Rm.. Sn.. d24; fmov (d24,Rm),FSn
+8.0xfd+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4a:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+ }
+}
+
+// 1111 1101 0010 001X Rm.. Sn.. d24; fmov (Rm+,imm24),FSn
+8.0xfd+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1101 0010 010X ---- Sn.. d24; fmov (d24,SP),FSn
+8.0xfd+4.2,3.2,1.X+4.0,4.Sn+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ XS2FS (X, Sn) = load_word (State.regs[reg] + FETCH24 (IMM24A,
+ IMM24B, IMM24C));
+ }
+}
+
+// 1111 1101 0011 00Y0 Sm.. Rn.. d24; fmov FSm,(d24,Rn)
+8.0xfd+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4e:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)), XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1101 0011 00Y1 Sm.. Rn.. d24; fmov FSm,(Rn+,d24)
+8.0xfd+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4f:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)), XS2FS (Y, Sm));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1101 0011 01Y0 Sm.. ---- d24; fmov FSm,(d24,SP)
+8.0xfd+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM24A+8.IMM24B+8.IMM24C:D4g:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_word (State.regs[reg]
+ + FETCH24 (IMM24A,
+ IMM24B, IMM24C), XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1110 0010 000X Rm.. Sn.. d32; fmov (d32,Rm),FSn
+8.0xfe+4.2,3.0,1.X+4.Rm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)));
+ }
+}
+
+// 1111 1110 0010 001X Rm.. Sn.. d32; fmov (Rm+,imm32),FSn
+8.0xfe+4.2,3.1,1.X+4.Rm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1110 0010 010X ---- Sn.. d32; fmov (d32,SP),FSn
+8.0xfe+4.2,3.2,1.X+4.0,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ XS2FS (X, Sn) = load_word (State.regs[reg]
+ + FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D));
+ }
+}
+
+// 1111 1110 0010 011X ---- Sn.. d32; fmov imm32,FSn
+8.0xfe+4.2,3.3,1.X+4.0,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ XS2FS (X, Sn) = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+// 1111 1110 0011 00Y0 Sm.. Rn.. d32; fmov FSm,(d32,Rn)
+8.0xfe+4.3,2.0,1.Y,1.0+4.Sm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)), XS2FS (Y, Sm));
+ }
+}
+
+// 1111 1110 0011 00Y1 Sm.. Rn.. d32; fmov FSm,(Rn+,d32)
+8.0xfe+4.3,2.0,1.Y,1.1+4.Sm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_word (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)), XS2FS (Y, Sm));
+ State.regs[reg] += 4;
+ }
+}
+
+// 1111 1110 0011 01Y0 Sm.. ---- d32; fmov FSm,(d32,SP)
+8.0xfe+4.3,2.1,1.Y,1.0+4.Sm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_word (State.regs[reg]
+ + FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D), XS2FS (Y, Sm));
+ }
+}
+
+// double precision fmov:
+
+// 1111 1001 1010 000X Rm.. fn.-; fmov (Rm),FDn
+8.0xf9+4.0xa,3.0,1.X+4.Rm,3.fn,1.0:D1j:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X,fn) = load_dword (State.regs[reg]);
+ }
+}
+
+// 1111 1001 1010 001X Rm.. fn.-; fmov (Rm+),FDn
+8.0xf9+4.0xa,3.1,1.X+4.Rm,3.fn,1.0:D1k:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X,fn) = load_dword (State.regs[reg]);
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1001 1010 010X ---- fn.-; fmov (SP),FDn
+8.0xf9+4.0xa,3.2,1.X+4.0,3.fn,1.0:D1l:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ Xf2FD (X,fn) = load_dword (State.regs[reg]);
+ }
+}
+
+// 1111 1001 1011 00Y0 fm.- Rn..; fmov FDm,(Rn)
+8.0xf9+4.0xb,2.0,1.Y,1.0+3.fm,1.0,4.Rn:D1m:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg], Xf2FD (Y,fm));
+ }
+}
+
+// 1111 1001 1011 00Y1 fm.- Rn..; fmov FDm,(Rn+)
+8.0xf9+4.0xb,2.0,1.Y,1.1+3.fm,1.0,4.Rn:D1n:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg], Xf2FD (Y,fm));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1001 1011 01Y0 fm.- ----; fmov FDm,(SP)
+8.0xf9+4.0xb,2.1,1.Y,1.0+3.fm,1.0,4.0:D1o:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_dword (State.regs[reg], Xf2FD (Y,fm));
+ }
+}
+
+// 1111 1001 1100 00YX fm.- fn.-; fmov FDm,FDn
+8.0xf9+4.0xc,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1p:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0111 Ri.. Rm.. fn.- --Z-; fmov (Ri,Rm),FDn
+8.0xfb+8.0x47+4.Ri,4.Rm+3.fn,1.0,2.0,1.Z,1.0:D2i:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int ri = translate_rreg (SD_, Ri);
+ int rm = translate_rreg (SD_, Rm);
+ Xf2FD (Z,fn) = load_dword (State.regs[ri] + State.regs[rm]);
+ }
+}
+
+// 1111 1011 0101 0111 Ri.. Rn.. fm.- --Z-; fmov FDm,(Ri,Rn)
+8.0xfb+8.0x57+4.Ri,4.Rn+3.fm,1.0,2.0,1.Z,1.0:D2j:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int ri = translate_rreg (SD_, Ri);
+ int rn = translate_rreg (SD_, Rn);
+ store_dword (State.regs[ri] + State.regs[rn], Xf2FD (Z,fm));
+ }
+}
+
+// 1111 1011 1010 000X Rm.. fn.- d8; fmov (d8,Rm),FDn
+8.0xfb+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM8:D2k:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg] + EXTEND8 (IMM8));
+ }
+}
+
+// 1111 1011 1010 001X Rm.. fn.- d8; fmov (Rm+,imm8),FDn
+8.0xfb+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM8:D2l:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg] + EXTEND8 (IMM8));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1011 1010 010X ---- fn.- d8; fmov (d8,SP),FDn
+8.0xfb+4.0xa,3.2,1.X+4.0,4.fn+8.IMM8:D2m:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ Xf2FD (X, fn) = load_dword (State.regs[reg] + IMM8);
+ }
+}
+
+// 1111 1011 1011 00Y0 fm.- Rn.. d8; fmov FDm,(d8,Rn)
+8.0xfb+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM8:D2n:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg] + EXTEND8 (IMM8), Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1011 1011 00Y1 fm.- Rn.. d8; fmov FDm,(Rn+,d8)
+8.0xfb+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM8:D2o:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg] + EXTEND8 (IMM8), Xf2FD (Y, fm));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1011 1011 01Y0 fm.- ---- d8; fmov FDm,(d8,SP)
+8.0xfb+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM8:D2p:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_dword (State.regs[reg] + IMM8, Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1101 1010 000X Rm.. fn.- d24; fmov (d24,Rm),FDn
+8.0xfd+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+ }
+}
+
+// 1111 1101 1010 001X Rm.. fn.- d24; fmov (Rm+,imm24),FDn
+8.0xfd+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4l:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1101 1010 010X ---- fn.- d24; fmov (d24,SP),FDn
+8.0xfd+4.0xa,3.2,1.X+4.0,4.fn+8.IMM24A+8.IMM24B+8.IMM24C:D4m:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + FETCH24 (IMM24A,
+ IMM24B, IMM24C));
+ }
+}
+
+// 1111 1101 1011 00Y0 fm.- Rn.. d24; fmov FDm,(d24,Rn)
+8.0xfd+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4n:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)), Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1101 1011 00Y1 fm.- Rn.. d24; fmov FDm,(Rn+,d24)
+8.0xfd+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)), Xf2FD (Y, fm));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1101 1011 01Y0 fm.- ---- d24; fmov FDm,(d24,SP)
+8.0xfd+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_dword (State.regs[reg] + FETCH24 (IMM24A,
+ IMM24B, IMM24C), Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1110 1010 000X Rm.. fn.- d32; fmov (d32,Rm),FDn
+8.0xfe+4.0xa,3.0,1.X+4.Rm,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5k:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)));
+ }
+}
+
+// 1111 1110 1010 001X Rm.. fn.- d32; fmov (Rm+,imm32),FDn
+8.0xfe+4.0xa,3.1,1.X+4.Rm,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5l:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1110 1010 010X ---- fn.- d32; fmov (d32,SP),FDn
+8.0xfe+4.0xa,3.2,1.X+4.0,4.fn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5m:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ Xf2FD (X, fn) = load_dword (State.regs[reg]
+ + FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D));
+ }
+}
+
+// 1111 1110 1011 00Y0 fm.- Rn.. d32; fmov FDm,(d32,Rn)
+8.0xfe+4.0xb,2.0,1.Y,1.0+4.fm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5n:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)), Xf2FD (Y, fm));
+ }
+}
+
+// 1111 1110 1011 00Y1 fm.- Rn.. d32; fmov FDm,(Rn+,d32)
+8.0xfe+4.0xb,2.0,1.Y,1.1+4.fm,4.Rn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5o:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ store_dword (State.regs[reg]
+ + EXTEND32 (FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D)), Xf2FD (Y, fm));
+ State.regs[reg] += 8;
+ }
+}
+
+// 1111 1110 1011 01Y0 fm.- ---- d32; fmov FDm,(d32,SP)
+8.0xfe+4.0xb,2.1,1.Y,1.0+4.fm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5p:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = REG_SP;
+ store_dword (State.regs[reg]
+ + FETCH32 (IMM32A, IMM32B,
+ IMM32C, IMM32D), Xf2FD (Y, fm));
+ }
+}
+
+// FPCR fmov:
+
+// 1111 1001 1011 0101 Rm.. ----; fmov Rm,FPCR
+8.0xf9+8.0xb5+4.Rm,4.0:D1q:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rm);
+ unsigned32 val = State.regs[reg];
+ FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
+ | ((FPCR & ~val) & EF_MASK);
+ }
+}
+
+// 1111 1001 1011 0111 ---- Rn..; fmov FPCR,Rn
+8.0xf9+8.0xb7+4.0,4.Rn:D1r:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ int reg = translate_rreg (SD_, Rn);
+ State.regs[reg] = FPCR & FPCR_MASK;
+ }
+}
+
+// 1111 1101 1011 0101 imm32; fmov imm32,FPCR
+8.0xfd+8.0xb5+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fmov
+"fmov"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ unsigned32 val = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+ FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
+ | ((FPCR & ~val) & EF_MASK);
+ }
+}
+
+// fabs:
+
+// 1111 1001 0100 010X ---- Sn..; fabs FSn
+8.0xf9+4.4,3.2,1.X+4.0,4.Sn:D1a:::fabs
+"fabs"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ sim_fpu in, out;
+
+ FS2FPU (XS2FS (X,Sn), in);
+ sim_fpu_abs (&out, &in);
+ FPU2FS (out, XS2FS (X,Sn));
+ }
+}
+
+// 1111 1001 1100 010X ---- Sn..; fabs FDn
+8.0xf9+4.0xc,3.2,1.X+4.0,3.fn,1.0:D1b:::fabs
+"fabs"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0100 Sm.. ---- Sn.. X-Z-; fabs FSm,FSn
+8.0xfb+8.0x44+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fabs
+"fabs"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ sim_fpu in, out;
+
+ FS2FPU (XS2FS (X,Sm), in);
+ sim_fpu_abs (&out, &in);
+ FPU2FS (out, XS2FS (Z,Sn));
+ }
+}
+
+// 1111 1011 1100 0100 fm.- ---- fn.- X-Z-; fabs FDm,FDn
+8.0xfb+8.0xc4+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fabs
+"fabs"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0100 011X ---- Sn..; fneg FSn
+8.0xf9+4.4,3.3,1.X+4.0,4.Sn:D1a:::fneg
+"fneg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ sim_fpu in, out;
+
+ FS2FPU (XS2FS (X,Sn), in);
+ sim_fpu_neg (&out, &in);
+ FPU2FS (out, XS2FS (X,Sn));
+ }
+}
+
+// 1111 1001 1100 011X ---- Sn..; fneg FDn
+8.0xf9+4.0xc,3.3,1.X+4.0,3.fn,1.0:D1b:::fneg
+"fneg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0110 Sm.. ---- Sn.. X-Z-; fneg FSm,FSn
+8.0xfb+8.0x46+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fneg
+"fneg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ sim_fpu in, out;
+
+ FS2FPU (XS2FS (X,Sm), in);
+ sim_fpu_neg (&out, &in);
+ FPU2FS (out, XS2FS (Z,Sn));
+ }
+}
+
+// 1111 1011 1100 0110 fm.- ---- fn.- X-Z-; fneg FDm,FDn
+8.0xfb+8.0xc6+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fneg
+"fneg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0101 000X ---- Sn..; frsqrt FSn
+8.0xf9+4.5,3.0,1.X+4.0,4.Sn:D1a:::frsqrt
+"frsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_rsqrt (SD, CPU, cia, &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1101 000X ---- fn.-; frsqrt FDn
+8.0xf9+4.0xd,3.0,1.X+4.0,3.fn,1.0:D1b:::frsqrt
+"frsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0000 Sm.. ---- Sn.. X-Z-; frsqrt FSm,FSn
+8.0xfb+8.0x50+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::frsqrt
+"frsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_rsqrt (SD, CPU, cia, &XS2FS (X,Sm), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1101 0000 fm.- ---- fn.- X-Z-; frsqrt FDm,FDn
+8.0xfb+8.0xd0+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::frsqrt
+"frsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0101 001X ---- Sn..; fsqrt FSn
+8.0xf9+4.5,3.1,1.X+4.0,4.Sn:D1a:::fsqrt
+"fsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 1101 001X ---- fn.-; fsqrt FDn
+8.0xf9+4.0xd,3.1,1.X+4.0,3.fn,1.0:D1b:::fsqrt
+"fsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0100 Sm.. ---- Sn.. X-Z-; fsqrt FSm,FSn
+8.0xfb+8.0x54+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2a:::fsqrt
+"fsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 1101 0100 fm.- ---- fn.- X-Z-; fsqrt FDm,FDn
+8.0xfb+8.0xd4+3.fm,1.0,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2b:::fsqrt
+"fsqrt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1001 0101 01YX Sm.. Sn..; fcmp FSm, FSn
+8.0xf9+4.5,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fcmp
+"fcmp"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_cmp (SD, CPU, cia, &XS2FS (X,Sn), &XS2FS (Y,Sm), FP_SINGLE);
+}
+
+// 1111 1001 1101 01YX fm.- fn.-; fcmp FDm, FDn
+8.0xf9+4.0xd,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fcmp
+"fcmp"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1110 0011 01Y1 Sm.. ---- IMM32; fcmp imm32, FSm
+8.0xfe+4.3,2.1,1.Y,1.1+4.Sm,4.0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fcmp
+"fcmp"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_cmp (SD, CPU, cia, &XS2FS (Y,Sm), &imm, FP_SINGLE);
+ }
+}
+
+// 1111 1001 0110 00YX Sm.. Sn..; fadd FSm, FSn
+8.0xf9+4.6,2.0,1.Y,1.X+4.Sm,4.Sn:D1a:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_add (SD, CPU, cia,
+ &XS2FS (Y,Sm), &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1110 00YX fm.- fn.-; fadd FDm, FDn
+8.0xf9+4.0xe,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0110 0000 Sm1. Sm2. Sn.. XYZ-; fadd FSm1, FSm2, FSn
+8.0xfb+8.0x60+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_add (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1110 0000 fm1- fm2- fn.- XYZ-; fadd FDm1, FDm2, FDn
+8.0xfb+8.0xe0+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0110 00YX Sm.. Sn.. IMM32; fadd imm32, FSm, FSn
+8.0xfe+4.6,2.0,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fadd
+"fadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_add (SD, CPU, cia,
+ &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
+ }
+}
+
+// 1111 1001 0110 01YX Sm.. Sn..; fsub FSm, FSn
+8.0xf9+4.6,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_sub (SD, CPU, cia,
+ &XS2FS (X,Sn), &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1110 01YX fm.- fn.-; fsub FDm, FDn
+8.0xf9+4.0xe,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0110 0100 Sm1. Sm2. Sn.. XYZ-; fsub FSm1, FSm2, FSn
+8.0xfb+8.0x64+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_sub (SD, CPU, cia,
+ &XS2FS (Y,Sm2), &XS2FS (X,Sm1), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1110 0100 fm1- fm2- fn.- XYZ-; fsub FDm1, FDm2, FDn
+8.0xfb+8.0xe4+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0110 01YX Sm.. Sn.. IMM32; fsub imm32, FSm, FSn
+8.0xfe+4.6,2.1,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fsub
+"fsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_sub (SD, CPU, cia,
+ &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
+ }
+}
+
+// 1111 1001 0111 00YX Sm.. Sn..; fmul FSm, FSn
+8.0xf9+4.7,2.0,1.Y,1.X+4.Sm,4.Sn:D1a:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_mul (SD, CPU, cia,
+ &XS2FS (Y,Sm), &XS2FS (X,Sn), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1111 00YX fm.- fn.-; fmul FDm, FDn
+8.0xf9+4.0xf,2.0,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0111 0000 Sm1. Sm2. Sn.. XYZ-; fmul FSm1, FSm2, FSn
+8.0xfb+8.0x70+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_mul (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1111 0000 fm1- fm2- fn.- XYZ-; fmul FDm1, FDm2, FDn
+8.0xfb+8.0xf0+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0111 00YX Sm.. Sn.. IMM32; fmul imm32, FSm, FSn
+8.0xfe+4.7,2.0,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fmul
+"fmul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_mul (SD, CPU, cia,
+ &imm, &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
+ }
+}
+
+// 1111 1001 0111 01YX Sm.. Sn..; fdiv FSm, FSn
+8.0xf9+4.7,2.1,1.Y,1.X+4.Sm,4.Sn:D1a:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_div (SD, CPU, cia,
+ &XS2FS (X,Sn), &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
+}
+
+// 1111 1001 1111 01YX fm.- fn.-; fdiv FDm, FDn
+8.0xf9+4.0xf,2.1,1.Y,1.X+3.fm,1.0,3.fn,1.0:D1b:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0111 0100 Sm1. Sm2. Sn.. XYZ-; fdiv FSm1, FSm2, FSn
+8.0xfb+8.0x74+4.Sm1,4.Sm2+4.Sn,1.X,1.Y,1.Z,1.0:D2a:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_div (SD, CPU, cia,
+ &XS2FS (Y,Sm2), &XS2FS (X,Sm1), &XS2FS (Z,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1111 0100 fm1- fm2- fn.- XYZ-; fdiv FDm1, FDm2, FDn
+8.0xfb+8.0xf4+3.fm1,1.0,3.fm2,1.0+3.fn,1.0,1.X,1.Y,1.Z,1.0:D2b:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+
+// 1111 1110 0111 01YX Sm.. Sn.. IMM32; fdiv imm32, FSm, FSn
+8.0xfe+4.7,2.1,1.Y,1.X+4.Sm,4.Sn+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::fdiv
+"fdiv"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ {
+ uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ fpu_div (SD, CPU, cia,
+ &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
+ }
+}
+
+// 1111 1011 1000 00Sn Sm1. Sm2. Sm3. XYZA; fmadd FSm1, FSm2, FSm3, FSn
+8.0xfb+4.8,2.0,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fmadd
+"fmadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_fmadd (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+ &AS2FS (A,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1000 01Sn Sm1. Sm2. Sm3. XYZA; fmsub FSm1, FSm2, FSm3, FSn
+8.0xfb+4.8,2.1,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fmsub
+"fmsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_fmsub (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+ &AS2FS (A,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1001 00Sn Sm1. Sm2. Sm3. XYZA; fnmadd FSm1, FSm2, FSm3, FSn
+8.0xfb+4.9,2.0,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fnmadd
+"fnmadd"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_fnmadd (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+ &AS2FS (A,Sn), FP_SINGLE);
+}
+
+// 1111 1011 1001 01Sn Sm1. Sm2. Sm3. XYZA; fnmsub FSm1, FSm2, FSm3, FSn
+8.0xfb+4.9,2.1,2.Sn+4.Sm1,4.Sm2+4.Sm3,1.X,1.Y,1.Z,1.A:D2:::fnmsub
+"fnmsub"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_fnmsub (SD, CPU, cia,
+ &XS2FS (X,Sm1), &XS2FS (Y,Sm2), &XS2FS (Z,Sm3),
+ &AS2FS (A,Sn), FP_SINGLE);
+}
+
+// conversion:
+
+// 1111 1011 0100 0000 Sm.. ---- Sn.. X-Z-; ftoi FSm,FSn
+8.0xfb+8.0x40+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::ftoi
+"ftoi"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0100 0010 Sm.. ---- Sn.. X-Z-; itof FSm,FSn
+8.0xfb+8.0x42+4.Sm,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::itof
+"itof"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0010 Sm.. ---- fn.- X-Z-; ftod FSm,FDn
+8.0xfb+8.0x52+4.Sm,4.0+3.fn,1.0,1.X,1.0,1.Z,1.0:D2:::ftod
+"ftod"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// 1111 1011 0101 0110 fm.- ---- Sn.. X-Z-; dtof FDm,FSn
+8.0xfb+8.0x56+3.fm,1.0,4.0+4.Sn,1.X,1.0,1.Z,1.0:D2:::dtof
+"dtof"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else
+ fpu_unimp_exception (SD, CPU, cia);
+}
+
+// branching:
+
+// 1111 1000 1101 0000 d8; fbeq (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd0+8.D8:D1:::fbeq
+"fbeq"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_E))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0001 d8; fbne (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd1+8.D8:D1:::fbne
+"fbne"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L | FCC_G)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0010 d8; fbgt (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd2+8.D8:D1:::fbgt
+"fbgt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_G))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0011 d8; fbge (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd3+8.D8:D1:::fbge
+"fbge"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_G | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0100 d8; fblt (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd4+8.D8:D1:::fblt
+"fblt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_L))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0101 d8; fble (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd5+8.D8:D1:::fble
+"fble"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0110 d8; fbuo (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd6+8.D8:D1:::fbuo
+"fbuo"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_U))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 0111 d8; fblg (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd7+8.D8:D1:::fblg
+"fblg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_G)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+// 1111 1000 1101 1000 d8; fbleg (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd8+8.D8:D1:::fbleg
+"fbleg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_E | FCC_G)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1001 d8; fbug (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xd9+8.D8:D1:::fbug
+"fbug"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_G)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1010 d8; fbuge (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xda+8.D8:D1:::fbuge
+"fbuge"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_G | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1011 d8; fbul (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xdb+8.D8:D1:::fbul
+"fbul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1100 d8; fbule (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xdc+8.D8:D1:::fbule
+"fbule"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 1000 1101 1101 d8; fbue (d8,PC) (d8 is sign-extended)
+8.0xf8+8.0xdd+8.D8:D1:::fbue
+"fbue"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_E)))
+ {
+ State.regs[REG_PC] += EXTEND8 (D8);
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0000; fleq
+8.0xf0+8.0xd0:D0:::fleq
+"fleq"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_E))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0001; flne
+8.0xf0+8.0xd1:D0:::flne
+"flne"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L | FCC_G)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0010; flgt
+8.0xf0+8.0xd2:D0:::flgt
+"flgt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_G))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0011; flge
+8.0xf0+8.0xd3:D0:::flge
+"flge"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_G | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0100; fllt
+8.0xf0+8.0xd4:D0:::fllt
+"fllt"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_L))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0101; flle
+8.0xf0+8.0xd5:D0:::flle
+"flle"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0110; fluo
+8.0xf0+8.0xd6:D0:::fluo
+"fluo"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & FCC_U))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 0111; fllg
+8.0xf0+8.0xd7:D0:::fllg
+"fllg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_G)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+// 1111 0000 1101 1000; flleg
+8.0xf0+8.0xd8:D0:::flleg
+"flleg"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_L | FCC_E | FCC_G)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1001; flug
+8.0xf0+8.0xd9:D0:::flug
+"flug"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_G)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1010; fluge
+8.0xf0+8.0xda:D0:::fluge
+"fluge"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_G | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1011; flul
+8.0xf0+8.0xdb:D0:::flul
+"flul"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1100; flule
+8.0xf0+8.0xdc:D0:::flule
+"flule"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_L | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0000 1101 1101; flue
+8.0xf0+8.0xdd:D0:::flue
+"flue"
+*am33_2
+{
+ PC = cia;
+
+ if (FPU_DISABLED)
+ fpu_disabled_exception (SD, CPU, cia);
+ else if ((FPCR & (FCC_U | FCC_E)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
Index: mn10300.dc
===================================================================
--- mn10300.dc (nonexistent)
+++ mn10300.dc (revision 842)
@@ -0,0 +1,4 @@
+switch : 7 : 0 : : : : 0 : :
+switch : 7 : 0 : : : : 1 : :
+switch : 7 : 0 : : : : 2 : :
+switch : 7 : 0 : : : : 3 : :
Index: am33.igen
===================================================================
--- am33.igen (nonexistent)
+++ am33.igen (revision 842)
@@ -0,0 +1,9132 @@
+// Helper:
+//
+// Given an extended register number, translate it into an index into the
+// register array. This is necessary as the upper 8 extended registers are
+// actually synonyms for the d0-d3/a0-a3 registers.
+//
+//
+
+:function:::int:translate_rreg:int rreg
+{
+
+ /* The higher register numbers actually correspond to the
+ basic machine's address and data registers. */
+ if (rreg > 7 && rreg < 12)
+ return REG_A0 + rreg - 8;
+ else if (rreg > 11 && rreg < 16)
+ return REG_D0 + rreg - 12;
+ else
+ return REG_E0 + rreg;
+}
+
+:function:::int:translate_xreg:int xreg
+{
+ switch (xreg)
+ {
+ case 0:
+ return REG_SP;
+ case 1:
+ return REG_MDRQ;
+ case 2:
+ return REG_MCRH;
+ case 3:
+ return REG_MCRL;
+ case 4:
+ return REG_MCVF;
+ default:
+ sim_engine_abort (SD, CPU, cia, "%s:%d: bad switch\n", __FILE__, __LINE__);
+ }
+}
+
+// 1111 0000 0010 00An; mov USP,An
+8.0xf0+4.0x2,00,2.AN0:D0m:::mov
+"mov"
+*am33
+*am33_2
+{
+ PC = cia;
+ State.regs[REG_A0 + AN0] = State.regs[REG_USP];
+}
+
+
+// 1111 0000 0010 01An; mov SSP,An
+8.0xf0+4.0x2,01,2.AN0:D0n:::mov
+"mov"
+*am33
+*am33_2
+{
+ PC = cia;
+ State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
+}
+
+
+// 1111 0000 0010 10An; mov MSP,An
+8.0xf0+4.0x2,10,2.AN0:D0o:::mov
+"mov"
+*am33
+*am33_2
+{
+ PC = cia;
+ State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
+}
+
+
+// 1111 0000 0010 11An; mov PC,An
+8.0xf0+4.0x2,11,2.AN0:D0p:::mov
+"mov"
+*am33
+*am33_2
+{
+ PC = cia;
+ State.regs[REG_A0 + AN0] = PC;
+}
+
+
+// 1111 0000 0011 Am00; mov Am,USP
+8.0xf0+4.0x3,2.AM1,00:D0q:::mov
+"mov"
+*am33
+*am33_2
+{
+ PC = cia;
+ State.regs[REG_USP] = State.regs[REG_A0 + AM1];
+}
+
+// 1111 0000 0011 Am01; mov Am,SSP
+8.0xf0+4.0x3,2.AM1,01:D0r:::mov
+"mov"
+*am33
+*am33_2
+{
+ PC = cia;
+ State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
+}
+
+// 1111 0000 0011 Am10; mov Am,MSP
+8.0xf0+4.0x3,2.AM1,10:D0s:::mov
+"mov"
+*am33
+*am33_2
+{
+ PC = cia;
+ State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
+}
+
+
+// 1111 0000 1110 imm4; syscall
+8.0xf0+4.0xe,IMM4:D0t:::syscall
+"syscall"
+*am33
+*am33_2
+{
+ unsigned32 sp, next_pc;
+
+ PC = cia;
+ sp = State.regs[REG_SP];
+ next_pc = State.regs[REG_PC] + 2;
+ store_word (sp - 4, next_pc);
+ store_word (sp - 8, PSW);
+ State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
+ nia = PC;
+}
+
+
+// 1111 0010 1110 11Dn; mov EPSW,Dn
+8.0xf2+4.0xe,11,2.DN0:D0u:::mov
+"mov"
+*am33
+*am33_2
+{
+ PC = cia;
+ State.regs[REG_D0 + DN0] = PSW;
+}
+
+
+// 1111 0010 1111 Dm01; mov Dm,EPSW
+8.0xf2+4.0xf,2.DM1,01:D0v:::mov
+"mov"
+*am33
+*am33_2
+{
+ PC = cia;
+ PSW = State.regs[REG_D0 + DM1];
+}
+
+// 1111 0101 00Am Rn; mov Am,Rn
+8.0xf5+00,2.AM1,4.RN0:D0w:::mov
+"mov"
+*am33
+*am33_2
+{
+ int destreg = translate_rreg (SD_, RN0);
+
+ PC = cia;
+ State.regs[destreg] = State.regs[REG_A0 + AM1];
+}
+
+// 1111 0101 01Dm Rn; mov Dm,Rn
+8.0xf5+01,2.DM1,4.RN0:D0x:::mov
+"mov"
+*am33
+*am33_2
+{
+ int destreg = translate_rreg (SD_, RN0);
+
+ PC = cia;
+ State.regs[destreg] = State.regs[REG_D0 + DM1];
+}
+
+// 1111 0101 10Rm An; mov Rm,An
+8.0xf5+10,4.RM1,2.AN0:D0y:::mov
+"mov"
+*am33
+*am33_2
+{
+ int destreg = translate_rreg (SD_, RM1);
+
+ PC = cia;
+ State.regs[REG_A0 + AN0] = State.regs[destreg];
+}
+
+// 1111 0101 11Rm Dn; mov Rm,Dn
+8.0xf5+11,4.RM1,2.DN0:D0z:::mov
+"mov"
+*am33
+*am33_2
+{
+ int destreg = translate_rreg (SD_, RM1);
+
+ PC = cia;
+ State.regs[REG_D0 + DN0] = State.regs[destreg];
+}
+
+
+// 1111 1000 1100 1110 regs....; movm (USP),regs
+8.0xf8+8.0xce+8.REGS:D1a:::movm
+"movm"
+*am33
+*am33_2
+{
+ unsigned32 usp = State.regs[REG_USP];
+ unsigned32 mask;
+
+ PC = cia;
+ mask = REGS;
+
+ if (mask & 0x8)
+ {
+ usp += 4;
+ State.regs[REG_LAR] = load_word (usp);
+ usp += 4;
+ State.regs[REG_LIR] = load_word (usp);
+ usp += 4;
+ State.regs[REG_MDR] = load_word (usp);
+ usp += 4;
+ State.regs[REG_A0 + 1] = load_word (usp);
+ usp += 4;
+ State.regs[REG_A0] = load_word (usp);
+ usp += 4;
+ State.regs[REG_D0 + 1] = load_word (usp);
+ usp += 4;
+ State.regs[REG_D0] = load_word (usp);
+ usp += 4;
+ }
+
+ if (mask & 0x10)
+ {
+ State.regs[REG_A0 + 3] = load_word (usp);
+ usp += 4;
+ }
+
+ if (mask & 0x20)
+ {
+ State.regs[REG_A0 + 2] = load_word (usp);
+ usp += 4;
+ }
+
+ if (mask & 0x40)
+ {
+ State.regs[REG_D0 + 3] = load_word (usp);
+ usp += 4;
+ }
+
+ if (mask & 0x80)
+ {
+ State.regs[REG_D0 + 2] = load_word (usp);
+ usp += 4;
+ }
+
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+ )
+ {
+ if (mask & 0x1)
+ {
+ /* Need to restore MDQR, MCRH, MCRL, and MCVF */
+ usp += 16;
+ State.regs[REG_E0 + 1] = load_word (usp);
+ usp += 4;
+ State.regs[REG_E0 + 0] = load_word (usp);
+ usp += 4;
+ }
+
+ if (mask & 0x2)
+ {
+ State.regs[REG_E0 + 7] = load_word (usp);
+ usp += 4;
+ State.regs[REG_E0 + 6] = load_word (usp);
+ usp += 4;
+ State.regs[REG_E0 + 5] = load_word (usp);
+ usp += 4;
+ State.regs[REG_E0 + 4] = load_word (usp);
+ usp += 4;
+ }
+
+ if (mask & 0x4)
+ {
+ State.regs[REG_E0 + 3] = load_word (usp);
+ usp += 4;
+ State.regs[REG_E0 + 2] = load_word (usp);
+ usp += 4;
+ }
+ }
+
+ /* And make sure to update the stack pointer. */
+ State.regs[REG_USP] = usp;
+}
+
+// 1111 1000 1100 1111 regs....; movm (USP),regs
+8.0xf8+8.0xcf+8.REGS:D1b:::movm
+"movm"
+*am33
+*am33_2
+{
+ unsigned32 usp = State.regs[REG_USP];
+ unsigned32 mask;
+
+ PC = cia;
+ mask = REGS;
+
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+ )
+ {
+ if (mask & 0x4)
+ {
+ usp -= 4;
+ store_word (usp, State.regs[REG_E0 + 2]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_E0 + 3]);
+ }
+
+ if (mask & 0x2)
+ {
+ usp -= 4;
+ store_word (usp, State.regs[REG_E0 + 4]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_E0 + 5]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_E0 + 6]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_E0 + 7]);
+ }
+
+ if (mask & 0x1)
+ {
+ usp -= 4;
+ store_word (usp, State.regs[REG_E0 + 0]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_E0 + 1]);
+ usp -= 16;
+ /* Need to save MDQR, MCRH, MCRL, and MCVF */
+ }
+ }
+
+ if (mask & 0x80)
+ {
+ usp -= 4;
+ store_word (usp, State.regs[REG_D0 + 2]);
+ }
+
+ if (mask & 0x40)
+ {
+ usp -= 4;
+ store_word (usp, State.regs[REG_D0 + 3]);
+ }
+
+ if (mask & 0x20)
+ {
+ usp -= 4;
+ store_word (usp, State.regs[REG_A0 + 2]);
+ }
+
+ if (mask & 0x10)
+ {
+ usp -= 4;
+ store_word (usp, State.regs[REG_A0 + 3]);
+ }
+
+ if (mask & 0x8)
+ {
+ usp -= 4;
+ store_word (usp, State.regs[REG_D0]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_D0 + 1]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_A0]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_A0 + 1]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_MDR]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_LIR]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_LAR]);
+ usp -= 4;
+ }
+
+ /* And make sure to update the stack pointer. */
+ State.regs[REG_USP] = usp;
+}
+
+// 1111 1100 1111 1100 imm32...; and imm32,EPSW
+8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
+"and"
+*am33
+*am33_2
+{
+ PC = cia;
+ PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+// 1111 1100 1111 1101 imm32...; or imm32,EPSW
+8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
+"or"
+*am33
+*am33_2
+{
+ PC = cia;
+ PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+// 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
+8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = State.regs[srcreg];
+}
+
+// 1111 1001 0001 1000 Rn Rn; ext Rn
+8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
+"mov"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ if (State.regs[srcreg] & 0x80000000)
+ State.regs[REG_MDR] = -1;
+ else
+ State.regs[REG_MDR] = 0;
+}
+
+// 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
+8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
+"extb"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
+}
+
+// 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
+8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
+"extbu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = State.regs[srcreg] & 0xff;
+}
+
+// 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
+8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
+"exth"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
+}
+
+// 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
+8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
+"exthu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = State.regs[srcreg] & 0xffff;
+}
+
+// 1111 1001 0110 1000 Rn Rn; clr Rn
+8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
+"clr"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = 0;
+ PSW |= PSW_Z;
+ PSW &= ~(PSW_V | PSW_C | PSW_N);
+}
+
+// 1111 1001 0111 1000 Rm Rn; add Rm,Rn
+8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
+"add"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ genericAdd (State.regs[srcreg], dstreg);
+}
+
+// 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
+8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
+"addc"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+ int z, c, n, v;
+ unsigned32 reg1, reg2, sum;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ reg1 = State.regs[srcreg];
+ reg2 = State.regs[dstreg];
+ sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = sum;
+
+ z = ((PSW & PSW_Z) != 0) && (sum == 0);
+ n = (sum & 0x80000000);
+ c = (sum < reg1) || (sum < reg2);
+ v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
+ && (reg2 & 0x80000000) != (sum & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
+8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
+"sub"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ genericSub (State.regs[srcreg], dstreg);
+}
+
+// 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
+8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
+"subc"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+ int z, c, n, v;
+ unsigned32 reg1, reg2, difference;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ reg1 = State.regs[srcreg];
+ reg2 = State.regs[dstreg];
+ difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = difference;
+
+ z = ((PSW & PSW_Z) != 0) && (difference == 0);
+ n = (difference & 0x80000000);
+ c = (reg1 > reg2);
+ v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
+ && (reg2 & 0x80000000) != (difference & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1001 1011 1000 Rn Rn; inc Rn
+8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
+"inc"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ genericAdd (1, dstreg);
+}
+
+// 1111 1001 1101 1000 Rn Rn; inc Rn
+8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
+"inc4"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ genericAdd (4, dstreg);
+}
+
+// 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
+8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
+"cmp"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RN0);
+ srcreg2 = translate_rreg (SD_, RM2);
+ genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
+}
+
+// 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
+8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
+"mov"
+*am33
+*am33_2
+{
+ int dstreg, srcreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ srcreg = translate_xreg (SD_, XRM2);
+
+ State.regs[dstreg] = State.regs[srcreg];
+}
+
+// 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
+8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_xreg (SD_, XRN0);
+
+ State.regs[dstreg] = State.regs[srcreg];
+}
+
+// 1111 1001 0000 1001 Rm Rn; and Rm,Rn
+8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
+"and"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+ int z, n;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] &= State.regs[srcreg];
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 0001 1001 Rm Rn; or Rm,Rn
+8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
+"or"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+ int z, n;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] |= State.regs[srcreg];
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
+8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
+"xor"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+ int z, n;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] ^= State.regs[srcreg];
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 0011 1001 Rn Rn; not Rn
+8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
+"not"
+*am33
+*am33_2
+{
+ int dstreg;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] = ~State.regs[dstreg];
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
+8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
+"asr"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+ signed32 temp;
+ int c, z, n;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = State.regs[dstreg];
+ c = temp & 1;
+ temp >>= State.regs[srcreg];
+ State.regs[dstreg] = temp;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+// 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
+8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
+"lsr"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+ int z, n, c;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ c = State.regs[dstreg] & 1;
+ State.regs[dstreg] >>= State.regs[srcreg];
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+// 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
+8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
+"asl"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+ int z, n;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] <<= State.regs[srcreg];
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 0111 1001 Rn Rn; asl2 Rn
+8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
+"asl2"
+*am33
+*am33_2
+{
+ int dstreg;
+ int n, z;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] <<= 2;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 1000 1001 Rn Rn; ror Rn
+8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
+"ror"
+*am33
+*am33_2
+{
+ int dstreg;
+ int c, n, z;
+ unsigned32 value;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ value = State.regs[dstreg];
+ c = (value & 0x1);
+
+ value >>= 1;
+ value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
+ State.regs[dstreg] = value;
+ z = (value == 0);
+ n = (value & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+// 1111 1001 1001 1001 Rn Rn; rol Rn
+8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
+"rol"
+*am33
+*am33_2
+{
+ int dstreg;
+ int c, n, z;
+ unsigned32 value;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ value = State.regs[dstreg];
+ c = (value & 0x80000000) ? 1 : 0;
+
+ value <<= 1;
+ value |= ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = value;
+ z = (value == 0);
+ n = (value & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+// 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
+8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
+"mul"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+ unsigned64 temp;
+ int n, z;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((signed64)(signed32)State.regs[dstreg]
+ * (signed64)(signed32)State.regs[srcreg]);
+ State.regs[dstreg] = temp & 0xffffffff;
+ State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
+8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
+"mulu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+ unsigned64 temp;
+ int n, z;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned64)State.regs[dstreg]
+ * (unsigned64)State.regs[srcreg]);
+ State.regs[dstreg] = temp & 0xffffffff;
+ State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 1100 1001 Rm Rn; div Rm,Rn
+8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
+"div"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+ signed64 temp;
+ int n, z;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = State.regs[REG_MDR];
+ temp <<= 32;
+ temp |= State.regs[dstreg];
+ State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
+ temp /= (signed32)State.regs[srcreg];
+ State.regs[dstreg] = temp & 0xffffffff;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
+8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
+"divu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+ unsigned64 temp;
+ int n, z;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = State.regs[REG_MDR];
+ temp <<= 32;
+ temp |= State.regs[dstreg];
+ State.regs[REG_MDR] = temp % State.regs[srcreg];
+ temp /= State.regs[srcreg];
+ State.regs[dstreg] = temp & 0xffffffff;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
+8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+}
+
+// 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
+8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_word (State.regs[dstreg], State.regs[srcreg]);
+}
+
+// 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
+8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (State.regs[srcreg]);
+}
+
+// 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
+8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_byte (State.regs[dstreg], State.regs[srcreg]);
+}
+
+// 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
+8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[srcreg]);
+}
+
+// 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
+8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_half (State.regs[dstreg], State.regs[srcreg]);
+}
+
+// 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
+8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += 4;
+}
+
+// 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
+8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_word (State.regs[dstreg], State.regs[srcreg]);
+ State.regs[dstreg] += 4;
+}
+
+// 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
+8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
+"mov"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[REG_SP]);
+}
+
+// 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
+8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_word (State.regs[REG_SP], State.regs[srcreg]);
+}
+
+// 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
+8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (State.regs[REG_SP]);
+}
+
+// 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
+8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_byte (State.regs[REG_SP], State.regs[srcreg]);
+}
+
+// 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
+8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[REG_SP]);
+}
+
+// 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
+8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_half (State.regs[REG_SP], State.regs[srcreg]);
+}
+
+// 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
+8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[srcreg]);
+ State.regs[srcreg] += 2;
+}
+
+// 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
+8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_half (State.regs[dstreg], State.regs[srcreg]);
+ State.regs[dstreg] += 2;
+}
+
+
+// 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
+8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
+"mac"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2;
+ signed64 temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+
+ temp = ((signed64)(signed32)State.regs[srcreg2]
+ * (signed64)(signed32)State.regs[srcreg1]);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
+8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
+"macu"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2;
+ unsigned64 temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned64)State.regs[srcreg2]
+ * (unsigned64)State.regs[srcreg1]);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
+8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
+"macb"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2;
+ signed32 temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+
+ temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
+ * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
+ sum = State.regs[REG_MCRL] + temp;
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
+8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
+"macbu"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2;
+ signed64 temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
+ * (unsigned32)(State.regs[srcreg1] & 0xff));
+ sum = State.regs[REG_MCRL] + temp;
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
+8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
+"mach"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2;
+ signed64 temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
+ * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
+8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
+"machu"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2;
+ signed64 temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
+ * (unsigned64)(State.regs[srcreg1] & 0xffff));
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
+8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
+"dmach"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2;
+ signed32 temp, temp2, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+
+ temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
+8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
+"dmachu"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2;
+ unsigned32 temp, temp2, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
+ * (unsigned32)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
+8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
+"dmulh"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+ signed32 temp;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
+ State.regs[REG_MDRQ] = temp;
+ temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
+ State.regs[dstreg] = temp;
+}
+
+// 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
+8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
+"dmachu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+ unsigned32 temp;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
+ * (unsigned32)(State.regs[srcreg] & 0xffff));
+ State.regs[REG_MDRQ] = temp;
+ temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
+ * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
+ State.regs[dstreg] = temp;
+}
+
+// 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
+8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
+"sat16"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+ int value, z, n;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ value = State.regs[srcreg];
+
+ if (value >= 0x7fff)
+ State.regs[dstreg] = 0x7fff;
+ else if (value <= 0xffff8000)
+ State.regs[dstreg] = 0xffff8000;
+ else
+ State.regs[dstreg] = value;
+
+ n = (State.regs[dstreg] & 0x8000) != 0;
+ z = (State.regs[dstreg] == 0);
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
+8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
+"mcste"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ PSW &= ~(PSW_V | PSW_C);
+ PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
+
+ /* 32bit saturation. */
+ if (State.regs[srcreg] == 0x20)
+ {
+ signed64 tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x7fffffff)
+ State.regs[dstreg] = 0x7fffffff;
+ else if (tmp < 0xffffffff80000000LL)
+ State.regs[dstreg] = 0x80000000;
+ else
+ State.regs[dstreg] = tmp;
+ }
+ /* 16bit saturation */
+ else if (State.regs[srcreg] == 0x10)
+ {
+ signed64 tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x7fff)
+ State.regs[dstreg] = 0x7fff;
+ else if (tmp < 0xffffffffffff8000LL)
+ State.regs[dstreg] = 0x8000;
+ else
+ State.regs[dstreg] = tmp;
+ }
+ /* 8 bit saturation */
+ else if (State.regs[srcreg] == 0x8)
+ {
+ signed64 tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x7f)
+ State.regs[dstreg] = 0x7f;
+ else if (tmp < 0xffffffffffffff80LL)
+ State.regs[dstreg] = 0x80;
+ else
+ State.regs[dstreg] = tmp;
+ }
+ /* 9 bit saturation */
+ else if (State.regs[srcreg] == 0x9)
+ {
+ signed64 tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x80)
+ State.regs[dstreg] = 0x80;
+ else if (tmp < 0xffffffffffffff81LL)
+ State.regs[dstreg] = 0x81;
+ else
+ State.regs[dstreg] = tmp;
+ }
+ /* 9 bit saturation */
+ else if (State.regs[srcreg] == 0x30)
+ {
+ signed64 tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x7fffffffffffLL)
+ tmp = 0x7fffffffffffLL;
+ else if (tmp < 0xffff800000000000LL)
+ tmp = 0xffff800000000000LL;
+
+ tmp >>= 16;
+ State.regs[dstreg] = tmp;
+ }
+}
+
+// 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
+8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
+"swap"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
+ | (((State.regs[srcreg] >> 8) & 0xff) << 16)
+ | (((State.regs[srcreg] >> 16) & 0xff) << 8)
+ | ((State.regs[srcreg] >> 24) & 0xff));
+}
+
+// 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
+8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
+"swaph"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
+ | ((State.regs[srcreg] >> 8) & 0xff)
+ | (((State.regs[srcreg] >> 16) & 0xff) << 24)
+ | (((State.regs[srcreg] >> 24) & 0xff) << 16));
+}
+
+// 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
+8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
+"swhw"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
+ | ((State.regs[srcreg] >> 16) & 0xffff));
+}
+
+// 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
+8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
+"bsch"
+*am33
+*am33_2
+{
+ int temp, c, i;
+ int srcreg, dstreg;
+ int start;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = State.regs[srcreg];
+ start = (State.regs[dstreg] & 0x1f) - 1;
+ if (start == -1)
+ start = 31;
+
+ c = 0;
+ for (i = start; i >= 0; i--)
+ {
+ if (temp & (1 << i))
+ {
+ c = 1;
+ State.regs[dstreg] = i;
+ break;
+ }
+ }
+
+ if (i < 0)
+ {
+ c = 0;
+ State.regs[dstreg] = 0;
+ }
+ PSW &= ~(PSW_C);
+ PSW |= (c ? PSW_C : 0);
+}
+
+
+// 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
+8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
+"mov"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = EXTEND8 (IMM8);
+}
+
+// 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
+8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
+"movu"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = IMM8 & 0xff;
+}
+
+// 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
+8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
+"add"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ genericAdd (EXTEND8 (IMM8), dstreg);
+}
+
+// 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
+8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
+"addc"
+*am33
+*am33_2
+{
+ int dstreg, imm;
+ int z, c, n, v;
+ unsigned32 reg2, sum;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ imm = EXTEND8 (IMM8);
+ reg2 = State.regs[dstreg];
+ sum = imm + reg2 + ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = sum;
+
+ z = ((PSW & PSW_Z) != 0) && (sum == 0);
+ n = (sum & 0x80000000);
+ c = (sum < imm) || (sum < reg2);
+ v = ((reg2 & 0x80000000) == (imm & 0x80000000)
+ && (reg2 & 0x80000000) != (sum & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
+8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
+"sub"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ genericSub (EXTEND8 (IMM8), dstreg);
+}
+
+// 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
+8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
+"subc"
+*am33
+*am33_2
+{
+ int imm, dstreg;
+ int z, c, n, v;
+ unsigned32 reg2, difference;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ imm = EXTEND8 (IMM8);
+ reg2 = State.regs[dstreg];
+ difference = reg2 - imm - ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = difference;
+
+ z = ((PSW & PSW_Z) != 0) && (difference == 0);
+ n = (difference & 0x80000000);
+ c = (imm > reg2);
+ v = ((reg2 & 0x80000000) == (imm & 0x80000000)
+ && (reg2 & 0x80000000) != (difference & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
+8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
+"cmp"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
+}
+
+// 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
+8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
+"mov"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_xreg (SD_, XRN0);
+
+ State.regs[dstreg] = IMM8;
+}
+
+// 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
+8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
+"and"
+*am33
+*am33_2
+{
+ int dstreg;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] &= (IMM8 & 0xff);
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
+8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
+"or"
+*am33
+*am33_2
+{
+ int dstreg;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] |= (IMM8 & 0xff);
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
+8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
+"xor"
+*am33
+*am33_2
+{
+ int dstreg;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] ^= (IMM8 & 0xff);
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
+8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
+"asr"
+*am33
+*am33_2
+{
+ int dstreg;
+ signed32 temp;
+ int c, z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = State.regs[dstreg];
+ c = temp & 1;
+ temp >>= (IMM8 & 0xff);
+ State.regs[dstreg] = temp;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+// 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
+8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
+"lsr"
+*am33
+*am33_2
+{
+ int dstreg;
+ int z, n, c;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ c = State.regs[dstreg] & 1;
+ State.regs[dstreg] >>= (IMM8 & 0xff);
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+// 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
+8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
+"asl"
+*am33
+*am33_2
+{
+ int dstreg;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] <<= (IMM8 & 0xff);
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
+8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
+"mul"
+*am33
+*am33_2
+{
+ int dstreg;
+ unsigned64 temp;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((signed64)(signed32)State.regs[dstreg]
+ * (signed64)(signed32)EXTEND8 (IMM8));
+ State.regs[dstreg] = temp & 0xffffffff;
+ State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
+8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
+"mulu"
+*am33
+*am33_2
+{
+ int dstreg;
+ unsigned64 temp;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned64)State.regs[dstreg]
+ * (unsigned64)(IMM8 & 0xff));
+ State.regs[dstreg] = temp & 0xffffffff;
+ State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
+8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
+"btst"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ genericBtst(IMM8, State.regs[srcreg]);
+}
+
+// 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
+8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
+}
+
+// 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
+8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
+}
+
+// 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
+8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
+}
+
+// 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
+8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
+}
+
+// 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
+8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
+}
+
+// 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
+8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
+}
+
+// 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
+8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND8 (IMM8);
+}
+
+// 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
+8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_word (State.regs[dstreg], State.regs[srcreg]);
+ State.regs[dstreg] += EXTEND8 (IMM8);
+}
+
+
+// 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
+8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
+"mov"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[REG_SP] + IMM8);
+}
+
+// 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,sp)
+8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_word (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
+}
+
+// 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
+8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (State.regs[REG_SP] + IMM8);
+}
+
+// 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(d8,sp)
+8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_byte (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
+}
+
+// 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
+8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[REG_SP] + IMM8);
+}
+
+// 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
+8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_half (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
+}
+
+// 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
+8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND8 (IMM8);
+}
+
+// 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
+8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_half (State.regs[dstreg], State.regs[srcreg]);
+ State.regs[dstreg] += EXTEND8 (IMM8);
+}
+
+
+// 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
+8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
+"mac"
+*am33
+*am33_2
+{
+ int srcreg;
+ signed64 temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((signed64)(signed32)EXTEND8 (IMM8)
+ * (signed64)(signed32)State.regs[srcreg]);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
+8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
+"macu"
+*am33
+*am33_2
+{
+ int srcreg;
+ signed64 temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((unsigned64) (IMM8)
+ * (unsigned64)State.regs[srcreg]);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
+8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
+"macb"
+*am33
+*am33_2
+{
+ int srcreg;
+ signed64 temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((signed64)(signed8)EXTEND8 (IMM8)
+ * (signed64)(signed8)State.regs[srcreg] & 0xff);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
+8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
+"macbu"
+*am33
+*am33_2
+{
+ int srcreg;
+ signed64 temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((unsigned64) (IMM8)
+ * (unsigned64)State.regs[srcreg] & 0xff);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
+8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
+"mach"
+*am33
+*am33_2
+{
+ int srcreg;
+ signed64 temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((signed64)(signed16)EXTEND8 (IMM8)
+ * (signed64)(signed16)State.regs[srcreg] & 0xffff);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
+8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
+"machu"
+*am33
+*am33_2
+{
+ int srcreg;
+ signed64 temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((unsigned64) (IMM8)
+ * (unsigned64)State.regs[srcreg] & 0xffff);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
+8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
+"mcste"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ PSW &= ~(PSW_V | PSW_C);
+ PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
+
+ /* 32bit saturation. */
+ if (IMM8 == 0x20)
+ {
+ signed64 tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x7fffffff)
+ State.regs[dstreg] = 0x7fffffff;
+ else if (tmp < 0xffffffff80000000LL)
+ State.regs[dstreg] = 0x80000000;
+ else
+ State.regs[dstreg] = tmp;
+ }
+ /* 16bit saturation */
+ else if (IMM8 == 0x10)
+ {
+ signed64 tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x7fff)
+ State.regs[dstreg] = 0x7fff;
+ else if (tmp < 0xffffffffffff8000LL)
+ State.regs[dstreg] = 0x8000;
+ else
+ State.regs[dstreg] = tmp;
+ }
+ /* 8 bit saturation */
+ else if (IMM8 == 0x8)
+ {
+ signed64 tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x7f)
+ State.regs[dstreg] = 0x7f;
+ else if (tmp < 0xffffffffffffff80LL)
+ State.regs[dstreg] = 0x80;
+ else
+ State.regs[dstreg] = tmp;
+ }
+ /* 9 bit saturation */
+ else if (IMM8 == 0x9)
+ {
+ signed64 tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x80)
+ State.regs[dstreg] = 0x80;
+ else if (tmp < 0xffffffffffffff81LL)
+ State.regs[dstreg] = 0x81;
+ else
+ State.regs[dstreg] = tmp;
+ }
+ /* 9 bit saturation */
+ else if (IMM8 == 0x30)
+ {
+ signed64 tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x7fffffffffffLL)
+ tmp = 0x7fffffffffffLL;
+ else if (tmp < 0xffff800000000000LL)
+ tmp = 0xffff800000000000LL;
+
+ tmp >>= 16;
+ State.regs[dstreg] = tmp;
+ }
+}
+
+// 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
+8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
+"add"
+*am33
+*am33_2
+{
+ int z, c, n, v;
+ unsigned32 sum, source1, source2;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ source1 = State.regs[srcreg1];
+ source2 = State.regs[srcreg2];
+ sum = source1 + source2;
+ State.regs[dstreg] = sum;
+
+ z = (sum == 0);
+ n = (sum & 0x80000000);
+ c = (sum < source1) || (sum < source2);
+ v = ((source1 & 0x80000000) == (source2 & 0x80000000)
+ && (source1 & 0x80000000) != (sum & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
+8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
+"addc"
+*am33
+*am33_2
+{
+ int z, c, n, v;
+ unsigned32 sum, source1, source2;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ source1 = State.regs[srcreg1];
+ source2 = State.regs[srcreg2];
+ sum = source1 + source2 + ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = sum;
+
+ z = ((PSW & PSW_Z) != 0) && (sum == 0);
+ n = (sum & 0x80000000);
+ c = (sum < source1) || (sum < source2);
+ v = ((source1 & 0x80000000) == (source2 & 0x80000000)
+ && (source1 & 0x80000000) != (sum & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
+8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
+"sub"
+*am33
+*am33_2
+{
+ int z, c, n, v;
+ unsigned32 difference, source1, source2;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ source1 = State.regs[srcreg1];
+ source2 = State.regs[srcreg2];
+ difference = source2 - source1;
+ State.regs[dstreg] = difference;
+
+ z = (difference == 0);
+ n = (difference & 0x80000000);
+ c = (source1 > source1);
+ v = ((source1 & 0x80000000) == (source2 & 0x80000000)
+ && (source1 & 0x80000000) != (difference & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
+8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
+"subc"
+*am33
+*am33_2
+{
+ int z, c, n, v;
+ unsigned32 difference, source1, source2;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ source1 = State.regs[srcreg1];
+ source2 = State.regs[srcreg2];
+ difference = source2 - source1 - ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = difference;
+
+ z = ((PSW & PSW_Z) != 0) && (difference == 0);
+ n = (difference & 0x80000000);
+ c = (source1 > source2);
+ v = ((source1 & 0x80000000) == (source2 & 0x80000000)
+ && (source1 & 0x80000000) != (difference & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
+8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
+"and"
+*am33
+*am33_2
+{
+ int z, n;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
+
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000);
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
+}
+
+// 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
+8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
+"or"
+*am33
+*am33_2
+{
+ int z, n;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
+
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000);
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
+}
+
+// 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
+8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
+"xor"
+*am33
+*am33_2
+{
+ int z, n;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
+
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000);
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
+}
+
+// 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
+8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
+"asr"
+*am33
+*am33_2
+{
+ int z, c, n;
+ signed32 temp;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ temp = State.regs[srcreg2];
+ c = temp & 1;
+ temp >>= State.regs[srcreg1];
+ State.regs[dstreg] = temp;
+
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000);
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
+}
+
+// 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
+8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
+"lsr"
+*am33
+*am33_2
+{
+ int z, c, n;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ c = State.regs[srcreg2] & 1;
+ State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
+
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000);
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
+}
+
+// 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
+8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
+"asl"
+*am33
+*am33_2
+{
+ int z, n;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];
+
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000);
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
+}
+
+// 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
+8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
+"mul"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed64 temp;
+ int n, z;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg1 = translate_rreg (SD_, RD0);
+ dstreg2 = translate_rreg (SD_, RD2);
+
+ temp = ((signed64)(signed32)State.regs[srcreg1]
+ * (signed64)(signed32)State.regs[srcreg2]);
+ State.regs[dstreg2] = temp & 0xffffffff;
+ State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
+
+ z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
+ n = (State.regs[dstreg1] & 0x80000000);
+
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
+}
+
+// 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
+8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
+"mulu"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed64 temp;
+ int n, z;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg1 = translate_rreg (SD_, RD0);
+ dstreg2 = translate_rreg (SD_, RD2);
+
+ temp = ((unsigned64)State.regs[srcreg1]
+ * (unsigned64)State.regs[srcreg2]);
+ State.regs[dstreg2] = temp & 0xffffffff;
+ State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
+
+ z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
+ n = (State.regs[dstreg1] & 0x80000000);
+
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
+}
+
+// 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
+8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
+"mov"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (IMM8);
+}
+
+// 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
+8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_word (IMM8, State.regs[srcreg]);
+}
+
+// 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
+8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (IMM8);
+}
+
+// 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
+8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_byte (IMM8, State.regs[srcreg]);
+}
+
+// 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
+8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (IMM8);
+}
+
+// 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
+8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_half (IMM8, State.regs[srcreg]);
+}
+
+// 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
+8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM0);
+ srcreg2 = translate_rreg (SD_, RI0);
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
+}
+
+// 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
+8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg1 = translate_rreg (SD_, RI0);
+ dstreg2 = translate_rreg (SD_, RN0);
+ store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
+}
+
+// 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
+8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM0);
+ srcreg2 = translate_rreg (SD_, RI0);
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
+}
+
+// 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
+8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg1 = translate_rreg (SD_, RI0);
+ dstreg2 = translate_rreg (SD_, RN0);
+ store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
+}
+
+// 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
+8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM0);
+ srcreg2 = translate_rreg (SD_, RI0);
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
+}
+
+// 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
+8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg1 = translate_rreg (SD_, RI0);
+ dstreg2 = translate_rreg (SD_, RN0);
+ store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
+}
+
+// 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
+8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
+"mac"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed64 temp;
+ unsigned32 sum;
+ int c, v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg1 = translate_rreg (SD_, RD0);
+ dstreg2 = translate_rreg (SD_, RD2);
+
+ temp = ((signed64)(signed32)State.regs[srcreg1]
+ * (signed64)(signed32)State.regs[srcreg2]);
+
+ sum = State.regs[dstreg2] + (temp & 0xffffffff);
+ c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
+ State.regs[dstreg2] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[dstreg1] + temp + c;
+ v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[dstreg1] = sum;
+ if (v)
+ {
+ State.regs[REG_MCVF] = 1;
+ PSW &= ~(PSW_V);
+ PSW |= (( v ? PSW_V : 0));
+ }
+}
+
+// 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
+8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
+"macu"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed64 temp;
+ unsigned32 sum;
+ int c, v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg1 = translate_rreg (SD_, RD0);
+ dstreg2 = translate_rreg (SD_, RD2);
+
+ temp = ((unsigned64)State.regs[srcreg1]
+ * (unsigned64)State.regs[srcreg2]);
+
+ sum = State.regs[dstreg2] + (temp & 0xffffffff);
+ c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
+ State.regs[dstreg2] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[dstreg1] + temp + c;
+ v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[dstreg1] = sum;
+ if (v)
+ {
+ State.regs[REG_MCVF] = 1;
+ PSW &= ~(PSW_V);
+ PSW |= (( v ? PSW_V : 0));
+ }
+}
+
+// 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
+8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
+"macb"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg;
+ signed32 temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ temp = ((signed32)(State.regs[srcreg2] & 0xff)
+ * (signed32)(State.regs[srcreg1] & 0xff));
+ sum = State.regs[dstreg] + temp;
+ v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[dstreg] = sum;
+ if (v)
+ {
+ State.regs[REG_MCVF] = 1;
+ PSW &= ~(PSW_V);
+ PSW |= ((v ? PSW_V : 0));
+ }
+}
+
+// 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
+8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
+"macbu"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg;
+ signed32 temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
+ * (unsigned32)(State.regs[srcreg1] & 0xff));
+ sum = State.regs[dstreg] + temp;
+ v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[dstreg] = sum;
+ if (v)
+ {
+ State.regs[REG_MCVF] = 1;
+ PSW &= ~(PSW_V);
+ PSW |= ((v ? PSW_V : 0));
+ }
+}
+
+// 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1,Rd2
+8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
+"mach"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed64 temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg1 = translate_rreg (SD_, RD0);
+ dstreg2 = translate_rreg (SD_, RD0);
+
+ temp = ((signed32)(State.regs[srcreg2] & 0xffff)
+ * (signed32)(State.regs[srcreg1] & 0xffff));
+ State.regs[dstreg2] += (temp & 0xffffffff);
+ sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
+ v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[dstreg1] = sum;
+ if (v)
+ {
+ State.regs[REG_MCVF] = 1;
+ PSW &= ~(PSW_V);
+ PSW |= ((v ? PSW_V : 0));
+ }
+}
+
+// 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1,Rd2
+8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
+"machu"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed64 temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg1 = translate_rreg (SD_, RD0);
+ dstreg2 = translate_rreg (SD_, RD0);
+
+ temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
+ * (unsigned32)(State.regs[srcreg1] & 0xffff));
+ State.regs[dstreg2] += (temp & 0xffffffff);
+ sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
+ v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[dstreg1] = sum;
+ if (v)
+ {
+ State.regs[REG_MCVF] = 1;
+ PSW &= ~(PSW_V);
+ PSW |= ((v ? PSW_V : 0));
+ }
+}
+
+// 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
+8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
+"dmach"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg;
+ signed32 temp, temp2, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ temp = ((signed32)(State.regs[srcreg2] & 0xffff)
+ * (signed32)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[dstreg];
+ v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[dstreg] = sum;
+ if (v)
+ {
+ State.regs[REG_MCVF] = 1;
+ PSW &= ~(PSW_V);
+ PSW |= ((v ? PSW_V : 0));
+ }
+}
+
+// 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
+8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
+"dmachu"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg;
+ signed32 temp, temp2, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
+ * (unsigned32)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[dstreg];
+ v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[dstreg] = sum;
+ if (v)
+ {
+ State.regs[REG_MCVF] = 1;
+ PSW &= ~(PSW_V);
+ PSW |= ((v ? PSW_V : 0));
+ }
+}
+
+// 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
+8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
+"dmulh"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed64 temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg1 = translate_rreg (SD_, RD0);
+ dstreg2 = translate_rreg (SD_, RD2);
+
+ temp = ((signed32)(State.regs[srcreg1] & 0xffff)
+ * (signed32)(State.regs[srcreg1] & 0xffff));
+ State.regs[dstreg2] = temp;
+ temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
+ State.regs[dstreg1] = temp;
+}
+
+// 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
+8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
+"dmulhu"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed64 temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg1 = translate_rreg (SD_, RD0);
+ dstreg2 = translate_rreg (SD_, RD2);
+
+ temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
+ * (unsigned32)(State.regs[srcreg1] & 0xffff));
+ State.regs[dstreg2] = temp;
+ temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
+ State.regs[dstreg1] = temp;
+}
+
+// 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
+8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
+"sat24"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+ int value, n, z;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ value = State.regs[srcreg];
+
+ if (value >= 0x7fffff)
+ State.regs[dstreg] = 0x7fffff;
+ else if (value <= 0xff800000)
+ State.regs[dstreg] = 0xff800000;
+ else
+ State.regs[dstreg] = value;
+
+ n = (State.regs[dstreg] & 0x800000) != 0;
+ z = (State.regs[dstreg] == 0);
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
+8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
+"bsch"
+*am33
+*am33_2
+{
+ int temp, c, i;
+ int srcreg1, srcreg2, dstreg;
+ int start;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ temp = State.regs[srcreg1];
+ start = (State.regs[srcreg2] & 0x1f) - 1;
+ if (start == -1)
+ start = 31;
+
+ c = 0;
+ for (i = start; i >= 0; i--)
+ {
+ if (temp & (1 << i))
+ {
+ c = 1;
+ State.regs[dstreg] = i;
+ break;
+ }
+ }
+
+ if (i < 0)
+ {
+ c = 0;
+ State.regs[dstreg] = 0;
+ }
+ PSW &= ~(PSW_C);
+ PSW |= (c ? PSW_C : 0);
+}
+
+// 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
+8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
+"mov"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
+}
+
+// 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
+8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
+"movu"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
+}
+
+// 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
+8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
+"add"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
+}
+
+// 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
+8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
+"addc"
+*am33
+*am33_2
+{
+ int dstreg, z, n, c, v;
+ unsigned32 sum, imm, reg2;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
+ reg2 = State.regs[dstreg];
+ sum = imm + reg2 + ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = sum;
+
+ z = ((PSW & PSW_Z) != 0) && (sum == 0);
+ n = (sum & 0x80000000);
+ c = (sum < imm) || (sum < reg2);
+ v = ((reg2 & 0x80000000) == (imm & 0x80000000)
+ && (reg2 & 0x80000000) != (sum & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
+8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
+"sub"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
+}
+
+// 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
+8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
+"subc"
+*am33
+*am33_2
+{
+ int dstreg, z, n, c, v;
+ unsigned32 difference, imm, reg2;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
+ reg2 = State.regs[dstreg];
+ difference = reg2 - imm - ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = difference;
+
+ z = ((PSW & PSW_Z) != 0) && (difference == 0);
+ n = (difference & 0x80000000);
+ c = (imm > reg2);
+ v = ((reg2 & 0x80000000) == (imm & 0x80000000)
+ && (reg2 & 0x80000000) != (difference & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
+8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
+"cmp"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
+}
+
+// 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
+8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
+"mov"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_xreg (SD_, XRN0);
+
+ State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
+}
+
+// 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
+8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
+"and"
+*am33
+*am33_2
+{
+ int dstreg;
+ int z,n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
+8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
+"or"
+*am33
+*am33_2
+{
+ int dstreg;
+ int z,n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
+8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
+"xor"
+*am33
+*am33_2
+{
+ int dstreg;
+ int z,n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
+8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
+"asr"
+*am33
+*am33_2
+{
+ int dstreg;
+ signed32 temp;
+ int c, z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = State.regs[dstreg];
+ c = temp & 1;
+ temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
+ State.regs[dstreg] = temp;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+
+// 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
+8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
+"lsr"
+*am33
+*am33_2
+{
+ int dstreg;
+ int z, n, c;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ c = State.regs[dstreg] & 1;
+ State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+// 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
+8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
+"asl"
+*am33
+*am33_2
+{
+ int dstreg;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
+8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
+"mul"
+*am33
+*am33_2
+{
+ int dstreg;
+ unsigned64 temp;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((signed64)(signed32)State.regs[dstreg]
+ * (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
+ State.regs[dstreg] = temp & 0xffffffff;
+ State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
+8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
+"mulu"
+*am33
+*am33_2
+{
+ int dstreg;
+ unsigned64 temp;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned64)State.regs[dstreg]
+ * (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
+ State.regs[dstreg] = temp & 0xffffffff;
+ State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
+8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
+"btst"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
+}
+
+// 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
+8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[srcreg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+}
+
+// 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
+8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
+ State.regs[srcreg]);
+}
+
+// 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
+8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (State.regs[srcreg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+}
+
+// 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
+8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
+ State.regs[srcreg]);
+}
+
+// 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
+8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[srcreg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+}
+
+// 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
+8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
+ State.regs[srcreg]);
+}
+
+// 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
+8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
+}
+
+// 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
+8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_word (State.regs[dstreg], State.regs[srcreg]);
+ State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
+}
+
+
+// 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
+8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
+"mov"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[REG_SP]
+ + FETCH24 (IMM24A, IMM24B, IMM24C));
+}
+
+// 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
+8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
+ State.regs[srcreg]);
+}
+
+// 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,sp),Rn
+8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (State.regs[REG_SP]
+ + FETCH24 (IMM24A, IMM24B, IMM24C));
+}
+
+// 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
+8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
+ State.regs[srcreg]);
+}
+
+// 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
+8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[REG_SP]
+ + FETCH24 (IMM24A, IMM24B, IMM24C));
+}
+
+// 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
+8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
+ State.regs[srcreg]);
+}
+
+// 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
+8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[srcreg]);
+ State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
+}
+
+// 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
+8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_half (State.regs[dstreg], State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
+}
+
+// 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
+8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
+"mac"
+*am33
+*am33_2
+{
+ int srcreg;
+ signed64 temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
+ * (signed64)State.regs[srcreg]);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
+8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
+"macu"
+*am33
+*am33_2
+{
+ int srcreg;
+ signed64 temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
+ * (unsigned64)State.regs[srcreg]);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
+8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
+"macb"
+*am33
+*am33_2
+{
+ int srcreg;
+ signed64 temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
+ * (signed64)State.regs[srcreg] & 0xff);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
+8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
+"macbu"
+*am33
+*am33_2
+{
+ int srcreg;
+ signed64 temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
+ * (unsigned64)State.regs[srcreg] & 0xff);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
+8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
+"mach"
+*am33
+*am33_2
+{
+ int srcreg;
+ signed64 temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
+ * (signed64)State.regs[srcreg] & 0xffff);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
+8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
+"machu"
+*am33
+*am33_2
+{
+ int srcreg;
+ signed64 temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
+ * (unsigned64)State.regs[srcreg] & 0xffff);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
+8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
+"mov"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
+}
+
+// 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
+8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
+}
+
+
+// 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
+8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
+}
+
+// 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
+8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
+}
+
+
+// 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
+8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
+}
+
+// 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
+8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
+}
+
+
+// 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
+8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
+"mov"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+// 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
+8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
+"movu"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+// 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
+8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
+"add"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
+}
+
+// 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
+8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
+"addc"
+*am33
+*am33_2
+{
+ int dstreg;
+ unsigned32 imm, reg2, sum;
+ int z, n, c, v;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+ reg2 = State.regs[dstreg];
+ sum = imm + reg2 + ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = sum;
+
+ z = ((PSW & PSW_Z) != 0) && (sum == 0);
+ n = (sum & 0x80000000);
+ c = (sum < imm) || (sum < reg2);
+ v = ((reg2 & 0x80000000) == (imm & 0x80000000)
+ && (reg2 & 0x80000000) != (sum & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
+8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
+"sub"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
+}
+
+// 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
+8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
+"subc"
+*am33
+*am33_2
+{
+ int dstreg;
+ unsigned32 imm, reg2, difference;
+ int z, n, c, v;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+ reg2 = State.regs[dstreg];
+ difference = reg2 - imm - ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = difference;
+
+ z = ((PSW & PSW_Z) != 0) && (difference == 0);
+ n = (difference & 0x80000000);
+ c = (imm > reg2);
+ v = ((reg2 & 0x80000000) == (imm & 0x80000000)
+ && (reg2 & 0x80000000) != (difference & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
+8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
+"cmp"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+}
+
+// 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
+8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
+"mov"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_xreg (SD_, XRN0);
+
+ State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+// 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
+8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
+"and"
+*am33
+*am33_2
+{
+ int dstreg;
+ int z,n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
+8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
+"or"
+*am33
+*am33_2
+{
+ int dstreg;
+ int z,n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
+8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
+"xor"
+*am33
+*am33_2
+{
+ int dstreg;
+ int z,n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
+8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
+"asr"
+*am33
+*am33_2
+{
+ int dstreg;
+ signed32 temp;
+ int c, z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = State.regs[dstreg];
+ c = temp & 1;
+ temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+ State.regs[dstreg] = temp;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+// 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
+8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
+"lsr"
+*am33
+*am33_2
+{
+ int dstreg;
+ int z, n, c;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ c = State.regs[dstreg] & 1;
+ State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+// 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
+8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
+"asl"
+*am33
+*am33_2
+{
+ int dstreg;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn
+8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
+"mul"
+*am33
+*am33_2
+{
+ int dstreg;
+ unsigned64 temp;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((signed64)(signed32)State.regs[dstreg]
+ * (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
+ State.regs[dstreg] = temp & 0xffffffff;
+ State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn
+8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
+"mulu"
+*am33
+*am33_2
+{
+ int dstreg;
+ unsigned64 temp;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned64)State.regs[dstreg]
+ * (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
+ State.regs[dstreg] = temp & 0xffffffff;
+ State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
+8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
+"btst"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+}
+
+// 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
+8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[srcreg]
+ + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
+8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[srcreg]);
+}
+
+// 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
+8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (State.regs[srcreg]
+ + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
+8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[srcreg]);
+}
+
+// 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
+8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[srcreg]
+ + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
+8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[srcreg]);
+}
+
+// 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
+8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+// 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
+8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_word (State.regs[dstreg], State.regs[srcreg]);
+ State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+
+// 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
+8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
+"mov"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[REG_SP]
+ + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
+8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[srcreg]);
+}
+
+// 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
+8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (State.regs[REG_SP]
+ + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
+8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[srcreg]);
+}
+
+// 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
+8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[REG_SP]
+ + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
+8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[srcreg]);
+}
+
+
+// 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
+8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[srcreg]);
+ State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+// 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
+8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_half (State.regs[dstreg], State.regs[srcreg]);
+ State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+
+// 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn
+8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
+"mac"
+*am33
+*am33_2
+{
+ int srcreg, imm;
+ signed64 temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((signed64)(signed32)State.regs[srcreg]
+ * (signed64)(signed32)imm);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn
+8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
+"macu"
+*am33
+*am33_2
+{
+ int srcreg, imm;
+ signed64 temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((unsigned64)State.regs[srcreg]
+ * (unsigned64)imm);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn
+8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
+"macb"
+*am33
+*am33_2
+{
+ int srcreg, imm;
+ signed32 temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff)
+ * (signed32)(signed8)(imm & 0xff));
+ sum = State.regs[REG_MCRL] + temp;
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn
+8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
+"macbu"
+*am33
+*am33_2
+{
+ int srcreg, imm;
+ signed32 temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((unsigned32)(State.regs[srcreg] & 0xff)
+ * (unsigned32)(imm & 0xff));
+ sum = State.regs[REG_MCRL] + temp;
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn
+8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
+"mach"
+*am33
+*am33_2
+{
+ int srcreg, imm;
+ signed32 temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
+ * (signed32)(signed16)(imm & 0xffff));
+ sum = State.regs[REG_MCRL] + temp;
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn
+8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
+"machu"
+*am33
+*am33_2
+{
+ int srcreg, imm;
+ signed32 temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
+ * (unsigned32)(imm & 0xffff));
+ sum = State.regs[REG_MCRL] + temp;
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn
+8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
+"dmach"
+*am33
+*am33_2
+{
+ int srcreg, imm;
+ signed32 temp, temp2, sum;
+ int v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
+ * (signed32)(signed16)(imm & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff)
+ * (signed32)(signed16)((imm >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn
+8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
+"dmachu"
+*am33
+*am33_2
+{
+ int srcreg, imm;
+ signed32 temp, temp2, sum;
+ int v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
+ * (unsigned32)(imm & 0xffff));
+ temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff)
+ * (unsigned32)((imm >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn
+8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
+"dmulh"
+*am33
+*am33_2
+{
+ int imm, dstreg;
+ signed32 temp;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
+ * (signed32)(signed16)(imm & 0xffff));
+ State.regs[REG_MDRQ] = temp;
+ temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
+ * (signed32)(signed16)((imm>>16) & 0xffff));
+ State.regs[dstreg] = temp;
+}
+
+// 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn
+8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
+"dmulhu"
+*am33
+*am33_2
+{
+ int imm, dstreg;
+ signed32 temp;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
+ * (unsigned32)(imm & 0xffff));
+ State.regs[REG_MDRQ] = temp;
+ temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
+ * (unsigned32)((imm >>16) & 0xffff));
+ State.regs[dstreg] = temp;
+}
+
+// 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
+8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
+"mov"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
+8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
+"mov"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+}
+
+// 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
+8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
+8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
+"movbu"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+}
+
+// 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
+8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
+8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
+"movhu"
+*am33
+*am33_2
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+}
+
+// 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
+"add_add"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
+"add_add"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
+"add_sub"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
+"add_sub"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
+"add_cmp"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] += State.regs[srcreg1];
+}
+
+// 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
+"add_cmp"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] += State.regs[srcreg1];
+}
+
+// 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
+"add_mov"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
+"add_mov"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
+"add_asr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
+"add_asr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
+"add_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
+"add_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
+"add_asl"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
+"add_asl"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
+"cmp_add"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] += State.regs[srcreg2];
+}
+
+// 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
+"cmp_add"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+}
+
+// 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
+"cmp_sub"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] -= State.regs[srcreg2];
+}
+
+// 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
+"cmp_sub"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+}
+
+// 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
+"cmp_mov"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] = State.regs[srcreg2];
+}
+
+// 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
+"cmp_mov"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+}
+
+// 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
+"cmp_asr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+}
+
+// 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
+"cmp_asr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+}
+
+// 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
+"cmp_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+}
+
+// 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
+"cmp_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] >>= IMM4;
+}
+
+
+// 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
+"cmp_asl"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+}
+
+// 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
+"cmp_asl"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] <<= IMM4;
+}
+
+// 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
+"sub_add"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
+"sub_add"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
+"sub_sub"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
+"sub_sub"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
+"sub_cmp"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] -= State.regs[srcreg1];
+}
+
+// 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
+"sub_cmp"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] -= State.regs[srcreg1];
+}
+
+// 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
+"sub_mov"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
+"sub_mov"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
+"sub_asr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
+"sub_asr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
+"sub_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
+"sub_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
+"sub_asl"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
+"sub_asl"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
+"mov_add"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
+"mov_add"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
+"mov_sub"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
+"mov_sub"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
+"mov_cmp"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] = State.regs[srcreg1];
+}
+
+// 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
+"mov_cmp"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] = State.regs[srcreg1];
+}
+
+// 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
+"mov_mov"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
+"mov_mov"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
+"mov_asr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
+"mov_asr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
+"mov_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
+"mov_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
+"mov_asl"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
+"mov_asl"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
+"add_add"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
+"add_add"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
+"add_sub"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
+"add_sub"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
+"add_cmp"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] += EXTEND4 (IMM4A);
+}
+
+// 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
+"add_cmp"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] += EXTEND4 (IMM4A);
+}
+
+// 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
+"add_mov"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
+"add_mov"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
+"add_asr"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
+"add_asr"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
+"add_lsr"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2
+8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
+"add_lsr"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
+"add_asl"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2
+8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
+"add_asl"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
+"cmp_add"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] += State.regs[srcreg2];
+}
+
+// 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
+"cmp_add"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+}
+
+// 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
+"cmp_sub"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] -= State.regs[srcreg2];
+}
+
+// 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
+"cmp_sub"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+}
+
+// 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
+"cmp_mov"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] = State.regs[srcreg2];
+}
+
+// 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
+"cmp_mov"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+}
+
+// 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
+"cmp_asr"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+ signed int temp;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+}
+
+// 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
+"cmp_asr"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+ signed int temp;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+}
+
+// 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
+"cmp_lsr"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+}
+
+// 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2
+8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
+"cmp_lsr"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] >>= IMM4;
+}
+
+
+// 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
+"cmp_asl"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+}
+
+// 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2
+8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
+"cmp_asl"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] <<= IMM4;
+}
+
+// 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
+"sub_add"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
+"sub_add"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
+"sub_sub"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
+"sub_sub"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
+"sub_cmp"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] -= EXTEND4 (IMM4A);
+}
+
+// 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
+"sub_cmp"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] -= EXTEND4 (IMM4A);
+}
+
+// 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
+"sub_mov"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
+"sub_mov"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
+"sub_asr"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
+"sub_asr"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
+"sub_lsr"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2
+8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
+"sub_lsr"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
+"sub_asl"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2
+8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
+"sub_asl"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
+"mov_add"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
+"mov_add"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
+"mov_sub"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
+"mov_sub"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
+"mov_cmp"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] = EXTEND4 (IMM4A);
+}
+
+// 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
+"mov_cmp"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] = EXTEND4 (IMM4A);
+}
+
+// 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
+"mov_mov"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
+"mov_mov"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
+"mov_asr"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
+"mov_asr"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
+"mov_lsr"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2
+8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
+"mov_lsr"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
+"mov_asl"
+*am33
+*am33_2
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2
+8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
+"mov_asl"
+*am33
+*am33_2
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
+"and_add"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
+"and_add"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
+"and_sub"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
+"and_sub"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
+"and_cmp"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] &= State.regs[srcreg1];
+}
+
+// 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
+"and_cmp"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] &= State.regs[srcreg1];
+}
+
+// 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
+"and_mov"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
+"and_mov"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
+"and_asr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
+"and_asr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
+"and_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
+"and_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
+"and_asl"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
+"and_asl"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
+"dmach_add"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed32 temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
+"dmach_add"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ signed32 temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
+"dmach_sub"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed32 temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
+"dmach_sub"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ signed32 temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
+"dmach_cmp"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed32 temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
+"dmach_cmp"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ signed32 temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
+"dmach_mov"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed32 temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
+"dmach_mov"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ signed32 temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
+"dmach_asr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed32 temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
+"dmach_asr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ signed32 temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
+"dmach_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed32 temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
+"dmach_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ signed32 temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = sum;
+}
+
+
+// 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
+"dmach_asl"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed32 temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
+"dmach_asl"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ signed32 temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
+"xor_add"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
+"xor_add"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
+"xor_sub"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
+"xor_sub"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
+"xor_cmp"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] ^= State.regs[srcreg1];
+}
+
+// 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
+"xor_cmp"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] ^= State.regs[srcreg1];
+}
+
+// 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
+"xor_mov"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
+"xor_mov"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
+"xor_asr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
+"xor_asr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
+"xor_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
+"xor_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
+"xor_asl"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
+"xor_asl"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
+"swhw_add"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
+"swhw_add"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
+"swhw_sub"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
+"swhw_sub"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
+"swhw_cmp"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+}
+
+// 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
+"swhw_cmp"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+}
+
+// 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
+"swhw_mov"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
+"swhw_mov"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
+"swhw_asr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
+"swhw_asr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
+"swhw_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
+"swhw_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
+"swhw_asl"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
+"swhw_asl"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
+"or_add"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
+"or_add"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
+"or_sub"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
+"or_sub"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
+"or_cmp"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] |= State.regs[srcreg1];
+}
+
+// 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
+"or_cmp"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] |= State.regs[srcreg1];
+}
+
+// 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
+"or_mov"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
+"or_mov"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
+"or_asr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
+"or_asr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
+"or_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
+"or_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
+"or_asl"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
+"or_asl"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
+"sat16_add"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
+"sat16_add"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
+"sat16_sub"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
+"sat16_sub"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
+"sat16_cmp"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[dstreg2], State.regs[dstreg1]);
+ if (State.regs[srcreg1] >= 0x7fff)
+ State.regs[dstreg1] = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ State.regs[dstreg1] = 0xffff8000;
+ else
+ State.regs[dstreg1] = State.regs[srcreg1];
+}
+
+// 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
+"sat16_cmp"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ if (State.regs[srcreg1] >= 0x7fff)
+ State.regs[dstreg1] = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ State.regs[dstreg1] = 0xffff8000;
+ else
+ State.regs[dstreg1] = State.regs[srcreg1];
+}
+
+// 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
+"sat16_mov"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
+"sat16_mov"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
+"sat16_asr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
+"sat16_asr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
+"sat16_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
+"sat16_lsr"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
+"sat16_asl"
+*am33
+*am33_2
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
+"sat16_asl"
+*am33
+*am33_2
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
+"mov_llt"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
+"mov_lgt"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if (!((PSW & PSW_Z)
+ || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
+"mov_lge"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
+"mov_lle"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if ((PSW & PSW_Z)
+ || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
+"mov_lcs"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if (PSW & PSW_C)
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
+"mov_lhi"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
+"mov_lcc"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if (!(PSW & PSW_C))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
+"mov_lls"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
+"mov_leq"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if (PSW & PSW_Z)
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
+"mov_lne"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if (!(PSW & PSW_Z))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
+"mov_lra"
+*am33
+*am33_2
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+}
+
+:include::am33_2:am33-2.igen
Index: ChangeLog
===================================================================
--- ChangeLog (nonexistent)
+++ ChangeLog (revision 842)
@@ -0,0 +1,1178 @@
+2010-01-09 Ralf Wildenhues
+
+ * configure: Regenerate.
+
+2009-08-22 Ralf Wildenhues
+
+ * config.in: Regenerate.
+ * configure: Likewise.
+
+ * configure: Regenerate.
+
+2008-07-11 Hans-Peter Nilsson
+
+ * configure: Regenerate to track ../common/common.m4 changes.
+ * config.in: Ditto.
+
+2008-06-06 Vladimir Prus
+ Daniel Jacobowitz
+ Joseph Myers
+
+ * configure: Regenerate.
+
+2006-12-21 Hans-Peter Nilsson
+
+ * acconfig.h: Remove.
+ * config.in: Regenerate.
+
+2006-06-13 Richard Earnshaw
+
+ * configure: Regenerated.
+
+2006-06-05 Daniel Jacobowitz
+
+ * configure: Regenerated.
+
+2006-05-31 Daniel Jacobowitz
+
+ * configure: Regenerated.
+
+2006-03-29 Hans-Peter Nilsson
+
+ * configure: Regenerate.
+
+2005-03-23 Mark Kettenis
+
+ * configure: Regenerate.
+
+2005-01-14 Andrew Cagney
+
+ * configure.ac: Sinclude aclocal.m4 before common.m4. Add
+ explicit call to AC_CONFIG_HEADER.
+ * configure: Regenerate.
+
+2005-01-12 Andrew Cagney
+
+ * configure.ac: Update to use ../common/common.m4.
+ * configure: Re-generate.
+
+2005-01-11 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+2005-01-07 Andrew Cagney
+
+ * configure.ac: Rename configure.in, require autoconf 2.59.
+ * configure: Re-generate.
+
+2004-12-08 Hans-Peter Nilsson
+
+ * configure: Regenerate for ../common/aclocal.m4 update.
+
+2004-06-26 Alexandre Oliva
+
+ 2000-08-07 Graham Stott
+ * am33-2.igen (fmadd, fmsub, fmnadd, fmnsub): Correct typo.
+ 2000-05-29 Alexandre Oliva
+ * interp.c (fpu_disabled_exception, fpu_unimp_exception,
+ fpu_check_signal_exception): Take additional state arguments.
+ Print exception type and call program_interrupt. Adjust callers.
+ (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
+ fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Take additional
+ arguments.
+ * mn10300_sim.h (fpu_disabled_exception, fpu_unimp_exception,
+ fpu_check_signal_exception): Adjust prototypes.
+ (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
+ fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Likewise.
+ * am33-2.igen: Adjust calls.
+ 2000-05-19 Alexandre Oliva
+ * op_utils.c (cmp2fcc): Moved...
+ * interp.c: ... here.
+ 2000-05-18 Alexandre Oliva
+ * am33-2.igen: Use `unsigned32', `signed32', `unsigned64' or
+ `signed64' where type width is relevant.
+ 2000-05-15 Alexandre Oliva
+ * mn10300_sim.h: Include sim-fpu.h.
+ (FD2FPU, FPU2FD): Enclose the FD argument in parentheses.
+ (fpu_check_signal_exception): Declare.
+ (struct fp_prec_t, fp_single_prec, fp_double_prec): Likewise.
+ (FP_SINGLE, FP_DOUBLE): Shorthands for fp_*_prec.
+ (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
+ fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Declare.
+ * interp.c (fpu_disabled_exception): Document.
+ (fpu_unimp_exception): Likewise.
+ (fpu_check_signal_exception): Define.
+ (reg2val_32, round_32, val2reg_32, fp_single_prec): Likewise.
+ (reg2val_64, round_64, val2reg_64, fp_double_prec): Likewise.
+ (REG2VAL, ROUND, VAL2REG): Define shorthands.
+ (fpu_status_ok): Define.
+ (fpu_rsqrt, fpu_cmp, fpu_add, fpu_sub, fpu_mul, fpu_div,
+ fpu_fmadd, fpu_fmsub, fpu_fnmadd, fpu_fnmsub): Define.
+ * am33-2.igen (frsqrt, fcmp, fadd, fsub, fmul, fdiv,
+ fmadd, fmsub, fnmadd, fnmsub): Use new functions.
+ 2000-04-27 Alexandre Oliva
+ * interp.c (sim_create_inferior): Set PSW bit to enable FP insns
+ if architecture is AM33/2.0.
+ * am33.igen: Include am33-2.igen.
+ 2000-04-23 Alexandre Oliva
+ * mn10300.igen (movm, call, ret, retf): Check for am33_2 too.
+ * am33.igen (movm): Likewise.
+ 2000-04-19 Alexandre Oliva
+ * am33.igen: Added `*am33_2' to some instructions that were
+ missing it.
+ 2000-04-07 Alexandre Oliva
+ * am33-2.igen: New file. All insns implemented, but FP flags are
+ only set for fcmp, exceptional conditions are not handled yet.
+ * Makefile.in (IGEN_INSN): Added am33-2.igen.
+ (tmp-igen): Added -M am33_2.
+ * mn10300.igen, am33.igen: Added `*am33_2' to all insns.
+ * gencode.c: Support FMT_D3.
+ * mn10300_sim.h (dword): New type.
+ (struct _state): Added fpregs.
+ (REG_FPCR, FPCR): New define. All assorted bitmaps.
+ (XS2FS, AS2FS, Xf2FD): New macros.
+ (FS2FPU, FD2FPU, FPU2FS, FPU2FD): Likewise.
+ (load_dword, store_dword): New functions or macros.
+ (u642dw, dw2u64): New functions.
+ (fpu_disabled_exception, fpu_unimp_exception): Declared.
+ * interp.c (fpu_disabled_exception): Defined; no actual
+ implementation.
+ (fpu_unimp_exception): Likewise.
+ * op_utils.c (cmp2fcc): New function.
+
+ * interp.c, mn10300_sim.h, op_utils.c: Convert function prototypes
+ and definitions to ISO C.
+
+ * gencode.c, simops.c: Delete.
+ * Makefile.in: Remove non-COMMON dependencies and commands.
+
+ * configure.in: Use common simulator always. Don't subst sim_gen
+ nor mn10300_common.
+ * configure: Rebuilt.
+ * Makefile.in (WITHOUT_COMMON_OBJS, WITHOUT_COMMON_INTERP_DEP,
+ WITHOUT_COMMON_RUN_OBJS): Remove.
+ (WITH_COMMON_OBJS): Rename to MN10300_OBJS.
+ (WITH_COMMON_INTERP_DEP): Rename to MN10300_INTERP_DEP.
+ (WITH_COMMON_RUN_OBJS): Rename to SIM_RUN_OBJS.
+ (SIM_EXTRA_CFLAGS): Don't use @sim_gen@.
+ * interp.c: Remove non-common bits.
+ * mn10300_sim.h: Likewise.
+
+2003-08-28 Andrew Cagney
+
+ * dv-mn103ser.c (do_polling_event): Change type of "serial_reg" to
+ "long".
+ (read_status_reg): Cast "serial_reg" to "long".
+ * dv-mn103tim.c (do_counter_event): Change type of "timer_nr" to
+ "long".
+ (do_counter6_event, write_mode_reg, write_tm6md): Ditto.
+
+2003-02-27 Andrew Cagney
+
+ * interp.c (sim_open, sim_create_inferior, sim_open)
+ (sim_create_inferior): Rename _bfd to bfd.
+
+2003-02-26 Andrew Cagney
+
+ * am33.igen: Call sim_engine_abort instead of abort.
+
+2003-02-26 David Carlton
+
+ * dv-mn103tim.c (read_special_timer6_reg): Add break after
+ empty default: label.
+ (write_special_timer6_reg): Ditto.
+ Update copyright.
+
+2002-11-28 Andrew Cagney
+
+ * sim-main.h: Only include "idecode.h" once.
+ * Makefile.in (SIM_EXTRA_DEPS): Define.
+
+2002-06-16 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+2002-06-09 Andrew Cagney
+
+ * Makefile.in (INCLUDE): Update path to callback.h.
+ * mn10300_sim.h: Include "gdb/callback.h" and "gdb/remote-sim.h".
+ * tconfig.in: Ditto.
+
+2001-05-06 Jim Blandy
+
+ * mn10300.igen: Doc fixes.
+
+2001-04-26 Alexandre Oliva
+
+ * Makefile.in (idecode.o, op_utils.o, semantics.o, simops.o):
+ Depend on targ-vals.h.
+
+2001-04-15 J.T. Conklin
+
+ * Makefile.in (simops.o): Add simops.h to dependency list.
+
+Wed Aug 9 02:24:53 2000 Graham Stott
+
+ * am33.igen: Warning clean-up.
+ (movm): Initialize PC and mask.
+ (mov, movbu, movhu): Set srcreg2 from RI0.
+ (bsch): Initialize c.
+ (sat16_cmp): Actually do the comparison.
+ (mov_llt): Do not overwrite dstreg with uninitialized variable.
+
+Tue May 23 21:39:23 2000 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+2000-05-22 Alexandre Oliva
+
+ * am33.igen: Fix leading comments of SP-relative offset insns that
+ referred to other registers. Make their offsets unsigned.
+
+2000-05-18 Alexandre Oliva
+
+ * mn10300_sim.h (genericAdd, genericSub, genericCmp, genericOr,
+ genericXor, genericBtst): Use `unsigned32'.
+ * op_utils.c: Likewise.
+ * mn10300.igen, am33.igen: Use `unsigned32', `signed32',
+ `unsigned64' or `signed64' where type width is relevant.
+
+2000-04-25 Alexandre Oliva
+
+ * am33.igen (inc4 Rn): Use genericAdd so as to modify flags.
+
+2000-04-09 Alexandre Oliva
+
+ * am33.igen: Make SP-relative offsets unsigned. Add `*am33' for
+ some instructions that were missing it.
+
+2000-03-03 Alexandre Oliva
+
+ * Makefile.in (IGEN_INSN): Added am33.igen.
+
+Thu Sep 2 18:15:53 1999 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Tue Jul 13 13:26:20 1999 Andrew Cagney
+
+ * interp.c: Clarify error message reporting an unknown board.
+
+1999-05-08 Felix Lee
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+1999-04-16 Frank Ch. Eigler
+
+ * interp.c (program_interrupt): Detect undesired recursion using
+ static flag. Set NMIRC register's SYSEF flag during
+ --board=stdeval1 mode.
+ * dv-mn103-int.c (write_icr): Add backdoor address to allow CPU to
+ set SYSEF flag.
+
+1999-04-02 Keith Seitz
+
+ * Makefile.in (SIM_EXTRA_CFLAGS): Define a POLL_QUIT_INTERVAL
+ for use in the simulator so that the poll_quit callback is
+ not called too often.
+
+Tue Mar 9 21:26:41 1999 Andrew Cagney
+
+ * dv-mn103int.c (mn103int_ioctl): Return something.
+ * dv-mn103tim.c (write_tm6md): GCC suggested parentheses around &&
+ within ||.
+
+Tue Feb 16 23:57:17 1999 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300.igen (retf): Fix return address computation and store
+ the new pc value into nia.
+
+1998-12-29 Frank Ch. Eigler
+
+ * Makefile.in (WITH_COMMON_OBJS): Build also dv-sockser.o.
+ * interp.c (sim_open): Add stub mn103002 cache control memory regions.
+ Set OPERATING_ENVIRONMENT on "stdeval1" board.
+ (mn10300_core_signal): New function to intercept memory errors.
+ (program_interrupt): New function to dispatch to exception vector
+ (mn10300_exception_*): New functions to snapshot pre/post exception
+ state.
+ * sim-main.h (SIM_CORE_SIGNAL): Define hook - call mn10300_core_signal.
+ (SIM_ENGINE_HALT_HOOK): Do nothing.
+ (SIM_CPU_EXCEPTION*): Define hooks to call mn10300_cpu_exception*().
+ (_sim_cpu): Add exc_* fields to store register value snapshots.
+ * dv-mn103ser.c (*): Support dv-sockser backend for UART I/O.
+ Various endianness and warning fixes.
+ * mn10300.igen (illegal): Call program_interrupt on error.
+ (break): Call program_interrupt on breakpoint
+
+ Several changes from and
+ merged in:
+ * dv-mn103int.c (mn103int_ioctl): New function for NMI
+ generation. (mn103int_finish): Install it as ioctl handler.
+ * dv-mn103tim.c: Support timer 6 specially. Endianness fixes.
+
+Wed Oct 14 12:11:05 1998 Jeffrey A Law (law@cygnus.com)
+
+ * am33.igen: Allow autoincrement stores using the same register
+ for source and destination operands.
+
+Mon Aug 31 10:19:55 1998 Jeffrey A Law (law@cygnus.com)
+
+ * am33.igen: Reverse HI/LO outputs of 4 operand "mul" and "mulu".
+
+Fri Aug 28 14:40:49 1998 Joyce Janczyn
+
+ * interp.c (sim_open): Check for invalid --board option, fix
+ indentation, allocate memory for mem control and DMA regs.
+
+Wed Aug 26 09:29:38 1998 Joyce Janczyn
+
+ * mn10300.igen (div,divu): Fix divide instructions so divide by 0
+ behaves like the hardware.
+
+Mon Aug 24 11:50:09 1998 Joyce Janczyn
+
+ * sim-main.h (SIM_HANDLES_LMA): Define SIM_HANDLES_LMA.
+
+Wed Aug 12 12:36:07 1998 Jeffrey A Law (law@cygnus.com)
+
+ * am33.igen: Handle case where first DSP operation modifies a
+ register used in the second DSP operation correctly.
+
+Tue Jul 28 10:10:25 1998 Jeffrey A Law (law@cygnus.com)
+
+ * am33.igen: Detect cases where two operands must not match for
+ DSP instructions too.
+
+Mon Jul 27 12:04:17 1998 Jeffrey A Law (law@cygnus.com)
+
+ * am33.igen: Detect cases where two operands must not match in
+ non-DSP instructions.
+
+Fri Jul 24 18:15:21 1998 Joyce Janczyn
+
+ * op_utils.c (do_syscall): Rewrite to use common/syscall.c.
+ (syscall_read_mem, syscall_write_mem): New functions for syscall
+ callbacks.
+ * mn10300_sim.h: Add prototypes for syscall_read_mem and
+ syscall_write_mem.
+ * mn10300.igen: Change C++ style comments to C style comments.
+ Check for divide by zero in div and divu ops.
+
+Fri Jul 24 12:49:28 1998 Jeffrey A Law (law@cygnus.com)
+
+ * am33.igen (translate_xreg): New function. Use it as needed.
+
+Thu Jul 23 10:05:28 1998 Jeffrey A Law (law@cygnus.com)
+
+ * am33.igen: Add some missing instructions.
+
+ * am33.igen: Autoincrement loads/store fixes.
+
+Tue Jul 21 09:48:14 1998 Jeffrey A Law (law@cygnus.com)
+
+ * am33.igen: Add mov_lCC DSP instructions.
+
+ * am33.igen: Add most am33 DSP instructions.
+
+Thu Jul 9 10:06:55 1998 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300.igen: Fix Z bit for addc and subc instructions.
+ Minor fixes in multiply/divide patterns.
+
+ * am33.igen: Add missing mul[u] imm32,Rn. Fix condition code
+ handling for many instructions. Fix sign extension for some
+ 24bit immediates.
+
+ * am33.igen: Fix Z bit for remaining addc/subc instructions.
+ Do not sign extend immediate for mov imm,XRn.
+ More random mul, mac & div fixes.
+ Remove some unused variables.
+ Sign extend 24bit displacement in memory addresses.
+
+ * am33.igen: Fix Z bit for addc Rm,Rn and subc Rm,Rn. Various
+ fixes to 2 register multiply, divide and mac instructions. Set
+ Z,N correctly for sat16. Sign extend 24 bit immediate for add,
+ and sub instructions.
+
+ * am33.igen: Add remaining non-DSP instructions.
+
+Wed Jul 8 16:29:12 1998 Jeffrey A Law (law@cygnus.com)
+
+ * am33.igen (translate_rreg): New function. Use it as appropriate.
+
+ * am33.igen: More am33 instructions. Fix "div".
+
+Mon Jul 6 15:39:22 1998 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300.igen: Add am33 support.
+
+ * Makefile.in: Use multi-sim to support both a mn10300 and am33
+ simulator.
+
+ * am33.igen: Add many more am33 instructions.
+
+Wed Jul 1 17:07:09 1998 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300_sim.h (FETCH24): Define.
+
+ * mn10300_sim.h: Add defines for some registers found on the AM33.
+ * am33.igen: New file with some am33 support.
+
+Tue Jun 30 11:23:20 1998 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300_sim.h: Include bfd.h
+ (struct state): Add more room for processor specific registers.
+ (REG_E0): Define.
+
+Thu Jun 25 10:12:03 1998 Joyce Janczyn
+
+ * dv-mn103tim.c: Include sim-assert.h
+ * dv-mn103ser.c (do_polling_event): Check for incoming data on
+ serial line and schedule next polling event.
+ (read_status_reg): schedule events to check for incoming data on
+ serial line and issue interrupt if necessary.
+
+Fri Jun 19 16:47:27 1998 Joyce Janczyn
+
+ * interp.c (sim_open): hook up serial 1 and 2 ports properly (typo).
+
+Fri Jun 19 11:59:26 1998 Joyce Janczyn
+
+ * interp.c (board): Rename am32 to stdeval1 as this is the name
+ consistently used to refer to the mn1030002 board.
+
+Thu June 18 14:37:14 1998 Joyce Janczyn
+ * interp.c (sim_open): Fix typo in address of EXTMD register
+ (0x34000280, not 0x3400280).
+
+Wed Jun 17 18:00:18 1998 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c (syscall): Handle change in opcode # for syscall.
+ * mn10300.igen (syscall): Likewise.
+
+Tue June 16 09:36:21 1998 Joyce Janczyn
+ * dv-mn103int.c (mn103int_finish): Regular interrupts (not NMI or
+ reset) are not enabled on reset.
+
+Sun June 14 17:04:00 1998 Joyce Janczyn
+ * dv-mn103iop.c (write_*_reg): Check for attempt to write r/o
+ register bits.
+ * dv-mn103ser.c: Fill in methods for reading and writing to serial
+ device registers.
+ * interp.c (sim_open): Make the serial device a polling device.
+
+Fri June 12 16:24:00 1998 Joyce Janczyn
+ * dv-mn103iop.c: New file for handling am32 io ports.
+ * configure.in: Add mn103iop to hw_device list.
+ * configure: Re-generate.
+ * interp.c (sim_open): Create io port device.
+
+Wed June 10 14:34:00 1998 Joyce Janczyn
+ * dv-mn103int.c (external_group): Use enumerated types to access
+ correct group addresses.
+ * dv-mn103tim.c (do_counter_event): Underflow of cascaded timer
+ triggers an interrupt on the higher-numbered timer's port.
+
+Mon June 8 13:30:00 1998 Joyce Janczyn
+ * interp.c: (mn10300_option_handler): New function parses arguments
+ using sim-options.
+ * (board): Add --board option for specifying am32.
+ * (sim_open): Create new timer and serial devices and control
+ configuration of other am32 devices via board option.
+ * dv-mn103tim.c, dv-mn103ser.c: New files for timers and serial devices.
+ * dv-mn103cpu.c: Fix typos in opening comments.
+ * dv-mn103int.c: Adjust interrupt controller settings for am32 instead of am30.
+ * configure.in: Add mn103tim and mn103ser to hw_device list.
+ * configure: Re-generate.
+
+Mon May 25 20:50:35 1998 Andrew Cagney
+
+ * dv-mn103int.c, dv-mn103cpu.c: Rename *_callback to *_method.
+
+ * dv-mn103cpu.c, dv-mn103int.c: Include hw-main.h and
+ sim-main.h. Declare a struct hw_descriptor instead of struct
+ hw_device_descriptor.
+
+Mon May 25 17:33:33 1998 Andrew Cagney
+
+ * dv-mn103cpu.c (struct mn103cpu): Change type of pending_handler
+ to struct hw_event.
+
+Fri May 22 12:17:41 1998 Andrew Cagney
+
+ * configure.in (SIM_AC_OPTION_HARDWARE): Add argument "yes".
+
+Wed May 6 13:29:06 1998 Andrew Cagney
+
+ * interp.c (sim_open): Create a polling PAL device.
+
+Fri May 1 16:39:15 1998 Andrew Cagney
+
+ * dv-mn103int.c (mn103int_port_event):
+ (mn103int_port_event):
+ (mn103int_io_read_buffer):
+ (mn103int_io_write_buffer):
+
+ * dv-mn103cpu.c (deliver_mn103cpu_interrupt): Drop CPU/CIA args.
+ (mn103cpu_port_event): Ditto.
+ (mn103cpu_io_read_buffer): Ditto.
+ (mn103cpu_io_write_buffer): Ditto.
+
+Tue Apr 28 18:33:31 1998 Geoffrey Noer
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Sun Apr 26 15:31:55 1998 Tom Tromey
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Sun Apr 26 15:19:55 1998 Tom Tromey
+
+ * acconfig.h: New file.
+ * configure.in: Reverted change of Apr 24; use sinclude again.
+
+Fri Apr 24 14:16:40 1998 Tom Tromey
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Fri Apr 24 11:19:07 1998 Tom Tromey
+
+ * configure.in: Don't call sinclude.
+
+Tue Apr 14 10:03:02 1998 Andrew Cagney
+
+ * mn10300_sim.h: Declare all functions in op_utils.c using
+ INLINE_SIM_MAIN.
+ * op_utils.c: Ditto.
+ * sim-main.c: New file. Include op_utils.c.
+
+ * mn10300.igen (mov, cmp): Use new igen operators `!' and `=' to
+ differentiate between MOV/CMP immediate/register instructions.
+
+ * configure.in (SIM_AC_OPTION_INLINE): Add and enable.
+ * configure: Regenerate.
+
+Sat Apr 4 20:36:25 1998 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Mar 27 16:15:52 1998 Andrew Cagney
+
+ * interp.c (hw): Delete variable, moved to SIM_DESC.
+ (sim_open): Delete calls to hw_tree_create, hw_tree_finish.
+ Handled by sim-module.
+ (sim_open): Do not anotate tree with trace properties, handled by
+ sim-hw.c
+ (sim_open): Call sim_hw_parse instead of hw_tree_parse.
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Thu Mar 26 20:46:18 1998 Stu Grossman
+
+ * dv-mn103cpu.c (deliver_mn103cpu_interrupt): Save the entire PC
+ on the stack when delivering interrupts (not just the lower
+ half)...
+ * mn10300.igen (mov (Di,Am),Dn): Fix decode. Registers were
+ specified in the wrong order.
+
+Fri Mar 27 00:56:40 1998 Andrew Cagney
+
+ * dv-mn103cpu.c (deliver_mn103cpu_interrupt): Stop loss of
+ succeeding interrupts, clear pending_handler when the handler
+ isn't re-scheduled.
+
+Thu Mar 26 10:11:01 1998 Stu Grossman
+
+ * Makefile.in (tmp-igen): Prefix all usage of move-if-change
+ script with $(SHELL) to make NT native builds happy.
+ * configure: Regenerate because of change to ../common/aclocal.m4.
+
+Thu Mar 26 11:22:31 1998 Andrew Cagney
+
+ * configure.in: Make --enable-sim-common the default.
+ * configure: Re-generate.
+
+ * sim-main.h (CIA_GET, CIA_SET): Save/restore current instruction
+ address into Sate.regs[REG_PC] instead of common struct.
+
+Wed Mar 25 17:42:00 1998 Joyce Janczyn
+
+ * mn10300.igen (cmp imm8,An): Do not sign extend imm8 value.
+
+Wed Mar 25 12:08:00 1998 Joyce Janczyn
+
+ * simops.c (OP_F0FD): Initialise variable 'sp'.
+
+Thu Mar 26 00:21:32 1998 Andrew Cagney
+
+ * dv-mn103int.c (decode_group): A group register every 4 bytes not
+ 8.
+ (write_icr): Rewrite equation updating request field.
+ (read_iagr): Fix check that interrupt is still pending.
+
+Wed Mar 25 16:14:50 1998 Andrew Cagney
+
+ * interp.c (sim_open): Tidy up device creation.
+
+ * dv-mn103int.c (mn103int_port_event): Drive NMI with non-zero
+ value.
+ (mn103int_io_read_buffer): Convert absolute address to register
+ block offsets.
+ (read_icr, write_icr): Convert block offset into group offset.
+
+Wed Mar 25 15:08:49 1998 Andrew Cagney
+
+ * interp.c (sim_open): Create second 1mb memory region at
+ 0x40000000.
+ (sim_open): Create a device tree.
+ (sim-hw.h): Include.
+ (do_interrupt): Delete, needs to use dv-mn103cpu.c
+
+ * dv-mn103int.c, dv-mn103cpu.c: New files.
+
+Wed Mar 25 08:47:38 1998 Andrew Cagney
+
+ * mn10300_sim.h (EXTRACT_PSW_LM, INSERT_PSW_LM, PSW_IE, PSW_LM):
+ Define.
+ (SP): Define.
+
+Wed Mar 25 12:35:29 1998 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Mar 25 10:24:48 1998 Andrew Cagney
+
+ * interp.c (sim-options.h): Include.
+ (sim_kind, myname): Declare when not using common framework.
+
+ * mn10300_sim.h (do_syscall, generic*): Provide prototypes for
+ functions found in op_utils.c
+
+ * mn10300.igen (add): Discard unused variables.
+
+ * configure, config.in: Re-generate with autoconf 2.12.1.
+
+Tue Mar 24 15:27:00 1998 Joyce Janczyn
+
+ Add support for --enable-sim-common option.
+ * Makefile.in (WITHOUT_COMMON_OBJS): Files included if
+ ! --enable-sim-common
+ (WITH_COMMON_OBJS): Files included if --enable-sim-common.
+ (MN10300_OBJS,MN10300_INTERP_DEP): New variables.
+ (SIM_OBJS): Rewrite.
+ ({WITHOUT,WITH}_COMMON_RUN_OBJS,SIM_RUN_OBJS): New variables.
+ (SIM_EXTRA_CFLAGS): New variable.
+ (clean-extra): Clean up igen files.
+ (../igen/igen,clean-igen,tmp-igen): New rules.
+ * configure.in: Add support for common framework via
+ --enable-sim-common.
+ * configure: Regenerate.
+ * interp.c: #include sim-main if WITH_COMMON, not mn10300_sim.h.
+ (hash,dispatch,sim_size): Don't compile if ! WITH_COMMON.
+ (init_system,sim_write,compare_simops): Likewise.
+ (sim_set_profile,sim_set_profile_size): Likewise.
+ (sim_stop,sim_resume,sim_trace,sim_info): Likewise.
+ (sim_set_callbacks,sim_stop_reason,sim_read,sim_load): Likewise.
+ (enum interrupt_type): New enum.
+ (interrupt_names): New global.
+ (do_interrupt): New function.
+ (sim_open): Define differently if WITH_COMMON.
+ (sim_close,sim_create_inferior,sim_do_command): Likewise.
+ * mn10300_sim.h ({load,store}_{byte,half,word}): Define versions
+ for WITH_COMMON.
+ * mn10300.igen: New file.
+ * mn10300.dc: New file.
+ * op_utils.c: New file.
+ * sim-main.h: New file.
+
+Wed Mar 18 12:38:12 1998 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Feb 27 18:36:04 1998 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c (inc): Fix typo.
+
+Wed Feb 25 01:59:29 1998 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c (signed multiply instructions): Cast input operands to
+ signed32 before casting them to signed64 so that the sign bit
+ is propagated properly.
+
+Mon Feb 23 20:23:19 1998 Mark Alexander
+
+ * Makefile.in: Last change was bad. Define NL_TARGET
+ so that targ-vals.h will be used instead of syscall.h.
+ * simops.c: Use targ-vals.h instead of syscall.h.
+ (OP_F020): Disable unsupported system calls.
+
+Mon Feb 23 09:44:38 1998 Mark Alexander
+
+ * Makefile.in: Get header files from libgloss/mn10300/sys.
+
+Sun Feb 22 16:02:24 1998 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Include sim-types.h.
+
+Wed Feb 18 13:07:08 1998 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c (multiply instructions): Cast input operands to a
+ signed64/unsigned64 type as appropriate.
+
+Tue Feb 17 12:47:16 1998 Andrew Cagney
+
+ * interp.c (sim_store_register, sim_fetch_register): Pass in
+ length parameter. Return -1.
+
+Sun Feb 1 16:47:51 1998 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Sat Jan 31 18:15:41 1998 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Mon Jan 19 22:26:29 1998 Doug Evans
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Mon Dec 15 23:17:11 1997 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Thu Dec 4 09:21:05 1997 Doug Evans
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Tue Nov 11 10:38:52 1997 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c (call:16 call:32): Stack adjustment is determined solely
+ by the imm8 field.
+
+Wed Oct 22 14:43:00 1997 Andrew Cagney
+
+ * interp.c (sim_load): Pass lma_p and sim_write args to
+ sim_load_file.
+
+Tue Oct 21 10:12:03 1997 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Correctly handle register restores for "ret" and "retf"
+ instructions.
+
+Fri Oct 3 09:28:00 1997 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Sep 24 17:38:57 1997 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Tue Sep 23 11:04:38 1997 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Mon Sep 22 11:46:20 1997 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Sep 19 17:45:25 1997 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Mon Sep 15 17:36:15 1997 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Thu Sep 4 17:21:23 1997 Doug Evans
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Aug 27 18:13:22 1997 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Tue Aug 26 10:41:07 1997 Andrew Cagney
+
+ * interp.c (sim_kill): Delete.
+ (sim_create_inferior): Add ABFD argument.
+ (sim_load): Move setting of PC from here.
+ (sim_create_inferior): To here.
+
+Mon Aug 25 17:50:22 1997 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Mon Aug 25 16:14:44 1997 Andrew Cagney
+
+ * interp.c (sim_open): Add ABFD argument.
+
+Tue Jun 24 13:46:20 1997 Jeffrey A Law (law@cygnus.com)
+
+ * interp.c (sim_resume): Clear State.exited.
+ (sim_stop_reason): If State.exited is nonzero, then indicate that
+ the simulator exited instead of stopped.
+ * mn10300_sim.h (struct _state): Add exited field.
+ * simops.c (syscall): Set State.exited for SYS_exit.
+
+Wed Jun 11 22:07:56 1997 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Fix thinko in last change.
+
+Tue Jun 10 12:31:32 1997 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: "call" stores the callee saved registers into the
+ stack! Update the stack pointer properly when done with
+ register saves.
+
+ * simops.c: Fix return address computation for "call" instructions.
+
+Thu May 22 01:43:11 1997 Jeffrey A Law (law@cygnus.com)
+
+ * interp.c (sim_open): Fix typo.
+
+Wed May 21 23:27:58 1997 Jeffrey A Law (law@cygnus.com)
+
+ * interp.c (sim_resume): Add missing case in big switch
+ statement (for extb instruction).
+
+Tue May 20 17:51:30 1997 Jeffrey A Law (law@cygnus.com)
+
+ * interp.c: Replace all references to load_mem and store_mem
+ with references to load_byte, load_half, load_3_byte, load_word
+ and store_byte, store_half, store_3_byte, store_word.
+ (INLINE): Delete definition.
+ (load_mem_big): Likewise.
+ (max_mem): Make it global.
+ (dispatch): Make this function inline.
+ (load_mem, store_mem): Delete functions.
+ * mn10300_sim.h (INLINE): Define.
+ (RLW): Delete unused definition.
+ (load_mem, store_mem): Delete declarations.
+ (load_mem_big): New definition.
+ (load_byte, load_half, load_3_byte, load_word): New functions.
+ (store_byte, store_half, store_3_byte, store_word): New functions.
+ * simops.c: Replace all references to load_mem and store_mem
+ with references to load_byte, load_half, load_3_byte, load_word
+ and store_byte, store_half, store_3_byte, store_word.
+
+Tue May 20 10:21:51 1997 Andrew Cagney
+
+ * interp.c (sim_open): Add callback to arguments.
+ (sim_set_callbacks): Delete SIM_DESC argument.
+
+Mon May 19 13:54:22 1997 Jeffrey A Law (law@cygnus.com)
+
+ * interp.c (dispatch): Make this an inline function.
+
+ * simops.c (syscall): Use callback->write regardless of
+ what file descriptor we're writing too.
+
+Sun May 18 16:46:31 1997 Jeffrey A Law (law@cygnus.com)
+
+ * interp.c (load_mem_big): Remove function. It's now a macro
+ defined elsewhere.
+ (compare_simops): New function.
+ (sim_open): Sort the Simops table before inserting entries
+ into the hash table.
+ * mn10300_sim.h: Remove unused #defines.
+ (load_mem_big): Define.
+
+Fri May 16 16:36:17 1997 Jeffrey A Law (law@cygnus.com)
+
+ * interp.c (load_mem): If we get a load from an out of range
+ address, abort.
+ (store_mem): Likewise for stores.
+ (max_mem): New variable.
+
+Tue May 6 13:24:36 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300_sim.h: Fix ordering of bits in the PSW.
+
+ * interp.c: Improve hashing routine to avoid long list
+ traversals for common instructions. Add HASH_STAT support.
+ Rewrite opcode dispatch code using a big switch instead of
+ cascaded if/else statements. Avoid useless calls to load_mem.
+
+Mon May 5 18:07:48 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300_sim.h (struct _state): Add space for mdrq register.
+ (REG_MDRQ): Define.
+ * simops.c: Don't abort for trap. Add support for the extended
+ instructions, "getx", "putx", "mulq", "mulqu", "sat16", "sat24",
+ and "bsch".
+
+Thu Apr 24 00:39:51 1997 Doug Evans
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Apr 18 14:04:04 1997 Andrew Cagney
+
+ * interp.c (sim_stop): Add stub function.
+
+Thu Apr 17 03:26:59 1997 Doug Evans
+
+ * Makefile.in (SIM_OBJS): Add sim-load.o.
+ * interp.c (sim_kind, myname): New static locals.
+ (sim_open): Set sim_kind, myname. Ignore -E arg.
+ (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
+ load file into simulator. Set start address from bfd.
+ (sim_create_inferior): Return SIM_RC. Delete arg start_address.
+
+Wed Apr 16 19:30:44 1997 Andrew Cagney
+
+ * simops.c (OP_F020): SYS_execv, SYS_time, SYS_times, SYS_utime
+ only include if implemented by host.
+ (OP_F020): Typecast arg passed to time function;
+
+Mon Apr 7 23:57:49 1997 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c (syscall): Handle new mn10300 calling conventions.
+
+Mon Apr 7 15:45:02 1997 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Fri Apr 4 20:02:37 1997 Ian Lance Taylor
+
+ * Makefile.in: Change mn10300-opc.o to m10300-opc.o, to match
+ corresponding change in opcodes directory.
+
+Wed Apr 2 15:06:28 1997 Doug Evans
+
+ * interp.c (sim_open): New arg `kind'.
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Apr 2 14:34:19 1997 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Thu Mar 20 11:58:02 1997 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Fix register extraction for a two "movbu" variants.
+ Somewhat simplify "sub" instructions.
+ Correctly sign extend operands for "mul". Put the correct
+ half of the result in MDR for "mul" and "mulu".
+ Implement remaining instructions.
+ Tweak opcode for "syscall".
+
+Tue Mar 18 14:21:21 1997 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Do syscall emulation in "syscall" instruction. Add
+ dummy "trap" instruction.
+
+Wed Mar 19 01:14:00 1997 Andrew Cagney
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Mon Mar 17 15:10:07 1997 Andrew Cagney
+
+ * configure: Re-generate.
+
+Fri Mar 14 10:34:11 1997 Michael Meissner
+
+ * configure: Regenerate to track ../common/aclocal.m4 changes.
+
+Thu Mar 13 12:54:45 1997 Doug Evans
+
+ * interp.c (sim_open): New SIM_DESC result. Argument is now
+ in argv form.
+ (other sim_*): New SIM_DESC argument.
+
+Wed Mar 12 15:04:00 1997 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Fix carry bit computation for "add" instructions.
+
+ * simops.c: Fix typos in bset insns. Fix arguments to store_mem
+ for bset imm8,(d8,an) and bclr imm8,(d8,an).
+
+Wed Mar 5 15:00:10 1997 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Fix register references when computing Z and N bits
+ for lsr imm8,dn.
+
+Tue Feb 4 13:33:30 1997 Doug Evans
+
+ * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
+ COMMON_{PRE,POST}_CONFIG_FRAG instead.
+ * configure.in: sinclude ../common/aclocal.m4.
+ * configure: Regenerated.
+
+Fri Jan 24 10:47:25 1997 Jeffrey A Law (law@cygnus.com)
+
+ * interp.c (init_system): Allocate 2^19 bytes of space for the
+ simulator.
+
+Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
+
+ * configure configure.in Makefile.in: Update to new configure
+ scheme which is more compatible with WinGDB builds.
+ * configure.in: Improve comment on how to run autoconf.
+ * configure: Re-run autoconf to get new ../common/aclocal.m4.
+ * Makefile.in: Use autoconf substitution to install common
+ makefile fragment.
+
+Tue Jan 21 15:03:04 1997 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Undo last change to "rol" and "ror", original code
+ was correct!
+
+Thu Jan 16 11:28:14 1997 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Fix "rol" and "ror".
+
+Wed Jan 15 06:45:58 1997 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Fix typo in last change.
+
+Mon Jan 13 13:22:35 1997 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Use REG macros in few places not using them yet.
+
+Mon Jan 6 16:21:19 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300_sim.h (struct _state): Fix number of registers!
+
+Tue Dec 31 16:20:41 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300_sim.h (struct _state): Put all registers into a single
+ array to make gdb implementation easier.
+ (REG_*): Add definitions for all registers in the state array.
+ (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
+ * simops.c: Related changes.
+
+Wed Dec 18 10:10:45 1996 Jeffrey A Law (law@cygnus.com)
+
+ * interp.c (sim_resume): Handle 0xff as a single byte insn.
+
+ * simops.c: Fix overflow computation for "add" and "inc"
+ instructions.
+
+Mon Dec 16 10:03:52 1996 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Handle "break" instruction.
+
+ * simops.c: Fix restoring the PC for "ret" and "retf" instructions.
+
+Wed Dec 11 09:53:10 1996 Jeffrey A Law (law@cygnus.com)
+
+ * gencode.c (write_opcodes): Also write out the format of the
+ opcode.
+ * mn10300_sim.h (simops): Add "format" field.
+ * interp.c (sim_resume): Deal with endianness issues here.
+
+Tue Dec 10 15:05:37 1996 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c (REG0_4): Define.
+ Use REG0_4 for indexed loads/stores.
+
+Sat Dec 7 09:50:28 1996 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c (REG0_16): Fix typo.
+
+Fri Dec 6 14:13:34 1996 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Call abort for any instruction that's not currently
+ simulated.
+
+ * simops.c: Define accessor macros to extract register
+ values from instructions. Use them consistently.
+
+ * interp.c: Delete unused global variable "OP".
+ (sim_resume): Remove unused variable "opcode".
+ * simops.c: Fix some uninitialized variable problems, add
+ parens to fix various -Wall warnings.
+
+ * gencode.c (write_header): Add "insn" and "extension" arguments
+ to the OP_* declarations.
+ (write_template): Similarly for function templates.
+ * interp.c (insn, extension): Remove global variables. Instead
+ pass them as arguments to the OP_* functions.
+ * mn10300_sim.h: Remove decls for "insn" and "extension".
+ * simops.c (OP_*): Accept "insn" and "extension" as arguments
+ instead of using globals.
+
+Thu Dec 5 22:26:31 1996 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
+
+ * simops.c: Fix thinkos in last change to "inc dn".
+
+Wed Dec 4 10:57:53 1996 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: "add imm,sp" does not effect the condition codes.
+ "inc dn" does effect the condition codes.
+
+Tue Dec 3 17:37:45 1996 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Treat both operands as signed values for
+ "div" instruction.
+
+ * simops.c: Fix simulation of division instructions.
+ Fix typos/thinkos in several "cmp" and "sub" instructions.
+
+Mon Dec 2 12:31:40 1996 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Fix carry bit handling in "sub" and "cmp"
+ instructions.
+
+ * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
+
+Sun Dec 1 16:05:42 1996 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Fix overflow computation for many instructions.
+
+ * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
+
+ * simops.c: Fix "mov am, dn".
+
+ * simops.c: Fix more bugs in "add imm,an" and
+ "add imm,dn".
+
+Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Fix bugs in "movm" and "add imm,an".
+
+ * simops.c: Don't lose the upper 24 bits of the return
+ pointer in "call" and "calls" instructions. Rough cut
+ at emulated system calls.
+
+ * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
+
+ * simops.c: Implement remaining 4 byte instructions.
+
+ * simops.c: Implement remaining 3 byte instructions.
+
+ * simops.c: Implement remaining 2 byte instructions. Call
+ abort for instructions we're not implementing now.
+
+Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Implement lots of random instructions.
+
+ * simops.c: Implement "movm" and "bCC" insns.
+
+ * mn10300_sim.h (_state): Add another register (MDR).
+ (REG_MDR): Define.
+ * simops.c: Implement "cmp", "calls", "rets", "jmp" and
+ a few additional random insns.
+
+ * mn10300_sim.h (PSW_*): Define for CC status tracking.
+ (REG_D0, REG_A0, REG_SP): Define.
+ * simops.c: Implement "add", "addc" and a few other random
+ instructions.
+
+ * gencode.c, interp.c: Snapshot current simulator code.
+
+Mon Nov 25 12:46:38 1996 Jeffrey A Law (law@cygnus.com)
+
+ * Makefile.in, config.in, configure, configure.in: New files.
+ * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
+
ChangeLog
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: sim-main.c
===================================================================
--- sim-main.c (nonexistent)
+++ sim-main.c (revision 842)
@@ -0,0 +1,4 @@
+#ifndef SIM_MAIN_C
+#define SIM_MAIN_C
+#include "op_utils.c"
+#endif
sim-main.c
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: mn10300_sim.h
===================================================================
--- mn10300_sim.h (nonexistent)
+++ mn10300_sim.h (revision 842)
@@ -0,0 +1,299 @@
+#include
+#include
+#include "ansidecl.h"
+#include "gdb/callback.h"
+#include "opcode/mn10300.h"
+#include
+#include "gdb/remote-sim.h"
+#include "bfd.h"
+#include "sim-fpu.h"
+
+#ifndef INLINE
+#ifdef __GNUC__
+#define INLINE inline
+#else
+#define INLINE
+#endif
+#endif
+
+extern host_callback *mn10300_callback;
+extern SIM_DESC simulator;
+
+#define DEBUG_TRACE 0x00000001
+#define DEBUG_VALUES 0x00000002
+
+extern int mn10300_debug;
+
+#if UCHAR_MAX == 255
+typedef unsigned char uint8;
+typedef signed char int8;
+#else
+#error "Char is not an 8-bit type"
+#endif
+
+#if SHRT_MAX == 32767
+typedef unsigned short uint16;
+typedef signed short int16;
+#else
+#error "Short is not a 16-bit type"
+#endif
+
+#if INT_MAX == 2147483647
+
+typedef unsigned int uint32;
+typedef signed int int32;
+
+#else
+# if LONG_MAX == 2147483647
+
+typedef unsigned long uint32;
+typedef signed long int32;
+
+# else
+# error "Neither int nor long is a 32-bit type"
+# endif
+#endif
+
+typedef struct
+{
+ uint32 low, high;
+} dword;
+typedef uint32 reg_t;
+
+struct simops
+{
+ long opcode;
+ long mask;
+ void (*func)();
+ int length;
+ int format;
+ int numops;
+ int operands[16];
+};
+
+/* The current state of the processor; registers, memory, etc. */
+
+struct _state
+{
+ reg_t regs[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
+ lir, lar, mdrq, plus some room for processor
+ specific regs. */
+ union
+ {
+ reg_t fs[32]; /* FS0-31 */
+ dword fd[16]; /* FD0,2,...,30 */
+ } fpregs;
+ uint8 *mem; /* main memory */
+ int exception;
+ int exited;
+
+ /* All internal state modified by signal_exception() that may need to be
+ rolled back for passing moment-of-exception image back to gdb. */
+ reg_t exc_trigger_regs[32];
+ reg_t exc_suspend_regs[32];
+ int exc_suspended;
+
+#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA)
+#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC)
+#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC)
+};
+
+extern struct _state State;
+extern uint32 OP[4];
+extern struct simops Simops[];
+
+#define PC (State.regs[REG_PC])
+#define SP (State.regs[REG_SP])
+
+#define PSW (State.regs[11])
+#define PSW_Z 0x1
+#define PSW_N 0x2
+#define PSW_C 0x4
+#define PSW_V 0x8
+#define PSW_IE LSBIT (11)
+#define PSW_LM LSMASK (10, 8)
+
+#define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8)
+#define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8)
+
+#define REG_D0 0
+#define REG_A0 4
+#define REG_SP 8
+#define REG_PC 9
+#define REG_MDR 10
+#define REG_PSW 11
+#define REG_LIR 12
+#define REG_LAR 13
+#define REG_MDRQ 14
+#define REG_E0 15
+#define REG_SSP 23
+#define REG_MSP 24
+#define REG_USP 25
+#define REG_MCRH 26
+#define REG_MCRL 27
+#define REG_MCVF 28
+
+#define REG_FPCR 29
+
+#define FPCR (State.regs[REG_FPCR])
+
+#define FCC_MASK LSMASK (21, 18)
+#define RM_MASK LSMASK (17, 16) /* Must always be zero. */
+#define EC_MASK LSMASK (14, 10)
+#define EE_MASK LSMASK ( 9, 5)
+#define EF_MASK LSMASK ( 4, 0)
+#define FPCR_MASK (FCC_MASK | EC_MASK | EE_MASK | EF_MASK)
+
+#define FCC_L LSBIT (21)
+#define FCC_G LSBIT (20)
+#define FCC_E LSBIT (19)
+#define FCC_U LSBIT (18)
+
+#define EC_V LSBIT (14)
+#define EC_Z LSBIT (13)
+#define EC_O LSBIT (12)
+#define EC_U LSBIT (11)
+#define EC_I LSBIT (10)
+
+#define EE_V LSBIT (9)
+#define EE_Z LSBIT (8)
+#define EE_O LSBIT (7)
+#define EE_U LSBIT (6)
+#define EE_I LSBIT (5)
+
+#define EF_V LSBIT (4)
+#define EF_Z LSBIT (3)
+#define EF_O LSBIT (2)
+#define EF_U LSBIT (1)
+#define EF_I LSBIT (0)
+
+#define PSW_FE LSBIT(20)
+#define FPU_DISABLED !(PSW & PSW_FE)
+
+#define XS2FS(X,S) State.fpregs.fs[((X<<4)|(S))]
+#define AS2FS(A,S) State.fpregs.fs[((A<<2)|(S))]
+#define Xf2FD(X,f) State.fpregs.fd[((X<<3)|(f))]
+
+#define FS2FPU(FS,F) sim_fpu_32to (&(F), (FS))
+#define FD2FPU(FD,F) sim_fpu_232to (&(F), ((FD).high), ((FD).low))
+#define FPU2FS(F,FS) sim_fpu_to32 (&(FS), &(F))
+#define FPU2FD(F,FD) sim_fpu_to232 (&((FD).high), &((FD).low), &(F))
+
+#ifdef _WIN32
+#define SIGTRAP 5
+#define SIGQUIT 3
+#endif
+
+#define FETCH32(a,b,c,d) \
+ ((a)+((b)<<8)+((c)<<16)+((d)<<24))
+
+#define FETCH24(a,b,c) \
+ ((a)+((b)<<8)+((c)<<16))
+
+#define FETCH16(a,b) ((a)+((b)<<8))
+
+#define load_byte(ADDR) \
+sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
+
+#define load_half(ADDR) \
+sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
+
+#define load_word(ADDR) \
+sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
+
+#define load_dword(ADDR) \
+u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \
+ PC, read_map, (ADDR)))
+
+static INLINE dword
+u642dw (unsigned64 dw)
+{
+ dword r;
+
+ r.low = (unsigned32)dw;
+ r.high = (unsigned32)(dw >> 32);
+ return r;
+}
+
+#define store_byte(ADDR, DATA) \
+sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
+ PC, write_map, (ADDR), (DATA))
+
+
+#define store_half(ADDR, DATA) \
+sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \
+ PC, write_map, (ADDR), (DATA))
+
+
+#define store_word(ADDR, DATA) \
+sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
+ PC, write_map, (ADDR), (DATA))
+#define store_dword(ADDR, DATA) \
+sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \
+ PC, write_map, (ADDR), dw2u64 (DATA))
+
+static INLINE unsigned64
+dw2u64 (dword data)
+{
+ return data.low | (((unsigned64)data.high) << 32);
+}
+
+/* Function declarations. */
+
+uint32 get_word (uint8 *);
+uint16 get_half (uint8 *);
+uint8 get_byte (uint8 *);
+void put_word (uint8 *, uint32);
+void put_half (uint8 *, uint16);
+void put_byte (uint8 *, uint8);
+
+extern uint8 *map (SIM_ADDR addr);
+
+INLINE_SIM_MAIN (void) genericAdd (unsigned32 source, unsigned32 destReg);
+INLINE_SIM_MAIN (void) genericSub (unsigned32 source, unsigned32 destReg);
+INLINE_SIM_MAIN (void) genericCmp (unsigned32 leftOpnd, unsigned32 rightOpnd);
+INLINE_SIM_MAIN (void) genericOr (unsigned32 source, unsigned32 destReg);
+INLINE_SIM_MAIN (void) genericXor (unsigned32 source, unsigned32 destReg);
+INLINE_SIM_MAIN (void) genericBtst (unsigned32 leftOpnd, unsigned32 rightOpnd);
+INLINE_SIM_MAIN (int) syscall_read_mem (host_callback *cb,
+ struct cb_syscall *sc,
+ unsigned long taddr,
+ char *buf,
+ int bytes);
+INLINE_SIM_MAIN (int) syscall_write_mem (host_callback *cb,
+ struct cb_syscall *sc,
+ unsigned long taddr,
+ const char *buf,
+ int bytes);
+INLINE_SIM_MAIN (void) do_syscall (void);
+void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig);
+
+void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
+void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
+void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
+
+void fpu_disabled_exception (SIM_DESC, sim_cpu *, address_word);
+void fpu_unimp_exception (SIM_DESC, sim_cpu *, address_word);
+void fpu_check_signal_exception (SIM_DESC, sim_cpu *, address_word);
+
+extern const struct fp_prec_t
+{
+ void (* reg2val) (const void *, sim_fpu *);
+ int (* round) (sim_fpu *);
+ void (* val2reg) (const sim_fpu *, void *);
+} fp_single_prec, fp_double_prec;
+
+#define FP_SINGLE (&fp_single_prec)
+#define FP_DOUBLE (&fp_double_prec)
+
+void fpu_rsqrt (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
+void fpu_sqrt (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
+void fpu_cmp (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const struct fp_prec_t *);
+void fpu_add (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_sub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_mul (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_div (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fnmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
+void fpu_fnmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
mn10300_sim.h
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tconfig.in
===================================================================
--- tconfig.in (nonexistent)
+++ tconfig.in (revision 842)
@@ -0,0 +1,26 @@
+/* mn10300 target configuration file. */
+
+/* FIXME: This is unnecessarily necessary: */
+#include "ansidecl.h"
+#include "gdb/callback.h"
+#include "gdb/remote-sim.h"
+#include "sim-module.h"
+
+MODULE_INSTALL_FN dv_sockser_install;
+#define MODULE_LIST dv_sockser_install,
+
+/* Define this if the simulator supports profiling.
+ See the mips simulator for an example.
+ This enables the `-p foo' and `-s bar' options.
+ The target is required to provide sim_set_profile{,_size}. */
+/* #define SIM_HAVE_PROFILE */
+
+/* Define this if the simulator uses an instruction cache.
+ See the h8/300 simulator for an example.
+ This enables the `-c size' option to set the size of the cache.
+ The target is required to provide sim_set_simcache_size. */
+/* #define SIM_HAVE_SIMCACHE */
+
+/* Define this if the target cpu is bi-endian
+ and the simulator supports it. */
+/* #define SIM_HAVE_BIENDIAN */
Index: dv-mn103cpu.c
===================================================================
--- dv-mn103cpu.c (nonexistent)
+++ dv-mn103cpu.c (revision 842)
@@ -0,0 +1,430 @@
+/* This file is part of the program GDB, the GNU debugger.
+
+ Copyright (C) 1998, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+ Contributed by Cygnus Solutions.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see
+
+ Specify the address of the mn10300's control register block. This
+ block contains the Interrupt Vector Registers.
+
+ The reg property value `0x20000000 0x42' locates the register block
+ at the address specified in the mn10300 user guide.
+
+
+ PORTS
+
+
+ reset (input)
+
+ Currently ignored.
+
+
+ nmi (input)
+
+ Deliver a non-maskable interrupt to the processor.
+
+
+ level (input)
+
+ Maskable interrupt level port port. The interrupt controller
+ notifies the processor of any change in the level of pending
+ requested interrupts via this port.
+
+
+ ack (output)
+
+ Output signal indicating that the processor is delivering a level
+ interrupt. The value passed with the event specifies the level of
+ the interrupt being delivered.
+
+
+ BUGS
+
+
+ When delivering an interrupt, this code assumes that there is only
+ one processor (number 0).
+
+ This code does not attempt to be efficient at handling pending
+ interrupts. It simply schedules the interrupt delivery handler
+ every instruction cycle until all pending interrupts go away. An
+ alternative implementation might modify instructions that change
+ the PSW and have them check to see if the change makes an interrupt
+ delivery possible.
+
+ */
+
+
+/* The interrupt vectors */
+
+enum { NR_VECTORS = 7, };
+
+
+/* The interrupt controller register address blocks */
+
+struct mn103cpu_block {
+ unsigned_word base;
+ unsigned_word bound;
+};
+
+
+struct mn103cpu {
+ struct mn103cpu_block block;
+ struct hw_event *pending_handler;
+ int pending_level;
+ int pending_nmi;
+ int pending_reset;
+ /* the visible registers */
+ unsigned16 interrupt_vector[NR_VECTORS];
+ unsigned16 internal_memory_control;
+ unsigned16 cpu_mode;
+};
+
+
+
+/* input port ID's */
+
+enum {
+ RESET_PORT,
+ NMI_PORT,
+ LEVEL_PORT,
+};
+
+
+/* output port ID's */
+
+enum {
+ ACK_PORT,
+};
+
+static const struct hw_port_descriptor mn103cpu_ports[] = {
+
+ /* interrupt inputs */
+ { "reset", RESET_PORT, 0, input_port, },
+ { "nmi", NMI_PORT, 0, input_port, },
+ { "level", LEVEL_PORT, 0, input_port, },
+
+ /* interrupt ack (latch) output from cpu */
+ { "ack", ACK_PORT, 0, output_port, },
+
+ { NULL, },
+};
+
+
+/* Finish off the partially created hw device. Attach our local
+ callbacks. Wire up our port names etc */
+
+static hw_io_read_buffer_method mn103cpu_io_read_buffer;
+static hw_io_write_buffer_method mn103cpu_io_write_buffer;
+static hw_port_event_method mn103cpu_port_event;
+
+static void
+attach_mn103cpu_regs (struct hw *me,
+ struct mn103cpu *controller)
+{
+ unsigned_word attach_address;
+ int attach_space;
+ unsigned attach_size;
+ reg_property_spec reg;
+ if (hw_find_property (me, "reg") == NULL)
+ hw_abort (me, "Missing \"reg\" property");
+ if (!hw_find_reg_array_property (me, "reg", 0, ®))
+ hw_abort (me, "\"reg\" property must contain three addr/size entries");
+ hw_unit_address_to_attach_address (hw_parent (me),
+ ®.address,
+ &attach_space,
+ &attach_address,
+ me);
+ controller->block.base = attach_address;
+ hw_unit_size_to_attach_size (hw_parent (me),
+ ®.size,
+ &attach_size, me);
+ controller->block.bound = attach_address + (attach_size - 1);
+ if ((controller->block.base & 3) != 0)
+ hw_abort (me, "cpu register block must be 4 byte aligned");
+ hw_attach_address (hw_parent (me),
+ 0,
+ attach_space, attach_address, attach_size,
+ me);
+}
+
+
+static void
+mn103cpu_finish (struct hw *me)
+{
+ struct mn103cpu *controller;
+
+ controller = HW_ZALLOC (me, struct mn103cpu);
+ set_hw_data (me, controller);
+ set_hw_io_read_buffer (me, mn103cpu_io_read_buffer);
+ set_hw_io_write_buffer (me, mn103cpu_io_write_buffer);
+ set_hw_ports (me, mn103cpu_ports);
+ set_hw_port_event (me, mn103cpu_port_event);
+
+ /* Attach ourself to our parent bus */
+ attach_mn103cpu_regs (me, controller);
+
+ /* Initialize the read-only registers */
+ controller->pending_level = 7; /* FIXME */
+ /* ... */
+}
+
+
+
+/* An event arrives on an interrupt port */
+
+static void
+deliver_mn103cpu_interrupt (struct hw *me,
+ void *data)
+{
+ struct mn103cpu *controller = hw_data (me);
+ SIM_DESC simulator = hw_system (me);
+ sim_cpu *cpu = STATE_CPU (simulator, 0);
+
+ if (controller->pending_reset)
+ {
+ controller->pending_reset = 0;
+ /* need to clear all registers et.al! */
+ HW_TRACE ((me, "Reset!"));
+ hw_abort (me, "Reset!");
+ }
+ else if (controller->pending_nmi)
+ {
+ controller->pending_nmi = 0;
+ store_word (SP - 4, CIA_GET (cpu));
+ store_half (SP - 8, PSW);
+ PSW &= ~PSW_IE;
+ SP = SP - 8;
+ CIA_SET (cpu, 0x40000008);
+ HW_TRACE ((me, "nmi pc=0x%08lx psw=0x%04x sp=0x%08lx",
+ (long) CIA_GET (cpu), (unsigned) PSW, (long) SP));
+ }
+ else if ((controller->pending_level < EXTRACT_PSW_LM)
+ && (PSW & PSW_IE))
+ {
+ /* Don't clear pending level. Request continues to be pending
+ until the interrupt controller clears/changes it */
+ store_word (SP - 4, CIA_GET (cpu));
+ store_half (SP - 8, PSW);
+ PSW &= ~PSW_IE;
+ PSW &= ~PSW_LM;
+ PSW |= INSERT_PSW_LM (controller->pending_level);
+ SP = SP - 8;
+ CIA_SET (cpu, 0x40000000 + controller->interrupt_vector[controller->pending_level]);
+ HW_TRACE ((me, "port-out ack %d", controller->pending_level));
+ hw_port_event (me, ACK_PORT, controller->pending_level);
+ HW_TRACE ((me, "int level=%d pc=0x%08lx psw=0x%04x sp=0x%08lx",
+ controller->pending_level,
+ (long) CIA_GET (cpu), (unsigned) PSW, (long) SP));
+ }
+
+ if (controller->pending_level < 7) /* FIXME */
+ {
+ /* As long as there is the potential need to deliver an
+ interrupt we keep rescheduling this routine. */
+ if (controller->pending_handler != NULL)
+ controller->pending_handler =
+ hw_event_queue_schedule (me, 1, deliver_mn103cpu_interrupt, NULL);
+ }
+ else
+ {
+ /* Don't bother re-scheduling the interrupt handler as there is
+ nothing to deliver */
+ controller->pending_handler = NULL;
+ }
+
+}
+
+
+static void
+mn103cpu_port_event (struct hw *me,
+ int my_port,
+ struct hw *source,
+ int source_port,
+ int level)
+{
+ struct mn103cpu *controller = hw_data (me);
+
+ /* Schedule our event handler *now* */
+ if (controller->pending_handler == NULL)
+ controller->pending_handler =
+ hw_event_queue_schedule (me, 0, deliver_mn103cpu_interrupt, NULL);
+
+ switch (my_port)
+ {
+
+ case RESET_PORT:
+ controller->pending_reset = 1;
+ HW_TRACE ((me, "port-in reset"));
+ break;
+
+ case NMI_PORT:
+ controller->pending_nmi = 1;
+ HW_TRACE ((me, "port-in nmi"));
+ break;
+
+ case LEVEL_PORT:
+ controller->pending_level = level;
+ HW_TRACE ((me, "port-in level=%d", level));
+ break;
+
+ default:
+ hw_abort (me, "bad switch");
+ break;
+
+ }
+}
+
+
+/* Read/write to a CPU register */
+
+enum mn103cpu_regs {
+ INVALID_REG,
+ IVR0_REG,
+ IVR1_REG,
+ IVR2_REG,
+ IVR3_REG,
+ IVR4_REG,
+ IVR5_REG,
+ IVR6_REG,
+ IMCR_REG,
+ CPUM_REG,
+};
+
+static enum mn103cpu_regs
+decode_mn103cpu_addr (struct hw *me,
+ struct mn103cpu *controller,
+ unsigned_word base)
+{
+ switch (base - controller->block.base)
+ {
+ case 0x000: return IVR0_REG;
+ case 0x004: return IVR1_REG;
+ case 0x008: return IVR2_REG;
+ case 0x00c: return IVR3_REG;
+ case 0x010: return IVR4_REG;
+ case 0x014: return IVR5_REG;
+ case 0x018: return IVR6_REG;
+ case 0x020: return IMCR_REG;
+ case 0x040: return CPUM_REG;
+ default: return INVALID_REG;
+ }
+}
+
+static unsigned
+mn103cpu_io_read_buffer (struct hw *me,
+ void *dest,
+ int space,
+ unsigned_word base,
+ unsigned nr_bytes)
+{
+ struct mn103cpu *controller = hw_data (me);
+ unsigned16 val = 0;
+ enum mn103cpu_regs reg = decode_mn103cpu_addr (me, controller, base);
+
+ switch (reg)
+ {
+ case IVR0_REG:
+ case IVR1_REG:
+ case IVR2_REG:
+ case IVR3_REG:
+ case IVR4_REG:
+ case IVR5_REG:
+ case IVR6_REG:
+ val = controller->interrupt_vector[reg - IVR0_REG];
+ break;
+ case IMCR_REG:
+ val = controller->internal_memory_control;
+ break;
+ case CPUM_REG:
+ val = controller->cpu_mode;
+ break;
+ default:
+ /* just ignore the read */
+ break;
+ }
+
+ if (nr_bytes == 2)
+ *(unsigned16*) dest = H2LE_2 (val);
+
+ return nr_bytes;
+}
+
+static unsigned
+mn103cpu_io_write_buffer (struct hw *me,
+ const void *source,
+ int space,
+ unsigned_word base,
+ unsigned nr_bytes)
+{
+ struct mn103cpu *controller = hw_data (me);
+ unsigned16 val;
+ enum mn103cpu_regs reg;
+
+ if (nr_bytes != 2)
+ hw_abort (me, "must be two byte write");
+
+ reg = decode_mn103cpu_addr (me, controller, base);
+ val = LE2H_2 (* (unsigned16 *) source);
+
+ switch (reg)
+ {
+ case IVR0_REG:
+ case IVR1_REG:
+ case IVR2_REG:
+ case IVR3_REG:
+ case IVR4_REG:
+ case IVR5_REG:
+ case IVR6_REG:
+ controller->interrupt_vector[reg - IVR0_REG] = val;
+ HW_TRACE ((me, "ivr%d = 0x%04lx", reg - IVR0_REG, (long) val));
+ break;
+ default:
+ /* just ignore the write */
+ break;
+ }
+
+ return nr_bytes;
+}
+
+
+const struct hw_descriptor dv_mn103cpu_descriptor[] = {
+ { "mn103cpu", mn103cpu_finish, },
+ { NULL },
+};
dv-mn103cpu.c
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: dv-mn103iop.c
===================================================================
--- dv-mn103iop.c (nonexistent)
+++ dv-mn103iop.c (revision 842)
@@ -0,0 +1,554 @@
+/* This file is part of the program GDB, the GNU debugger.
+
+ Copyright (C) 1998, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+ Contributed by Cygnus Solutions.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see ...
+
+
+ BUGS
+
+ */
+
+
+/* The I/O ports' registers' address block */
+
+struct mn103iop_block {
+ unsigned_word base;
+ unsigned_word bound;
+};
+
+
+
+enum io_port_register_types {
+ P0OUT,
+ P1OUT,
+ P2OUT,
+ P3OUT,
+ P0MD,
+ P1MD,
+ P2MD,
+ P3MD,
+ P2SS,
+ P4SS,
+ P0DIR,
+ P1DIR,
+ P2DIR,
+ P3DIR,
+ P0IN,
+ P1IN,
+ P2IN,
+ P3IN,
+};
+
+#define NR_PORTS 4
+
+enum {
+ OUTPUT_BLOCK,
+ MODE_BLOCK,
+ DED_CTRL_BLOCK,
+ CTRL_BLOCK,
+ PIN_BLOCK,
+ NR_BLOCKS
+};
+
+typedef struct _mn10300_ioport {
+ unsigned8 output, output_mode, control, pin;
+ struct hw_event *event;
+} mn10300_ioport;
+
+
+
+struct mn103iop {
+ struct mn103iop_block block[NR_BLOCKS];
+ mn10300_ioport port[NR_PORTS];
+ unsigned8 p2ss, p4ss;
+};
+
+
+/* Finish off the partially created hw device. Attach our local
+ callbacks. Wire up our port names etc */
+
+static hw_io_read_buffer_method mn103iop_io_read_buffer;
+static hw_io_write_buffer_method mn103iop_io_write_buffer;
+
+static void
+attach_mn103iop_regs (struct hw *me,
+ struct mn103iop *io_port)
+{
+ int i;
+ unsigned_word attach_address;
+ int attach_space;
+ unsigned attach_size;
+ reg_property_spec reg;
+
+ if (hw_find_property (me, "reg") == NULL)
+ hw_abort (me, "Missing \"reg\" property");
+
+ for (i=0; i < NR_BLOCKS; ++i )
+ {
+ if (!hw_find_reg_array_property (me, "reg", i, ®))
+ hw_abort (me, "\"reg\" property must contain five addr/size entries");
+ hw_unit_address_to_attach_address (hw_parent (me),
+ ®.address,
+ &attach_space,
+ &attach_address,
+ me);
+ io_port->block[i].base = attach_address;
+ hw_unit_size_to_attach_size (hw_parent (me),
+ ®.size,
+ &attach_size, me);
+ io_port->block[i].bound = attach_address + (attach_size - 1);
+ hw_attach_address (hw_parent (me),
+ 0,
+ attach_space, attach_address, attach_size,
+ me);
+ }
+}
+
+static void
+mn103iop_finish (struct hw *me)
+{
+ struct mn103iop *io_port;
+ int i;
+
+ io_port = HW_ZALLOC (me, struct mn103iop);
+ set_hw_data (me, io_port);
+ set_hw_io_read_buffer (me, mn103iop_io_read_buffer);
+ set_hw_io_write_buffer (me, mn103iop_io_write_buffer);
+
+ /* Attach ourself to our parent bus */
+ attach_mn103iop_regs (me, io_port);
+
+ /* Initialize the i/o port registers. */
+ for ( i=0; iport[i].output = 0;
+ io_port->port[i].output_mode = 0;
+ io_port->port[i].control = 0;
+ io_port->port[i].pin = 0;
+ }
+ io_port->port[2].output_mode = 0xff;
+ io_port->p2ss = 0;
+ io_port->p4ss = 0x0f;
+}
+
+
+/* read and write */
+
+static int
+decode_addr (struct hw *me,
+ struct mn103iop *io_port,
+ unsigned_word address)
+{
+ unsigned_word offset;
+ offset = address - io_port->block[0].base;
+ switch (offset)
+ {
+ case 0x00: return P0OUT;
+ case 0x01: return P1OUT;
+ case 0x04: return P2OUT;
+ case 0x05: return P3OUT;
+ case 0x20: return P0MD;
+ case 0x21: return P1MD;
+ case 0x24: return P2MD;
+ case 0x25: return P3MD;
+ case 0x44: return P2SS;
+ case 0x48: return P4SS;
+ case 0x60: return P0DIR;
+ case 0x61: return P1DIR;
+ case 0x64: return P2DIR;
+ case 0x65: return P3DIR;
+ case 0x80: return P0IN;
+ case 0x81: return P1IN;
+ case 0x84: return P2IN;
+ case 0x85: return P3IN;
+ default:
+ {
+ hw_abort (me, "bad address");
+ return -1;
+ }
+ }
+}
+
+
+static void
+read_output_reg (struct hw *me,
+ struct mn103iop *io_port,
+ unsigned_word io_port_reg,
+ const void *dest,
+ unsigned nr_bytes)
+{
+ if ( nr_bytes == 1 )
+ {
+ *(unsigned8 *)dest = io_port->port[io_port_reg].output;
+ }
+ else
+ {
+ hw_abort (me, "bad read size of %d bytes from P%dOUT.", nr_bytes,
+ io_port_reg);
+ }
+}
+
+
+static void
+read_output_mode_reg (struct hw *me,
+ struct mn103iop *io_port,
+ unsigned_word io_port_reg,
+ const void *dest,
+ unsigned nr_bytes)
+{
+ if ( nr_bytes == 1 )
+ {
+ /* check if there are fields which can't be written and
+ take appropriate action depending what bits are set */
+ *(unsigned8 *)dest = io_port->port[io_port_reg].output_mode;
+ }
+ else
+ {
+ hw_abort (me, "bad read size of %d bytes to P%dMD.", nr_bytes,
+ io_port_reg);
+ }
+}
+
+
+static void
+read_control_reg (struct hw *me,
+ struct mn103iop *io_port,
+ unsigned_word io_port_reg,
+ const void *dest,
+ unsigned nr_bytes)
+{
+ if ( nr_bytes == 1 )
+ {
+ *(unsigned8 *)dest = io_port->port[io_port_reg].control;
+ }
+ else
+ {
+ hw_abort (me, "bad read size of %d bytes to P%dDIR.", nr_bytes,
+ io_port_reg);
+ }
+}
+
+
+static void
+read_pin_reg (struct hw *me,
+ struct mn103iop *io_port,
+ unsigned_word io_port_reg,
+ const void *dest,
+ unsigned nr_bytes)
+{
+ if ( nr_bytes == 1 )
+ {
+ *(unsigned8 *)dest = io_port->port[io_port_reg].pin;
+ }
+ else
+ {
+ hw_abort (me, "bad read size of %d bytes to P%dIN.", nr_bytes,
+ io_port_reg);
+ }
+}
+
+
+static void
+read_dedicated_control_reg (struct hw *me,
+ struct mn103iop *io_port,
+ unsigned_word io_port_reg,
+ const void *dest,
+ unsigned nr_bytes)
+{
+ if ( nr_bytes == 1 )
+ {
+ /* select on io_port_reg: */
+ if ( io_port_reg == P2SS )
+ {
+ *(unsigned8 *)dest = io_port->p2ss;
+ }
+ else
+ {
+ *(unsigned8 *)dest = io_port->p4ss;
+ }
+ }
+ else
+ {
+ hw_abort (me, "bad read size of %d bytes to PSS.", nr_bytes);
+ }
+}
+
+
+static unsigned
+mn103iop_io_read_buffer (struct hw *me,
+ void *dest,
+ int space,
+ unsigned_word base,
+ unsigned nr_bytes)
+{
+ struct mn103iop *io_port = hw_data (me);
+ enum io_port_register_types io_port_reg;
+ HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
+
+ io_port_reg = decode_addr (me, io_port, base);
+ switch (io_port_reg)
+ {
+ /* Port output registers */
+ case P0OUT:
+ case P1OUT:
+ case P2OUT:
+ case P3OUT:
+ read_output_reg(me, io_port, io_port_reg-P0OUT, dest, nr_bytes);
+ break;
+
+ /* Port output mode registers */
+ case P0MD:
+ case P1MD:
+ case P2MD:
+ case P3MD:
+ read_output_mode_reg(me, io_port, io_port_reg-P0MD, dest, nr_bytes);
+ break;
+
+ /* Port control registers */
+ case P0DIR:
+ case P1DIR:
+ case P2DIR:
+ case P3DIR:
+ read_control_reg(me, io_port, io_port_reg-P0DIR, dest, nr_bytes);
+ break;
+
+ /* Port pin registers */
+ case P0IN:
+ case P1IN:
+ case P2IN:
+ read_pin_reg(me, io_port, io_port_reg-P0IN, dest, nr_bytes);
+ break;
+
+ case P2SS:
+ case P4SS:
+ read_dedicated_control_reg(me, io_port, io_port_reg, dest, nr_bytes);
+ break;
+
+ default:
+ hw_abort(me, "invalid address");
+ }
+
+ return nr_bytes;
+}
+
+
+static void
+write_output_reg (struct hw *me,
+ struct mn103iop *io_port,
+ unsigned_word io_port_reg,
+ const void *source,
+ unsigned nr_bytes)
+{
+ unsigned8 buf = *(unsigned8 *)source;
+ if ( nr_bytes == 1 )
+ {
+ if ( io_port_reg == 3 && (buf & 0xfc) != 0 )
+ {
+ hw_abort(me, "Cannot write to read-only bits of P3OUT.");
+ }
+ else
+ {
+ io_port->port[io_port_reg].output = buf;
+ }
+ }
+ else
+ {
+ hw_abort (me, "bad read size of %d bytes from P%dOUT.", nr_bytes,
+ io_port_reg);
+ }
+}
+
+
+static void
+write_output_mode_reg (struct hw *me,
+ struct mn103iop *io_port,
+ unsigned_word io_port_reg,
+ const void *source,
+ unsigned nr_bytes)
+{
+ unsigned8 buf = *(unsigned8 *)source;
+ if ( nr_bytes == 1 )
+ {
+ /* check if there are fields which can't be written and
+ take appropriate action depending what bits are set */
+ if ( ( io_port_reg == 3 && (buf & 0xfc) != 0 )
+ || ( (io_port_reg == 0 || io_port_reg == 1) && (buf & 0xfe) != 0 ) )
+ {
+ hw_abort(me, "Cannot write to read-only bits of output mode register.");
+ }
+ else
+ {
+ io_port->port[io_port_reg].output_mode = buf;
+ }
+ }
+ else
+ {
+ hw_abort (me, "bad write size of %d bytes to P%dMD.", nr_bytes,
+ io_port_reg);
+ }
+}
+
+
+static void
+write_control_reg (struct hw *me,
+ struct mn103iop *io_port,
+ unsigned_word io_port_reg,
+ const void *source,
+ unsigned nr_bytes)
+{
+ unsigned8 buf = *(unsigned8 *)source;
+ if ( nr_bytes == 1 )
+ {
+ if ( io_port_reg == 3 && (buf & 0xfc) != 0 )
+ {
+ hw_abort(me, "Cannot write to read-only bits of P3DIR.");
+ }
+ else
+ {
+ io_port->port[io_port_reg].control = buf;
+ }
+ }
+ else
+ {
+ hw_abort (me, "bad write size of %d bytes to P%dDIR.", nr_bytes,
+ io_port_reg);
+ }
+}
+
+
+static void
+write_dedicated_control_reg (struct hw *me,
+ struct mn103iop *io_port,
+ unsigned_word io_port_reg,
+ const void *source,
+ unsigned nr_bytes)
+{
+ unsigned8 buf = *(unsigned8 *)source;
+ if ( nr_bytes == 1 )
+ {
+ /* select on io_port_reg: */
+ if ( io_port_reg == P2SS )
+ {
+ if ( (buf && 0xfc) != 0 )
+ {
+ hw_abort(me, "Cannot write to read-only bits in p2ss.");
+ }
+ else
+ {
+ io_port->p2ss = buf;
+ }
+ }
+ else
+ {
+ if ( (buf && 0xf0) != 0 )
+ {
+ hw_abort(me, "Cannot write to read-only bits in p4ss.");
+ }
+ else
+ {
+ io_port->p4ss = buf;
+ }
+ }
+ }
+ else
+ {
+ hw_abort (me, "bad write size of %d bytes to PSS.", nr_bytes);
+ }
+}
+
+
+static unsigned
+mn103iop_io_write_buffer (struct hw *me,
+ const void *source,
+ int space,
+ unsigned_word base,
+ unsigned nr_bytes)
+{
+ struct mn103iop *io_port = hw_data (me);
+ enum io_port_register_types io_port_reg;
+ HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
+
+ io_port_reg = decode_addr (me, io_port, base);
+ switch (io_port_reg)
+ {
+ /* Port output registers */
+ case P0OUT:
+ case P1OUT:
+ case P2OUT:
+ case P3OUT:
+ write_output_reg(me, io_port, io_port_reg-P0OUT, source, nr_bytes);
+ break;
+
+ /* Port output mode registers */
+ case P0MD:
+ case P1MD:
+ case P2MD:
+ case P3MD:
+ write_output_mode_reg(me, io_port, io_port_reg-P0MD, source, nr_bytes);
+ break;
+
+ /* Port control registers */
+ case P0DIR:
+ case P1DIR:
+ case P2DIR:
+ case P3DIR:
+ write_control_reg(me, io_port, io_port_reg-P0DIR, source, nr_bytes);
+ break;
+
+ /* Port pin registers */
+ case P0IN:
+ case P1IN:
+ case P2IN:
+ hw_abort(me, "Cannot write to pin register.");
+ break;
+
+ case P2SS:
+ case P4SS:
+ write_dedicated_control_reg(me, io_port, io_port_reg, source, nr_bytes);
+ break;
+
+ default:
+ hw_abort(me, "invalid address");
+ }
+
+ return nr_bytes;
+}
+
+
+const struct hw_descriptor dv_mn103iop_descriptor[] = {
+ { "mn103iop", mn103iop_finish, },
+ { NULL },
+};
dv-mn103iop.c
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: dv-mn103ser.c
===================================================================
--- dv-mn103ser.c (nonexistent)
+++ dv-mn103ser.c (revision 842)
@@ -0,0 +1,711 @@
+/* This file is part of the program GDB, the GNU debugger.
+
+ Copyright (C) 1998, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+ Contributed by Cygnus Solutions.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see
+
+
+ BUGS
+
+ */
+
+
+/* The serial devices' registers' address block */
+
+struct mn103ser_block {
+ unsigned_word base;
+ unsigned_word bound;
+};
+
+
+
+enum serial_register_types {
+ SC0CTR,
+ SC1CTR,
+ SC2CTR,
+ SC0ICR,
+ SC1ICR,
+ SC2ICR,
+ SC0TXB,
+ SC1TXB,
+ SC2TXB,
+ SC0RXB,
+ SC1RXB,
+ SC2RXB,
+ SC0STR,
+ SC1STR,
+ SC2STR,
+ SC2TIM,
+};
+
+
+/* Access dv-sockser state */
+extern char* sockser_addr;
+#define USE_SOCKSER_P (sockser_addr != NULL)
+
+
+#define NR_SERIAL_DEVS 3
+#define SIO_STAT_RRDY 0x0010
+
+typedef struct _mn10300_serial {
+ unsigned16 status, control;
+ unsigned8 txb, rxb, intmode;
+ struct hw_event *event;
+} mn10300_serial;
+
+
+
+struct mn103ser {
+ struct mn103ser_block block;
+ mn10300_serial device[NR_SERIAL_DEVS];
+ unsigned8 serial2_timer_reg;
+ do_hw_poll_read_method *reader;
+};
+
+/* output port ID's */
+
+/* for mn103002 */
+enum {
+ SERIAL0_RECEIVE,
+ SERIAL1_RECEIVE,
+ SERIAL2_RECEIVE,
+ SERIAL0_SEND,
+ SERIAL1_SEND,
+ SERIAL2_SEND,
+};
+
+
+static const struct hw_port_descriptor mn103ser_ports[] = {
+
+ { "serial-0-receive", SERIAL0_RECEIVE, 0, output_port, },
+ { "serial-1-receive", SERIAL1_RECEIVE, 0, output_port, },
+ { "serial-2-receive", SERIAL2_RECEIVE, 0, output_port, },
+ { "serial-0-transmit", SERIAL0_SEND, 0, output_port, },
+ { "serial-1-transmit", SERIAL1_SEND, 0, output_port, },
+ { "serial-2-transmit", SERIAL2_SEND, 0, output_port, },
+
+ { NULL, },
+};
+
+
+
+/* Finish off the partially created hw device. Attach our local
+ callbacks. Wire up our port names etc */
+
+static hw_io_read_buffer_method mn103ser_io_read_buffer;
+static hw_io_write_buffer_method mn103ser_io_write_buffer;
+
+static void
+attach_mn103ser_regs (struct hw *me,
+ struct mn103ser *serial)
+{
+ unsigned_word attach_address;
+ int attach_space;
+ unsigned attach_size;
+ reg_property_spec reg;
+
+ if (hw_find_property (me, "reg") == NULL)
+ hw_abort (me, "Missing \"reg\" property");
+
+ if (!hw_find_reg_array_property (me, "reg", 0, ®))
+ hw_abort (me, "\"reg\" property must contain three addr/size entries");
+ hw_unit_address_to_attach_address (hw_parent (me),
+ ®.address,
+ &attach_space,
+ &attach_address,
+ me);
+ serial->block.base = attach_address;
+ hw_unit_size_to_attach_size (hw_parent (me),
+ ®.size,
+ &attach_size, me);
+ serial->block.bound = attach_address + (attach_size - 1);
+ hw_attach_address (hw_parent (me),
+ 0,
+ attach_space, attach_address, attach_size,
+ me);
+}
+
+static void
+mn103ser_finish (struct hw *me)
+{
+ struct mn103ser *serial;
+ int i;
+
+ serial = HW_ZALLOC (me, struct mn103ser);
+ set_hw_data (me, serial);
+ set_hw_io_read_buffer (me, mn103ser_io_read_buffer);
+ set_hw_io_write_buffer (me, mn103ser_io_write_buffer);
+ set_hw_ports (me, mn103ser_ports);
+
+ /* Attach ourself to our parent bus */
+ attach_mn103ser_regs (me, serial);
+
+ /* If so configured, enable polled input */
+ if (hw_find_property (me, "poll?") != NULL
+ && hw_find_boolean_property (me, "poll?"))
+ {
+ serial->reader = sim_io_poll_read;
+ }
+ else
+ {
+ serial->reader = sim_io_read;
+ }
+
+ /* Initialize the serial device registers. */
+ for ( i=0; idevice[i].txb = 0;
+ serial->device[i].rxb = 0;
+ serial->device[i].status = 0;
+ serial->device[i].control = 0;
+ serial->device[i].intmode = 0;
+ serial->device[i].event = NULL;
+ }
+}
+
+
+/* read and write */
+
+static int
+decode_addr (struct hw *me,
+ struct mn103ser *serial,
+ unsigned_word address)
+{
+ unsigned_word offset;
+ offset = address - serial->block.base;
+ switch (offset)
+ {
+ case 0x00: return SC0CTR;
+ case 0x04: return SC0ICR;
+ case 0x08: return SC0TXB;
+ case 0x09: return SC0RXB;
+ case 0x0C: return SC0STR;
+ case 0x10: return SC1CTR;
+ case 0x14: return SC1ICR;
+ case 0x18: return SC1TXB;
+ case 0x19: return SC1RXB;
+ case 0x1C: return SC1STR;
+ case 0x20: return SC2CTR;
+ case 0x24: return SC2ICR;
+ case 0x28: return SC2TXB;
+ case 0x29: return SC2RXB;
+ case 0x2C: return SC2STR;
+ case 0x2D: return SC2TIM;
+ default:
+ {
+ hw_abort (me, "bad address");
+ return -1;
+ }
+ }
+}
+
+static void
+do_polling_event (struct hw *me,
+ void *data)
+{
+ struct mn103ser *serial = hw_data(me);
+ long serial_reg = (long) data;
+ char c;
+ int count;
+
+ if(USE_SOCKSER_P)
+ {
+ int rd;
+ rd = dv_sockser_read (hw_system (me));
+ if(rd != -1)
+ {
+ c = (char) rd;
+ count = 1;
+ }
+ else
+ {
+ count = HW_IO_NOT_READY;
+ }
+ }
+ else
+ {
+ count = do_hw_poll_read (me, serial->reader,
+ 0/*STDIN*/, &c, sizeof(c));
+ }
+
+
+ switch (count)
+ {
+ case HW_IO_NOT_READY:
+ case HW_IO_EOF:
+ serial->device[serial_reg].rxb = 0;
+ serial->device[serial_reg].status &= ~SIO_STAT_RRDY;
+ break;
+ default:
+ serial->device[serial_reg].rxb = c;
+ serial->device[serial_reg].status |= SIO_STAT_RRDY;
+ hw_port_event (me, serial_reg+SERIAL0_RECEIVE, 1);
+ }
+
+ /* Schedule next polling event */
+ serial->device[serial_reg].event
+ = hw_event_queue_schedule (me, 1000,
+ do_polling_event, (void *)serial_reg);
+
+}
+
+static void
+read_control_reg (struct hw *me,
+ struct mn103ser *serial,
+ unsigned_word serial_reg,
+ void *dest,
+ unsigned nr_bytes)
+{
+ /* really allow 1 byte read, too */
+ if ( nr_bytes == 2 )
+ {
+ *(unsigned16 *)dest = H2LE_2 (serial->device[serial_reg].control);
+ }
+ else
+ {
+ hw_abort (me, "bad read size of %d bytes from SC%dCTR.", nr_bytes,
+ serial_reg);
+ }
+}
+
+
+static void
+read_intmode_reg (struct hw *me,
+ struct mn103ser *serial,
+ unsigned_word serial_reg,
+ void *dest,
+ unsigned nr_bytes)
+{
+ if ( nr_bytes == 1 )
+ {
+ *(unsigned8 *)dest = serial->device[serial_reg].intmode;
+ }
+ else
+ {
+ hw_abort (me, "bad read size of %d bytes from SC%dICR.", nr_bytes,
+ serial_reg);
+ }
+}
+
+
+static void
+read_txb (struct hw *me,
+ struct mn103ser *serial,
+ unsigned_word serial_reg,
+ void *dest,
+ unsigned nr_bytes)
+{
+ if ( nr_bytes == 1 )
+ {
+ *(unsigned8 *)dest = serial->device[serial_reg].txb;
+ }
+ else
+ {
+ hw_abort (me, "bad read size of %d bytes from SC%dTXB.", nr_bytes,
+ serial_reg);
+ }
+}
+
+
+static void
+read_rxb (struct hw *me,
+ struct mn103ser *serial,
+ unsigned_word serial_reg,
+ void *dest,
+ unsigned nr_bytes)
+{
+ if ( nr_bytes == 1 )
+ {
+ *(unsigned8 *)dest = serial->device[serial_reg].rxb;
+ /* Reception buffer is now empty. */
+ serial->device[serial_reg].status &= ~SIO_STAT_RRDY;
+ }
+ else
+ {
+ hw_abort (me, "bad read size of %d bytes from SC%dRXB.", nr_bytes,
+ serial_reg);
+ }
+}
+
+
+static void
+read_status_reg (struct hw *me,
+ struct mn103ser *serial,
+ unsigned_word serial_reg,
+ void *dest,
+ unsigned nr_bytes)
+{
+ char c;
+ int count;
+
+ if ( (serial->device[serial_reg].status & SIO_STAT_RRDY) == 0 )
+ {
+ /* FIFO is empty */
+ /* Kill current poll event */
+ if ( NULL != serial->device[serial_reg].event )
+ {
+ hw_event_queue_deschedule (me, serial->device[serial_reg].event);
+ serial->device[serial_reg].event = NULL;
+ }
+
+ if(USE_SOCKSER_P)
+ {
+ int rd;
+ rd = dv_sockser_read (hw_system (me));
+ if(rd != -1)
+ {
+ c = (char) rd;
+ count = 1;
+ }
+ else
+ {
+ count = HW_IO_NOT_READY;
+ }
+ }
+ else
+ {
+ count = do_hw_poll_read (me, serial->reader,
+ 0/*STDIN*/, &c, sizeof(c));
+ }
+
+ switch (count)
+ {
+ case HW_IO_NOT_READY:
+ case HW_IO_EOF:
+ serial->device[serial_reg].rxb = 0;
+ serial->device[serial_reg].status &= ~SIO_STAT_RRDY;
+ break;
+ default:
+ serial->device[serial_reg].rxb = c;
+ serial->device[serial_reg].status |= SIO_STAT_RRDY;
+ hw_port_event (me, serial_reg+SERIAL0_RECEIVE, 1);
+ }
+
+ /* schedule polling event */
+ serial->device[serial_reg].event
+ = hw_event_queue_schedule (me, 1000,
+ do_polling_event,
+ (void *) (long) serial_reg);
+ }
+
+ if ( nr_bytes == 1 )
+ {
+ *(unsigned8 *)dest = (unsigned8)serial->device[serial_reg].status;
+ }
+ else if ( nr_bytes == 2 && serial_reg != SC2STR )
+ {
+ *(unsigned16 *)dest = H2LE_2 (serial->device[serial_reg].status);
+ }
+ else
+ {
+ hw_abort (me, "bad read size of %d bytes from SC%dSTR.", nr_bytes,
+ serial_reg);
+ }
+}
+
+
+static void
+read_serial2_timer_reg (struct hw *me,
+ struct mn103ser *serial,
+ void *dest,
+ unsigned nr_bytes)
+{
+ if ( nr_bytes == 1 )
+ {
+ * (unsigned8 *) dest = (unsigned8) serial->serial2_timer_reg;
+ }
+ else
+ {
+ hw_abort (me, "bad read size of %d bytes to SC2TIM.", nr_bytes);
+ }
+}
+
+
+static unsigned
+mn103ser_io_read_buffer (struct hw *me,
+ void *dest,
+ int space,
+ unsigned_word base,
+ unsigned nr_bytes)
+{
+ struct mn103ser *serial = hw_data (me);
+ enum serial_register_types serial_reg;
+ HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
+
+ serial_reg = decode_addr (me, serial, base);
+ switch (serial_reg)
+ {
+ /* control registers */
+ case SC0CTR:
+ case SC1CTR:
+ case SC2CTR:
+ read_control_reg(me, serial, serial_reg-SC0CTR, dest, nr_bytes);
+ HW_TRACE ((me, "read - ctrl reg%d has 0x%x\n", serial_reg-SC0CTR,
+ *(unsigned8 *)dest));
+ break;
+
+ /* interrupt mode registers */
+ case SC0ICR:
+ case SC1ICR:
+ case SC2ICR:
+ read_intmode_reg(me, serial, serial_reg-SC0ICR, dest, nr_bytes);
+ HW_TRACE ((me, "read - intmode reg%d has 0x%x\n", serial_reg-SC0ICR,
+ *(unsigned8 *)dest));
+ break;
+
+ /* transmission buffers */
+ case SC0TXB:
+ case SC1TXB:
+ case SC2TXB:
+ read_txb(me, serial, serial_reg-SC0TXB, dest, nr_bytes);
+ HW_TRACE ((me, "read - txb%d has %c\n", serial_reg-SC0TXB,
+ *(char *)dest));
+ break;
+
+ /* reception buffers */
+ case SC0RXB:
+ case SC1RXB:
+ case SC2RXB:
+ read_rxb(me, serial, serial_reg-SC0RXB, dest, nr_bytes);
+ HW_TRACE ((me, "read - rxb%d has %c\n", serial_reg-SC0RXB,
+ *(char *)dest));
+ break;
+
+ /* status registers */
+ case SC0STR:
+ case SC1STR:
+ case SC2STR:
+ read_status_reg(me, serial, serial_reg-SC0STR, dest, nr_bytes);
+ HW_TRACE ((me, "read - status reg%d has 0x%x\n", serial_reg-SC0STR,
+ *(unsigned8 *)dest));
+ break;
+
+ case SC2TIM:
+ read_serial2_timer_reg(me, serial, dest, nr_bytes);
+ HW_TRACE ((me, "read - serial2 timer reg %d\n", *(unsigned8 *)dest));
+ break;
+
+ default:
+ hw_abort(me, "invalid address");
+ }
+
+ return nr_bytes;
+}
+
+
+static void
+write_control_reg (struct hw *me,
+ struct mn103ser *serial,
+ unsigned_word serial_reg,
+ const void *source,
+ unsigned nr_bytes)
+{
+ unsigned16 val = LE2H_2 (*(unsigned16 *)source);
+
+ /* really allow 1 byte write, too */
+ if ( nr_bytes == 2 )
+ {
+ if ( serial_reg == 2 && (val & 0x0C04) != 0 )
+ {
+ hw_abort(me, "Cannot write to read-only bits of SC2CTR.");
+ }
+ else
+ {
+ serial->device[serial_reg].control = val;
+ }
+ }
+ else
+ {
+ hw_abort (me, "bad read size of %d bytes from SC%dSTR.", nr_bytes,
+ serial_reg);
+ }
+}
+
+
+static void
+write_intmode_reg (struct hw *me,
+ struct mn103ser *serial,
+ unsigned_word serial_reg,
+ const void *source,
+ unsigned nr_bytes)
+{
+unsigned8 val = *(unsigned8 *)source;
+
+ if ( nr_bytes == 1 )
+ {
+ /* Check for attempt to write to read-only bits of register. */
+ if ( ( serial_reg == 2 && (val & 0xCA) != 0 )
+ || ( serial_reg != 2 && (val & 0x4A) != 0 ) )
+ {
+ hw_abort(me, "Cannot write to read-only bits of SC%dICR.",
+ serial_reg);
+ }
+ else
+ {
+ serial->device[serial_reg].intmode = val;
+ }
+ }
+ else
+ {
+ hw_abort (me, "bad write size of %d bytes to SC%dICR.", nr_bytes,
+ serial_reg);
+ }
+}
+
+
+static void
+write_txb (struct hw *me,
+ struct mn103ser *serial,
+ unsigned_word serial_reg,
+ const void *source,
+ unsigned nr_bytes)
+{
+ if ( nr_bytes == 1 )
+ {
+ serial->device[serial_reg].txb = *(unsigned8 *)source;
+
+ if(USE_SOCKSER_P)
+ {
+ dv_sockser_write(hw_system (me), * (char*) source);
+ }
+ else
+ {
+ sim_io_write_stdout(hw_system (me), (char *)source, 1);
+ sim_io_flush_stdout(hw_system (me));
+ }
+
+ hw_port_event (me, serial_reg+SERIAL0_SEND, 1);
+ }
+ else
+ {
+ hw_abort (me, "bad write size of %d bytes to SC%dTXB.", nr_bytes,
+ serial_reg);
+ }
+}
+
+
+static void
+write_serial2_timer_reg (struct hw *me,
+ struct mn103ser *serial,
+ const void *source,
+ unsigned nr_bytes)
+{
+ if ( nr_bytes == 1 )
+ {
+ serial->serial2_timer_reg = *(unsigned8 *)source;
+ }
+ else
+ {
+ hw_abort (me, "bad write size of %d bytes to SC2TIM.", nr_bytes);
+ }
+}
+
+
+static unsigned
+mn103ser_io_write_buffer (struct hw *me,
+ const void *source,
+ int space,
+ unsigned_word base,
+ unsigned nr_bytes)
+{
+ struct mn103ser *serial = hw_data (me);
+ enum serial_register_types serial_reg;
+ HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
+
+ serial_reg = decode_addr (me, serial, base);
+ switch (serial_reg)
+ {
+ /* control registers */
+ case SC0CTR:
+ case SC1CTR:
+ case SC2CTR:
+ HW_TRACE ((me, "write - ctrl reg%d has 0x%x, nrbytes=%d.\n",
+ serial_reg-SC0CTR, *(unsigned8 *)source, nr_bytes));
+ write_control_reg(me, serial, serial_reg-SC0CTR, source, nr_bytes);
+ break;
+
+ /* interrupt mode registers */
+ case SC0ICR:
+ case SC1ICR:
+ case SC2ICR:
+ HW_TRACE ((me, "write - intmode reg%d has 0x%x, nrbytes=%d.\n",
+ serial_reg-SC0ICR, *(unsigned8 *)source, nr_bytes));
+ write_intmode_reg(me, serial, serial_reg-SC0ICR, source, nr_bytes);
+ break;
+
+ /* transmission buffers */
+ case SC0TXB:
+ case SC1TXB:
+ case SC2TXB:
+ HW_TRACE ((me, "write - txb%d has %c, nrbytes=%d.\n",
+ serial_reg-SC0TXB, *(char *)source, nr_bytes));
+ write_txb(me, serial, serial_reg-SC0TXB, source, nr_bytes);
+ break;
+
+ /* reception buffers */
+ case SC0RXB:
+ case SC1RXB:
+ case SC2RXB:
+ hw_abort(me, "Cannot write to reception buffer.");
+ break;
+
+ /* status registers */
+ case SC0STR:
+ case SC1STR:
+ case SC2STR:
+ hw_abort(me, "Cannot write to status register.");
+ break;
+
+ case SC2TIM:
+ HW_TRACE ((me, "read - serial2 timer reg %d (nrbytes=%d)\n",
+ *(unsigned8 *)source, nr_bytes));
+ write_serial2_timer_reg(me, serial, source, nr_bytes);
+ break;
+
+ default:
+ hw_abort(me, "invalid address");
+ }
+
+ return nr_bytes;
+}
+
+
+const struct hw_descriptor dv_mn103ser_descriptor[] = {
+ { "mn103ser", mn103ser_finish, },
+ { NULL },
+};
dv-mn103ser.c
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
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Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: dv-mn103tim.c
===================================================================
--- dv-mn103tim.c (nonexistent)
+++ dv-mn103tim.c (revision 842)
@@ -0,0 +1,1035 @@
+/* This file is part of the program GDB, the GNU debugger.
+
+ Copyright (C) 1998, 2003, 2007, 2008, 2009, 2010
+ Free Software Foundation, Inc.
+ Contributed by Cygnus Solutions.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see
dv-mn103tim.c
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: sim-main.h
===================================================================
--- sim-main.h (nonexistent)
+++ sim-main.h (revision 842)
@@ -0,0 +1,105 @@
+/* This file is part of the program psim.
+
+ Copyright (C) 1994-1997, Andrew Cagney
+ Copyright (C) 1997, Free Software Foundation
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see /* For kill() in insns:do_trap */
+
+#include
+#ifdef HAVE_UNISTD_H
+#include
+#endif
+
+/* These are generated files. */
+#include "itable.h"
+#include "idecode.h"
+
+typedef instruction_address sim_cia;
+static const sim_cia null_cia = {0}; /* Dummy */
+#define NULL_CIA null_cia
+/* FIXME: Perhaps igen should generate access macros for
+ `instruction_address' that we could use. */
+/*#define CIA_ADDR(cia) ((cia).ip) doesn't work for mn10300*/
+
+#define WITH_WATCHPOINTS 1
+
+#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
+mn10300_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
+
+
+#include "sim-base.h"
+
+#include "mn10300_sim.h"
+
+/* Bring data in from the cold */
+
+#define IMEM8(EA) \
+(sim_core_read_aligned_1(STATE_CPU(sd, 0), EA, exec_map, (EA)))
+
+#define IMEM8_IMMED(EA, N) \
+(sim_core_read_aligned_1(STATE_CPU(sd, 0), EA, exec_map, (EA) + (N)))
+
+
+/* FIXME: For moment, save/restore PC value found in struct State.
+ Struct State will one day go away, being placed in the sim_cpu
+ state. */
+#define CIA_GET(CPU) ((PC) + 0)
+#define CIA_SET(CPU,VAL) ((CPU)->cia = (VAL), PC = (VAL))
+
+
+struct _sim_cpu {
+ sim_event *pending_nmi;
+ sim_cia cia;
+ sim_cpu_base base;
+};
+
+
+struct sim_state {
+
+ /* the processors proper */
+ sim_cpu cpu;
+#define STATE_CPU(sd, n) (&(sd)->cpu)
+
+ /* The base class. */
+ sim_state_base base;
+
+};
+
+/* For compatibility, until all functions converted to passing
+ SIM_DESC as an argument */
+extern SIM_DESC simulator;
+
+/* (re) initialize the simulator */
+
+extern void engine_init(SIM_DESC sd);
+extern SIM_CORE_SIGNAL_FN mn10300_core_signal;
+
+#endif
sim-main.h
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: dv-mn103int.c
===================================================================
--- dv-mn103int.c (nonexistent)
+++ dv-mn103int.c (revision 842)
@@ -0,0 +1,830 @@
+/* This file is part of the program GDB, the GNU debugger.
+
+ Copyright (C) 1998, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+ Contributed by Cygnus Solutions.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see
+
+ Specify the address of the ICR (total of 30 registers), IAGR and
+ EXTMD registers (within the parent bus).
+
+ The reg property value `0x34000100 0x7C 0x34000200 0x8 0x3400280
+ 0x8' locates the interrupt controller at the addresses specified in
+ the mn103002 interrupt controller user guide.
+
+
+ PORTS
+
+
+ nmi (output)
+
+ Non-maskable interrupt output port. An event on this output ports
+ indicates a NMI request from the interrupt controller. The value
+ attached to the event should be ignored.
+
+
+ level (output)
+
+ Maskable interrupt level output port. An event on this output port
+ indicates a maskable interrupt request at the specified level. The
+ event value defines the level being requested.
+
+ The interrupt controller will generate an event on this port
+ whenever there is a change to the internal state of the interrupt
+ controller.
+
+
+ ack (input)
+
+ Signal from processor indicating that a maskable interrupt has been
+ accepted and the interrupt controller should latch the IAGR with
+ value of the current highest priority interrupting group.
+
+ The event value is the interrupt level being accepted by the
+ processor. It should be consistent with the most recent LEVEL sent
+ to the processor from the interrupt controller.
+
+
+ int[0..100] (input)
+
+ Level or edge triggered interrupt input port. Each of the 30
+ groups (0..30) can have up to 4 (0..3) interrupt inputs. The
+ interpretation of a port event/value is determined by the
+ configuration of the corresponding interrupt group.
+
+ For convenience, numerous aliases to these interrupt inputs are
+ provided.
+
+
+ BUGS
+
+
+ For edge triggered interrupts, the interrupt controller does not
+ differentiate between POSITIVE (rising) and NEGATIVE (falling)
+ edges. Instead any input port event is considered to be an
+ interrupt trigger.
+
+ For level sensitive interrupts, the interrupt controller ignores
+ active HIGH/LOW settings and instead always interprets a nonzero
+ port value as an interrupt assertion and a zero port value as a
+ negation.
+
+ */
+
+
+/* The interrupt groups - numbered according to mn103002 convention */
+
+enum mn103int_trigger {
+ ACTIVE_LOW,
+ ACTIVE_HIGH,
+ POSITIVE_EDGE,
+ NEGATIVE_EDGE,
+};
+
+enum mn103int_type {
+ NMI_GROUP,
+ LEVEL_GROUP,
+};
+
+struct mn103int_group {
+ int gid;
+ int level;
+ unsigned enable;
+ unsigned request;
+ unsigned input;
+ enum mn103int_trigger trigger;
+ enum mn103int_type type;
+};
+
+enum {
+ FIRST_NMI_GROUP = 0,
+ LAST_NMI_GROUP = 1,
+ FIRST_LEVEL_GROUP = 2,
+ LAST_LEVEL_GROUP = 30,
+ NR_GROUPS,
+};
+
+enum {
+ LOWEST_LEVEL = 7,
+};
+
+/* The interrupt controller register address blocks */
+
+struct mn103int_block {
+ unsigned_word base;
+ unsigned_word bound;
+};
+
+enum { ICR_BLOCK, IAGR_BLOCK, EXTMD_BLOCK, NR_BLOCKS };
+
+
+struct mn103int {
+ struct mn103int_block block[NR_BLOCKS];
+ struct mn103int_group group[NR_GROUPS];
+ unsigned interrupt_accepted_group;
+};
+
+
+
+/* output port ID's */
+
+enum {
+ NMI_PORT,
+ LEVEL_PORT,
+};
+
+
+/* input port ID's */
+
+enum {
+ G0_PORT = 0,
+ G1_PORT = 4,
+ G2_PORT = 8,
+ G3_PORT = 12,
+ G4_PORT = 16,
+ G5_PORT = 20,
+ G6_PORT = 24,
+ G7_PORT = 28,
+ G8_PORT = 32,
+ G9_PORT = 36,
+ G10_PORT = 40,
+ G11_PORT = 44,
+ G12_PORT = 48,
+ G13_PORT = 52,
+ G14_PORT = 56,
+ G15_PORT = 60,
+ G16_PORT = 64,
+ G17_PORT = 68,
+ G18_PORT = 72,
+ G19_PORT = 76,
+ G20_PORT = 80,
+ G21_PORT = 84,
+ G22_PORT = 88,
+ G23_PORT = 92,
+ IRQ0_PORT = G23_PORT,
+ G24_PORT = 96,
+ G25_PORT = 100,
+ G26_PORT = 104,
+ G27_PORT = 108,
+ IRQ4_PORT = G27_PORT,
+ G28_PORT = 112,
+ G29_PORT = 116,
+ G30_PORT = 120,
+ NR_G_PORTS = 124,
+ ACK_PORT,
+};
+
+static const struct hw_port_descriptor mn103int_ports[] = {
+
+ /* interrupt outputs */
+
+ { "nmi", NMI_PORT, 0, output_port, },
+ { "level", LEVEL_PORT, 0, output_port, },
+
+ /* interrupt ack (latch) input from cpu */
+
+ { "ack", ACK_PORT, 0, input_port, },
+
+ /* interrupt inputs (as names) */
+
+ { "nmirq", G0_PORT + 0, 0, input_port, },
+ { "watchdog", G0_PORT + 1, 0, input_port, },
+ { "syserr", G0_PORT + 2, 0, input_port, },
+
+ { "timer-0-underflow", G2_PORT, 0, input_port, },
+ { "timer-1-underflow", G3_PORT, 0, input_port, },
+ { "timer-2-underflow", G4_PORT, 0, input_port, },
+ { "timer-3-underflow", G5_PORT, 0, input_port, },
+ { "timer-4-underflow", G6_PORT, 0, input_port, },
+ { "timer-5-underflow", G7_PORT, 0, input_port, },
+ { "timer-6-underflow", G8_PORT, 0, input_port, },
+
+ { "timer-6-compare-a", G9_PORT, 0, input_port, },
+ { "timer-6-compare-b", G10_PORT, 0, input_port, },
+
+ { "dma-0-end", G12_PORT, 0, input_port, },
+ { "dma-1-end", G13_PORT, 0, input_port, },
+ { "dma-2-end", G14_PORT, 0, input_port, },
+ { "dma-3-end", G15_PORT, 0, input_port, },
+
+ { "serial-0-receive", G16_PORT, 0, input_port, },
+ { "serial-0-transmit", G17_PORT, 0, input_port, },
+
+ { "serial-1-receive", G18_PORT, 0, input_port, },
+ { "serial-1-transmit", G19_PORT, 0, input_port, },
+
+ { "serial-2-receive", G20_PORT, 0, input_port, },
+ { "serial-2-transmit", G21_PORT, 0, input_port, },
+
+ { "irq-0", G23_PORT, 0, input_port, },
+ { "irq-1", G24_PORT, 0, input_port, },
+ { "irq-2", G25_PORT, 0, input_port, },
+ { "irq-3", G26_PORT, 0, input_port, },
+ { "irq-4", G27_PORT, 0, input_port, },
+ { "irq-5", G28_PORT, 0, input_port, },
+ { "irq-6", G29_PORT, 0, input_port, },
+ { "irq-7", G30_PORT, 0, input_port, },
+
+ /* interrupt inputs (as generic numbers) */
+
+ { "int", 0, NR_G_PORTS, input_port, },
+
+ { NULL, },
+};
+
+
+/* Macros for extracting/restoring the various register bits */
+
+#define EXTRACT_ID(X) (LSEXTRACTED8 ((X), 3, 0))
+#define INSERT_ID(X) (LSINSERTED8 ((X), 3, 0))
+
+#define EXTRACT_IR(X) (LSEXTRACTED8 ((X), 7, 4))
+#define INSERT_IR(X) (LSINSERTED8 ((X), 7, 4))
+
+#define EXTRACT_IE(X) (LSEXTRACTED8 ((X), 3, 0))
+#define INSERT_IE(X) (LSINSERTED8 ((X), 3, 0))
+
+#define EXTRACT_LV(X) (LSEXTRACTED8 ((X), 6, 4))
+#define INSERT_LV(X) (LSINSERTED8 ((X), 6, 4))
+
+
+
+/* Finish off the partially created hw device. Attach our local
+ callbacks. Wire up our port names etc */
+
+static hw_io_read_buffer_method mn103int_io_read_buffer;
+static hw_io_write_buffer_method mn103int_io_write_buffer;
+static hw_port_event_method mn103int_port_event;
+static hw_ioctl_method mn103int_ioctl;
+
+
+
+static void
+attach_mn103int_regs (struct hw *me,
+ struct mn103int *controller)
+{
+ int i;
+ if (hw_find_property (me, "reg") == NULL)
+ hw_abort (me, "Missing \"reg\" property");
+ for (i = 0; i < NR_BLOCKS; i++)
+ {
+ unsigned_word attach_address;
+ int attach_space;
+ unsigned attach_size;
+ reg_property_spec reg;
+ if (!hw_find_reg_array_property (me, "reg", i, ®))
+ hw_abort (me, "\"reg\" property must contain three addr/size entries");
+ hw_unit_address_to_attach_address (hw_parent (me),
+ ®.address,
+ &attach_space,
+ &attach_address,
+ me);
+ controller->block[i].base = attach_address;
+ hw_unit_size_to_attach_size (hw_parent (me),
+ ®.size,
+ &attach_size, me);
+ controller->block[i].bound = attach_address + (attach_size - 1);
+ hw_attach_address (hw_parent (me),
+ 0,
+ attach_space, attach_address, attach_size,
+ me);
+ }
+}
+
+static void
+mn103int_finish (struct hw *me)
+{
+ int gid;
+ struct mn103int *controller;
+
+ controller = HW_ZALLOC (me, struct mn103int);
+ set_hw_data (me, controller);
+ set_hw_io_read_buffer (me, mn103int_io_read_buffer);
+ set_hw_io_write_buffer (me, mn103int_io_write_buffer);
+ set_hw_ports (me, mn103int_ports);
+ set_hw_port_event (me, mn103int_port_event);
+ me->to_ioctl = mn103int_ioctl;
+
+ /* Attach ourself to our parent bus */
+ attach_mn103int_regs (me, controller);
+
+ /* Initialize all the groups according to their default configuration */
+ for (gid = 0; gid < NR_GROUPS; gid++)
+ {
+ struct mn103int_group *group = &controller->group[gid];
+ group->trigger = NEGATIVE_EDGE;
+ group->gid = gid;
+ if (FIRST_NMI_GROUP <= gid && gid <= LAST_NMI_GROUP)
+ {
+ group->enable = 0xf;
+ group->type = NMI_GROUP;
+ }
+ else if (FIRST_LEVEL_GROUP <= gid && gid <= LAST_LEVEL_GROUP)
+ {
+ group->enable = 0x0;
+ group->type = LEVEL_GROUP;
+ }
+ else
+ hw_abort (me, "internal error - unknown group id");
+ }
+}
+
+
+
+/* Perform the nasty work of figuring out which of the interrupt
+ groups should have its interrupt delivered. */
+
+static int
+find_highest_interrupt_group (struct hw *me,
+ struct mn103int *controller)
+{
+ int gid;
+ int selected;
+
+ /* FIRST_NMI_GROUP (group zero) is used as a special default value
+ when searching for an interrupt group.*/
+ selected = FIRST_NMI_GROUP;
+ controller->group[FIRST_NMI_GROUP].level = 7;
+
+ for (gid = FIRST_LEVEL_GROUP; gid <= LAST_LEVEL_GROUP; gid++)
+ {
+ struct mn103int_group *group = &controller->group[gid];
+ if ((group->request & group->enable) != 0)
+ {
+ /* Remember, lower level, higher priority. */
+ if (group->level < controller->group[selected].level)
+ {
+ selected = gid;
+ }
+ }
+ }
+ return selected;
+}
+
+
+/* Notify the processor of an interrupt level update */
+
+static void
+push_interrupt_level (struct hw *me,
+ struct mn103int *controller)
+{
+ int selected = find_highest_interrupt_group (me, controller);
+ int level = controller->group[selected].level;
+ HW_TRACE ((me, "port-out - selected=%d level=%d", selected, level));
+ hw_port_event (me, LEVEL_PORT, level);
+}
+
+
+/* An event arrives on an interrupt port */
+
+static void
+mn103int_port_event (struct hw *me,
+ int my_port,
+ struct hw *source,
+ int source_port,
+ int level)
+{
+ struct mn103int *controller = hw_data (me);
+
+ switch (my_port)
+ {
+
+ case ACK_PORT:
+ {
+ int selected = find_highest_interrupt_group (me, controller);
+ if (controller->group[selected].level != level)
+ hw_abort (me, "botched level synchronisation");
+ controller->interrupt_accepted_group = selected;
+ HW_TRACE ((me, "port-event port=ack level=%d - selected=%d",
+ level, selected));
+ break;
+ }
+
+ default:
+ {
+ int gid;
+ int iid;
+ struct mn103int_group *group;
+ unsigned interrupt;
+ if (my_port > NR_G_PORTS)
+ hw_abort (me, "Event on unknown port %d", my_port);
+
+ /* map the port onto an interrupt group */
+ gid = (my_port % NR_G_PORTS) / 4;
+ group = &controller->group[gid];
+ iid = (my_port % 4);
+ interrupt = 1 << iid;
+
+ /* update our cached input */
+ if (level)
+ group->input |= interrupt;
+ else
+ group->input &= ~interrupt;
+
+ /* update the request bits */
+ switch (group->trigger)
+ {
+ case ACTIVE_LOW:
+ case ACTIVE_HIGH:
+ if (level)
+ group->request |= interrupt;
+ break;
+ case NEGATIVE_EDGE:
+ case POSITIVE_EDGE:
+ group->request |= interrupt;
+ }
+
+ /* force a corresponding output */
+ switch (group->type)
+ {
+
+ case NMI_GROUP:
+ {
+ /* for NMI's the event is the trigger */
+ HW_TRACE ((me, "port-in port=%d group=%d interrupt=%d - NMI",
+ my_port, gid, iid));
+ if ((group->request & group->enable) != 0)
+ {
+ HW_TRACE ((me, "port-out NMI"));
+ hw_port_event (me, NMI_PORT, 1);
+ }
+ break;
+ }
+
+ case LEVEL_GROUP:
+ {
+ /* if an interrupt is now pending */
+ HW_TRACE ((me, "port-in port=%d group=%d interrupt=%d - INT",
+ my_port, gid, iid));
+ push_interrupt_level (me, controller);
+ break;
+ }
+ }
+ break;
+ }
+
+ }
+}
+
+/* Read/write to to an ICR (group control register) */
+
+static struct mn103int_group *
+decode_group (struct hw *me,
+ struct mn103int *controller,
+ unsigned_word base,
+ unsigned_word *offset)
+{
+ int gid = (base / 4) % NR_GROUPS;
+ *offset = (base % 4);
+ return &controller->group[gid];
+}
+
+static unsigned8
+read_icr (struct hw *me,
+ struct mn103int *controller,
+ unsigned_word base)
+{
+ unsigned_word offset;
+ struct mn103int_group *group = decode_group (me, controller, base, &offset);
+ unsigned8 val = 0;
+ switch (group->type)
+ {
+
+ case NMI_GROUP:
+ switch (offset)
+ {
+ case 0:
+ val = INSERT_ID (group->request);
+ HW_TRACE ((me, "read-icr group=%d:0 nmi 0x%02x",
+ group->gid, val));
+ break;
+ default:
+ break;
+ }
+ break;
+
+ case LEVEL_GROUP:
+ switch (offset)
+ {
+ case 0:
+ val = (INSERT_IR (group->request)
+ | INSERT_ID (group->request & group->enable));
+ HW_TRACE ((me, "read-icr group=%d:0 level 0x%02x",
+ group->gid, val));
+ break;
+ case 1:
+ val = (INSERT_LV (group->level)
+ | INSERT_IE (group->enable));
+ HW_TRACE ((me, "read-icr level-%d:1 level 0x%02x",
+ group->gid, val));
+ break;
+ }
+ break;
+
+ default:
+ break;
+
+ }
+
+ return val;
+}
+
+static void
+write_icr (struct hw *me,
+ struct mn103int *controller,
+ unsigned_word base,
+ unsigned8 val)
+{
+ unsigned_word offset;
+ struct mn103int_group *group = decode_group (me, controller, base, &offset);
+ switch (group->type)
+ {
+
+ case NMI_GROUP:
+ switch (offset)
+ {
+ case 0:
+ HW_TRACE ((me, "write-icr group=%d:0 nmi 0x%02x",
+ group->gid, val));
+ group->request &= ~EXTRACT_ID (val);
+ break;
+ /* Special backdoor access to SYSEF flag from CPU. See
+ interp.c:program_interrupt(). */
+ case 3:
+ HW_TRACE ((me, "write-icr-special group=%d:0 nmi 0x%02x",
+ group->gid, val));
+ group->request |= EXTRACT_ID (val);
+ default:
+ break;
+ }
+ break;
+
+ case LEVEL_GROUP:
+ switch (offset)
+ {
+ case 0: /* request/detect */
+ /* Clear any ID bits and then set them according to IR */
+ HW_TRACE ((me, "write-icr group=%d:0 level 0x%02x %x:%x:%x",
+ group->gid, val,
+ group->request, EXTRACT_IR (val), EXTRACT_ID (val)));
+ group->request =
+ ((EXTRACT_IR (val) & EXTRACT_ID (val))
+ | (EXTRACT_IR (val) & group->request)
+ | (~EXTRACT_IR (val) & ~EXTRACT_ID (val) & group->request));
+ break;
+ case 1: /* level/enable */
+ HW_TRACE ((me, "write-icr group=%d:1 level 0x%02x",
+ group->gid, val));
+ group->level = EXTRACT_LV (val);
+ group->enable = EXTRACT_IE (val);
+ break;
+ default:
+ /* ignore */
+ break;
+ }
+ push_interrupt_level (me, controller);
+ break;
+
+ default:
+ break;
+
+ }
+}
+
+
+/* Read the IAGR (Interrupt accepted group register) */
+
+static unsigned8
+read_iagr (struct hw *me,
+ struct mn103int *controller,
+ unsigned_word offset)
+{
+ unsigned8 val;
+ switch (offset)
+ {
+ case 0:
+ {
+ if (!(controller->group[controller->interrupt_accepted_group].request
+ & controller->group[controller->interrupt_accepted_group].enable))
+ {
+ /* oops, lost the request */
+ val = 0;
+ HW_TRACE ((me, "read-iagr:0 lost-0"));
+ }
+ else
+ {
+ val = (controller->interrupt_accepted_group << 2);
+ HW_TRACE ((me, "read-iagr:0 %d", (int) val));
+ }
+ break;
+ }
+ case 1:
+ val = 0;
+ HW_TRACE ((me, "read-iagr:1 %d", (int) val));
+ break;
+ default:
+ val = 0;
+ HW_TRACE ((me, "read-iagr 0x%08lx bad offset", (long) offset));
+ break;
+ }
+ return val;
+}
+
+
+/* Reads/writes to the EXTMD (external interrupt trigger configuration
+ register) */
+
+static struct mn103int_group *
+external_group (struct mn103int *controller,
+ unsigned_word offset)
+{
+ switch (offset)
+ {
+ case 0:
+ return &controller->group[IRQ0_PORT/4];
+ case 1:
+ return &controller->group[IRQ4_PORT/4];
+ default:
+ return NULL;
+ }
+}
+
+static unsigned8
+read_extmd (struct hw *me,
+ struct mn103int *controller,
+ unsigned_word offset)
+{
+ int gid;
+ unsigned8 val = 0;
+ struct mn103int_group *group = external_group (controller, offset);
+ if (group != NULL)
+ {
+ for (gid = 0; gid < 4; gid++)
+ {
+ val |= (group[gid].trigger << (gid * 2));
+ }
+ }
+ HW_TRACE ((me, "read-extmd 0x%02lx", (long) val));
+ return val;
+}
+
+static void
+write_extmd (struct hw *me,
+ struct mn103int *controller,
+ unsigned_word offset,
+ unsigned8 val)
+{
+ int gid;
+ struct mn103int_group *group = external_group (controller, offset);
+ if (group != NULL)
+ {
+ for (gid = 0; gid < 4; gid++)
+ {
+ group[gid].trigger = (val >> (gid * 2)) & 0x3;
+ /* MAYBE: interrupts already pending? */
+ }
+ }
+ HW_TRACE ((me, "write-extmd 0x%02lx", (long) val));
+}
+
+
+/* generic read/write */
+
+static int
+decode_addr (struct hw *me,
+ struct mn103int *controller,
+ unsigned_word address,
+ unsigned_word *offset)
+{
+ int i;
+ for (i = 0; i < NR_BLOCKS; i++)
+ {
+ if (address >= controller->block[i].base
+ && address <= controller->block[i].bound)
+ {
+ *offset = address - controller->block[i].base;
+ return i;
+ }
+ }
+ hw_abort (me, "bad address");
+ return -1;
+}
+
+static unsigned
+mn103int_io_read_buffer (struct hw *me,
+ void *dest,
+ int space,
+ unsigned_word base,
+ unsigned nr_bytes)
+{
+ struct mn103int *controller = hw_data (me);
+ unsigned8 *buf = dest;
+ unsigned byte;
+ /* HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes)); */
+ for (byte = 0; byte < nr_bytes; byte++)
+ {
+ unsigned_word address = base + byte;
+ unsigned_word offset;
+ switch (decode_addr (me, controller, address, &offset))
+ {
+ case ICR_BLOCK:
+ buf[byte] = read_icr (me, controller, offset);
+ break;
+ case IAGR_BLOCK:
+ buf[byte] = read_iagr (me, controller, offset);
+ break;
+ case EXTMD_BLOCK:
+ buf[byte] = read_extmd (me, controller, offset);
+ break;
+ default:
+ hw_abort (me, "bad switch");
+ }
+ }
+ return nr_bytes;
+}
+
+static unsigned
+mn103int_io_write_buffer (struct hw *me,
+ const void *source,
+ int space,
+ unsigned_word base,
+ unsigned nr_bytes)
+{
+ struct mn103int *controller = hw_data (me);
+ const unsigned8 *buf = source;
+ unsigned byte;
+ /* HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes)); */
+ for (byte = 0; byte < nr_bytes; byte++)
+ {
+ unsigned_word address = base + byte;
+ unsigned_word offset;
+ switch (decode_addr (me, controller, address, &offset))
+ {
+ case ICR_BLOCK:
+ write_icr (me, controller, offset, buf[byte]);
+ break;
+ case IAGR_BLOCK:
+ /* not allowed */
+ break;
+ case EXTMD_BLOCK:
+ write_extmd (me, controller, offset, buf[byte]);
+ break;
+ default:
+ hw_abort (me, "bad switch");
+ }
+ }
+ return nr_bytes;
+}
+
+static int
+mn103int_ioctl(struct hw *me,
+ hw_ioctl_request request,
+ va_list ap)
+{
+ struct mn103int *controller = (struct mn103int *)hw_data(me);
+ controller->group[0].request = EXTRACT_ID(4);
+ mn103int_port_event(me, 2 /* nmi_port(syserr) */, NULL, 0, 0);
+ return 0;
+}
+
+
+const struct hw_descriptor dv_mn103int_descriptor[] = {
+ { "mn103int", mn103int_finish, },
+ { NULL },
+};
dv-mn103int.c
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: configure.ac
===================================================================
--- configure.ac (nonexistent)
+++ configure.ac (revision 842)
@@ -0,0 +1,24 @@
+dnl Process this file with autoconf to produce a configure script.
+AC_PREREQ(2.59)dnl
+AC_INIT(Makefile.in)
+AC_CONFIG_HEADER(config.h:config.in)
+
+sinclude(../common/aclocal.m4)
+
+# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around
+# it by inlining the macro's contents.
+sinclude(../common/common.m4)
+
+SIM_AC_OPTION_ENDIAN(LITTLE_ENDIAN)
+SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
+SIM_AC_OPTION_HOSTENDIAN
+SIM_AC_OPTION_WARNINGS
+SIM_AC_OPTION_RESERVED_BITS
+SIM_AC_OPTION_BITSIZE(32,31)
+SIM_AC_OPTION_INLINE()
+SIM_AC_OPTION_HARDWARE(yes,,mn103cpu mn103int mn103tim mn103ser mn103iop)
+
+AC_CHECK_FUNCS(time chmod utime fork execve execv chown)
+AC_CHECK_HEADERS(unistd.h stdlib.h string.h strings.h utime.h time.h)
+
+SIM_AC_OUTPUT
configure.ac
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: config.in
===================================================================
--- config.in (nonexistent)
+++ config.in (revision 842)
@@ -0,0 +1,140 @@
+/* config.in. Generated from configure.ac by autoheader. */
+
+/* Define if building universal (internal helper macro) */
+#undef AC_APPLE_UNIVERSAL_BUILD
+
+/* Define to 1 if translation of program messages to the user's native
+ language is requested. */
+#undef ENABLE_NLS
+
+/* Define to 1 if you have the `chmod' function. */
+#undef HAVE_CHMOD
+
+/* Define to 1 if you have the `chown' function. */
+#undef HAVE_CHOWN
+
+/* Define to 1 if you have the header file. */
+#undef HAVE_DLFCN_H
+
+/* Define to 1 if you have the header file. */
+#undef HAVE_ERRNO_H
+
+/* Define to 1 if you have the `execv' function. */
+#undef HAVE_EXECV
+
+/* Define to 1 if you have the `execve' function. */
+#undef HAVE_EXECVE
+
+/* Define to 1 if you have the header file. */
+#undef HAVE_FCNTL_H
+
+/* Define to 1 if you have the `fork' function. */
+#undef HAVE_FORK
+
+/* Define to 1 if you have the header file. */
+#undef HAVE_FPU_CONTROL_H
+
+/* Define to 1 if you have the `getrusage' function. */
+#undef HAVE_GETRUSAGE
+
+/* Define to 1 if you have the header file. */
+#undef HAVE_INTTYPES_H
+
+/* Define to 1 if you have the `nsl' library (-lnsl). */
+#undef HAVE_LIBNSL
+
+/* Define to 1 if you have the `socket' library (-lsocket). */
+#undef HAVE_LIBSOCKET
+
+/* Define to 1 if you have the header file. */
+#undef HAVE_MEMORY_H
+
+/* Define to 1 if you have the `sigaction' function. */
+#undef HAVE_SIGACTION
+
+/* Define to 1 if you have the header file. */
+#undef HAVE_STDINT_H
+
+/* Define to 1 if you have the header file. */
+#undef HAVE_STDLIB_H
+
+/* Define to 1 if you have the header file. */
+#undef HAVE_STRINGS_H
+
+/* Define to 1 if you have the header file. */
+#undef HAVE_STRING_H
+
+/* Define to 1 if you have the header file. */
+#undef HAVE_SYS_RESOURCE_H
+
+/* Define to 1 if you have the header file. */
+#undef HAVE_SYS_STAT_H
+
+/* Define to 1 if you have the header file. */
+#undef HAVE_SYS_TIME_H
+
+/* Define to 1 if you have the header file. */
+#undef HAVE_SYS_TYPES_H
+
+/* Define to 1 if you have the `time' function. */
+#undef HAVE_TIME
+
+/* Define to 1 if you have the header file. */
+#undef HAVE_TIME_H
+
+/* Define to 1 if you have the header file. */
+#undef HAVE_UNISTD_H
+
+/* Define to 1 if you have the `utime' function. */
+#undef HAVE_UTIME
+
+/* Define to 1 if you have the header file. */
+#undef HAVE_UTIME_H
+
+/* Define to 1 if you have the header file. */
+#undef HAVE_ZLIB_H
+
+/* Define to 1 if you have the `__setfpucw' function. */
+#undef HAVE___SETFPUCW
+
+/* Define to the address where bug reports for this package should be sent. */
+#undef PACKAGE_BUGREPORT
+
+/* Define to the full name of this package. */
+#undef PACKAGE_NAME
+
+/* Define to the full name and version of this package. */
+#undef PACKAGE_STRING
+
+/* Define to the one symbol short name of this package. */
+#undef PACKAGE_TARNAME
+
+/* Define to the home page for this package. */
+#undef PACKAGE_URL
+
+/* Define to the version of this package. */
+#undef PACKAGE_VERSION
+
+/* Additional package description */
+#undef PKGVERSION
+
+/* Bug reporting address */
+#undef REPORT_BUGS_TO
+
+/* Define as the return type of signal handlers (`int' or `void'). */
+#undef RETSIGTYPE
+
+/* Define to 1 if you have the ANSI C header files. */
+#undef STDC_HEADERS
+
+/* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most
+ significant byte first (like Motorola and SPARC, unlike Intel). */
+#if defined AC_APPLE_UNIVERSAL_BUILD
+# if defined __BIG_ENDIAN__
+# define WORDS_BIGENDIAN 1
+# endif
+#else
+# ifndef WORDS_BIGENDIAN
+# undef WORDS_BIGENDIAN
+# endif
+#endif