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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/gnu-old/gdb-7.1/sim/testsuite/sim/cris
    from Rev 227 to Rev 816
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  •

Rev 227 → Rev 816

/asm/cmpr.ms
0,0 → 1,102
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: ffffffff\n2\nffff\nffffffff\n78134452\nffffffff\n2\nffff\nfedaffff\n78134452\nffffffff\n2\nff\nfeda49ff\n78134452\n85649222\n
 
.include "testutils.inc"
start
moveq -1,r3
moveq -2,r4
cmp.d r4,r3
test_cc 0 0 0 0
dumpr3 ; ffffffff
 
moveq 2,r3
moveq 1,r4
cmp.d r4,r3
test_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xffff,r3
move.d -0xffff,r4
cmp.d r4,r3
test_cc 0 0 0 1
dumpr3 ; ffff
 
moveq 1,r4
moveq -1,r3
cmp.d r4,r3
test_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d -0x5432f789,r4
move.d 0x78134452,r3
cmp.d r4,r3
test_cc 1 0 1 1
dumpr3 ; 78134452
 
moveq -1,r3
moveq -2,r4
cmp.w r4,r3
test_cc 0 0 0 0
dumpr3 ; ffffffff
 
moveq 2,r3
moveq 1,r4
cmp.w r4,r3
test_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xffff,r3
move.d -0xffff,r4
cmp.w r4,r3
test_cc 1 0 0 0
dumpr3 ; ffff
 
move.d 0xfedaffff,r3
move.d -0xfedaffff,r4
cmp.w r4,r3
test_cc 1 0 0 0
dumpr3 ; fedaffff
 
move.d -0x5432f789,r4
move.d 0x78134452,r3
cmp.w r4,r3
test_cc 0 0 0 0
dumpr3 ; 78134452
 
moveq -1,r3
moveq -2,r4
cmp.b r4,r3
test_cc 0 0 0 0
dumpr3 ; ffffffff
 
moveq 2,r3
moveq 1,r4
cmp.b r4,r3
test_cc 0 0 0 0
dumpr3 ; 2
 
move.d -0xff,r4
move.d 0xff,r3
cmp.b r4,r3
test_cc 1 0 0 0
dumpr3 ; ff
 
move.d -0xfeda49ff,r4
move.d 0xfeda49ff,r3
cmp.b r4,r3
test_cc 1 0 0 0
dumpr3 ; feda49ff
 
move.d -0x5432f789,r4
move.d 0x78134452,r3
cmp.b r4,r3
test_cc 1 0 0 1
dumpr3 ; 78134452
 
move.d 0x85649222,r3
move.d 0x77445622,r4
cmp.b r4,r3
test_cc 0 1 0 0
dumpr3 ; 85649222
 
quit
/asm/x7-v10.ms
0,0 → 1,31
#mach: crisv10
#ld: --section-start=.text=0
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: c 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnzvc 4\n
#output: e 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 10 0 0 0 24 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n
#output: 14 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 3\n
#output: 18 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 3\n
#output: 20 0 0 0 24 0 24 0 0 0 0 0 0 0 0 * ixnzvc 4\n
#sim: --cris-trace=basic
 
; With a "--cris-trace=all", cycles for the third and last line would be 5.
 
; Check that prefix+insn are traced as one.
 
.include "testutils.inc"
startnostack
nop
move.d [0f],r3
nop
moveq 0,r4
move.d [r3+r4.b],r5
move.d [r3+4],r5
bdap.d 0,r3
move.d [r3],r5
break 15
.p2align 2
0:
.dword 0b
.dword 0b
/asm/tmvm1.ms
0,0 → 1,53
#mach: crisv32
#output: Basic clock cycles, total @: 18\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 6\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
 
; Check that movem to register followed by register write dword
; to one of the registers is logged as needing two stall cycles,
; regardless of size.
 
.include "testutils.inc"
startnostack
move.d 0f,r5
moveq 0,r8
moveq 0,r9
 
movem [r5],r4
move.d r8,r1
addq 1,r1 ; 2 cycles.
 
movem [r5],r4
move.w r8,r1
addq 1,r1 ; 2 cycles.
 
movem [r5],r4
move.b r8,r1
addq 1,r1 ; 2 cycles.
 
movem [r5],r4
move.b r8,r1
addq 1,r9
 
movem [r5],r4
move.d r8,r1
addq 1,r8
 
break 15
 
.data
.p2align 5
0:
.dword 0b
.dword 0b
.dword 0b
.dword 0b
.dword 0b
/asm/x5-v32.ms
0,0 → 1,9
#mach: crisv32
#ld: --section-start=.text=0
#sim: --cris-trace=basic
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n
#output: 8 0 0 0 0 0 14 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: a 0 0 0 0 1 14 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: c 0 0 0 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: e 0 0 2 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
.include "tmemv10.ms"
/asm/movsr.ms
0,0 → 1,46
# mach: crisv3 crisv8 crisv10 crisv32
# output: 5\nfffffff5\n5\nfffffff5\n0\n
 
; Movs between registers. Check that sign-extension is performed and the
; full register is set.
 
.include "testutils.inc"
start
moveq -1,r5
moveq 5,r4
move.b r4,r5
moveq -1,r3
movs.b r5,r3
test_move_cc 0 0 0 0
dumpr3
 
moveq 0,r5
moveq -11,r4
move.b r4,r5
moveq 0,r3
movs.b r5,r3
test_move_cc 1 0 0 0
dumpr3
 
moveq -1,r5
moveq 5,r4
move.w r4,r5
moveq -1,r3
movs.w r5,r3
test_move_cc 0 0 0 0
dumpr3
 
moveq 0,r5
moveq -11,r4
move.w r4,r5
moveq 0,r3
movs.w r5,r3
test_move_cc 1 0 0 0
dumpr3
 
moveq 0,r5
movs.b r5,r3
test_move_cc 0 1 0 0
dumpr3
 
quit
/asm/movempc.ms
0,0 → 1,8
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
start
move.d _start,r12
move.d [r12],pc
/asm/movur.ms
0,0 → 1,45
# mach: crisv3 crisv8 crisv10 crisv32
# output: 5\nf5\n5\nfff5\n0\n
 
; Movu between registers. Check that zero-extension is performed and the
; full register is set.
 
.include "testutils.inc"
start
moveq -1,r5
moveq 5,r4
move.b r4,r5
moveq -1,r3
movu.b r5,r3
test_move_cc 0 0 0 0
dumpr3
 
moveq 0,r5
moveq -11,r4
move.b r4,r5
moveq -1,r3
movu.b r5,r3
test_move_cc 0 0 0 0
dumpr3
 
moveq -1,r5
moveq 5,r4
move.w r4,r5
moveq -1,r3
movu.w r5,r3
test_move_cc 0 0 0 0
dumpr3
 
moveq 0,r5
moveq -11,r4
move.w r4,r5
moveq -1,r3
movu.w r5,r3
test_move_cc 0 0 0 0
dumpr3
 
movu.w 0,r3
test_move_cc 0 1 0 0
dumpr3
 
quit
/asm/clrjmp1.ms
0,0 → 1,36
# mach: crisv3 crisv8 crisv10 crisv32
# output: ffffff00\n
 
; A bug resulting in a non-effectual clear.b discovered running the GCC
; testsuite; jump actually wrote to p0.
 
.include "testutils.inc"
 
start
jump 1f
nop
.p2align 8
1:
move.d y,r4
 
.if 0 == ..asm.arch.cris.v32
; There was a bug causing this insn to set special register p0
; (byte-clear) to 8 (low 8 bits of location after insn).
jump [r4+]
.endif
 
1:
move.d 0f,r4
 
; The corresponding bug would cause this insn too, to set p0.
jump r4
nop
quit
0:
moveq -1,r3
clear.b r3
dumpr3
quit
 
y:
.dword 1b
/asm/swap.ms
0,0 → 1,87
# mach: crisv8 crisv10 crisv32
# output: 1ec8224a\n13785244\nc81e4a22\n44527813\n224a1ec8\n52441378\n4a22c81e\n87ecbbad\ne137ddb5\nec87adbb\n37e1b5dd\nbbad87ec\nddb5e137\nadbbec87\nb5dd37e1\n0\n
 
.include "testutils.inc"
start
move.d 0x78134452,r4
move.d r4,r3
swapr r3
test_move_cc 0 0 0 0
dumpr3 ; 1ec8224a
 
move.d r4,r3
swapb r3
test_move_cc 0 0 0 0
dumpr3 ; 13785244
 
move.d r4,r3
swapbr r3
test_move_cc 1 0 0 0
dumpr3 ; c81e4a22
 
move.d r4,r3
swapw r3
test_move_cc 0 0 0 0
dumpr3 ; 44527813
 
move.d r4,r3
swapwr r3
test_move_cc 0 0 0 0
dumpr3 ; 224a1ec8
 
move.d r4,r3
swapwb r3
test_move_cc 0 0 0 0
dumpr3 ; 52441378
 
move.d r4,r3
swapwbr r3
test_move_cc 0 0 0 0
dumpr3 ; 4a22c81e
 
move.d r4,r3
swapn r3
test_move_cc 1 0 0 0
dumpr3 ; 87ecbbad
 
move.d r4,r3
swapnr r3
test_move_cc 1 0 0 0
dumpr3 ; e137ddb5
 
move.d r4,r3
swapnb r3
test_move_cc 1 0 0 0
dumpr3 ; ec87adbb
 
move.d r4,r3
swapnbr r3
test_move_cc 0 0 0 0
dumpr3 ; 37e1b5dd
 
move.d r4,r3
swapnw r3
test_move_cc 1 0 0 0
dumpr3 ; bbad87ec
 
move.d r4,r3
swapnwr r3
test_move_cc 1 0 0 0
dumpr3 ; ddb5e137
 
move.d r4,r3
swapnwb r3
test_move_cc 1 0 0 0
dumpr3 ; adbbec87
 
move.d r4,r3
swapnwbr r3
test_move_cc 1 0 0 0
dumpr3 ; b5dd37e1
 
moveq -1,r3
swapnwbr r3
test_move_cc 0 1 0 0
dumpr3 ; 0
 
quit
/asm/raw2.ms
0,0 → 1,22
; Checking read-after-write: write-then-write unaffected.
#mach: crisv32
#output: Basic clock cycles, total @: 4\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "testutils.inc"
startnostack
.lcomm x,4
.lcomm y,4
move.d x,$r0
move.d y,$r1
move.d $r1,[$r0]
move.d $r0,[$r1]
break 15
/asm/subr.ms
0,0 → 1,102
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n85649200\n
 
.include "testutils.inc"
start
moveq -1,r3
moveq -2,r4
sub.d r4,r3
test_cc 0 0 0 0
dumpr3 ; 1
 
moveq 2,r3
moveq 1,r4
sub.d r4,r3
test_cc 0 0 0 0
dumpr3 ; 1
 
move.d 0xffff,r3
move.d -0xffff,r4
sub.d r4,r3
test_cc 0 0 0 1
dumpr3 ; 1fffe
 
moveq 1,r4
moveq -1,r3
sub.d r4,r3
test_cc 1 0 0 0
dumpr3 ; fffffffe
 
move.d -0x5432f789,r4
move.d 0x78134452,r3
sub.d r4,r3
test_cc 1 0 1 1
dumpr3 ; cc463bdb
 
moveq -1,r3
moveq -2,r4
sub.w r4,r3
test_cc 0 0 0 0
dumpr3 ; ffff0001
 
moveq 2,r3
moveq 1,r4
sub.w r4,r3
test_cc 0 0 0 0
dumpr3 ; 1
 
move.d 0xffff,r3
move.d -0xffff,r4
sub.w r4,r3
test_cc 1 0 0 0
dumpr3 ; fffe
 
move.d 0xfedaffff,r3
move.d -0xfedaffff,r4
sub.w r4,r3
test_cc 1 0 0 0
dumpr3 ; fedafffe
 
move.d -0x5432f789,r4
move.d 0x78134452,r3
sub.w r4,r3
test_cc 0 0 0 0
dumpr3 ; 78133bdb
 
moveq -1,r3
moveq -2,r4
sub.b r4,r3
test_cc 0 0 0 0
dumpr3 ; ffffff01
 
moveq 2,r3
moveq 1,r4
sub.b r4,r3
test_cc 0 0 0 0
dumpr3 ; 1
 
move.d -0xff,r4
move.d 0xff,r3
sub.b r4,r3
test_cc 1 0 0 0
dumpr3 ; fe
 
move.d -0xfeda49ff,r4
move.d 0xfeda49ff,r3
sub.b r4,r3
test_cc 1 0 0 0
dumpr3 ; feda49fe
 
move.d -0x5432f789,r4
move.d 0x78134452,r3
sub.b r4,r3
test_cc 1 0 0 1
dumpr3 ; 781344db
 
move.d 0x85649222,r3
move.d 0x77445622,r4
sub.b r4,r3
test_cc 0 1 0 0
dumpr3 ; 85649200
 
quit
/asm/x10-v10.ms
0,0 → 1,21
#mach: crisv10
#ld: --section-start=.text=0
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 3\n
#output: 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#sim: --cris-trace=basic
 
; Check that "add.d x,pc" gets 3 cycles.
 
.include "testutils.inc"
startnostack
nop
nop
add.d 1f-0f,$pc
0:
nop
1:
nop
break 15
/asm/addcpc.ms
0,0 → 1,35
# mach: crisv3 crisv8 crisv10
# output: 2f\n31\n
 
# Test that the special case add.d const,pc works.
 
.include "testutils.inc"
start
x:
add.d y-y0,pc
y0:
quit
 
.space 1000
quit
quit
quit
quit
quit
z:
move.d 49,r3
dumpr3
quit
 
.space 1000
quit
quit
quit
quit
quit
y:
move.d 47,r3
dumpr3
add.d z-z0,pc
z0:
quit
/asm/nonvcv32.ms
0,0 → 1,167
# mach: crisv32
 
.include "testutils.inc"
 
; Check for various non-arithmetic insns that C and V are not affected
; on v32 (where they were on v10), as the generic tests don't cover
; that; they are cleared before testing.
 
; First, a macro testing that VC are unaffected, not counting previous
; register contents.
.macro nonvc0 insn op
move.d $r0,$r3
setf vc
.ifnc \insn,swapnwbr
\insn \op,$r3
.else
\insn $r3
.endif
bcc 9f
nop
bvc 9f
nop
move.d $r0,$r3
clearf vc
.ifnc \insn,swapnwbr
\insn \op,$r3
.else
\insn $r3
.endif
bcs 9f
nop
bvc 8f
nop
9:
fail
8:
.endm
 
; Use the above, but initialize the non-parameter operand to a value.
.macro nonvc1 insn val op
move.d \val,$r0
nonvc0 \insn,\op
.endm
 
; Use the above, iterating over various values.
.macro nonvc2 insn op
.irp p,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000
nonvc1 \insn,\p,\op
nonvc1 \insn,-\p,\op
.endr
.endm
 
.macro nonvc2q insn op min=-63 max=63
.if \op >= \min &&&& \op <= \max
nonvc2 \insn,\op
.endif
.endm
 
; The above, for each .b .w .d insn variant.
.macro nonvcbwd insn op
.irp s,.b,.w,.d
nonvc2 \insn\s,\op
.endr
.endm
 
; For various insns with register, dword constant and memory operands.
.macro nonvcitermcd op=[$r4]
nonvc2 and.d,\op
nonvc2 move.d,\op
nonvc2 or.d,\op
.endm
 
; Similar, for various insns with register, word constant and memory operands.
.macro nonvcitermcw op=[$r4]
nonvcitermcd \op
nonvc2 and.w,\op
nonvc2 move.w,\op
nonvc2 or.w,\op
nonvc2 movs.w,\op
nonvc2 movu.w,\op
.endm
 
; Similar, for various insns with register, byte constant and memory operands.
.macro nonvcitermcb op=[$r4]
nonvcitermcw \op
nonvc2 and.b,\op
nonvc2 move.b,\op
nonvc2 or.b,\op
nonvc2 movs.b,\op
nonvc2 movu.b,\op
.endm
 
; Similar, for insns with quick constant operands.
.macro nonvciterq op
nonvcitermcb \op
nonvc2 bound.b,\op
nonvc2q andq,\op,min=-32,max=31
nonvc2q asrq,\op,min=0,max=31
nonvc2q lsrq,\op,min=0,max=31
nonvc2q orq,\op,min=-32,max=31
nonvc2q moveq,\op,min=-32,max=31
.endm
 
; Similar, for insns with register operands.
.macro nonvciterr op
nonvcitermcb \op
nonvcbwd bound,\op
nonvc2 abs,\op
nonvcbwd asr,\op
nonvc2 dstep,\op
nonvcbwd lsr,\op
nonvcbwd lsl,\op
nonvc2 lz,\op
nonvc2 swapnwbr
nonvc2 xor,\op
.endm
 
; Test all applicable constant, register and memory variants of a value.
.macro tst op
; Constants
.if (\op <= 31 &&&& \op >= -32)
nonvciterq \op
.elseif (\op <= 255 &&&& \op >= -128)
nonvcitermcb \op
nonvcbwd bound,\op
.elseif (\op <= 65535 &&&& \op >= -32767)
nonvcitermcw \op
nonvc2 bound.w,\op
nonvc2 bound.d,\op
.else
nonvcitermcd \op
nonvc2 bound.d,\op
.endif
; Registers
move.d \op,$r4
nonvciterr $r4
; Memory
nonvcitermcb [$r5]
addq 4,$r5
.section .rodata
.dword \op
.previous
.endm
 
; As above but negation too.
.macro tstpm op
tst \op
tst -\op
.endm
 
 
; Set up for the actual test.
 
start
move.d c0,$r5
 
.section .rodata
c0:
.previous
 
; Finally, test.
 
.irp x,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000
tstpm \x
.endr
 
pass
/asm/test.ms
0,0 → 1,80
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 1\n
 
.include "testutils.inc"
.data
x:
.dword 0,2,-1,0x80000000,0x5432f789
.word 0,2,-1,0xffff,0xf789
.byte 0,2,0xff,0x89
 
start
clearf nzvc
moveq -1,r3
move.d x,r5
setf vc
test.d [r5+]
test_cc 0 1 0 0
 
setf vc
test.d [r5]
test_cc 0 0 0 0
 
addq 4,r5
 
setf vc
test.d [r5+]
test_cc 1 0 0 0
 
setf vc
test.d [r5+]
test_cc 1 0 0 0
 
setf vc
test.d [r5+]
test_cc 0 0 0 0
 
setf vc
test.w [r5+]
test_cc 0 1 0 0
 
setf vc
test.w [r5]
test_cc 0 0 0 0
 
addq 2,r5
 
setf vc
test.w [r5+]
test_cc 1 0 0 0
 
setf vc
test.w [r5+]
test_cc 1 0 0 0
 
setf vc
test.w [r5+]
test_cc 1 0 0 0
 
setf vc
test.b [r5]
test_cc 0 1 0 0
 
addq 1,r5
 
setf vc
test.b [r5+]
test_cc 0 0 0 0
 
setf vc
test.b [r5+]
test_cc 1 0 0 0
 
setf vc
test.b [r5]
test_cc 1 0 0 0
 
moveq 1,r3
dumpr3
 
quit
/asm/mcp.ms
0,0 → 1,49
# mach: crisv32
# output: fffffffe\n1\n1ffff\nfffffffe\ncc463bdc\n4c463bdc\n0\n
 
.include "testutils.inc"
start
 
; Set R, clear C.
move 0x100,ccs
moveq -5,r3
move 2,mof
mcp mof,r3
test_cc 1 0 0 0
dumpr3 ; fffffffe
 
moveq 2,r3
move -1,srp
mcp srp,r3
test_cc 0 0 0 0
dumpr3 ; 1
 
move 0xffff,srp
move srp,r3
mcp srp,r3
test_cc 0 0 0 0
dumpr3 ; 1ffff
 
move -1,mof
move mof,r3
mcp mof,r3
test_cc 1 0 0 0
dumpr3 ; fffffffe
 
move 0x5432f789,mof
move.d 0x78134452,r3
mcp mof,r3
test_cc 1 0 1 0
dumpr3 ; cc463bdc
 
move 0x80000000,srp
mcp srp,r3
test_cc 0 0 1 0
dumpr3 ; 4c463bdc
 
move 0xb3b9c423,srp
mcp srp,r3
test_cc 0 1 0 0
dumpr3 ; 0
 
quit
/asm/dstep.ms
0,0 → 1,42
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: fffffffc\n4\nffff\nfffffffe\n9bf3911b\n0\n
 
.include "testutils.inc"
start
moveq -1,r3
moveq 2,r4
dstep r4,r3
test_move_cc 1 0 0 0
dumpr3 ; fffffffc
 
moveq 2,r3
moveq -1,r4
dstep r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 4
 
move.d 0xffff,r4
move.d r4,r3
dstep r4,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
moveq -1,r4
move.d r4,r3
dstep r4,r3
test_move_cc 1 0 0 0
dumpr3 ; fffffffe
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
dstep r4,r3
test_move_cc 1 0 0 0
dumpr3 ; 9bf3911b
 
move.d 0xffff,r3
move.d 0x1fffe,r4
dstep r4,r3
test_move_cc 0 1 0 0
dumpr3 ; 0
 
quit
/asm/movecrt10.ms
0,0 → 1,17
#mach: crisv10
#output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n
#output: Basic clock cycles, total @: 82\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "movecr.ms"
 
# This test-case is accidentally the same; gets the same cycle
# count as movecrt32.ms, but please keep them separate.
/asm/subxc.ms
0,0 → 1,92
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 3\n3\nffffff03\nffff0003\nff00\n0\n10000\n10000\n0\nffffff00\n0\n781343c9\n781344c9\n78124cc9\n78134cc9\nc450\n7ffff8ce\n
 
.include "testutils.inc"
start
moveq 2,r3
subs.b 0xff,r3
test_cc 0 0 0 1
dumpr3 ; 3
 
moveq 2,r3
subs.w 0xffff,r3
test_cc 0 0 0 1
dumpr3 ; 3
 
moveq 2,r3
subu.b 0xff,r3
test_cc 1 0 0 1
dumpr3 ; ffffff03
 
moveq 2,r3
move.d 0xffffffff,r4
subu.w -1,r3
test_cc 1 0 0 1
dumpr3 ; ffff0003
 
move.d 0xffff,r3
subu.b -1,r3
test_cc 0 0 0 0
dumpr3 ; ff00
 
move.d 0xffff,r3
subu.w -1,r3
test_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0xffff,r3
subs.b 0xff,r3
test_cc 0 0 0 1
dumpr3 ; 10000
 
move.d 0xffff,r3
subs.w 0xffff,r3
test_cc 0 0 0 1
dumpr3 ; 10000
 
moveq -1,r3
subs.b 0xff,r3
test_cc 0 1 0 0
dumpr3 ; 0
 
moveq -1,r3
subs.w 0xff,r3
test_cc 1 0 0 0
dumpr3 ; ffffff00
 
moveq -1,r3
subs.w 0xffff,r3
test_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0x78134452,r3
subu.b 0x89,r3
test_cc 0 0 0 0
dumpr3 ; 781343c9
 
move.d 0x78134452,r3
subs.b 0x89,r3
test_cc 0 0 0 1
dumpr3 ; 781344c9
 
move.d 0x78134452,r3
subu.w 0xf789,r3
test_cc 0 0 0 0
dumpr3 ; 78124cc9
 
move.d 0x78134452,r3
subs.w 0xf789,r3
test_cc 0 0 0 1
dumpr3 ; 78134cc9
 
move.d 0x4452,r3
subs.w 0x8002,r3
test_cc 0 0 0 1
dumpr3 ; c450
 
move.d 0x80000032,r3
subu.w 0x764,r3
test_cc 0 0 1 0
dumpr3 ; 7ffff8ce
 
quit
/asm/andr.ms
0,0 → 1,95
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 2\n2\nffff\nffffffff\n50124400\nffff0002\n2\nfffff\nfedaff0f\n78134400\nffffff02\n2\nf02\n78134401\n78134400\n
 
.include "testutils.inc"
start
moveq -1,r3
moveq 2,r4
and.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
moveq 2,r3
moveq -1,r4
and.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xffff,r4
move.d r4,r3
and.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
moveq -1,r4
move.d r4,r3
and.d r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
and.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 50124400
 
moveq -1,r3
moveq 2,r4
and.w r4,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff0002
 
moveq 2,r3
moveq -1,r4
and.w r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xfffff,r3
move.d 0xffff,r4
and.w r4,r3
test_move_cc 1 0 0 0
dumpr3 ; fffff
 
move.d 0xfedaffaf,r3
move.d 0xff5f,r4
and.w r4,r3
test_move_cc 1 0 0 0
dumpr3 ; fedaff0f
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
and.w r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 78134400
 
moveq -1,r3
moveq 2,r4
and.b r4,r3
test_move_cc 0 0 0 0
dumpr3 ; ffffff02
 
moveq 2,r3
moveq -1,r4
and.b r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0x5a,r4
move.d 0xfa7,r3
and.b r4,r3
test_move_cc 0 0 0 0
dumpr3 ; f02
 
move.d 0x5432f789,r4
move.d 0x78134453,r3
and.b r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 78134401
 
moveq 0,r7
and.b r7,r3
test_move_cc 0 1 0 0
dumpr3 ; 78134400
 
quit
/asm/ftagd.ms
0,0 → 1,9
# mach: crisv32
# xerror:
# output: FTAGD isn't implemented\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
start
ftagd [r11]
 
quit
/asm/movumpc.ms
0,0 → 1,8
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
start
move.d _start,r1
movu.b [r1+],pc
/asm/io2.ms
0,0 → 1,18
# mach: crisv32
# sim: --cris-900000xx
# xerror:
# output: b1e\n
 
; Check correct "fail" exit.
 
.include "testutils.inc"
start
move.d 0xb1e,$r3
dumpr3
move.d 0x90000008,$acr
move.d $acr,[$acr]
move.d 0xbadc0de,$r3
dumpr3
0:
ba 0b
nop
/asm/boundr.ms
0,0 → 1,125
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 2\n2\nffff\nffffffff\n5432f789\n2\n2\nffff\nffff\nffff\nf789\n2\n2\nff\nff\n89\nfeda4953\nfeda4962\n0\n0\n
 
.include "testutils.inc"
start
moveq -1,r3
moveq 2,r4
bound.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
moveq 2,r3
moveq -1,r4
bound.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xffff,r4
move.d r4,r3
bound.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
moveq -1,r4
move.d r4,r3
bound.d r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
bound.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 5432f789
 
moveq -1,r3
moveq 2,r4
bound.w r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
moveq 2,r3
moveq -1,r4
bound.w r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
moveq -1,r3
bound.w r3,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
move.d 0xffff,r4
move.d r4,r3
bound.w r4,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
move.d 0xfedaffff,r4
move.d r4,r3
bound.w r4,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
bound.w r4,r3
test_move_cc 0 0 0 0
dumpr3 ; f789
 
moveq -1,r3
moveq 2,r4
bound.b r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
moveq 2,r3
moveq -1,r4
bound.b r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xff,r4
move.d r4,r3
bound.b r4,r3
test_move_cc 0 0 0 0
dumpr3 ; ff
 
move.d 0xfeda49ff,r4
move.d r4,r3
bound.b r4,r3
test_move_cc 0 0 0 0
dumpr3 ; ff
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
bound.b r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 89
 
move.d 0xfeda4956,r3
move.d 0xfeda4953,r4
bound.d r4,r3
test_move_cc 1 0 0 0
dumpr3 ; feda4953
 
move.d 0xfeda4962,r3
move.d 0xfeda4963,r4
bound.d r4,r3
test_move_cc 1 0 0 0
dumpr3 ; feda4962
 
move.d 0xfeda4956,r3
move.d 0,r4
bound.d r4,r3
test_move_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0xfeda4956,r4
move.d 0,r3
bound.d r4,r3
test_move_cc 0 1 0 0
dumpr3 ; 0
 
quit
/asm/movpmv32.ms
0,0 → 1,35
# mach: crisv32
# output: 11223320\nbb113344\naa557711\n
 
# Test v32-specific special registers. FIXME: more registers.
 
.include "testutils.inc"
start
.data
store:
.dword 0x11223344
.dword 0x77665544
 
.text
moveq -1,r3
move.d store,r4
move vr,[r4]
move [r4+],mof
move mof,r3
dumpr3
 
moveq -1,r3
clearf zcvn
move 0xbb113344,mof
test_cc 0 0 0 0
move mof,r3
dumpr3
 
setf zcvn
move 0xaa557711,mof
test_cc 1 1 1 1
move mof,[r4]
move.d [r4],r3
dumpr3
quit
/asm/movprv10.ms
0,0 → 1,21
# mach: crisv10
# output: ffffff0a\nbb113344\n
 
# Test v10-specific special registers. FIXME: ccr, irp, bar, brp, usp.
 
.include "testutils.inc"
start
moveq -1,r3
setf zcvn
move vr,r3
test_cc 1 1 1 1
dumpr3
 
moveq -1,r3
move.d 0xbb113344,r4
clearf zcvn
move r4,mof
move mof,r3
test_cc 0 0 0 0
dumpr3
quit
/asm/addc.ms
0,0 → 1,81
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n
 
.include "testutils.inc"
start
moveq -1,r3
add.d 2,r3
test_cc 0 0 0 1
dumpr3 ; 1
 
moveq 2,r3
add.d -1,r3
test_cc 0 0 0 1
dumpr3 ; 1
 
move.d 0xffff,r3
add.d 0xffff,r3
test_cc 0 0 0 0
dumpr3 ; 1fffe
 
moveq -1,r3
add.d -1,r3
test_cc 1 0 0 1
dumpr3 ; fffffffe
 
move.d 0x78134452,r3
add.d 0x5432f789,r3
test_cc 1 0 1 0
dumpr3 ; cc463bdb
 
moveq -1,r3
add.w 2,r3
test_cc 0 0 0 1
dumpr3 ; ffff0001
 
moveq 2,r3
add.w -1,r3
test_cc 0 0 0 1
dumpr3 ; 1
 
move.d 0xffff,r3
add.w 0xffff,r3
test_cc 1 0 0 1
dumpr3 ; fffe
 
move.d 0xfedaffff,r3
add.w 0xffff,r3
test_cc 1 0 0 1
dumpr3 ; fedafffe
 
move.d 0x78134452,r3
add.w 0xf789,r3
test_cc 0 0 0 1
dumpr3 ; 78133bdb
 
moveq -1,r3
add.b 2,r3
test_cc 0 0 0 1
dumpr3 ; ffffff01
 
moveq 2,r3
add.b -1,r3
test_cc 0 0 0 1
dumpr3 ; 1
 
move.d 0xff,r3
add.b 0xff,r3
test_cc 1 0 0 1
dumpr3 ; fe
 
move.d 0xfeda49ff,r3
add.b 0xff,r3
test_cc 1 0 0 1
dumpr3 ; feda49fe
 
move.d 0x78134452,r3
add.b 0x89,r3
test_cc 1 0 0 0
dumpr3 ; 781344db
 
quit
/asm/cmpm.ms
0,0 → 1,96
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: ffffffff\n2\nffff\nffffffff\n78134452\nffffffff\n2\nffff\nfedaffff\n78134452\nffffffff\n2\nff\nfeda49ff\n78134452\n85649222\n
 
.include "testutils.inc"
.data
x:
.dword -2,1,-0xffff,1,-0x5432f789
.word -2,1,1,0x877
.byte -2,1,0x77
.byte 0x22
 
start
moveq -1,r3
move.d x,r5
cmp.d [r5+],r3
test_cc 0 0 0 0
dumpr3 ; ffffffff
 
moveq 2,r3
cmp.d [r5],r3
test_cc 0 0 0 0
addq 4,r5
dumpr3 ; 2
 
move.d 0xffff,r3
cmp.d [r5+],r3
test_cc 0 0 0 1
dumpr3 ; ffff
 
moveq -1,r3
cmp.d [r5+],r3
test_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d 0x78134452,r3
cmp.d [r5+],r3
test_cc 1 0 1 1
dumpr3 ; 78134452
 
moveq -1,r3
cmp.w [r5+],r3
test_cc 0 0 0 0
dumpr3 ; ffffffff
 
moveq 2,r3
cmp.w [r5+],r3
test_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xffff,r3
cmp.w [r5],r3
test_cc 1 0 0 0
dumpr3 ; ffff
 
move.d 0xfedaffff,r3
cmp.w [r5+],r3
test_cc 1 0 0 0
dumpr3 ; fedaffff
 
move.d 0x78134452,r3
cmp.w [r5+],r3
test_cc 0 0 0 0
dumpr3 ; 78134452
 
moveq -1,r3
cmp.b [r5],r3
test_cc 0 0 0 0
addq 1,r5
dumpr3 ; ffffffff
 
moveq 2,r3
cmp.b [r5],r3
test_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xff,r3
cmp.b [r5],r3
test_cc 1 0 0 0
dumpr3 ; ff
 
move.d 0xfeda49ff,r3
cmp.b [r5+],r3
test_cc 1 0 0 0
dumpr3 ; feda49ff
 
move.d 0x78134452,r3
cmp.b [r5+],r3
test_cc 1 0 0 1
dumpr3 ; 78134452
 
move.d 0x85649222,r3
cmp.b [r5],r3
test_cc 0 1 0 0
dumpr3 ; 85649222
 
quit
/asm/movemrv10.ms
0,0 → 1,101
# mach: crisv0 crisv3 crisv8 crisv10
# output: 15\nffff1234\n2\n7\nb\n16\nf\n2\nf\nffffffef\n7\nfffffff4\nf\nfffffff2\nd\n10\nfffffff2\n8\nfffffff4\n
 
.include "testutils.inc"
.data
x:
.dword 8,9,10,11
y:
.dword -12,13,-14,15,16
 
start
moveq 7,r0
moveq 2,r1
move.d 0xffff1234,r2
moveq 21,r3
move.d x,r4
setf zcvn
movem r2,[r4+]
test_cc 1 1 1 1
subq 12,r4
 
dumpr3 ; 15
 
move.d [r4+],r3
dumpr3 ; ffff1234
 
move.d [r4+],r3
dumpr3 ; 2
 
move.d [r4+],r3
dumpr3 ; 7
 
move.d [r4+],r3
dumpr3 ; b
 
subq 16,r4
moveq 22,r0
moveq 15,r1
clearf zcvn
movem r0,[r4]
test_cc 0 0 0 0
move.d [r4+],r3
dumpr3 ; 16
 
move.d r1,r3
dumpr3 ; f
 
move.d [r4+],r3
dumpr3 ; 2
 
moveq 10,r2
moveq -17,r0
clearf zc
setf vn
movem r1,[r4=r4-8]
test_cc 1 0 1 0
move.d [r4+],r3
dumpr3 ; f
 
move.d [r4+],r3
dumpr3 ; ffffffef
 
move.d [r4+],r3
dumpr3 ; 7
 
move.d y,r4
setf zc
clearf vn
movem [r4+],r3
test_cc 0 1 0 1
dumpr3 ; fffffff4
 
move.d r0,r3
dumpr3 ; f
 
move.d r1,r3
dumpr3 ; fffffff2
 
moveq -12,r1
 
move.d r2,r3
dumpr3 ; d
 
move.d [r4],r3
dumpr3 ; 10
 
setf zcvn
movem [r5=r4-8],r0
test_cc 1 1 1 1
move.d r0,r3
dumpr3 ; fffffff2
 
sub.d r5,r4
move.d r4,r3
dumpr3 ; 8
 
move.d r1,r3
dumpr3 ; fffffff4
 
quit
 
/asm/opterr2.ms
0,0 → 1,5
# mach: crisv3 crisv8 crisv10 crisv32
# xerror:
# output: *: unrecognized option [`']--cris-xyz'\n
# sim: --cris-xyz
.include "nopv32t.ms"
/asm/raw15.ms
0,0 → 1,14
; Checking read-after-write: cycles included in "all".
#mach: crisv32
#output: All accounted clock cycles, total @: 6\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 2\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=all
.include "raw4.ms"
/asm/dflags.ms
0,0 → 1,62
# mach: crisv3 crisv8 crisv10 crisv32
# output: 31\n
 
; Check that flag settings in the delay slot for a conditional branch do
; not affect the branch.
 
.include "testutils.inc"
 
start
moveq 1,r3
moveq 0,r4
 
; 8-bit branches.
 
move.d r4,r4
bne 0f
move.d r3,r3
bne 1f
move.d r4,r4
nop
0:
quit
 
1:
move.d r3,r3
beq 0b
move.d r4,r4
beq 4f
move.d r3,r3
nop
quit
4:
jump 2f
nop
.space 1000
 
; 16-bit branches
 
2:
move.d r4,r4
bne 0b
move.d r3,r3
bne 3f
move.d r4,r4
nop
quit
.space 1000
 
3:
move.d r3,r3
beq 0b
move.d r4,r4
beq 4f
move.d r3,r3
nop
quit
.space 1000
 
4:
move.d 0x31,r3
dumpr3
quit
/asm/movsm.ms
0,0 → 1,44
# mach: crisv3 crisv8 crisv10 crisv32
# output: 5\nfffffff5\n5\nfffffff5\n0\n
 
; Movs between registers. Check that sign-extension is performed and the
; full register is set.
 
.include "testutils.inc"
 
.data
x:
.byte 5,-11
.word 5,-11
.word 0
 
start
move.d x,r5
 
moveq -1,r3
movs.b [r5+],r3
test_move_cc 0 0 0 0
dumpr3
 
moveq 0,r3
movs.b [r5],r3
test_move_cc 1 0 0 0
addq 1,r5
dumpr3
 
moveq -1,r3
movs.w [r5+],r3
test_move_cc 0 0 0 0
dumpr3
 
moveq 0,r3
movs.w [r5],r3
test_move_cc 1 0 0 0
addq 2,r5
dumpr3
 
movs.w [r5],r3
test_move_cc 0 1 0 0
dumpr3
 
quit
/asm/x6-v10.ms
0,0 → 1,11
#mach: crisv10
#ld: --section-start=.text=0
#sim: --cris-trace=basic
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n
#output: 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 6 0 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 8 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: a 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n
#output: c 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n
#output: e 1 2 0 2 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n
.include "tmulv10.ms"
/asm/moverwpc.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
startnostack
setf
move.d r5,pc
quit
/asm/movum.ms
0,0 → 1,40
# mach: crisv3 crisv8 crisv10 crisv32
# output: 5\nf5\n5\nfff5\n0\n
 
; Movu between registers. Check that zero-extension is performed and the
; full register is set.
 
.include "testutils.inc"
 
.data
x:
.byte 5,-11
.word 5,-11
.word 0
 
start
move.d x,r5
 
movu.b [r5+],r3
test_move_cc 0 0 0 0
dumpr3
 
movu.b [r5],r3
test_move_cc 0 0 0 0
addq 1,r5
dumpr3
 
movu.w [r5+],r3
test_move_cc 0 0 0 0
dumpr3
 
movu.w [r5],r3
test_move_cc 0 0 0 0
addq 2,r5
dumpr3
 
movu.w [r5],r3
test_move_cc 0 1 0 0
dumpr3
 
quit
/asm/fidxi.ms
0,0 → 1,9
# mach: crisv32
# xerror:
# output: FIDXI isn't implemented\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
start
fidxi [r5]
 
quit
/asm/x4-v32.ms
0,0 → 1,23
#mach: crisv32
#ld: --section-start=.text=0
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n
#output: 8 0 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: e 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 10 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 12 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 14 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 16 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 18 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 1a 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 1e 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 24 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 26 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 28 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 2a 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 2e 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 34 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 36 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 38 14 3a 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#sim: --cris-trace=basic
 
.include "tjmpsrv32.ms"
/asm/abs.ms
0,0 → 1,50
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 1\n0\n80000000\n7fffffff\n2a\n1\nffff\n1f\n0\n
 
.include "testutils.inc"
start
moveq -1,r3
 
abs r3,r3
test_move_cc 0 0 0 0
dumpr3 ; 1
 
moveq 0,r3
dumpr3 ; 0
 
move.d 0x80000000,r4
abs r4,r3
test_move_cc 1 0 0 0
dumpr3 ; 80000000
 
move.d 0x7fffffff,r4
abs r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 7fffffff
 
move.d 42,r3
abs r3,r3
test_move_cc 0 0 0 0
dumpr3 ; 2a
 
moveq 1,r6
abs r6,r3
test_move_cc 0 0 0 0
dumpr3 ; 1
 
move.d 0xffff,r3
abs r3,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
moveq -31,r5
abs r5,r3
test_move_cc 0 0 0 0
dumpr3 ; 1f
 
moveq 0,r5
abs r5,r3
test_move_cc 0 1 0 0
dumpr3 ; 0
 
quit
/asm/subm.ms
0,0 → 1,96
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n85649200\n
 
.include "testutils.inc"
.data
x:
.dword -2,1,-0xffff,1,-0x5432f789
.word -2,1,1,0x877
.byte -2,1,0x77
.byte 0x22
 
start
moveq -1,r3
move.d x,r5
sub.d [r5+],r3
test_cc 0 0 0 0
dumpr3 ; 1
 
moveq 2,r3
sub.d [r5],r3
test_cc 0 0 0 0
addq 4,r5
dumpr3 ; 1
 
move.d 0xffff,r3
sub.d [r5+],r3
test_cc 0 0 0 1
dumpr3 ; 1fffe
 
moveq -1,r3
sub.d [r5+],r3
test_cc 1 0 0 0
dumpr3 ; fffffffe
 
move.d 0x78134452,r3
sub.d [r5+],r3
test_cc 1 0 1 1
dumpr3 ; cc463bdb
 
moveq -1,r3
sub.w [r5+],r3
test_cc 0 0 0 0
dumpr3 ; ffff0001
 
moveq 2,r3
sub.w [r5+],r3
test_cc 0 0 0 0
dumpr3 ; 1
 
move.d 0xffff,r3
sub.w [r5],r3
test_cc 1 0 0 0
dumpr3 ; fffe
 
move.d 0xfedaffff,r3
sub.w [r5+],r3
test_cc 1 0 0 0
dumpr3 ; fedafffe
 
move.d 0x78134452,r3
sub.w [r5+],r3
test_cc 0 0 0 0
dumpr3 ; 78133bdb
 
moveq -1,r3
sub.b [r5],r3
test_cc 0 0 0 0
addq 1,r5
dumpr3 ; ffffff01
 
moveq 2,r3
sub.b [r5],r3
test_cc 0 0 0 0
dumpr3 ; 1
 
move.d 0xff,r3
sub.b [r5],r3
test_cc 1 0 0 0
dumpr3 ; fe
 
move.d 0xfeda49ff,r3
sub.b [r5+],r3
test_cc 1 0 0 0
dumpr3 ; feda49fe
 
move.d 0x78134452,r3
sub.b [r5+],r3
test_cc 1 0 0 1
dumpr3 ; 781344db
 
move.d 0x85649222,r3
sub.b [r5],r3
test_cc 0 1 0 0
dumpr3 ; 85649200
 
quit
/asm/nopv10t.ms
0,0 → 1,13
#mach: crisv0 crisv3 crisv8 crisv10
#output: Basic clock cycles, total @: 5\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "nopv32t.ms"
/asm/addoc.ms
0,0 → 1,44
# mach: crisv32
# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n
 
.include "testutils.inc"
.data
x:
.dword 0x55aa77ff
.dword 0xccff2244
.dword 0x88ccee19
 
start
moveq -1,r0
move.d x-32768,r5
addo.d 32769,r5,acr
move.d [acr],r3
dumpr3 ; 4455aa77
 
addu.w 32770,r5
addo.w -1,r5,acr
move.d [acr],r3
dumpr3 ; 4455aa77
 
addo.d 5,acr,acr
move.d [acr],r3
dumpr3 ; ee19ccff
 
addo.b 3,r5,acr
movu.w [acr],r3
dumpr3 ; ff22
 
addo.b -4,acr,acr
move.d [acr],r3
dumpr3 ; 4455aa77
 
addo.w 2,acr,acr
move.d [acr],r3
dumpr3 ; ff224455
 
addo.d -76789887,r5,acr
add.d 76789885,acr
move.d [acr],r3
dumpr3 ; 55aa77ff
 
quit
/asm/sfe.ms
0,0 → 1,51
# mach: crisv32
# output: 4000c800\nc3221800\nc8606400\n48606400\n419d8260\n
 
; Check that SFE affects CCS the right way.
 
.include "testutils.inc"
start
 
; Set SPC to 1 to disable single step exceptions when S flag is set.
move 1,spc
 
; CCS:
; 31 24 23 16 15 8 7 0
; +---+-----------+-------+-------+-----------+---+---------------+
; |Q M|S R P U I X N Z V C|S R P U I X N Z V C|S R P U I X N Z V C|
; | |2 2 2 2 2 2 2 2 2 2|1 1 1 1 1 1 1 1 1 1| |
; +---+-----------+-------+-------+-----------+---+---------------+
 
move 0x40000000,ccs
setf ixv
sfe
move ccs,r3
dumpr3 ; 0x4000c800
or.d 0x80000000,r3
move r3,ccs
 
setf pzv
sfe
move ccs,r3
dumpr3 ; 0xc3221800
 
setf xnc
sfe
move ccs,r3
dumpr3 ; 0xc8606400
 
; Clear Q, so we don't get S and Q at the same time when we set S.
lslq 1,r3
lsrq 1,r3
move r3,ccs
move ccs,r3
dumpr3 ; 0x48606400
 
or.w 0x300,r3
move r3,ccs
setf ui
sfe
move ccs,r3
dumpr3 ; 0x419d8260
 
quit
/asm/raw5.ms
0,0 → 1,23
; Checking read-after-write: write-then-nop-read 2 cycles.
#mach: crisv32
#output: Basic clock cycles, total @: 5\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 2\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "testutils.inc"
startnostack
.lcomm x,4
.lcomm y,4
move.d x,$r0
move.d y,$r1
move.d $r1,[$r0]
nop
move.d [$r1],$r2
break 15
/asm/moverdpc.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
startnostack
setf
move.d r5,pc
quit
/asm/andm.ms
0,0 → 1,90
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 2\n2\nffff\nffffffff\n50124400\nffff0002\n2\nfffff\nfedaff0f\n78134400\nffffff02\n2\nf02\n78134401\n78134400\n
 
.include "testutils.inc"
.data
x:
.dword 2,-1,0xffff,-1,0x5432f789
.word 2,-1,0xffff,0xff5f,0xf789
.byte 2,-1,0x5a,0x89,0
 
start
moveq -1,r3
move.d x,r5
and.d [r5+],r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
moveq 2,r3
and.d [r5],r3
test_move_cc 0 0 0 0
addq 4,r5
dumpr3 ; 2
 
move.d 0xffff,r3
and.d [r5+],r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
moveq -1,r3
and.d [r5+],r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d 0x78134452,r3
and.d [r5+],r3
test_move_cc 0 0 0 0
dumpr3 ; 50124400
 
moveq -1,r3
and.w [r5+],r3
test_move_cc 0 0 0 0
dumpr3 ; ffff0002
 
moveq 2,r3
and.w [r5+],r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xfffff,r3
and.w [r5],r3
test_move_cc 1 0 0 0
addq 2,r5
dumpr3 ; fffff
 
move.d 0xfedaffaf,r3
and.w [r5+],r3
test_move_cc 1 0 0 0
dumpr3 ; fedaff0f
 
move.d 0x78134452,r3
and.w [r5+],r3
test_move_cc 0 0 0 0
dumpr3 ; 78134400
 
moveq -1,r3
and.b [r5],r3
test_move_cc 0 0 0 0
addq 1,r5
dumpr3 ; ffffff02
 
moveq 2,r3
and.b [r5+],r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xfa7,r3
and.b [r5+],r3
test_move_cc 0 0 0 0
dumpr3 ; f02
 
move.d 0x78134453,r3
and.b [r5+],r3
test_move_cc 0 0 0 0
dumpr3 ; 78134401
 
and.b [r5],r3
test_move_cc 0 1 0 0
dumpr3 ; 78134400
 
quit
/asm/ccs-v32.ms
0,0 → 1,73
# mach: crisv32
# output: bf\n0\n80\n20\n10\n8\n4\n2\n1\n40\nfade040\n3ade0040\nfade040\n42\n
 
; Check flag settings.
 
.include "testutils.inc"
start
clear.d r3
setf pixnzvc ; Setting U(ser mode) would restrict tests of other flags.
move ccs,r3
dumpr3
 
clear.d r3
clearf puixnzvc
move ccs,r3
dumpr3
 
.macro testf BIT
clear.d r3
clearf puixnzvc
setf \BIT
move ccs,r3
dumpr3
.endm
 
testf p
testf i
testf x
testf n
testf z
testf v
testf c
testf u ; Can't test i-flag or clear u after this point.
 
.macro test_get_cc N Z V C
clearf znvc
move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),ccs
test_cc \N \Z \V \C
setf znvc
move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),ccs
test_cc \N \Z \V \C
move.d ((\N << 3)|(\Z << 2)|(\V << 1)|\C),r4
setf znvc
move r4,ccs
test_cc \N \Z \V \C
clearf znvc
move r4,ccs
test_cc \N \Z \V \C
.endm
 
test_get_cc 1 0 0 0
test_get_cc 0 1 0 0
test_get_cc 0 0 1 0
test_get_cc 0 0 0 1
 
; Test that the U bit sticks.
move 0x0fade000,ccs
move ccs,r3
dumpr3
 
; Check that the M and Q bits can't be set in user mode.
move 0xfade0000,ccs
move ccs,r3
dumpr3
 
move 0x0fade000,ccs
move ccs,r3
dumpr3
 
move.d 0x42,r3
dumpr3
 
quit
/asm/boundm.ms
0,0 → 1,105
# mach: crisv0 crisv3 crisv8 crisv10
# output: 2\n2\nffff\nffffffff\n5432f789\n2\nffff\n2\nffff\nffff\nf789\n2\n2\nff\nff\nff\n89\n0\n
 
.include "testutils.inc"
.data
x:
.dword 2,-1,0xffff,-1,0x5432f789
.word 2,0xffff,0xf789
.byte 2,0xff,0x89,0
 
start
move.d x,r5
 
moveq -1,r3
moveq 2,r4
bound.d [r5+],r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
moveq 2,r3
bound.d [r5],r3
test_move_cc 0 0 0 0
addq 4,r5
dumpr3 ; 2
 
move.d 0xffff,r3
bound.d [r5+],r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
moveq -1,r3
bound.d [r5+],r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d 0x78134452,r3
bound.d [r5+],r3
test_move_cc 0 0 0 0
dumpr3 ; 5432f789
 
moveq -1,r3
bound.w [r5+],r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
moveq -1,r3
bound.w [r5],r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
moveq 2,r3
bound.w [r5],r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xffff,r3
bound.w [r5],r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
move.d 0xfedaffff,r3
bound.w [r5+],r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
move.d 0x78134452,r3
bound.w [r5+],r3
test_move_cc 0 0 0 0
dumpr3 ; f789
 
moveq -1,r3
bound.b [r5+],r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
moveq 2,r3
bound.b [r5],r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
moveq -1,r3
bound.b [r5],r3
test_move_cc 0 0 0 0
dumpr3 ; ff
 
move.d 0xff,r3
bound.b [r5],r3
test_move_cc 0 0 0 0
dumpr3 ; ff
 
move.d 0xfeda49ff,r3
bound.b [r5+],r3
test_move_cc 0 0 0 0
dumpr3 ; ff
 
move.d 0x78134452,r3
bound.b [r5+],r3
test_move_cc 0 0 0 0
dumpr3 ; 89
 
bound.b [r5],r3
test_move_cc 0 1 0 0
dumpr3 ; 0
 
quit
/asm/break.ms
0,0 → 1,15
# mach: crisv3 crisv8 crisv10 crisv32
# sim: --trace-core=on
# ld: --section-start=.text=0
# output: read-2 exec:0x00000002 -> 0x05b0\nread-2 exec:0x00000004 -> 0xe93f\n
 
; First test: Must exit gracefully.
 
.include "testutils.inc"
 
; This first insn isn't executed (it's a filler); it would fail
; ungracefully if executed.
 
startnostack
setf
quit
/asm/movesmp.ms
0,0 → 1,28
# mach: crisv3 crisv8 crisv10
# output: bed0bed1\nabedab0d\nbed0bed1\n
 
# Test that move to and from special register and memory clears the
# "prefixed" bit.
 
.include "testutils.inc"
.data
w:
.dword 0
y:
.dword 0xbed0bed1
z:
.dword 0xabedab0d
 
start
x:
move.d y,r3
clear.d [w]
move.d [r3],r3
dumpr3 ; bed0bed1
move.d z,r3
move [w+4],srp
move.d [r3],r3
dumpr3 ; abedab0d
move srp,r3
dumpr3 ; bed0bed1
quit
/asm/option2.ms
0,0 → 1,5
#mach: crisv0 crisv3 crisv8 crisv10 crisv32
#sim: --sysroot=/non/exist/dir
#output: run: can't change directory to "/non/exist/dir"\n
#xerror:
.include "option1.ms"
/asm/raw10.ms
0,0 → 1,22
; Checking read-after-write: swrite-then-read 2 cycles.
#mach: crisv32
#output: Basic clock cycles, total @: 4\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 2\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "testutils.inc"
startnostack
.lcomm x,4
.lcomm y,4
move.d x,$r0
move.d y,$r1
clear.d [$r0]
move [$r1],$srp
break 15
/asm/movurpc.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
start
setf
movu.b r3,pc
quit
/asm/io5.ms
0,0 → 1,17
# mach: crisv32
# output: ce11d0c\n
 
; Check correct "pass" exit.
 
.include "testutils.inc"
start
move.d 0x0ce11d0c,$r3
dumpr3
moveq 1,$r9
moveq 0,$r10
break 13
move.d 0xbadc0de,$r3
dumpr3
0:
ba 0b
nop
/asm/msteppc1.ms
0,0 → 1,8
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\n
# output: program stopped with signal 5.\n
 
.include "testutils.inc"
start
mstep pc,r2
/asm/movmp.ms
0,0 → 1,127
# mach: crisv3 crisv8 crisv10 crisv32
# output: ffffff00\nffff0000\n0\nffffff00\nffff0000\n0\nffffff00\nffff0000\n0\nbb113344\n664433aa\ncc557788\nabcde012\nabcde000\n77880000\n0\n
 
# Test generic "move Ps,[]" and "move [],Pd" insns; the ones with
# functionality common to all models.
 
.include "testutils.inc"
start
 
.data
filler:
.byte 0xaa
.word 0x4433
.dword 0x55778866
.byte 0xcc
 
.text
; Test that writing to zero-registers is a nop
.if 0
; We used to just ignore the writes, but now an error is emitted. We
; keep the test-code but disabled, in case we need to change this again.
move 0xaa,p0
move 0x4433,p4
move 0x55774433,p8
.endif
 
moveq -1,r3
setf zcvn
clear.b r3
test_cc 1 1 1 1
dumpr3
 
moveq -1,r3
clearf zcvn
clear.w r3
test_cc 0 0 0 0
dumpr3
 
moveq -1,r3
clear.d r3
dumpr3
 
; "Write" using ordinary memory references too.
.if 0 ; See ".if 0" above.
move.d filler,r6
move [r6],p0
move [r6],p4
move [r6],p8
.endif
 
moveq -1,r3
clear.b r3
dumpr3
 
moveq -1,r3
clear.w r3
dumpr3
 
moveq -1,r3
clear.d r3
dumpr3
 
; And postincremented.
.if 0 ; See ".if 0" above.
move [r6+],p0
move [r6+],p4
move [r6+],p8
.endif
 
moveq -1,r3
clear.b r3
dumpr3
 
moveq -1,r3
clear.w r3
dumpr3
 
moveq -1,r3
clear.d r3
dumpr3
 
; Now see that we can write to the registers too.
 
; [PC+]
move.d filler,r9
move 0xbb113344,srp
move srp,r3
dumpr3
 
; [R+]
move [r9+],srp
move srp,r3
dumpr3
 
; [R]
move [r9],srp
move srp,r3
dumpr3
 
; And check writing to memory, clear and srp.
 
move.d filler,r9
move 0xabcde012,srp
setf zcvn
move srp,[r9+]
test_cc 1 1 1 1
subq 4,r9
move.d [r9],r3
dumpr3
 
clearf zcvn
clear.b [r9]
test_cc 0 0 0 0
move.d [r9],r3
dumpr3
 
addq 2,r9
clear.w [r9+]
subq 2,r9
move.d [r9],r3
dumpr3
 
clear.d [r9]
move.d [r9],r3
dumpr3
 
quit
/asm/fidxd.ms
0,0 → 1,9
# mach: crisv32
# xerror:
# output: FIDXD isn't implemented\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
start
fidxd [r3]
 
quit
/asm/nopv32t3.ms
0,0 → 1,13
#mach: crisv10 crisv32
#output: Schedulable clock cycles, total @: 5\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=schedulable
.include "nopv32t.ms"
/asm/lsr.ms
0,0 → 1,217
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: ffffffff\n1\n1\n1ffff\n5a67f\n1\n0\n0\n3699fc67\nffffffff\n1\n1\n1ffff\n5a67f\nda670000\nda670000\nda670000\nda673c67\nffffffff\nffff7fff\n1\nffff0000\nffff0001\n5a67000f\nda67f100\nda67f100\nda67f100\nda67f127\nffffffff\nffffff7f\n1\nffffff00\nffffff00\nffffff01\n5a67f100\n5a67f109\n
 
.include "testutils.inc"
start
moveq -1,r3
lsrq 0,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq 2,r3
lsrq 1,r3
test_move_cc 0 0 0 0
dumpr3 ; 1
 
moveq -1,r3
lsrq 31,r3
test_move_cc 0 0 0 0
dumpr3 ; 1
 
moveq -1,r3
lsrq 15,r3
test_move_cc 0 0 0 0
dumpr3 ; 1ffff
 
move.d 0x5a67f19f,r3
lsrq 12,r3
test_move_cc 0 0 0 0
dumpr3 ; 5a67f
 
move.d 0xda67f19f,r3
move.d 31,r4
lsr.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 1
 
move.d 0xda67f19f,r3
move.d 32,r4
lsr.d r4,r3
test_move_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0xda67f19f,r3
move.d 33,r4
lsr.d r4,r3
test_move_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0xda67f19f,r3
move.d 66,r4
lsr.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 3699fc67
 
moveq -1,r3
moveq 0,r4
lsr.d r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq 2,r3
moveq 1,r4
lsr.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 1
 
moveq -1,r3
moveq 31,r4
lsr.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 1
 
moveq -1,r3
moveq 15,r4
lsr.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 1ffff
 
move.d 0x5a67f19f,r3
moveq 12,r4
lsr.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 5a67f
 
move.d 0xda67f19f,r3
move.d 31,r4
lsr.w r4,r3
test_move_cc 0 1 0 0
dumpr3 ; da670000
 
move.d 0xda67f19f,r3
move.d 32,r4
lsr.w r4,r3
test_move_cc 0 1 0 0
dumpr3 ; da670000
 
move.d 0xda67f19f,r3
move.d 33,r4
lsr.w r4,r3
test_move_cc 0 1 0 0
dumpr3 ; da670000
 
move.d 0xda67f19f,r3
move.d 66,r4
lsr.w r4,r3
test_move_cc 0 0 0 0
dumpr3 ; da673c67
 
moveq -1,r3
moveq 0,r4
lsr.w r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq -1,r3
moveq 1,r4
lsr.w r4,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff7fff
 
moveq 2,r3
moveq 1,r4
lsr.w r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 1
 
moveq -1,r3
moveq 31,r4
lsr.w r4,r3
test_move_cc 0 1 0 0
dumpr3 ; ffff0000
 
moveq -1,r3
moveq 15,r4
lsr.w r4,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff0001
 
move.d 0x5a67f19f,r3
moveq 12,r4
lsr.w r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 5a67000f
 
move.d 0xda67f19f,r3
move.d 31,r4
lsr.b r4,r3
test_move_cc 0 1 0 0
dumpr3 ; da67f100
 
move.d 0xda67f19f,r3
move.d 32,r4
lsr.b r4,r3
test_move_cc 0 1 0 0
dumpr3 ; da67f100
 
move.d 0xda67f19f,r3
move.d 33,r4
lsr.b r4,r3
test_move_cc 0 1 0 0
dumpr3 ; da67f100
 
move.d 0xda67f19f,r3
move.d 66,r4
lsr.b r4,r3
test_move_cc 0 0 0 0
dumpr3 ; da67f127
 
moveq -1,r3
moveq 0,r4
lsr.b r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq -1,r3
moveq 1,r4
lsr.b r4,r3
test_move_cc 0 0 0 0
dumpr3 ; ffffff7f
 
moveq 2,r3
moveq 1,r4
lsr.b r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 1
 
moveq -1,r3
moveq 31,r4
lsr.b r4,r3
test_move_cc 0 1 0 0
dumpr3 ; ffffff00
 
moveq -1,r3
moveq 15,r4
lsr.b r4,r3
test_move_cc 0 1 0 0
dumpr3 ; ffffff00
 
moveq -1,r3
moveq 7,r4
lsr.b r4,r3
test_move_cc 0 0 0 0
dumpr3 ; ffffff01
 
move.d 0x5a67f19f,r3
moveq 12,r4
lsr.b r4,r3
test_move_cc 0 1 0 0
dumpr3 ; 5a67f100
 
move.d 0x5a67f19f,r3
moveq 4,r4
lsr.b r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 5a67f109
 
quit
/asm/not.ms
0,0 → 1,31
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: fffffffe\nfffffffd\nffff0f00\n0\n87ecbbad\n
 
.include "testutils.inc"
start
moveq 1,r3
not r3
test_move_cc 1 0 0 0
dumpr3 ; fffffffe
 
moveq 2,r3
not r3
test_move_cc 1 0 0 0
dumpr3 ; fffffffd
 
move.d 0xf0ff,r3
not r3
test_move_cc 1 0 0 0
dumpr3 ; ffff0f00
 
moveq -1,r3
not r3
test_move_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0x78134452,r3
not r3
test_move_cc 1 0 0 0
dumpr3 ; 87ecbbad
 
quit
/asm/opterr5.ms
0,0 → 1,7
# mach: crisv3 crisv8 crisv10 crisv32
# xerror:
# output: Invalid option [`']--cris-program-offset=x'\n
# sim: --cris-program-offset=x
.include "nopv32t.ms"
 
; Check that we recognize wrong usage of the --cris-program-offset option.
/asm/x5-v10.ms
0,0 → 1,9
#mach: crisv10
#ld: --section-start=.text=0
#sim: --cris-trace=basic
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n
#output: 8 0 0 0 0 0 14 0 0 0 0 0 0 0 0 * ixnzvc 2\n
#output: a 0 0 0 0 1 14 0 0 0 0 0 0 0 0 * ixnzvc 2\n
#output: c 0 0 0 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 2\n
#output: e 0 0 2 1 1 18 0 0 0 0 0 0 0 0 * ixnzvc 2\n
.include "tmemv10.ms"
/asm/orq.ms
0,0 → 1,41
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 3\n3\nffffffff\nffffffff\n1f\nffffffe0\n7813445e\n
 
.include "testutils.inc"
start
moveq 1,r3
orq 2,r3
test_move_cc 0 0 0 0
dumpr3 ; 3
 
moveq 2,r3
orq 1,r3
test_move_cc 0 0 0 0
dumpr3 ; 3
 
move.d 0xf0ff,r3
orq -1,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq 0,r3
orq -1,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq 0,r3
orq 31,r3
test_move_cc 0 0 0 0
dumpr3 ; 1f
 
moveq 0,r3
orq -32,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffe0
 
move.d 0x78134452,r3
orq 12,r3
test_move_cc 0 0 0 0
dumpr3 ; 7813445e
 
quit
/asm/x3-v32.ms
0,0 → 1,10
#mach: crisv32
#ld: --section-start=.text=0
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: a 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 12 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 1e 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#sim: --cris-trace=basic
 
.include "tjsrcv10.ms"
/asm/bas.ms
0,0 → 1,102
# mach: crisv32
# output: 0\n0\n0\nfb349abc\n0\n12124243\n0\n0\neab5baad\n0\nefb37832\n
 
.include "testutils.inc"
start
x:
setf zncv
bsr 0f
nop
0:
test_cc 1 1 1 1
move srp,r3
sub.d 0b,r3
dumpr3
 
bas 1f,mof
moveq 0,r0
6:
nop
quit
 
2:
move srp,r3
sub.d 3f,r3
dumpr3
move srp,r4
subq 4,r4
move.d [r4],r3
dumpr3
 
basc 4f,mof
nop
.dword 0x12124243
7:
nop
quit
 
8:
move mof,r3
sub.d 7f,r3
dumpr3
 
move mof,r4
subq 4,r4
move.d [r4],r3
dumpr3
 
jasc 9f,mof
nop
.dword 0xefb37832
0:
quit
 
quit
9:
move mof,r3
sub.d 0b,r3
dumpr3
 
move mof,r4
subq 4,r4
move.d [r4],r3
dumpr3
 
quit
 
4:
move mof,r3
sub.d 7b,r3
dumpr3
move mof,r4
subq 4,r4
move.d [r4],r3
dumpr3
basc 5f,bz
moveq 0,r3
.dword 0x7634aeba
quit
 
.space 32770,0
1:
move mof,r3
sub.d 6b,r3
dumpr3
 
bsrc 2b
nop
.dword 0xfb349abc
3:
 
quit
 
5:
move mof,r3
sub.d 7b,r3
dumpr3
move.d 8b,r6
jasc r6,mof
nop
.dword 0xeab5baad
7:
quit
/asm/neg.ms
0,0 → 1,102
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: ffffffff\nffffffff\n0\n80000000\n1\nba987655\nffff\nffff\n0\n89ab8000\nffff0001\n45677655\nff\nff\n0\n89abae80\nffffff01\n45678955\n
 
.include "testutils.inc"
start
moveq 0,r3
moveq 1,r4
neg.d r4,r3
test_cc 1 0 0 1
dumpr3 ; ffffffff
 
moveq 1,r3
moveq 0,r4
neg.d r3,r3
test_cc 1 0 0 1
dumpr3 ; ffffffff
 
moveq 0,r3
neg.d r3,r3
test_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0x80000000,r3
neg.d r3,r3
test_cc 1 0 1 1
dumpr3 ; 80000000
 
moveq -1,r3
neg.d r3,r3
test_cc 0 0 0 1
dumpr3 ; 1
 
move.d 0x456789ab,r3
neg.d r3,r3
test_cc 1 0 0 1
dumpr3 ; ba987655
 
moveq 0,r3
moveq 1,r4
neg.w r4,r3
test_cc 1 0 0 1
dumpr3 ; ffff
 
moveq 1,r3
moveq 0,r4
neg.w r3,r3
test_cc 1 0 0 1
dumpr3 ; ffff
 
moveq 0,r3
neg.w r3,r3
test_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0x89ab8000,r3
neg.w r3,r3
test_cc 1 0 1 1
dumpr3 ; 89ab8000
 
moveq -1,r3
neg.w r3,r3
test_cc 0 0 0 1
dumpr3 ; ffff0001
 
move.d 0x456789ab,r3
neg.w r3,r3
test_cc 0 0 0 1
dumpr3 ; 45677655
 
moveq 0,r3
moveq 1,r4
neg.b r4,r3
test_cc 1 0 0 1
dumpr3 ; ff
 
moveq 1,r3
moveq 0,r4
neg.b r3,r3
test_cc 1 0 0 1
dumpr3 ; ff
 
moveq 0,r3
neg.b r3,r3
test_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0x89abae80,r3
neg.b r3,r3
test_cc 1 0 1 1
dumpr3 ; 89abae80
 
moveq -1,r3
neg.b r3,r3
test_cc 0 0 0 1
dumpr3 ; ffffff01
 
move.d 0x456789ab,r3
neg.b r3,r3
test_cc 0 0 0 1
dumpr3 ; 45678955
 
quit
/asm/movscpc.ms
0,0 → 1,13
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
start
movs.b 0x42,pc
dumpr3
 
movs.w 0x4321,pc
dumpr3
 
quit
/asm/rfg.ms
0,0 → 1,9
# mach: crisv32
# xerror:
# output: RFG isn't implemented\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
start
rfg
 
quit
/asm/raw8.ms
0,0 → 1,26
; Checking read-after-write: movemwrite-then-nop-read 2 cycles.
#mach: crisv32
#ld: --section-start=.text=0
#output: Basic clock cycles, total @: 7\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 2\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 1\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "testutils.inc"
startnostack
.lcomm x,4*11
.lcomm y,4
move.d x,$r0
move.d y,$r1
nop
nop
movem $r10,[$r0]
nop
move.d [$r1],$r2
break 15
/asm/cmpc.ms
0,0 → 1,86
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: ffffffff\n2\nffff\nffffffff\n78134452\nffffffff\n2\nffff\nfedaffff\n78134452\nffffffff\n2\nff\nfeda49ff\n78134452\n85649282\n
 
.include "testutils.inc"
start
moveq -1,r3
cmp.d -2,r3
test_cc 0 0 0 0
dumpr3 ; ffffffff
 
moveq 2,r3
cmp.d 1,r3
test_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xffff,r3
cmp.d -0xffff,r3
test_cc 0 0 0 1
dumpr3 ; ffff
 
moveq -1,r3
cmp.d 1,r3
test_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d 0x78134452,r3
cmp.d -0x5432f789,r3
test_cc 1 0 1 1
dumpr3 ; 78134452
 
moveq -1,r3
cmp.w -2,r3
test_cc 0 0 0 0
dumpr3 ; ffffffff
 
moveq 2,r3
cmp.w 1,r3
test_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xffff,r3
cmp.w 1,r3
test_cc 1 0 0 0
dumpr3 ; ffff
 
move.d 0xfedaffff,r3
cmp.w 1,r3
test_cc 1 0 0 0
dumpr3 ; fedaffff
 
move.d 0x78134452,r3
cmp.w 0x877,r3
test_cc 0 0 0 0
dumpr3 ; 78134452
 
moveq -1,r3
cmp.b -2,r3
test_cc 0 0 0 0
dumpr3 ; ffffffff
 
moveq 2,r3
cmp.b 1,r3
test_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xff,r3
cmp.b 1,r3
test_cc 1 0 0 0
dumpr3 ; ff
 
move.d 0xfeda49ff,r3
cmp.b 1,r3
test_cc 1 0 0 0
dumpr3 ; feda49ff
 
move.d 0x78134452,r3
cmp.b 0x77,r3
test_cc 1 0 0 1
dumpr3 ; 78134452
 
move.d 0x85649282,r3
cmp.b 0x82,r3
test_cc 0 1 0 0
dumpr3 ; 85649282
 
quit
/asm/ba.ms
0,0 → 1,93
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: a\n
 
.include "testutils.inc"
 
.if ..asm.arch.cris.v32
.set smalloffset,0
.set largeoffset,0
.else
.set smalloffset,2
.set largeoffset,4
.endif
 
start
moveq 0,r3
 
; Short forward branch.
ba 0f
addq 1,r3
fail
 
; Max short forward branch.
1:
ba 2f
addq 1,r3
fail
 
; Short backward branch.
0:
ba 1b
addq 1,r3
fail
 
.space 254-2+smalloffset+1b-.,0
moveq 0,r3
 
2:
; Transit branch (long).
ba 3f
addq 1,r3
fail
 
moveq 0,r3
4:
; Long forward branch.
ba 5f
addq 1,r3
fail
 
.space 256-2-smalloffset+4b-.,0
 
moveq 0,r3
 
; Max short backward branch.
3:
ba 4b
addq 1,r3
fail
 
5:
; Max long forward branch.
ba 6f
addq 1,r3
fail
 
.space 32766+largeoffset-2+5b-.,0
 
moveq 0,r3
6:
; Transit branch.
ba 7f
addq 1,r3
fail
 
moveq 0,r3
9:
dumpr3
quit
 
; Transit branch.
moveq 0,r3
7:
ba 8f
addq 1,r3
fail
 
.space 32768-largeoffset+9b-.,0
 
8:
; Max long backward branch.
ba 9b
addq 1,r3
fail
/asm/asr.ms
0,0 → 1,228
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: ffffffff\n1\nffffffff\nffffffff\n5a67f\nffffffff\nffffffff\nffffffff\nf699fc67\nffffffff\n1\nffffffff\nffffffff\n5a67f\nda67ffff\nda67ffff\nda67ffff\nda67fc67\nffffffff\nffffffff\n1\nffffffff\nffffffff\n5a670007\nda67f1ff\nda67f1ff\nda67f1ff\nda67f1e7\nffffffff\nffffffff\n1\nffffffff\nffffffff\nffffffff\n5a67f1ff\n5a67f1f9\n0\n5a670000\n
 
.include "testutils.inc"
start
moveq -1,r3
asrq 0,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq 2,r3
asrq 1,r3
test_move_cc 0 0 0 0
dumpr3 ; 1
 
moveq -1,r3
asrq 31,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq -1,r3
asrq 15,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d 0x5a67f19f,r3
asrq 12,r3
test_move_cc 0 0 0 0
dumpr3 ; 5a67f
 
move.d 0xda67f19f,r3
move.d 31,r4
asr.d r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d 0xda67f19f,r3
move.d 32,r4
asr.d r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d 0xda67f19f,r3
move.d 33,r4
asr.d r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d 0xda67f19f,r3
move.d 66,r4
asr.d r4,r3
test_move_cc 1 0 0 0
dumpr3 ; f699fc67
 
moveq -1,r3
moveq 0,r4
asr.d r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq 2,r3
moveq 1,r4
asr.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 1
 
moveq -1,r3
moveq 31,r4
asr.d r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq -1,r3
moveq 15,r4
asr.d r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d 0x5a67f19f,r3
moveq 12,r4
asr.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 5a67f
 
move.d 0xda67f19f,r3
move.d 31,r4
asr.w r4,r3
test_move_cc 1 0 0 0
dumpr3 ; da67ffff
 
move.d 0xda67f19f,r3
move.d 32,r4
asr.w r4,r3
test_move_cc 1 0 0 0
dumpr3 ; da67ffff
 
move.d 0xda67f19f,r3
move.d 33,r4
asr.w r4,r3
test_move_cc 1 0 0 0
dumpr3 ; da67ffff
 
move.d 0xda67f19f,r3
move.d 66,r4
asr.w r4,r3
test_move_cc 1 0 0 0
dumpr3 ; da67fc67
 
moveq -1,r3
moveq 0,r4
asr.w r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq -1,r3
moveq 1,r4
asr.w r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq 2,r3
moveq 1,r4
asr.w r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 1
 
moveq -1,r3
moveq 31,r4
asr.w r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq -1,r3
moveq 15,r4
asr.w r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d 0x5a67719f,r3
moveq 12,r4
asr.w r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 5a670007
 
move.d 0xda67f19f,r3
move.d 31,r4
asr.b r4,r3
test_move_cc 1 0 0 0
dumpr3 ; da67f1ff
 
move.d 0xda67f19f,r3
move.d 32,r4
asr.b r4,r3
test_move_cc 1 0 0 0
dumpr3 ; da67f1ff
 
move.d 0xda67f19f,r3
move.d 33,r4
asr.b r4,r3
test_move_cc 1 0 0 0
dumpr3 ; da67f1ff
 
move.d 0xda67f19f,r3
move.d 66,r4
asr.b r4,r3
test_move_cc 1 0 0 0
dumpr3 ; da67f1e7
 
moveq -1,r3
moveq 0,r4
asr.b r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq -1,r3
moveq 1,r4
asr.b r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq 2,r3
moveq 1,r4
asr.b r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 1
 
moveq -1,r3
moveq 31,r4
asr.b r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq -1,r3
moveq 15,r4
asr.b r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq -1,r3
moveq 7,r4
asr.b r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d 0x5a67f19f,r3
moveq 12,r4
asr.b r4,r3
test_move_cc 1 0 0 0
dumpr3 ; 5a67f1ff
 
move.d 0x5a67f19f,r3
moveq 4,r4
asr.b r4,r3
test_move_cc 1 0 0 0
dumpr3 ; 5a67f1f9
 
move.d 0x5a67f19f,r3
asrq 31,r3
test_move_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0x5a67419f,r3
moveq 16,r4
asr.w r4,r3
test_move_cc 0 1 0 0
dumpr3 ; 5a670000
 
quit
/asm/movpmv10.ms
0,0 → 1,35
# mach: crisv10
# output: 1122330a\nbb113344\naa557711\n
 
# Test v10-specific special registers. FIXME: ccr, irp, bar, brp, usp.
 
.include "testutils.inc"
start
.data
store:
.dword 0x11223344
.dword 0x77665544
 
.text
moveq -1,r3
move.d store,r4
clearf zcvn
move vr,[r4]
test_cc 0 0 0 0
move [r4+],mof
move mof,r3
dumpr3
 
moveq -1,r3
move 0xbb113344,mof
move mof,r3
dumpr3
 
move 0xaa557711,mof
setf zcvn
move mof,[r4]
test_cc 1 1 1 1
move.d [r4],r3
dumpr3
quit
/asm/jumppv32.ms
0,0 → 1,28
# mach: crisv32
# output: 2222\n
 
# Test that jump Pd works.
 
.include "testutils.inc"
start
x:
setf zvnc
move 0f,srp
test_cc 1 1 1 1
jump srp
nop
quit
 
0:
test_cc 1 1 1 1
move 1f,mof
jump mof
nop
quit
 
.space 32768,0
quit
1:
move.d 0x2222,r3
dumpr3
quit
/asm/movmp8.ms
0,0 → 1,33
# mach: crisv3 crisv8 crisv10
 
# Make sure that "move [$sp=$sp+16],$p8" works; used in Linux.
 
.include "testutils.inc"
startnostack
move.d x,$sp
moveq 0,$r3
move [$sp=$sp+16],$p8
; Z not changed.
bne 0f
nop
cmp.d x+16,$sp
bne 0f
nop
move $p8,$r3
; Z not changed.
bne 0f
; P8 still 0.
test.d $r3
bne 0f
nop
pass
0:
fail
 
.data
x:
.dword 0xffffffff
.dword 0xffffffff
.dword 0xffffffff
.dword 0xffffffff
.dword 0xffffffff
/asm/bccb.ms
0,0 → 1,181
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 1c\n
 
.include "testutils.inc"
start
moveq 0,r3
 
clearf nzvc
setf nzv
bcc 0f
addq 1,r3
fail
 
0:
clearf nzvc
setf nzv
bcs dofail
addq 1,r3
 
clearf nzvc
setf ncv
bne 1f
addq 1,r3
 
dofail:
fail
 
1:
clearf nzvc
setf ncv
beq dofail
addq 1,r3
 
clearf nzvc
setf ncz
bvc 2f
addq 1,r3
fail
 
2:
clearf nzvc
setf ncz
bvs dofail
addq 1,r3
 
clearf nzvc
setf vcz
bpl 3f
addq 1,r3
fail
 
3:
clearf nzvc
setf vcz
bmi dofail
addq 1,r3
 
clearf nzvc
setf nv
bls dofail
addq 1,r3
 
clearf nzvc
setf nv
bhi 4f
addq 1,r3
fail
 
4:
clearf nzvc
setf zc
bge 5f
addq 1,r3
fail
 
5:
clearf nzvc
setf zc
blt dofail
addq 1,r3
 
clearf nzvc
setf c
bgt 6f
addq 1,r3
fail
 
6:
clearf nzvc
setf c
ble dofail
addq 1,r3
 
;;;;;;;;;;
 
setf nzvc
clearf nzv
bcc dofail
addq 1,r3
 
setf nzvc
clearf nzv
bcs 0f
addq 1,r3
fail
 
0:
setf nzvc
clearf ncv
bne dofail
addq 1,r3
 
setf nzvc
clearf ncv
beq 1f
addq 1,r3
fail
 
1:
setf nzvc
clearf ncz
bvc dofail
addq 1,r3
 
setf nzvc
clearf ncz
bvs 2f
addq 1,r3
fail
 
2:
setf nzvc
clearf vcz
bpl dofail
addq 1,r3
 
setf nzvc
clearf vcz
bmi 3f
addq 1,r3
fail
 
3:
setf nzvc
clearf nv
bls 4f
addq 1,r3
fail
 
4:
setf nzvc
clearf nv
bhi dofail
addq 1,r3
 
setf zvc
clearf nzc
bge dofail
addq 1,r3
 
setf nzc
clearf vzc
blt 5f
addq 1,r3
fail
 
5:
setf nzvc
clearf c
bgt dofail
addq 1,r3
 
setf nzvc
clearf c
ble 6f
addq 1,r3
fail
 
6:
dumpr3
quit
/asm/movrss.ms
0,0 → 1,8
# mach: crisv32
# xerror:
# output: Write to support register is unimplemented\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
start
move R3,S0
 
/asm/subc.ms
0,0 → 1,86
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n85649200\n
 
.include "testutils.inc"
start
moveq -1,r3
sub.d -2,r3
test_cc 0 0 0 0
dumpr3 ; 1
 
moveq 2,r3
sub.d 1,r3
test_cc 0 0 0 0
dumpr3 ; 1
 
move.d 0xffff,r3
sub.d -0xffff,r3
test_cc 0 0 0 1
dumpr3 ; 1fffe
 
moveq -1,r3
sub.d 1,r3
test_cc 1 0 0 0
dumpr3 ; fffffffe
 
move.d 0x78134452,r3
sub.d -0x5432f789,r3
test_cc 1 0 1 1
dumpr3 ; cc463bdb
 
moveq -1,r3
sub.w -2,r3
test_cc 0 0 0 0
dumpr3 ; ffff0001
 
moveq 2,r3
sub.w 1,r3
test_cc 0 0 0 0
dumpr3 ; 1
 
move.d 0xffff,r3
sub.w 1,r3
test_cc 1 0 0 0
dumpr3 ; fffe
 
move.d 0xfedaffff,r3
sub.w 1,r3
test_cc 1 0 0 0
dumpr3 ; fedafffe
 
move.d 0x78134452,r3
sub.w 0x877,r3
test_cc 0 0 0 0
dumpr3 ; 78133bdb
 
moveq -1,r3
sub.b -2,r3
test_cc 0 0 0 0
dumpr3 ; ffffff01
 
moveq 2,r3
sub.b 1,r3
test_cc 0 0 0 0
dumpr3 ; 1
 
move.d 0xff,r3
sub.b 1,r3
test_cc 1 0 0 0
dumpr3 ; fe
 
move.d 0xfeda49ff,r3
sub.b 1,r3
test_cc 1 0 0 0
dumpr3 ; feda49fe
 
move.d 0x78134452,r3
sub.b 0x77,r3
test_cc 1 0 0 1
dumpr3 ; 781344db
 
move.d 0x85649282,r3
sub.b 0x82,r3
test_cc 0 1 0 0
dumpr3 ; 85649200
 
quit
/asm/bare3.ms
0,0 → 1,41
# mach: crisv32
# ld: -N --oformat binary --section-start=.text=0x10000000
# sim: --architecture crisv32 --target binary --cris-program-offset=0x10000000 --cris-start-address=0x10000040 --cris-naked --memory-region 0x10000000,0x1000
.include "testutils.inc"
 
; Test that we can load a binary program at a non-zero address.
; Also serves to exercise the --cris-program-offset and
; --cris-start-address options.
 
; Make sure starting at the first address does fail.
fail
 
; ...and that we know an offset we can jump for it to work, and all we
; have to assume is that "fail" takes no more than 64 bytes.
.p2align 6
ba _start
nop
 
;
start
x:
 
; Make sure we're loaded at the linked address. Since we're re-used
; in other tests, we have to provide for non-v32 as well.
.if ..asm.arch.cris.v32
lapcq .,$r0
.else
move.d $pc,$r0
subq .-x,$r0
.endif
 
cmp.d x,$r0
bne y
nop
pass
y:
fail
 
; Make sure we have enough contents for the mapping.
.data
.fill 4096,1,0
/asm/tmemv32.ms
0,0 → 1,14
#mach: crisv32
#output: Basic clock cycles, total @: 4\n
#output: Memory source stall cycles: 1\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
 
.include "tmemv10.ms"
/asm/subqpc.ms
0,0 → 1,8
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
start
subq 31,pc
 
/asm/raw13.ms
0,0 → 1,22
; Checking read-after-write: write-MOF-then-read unaffected.
#mach: crisv32
#output: Basic clock cycles, total @: 4\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "testutils.inc"
startnostack
.lcomm x,4
.lcomm y,4
move.d x,$r0
move.d y,$r1
move [$r0],$mof
move [$r1],$srp
break 15
/asm/asm.exp
0,0 → 1,45
# Copyright (C) 2005, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
 
# Miscellaneous CRIS simulator testcases in assembly code.
 
if [istarget cris*-*-*] {
global ASFLAGS_FOR_TARGET
# All machines we test and the corresponding assembler option. Needs
# update if we build the simulator for crisv0 crisv3 and crisv8 too.
 
set combos {{"crisv10" "--march=v10 --no-mul-bug-abort"}
{"crisv32" "--march=v32"}}
 
# We need to pass different assembler flags for each machine.
# Specifying it here rather than adding a specifier to each and every
# test-file is preferrable.
 
foreach combo $combos {
set mach [lindex $combo 0]
set ASFLAGS_FOR_TARGET "[lindex $combo 1]"
 
# The .ms suffix is for "miscellaneous .s".
foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] {
# If we're only testing specific files and this isn't one of them,
# skip it.
if ![runtest_file_p $runtests $src] {
continue
}
 
run_sim_test $src $mach
}
}
}
/asm/io8.ms
0,0 → 1,21
# mach: crisv32
# ld: --section-start=.text=0
# xerror:
# output: b1e\n
# output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n
# output: program stopped with signal 11.\n
 
; Check invalid access valid with --cris-900000xx.
; "FAIL" area.
 
.include "testutils.inc"
start
move.d 0xb1e,$r3
dumpr3
move.d 0x90000008,$acr
move.d $acr,[$acr]
move.d 0xbadc0de,$r3
dumpr3
0:
ba 0b
nop
/asm/tmvrmv32.ms
0,0 → 1,14
#mach: crisv32
#output: Basic clock cycles, total @: 14\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 3\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
 
.include "tmvrmv10.ms"
/asm/x2-v32.ms
0,0 → 1,59
#mach: crisv32
#ld: --section-start=.text=0
#sim: --cris-trace=basic
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n
#output: c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n
#output: 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n
#output: 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 16 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 18 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 1a 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 16 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 18 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 1a 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 16 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 18 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 1a 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 16 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 18 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 1a 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n
#output: 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n
#output: 1a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n
#output: 1c ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n
#output: 1e ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n
#output: 20 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n
#output: 22 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n
#output: 26 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n
#output: 230 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n
#output: 232 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n
#output: 236 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n
#output: 440 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n
#output: 442 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n
#output: 446 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n
#output: 650 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n
#output: 654 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1 0\n
#output: 442 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 446 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 650 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 654 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 442 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 446 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 650 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 654 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 442 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 446 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 650 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 654 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 442 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n
#output: 446 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n
#output: 650 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n
#output: 654 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1 0\n
#output: 656 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n
#output: 658 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n
#output: 65a ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1 0\n
.include "tb.ms"
/asm/addi.ms
0,0 → 1,57
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 0\n1\n2\n4\nbe02460f\n69d035a6\nc16c14d4\n
 
.include "testutils.inc"
start
moveq 0,r3
moveq 0,r4
clearf zcvn
addi r4.b,r3
test_cc 0 0 0 0
dumpr3 ; 0
 
moveq 0,r3
moveq 1,r4
setf zcvn
addi r4.b,r3
test_cc 1 1 1 1
dumpr3 ; 1
 
moveq 0,r3
moveq 1,r4
setf cv
clearf zn
addi r4.w,r3
test_cc 0 0 1 1
dumpr3 ; 2
 
moveq 0,r3
moveq 1,r4
clearf cv
setf zn
addi r4.d,r3
test_cc 1 1 0 0
dumpr3 ; 4
 
move.d 0x12345678,r3
move.d 0xabcdef97,r4
clearf cn
setf zv
addi r4.b,r3
test_cc 0 1 1 0
dumpr3 ; be02460f
 
move.d 0x12345678,r3
move.d 0xabcdef97,r4
setf cn
clearf zv
addi r4.w,r3
test_cc 1 0 0 1
dumpr3 ; 69d035a6
 
move.d 0x12345678,r3
move.d 0xabcdef97,r4
addi r4.d,r3
dumpr3 ; c16c14d4
 
quit
/asm/addxr.ms
0,0 → 1,93
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 1\n1\n101\n10001\n100fe\n1fffe\nfffe\nfffe\nfffffffe\nfe\nfffffffe\n781344db\n781343db\n78143bdb\n78133bdb\n800000ed\n0\n
 
.include "testutils.inc"
start
moveq 2,r3
move.d 0xff,r4
adds.b r4,r3
dumpr3 ; 1
 
moveq 2,r3
move.d 0xffff,r4
adds.w r4,r3
dumpr3 ; 1
 
moveq 2,r3
move.d 0xffff,r4
addu.b r4,r3
dumpr3 ; 101
 
moveq 2,r3
move.d 0xffffffff,r4
addu.w r4,r3
dumpr3 ; 10001
 
move.d 0xffff,r3
move.d 0xffffffff,r4
addu.b r4,r3
dumpr3 ; 100fe
 
move.d 0xffff,r3
move.d 0xffffffff,r4
addu.w r4,r3
dumpr3 ; 1fffe
 
move.d 0xffff,r3
move.d 0xff,r4
adds.b r4,r3
dumpr3 ; fffe
 
move.d 0xffff,r4
move.d r4,r3
adds.w r4,r3
dumpr3 ; fffe
 
moveq -1,r3
move.d 0xff,r4
adds.b r4,r3
dumpr3 ; fffffffe
 
moveq -1,r3
move.d 0xff,r4
adds.w r4,r3
dumpr3 ; fe
 
moveq -1,r3
move.d 0xffff,r4
adds.w r4,r3
dumpr3 ; fffffffe
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
addu.b r4,r3
dumpr3 ; 781344db
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
adds.b r4,r3
dumpr3 ; 781343db
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
addu.w r4,r3
dumpr3 ; 78143bdb
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
adds.w r4,r3
dumpr3 ; 78133bdb
 
move.d 0x7fffffee,r3
move.d 0xff,r4
addu.b r4,r3
test_cc 1 0 1 0
dumpr3 ; 800000ed
 
move.d 0x1,r3
move.d 0xffff,r4
adds.w r4,r3
test_cc 0 1 0 1
dumpr3 ; 0
 
quit
/asm/tmvm2.ms
0,0 → 1,351
#mach: crisv32
#output: Basic clock cycles, total @: *\n
#output: Memory source stall cycles: 82\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 6\n
#output: Movem destination stall cycles: 880\n
#output: Movem address stall cycles: 4\n
#output: Multiplication source stall cycles: 18\n
#output: Jump source stall cycles: 6\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
 
.include "testutils.inc"
 
; Macros for testing correctness of movem destination stall
; cycles for various insn types. Beware: macro parameters can
; be comma or space-delimited. There are problems (i.e. bugs)
; with using space-delimited operands and operands with
; non-alphanumeric characters, like "[]-." so use comma for
; them. Lots of trouble passing empty parameters and parameters
; with comma. Ugh. FIXME: Report bugs, fix bugs, fix other
; shortcomings, fix that darn old macro-parameter-in-string.
 
; Helper macro. Unfortunately I find no cleaner way to unify
; one and two-operand cases, the main problem being the comma
; operand delimiter clashing with macro operand delimiter.
.macro t_S_x_y S insn x y=none
movem [r7],r6
.ifc \y,none
.ifc \S,none
\insn \x
.else
\insn\S \x
.endif
.else
.ifc \S,none
\insn \x,\y
.else
\insn\S \x,\y
.endif
.endif
nop
nop
nop
.endm
 
; An insn-type that has a single register operand. The register
; may or may not be a source register for the insn.
.macro t_r insn
t_S_x_y none,\insn,r3
t_S_x_y none,\insn,r8
.endm
 
; An insn-type that jumps to the destination of the register.
.macro t_r_j insn
move.d 0f,r7
move.d 1f,r8
move.d r8,r9
nop
nop
nop
.section ".rodata"
.p2align 5
0:
.dword 1f
.dword 1f
.dword 1f
.dword 1f
.dword 1f
.dword 1f
.dword 1f
.previous
t_r \insn
1:
.endm
 
; An insn-type that has a size-modifier and two register
; operands.
.macro t_xr_r S insn
t_S_x_y \S \insn r3 r8
t_S_x_y \S \insn r8 r3
move.d r3,r9
t_S_x_y \S \insn r4 r3
t_S_x_y \S \insn r8 r9
.endm
 
; An insn-type that has two register operands.
.macro t_r_r insn
t_xr_r none \insn
.endm
 
; An t_r_rx insn with a byte or word-size modifier.
.macro t_wbr_r insn
t_xr_r .b,\insn
t_xr_r .w,\insn
.endm
 
; Ditto with a dword-size modifier.
.macro t_dwbr_r insn
t_xr_r .d,\insn
t_wbr_r \insn
.endm
 
; An insn-type that has a size-modifier, a constant and a
; register operand.
.macro t_xc_r S insn
t_S_x_y \S \insn 24 r3
move.d r3,r9
t_S_x_y \S \insn 24 r8
.endm
 
; An insn-type that has a constant and a register operand.
.macro t_c_r insn
t_xc_r none \insn
.endm
 
; An t_c_r insn with a byte or word-size modifier.
.macro t_wbc_r insn
t_xc_r .b,\insn
t_xc_r .w,\insn
.endm
 
; Ditto with a dword-size modifier.
.macro t_dwbc_r insn
t_xc_r .d,\insn
t_wbc_r \insn
.endm
 
; An insn-type that has size-modifier, a memory operand and a
; register operand.
.macro t_xm_r S insn
move.d 9b,r8
t_S_x_y \S,\insn,[r4],r3
move.d r3,r9
t_S_x_y \S,\insn,[r8],r5
move.d r5,r9
t_S_x_y \S,\insn,[r3],r9
t_S_x_y \S,\insn,[r8],r9
.endm
 
; Ditto, to memory.
.macro t_xr_m S insn
move.d 9b,r8
t_S_x_y \S,\insn,r3,[r4]
t_S_x_y \S,\insn,r8,[r3]
t_S_x_y \S,\insn,r3,[r8]
t_S_x_y \S,\insn,r9,[r8]
.endm
 
; An insn-type that has a memory operand and a register operand.
.macro t_m_r insn
t_xm_r none \insn
.endm
 
; An t_m_r insn with a byte or word-size modifier.
.macro t_wbm_r insn
t_xm_r .b,\insn
t_xm_r .w,\insn
.endm
 
; Ditto with a dword-size modifier.
.macro t_dwbm_r insn
t_xm_r .d,\insn
t_wbm_r \insn
.endm
 
; Insn types of the regular type (r, c, m, size d w b).
.macro t_dwb insn
t_dwbr_r \insn
t_dwbc_r \insn
t_dwbm_r \insn
.endm
 
; Similar, sizes w b.
.macro t_wb insn
t_wbr_r \insn
t_wbc_r \insn
t_wbm_r \insn
.endm
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
startnostack
 
; Initialize registers so they don't contain unknowns.
 
move.d 9f,r7
move.d r7,r8
moveq 0,r9
 
; Movem source area. Register contents must be valid
; addresses, aligned on a cache boundary.
.section ".rodata"
.p2align 5
9:
.dword 9b
.dword 9b
.dword 9b
.dword 9b
.dword 9b
.dword 9b
.dword 9b
.dword 9b
.dword 9b
.dword 9b
.previous
 
; The actual tests. The numbers in the comments specify the
; number of movem destination stall cycles. Some of them may be
; filed as memory source address stalls, multiplication source
; stalls or jump source stalls, duly marked so.
 
t_r_r abs ; 3+3
 
t_dwb add ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src)
 
t_r_r addc ; (3+3+3)
t_c_r addc ; 3
t_m_r addc ; (3+3+3) (2 mem src)
 
t_dwb move ; (3+3)+(3+3+3)*2+3*2+(3+3+3)*3 (6 mem src)
t_xr_m .b move ; 3+3+3 (2 mem src)
t_xr_m .w move ; 3+3+3 (2 mem src)
t_xr_m .d move ; 3+3+3 (2 mem src)
 
t_S_x_y none addi r3.b r8 ; 3
t_S_x_y none addi r8.w r3 ; 3
t_S_x_y none addi r4.d r3 ; 3
t_S_x_y none addi r8.w r9
 
; Addo has three-operand syntax, so we have to expand (a useful
; subset of) "t_dwb".
t_S_x_y none addi r3.b "r8,acr" ; 3
t_S_x_y none addi r8.w "r3,acr" ; 3
t_S_x_y none addi r4.d "r3,acr" ; 3
t_S_x_y none addi r8.w "r9,acr"
 
t_S_x_y .b addo 42 "r8,acr"
t_S_x_y .w addo 4200 "r3,acr" ; 3
t_S_x_y .d addo 420000 "r3,acr" ; 3
 
move.d 9b,r8
t_S_x_y .d,addo,[r4],"r3,acr" ; 3 (1 mem src)
t_S_x_y .b,addo,[r3],"r8,acr" ; 3 (1 mem src)
t_S_x_y .w,addo,[r8],"r3,acr" ; 3
t_S_x_y .w,addo,[r8],"r9,acr"
 
; Similar for addoq.
t_S_x_y none addoq 42 "r8,acr"
t_S_x_y none addoq 42 "r3,acr" ; 3
 
t_c_r addq ; 3
 
t_wb adds ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src)
t_wb addu ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src)
 
t_dwb and ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src)
t_c_r andq ; 3
 
t_dwbr_r asr ; (3+3+3)*3
t_c_r asrq ; 3
 
t_dwbr_r bound ; (3+3+3)*3
t_dwbc_r bound ; 3*3
 
t_r_r btst ; (3+3+3)
t_c_r btstq ; 3
 
t_dwb cmp ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src)
t_c_r cmpq ; 3
 
t_wbc_r cmps ; 3*2
t_wbc_r cmpu ; 3*2
t_wbm_r cmps ; (3+3+3)*2 (4 mem src)
t_wbm_r cmpu ; (3+3+3)*2 (4 mem src)
 
t_r_r dstep ; (3+3+3)
 
; FIXME: idxd, fidxi, ftagd, ftagi when supported.
 
t_r_j jsr ; 3 (2 jump src)
t_r_j jump ; 3 (2 jump src)
 
t_c_r lapc.d
 
; The "quick operand" must be in range [. to .+15*2] so we can't
; use t_c_r.
t_S_x_y none lapcq .+4 r3
t_S_x_y none lapcq .+4 r8
 
t_dwbr_r lsl ; (3+3+3)*3
t_c_r lslq ; 3
 
t_dwbr_r lsr ; (3+3+3)*3
t_c_r lsrq ; 3
 
t_r_r lz ; 3+3
 
t_S_x_y none mcp srp r3 ; 3
t_S_x_y none mcp srp r8
 
t_c_r moveq
 
t_S_x_y none move srp r8
t_S_x_y none move srp r3
t_S_x_y none move r8 srp
t_S_x_y none move r3 srp ; 3
 
; FIXME: move supreg,Rd and move Rs,supreg when supported.
 
t_wb movs ; (3+3)*2+0+(3+3)*2 (4 mem src)
t_wb movu ; (3+3)*2+0+(3+3)*2 (4 mem src)
 
t_dwbr_r muls ; (3+3+3)*3 (9 mul src)
t_dwbr_r mulu ; (3+3+3)*3 (9 mul src)
 
t_dwbr_r neg ; (3+3)*3
 
t_r not ; 3 cycles.
 
t_dwb or ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src)
t_c_r orq ; 3
 
t_r seq
 
t_dwb sub ; (3+3+3)*3+3*3+(3+3+3)*3 (6 mem src)
t_c_r subq ; 3
 
t_wb subs ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src)
t_wb subu ; (3+3+3)*2+3*2+(3+3+3)*2 (4 mem src)
 
t_r swapw ; 3 cycles.
t_r swapnwbr ; 3 cycles.
 
t_r_j jsrc ; 3 (2 jump src)
 
t_r_r xor ; (3+3+3)
 
move.d 9b,r7
nop
nop
nop
t_xm_r none movem ; (3+3) (2 mem src, 1+1 movem addr)
; As implied by the comment, all movem destination penalty
; cycles (but one) are accounted for as memory source address
; and movem source penalties. There are also two movem address
; cache-line straddle penalties.
t_xr_m none movem ; (3+3+2+2) (2 mem, 6 movem src, +2 movem addr)
 
break 15
/asm/andc.ms
0,0 → 1,80
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 2\n2\nffff\nffffffff\n50124400\nffff0002\n2\nfffff\nfedaff0f\n78134400\nffffff02\n2\nf02\n78134401\n78134400\n
 
.include "testutils.inc"
start
moveq -1,r3
and.d 2,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
moveq 2,r3
and.d -1,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xffff,r3
and.d 0xffff,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
moveq -1,r3
and.d -1,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d 0x78134452,r3
and.d 0x5432f789,r3
test_move_cc 0 0 0 0
dumpr3 ; 50124400
 
moveq -1,r3
and.w 2,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff0002
 
moveq 2,r3
and.w -1,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xfffff,r3
and.w 0xffff,r3
test_move_cc 1 0 0 0
dumpr3 ; fffff
 
move.d 0xfedaffaf,r3
and.w 0xff5f,r3
test_move_cc 1 0 0 0
dumpr3 ; fedaff0f
 
move.d 0x78134452,r3
and.w 0xf789,r3
test_move_cc 0 0 0 0
dumpr3 ; 78134400
 
moveq -1,r3
and.b 2,r3
test_move_cc 0 0 0 0
dumpr3 ; ffffff02
 
moveq 2,r3
and.b -1,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xfa7,r3
and.b 0x5a,r3
test_move_cc 0 0 0 0
dumpr3 ; f02
 
move.d 0x78134453,r3
and.b 0x89,r3
test_move_cc 0 0 0 0
dumpr3 ; 78134401
 
and.b 0,r3
test_move_cc 0 1 0 0
dumpr3 ; 78134400
 
quit
/asm/badarch1.ms
0,0 → 1,5
# mach: crisv3 crisv8 crisv10 crisv32
# xerror:
# output: *not a CRIS program*
# sim: /bin/sh
.include "nopv32t.ms"
/asm/moverm.ms
0,0 → 1,45
# mach: crisv3 crisv8 crisv10 crisv32
# output: 7823fec2\n10231879\n102318fe\n
 
.include "testutils.inc"
start
 
.data
mem1:
.dword 0x12345678
mem2:
.word 0x4567
mem3:
.byte 0x23
.dword 0x76543210
.byte 0xaa,0x11,0x99
 
.text
move.d mem1,r2
move.d 0x7823fec2,r4
setf nzvc
move.d r4,[r2+]
test_cc 1 1 1 1
subq 4,r2
move.d [r2],r3
dumpr3 ; 7823fec2
 
move.d mem2,r3
move.d 0x45231879,r4
clearf nzvc
move.w r4,[r3]
test_cc 0 0 0 0
move.d [r3],r3
dumpr3 ; 10231879
 
move.d mem2,r2
moveq -2,r4
clearf nc
setf zv
move.b r4,[r2+]
test_cc 0 1 1 0
subq 1,r2
move.d [r2],r3
dumpr3 ; 102318ff
 
quit
/asm/jumpmp.ms
0,0 → 1,21
# mach: crisv3 crisv8 crisv10
# output: bed0bed1\n
 
# Test that jump indirect clears the "prefixed"
# bit.
 
.include "testutils.inc"
.data
w:
.dword x1
y:
.dword 0xbed0bed1
 
start
x:
move.d y,r3
jump [w]
x1:
move.d [r3],r3
dumpr3 ; bed0bed1
quit
/asm/addq.ms
0,0 → 1,47
# mach: crisv3 crisv8 crisv10 crisv32
# output: ffffffff\n0\n1\n100\n10000\n47\n67\na6\n80000001\n
 
.include "testutils.inc"
start
moveq -2,r3
addq 1,r3
test_cc 1 0 0 0
dumpr3
 
addq 1,r3
test_cc 0 1 0 1
dumpr3
 
addq 1,r3
test_cc 0 0 0 0
dumpr3
 
move.d 0xff,r3
addq 1,r3
test_cc 0 0 0 0
dumpr3
 
move.d 0xffff,r3
addq 1,r3
test_cc 0 0 0 0
dumpr3
 
move.d 0x42,r3
addq 5,r3
test_cc 0 0 0 0
dumpr3
 
addq 32,r3
test_cc 0 0 0 0
dumpr3
 
addq 63,r3
test_cc 0 0 0 0
dumpr3
 
move.d 0x7ffffffe,r3
addq 3,r3
test_cc 1 0 1 0
dumpr3
 
quit
/asm/tjmpsrv32.ms
0,0 → 1,50
#mach: crisv32
#output: Basic clock cycles, total @: 17\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 5\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
 
; Check that "ret"-type insns get the right number of penalty
; cycles for the special register source.
 
.include "testutils.inc"
startnostack
move.d 1f,$r1
move.d 0f,$r0
move $r0,$mof
jump $mof ; 2 cycles penalty.
nop
 
0:
move [$r1],$srp
nop
ret ; 1 cycle penalty.
nop
 
break 15
 
0:
move 2f,$nrp
nop
nop
jump $nrp ; no penalty.
nop
 
break 15
 
2:
move 3f,$srp ; 2 cycles penalty.
ret
nop
 
3:
break 15
1:
.dword 0b
/asm/boundc.ms
0,0 → 1,101
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 2\n2\nffff\nffffffff\n5432f789\n2\nffff\n2\nffff\nffff\nf789\n2\n2\nff\nff\nff\n89\n0\nff\n
 
.include "testutils.inc"
start
moveq -1,r3
moveq 2,r4
bound.d 2,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
moveq 2,r3
bound.d 0xffffffff,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xffff,r3
bound.d 0xffff,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
moveq -1,r3
bound.d 0xffffffff,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d 0x78134452,r3
bound.d 0x5432f789,r3
test_move_cc 0 0 0 0
dumpr3 ; 5432f789
 
moveq -1,r3
bound.w 2,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
moveq -1,r3
bound.w 0xffff,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
moveq 2,r3
bound.w 0xffff,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xffff,r3
bound.w 0xffff,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
move.d 0xfedaffff,r3
bound.w 0xffff,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
move.d 0x78134452,r3
bound.w 0xf789,r3
test_move_cc 0 0 0 0
dumpr3 ; f789
 
moveq -1,r3
bound.b 2,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
moveq 2,r3
bound.b 0xff,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
moveq -1,r3
bound.b 0xff,r3
test_move_cc 0 0 0 0
dumpr3 ; ff
 
move.d 0xff,r3
bound.b 0xff,r3
test_move_cc 0 0 0 0
dumpr3 ; ff
 
move.d 0xfeda49ff,r3
bound.b 0xff,r3
test_move_cc 0 0 0 0
dumpr3 ; ff
 
move.d 0x78134452,r3
bound.b 0x89,r3
test_move_cc 0 0 0 0
dumpr3 ; 89
 
bound.w 0,r3
test_move_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0xffff,r3
bound.b -1,r3
test_move_cc 0 0 0 0
dumpr3 ; ff
 
quit
/asm/nopv32t.ms
0,0 → 1,21
#mach: crisv32
#output: Basic clock cycles, total @: 5\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "testutils.inc"
.global _start
_start:
nop
nop
nop
nop
nop
break 15
/asm/biap.ms
0,0 → 1,56
# mach: crisv0 crisv3 crisv8 crisv10
# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n
 
.include "testutils.inc"
.data
x:
.dword 0x55aa77ff
.dword 0xccff2244
.dword 0x88ccee19
 
start
moveq -1,r0
move.d x-32768,r5
move.d 32769,r6
move.d [r5+r6.b],r3
test_cc 0 0 0 0
dumpr3 ; 4455aa77
 
addu.w 32771,r5
moveq -1,r8
move.d [r11=r5+r8.w],r3
test_cc 0 0 0 0
dumpr3 ; 4455aa77
 
moveq 5,r10
move.d [r11+r10.b],r3
test_cc 1 0 0 0
dumpr3 ; ee19ccff
 
subq 1,r5
move.d r5,r8
subq 1,r8
moveq 1,r9
movu.w [r12=r8+r9.d],r3
test_cc 0 0 0 0
dumpr3 ; ff22
 
moveq -2,r11
move.d [r13=r12+r11.w],r3
test_cc 0 0 0 0
dumpr3 ; 4455aa77
 
subq 18,r13
moveq 5,r9
move.d [r13+r9.d],r3
test_cc 1 0 0 0
dumpr3 ; ff224455
 
move.d r5,r7
add.d 76789886,r7
move.d -76789888/4,r12
move.d [r7+r12.d],r3
test_cc 0 0 0 0
dumpr3 ; 55aa77ff
 
quit
/asm/raw3.ms
0,0 → 1,22
; Checking read-after-write: read-then-write unaffected.
#mach: crisv32
#output: Basic clock cycles, total @: 4\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "testutils.inc"
startnostack
.lcomm x,4
.lcomm y,4
move.d x,$r0
move.d y,$r1
move.d [$r0],$r2
move.d $r0,[$r1]
break 15
/asm/dip.ms
0,0 → 1,41
# mach: crisv0 crisv3 crisv8 crisv10
# output: 4455aa77\nee19ccff\nb232765a\nff22\n5a88ccee\n
 
.include "testutils.inc"
.data
x:
.dword 0x55aa77ff
.dword 0xccff2244
.dword 0x88ccee19
.dword 0xb232765a
y:
.dword x+12
.dword x+5
.dword x+9
 
start
moveq -1,r0
moveq -1,r2
move.d [x+1],r3
test_cc 0 0 0 0
dumpr3 ; 4455aa77
 
move.d [x+6],r3
test_cc 1 0 0 0
dumpr3 ; ee19ccff
 
move.d y,r8
move.d [[r8+]],r3
test_cc 1 0 0 0
dumpr3 ; b232765a
 
movu.w [[r8]],r3
test_cc 0 0 0 0
dumpr3 ; ff22
addq 4,r8
 
move.d [[r8]],r3
test_cc 0 0 0 0
dumpr3 ; 5a88ccee
 
quit
/asm/tjsrcv32.ms
0,0 → 1,13
#mach: crisv32
#output: Basic clock cycles, total @: 6\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 2\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "tjsrcv10.ms"
/asm/bdapm.ms
0,0 → 1,56
# mach: crisv0 crisv3 crisv8 crisv10
# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n
 
.include "testutils.inc"
.data
x:
.dword 0x55aa77ff
.dword 0xccff2244
.dword 0x88ccee19
y:
.dword 32769
.word -1
.dword 5
.byte 3,-4
.word 2
.dword -76789887
 
start
moveq -1,r0
move.d x-32768,r5
move.d y,r13
bdap.d [r13+],r5
move.d [r3],r9
test_move_cc 0 0 0 0
dumpr3 ; 4455aa77
 
addu.w 32770,r5
bdap.w [r13+],r5
move.d [r9+],r3
dumpr3 ; 4455aa77
 
bdap.d [r13],r9
move.d [r3],r7
addq 4,r13
dumpr3 ; ee19ccff
 
bdap.b [r13+],r5
movu.w [r7+],r3
dumpr3 ; ff22
 
bdap.b [r13],r7
move.d [r7+],r3
addq 1,r13
dumpr3 ; 4455aa77
 
bdap.w [r13],r7
move.d [r3],r3
addq 2,r13
dumpr3 ; ff224455
 
add.d 76789885,r5
bdap.d [r13+],r5
move.d [r3],r9
dumpr3 ; 55aa77ff
 
quit
/asm/addswpc.ms
0,0 → 1,61
# mach: crisv3 crisv8 crisv10
# output: 7\n
 
# Test that the special case adds.w [pc+rN.w],pc works.
 
.include "testutils.inc"
start
x:
moveq 0,r3
ba xy
moveq 5,r2
 
ok:
moveq 7,r3
dumpr3
quit
 
xy:
adds.w [pc+r2.w],pc
y:
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word ok-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
.word x0-y
x0:
quit
/asm/clearfv32.ms
0,0 → 1,12
# mach: crisv32
# output: ef\n
 
; Check that "clearf x" doesn't trivially fail.
 
.include "testutils.inc"
start
setf puixnzvc
clearf x ; Actually, x would be cleared by almost-all other insns.
move ccs,r3
dumpr3
quit
/asm/addoq.ms
0,0 → 1,31
# mach: crisv32
# output: ccff2244\n88ccee19\n55aa77ff\n19cc\n
 
.include "testutils.inc"
.data
x:
.dword 0x55aa77ff
.dword 0xccff2244
.dword 0x88ccee19
start
moveq -1,r0
move.d x+4,r5
setf zvnc
addoq 0,r5,acr
test_cc 1 1 1 1
move.d [acr],r3
dumpr3 ; ccff2244
setf zvnc
addoq 4,r5,acr
test_cc 1 1 1 1
move.d [acr],r3
dumpr3 ; 88ccee19
clearf zvnc
addoq -8,acr,acr
test_cc 0 0 0 0
move.d [acr],r3
dumpr3 ; 55aa77ff
addoq 3,r5,acr
movu.w [acr],r3
dumpr3 ; 19cc
quit
/asm/io3.ms
0,0 → 1,17
# mach: crisv32
# sim: --cris-900000xx
# output: ce11d0c\n
 
; Check correct "pass" exit.
 
.include "testutils.inc"
start
move.d 0x0ce11d0c,$r3
dumpr3
move.d 0x90000004,$acr
move.d $acr,[$acr]
move.d 0xbadc0de,$r3
dumpr3
0:
ba 0b
nop
/asm/sbfs.ms
0,0 → 1,7
# mach: crisv10
# xerror:
# output: SBFS isn't implemented\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
start
sbfs [r10]
/asm/addxm.ms
0,0 → 1,106
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 1\n1\n101\n10001\n100fe\n1fffe\nfffe\nfffe\nfffffffe\nfe\nfffffffe\n781344db\n781343db\n78143bdb\n78133bdb\n800000ed\n0\n
 
.include "testutils.inc"
.data
x:
.byte 0xff
.word 0xffff
.word 0xff
.word 0xffff
.byte 0x89
.word 0xf789
.byte 0xff
.word 0xffff
 
start
moveq 2,r3
move.d x,r5
adds.b [r5+],r3
test_cc 0 0 0 1
dumpr3 ; 1
 
moveq 2,r3
adds.w [r5+],r3
test_cc 0 0 0 1
dumpr3 ; 1
 
moveq 2,r3
subq 3,r5
addu.b [r5+],r3
test_cc 0 0 0 0
dumpr3 ; 101
 
moveq 2,r3
addu.w [r5+],r3
subq 3,r5
test_cc 0 0 0 0
dumpr3 ; 10001
 
move.d 0xffff,r3
addu.b [r5],r3
test_cc 0 0 0 0
dumpr3 ; 100fe
 
move.d 0xffff,r3
addu.w [r5],r3
test_cc 0 0 0 0
dumpr3 ; 1fffe
 
move.d 0xffff,r3
adds.b [r5],r3
test_cc 0 0 0 1
dumpr3 ; fffe
 
move.d 0xffff,r3
adds.w [r5],r3
test_cc 0 0 0 1
dumpr3 ; fffe
 
moveq -1,r3
adds.b [r5],r3
test_cc 1 0 0 1
addq 3,r5
dumpr3 ; fffffffe
 
moveq -1,r3
adds.w [r5+],r3
test_cc 0 0 0 1
dumpr3 ; fe
 
moveq -1,r3
adds.w [r5+],r3
test_cc 1 0 0 1
dumpr3 ; fffffffe
 
move.d 0x78134452,r3
addu.b [r5],r3
test_cc 0 0 0 0
dumpr3 ; 781344db
 
move.d 0x78134452,r3
adds.b [r5+],r3
test_cc 0 0 0 1
dumpr3 ; 781343db
 
move.d 0x78134452,r3
addu.w [r5],r3
test_cc 0 0 0 0
dumpr3 ; 78143bdb
 
move.d 0x78134452,r3
adds.w [r5+],r3
test_cc 0 0 0 1
dumpr3 ; 78133bdb
 
move.d 0x7fffffee,r3
addu.b [r5+],r3
test_cc 1 0 1 0
dumpr3 ; 800000ed
 
move.d 0x1,r3
adds.w [r5+],r3
test_cc 0 1 0 1
dumpr3 ; 0
 
quit
/asm/x3-v10.ms
0,0 → 1,12
#mach: crisv10
#ld: --section-start=.text=0
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: a 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 2\n
#output: 12 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 1e 0 0 0 0 0 12 0 0 0 0 0 0 0 0 * ixnzvc 2\n
#sim: --cris-trace=basic
 
; With a "--cris-trace=all", cycles for the third line would be 3.
 
.include "tjsrcv10.ms"
/asm/opterr3.ms
0,0 → 1,10
# mach: crisv3 crisv8 crisv10 crisv32
# ld: -N --oformat binary --section-start=.text=0x10000000
# sim: --cris-naked --memory-mapfile
# xerror:
# output: Usage: run \[options\] program \[program args\]\n*\n
# progopts: --memory-region 0x10000000,0x1000
.include "bare3.ms"
 
; Check that we get an error for wrong usage, not a SEGV for lack of
; bfd when missing the program argument (can't use *only* mapped files).
/asm/x1-v32.ms
0,0 → 1,8
#mach: crisv32
#ld: --section-start=.text=0
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: a 0 0 0 0 0 ff004567 0 0 0 0 0 0 0 0 * ixNzvc 1 0\n
#sim: --cris-trace=basic
 
.include "movect10.ms"
/asm/raw16.ms
0,0 → 1,14
; Checking read-after-write: cycles included in "unaligned".
#mach: crisv32
#output: Clock cycles including stall cycles for unaligned accesses @: 4\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 2\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=unaligned
.include "raw4.ms"
/asm/movpr.ms
0,0 → 1,28
# mach: crisv3 crisv8 crisv10 crisv32
# output: ffffff00\nffff0000\n0\nbb113344\n
 
# Test generic "move Ps,Rd" and "move Rs,Pd" insns; the ones with
# functionality common to all models.
 
.include "testutils.inc"
start
moveq -1,r3
clear.b r3
dumpr3
 
moveq -1,r3
clear.w r3
dumpr3
 
moveq -1,r3
clear.d r3
dumpr3
 
moveq -1,r3
move.d 0xbb113344,r4
setf zcvn
move r4,srp
move srp,r3
test_cc 1 1 1 1
dumpr3
quit
/asm/movppc.ms
0,0 → 1,7
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
start
move srp,[PC+]
/asm/pcplus.ms
0,0 → 1,46
# mach: crisv0 crisv3 crisv8 crisv10
 
; Test that a forward as well as backward 32-bit "branch" expansion
; works including that the right offset is applied.
 
.macro nop32
.rept 32
nop
.endr
.endm
 
.include "testutils.inc"
start
jump start1
fail
 
nop32
subq 63,$r10
9: subq 1,$r10
nop32
jump 0f
 
fail
0: move [$pc=$pc+1f-6-0b],$p0
nop32
fail
 
.skip 32768,0
 
nop32
subq 63,$r10
1:
subq 1,$r10
nop32
test.d $r10
bne 7f
nop
pass
7:
fail
 
start1:
moveq 2,$r10
0: move [$pc=$pc+9b-6-0b],$p0
subq 63,$r10
fail
/asm/addcv32r.ms
0,0 → 1,57
# mach: crisv32
# output: 0\n0\n1\n1\n2\n1ffff\nfffffffe\ncc463bdc\n
 
.include "testutils.inc"
start
clearf cz
moveq 0,r3
moveq 0,r4
addc r4,r3
test_cc 0 0 0 0
dumpr3 ; 0
 
setf z
moveq 0,r3
moveq 0,r4
addc r4,r3
test_cc 0 1 0 0
dumpr3 ; 0
 
setf cz
moveq 0,r3
moveq 0,r4
addc r4,r3
test_cc 0 0 0 0
dumpr3 ; 1
 
moveq -1,r3
moveq 2,r4
addc r4,r3
test_cc 0 0 0 1
dumpr3 ; 1+c
 
moveq 2,r3
moveq -1,r4
addc r4,r3
test_cc 0 0 0 1
dumpr3 ; 2+c
 
move.d 0xffff,r4
move.d r4,r3
addc r4,r3
test_cc 0 0 0 0
dumpr3 ; 1ffff
 
moveq -1,r4
move.d r4,r3
addc r4,r3
test_cc 1 0 0 1
dumpr3 ; fffffffe+c
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
addc r4,r3
test_cc 1 0 1 0
dumpr3 ; cc463bdc
 
quit
/asm/movscr.ms
0,0 → 1,29
# mach: crisv3 crisv8 crisv10 crisv32
# output: 42\nffffff85\n7685\nffff8765\n0\n
 
; Move constant byte, word, dword to register. Check that sign-extension
; is performed.
 
.include "testutils.inc"
start
moveq -1,r3
movs.b 0x42,r3
dumpr3
 
movs.b 0x85,r3
test_move_cc 1 0 0 0
dumpr3
 
movs.w 0x7685,r3
test_move_cc 0 0 0 0
dumpr3
 
movs.w 0x8765,r3
test_move_cc 1 0 0 0
dumpr3
 
movs.w 0,r3
test_move_cc 0 1 0 0
dumpr3
 
quit
/asm/moveqpc.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
startnostack
setf
moveq -30,pc
quit
/asm/ccr-v10.ms
0,0 → 1,79
# mach: crisv10
# output: ff\nff\n0\n0\n80\n40\n20\n10\n8\n4\n2\n1\n80\n40\n20\n10\n8\n4\n2\n1\n42\n
 
; Check that flag settings affect ccr and dccr and vice versa.
 
.include "testutils.inc"
start
clear.d r3
setf mbixnzvc
move ccr,r3
dumpr3
 
clear.d r3
setf mbixnzvc
move dccr,r3
dumpr3
 
clear.d r3
clearf mbixnzvc
move ccr,r3
dumpr3
 
clear.d r3
clearf mbixnzvc
move dccr,r3
dumpr3
 
.macro testfr BIT REG
clear.d r3
clearf mbixnzvc
setf \BIT
move \REG,r3
dumpr3
.endm
 
testfr m ccr
testfr b ccr
testfr i ccr
testfr x ccr
testfr n ccr
testfr z ccr
testfr v ccr
testfr c ccr
 
testfr m dccr
testfr b dccr
testfr i dccr
testfr x dccr
testfr n dccr
testfr z dccr
testfr v dccr
testfr c dccr
 
; Check only the nzvc bits; do the other bits in special tests as they're
; implemented.
.macro test_get_cc N Z V C
clearf znvc
move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),ccr
test_cc \N \Z \V \C
setf znvc
move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),dccr
test_cc \N \Z \V \C
move.d ((\N << 3)|(\Z << 2)|(\V << 1)|\C),r4
setf znvc
move r4,ccr
test_cc \N \Z \V \C
clearf znvc
move r4,dccr
test_cc \N \Z \V \C
.endm
 
test_get_cc 1 0 0 0
test_get_cc 0 1 0 0
test_get_cc 0 0 1 0
test_get_cc 0 0 0 1
 
move.d 0x42,r3
dumpr3
quit
/asm/rfe.ms
0,0 → 1,47
# mach: crisv32
# output: 4000c3af\n40000020\n40000080\n40000000\n
 
; Check that RFE affects CCS the right way.
 
.include "testutils.inc"
start
 
; Set SPC to 1 to disable single step exceptions when S flag is set.
move 1,spc
 
; CCS:
; 31 24 23 16 15 8 7 0
; +---+-----------+-------+-------+-----------+---+---------------+
; |Q M|S R P U I X N Z V C|S R P U I X N Z V C|S R P U I X N Z V C|
; | |2 2 2 2 2 2 2 2 2 2|1 1 1 1 1 1 1 1 1 1| |
; +---+-----------+-------+-------+-----------+---+---------------+
 
; Clear S R P U I X N Z V C, set S1 R1 P1 (not U1) I1 X1 N1 Z1 V1 C1,
; clear S2 R2 P2 U2 N2 Z2 V2 C2, Q; set I2 X2 M:
; 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
move 0x430efc00,ccs
 
test_cc 0 0 0 0
 
rfe
test_cc 1 1 1 1
move ccs,r3
dumpr3 ; 0x4000c3af
 
rfe
test_cc 0 0 0 0
move ccs,r3
dumpr3 ; 0x40000020
 
rfe
test_cc 0 0 0 0
move ccs,r3
dumpr3 ; 0x40000080
 
or.w 0x100,r3
move $r3,ccs
rfe
move ccs,r3
dumpr3 ; 0x40000000
 
quit
/asm/raw6.ms
0,0 → 1,24
; Checking read-after-write: write-then-nop-nop-read unaffected.
#mach: crisv32
#output: Basic clock cycles, total @: 6\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "testutils.inc"
startnostack
.lcomm x,4
.lcomm y,4
move.d x,$r0
move.d y,$r1
move.d $r1,[$r0]
nop
nop
move.d [$r1],$r2
break 15
/asm/lapc.ms
0,0 → 1,78
# mach: crisv32
# output: 0\n0\nfffffffa\nfffffffe\nffffffda\n1e\n1e\n0\n
 
.include "testutils.inc"
 
; To accommodate dumpr3 with more than one instruction, keep it
; out of lapc operand ranges and difference calculations.
 
start
lapc.d 0f,r3
0:
sub.d .,r3
dumpr3 ; 0
 
lapcq 0f,r3
0:
sub.d .,r3
dumpr3 ; 0
 
lapc.d .,r3
sub.d .,r3
dumpr3 ; fffffffa
 
lapcq .,r3
sub.d .,r3
dumpr3 ; fffffffe
 
0:
.rept 16
nop
.endr
lapc.d 0b,r3
sub.d .,r3
dumpr3 ; ffffffda
 
setf zcvn
lapc.d 0f,r3
test_cc 1 1 1 1
sub.d .,r3
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
0:
dumpr3 ; 1e
0:
lapcq 0f,r3
sub.d 0b,r3
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
0:
dumpr3 ; 1e
clearf cn
setf zv
1:
lapcq .,r3
test_cc 0 1 1 0
sub.d 1b,r3
dumpr3 ; 0
 
quit
/asm/movei.ms
0,0 → 1,47
# mach: crisv32
# output: fffffffe\n
# output: fffffffe\n
 
; Check basic integral-write semantics regarding flags.
 
.include "testutils.inc"
start
 
; A write that works. Check that flags are set correspondingly.
move.d d,r4
moveq -2,r5
setf c
clearf p
move.d [r4],r3
ax
move.d r5,[r4]
move.d [r4],r3
 
bcc 0f
nop
fail
 
0:
dumpr3 ; fffffffe
 
; A write that fails; check flags too.
move.d d,r4
moveq 23,r5
setf p
clearf c
move.d [r4],r3
ax
move.d r5,[r4]
move.d [r4],r3
 
bcs 0f
nop
fail
 
0:
dumpr3 ; fffffffe
quit
 
.data
d:
.dword 42424242
/asm/moverpcd.ms
0,0 → 1,13
# mach: crisv3 crisv8 crisv10
# output: 4\n
 
# Test that move.d pc,R works.
 
.include "testutils.inc"
start
x:
move.d pc,r3
y:
sub.d y-4,r3
dumpr3
quit
/asm/cmpxm.ms
0,0 → 1,106
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 2\n2\n2\n2\nffff\nffff\nffff\nffff\nffffffff\nffffffff\nffffffff\n78134452\n78134452\n78134452\n78134452\n4452\n80000032\n
 
.include "testutils.inc"
.data
x:
.byte 0xff
.word 0xffff
.word 0xff
.word 0xffff
.byte 0x89
.word 0xf789
.word 0x8002
.word 0x764
 
start
moveq 2,r3
move.d x,r5
cmps.b [r5+],r3
test_cc 0 0 0 1
dumpr3 ; 2
 
moveq 2,r3
cmps.w [r5+],r3
test_cc 0 0 0 1
dumpr3 ; 2
 
moveq 2,r3
subq 3,r5
cmpu.b [r5+],r3
test_cc 1 0 0 1
dumpr3 ; 2
 
moveq 2,r3
cmpu.w [r5+],r3
test_cc 1 0 0 1
subq 3,r5
dumpr3 ; 2
 
move.d 0xffff,r3
cmpu.b [r5],r3
test_cc 0 0 0 0
dumpr3 ; ffff
 
move.d 0xffff,r3
cmpu.w [r5],r3
test_cc 0 1 0 0
dumpr3 ; ffff
 
move.d 0xffff,r3
cmps.b [r5],r3
test_cc 0 0 0 1
dumpr3 ; ffff
 
move.d 0xffff,r3
cmps.w [r5],r3
test_cc 0 0 0 1
dumpr3 ; ffff
 
moveq -1,r3
cmps.b [r5],r3
test_cc 0 1 0 0
addq 3,r5
dumpr3 ; ffffffff
 
moveq -1,r3
cmps.w [r5+],r3
test_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq -1,r3
cmps.w [r5+],r3
test_cc 0 1 0 0
dumpr3 ; ffffffff
 
move.d 0x78134452,r3
cmpu.b [r5],r3
test_cc 0 0 0 0
dumpr3 ; 78134452
 
move.d 0x78134452,r3
cmps.b [r5+],r3
test_cc 0 0 0 1
dumpr3 ; 78134452
 
move.d 0x78134452,r3
cmpu.w [r5],r3
test_cc 0 0 0 0
dumpr3 ; 78134452
 
move.d 0x78134452,r3
cmps.w [r5+],r3
test_cc 0 0 0 1
dumpr3 ; 78134452
 
move.d 0x4452,r3
cmps.w [r5+],r3
test_cc 0 0 0 1
dumpr3 ; 4452
 
move.d 0x80000032,r3
cmpu.w [r5+],r3
test_cc 0 0 1 0
dumpr3 ; 80000032
 
quit
/asm/movsmpc.ms
0,0 → 1,8
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
start
move.d _start,r12
movs.w [r12],pc
/asm/moveq.ms
0,0 → 1,15
# mach: crisv3 crisv8 crisv10 crisv32
# sim: --trace-core=on
# ld: --section-start=.text=0
# output: read-2 exec:0x00000002 -> 0x3262\nread-2 exec:0x00000004 -> 0xe93e\nffffffe2\nread-2 exec:0x00000006 -> 0x324d\nread-2 exec:0x00000008 -> 0xe93e\nd\nread-2 exec:0x0000000a -> 0xe93f\n
 
; Output a positive and a negative number, set from moveq.
 
.include "testutils.inc"
startnostack
moveq -30,r3
dumpr3
moveq 13,r3
dumpr3
quit
 
/asm/movssr.ms
0,0 → 1,8
# mach: crisv32
# xerror:
# output: Read of support register is unimplemented\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
start
move S0,R3
 
/asm/tmemv10.ms
0,0 → 1,27
#mach: crisv10
#output: Basic clock cycles, total @: 8\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
 
; Check that the memory indirection doesn't make the simulator barf.
; Nothing deeper.
 
.include "testutils.inc"
startnostack
move.d 0f,r5
move.d [r5],r4
move.d [r5+],r3
move.d [r5],r2
break 15
nop
.p2align 2
0:
.dword 1,2,3
/asm/bare1.ms
0,0 → 1,24
# mach: crisv32
# ld: --section-start=.text=0
# output: 0\n0\n4\n42\n
# sim: --cris-naked
 
; Check that we don't get signs of an initialized environment
; when --cris-naked.
 
.include "testutils.inc"
.text
.global _start
_start:
nop
nop
start2:
move.d $r10,$r3
dumpr3
move.d $sp,$r3
dumpr3
lapc start2,$r3
dumpr3
move.d 0x42,$r3
dumpr3
quit
/asm/option3.ms
0,0 → 1,7
#mach: crisv0 crisv3 crisv8 crisv10 crisv32
#sim: --cris-cycles=foo
#xerror:
#output: Unknown option `--cris-cycles=foo'\n
.include "testutils.inc"
start
fail
/asm/raw11.ms
0,0 → 1,23
; Checking read-after-write: swrite-then-nop-read 2 cycles.
#mach: crisv32
#output: Basic clock cycles, total @: 5\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 2\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "testutils.inc"
startnostack
.lcomm x,4
.lcomm y,4
move.d x,$r0
move.d y,$r1
clear.d [$r0]
nop
move [$r1],$srp
break 15
/asm/tmvrmv10.ms
0,0 → 1,40
#mach: crisv10
#output: Basic clock cycles, total @: 31\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
 
; Check that movem to memory basically looks ok cycle-wise.
; Nothing deep.
 
.include "testutils.inc"
startnostack
move.d 0f,r4
moveq 0,r0
moveq 1,r3
moveq 2,r1
moveq 1,r2
movem r3,[r4] ; 2 cycles penalty for v32
movem r3,[r4] ; 0 cycles penalty for v32
moveq 1,r3
nop
movem r3,[r4] ; 1 cycle penalty for v32
moveq 1,r3
nop
nop
movem r3,[r4] ; 0 cycles penalty for v32
break 15
 
.data
0:
.dword 0
.dword 0
.dword 0
.dword 0
/asm/io6.ms
0,0 → 1,22
# mach: crisv32
# ld: --section-start=.text=0
# sim: --cris-900000xx
# xerror:
# output: b1e\n
# output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n
# output: program stopped with signal 11.\n
 
; Check that invalid access to the simulator area is recognized.
; "FAIL" area.
 
.include "testutils.inc"
start
move.d 0xb1e,$r3
dumpr3
move.d 0x90000008,$acr
clear.d [$acr]
move.d 0xbadc0de,$r3
dumpr3
0:
ba 0b
nop
/asm/msteppc2.ms
0,0 → 1,8
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\n
# output: program stopped with signal 5.\n
 
.include "testutils.inc"
start
mstep r2,pc
/asm/pid1.ms
0,0 → 1,45
# mach: crisv32
# output: 0\ncafebabe\nbaddbeef\necc0d00d\nc0ceface\npass\n
 
; Check that the PID register has the right size, 32 bits: check
; immediate, to/from register and memory. (This has to be done in
; supervisor mode, so don't set u.)
 
.include "testutils.inc"
.macro dumpid
move $pid,$r3
dumpr3
.endm
 
start
moveq -1,$r3
move 0,$pid
dumpid ; 0
move 0xcafebabe,$pid
dumpid ; cafebabe
move.d 0xbaddbeef,$r2
move $r2,$pid
dumpid ; baddbeef
move.d 0f,$r0
move [$r0+],$pid
cmp.d 0f+4,$r0
beq 1f
nop
dofail:
fail
0:
.dword 0xecc0d00d
0:
.dword 0xc0ceface
1:
dumpid ; ecc0d00d
move.d 0b,$r1
move 0xc0ceface,$pid
move $pid,[$r1+]
cmp.d 0b+4,$r1
bne dofail
subq 4,$r1
nop
move.d [$r1],$r3
dumpr3 ; c0ceface
pass
/asm/x2-v10.ms
0,0 → 1,59
#mach: crisv10
#ld: --section-start=.text=0
#sim: --cris-trace=basic
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1\n
#output: c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1\n
#output: 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvC 1\n
#output: 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 16 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 18 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 1a 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 16 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 18 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 1a 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 16 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 18 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 1a 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 16 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 18 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 1a 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n
#output: 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n
#output: 1a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n
#output: 1c ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n
#output: 1e ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n
#output: 20 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n
#output: 22 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n
#output: 26 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 2\n
#output: 230 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n
#output: 232 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n
#output: 236 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 2\n
#output: 440 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n
#output: 442 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 446 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n
#output: 650 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 654 4 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n
#output: 442 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 446 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n
#output: 650 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 654 3 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n
#output: 442 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 446 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n
#output: 650 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 654 2 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n
#output: 442 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 446 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n
#output: 650 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: 654 1 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 2\n
#output: 442 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n
#output: 446 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 2\n
#output: 650 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 1\n
#output: 654 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnZvc 2\n
#output: 656 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n
#output: 658 ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n
#output: 65a ffffffff 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvC 1\n
.include "tb.ms"
/asm/nopv32t4.ms
0,0 → 1,13
#mach: crisv10 crisv32
#output: All accounted clock cycles, total @: 5\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=all
.include "nopv32t.ms"
/asm/x0-v32.ms
0,0 → 1,7
#mach: crisv32
#ld: --section-start=.text=0
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[0-9a-f][0-9a-f][0-9a-f] ixnzvc 0 0\n
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[0-9a-f][0-9a-f][0-9a-f] ixnzvc 1 0\n
#sim: --cris-trace=basic
 
.include "break.ms"
/asm/cmpq.ms
0,0 → 1,75
# mach: crisv3 crisv8 crisv10 crisv32
# output: 1\n1\n1\n1f\n1f\nffffffe1\nffffffe1\nffffffe0\n0\n0\nffffffff\nffffffff\n10000\n100\n5678900\n
 
.include "testutils.inc"
start
moveq 1,r3
cmpq 1,r3
test_cc 0 1 0 0
dumpr3 ; 1
 
cmpq -1,r3
test_cc 0 0 0 1
dumpr3 ; 1
 
cmpq 31,r3
test_cc 1 0 0 1
dumpr3 ; 1
 
moveq 31,r3
cmpq 31,r3
test_cc 0 1 0 0
dumpr3 ; 1f
 
cmpq -31,r3
test_cc 0 0 0 1
dumpr3 ; 1f
 
movs.b -31,r3
cmpq -31,r3
test_cc 0 1 0 0
dumpr3 ; ffffffe1
 
cmpq -32,r3
test_cc 0 0 0 0
dumpr3 ; ffffffe1
 
movs.b -32,r3
cmpq -32,r3
test_cc 0 1 0 0
dumpr3 ; ffffffe0
 
moveq 0,r3
cmpq 1,r3
test_cc 1 0 0 1
dumpr3 ; 0
 
cmpq -32,r3
test_cc 0 0 0 1
dumpr3 ; 0
 
moveq -1,r3
cmpq 1,r3
test_cc 1 0 0 0
dumpr3 ; ffffffff
 
cmpq -1,r3
test_cc 0 1 0 0
dumpr3 ; ffffffff
 
move.d 0x10000,r3
cmpq 1,r3
test_cc 0 0 0 0
dumpr3 ; 10000
 
move.d 0x100,r3
cmpq 1,r3
test_cc 0 0 0 0
dumpr3 ; 100
 
move.d 0x5678900,r3
cmpq 7,r3
test_cc 0 0 0 0
dumpr3 ; 5678900
 
quit
/asm/orr.ms
0,0 → 1,84
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 3\n3\nffff\nffffffff\n7c33f7db\nffff0003\n3\nfedaffff\n7813f7db\n3\n3\nfeb\n781344db\n
 
.include "testutils.inc"
start
moveq 1,r3
moveq 2,r4
or.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 3
 
moveq 2,r3
moveq 1,r4
or.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 3
 
move.d 0xff0f,r4
move.d 0xf0ff,r3
or.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
moveq -1,r4
move.d r4,r3
or.d r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
or.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 7c33f7db
 
move.d 0xffff0001,r3
moveq 2,r4
or.w r4,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff0003
 
moveq 2,r3
move.d 0xffff0001,r4
or.w r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 3
 
move.d 0xfedaffaf,r3
move.d 0xffffff5f,r4
or.w r4,r3
test_move_cc 1 0 0 0
dumpr3 ; fedaffff
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
or.w r4,r3
test_move_cc 1 0 0 0
dumpr3 ; 7813f7db
 
moveq 1,r3
move.d 0xffffff02,r4
or.b r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 3
 
moveq 2,r3
moveq 1,r4
or.b r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 3
 
move.d 0x4a,r4
move.d 0xfa3,r3
or.b r4,r3
test_move_cc 1 0 0 0
dumpr3 ; feb
 
move.d 0x5432f789,r4
move.d 0x78134453,r3
or.b r4,r3
test_move_cc 1 0 0 0
dumpr3 ; 781344db
 
quit
/asm/addcv32m.ms
0,0 → 1,69
# mach: crisv32
# output: 0\n0\n1\n0\n1\n1\n2\n1ffff\nfffffffe\ncc463bdc\n
 
.include "testutils.inc"
.data
x:
.dword 0,0,2,-1,0xffff,-1,0x5432f789
 
start
move.d x,r5
clearf cz
moveq 0,r3
addc [r5],r3
test_cc 0 0 0 0
dumpr3 ; 0
 
setf z
moveq 0,r3
addc [r5],r3
test_cc 0 1 0 0
dumpr3 ; 0
 
setf c
moveq 0,r3
addc [r5],r3
test_cc 0 0 0 0
dumpr3 ; 1
 
clearf c
moveq 0,r3
addc [r5+],r3
test_cc 0 0 0 0
dumpr3 ; 0
 
setf c
moveq 0,r3
addc [r5+],r3
test_cc 0 0 0 0
dumpr3 ; 1
 
clearf c
moveq -1,r3
addc [r5+],r3
test_cc 0 0 0 1
dumpr3 ; 1+c
 
moveq 2,r3
addc [r5],r3
moveq 4,r6
addi r6.b,r5
test_cc 0 0 0 1
dumpr3 ; 2+c
 
move.d 0xffff,r3
addc [r5+],r3
test_cc 0 0 0 0
dumpr3 ; 1ffff
 
moveq -1,r3
addc [r5+],r3
test_cc 1 0 0 1
dumpr3 ; fffffffe+c
 
move.d 0x78134452,r3
addc [r5+],r3
test_cc 1 0 1 0
dumpr3 ; cc463bdc
 
quit
/asm/bdapc.ms
0,0 → 1,57
# mach: crisv0 crisv3 crisv8 crisv10
# output: 4455aa77\n4455aa77\nee19ccff\n88ccee19\nff22\n4455aa77\nff224455\n55aa77ff\n
 
.include "testutils.inc"
.data
x:
.dword 0x55aa77ff
.dword 0xccff2244
.dword 0x88ccee19
.dword 0xb232765a
 
start
moveq -1,r0
moveq -1,r2
move.d x-32768,r5
move.d [r5+32769],r3
test_move_cc 0 0 0 0
dumpr3 ; 4455aa77
 
addu.w 32770,r5
bdap.w -1,r5
move.d [r0],r3
test_move_cc 0 0 0 0
dumpr3 ; 4455aa77
 
bdap.d 4,r5
move.d [r2+],r3
test_move_cc 1 0 0 0
dumpr3 ; ee19ccff
 
bdap.b 2,r2
move.d [r3],r3
test_move_cc 1 0 0 0
dumpr3 ; 88ccee19
 
bdap.b 3,r5
movu.w [r4+],r3
test_move_cc 0 0 0 0
dumpr3 ; ff22
 
bdap.b -4,r4
move.d [r6+],r3
test_move_cc 0 0 0 0
dumpr3 ; 4455aa77
 
bdap.w 2,r6
move.d [r3],r9
test_move_cc 1 0 0 0
dumpr3 ; ff224455
 
add.d 76789885,r5
bdap.d -76789887,r5
move.d [r3],r9
test_move_cc 0 0 0 0
dumpr3 ; 55aa77ff
 
quit
/asm/raw1.ms
0,0 → 1,22
; Checking read-after-write: read-then-read unaffected.
#mach: crisv32
#output: Basic clock cycles, total @: 4\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "testutils.inc"
startnostack
.lcomm x,4
.lcomm y,4
move.d x,$r0
move.d y,$r1
move.d [$r0],$r2
move.d [$r1],$r4
break 15
/asm/subq.ms
0,0 → 1,52
# mach: crisv3 crisv8 crisv10 crisv32
# output: 0\nffffffff\nfffffffe\nffff\nff\n56788f9\n56788d9\n567889a\n0\n7ffffffc\n
 
.include "testutils.inc"
start
moveq 1,r3
subq 1,r3
test_cc 0 1 0 0
dumpr3 ; 0
 
subq 1,r3
test_cc 1 0 0 1
dumpr3 ; ffffffff
 
subq 1,r3
test_cc 1 0 0 0
dumpr3 ; fffffffe
 
move.d 0x10000,r3
subq 1,r3
test_cc 0 0 0 0
dumpr3 ; ffff
 
move.d 0x100,r3
subq 1,r3
test_cc 0 0 0 0
dumpr3 ; ff
 
move.d 0x5678900,r3
subq 7,r3
test_cc 0 0 0 0
dumpr3 ; 56788f9
 
subq 32,r3
test_cc 0 0 0 0
dumpr3 ; 56788d9
 
subq 63,r3
test_cc 0 0 0 0
dumpr3 ; 567889a
 
move.d 34,r3
subq 34,r3
test_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0x80000024,r3
subq 40,r3
test_cc 0 0 1 0
dumpr3 ; 7ffffffc
 
quit
/asm/tjsrcv10.ms
0,0 → 1,29
#mach: crisv10
#output: Basic clock cycles, total @: 6\n
#output: Memory source stall cycles: 1\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
 
; Check that the 4-byte-skip doesn't make the simulator barf.
; Nothing deeper.
 
.include "testutils.inc"
startnostack
nop
move.d 0f,r5
jsrc r5
nop
.dword -1
0:
jsrc 1f
nop
.dword -2
1:
break 15
/asm/tmulv32.ms
0,0 → 1,14
#mach: crisv32
#output: Basic clock cycles, total @: 6\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 2\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
 
.include "tmulv10.ms"
/asm/raw9.ms
0,0 → 1,27
; Checking read-after-write: movemwrite-then-nop-nop-read unaffected.
#mach: crisv32
#ld: --section-start=.text=0
#output: Basic clock cycles, total @: 8\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 1\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "testutils.inc"
startnostack
.lcomm x,4*11
.lcomm y,4
move.d x,$r0
move.d y,$r1
nop
nop
movem $r10,[$r0]
nop
nop
move.d [$r1],$r2
break 15
/asm/andq.ms
0,0 → 1,46
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 2\n2\nffff\nffffffff\n1f\nffffffe0\n78134452\n0\n
 
.include "testutils.inc"
start
moveq -1,r3
andq 2,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
moveq 2,r3
andq -1,r3
test_move_cc 0 0 0 0
dumpr3 ; 2
 
move.d 0xffff,r3
andq -1,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
moveq -1,r3
andq -1,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq -1,r3
andq 31,r3
test_move_cc 0 0 0 0
dumpr3 ; 1f
 
moveq -1,r3
andq -32,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffe0
 
move.d 0x78134457,r3
andq -14,r3
test_move_cc 0 0 0 0
dumpr3 ; 78134452
 
moveq 0,r3
andq -14,r3
test_move_cc 0 1 0 0
dumpr3 ; 0
 
quit
/asm/addxc.ms
0,0 → 1,91
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 1\n1\n101\n10001\n100fe\n1fffe\nfffe\nfffe\nfffffffe\nfe\nfffffffe\n781344db\n781343db\n78143bdb\n78133bdb\n800000ed\n0\n
 
.include "testutils.inc"
start
moveq 2,r3
adds.b 0xff,r3
test_cc 0 0 0 1
dumpr3 ; 1
 
moveq 2,r3
adds.w 0xffff,r3
test_cc 0 0 0 1
dumpr3 ; 1
 
moveq 2,r3
addu.b 0xff,r3
dumpr3 ; 101
 
moveq 2,r3
move.d 0xffffffff,r4
addu.w -1,r3
test_cc 0 0 0 0
dumpr3 ; 10001
 
move.d 0xffff,r3
addu.b -1,r3
test_cc 0 0 0 0
dumpr3 ; 100fe
 
move.d 0xffff,r3
addu.w -1,r3
test_cc 0 0 0 0
dumpr3 ; 1fffe
 
move.d 0xffff,r3
adds.b 0xff,r3
test_cc 0 0 0 1
dumpr3 ; fffe
 
move.d 0xffff,r3
adds.w 0xffff,r3
test_cc 0 0 0 1
dumpr3 ; fffe
 
moveq -1,r3
adds.b 0xff,r3
test_cc 1 0 0 1
dumpr3 ; fffffffe
 
moveq -1,r3
adds.w 0xff,r3
test_cc 0 0 0 1
dumpr3 ; fe
 
moveq -1,r3
adds.w 0xffff,r3
test_cc 1 0 0 1
dumpr3 ; fffffffe
 
move.d 0x78134452,r3
addu.b 0x89,r3
test_cc 0 0 0 0
dumpr3 ; 781344db
 
move.d 0x78134452,r3
adds.b 0x89,r3
test_cc 0 0 0 1
dumpr3 ; 781343db
 
move.d 0x78134452,r3
addu.w 0xf789,r3
test_cc 0 0 0 0
dumpr3 ; 78143bdb
 
move.d 0x78134452,r3
adds.w 0xf789,r3
test_cc 0 0 0 1
dumpr3 ; 78133bdb
 
move.d 0x7fffffee,r3
addu.b 0xff,r3
test_cc 1 0 1 0
dumpr3 ; 800000ed
 
move.d 0x1,r3
adds.w 0xffff,r3
test_cc 0 1 0 1
dumpr3 ; 0
 
quit
/asm/clearfv10.ms
0,0 → 1,12
# mach: crisv10
# output: ef\n
 
; Check that "clearf x" doesn't trivially fail.
 
.include "testutils.inc"
start
setf mbixnzvc
clearf x ; Actually, x would be cleared by almost-all other insns.
move dccr,r3
dumpr3
quit
/asm/io1.ms
0,0 → 1,8
# mach: crisv32
# sim: --cris-900000xx --memory-region 0x90000000,0x10
# xerror:
# output: Seeing --cris-900000xx with memory defined there\n
 
; Check that I/O region overlap is detected.
 
.include "nopv32t.ms"
/asm/mulv32.ms
0,0 → 1,51
# mach: crisv32
# output: fffffffe\n
# output: ffffffff\n
# output: fffffffe\n
# output: 1\n
# output: fffffffe\n
# output: ffffffff\n
# output: fffffffe\n
# output: 1\n
 
; Check that carry is not modified on v32.
 
.include "testutils.inc"
start
moveq -1,r3
moveq 2,r4
setf c
muls.d r4,r3
test_cc 1 0 0 1
dumpr3 ; fffffffe
move mof,r3
dumpr3 ; ffffffff
 
moveq -1,r3
moveq 2,r4
setf c
mulu.d r4,r3
test_cc 0 0 1 1
dumpr3 ; fffffffe
move mof,r3
dumpr3 ; 1
 
moveq -1,r3
moveq 2,r4
clearf c
muls.d r4,r3
test_cc 1 0 0 0
dumpr3 ; fffffffe
move mof,r3
dumpr3 ; ffffffff
 
moveq -1,r3
moveq 2,r4
clearf c
mulu.d r4,r3
test_cc 0 0 1 0
dumpr3 ; fffffffe
move mof,r3
dumpr3 ; 1
 
quit
/asm/movsrpc.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
start
setf
movs.w r0,pc
quit
/asm/ret.ms
0,0 → 1,25
# mach: crisv3 crisv8 crisv10
# output: 3\n
 
# Test that ret works.
 
.include "testutils.inc"
start
x:
moveq 0,r3
jsr z
w:
quit
y:
addq 1,r3
dumpr3
quit
 
z:
addq 1,r3
move srp,r2
add.d y-w,r2
move r2,srp
ret
addq 1,r3
quit
/asm/movecr.ms
0,0 → 1,37
# mach: crisv3 crisv8 crisv10 crisv32
# output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n
 
; Move constant byte, word, dword to register. Check that no extension is
; performed, that only part of the register is set.
 
.include "testutils.inc"
startnostack
moveq -1,r3
move.b 0x42,r3
test_move_cc 0 0 0 0
dumpr3
 
moveq 0,r3
move.b 0x94,r3
test_move_cc 1 0 0 0
dumpr3
 
moveq -1,r3
move.w 0x4321,r3
test_move_cc 0 0 0 0
dumpr3
 
moveq 0,r3
move.w 0x9234,r3
test_move_cc 1 0 0 0
dumpr3
 
move.d 0x76543210,r3
test_move_cc 0 0 0 0
dumpr3
 
move.w 0,r3
test_move_cc 0 1 0 0
dumpr3
 
quit
/asm/movecpc.ms
0,0 → 1,19
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register * PC is not implemented.\nprogram stopped with signal 5.\n
 
# We deliberately match both "read from" and "write to" above.
 
.include "testutils.inc"
startnostack
moveq -1,r3
move.b 0x42,pc
dumpr3
 
move.w 0x4321,pc
dumpr3
 
move.d 0x76543210,pc
dumpr3
 
quit
/asm/opterr1.ms
0,0 → 1,5
# mach: crisv3 crisv8 crisv10 crisv32
# xerror:
# output: *: unrecognized option [`']--cris-stats=xyz'\n
# sim: --cris-stats=xyz
.include "nopv32t.ms"
/asm/x1-v10.ms
0,0 → 1,10
#mach: crisv10
#ld: --section-start=.text=0
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#output: a 0 0 0 0 0 ff004567 0 0 0 0 0 0 0 0 * ixNzvc 2\n
#sim: --cris-trace=basic
 
; With a "--cris-trace=all", cycles for the last line would be 3.
 
.include "movect10.ms"
/asm/movepcd.ms
0,0 → 1,16
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register * PC is not implemented.\nprogram stopped with signal 5.\n
 
# Both source and dest contain PC for "test.d r" (move.d r,r). Ideally,
# the output message should say "read" of PC, but we allow PC as source in
# a move.d r,R insn, so there's no logical way to get that, short of a
# special pattern, which would be just too ugly. The output message says
# "write", but let's match "read" too so we won't fail if things suddenly
# improve.
 
.include "testutils.inc"
startnostack
setf
test.d pc
quit
/asm/orm.ms
0,0 → 1,75
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 3\n3\nffff\nffffffff\n7c33f7db\nffff0003\n3\nfedaffff\n7813f7db\n3\n3\nfeb\n781344db\n
 
.include "testutils.inc"
.data
x:
.dword 2,1,0xff0f,-1,0x5432f789
.word 2,1,0xff5f,0xf789
.byte 2,1,0x4a,0x89
 
start
moveq 1,r3
move.d x,r5
or.d [r5+],r3
dumpr3 ; 3
 
moveq 2,r3
or.d [r5],r3
addq 4,r5
dumpr3 ; 3
 
move.d 0xf0ff,r3
or.d [r5+],r3
dumpr3 ; ffff
 
moveq -1,r3
or.d [r5+],r3
dumpr3 ; ffffffff
 
move.d 0x78134452,r3
or.d [r5+],r3
dumpr3 ; 7c33f7db
 
move.d 0xffff0001,r3
or.w [r5+],r3
dumpr3 ; ffff0003
 
moveq 2,r3
or.w [r5],r3
addq 2,r5
test_move_cc 0 0 0 0
dumpr3 ; 3
 
move.d 0xfedaffaf,r3
or.w [r5+],r3
test_move_cc 1 0 0 0
dumpr3 ; fedaffff
 
move.d 0x78134452,r3
or.w [r5+],r3
test_move_cc 1 0 0 0
dumpr3 ; 7813f7db
 
moveq 1,r3
or.b [r5+],r3
test_move_cc 0 0 0 0
dumpr3 ; 3
 
moveq 2,r3
or.b [r5],r3
addq 1,r5
test_move_cc 0 0 0 0
dumpr3 ; 3
 
move.d 0xfa3,r3
or.b [r5+],r3
test_move_cc 1 0 0 0
dumpr3 ; feb
 
move.d 0x78134453,r3
or.b [r5],r3
test_move_cc 1 0 0 0
dumpr3 ; 781344db
 
quit
/asm/raw14.ms
0,0 → 1,14
; Checking read-after-write: cycles included in "schedulable".
#mach: crisv32
#output: Schedulable clock cycles, total @: 6\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 2\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=schedulable
.include "raw4.ms"
/asm/io9.ms
0,0 → 1,21
# mach: crisv32
# ld: --section-start=.text=0
# xerror:
# output: ce11d0c\n
# output: core: 4 byte write to unmapped address 0x90000004 at 0x16\n
# output: program stopped with signal 11.\n
 
; Check invalid access valid with --cris-900000xx.
; "PASS" area.
 
.include "testutils.inc"
start
move.d 0x0ce11d0c,$r3
dumpr3
move.d 0x90000004,$acr
move.d $acr,[$acr]
move.d 0xbadc0de,$r3
dumpr3
0:
ba 0b
nop
/asm/tmvmrv32.ms
0,0 → 1,14
#mach: crisv32
#output: Basic clock cycles, total @: 17\n
#output: Memory source stall cycles: 1\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 10\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
 
.include "tmvmrv10.ms"
/asm/op3.ms
0,0 → 1,98
# mach: crisv0 crisv3 crisv8 crisv10
# output: ee19cd0b\nee197761\nccff2244\n55aa77ff\nffffaa77\naa\n4243ab11\n424377ab\nfdedaaf0\n4242dd68\n4242dd68\n40025567\n57eb77ff\n55aa77ff\n
 
.include "testutils.inc"
.data
x:
.dword 0x55aa77ff
.dword 0xccff2244
.dword 0x88ccee19
 
start
move.d x,r10
moveq 0,r3
moveq 12,r4
add.d [r10+6],r4,r3
test_cc 1 0 0 0
dumpr3 ; ee19cd0b
 
move.d 0x1267,r7
subu.w [r10+2],r3,r8
test_cc 1 0 0 0
move.d r8,r3
dumpr3 ; ee197761
 
moveq 1,r8
bound.d [r10+r8.d],r3,r5
test_move_cc 1 0 0 0
move.d r5,r3
dumpr3 ; ccff2244
 
; Also applies to move insns. Bleah.
moveq 0,r5
bdap 0,r10
move.d [r3],r5
test_move_cc 0 0 0 0
dumpr3 ; 55aa77ff
 
moveq 0,r5
bdap 1,r10
movs.w [r3],r5
test_move_cc 1 0 0 0
dumpr3 ; ffffaa77
 
moveq 0,r5
bdap 2,r10
movu.b [r3],r5
test_move_cc 0 0 0 0
dumpr3 ; aa
 
move.d 0x42435567,r8
bdap 2,r10
adds.w [r3],r8
test_cc 0 0 0 0
dumpr3 ; 4243ab11
 
move.d 0x42435567,r8
bdap 4,r10
addu.w [r3],r8
test_cc 0 0 0 0
dumpr3 ; 424377ab
 
move.d 0x42435567,r8
bdap 1,r10
sub.d [r3],r8
test_cc 1 0 0 1
dumpr3 ; fdedaaf0
 
move.d 0x42435567,r8
bdap 0,r10
subs.w [r3],r8
test_cc 0 0 0 0
dumpr3 ; 4242dd68
 
move.d 0x42435567,r8
bdap 0,r10
subu.w [r3],r8
test_cc 0 0 0 0
dumpr3 ; 4242dd68
 
move.d 0x42435567,r8
bdap 0,r10
and.d [r3],r8
test_move_cc 0 0 0 0
dumpr3 ; 40025567
 
move.d 0x42435567,r8
bdap 0,r10
or.d [r3],r8
test_move_cc 0 0 0 0
dumpr3 ; 57eb77ff
 
move.d 0xc2435567,r8
bdap 0,r10
bound.d [r3],r8
test_move_cc 0 0 0 0
dumpr3 ; 55aa77ff
 
quit
/asm/moverpcw.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
startnostack
setf
move.w pc,r2
quit
/asm/jsrmv10.ms
0,0 → 1,40
# mach: crisv3 crisv8 crisv10
# output: 23\n
 
# Test that jsr [] records the correct return-address.
 
.include "testutils.inc"
start
x:
moveq 0,r3
jsr [z]
addq 1,r3
nop
nop
nop
nop
nop
move.d w,r2
jsr [r2]
addq 1,r3
nop
nop
nop
nop
nop
dumpr3 ; 23
quit
y:
ret
addq 1,r3
quit
 
v:
ret
addq 32,r3
quit
 
z:
.dword y
w:
.dword v
/asm/subxr.ms
0,0 → 1,108
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 3\n3\nffffff03\nffff0003\nff00\n0\n10000\n10000\n0\nffffff00\n0\n781343c9\n781344c9\n78124cc9\n78134cc9\nc450\n7ffff8ce\n
 
.include "testutils.inc"
start
moveq 2,r3
move.d 0xff,r4
subs.b r4,r3
test_cc 0 0 0 1
dumpr3 ; 3
 
moveq 2,r3
move.d 0xffff,r4
subs.w r4,r3
test_cc 0 0 0 1
dumpr3 ; 3
 
moveq 2,r3
move.d 0xffff,r4
subu.b r4,r3
test_cc 1 0 0 1
dumpr3 ; ffffff03
 
moveq 2,r3
move.d 0xffffffff,r4
subu.w r4,r3
test_cc 1 0 0 1
dumpr3 ; ffff0003
 
move.d 0xffff,r3
move.d 0xffffffff,r4
subu.b r4,r3
test_cc 0 0 0 0
dumpr3 ; ff00
 
move.d 0xffff,r3
move.d 0xffffffff,r4
subu.w r4,r3
test_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0xffff,r3
move.d 0xff,r4
subs.b r4,r3
test_cc 0 0 0 1
dumpr3 ; 10000
 
move.d 0xffff,r4
move.d r4,r3
subs.w r4,r3
test_cc 0 0 0 1
dumpr3 ; 10000
 
moveq -1,r3
move.d 0xff,r4
subs.b r4,r3
test_cc 0 1 0 0
dumpr3 ; 0
 
moveq -1,r3
move.d 0xff,r4
subs.w r4,r3
test_cc 1 0 0 0
dumpr3 ; ffffff00
 
moveq -1,r3
move.d 0xffff,r4
subs.w r4,r3
test_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
subu.b r4,r3
test_cc 0 0 0 0
dumpr3 ; 781343c9
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
subs.b r4,r3
test_cc 0 0 0 1
dumpr3 ; 781344c9
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
subu.w r4,r3
test_cc 0 0 0 0
dumpr3 ; 78124cc9
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
subs.w r4,r3
test_cc 0 0 0 1
dumpr3 ; 78134cc9
 
move.d 0x4452,r3
move.d 0x78568002,r4
subs.w r4,r3
test_cc 0 0 0 1
dumpr3 ; c450
 
move.d 0x80000032,r3
move.d 0xffff0764,r4
subu.w r4,r3
test_cc 0 0 1 0
dumpr3 ; 7ffff8ce
 
quit
/asm/x9-v10.ms
0,0 → 1,23
#mach: crisv10
#ld: --section-start=.text=0
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n
#output: 4 0 0 0 0 0 0 0 0 0 1 0 0 0 0 * ixnzvc 1\n
#output: 10 0 0 0 0 0 0 0 0 0 1 0 0 0 0 * ixnzvc 4\n
#output: 12 0 0 0 0 0 0 0 0 0 1 0 0 0 0 * ixnzvc 1\n
#sim: --cris-trace=basic
 
; Check that "adds.w [$pc+$r9.w],$pc" gets 4 cycles.
 
.include "testutils.inc"
startnostack
moveq 1,r9
adds.w [$pc+$r9.w],$pc
0:
.word 1f-0b
.word 2f-0b
.word 1f-0b
1:
break 15
2:
nop
break 15
/asm/movemr.ms
0,0 → 1,79
# mach: crisv3 crisv8 crisv10 crisv32
# output: 12345678\n10234567\n12345678\n12344567\n12344523\n76543210\nffffffaa\naa\n9911\nffff9911\n78\n56\n3456\n6712\n
 
.include "testutils.inc"
start
 
.data
mem1:
.dword 0x12345678
mem2:
.word 0x4567
mem3:
.byte 0x23
.dword 0x76543210
.byte 0xaa,0x11,0x99
 
.text
move.d mem1,r2
move.d [r2],r3
test_move_cc 0 0 0 0
dumpr3
 
move.d mem2,r3
move.d [r3],r3
test_move_cc 0 0 0 0
dumpr3
 
move.d mem1,r2
move.d [r2+],r3
test_move_cc 0 0 0 0
dumpr3
 
move.w [r2+],r3
test_move_cc 0 0 0 0
dumpr3
 
move.b [r2+],r3
test_move_cc 0 0 0 0
dumpr3
 
move.d [r2+],r3
test_move_cc 0 0 0 0
dumpr3
 
movs.b [r2],r3
test_move_cc 1 0 0 0
dumpr3
 
movu.b [r2+],r3
test_move_cc 0 0 0 0
dumpr3
 
movu.w [r2],r3
test_move_cc 0 0 0 0
dumpr3
 
movs.w [r2+],r3
test_move_cc 1 0 0 0
dumpr3
 
move.d mem1,r13
movs.b [r13+],r3
test_move_cc 0 0 0 0
dumpr3
 
movu.b [r13],r3
test_move_cc 0 0 0 0
dumpr3
 
movs.w [r13+],r3
test_move_cc 0 0 0 0
dumpr3
 
movu.w [r13+],r3
test_move_cc 0 0 0 0
dumpr3
 
quit
 
/asm/tb.ms
0,0 → 1,72
#mach: crisv32
#output: Basic clock cycles, total @: 54\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 18\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
 
; Check branch penalties. It is assumed that the taken-counters
; in the bimodal branch-predictors start at 0, meaning two taken
; branches are required for a branch to be predicted as taken
; for each counter, from reset. None of these branches go
; to the end of a cache-line and none map to the same counter.
 
.include "testutils.inc"
startnostack
ba 0f ; No penalty: always-taken condition not "predicted".
nop
nop
0:
setf c
bcs 0f ; Penalty 2 cycles.
nop
 
nop
0:
clearf c
bcc 0f ; Penalty 2 cycles, though branch is a nop.
moveq 4,r0 ; Execute 5 times:
 
0:
move.d r0,r0
bne 0b ; Mispredicted 3 out of 5 times: penalty 3*2 cycles.
subq 1,r0
 
0:
beq 0f ; Not taken; no penalty.
nop
 
nop
0:
 
; (Almost) same insns, but with 16-bit bCC insns.
 
ba 0f ; No penalty: always-taken condition not "predicted".
nop
.space 520
0:
setf c
bcs 0f ; Penalty 2 cycles.
nop
 
.space 520
0:
moveq 4,r0 ; Execute 5 times:
0:
ba 1f
move.d r0,r0 ; Mispredicted 3 out of 5 times:
.space 520
1:
bne 0b ; Penalty 3*2 cycles.
subq 1,r0
 
beq 0f ; Not taken; no penalty.
nop
0:
break 15
/asm/x7-v32.ms
0,0 → 1,19
#mach: crisv32
#ld: --section-start=.text=0
#sim: --cris-trace=basic
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n
#output: 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixNzvc 1 aa424243\n
#output: a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 55212121\n
#output: c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 1\n
#output: e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
 
; Check that trace with changing ACR works.
 
.include "testutils.inc"
startnostack
move.d 0xaa424243,$acr
lsrq 1,$acr
moveq 1,$acr
clear.d $acr
break 15
nop
/asm/xor.ms
0,0 → 1,47
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 3\n3\nff0\n0\n2c21b3db\n0\nffffffff\n
 
.include "testutils.inc"
start
moveq 1,r3
moveq 2,r4
xor r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 3
 
moveq 2,r3
moveq 1,r4
xor r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 3
 
move.d 0xff0f,r4
move.d 0xf0ff,r3
xor r4,r3
test_move_cc 0 0 0 0
dumpr3 ; ff0
 
moveq -1,r4
move.d r4,r3
xor r4,r3
test_move_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
xor r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 2c21b3db
 
moveq 0,r4
moveq 0,r3
xor r4,r3
test_move_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0x7fffffff,r3
move.d 0x80000000,r4
xor r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
quit
/asm/tjmpsrv32-2.ms
0,0 → 1,55
#mach: crisv32
#output: Basic clock cycles, total @: 37\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 6\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
 
; Check that we correctly account for that a "jas N,Pn",
; "jasc N,Pn", "bas N,Pn" and "basc N,Pn" sets the specific
; special register and causes a pipeline hazard. The amount
; of nops below is a bit inflated, in an attempt to make
; errors more discernible. For special registers, we just
; check SRP.
 
.include "testutils.inc"
startnostack
move.d 0f,$r0
jsr 0f
nop
nop
nop
jsrc 0f
nop
.dword -1
nop
nop
jsr $r0
nop
nop
nop
jsrc $r0
nop
.dword -1
nop
nop
bsr 0f
nop
nop
nop
bsrc 0f
nop
.dword -1
nop
nop
break 15
 
0:
ret ; 1 cycle penalty.
nop
/asm/addr.ms
0,0 → 1,96
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n
 
.include "testutils.inc"
start
moveq -1,r3
moveq 2,r4
add.d r4,r3
test_cc 0 0 0 1
dumpr3 ; 1
 
moveq 2,r3
moveq -1,r4
add.d r4,r3
test_cc 0 0 0 1
dumpr3 ; 1
 
move.d 0xffff,r4
move.d r4,r3
add.d r4,r3
test_cc 0 0 0 0
dumpr3 ; 1fffe
 
moveq -1,r4
move.d r4,r3
add.d r4,r3
test_cc 1 0 0 1
dumpr3 ; fffffffe
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
add.d r4,r3
test_cc 1 0 1 0
dumpr3 ; cc463bdb
 
moveq -1,r3
moveq 2,r4
add.w r4,r3
test_cc 0 0 0 1
dumpr3 ; ffff0001
 
moveq 2,r3
moveq -1,r4
add.w r4,r3
test_cc 0 0 0 1
dumpr3 ; 1
 
move.d 0xffff,r4
move.d r4,r3
add.w r4,r3
test_cc 1 0 0 1
dumpr3 ; fffe
 
move.d 0xfedaffff,r4
move.d r4,r3
add.w r4,r3
test_cc 1 0 0 1
dumpr3 ; fedafffe
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
add.w r4,r3
test_cc 0 0 0 1
dumpr3 ; 78133bdb
 
moveq -1,r3
moveq 2,r4
add.b r4,r3
test_cc 0 0 0 1
dumpr3 ; ffffff01
 
moveq 2,r3
moveq -1,r4
add.b r4,r3
test_cc 0 0 0 1
dumpr3 ; 1
 
move.d 0xff,r4
move.d r4,r3
add.b r4,r3
test_cc 1 0 0 1
dumpr3 ; fe
 
move.d 0xfeda49ff,r4
move.d r4,r3
add.b r4,r3
test_cc 1 0 0 1
dumpr3 ; feda49fe
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
add.b r4,r3
test_cc 1 0 0 0
dumpr3 ; 781344db
 
quit
/asm/cmpxc.ms
0,0 → 1,92
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 2\n2\n2\n2\nffff\nffff\nffff\nffff\nffffffff\nffffffff\nffffffff\n78134452\n78134452\n78134452\n78134452\n4452\n80000032\n
 
.include "testutils.inc"
start
moveq 2,r3
cmps.b 0xff,r3
test_cc 0 0 0 1
dumpr3 ; 2
 
moveq 2,r3
cmps.w 0xffff,r3
test_cc 0 0 0 1
dumpr3 ; 2
 
moveq 2,r3
cmpu.b 0xff,r3
test_cc 1 0 0 1
dumpr3 ; 2
 
moveq 2,r3
move.d 0xffffffff,r4
cmpu.w -1,r3
test_cc 1 0 0 1
dumpr3 ; 2
 
move.d 0xffff,r3
cmpu.b -1,r3
test_cc 0 0 0 0
dumpr3 ; ffff
 
move.d 0xffff,r3
cmpu.w -1,r3
test_cc 0 1 0 0
dumpr3 ; ffff
 
move.d 0xffff,r3
cmps.b 0xff,r3
test_cc 0 0 0 1
dumpr3 ; ffff
 
move.d 0xffff,r3
cmps.w 0xffff,r3
test_cc 0 0 0 1
dumpr3 ; ffff
 
moveq -1,r3
cmps.b 0xff,r3
test_cc 0 1 0 0
dumpr3 ; ffffffff
 
moveq -1,r3
cmps.w 0xff,r3
test_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq -1,r3
cmps.w 0xffff,r3
test_cc 0 1 0 0
dumpr3 ; ffffffff
 
move.d 0x78134452,r3
cmpu.b 0x89,r3
test_cc 0 0 0 0
dumpr3 ; 78134452
 
move.d 0x78134452,r3
cmps.b 0x89,r3
test_cc 0 0 0 1
dumpr3 ; 78134452
 
move.d 0x78134452,r3
cmpu.w 0xf789,r3
test_cc 0 0 0 0
dumpr3 ; 78134452
 
move.d 0x78134452,r3
cmps.w 0xf789,r3
test_cc 0 0 0 1
dumpr3 ; 78134452
 
move.d 0x4452,r3
cmps.w 0x8002,r3
test_cc 0 0 0 1
dumpr3 ; 4452
 
move.d 0x80000032,r3
cmpu.w 0x764,r3
test_cc 0 0 1 0
dumpr3 ; 80000032
 
quit
/asm/movucr.ms
0,0 → 1,33
# mach: crisv3 crisv8 crisv10 crisv32
# output: 42\n85\n7685\n8765\n0\n
 
; Move constant byte, word, dword to register. Check that zero-extension
; is performed.
 
.include "testutils.inc"
start
moveq -1,r3
movu.b 0x42,r3
test_move_cc 0 0 0 0
dumpr3
 
moveq -1,r3
movu.b 0x85,r3
test_move_cc 0 0 0 0
dumpr3
 
moveq -1,r3
movu.w 0x7685,r3
test_move_cc 0 0 0 0
dumpr3
 
moveq -1,r3
movu.w 0x8765,r3
test_move_cc 0 0 0 0
dumpr3
 
movu.b 0,r3
test_move_cc 0 1 0 0
dumpr3
 
quit
/asm/movucpc.ms
0,0 → 1,10
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
start
movu.w 0x4321,pc
dumpr3
 
quit
/asm/movdelsr1.ms
0,0 → 1,33
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: aa117acd\n
# output: eeaabb42\n
 
; Bug with move to special register in delay slot, due to
; special flush-insn-cache simulator use. Ordinary move worked;
; special register caused branch to fail.
 
.include "testutils.inc"
start
move -1,srp
 
move.d 0xaa117acd,r1
moveq 3,r9
cmpq 1,r9
bhi 0f
move.d r1,r3
 
fail
0:
dumpr3
 
move.d 0xeeaabb42,r1
moveq 3,r9
cmpq 1,r9
bhi 0f
move r1,srp
 
fail
0:
move srp,r3
dumpr3
quit
/asm/moverpcb.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
startnostack
setf
move.b pc,r5
quit
/asm/raw4.ms
0,0 → 1,22
; Checking read-after-write: write-then-read 2 cycles.
#mach: crisv32
#output: Basic clock cycles, total @: 4\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 2\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "testutils.inc"
startnostack
.lcomm x,4
.lcomm y,4
move.d x,$r0
move.d y,$r1
move.d $r1,[$r0]
move.d [$r1],$r2
break 15
/asm/user.ms
0,0 → 1,75
# mach: crisv32
# output: 40\n40\n140\nabadefb0\n6543789c\n0\n0\n0\n0\n0\n0\n0\n0\n
 
; Check for protected operations being NOP in user mode, for the
; parts implemented in this simulator.
 
.include "testutils.inc"
start
move 0,ccs
move 0,usp
move 0,pid
move 0,srs
move 0,ebp
move 0,spc
setf u
 
; Flag settings, besides what's tested in rfn.ms, rfe.ms and
; sfe.ms.
setf i
move ccs,r3
dumpr3 ; 0x40
 
clearf u
move ccs,r3
dumpr3 ; 0x40
 
move 0xc0000300,ccs
move ccs,r3
dumpr3 ; 0x140
 
; R14==USP
move.d 0xabadefb0,r14
nop
nop
nop
move usp,r3
dumpr3 ; 0xabadefb0
move 0x6543789c,usp
nop
nop
nop
move.d r14,r3
dumpr3 ; 0x6543789c
 
; We can't go back to kernel mode, so we can't check that R14 in
; kernel mode wasn't affected.
 
; Moves to protected special registers.
.macro testsr reg,val=-1
move \val,\reg
; Registers shorter than dword will not affect the rest of the
; general register when copied using a move insn.
clear.d r3
; Three cycles are needed between move to protected register and
; read from it, to avoid reading undefined contents due to
; incomplete forwarding.
nop
nop
move \reg,r3
dumpr3
moveq \val,r3
move r3,\reg
clear.d r3
nop
nop
move \reg,r3
dumpr3
.endm
 
testsr pid ; 0 0
testsr srs,3 ; 0 0
testsr ebp ; 0 0
testsr spc ; 0 0
 
quit
/asm/movecrt32.ms
0,0 → 1,14
#mach: crisv32
#output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n
#output: Basic clock cycles, total @: 82\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "movecr.ms"
/asm/lz.ms
0,0 → 1,52
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 0\n20\n0\n1\n1\n1a\n1f\n10\n1e\n
 
.include "testutils.inc"
start
moveq -1,r3
 
lz r3,r3
test_move_cc 0 1 0 0
dumpr3 ; 0
 
moveq 0,r3
lz r3,r3
test_move_cc 0 0 0 0
dumpr3 ; 20
 
move.d 0x80000000,r4
lz r4,r3
test_move_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0x40000000,r4
lz r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 1
 
move.d 0x7fffffff,r4
lz r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 1
 
move.d 42,r3
lz r3,r3
test_move_cc 0 0 0 0
dumpr3 ; 1a
 
moveq 1,r6
lz r6,r3
test_move_cc 0 0 0 0
dumpr3 ; 1f
 
move.d 0xffff,r3
lz r3,r3
test_move_cc 0 0 0 0
dumpr3 ; 10
 
moveq 2,r5
lz r5,r3
test_move_cc 0 0 0 0
dumpr3 ; 1e
 
quit
/asm/mulx.ms
0,0 → 1,246
# mach: crisv10 crisv32
# output: fffffffe\nffffffff\nfffffffe\n1\nfffffffe\nffffffff\nfffffffe\n1\nfffe0001\n0\nfffe0001\n0\n1\n0\n1\nfffffffe\n193eade2\n277e3a49\n193eade2\n277e3a49\nfffffffe\nffffffff\n1fffe\n0\nfffffffe\nffffffff\n1fffe\n0\n1\n0\nfffe0001\n0\nfdbdade2\nffffffff\n420fade2\n0\nfffffffe\nffffffff\n1fe\n0\nfffffffe\nffffffff\n1fe\n0\n1\n0\nfe01\n0\n1\n0\nfe01\n0\nffffd9e2\nffffffff\n2be2\n0\n0\n0\n0\n0\n
 
.include "testutils.inc"
start
moveq -1,r3
moveq 2,r4
muls.d r4,r3
test_cc 1 0 0 0
dumpr3 ; fffffffe
move mof,r3
dumpr3 ; ffffffff
 
moveq -1,r3
moveq 2,r4
mulu.d r4,r3
test_cc 0 0 1 0
dumpr3 ; fffffffe
move mof,r3
dumpr3 ; 1
 
moveq 2,r3
moveq -1,r4
muls.d r4,r3
test_cc 1 0 0 0
dumpr3 ; fffffffe
move mof,r3
dumpr3 ; ffffffff
 
moveq 2,r3
moveq -1,r4
mulu.d r4,r3
test_cc 0 0 1 0
dumpr3 ; fffffffe
move mof,r3
dumpr3 ; 1
 
move.d 0xffff,r4
move.d r4,r3
muls.d r4,r3
test_cc 0 0 1 0
dumpr3 ; fffe0001
move mof,r3
dumpr3 ; 0
 
move.d 0xffff,r4
move.d r4,r3
mulu.d r4,r3
test_cc 0 0 0 0
dumpr3 ; fffe0001
move mof,r3
dumpr3 ; 0
 
moveq -1,r4
move.d r4,r3
muls.d r4,r3
test_cc 0 0 0 0
dumpr3 ; 1
move mof,r3
dumpr3 ; 0
 
moveq -1,r4
move.d r4,r3
mulu.d r4,r3
test_cc 1 0 1 0
dumpr3 ; 1
move mof,r3
dumpr3 ; fffffffe
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
muls.d r4,r3
test_cc 0 0 1 0
dumpr3 ; 193eade2
move mof,r3
dumpr3 ; 277e3a49
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
mulu.d r4,r3
test_cc 0 0 1 0
dumpr3 ; 193eade2
move mof,r3
dumpr3 ; 277e3a49
 
move.d 0xffff,r3
moveq 2,r4
muls.w r4,r3
test_cc 1 0 0 0
dumpr3 ; fffffffe
move mof,r3
dumpr3 ; ffffffff
 
moveq -1,r3
moveq 2,r4
mulu.w r4,r3
test_cc 0 0 0 0
dumpr3 ; 1fffe
move mof,r3
dumpr3 ; 0
 
moveq 2,r3
move.d 0xffff,r4
muls.w r4,r3
test_cc 1 0 0 0
dumpr3 ; fffffffe
move mof,r3
dumpr3 ; ffffffff
 
moveq 2,r3
moveq -1,r4
mulu.w r4,r3
test_cc 0 0 0 0
dumpr3 ; 1fffe
move mof,r3
dumpr3 ; 0
 
move.d 0xffff,r4
move.d r4,r3
muls.w r4,r3
test_cc 0 0 0 0
dumpr3 ; 1
move mof,r3
dumpr3 ; 0
 
moveq -1,r4
move.d r4,r3
mulu.w r4,r3
test_cc 0 0 0 0
dumpr3 ; fffe0001
move mof,r3
dumpr3 ; 0
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
muls.w r4,r3
test_cc 1 0 0 0
dumpr3 ; fdbdade2
move mof,r3
dumpr3 ; ffffffff
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
mulu.w r4,r3
test_cc 0 0 0 0
dumpr3 ; 420fade2
move mof,r3
dumpr3 ; 0
 
move.d 0xff,r3
moveq 2,r4
muls.b r4,r3
test_cc 1 0 0 0
dumpr3 ; fffffffe
move mof,r3
dumpr3 ; ffffffff
 
moveq -1,r3
moveq 2,r4
mulu.b r4,r3
test_cc 0 0 0 0
dumpr3 ; 1fe
move mof,r3
dumpr3 ; 0
 
moveq 2,r3
moveq -1,r4
muls.b r4,r3
test_cc 1 0 0 0
dumpr3 ; fffffffe
move mof,r3
dumpr3 ; ffffffff
 
moveq 2,r3
moveq -1,r4
mulu.b r4,r3
test_cc 0 0 0 0
dumpr3 ; 1fe
move mof,r3
dumpr3 ; 0
 
move.d 0xff,r4
move.d r4,r3
muls.b r4,r3
test_cc 0 0 0 0
dumpr3 ; 1
move mof,r3
dumpr3 ; 0
 
moveq -1,r4
move.d r4,r3
mulu.b r4,r3
test_cc 0 0 0 0
dumpr3 ; fe01
move mof,r3
dumpr3 ; 0
 
move.d 0xfeda49ff,r4
move.d r4,r3
muls.b r4,r3
test_cc 0 0 0 0
dumpr3 ; 1
move mof,r3
dumpr3 ; 0
 
move.d 0xfeda49ff,r4
move.d r4,r3
mulu.b r4,r3
test_cc 0 0 0 0
dumpr3 ; fe01
move mof,r3
dumpr3 ; 0
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
muls.b r4,r3
test_cc 1 0 0 0
dumpr3 ; ffffd9e2
move mof,r3
dumpr3 ; ffffffff
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
mulu.b r4,r3
test_cc 0 0 0 0
dumpr3 ; 2be2
move mof,r3
dumpr3 ; 0
 
moveq 0,r3
move.d 0xf87f4aeb,r4
muls.d r4,r3
test_cc 0 1 0 0
dumpr3 ; 0
move mof,r3
dumpr3 ; 0
 
move.d 0xf87f4aeb,r3
moveq 0,r4
mulu.d r4,r3
test_cc 0 1 0 0
dumpr3 ; 0
move mof,r3
dumpr3 ; 0
 
quit
/asm/addcv32c.ms
0,0 → 1,50
# mach: crisv32
# output: 0\n0\n1\n1\n2\n1ffff\nfffffffe\ncc463bdc\n
 
.include "testutils.inc"
start
clearf cz
moveq 0,r3
addc 0,r3
test_cc 0 0 0 0
dumpr3 ; 0
 
setf z
moveq 0,r3
addc 0,r3
test_cc 0 1 0 0
dumpr3 ; 0
 
setf cz
moveq 0,r3
addc 0,r3
test_cc 0 0 0 0
dumpr3 ; 1
 
clearf c
moveq -1,r3
addc 2,r3
test_cc 0 0 0 1
dumpr3 ; 1+c
 
moveq 2,r3
addc -1,r3
test_cc 0 0 0 1
dumpr3 ; 2+c
 
move.d 0xffff,r3
addc 0xffff,r3
test_cc 0 0 0 0
dumpr3 ; 1ffff
 
moveq -1,r3
addc -1,r3
test_cc 1 0 0 1
dumpr3 ; fffffffe+c
 
move.d 0x78134452,r3
addc 0x5432f789,r3
test_cc 1 0 1 0
dumpr3 ; cc463bdc
 
quit
/asm/option1.ms
0,0 → 1,7
#mach: crisv0 crisv3 crisv8 crisv10 crisv32
#sim: --cris-trace=foo
#xerror:
#output: Unknown option `--cris-trace=foo'\n
.include "testutils.inc"
start
fail
/asm/io4.ms
0,0 → 1,18
# mach: crisv32
# xerror:
# output: b1e\n
 
; Check correct "fail" exit.
 
.include "testutils.inc"
start
move.d 0xb1e,$r3
dumpr3
moveq 1,$r9
moveq 2,$r10
break 13
move.d 0xbadc0de,$r3
dumpr3
0:
ba 0b
nop
/asm/x0-v10.ms
0,0 → 1,7
#mach: crisv10
#ld: --section-start=.text=0
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[0-9a-f][0-9a-f][0-9a-f] ixnzvc 0\n
#output: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3dfff[0-9a-f][0-9a-f][0-9a-f] ixnzvc 1\n
#sim: --cris-trace=basic
 
.include "break.ms"
/asm/addqpc.ms
0,0 → 1,8
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
start
addq 1,pc
 
/asm/nopv32t2.ms
0,0 → 1,13
#mach: crisv10 crisv32
#output: Clock cycles including stall cycles for unaligned accesses @: 5\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=unaligned
.include "nopv32t.ms"
/asm/movprv32.ms
0,0 → 1,21
# mach: crisv32
# output: ffffff20\nbb113344\n
 
# Test v32-specific special registers. FIXME: more registers.
 
.include "testutils.inc"
start
moveq -1,r3
setf zcvn
move vr,r3
test_cc 1 1 1 1
dumpr3
 
moveq -1,r3
move.d 0xbb113344,r4
clearf cvnz
move r4,mof
test_cc 0 0 0 0
move mof,r3
dumpr3
quit
/asm/movect10.ms
0,0 → 1,18
#mach: crisv10
#output: Basic clock cycles, total @: 3\n
#output: Memory source stall cycles: 1\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
 
.include "testutils.inc"
startnostack
nop
move.d 0xff004567,r5
break 15
/asm/subxm.ms
0,0 → 1,106
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 3\n3\nffffff03\nffff0003\nff00\n0\n10000\n10000\n0\nffffff00\n0\n781343c9\n781344c9\n78124cc9\n78134cc9\nc450\n7ffff8ce\n
 
.include "testutils.inc"
.data
x:
.byte 0xff
.word 0xffff
.word 0xff
.word 0xffff
.byte 0x89
.word 0xf789
.word 0x8002
.word 0x764
 
start
moveq 2,r3
move.d x,r5
subs.b [r5+],r3
test_cc 0 0 0 1
dumpr3 ; 3
 
moveq 2,r3
subs.w [r5+],r3
test_cc 0 0 0 1
dumpr3 ; 3
 
moveq 2,r3
subq 3,r5
subu.b [r5+],r3
test_cc 1 0 0 1
dumpr3 ; ffffff03
 
moveq 2,r3
subu.w [r5+],r3
test_cc 1 0 0 1
subq 3,r5
dumpr3 ; ffff0003
 
move.d 0xffff,r3
subu.b [r5],r3
test_cc 0 0 0 0
dumpr3 ; ff00
 
move.d 0xffff,r3
subu.w [r5],r3
test_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0xffff,r3
subs.b [r5],r3
test_cc 0 0 0 1
dumpr3 ; 10000
 
move.d 0xffff,r3
subs.w [r5],r3
test_cc 0 0 0 1
dumpr3 ; 10000
 
moveq -1,r3
subs.b [r5],r3
test_cc 0 1 0 0
addq 3,r5
dumpr3 ; 0
 
moveq -1,r3
subs.w [r5+],r3
test_cc 1 0 0 0
dumpr3 ; ffffff00
 
moveq -1,r3
subs.w [r5+],r3
test_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0x78134452,r3
subu.b [r5],r3
test_cc 0 0 0 0
dumpr3 ; 781343c9
 
move.d 0x78134452,r3
subs.b [r5+],r3
test_cc 0 0 0 1
dumpr3 ; 781344c9
 
move.d 0x78134452,r3
subu.w [r5],r3
test_cc 0 0 0 0
dumpr3 ; 78124cc9
 
move.d 0x78134452,r3
subs.w [r5+],r3
test_cc 0 0 0 1
dumpr3 ; 78134cc9
 
move.d 0x4452,r3
subs.w [r5+],r3
test_cc 0 0 0 1
dumpr3 ; c450
 
move.d 0x80000032,r3
subu.w [r5+],r3
test_cc 0 0 1 0
dumpr3 ; 7ffff8ce
 
quit
/asm/opterr4.ms
0,0 → 1,7
# mach: crisv3 crisv8 crisv10 crisv32
# xerror:
# output: Invalid option [`']--cris-start-address=x'\n
# sim: --cris-start-address=x
.include "nopv32t.ms"
 
; Check that we recognize wrong usage of the --cris-start-address option.
/asm/movemrv32.ms
0,0 → 1,97
# mach: crisv32
# output: 15\n7\n2\nffff1234\nb\n16\nf\n2\nffffffef\nf\nffff1234\nf\nfffffff4\nd\nfffffff2\n10\nfffffff2\nd\n
 
.include "testutils.inc"
.data
x:
.dword 8,9,10,11
y:
.dword -12,13,-14,15,16
 
start
moveq 7,r0
moveq 2,r1
move.d 0xffff1234,r2
moveq 21,r3
move.d x,r4
setf zcvn
movem r2,[r4+]
test_cc 1 1 1 1
subq 12,r4
 
dumpr3 ; 15
 
move.d [r4+],r3
dumpr3 ; 7
 
move.d [r4+],r3
dumpr3 ; 2
 
move.d [r4+],r3
dumpr3 ; ffff1234
 
move.d [r4+],r3
dumpr3 ; b
 
subq 16,r4
moveq 22,r0
moveq 15,r1
clearf zcvn
movem r0,[r4]
test_cc 0 0 0 0
move.d [r4+],r3
dumpr3 ; 16
 
move.d r1,r3
dumpr3 ; f
 
move.d [r4+],r3
dumpr3 ; 2
 
subq 8,r4
moveq 10,r2
moveq -17,r0
clearf zc
setf vn
movem r1,[r4]
test_cc 1 0 1 0
move.d [r4+],r3
dumpr3 ; ffffffef
 
move.d [r4+],r3
dumpr3 ; f
 
move.d [r4+],r3
dumpr3 ; ffff1234
 
move.d y,r4
setf zc
clearf vn
movem [r4+],r3
test_cc 0 1 0 1
dumpr3 ; f
 
move.d r0,r3
dumpr3 ; fffffff4
 
move.d r1,r3
dumpr3 ; d
 
move.d r2,r3
dumpr3 ; fffffff2
 
move.d [r4],r3
dumpr3 ; 10
 
subq 8,r4
setf zcvn
movem [r4+],r0
test_cc 1 1 1 1
move.d r0,r3
dumpr3 ; fffffff2
 
move.d r1,r3
dumpr3 ; d
 
quit
 
/asm/raw17.ms
0,0 → 1,29
; Checking read-after-write: different read-after-write combinations.
#mach: crisv32
#output: Basic clock cycles, total @: 11\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 8\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "testutils.inc"
startnostack
.lcomm x,4
.lcomm y,4
move.d x,$r0
move.d y,$r1
move.d $r1,[$r0]
move.d [$r1],$r2
move.d [$r1],$r2
clear.d [$r0]
move.d [$r1],$r2
movem $r0,[$r1]
movem [$r1],$r0
move $srp,[$r1]
move.d [$r1],$r0
break 15
/asm/x8-v10.ms
0,0 → 1,20
#mach: crisv10
#ld: --section-start=.text=0
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0\n
#output: 8 0 0 0 0 0 10 0 0 0 0 0 0 0 0 * ixnzvc 2\n
#output: c 0 0 0 0 0 10 0 0 0 0 0 0 0 0 * ixnzvc 2\n
#output: e 0 0 0 0 0 10 0 0 0 0 0 0 0 0 * ixnzvc 1\n
#sim: --cris-trace=basic
 
; Check that "jump [rN]" gets 2 cycles.
 
.include "testutils.inc"
startnostack
move.d 0f,r5
jump [r5]
break 15
1:
nop
break 15
0:
.dword 1b
/asm/addm.ms
0,0 → 1,96
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 1\n1\n1fffe\nfffffffe\ncc463bdb\nffff0001\n1\nfffe\nfedafffe\n78133bdb\nffffff01\n1\nfe\nfeda49fe\n781344db\n781344d0\n
 
.include "testutils.inc"
.data
x:
.dword 2,-1,0xffff,-1,0x5432f789
.word 2,-1,0xffff,0xf789
.byte 2,0xff,0x89
.byte 0x7e
 
start
moveq -1,r3
move.d x,r5
add.d [r5+],r3
test_cc 0 0 0 1
dumpr3 ; 1
 
moveq 2,r3
add.d [r5],r3
test_cc 0 0 0 1
addq 4,r5
dumpr3 ; 1
 
move.d 0xffff,r3
add.d [r5+],r3
test_cc 0 0 0 0
dumpr3 ; 1fffe
 
moveq -1,r3
add.d [r5+],r3
test_cc 1 0 0 1
dumpr3 ; fffffffe
 
move.d 0x78134452,r3
add.d [r5+],r3
test_cc 1 0 1 0
dumpr3 ; cc463bdb
 
moveq -1,r3
add.w [r5+],r3
test_cc 0 0 0 1
dumpr3 ; ffff0001
 
moveq 2,r3
add.w [r5+],r3
test_cc 0 0 0 1
dumpr3 ; 1
 
move.d 0xffff,r3
add.w [r5],r3
test_cc 1 0 0 1
dumpr3 ; fffe
 
move.d 0xfedaffff,r3
add.w [r5+],r3
test_cc 1 0 0 1
dumpr3 ; fedafffe
 
move.d 0x78134452,r3
add.w [r5+],r3
test_cc 0 0 0 1
dumpr3 ; 78133bdb
 
moveq -1,r3
add.b [r5],r3
test_cc 0 0 0 1
addq 1,r5
dumpr3 ; ffffff01
 
moveq 2,r3
add.b [r5],r3
test_cc 0 0 0 1
dumpr3 ; 1
 
move.d 0xff,r3
add.b [r5],r3
test_cc 1 0 0 1
dumpr3 ; fe
 
move.d 0xfeda49ff,r3
add.b [r5+],r3
test_cc 1 0 0 1
dumpr3 ; feda49fe
 
move.d 0x78134452,r3
add.b [r5+],r3
test_cc 1 0 0 0
dumpr3 ; 781344db
 
move.d 0x78134452,r3
add.b [r5],r3
test_cc 1 0 1 0
dumpr3 ; 781344d0
 
quit
/asm/x6-v32.ms
0,0 → 1,11
#mach: crisv32
#ld: --section-start=.text=0
#sim: --cris-trace=basic
#output: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * ixnzvc 0 0\n
#output: 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 6 0 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: 8 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: a 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: c 1 2 0 1 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
#output: e 1 2 0 2 0 0 0 0 0 0 0 0 0 0 * ixnzvc 1 0\n
.include "tmulv10.ms"
/asm/scc.ms
0,0 → 1,89
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 1\n0\n1\n0\n1\n0\n1\n0\n0\n1\n1\n0\n1\n0\n1\n0\n1\n0\n0\n1\n0\n1\n1\n0\n1\n0\n0\n1\n1\n0\n1\n1\n0\n
 
.include "testutils.inc"
 
start
clearf nzvc
scc r3
dumpr3 ; 1
scs r3
dumpr3 ; 0
sne r3
dumpr3 ; 1
seq r3
dumpr3 ; 0
svc r3
dumpr3 ; 1
svs r3
dumpr3 ; 0
spl r3
dumpr3 ; 1
smi r3
dumpr3 ; 0
sls r3
dumpr3 ; 0
shi r3
dumpr3 ; 1
sge r3
dumpr3 ; 1
slt r3
dumpr3 ; 0
sgt r3
dumpr3 ; 1
sle r3
dumpr3 ; 0
sa r3
dumpr3 ; 1
setf nzvc
scc r3
dumpr3 ; 0
scs r3
dumpr3 ; 1
sne r3
dumpr3 ; 0
svc r3
dumpr3 ; 0
svs r3
dumpr3 ; 1
spl r3
dumpr3 ; 0
smi r3
dumpr3 ; 1
sls r3
dumpr3 ; 1
shi r3
dumpr3 ; 0
sge r3
dumpr3 ; 1
slt r3
dumpr3 ; 0
sgt r3
dumpr3 ; 0
sle r3
dumpr3 ; 1
sa r3
dumpr3 ; 1
clearf n
sge r3
dumpr3 ; 0
slt r3
dumpr3 ; 1
 
.if ..asm.arch.cris.v32
setf p
ssb r3
.else
moveq 1,r3
.endif
dumpr3 ; 1
 
.if ..asm.arch.cris.v32
clearf p
ssb r3
.else
moveq 0,r3
.endif
dumpr3 ; 0
 
quit
/asm/tmulv10.ms
0,0 → 1,26
#mach: crisv10
#output: Basic clock cycles, total @: 9\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
 
; Check that multiplications do not make the simulator barf.
; Nothing deeper.
 
.include "testutils.inc"
startnostack
moveq 1,r3
moveq 2,r1
moveq 1,r0
muls.d r0,r1
muls.d r0,r3
mulu.d r1,r3
break 15
nop
/asm/bdapqpc.ms
0,0 → 1,30
# mach: crisv3 crisv8 crisv10
# output: aaeebb11\nde378218\n
 
# Test that the special case "X [pc+I],Y" works, where I byte-sized.
 
.include "testutils.inc"
start
x:
; FIXME: Gas bugs are making this a bit harder than necessary.
; move.d [pc+y-(.+2)],r3
move.d [pc+8],r3
yy:
jump zz
 
y:
.dword 0xaaeebb11
y2:
.dword 0xde378218
 
zz:
dumpr3
jump z
quit
 
; Check a negative offset.
.space 50
z:
move.d [pc+y2-(.+2)],r3
dumpr3
quit
/asm/btst.ms
0,0 → 1,87
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 1111\n
 
.include "testutils.inc"
start
clearf nzvc
moveq -1,r3
.if ..asm.arch.cris.v32
.else
setf vc
.endif
btstq 0,r3
test_cc 1 0 0 0
 
moveq 2,r3
btstq 1,r3
test_cc 1 0 0 0
 
moveq 4,r3
btstq 1,r3
test_cc 0 1 0 0
 
moveq -1,r3
btstq 31,r3
test_cc 1 0 0 0
 
move.d 0x5a67f19f,r3
btstq 12,r3
test_cc 1 0 0 0
 
move.d 0xda67f19f,r3
move.d 29,r4
btst r4,r3
test_cc 0 0 0 0
 
move.d 0xda67f19f,r3
move.d 32,r4
btst r4,r3
test_cc 1 0 0 0
 
move.d 0xda67f191,r3
move.d 33,r4
btst r4,r3
test_cc 0 0 0 0
 
moveq -1,r3
moveq 0,r4
btst r4,r3
test_cc 1 0 0 0
 
moveq 2,r3
moveq 1,r4
btst r4,r3
test_cc 1 0 0 0
 
moveq -1,r3
moveq 31,r4
btst r4,r3
test_cc 1 0 0 0
 
moveq 4,r3
btstq 1,r3
test_cc 0 1 0 0
 
moveq -1,r3
moveq 15,r4
btst r4,r3
test_cc 1 0 0 0
 
move.d 0x5a67f19f,r3
moveq 12,r4
btst r4,r3
test_cc 1 0 0 0
 
move.d 0x5a678000,r3
moveq 11,r4
btst r4,r3
test_cc 0 1 0 0
 
move.d 0x5a67f19f,r3
btst r3,r3
test_cc 0 0 0 0
 
move.d 0x1111,r3
dumpr3
 
quit
/asm/moverbpc.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
startnostack
setf
move.d r5,pc
quit
/asm/boundmv32.ms
0,0 → 1,15
# mach: crisv32
# xerror:
# output: program stopped with signal 4.\n
.include "testutils.inc"
 
; Check that bound with a memory operand is invalid.
start
move.d 0f,r5
move.d r5,r3
.byte 0xd5,0x39 ; bound.d [r5],r3 -- we can't assemble it.
pass
 
0:
.dword 0b
 
/asm/movepcw.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
startnostack
setf
test.w pc
quit
/asm/raw7.ms
0,0 → 1,25
; Checking read-after-write: movemwrite-then-read 2 cycles.
#mach: crisv32
#ld: --section-start=.text=0
#output: Basic clock cycles, total @: 6\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 2\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 1\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "testutils.inc"
startnostack
.lcomm x,4*11
.lcomm y,4
move.d x,$r0
move.d y,$r1
nop
nop
movem $r10,[$r0]
move.d [$r1],$r2
break 15
/asm/orc.ms
0,0 → 1,71
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: 3\n3\nffff\nffffffff\n7c33f7db\nffff0003\n3\nfedaffff\n7813f7db\n3\n3\nfeb\n781344db\n
 
.include "testutils.inc"
start
moveq 1,r3
or.d 2,r3
test_move_cc 0 0 0 0
dumpr3 ; 3
 
moveq 2,r3
or.d 1,r3
test_move_cc 0 0 0 0
dumpr3 ; 3
 
move.d 0xf0ff,r3
or.d 0xff0f,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff
 
moveq -1,r3
or.d -1,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d 0x78134452,r3
or.d 0x5432f789,r3
test_move_cc 0 0 0 0
dumpr3 ; 7c33f7db
 
move.d 0xffff0001,r3
or.w 2,r3
test_move_cc 0 0 0 0
dumpr3 ; ffff0003
 
moveq 2,r3
or.w 1,r3
test_move_cc 0 0 0 0
dumpr3 ; 3
 
move.d 0xfedaffaf,r3
or.w 0xff5f,r3
test_move_cc 1 0 0 0
dumpr3 ; fedaffff
 
move.d 0x78134452,r3
or.w 0xf789,r3
test_move_cc 1 0 0 0
dumpr3 ; 7813f7db
 
moveq 1,r3
or.b 2,r3
test_move_cc 0 0 0 0
dumpr3 ; 3
 
moveq 2,r3
or.b 1,r3
test_move_cc 0 0 0 0
dumpr3 ; 3
 
move.d 0xfa3,r3
or.b 0x4a,r3
test_move_cc 1 0 0 0
dumpr3 ; feb
 
move.d 0x78134453,r3
or.b 0x89,r3
test_move_cc 1 0 0 0
dumpr3 ; 781344db
 
quit
/asm/addom.ms
0,0 → 1,55
# mach: crisv32
# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n
 
.include "testutils.inc"
.data
x:
.dword 0x55aa77ff
.dword 0xccff2244
.dword 0x88ccee19
y:
.dword 32769
.word -1
.dword 5
.byte 3,-4
.word 2
.dword -76789887
 
start
moveq -1,r0
move.d x-32768,r5
move.d y,r13
addo.d [r13+],r5,acr
move.d [acr],r3
dumpr3 ; 4455aa77
 
addu.w 32770,r5
addo.w [r13+],r5,acr
move.d [acr],r3
dumpr3 ; 4455aa77
 
addo.d [r13],acr,acr
addq 4,r13
move.d [acr],r3
dumpr3 ; ee19ccff
 
addo.b [r13+],r5,acr
movu.w [acr],r3
dumpr3 ; ff22
 
addo.b [r13],acr,acr
addq 1,r13
move.d [acr],r3
dumpr3 ; 4455aa77
 
addo.w [r13],acr,acr
addq 2,r13
move.d [acr],r3
dumpr3 ; ff224455
 
addo.d [r13+],r5,acr
add.d 76789885,acr
move.d [acr],r3
dumpr3 ; 55aa77ff
 
quit
/asm/mulv10.ms
0,0 → 1,29
# mach: crisv8 crisv10
# output: fffffffe\n
# output: ffffffff\n
# output: fffffffe\n
# output: 1\n
 
; Check that carry is cleared on v8, v10.
 
.include "testutils.inc"
start
moveq -1,r3
moveq 2,r4
setf c
muls.d r4,r3
test_cc 1 0 0 0
dumpr3 ; fffffffe
move mof,r3
dumpr3 ; ffffffff
 
moveq -1,r3
moveq 2,r4
setf c
mulu.d r4,r3
test_cc 0 0 1 0
dumpr3 ; fffffffe
move mof,r3
dumpr3 ; 1
 
quit
/asm/rfn.ms
0,0 → 1,53
# mach: crisv32
# output: c008c1af\n40000220\n40000080\n40000000\n
 
; Check that RFN affects CCS the right way.
 
.include "testutils.inc"
start
 
; Set SPC to 1 to disable single step exceptions when S flag is set.
move 1,spc
 
; CCS:
; 31 24 23 16 15 8 7 0
; +---+-----------+-------+-------+-----------+---+---------------+
; |Q M|S R P U I X N Z V C|S R P U I X N Z V C|S R P U I X N Z V C|
; | |2 2 2 2 2 2 2 2 2 2|1 1 1 1 1 1 1 1 1 1| |
; +---+-----------+-------+-------+-----------+---+---------------+
 
; Clear S R P U I X N Z V C, set R1 P1 (not U1) I1 X1 N1 Z1 V1 C1,
; clear S1 R2 P2 U2 N2 Z2 V2 C2, set S2 I2 X2 Q, clear M:
; 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
move 0xa306fc00,ccs
 
test_cc 0 0 0 0
 
rfn
test_cc 1 1 1 1
move ccs,r3
dumpr3 ; 0xc008c1af
 
and.d 0x3fffffff,r3
move r3,ccs
rfn
test_cc 0 0 0 0
move ccs,r3
dumpr3 ; 0x40000220
 
and.d 0x3fffffff,r3
move r3,ccs
rfn
test_cc 0 0 0 0
move ccs,r3
dumpr3 ; 0x40000080
 
and.d 0x3fffffff,r3
move r3,ccs
or.w 0x100,r3
move r3,ccs
rfn
move ccs,r3
dumpr3 ; 0x40000000
 
quit
/asm/bdapq.ms
0,0 → 1,29
# mach: crisv0 crisv3 crisv8 crisv10
# output: ccff2244\n88ccee19\n55aa77ff\n19cc\n0\n
 
.include "testutils.inc"
.data
x:
.dword 0x55aa77ff
.dword 0xccff2244
.dword 0x88ccee19
.dword 0
start
moveq -1,r0
move.d x+4,r5
move.d [r5+0],r3
test_move_cc 1 0 0 0
dumpr3 ; ccff2244
move.d [r5=r5+4],r3
test_move_cc 1 0 0 0
dumpr3 ; 88ccee19
move.d [r5=r5-8],r3
test_move_cc 0 0 0 0
dumpr3 ; 55aa77ff
movu.w [r5+7],r3
test_move_cc 0 0 0 0
dumpr3 ; 19cc
move.d [r5+12],r3
test_move_cc 0 1 0 0
dumpr3 ; 0
quit
/asm/mstep.ms
0,0 → 1,108
# mach: crisv3 crisv8 crisv10
#output: fffffffe\n
#output: 3\n
#output: 1fffe\n
#output: 2fffd\n
#output: fffffffd\n
#output: ffffffff\n
#output: f02688a4\n
#output: 1fffe\n
#output: fffffffe\n
#output: fffffffe\n
#output: fffffff9\n
#output: 0\n
#output: 4459802d\n
#output: 4459802d\n
 
.include "testutils.inc"
start
moveq -1,r3
moveq 2,r4
mstep r4,r3
test_move_cc 1 0 0 0
dumpr3 ; fffffffe
 
moveq 2,r3
moveq -1,r4
mstep r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 3
 
move.d 0xffff,r4
move.d r4,r3
mstep r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 1fffe
 
move.d 0xffff,r4
move.d r4,r3
setf n
mstep r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 2fffd
 
moveq -1,r4
move.d r4,r3
mstep r4,r3
test_move_cc 1 0 0 0
dumpr3 ; fffffffd
 
moveq -1,r3
moveq 1,r4
setf n
mstep r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
mstep r4,r3
test_move_cc 1 0 0 0
dumpr3 ; f02688a4
 
move.d 0xffff,r3
move.d 0x1fffe,r4
mstep r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 1fffe
 
move.d 0x7fffffff,r3
moveq 5,r5
mstep r5,r3
test_move_cc 1 0 0 0
dumpr3 ; fffffffe
 
move.d 0x7fffffff,r3
moveq 0,r5
mstep r5,r3
test_move_cc 1 0 0 0
dumpr3 ; fffffffe
 
move.d 0x7fffffff,r3
moveq -5,r5
mstep r5,r3
test_move_cc 1 0 0 0
dumpr3 ; fffffff9
 
move.d 0x7fffffff,r3
moveq 2,r5
setf n
mstep r5,r3
test_move_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
setf n
mstep r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 4459802d
 
move.d 0x5432f789,r4
move.d 0x78134452,r3
setf nc
mstep r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 4459802d
 
quit
/asm/mover.ms
0,0 → 1,29
# mach: crisv3 crisv8 crisv10 crisv32
# output: ffffff05\nffff0005\n5\nffffff00\n
 
; Move between registers. Check that just the subreg is copied.
 
.include "testutils.inc"
startnostack
moveq -30,r3
moveq 5,r4
move.b r4,r3
test_move_cc 0 0 0 0
dumpr3
 
move.w r4,r3
test_move_cc 0 0 0 0
dumpr3
 
move.d r4,r3
test_move_cc 0 0 0 0
dumpr3
 
moveq -1,r3
moveq 0,r4
move.b r4,r3
test_move_cc 0 1 0 0
dumpr3
 
quit
 
/asm/halt.ms
0,0 → 1,9
# mach: crisv32
# xerror:
# output: HALT isn't implemented\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
start
halt
 
quit
/asm/lsl.ms
0,0 → 1,217
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
# output: ffffffff\n4\n80000000\nffff8000\n7f19f000\n80000000\n0\n0\n699fc67c\nffffffff\n4\n80000000\nffff8000\n7f19f000\nda670000\nda670000\nda670000\nda67c67c\nffffffff\nfffafffe\n4\nffff0000\nffff8000\n5a67f000\nda67f100\nda67f100\nda67f100\nda67f17c\nfff3faff\nfff3fafe\n4\nffffff00\nffffff00\nffffff80\n5a67f100\n5a67f1f0\n
 
.include "testutils.inc"
start
moveq -1,r3
lslq 0,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq 2,r3
lslq 1,r3
test_move_cc 0 0 0 0
dumpr3 ; 4
 
moveq -1,r3
lslq 31,r3
test_move_cc 1 0 0 0
dumpr3 ; 80000000
 
moveq -1,r3
lslq 15,r3
test_move_cc 1 0 0 0
dumpr3 ; ffff8000
 
move.d 0x5a67f19f,r3
lslq 12,r3
test_move_cc 0 0 0 0
dumpr3 ; 7f19f000
 
move.d 0xda67f19f,r3
move.d 31,r4
lsl.d r4,r3
test_move_cc 1 0 0 0
dumpr3 ; 80000000
 
move.d 0xda67f19f,r3
move.d 32,r4
lsl.d r4,r3
test_move_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0xda67f19f,r3
move.d 33,r4
lsl.d r4,r3
test_move_cc 0 1 0 0
dumpr3 ; 0
 
move.d 0xda67f19f,r3
move.d 66,r4
lsl.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 699fc67c
 
moveq -1,r3
moveq 0,r4
lsl.d r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
moveq 2,r3
moveq 1,r4
lsl.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 4
 
moveq -1,r3
moveq 31,r4
lsl.d r4,r3
test_move_cc 1 0 0 0
dumpr3 ; 80000000
 
moveq -1,r3
moveq 15,r4
lsl.d r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffff8000
 
move.d 0x5a67f19f,r3
moveq 12,r4
lsl.d r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 7f19f000
 
move.d 0xda67f19f,r3
move.d 31,r4
lsl.w r4,r3
test_move_cc 0 1 0 0
dumpr3 ; da670000
 
move.d 0xda67f19f,r3
move.d 32,r4
lsl.w r4,r3
test_move_cc 0 1 0 0
dumpr3 ; da670000
 
move.d 0xda67f19f,r3
move.d 33,r4
lsl.w r4,r3
test_move_cc 0 1 0 0
dumpr3 ; da670000
 
move.d 0xda67f19f,r3
move.d 66,r4
lsl.w r4,r3
test_move_cc 1 0 0 0
dumpr3 ; da67c67c
 
moveq -1,r3
moveq 0,r4
lsl.w r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffffff
 
move.d 0xfffaffff,r3
moveq 1,r4
lsl.w r4,r3
test_move_cc 1 0 0 0
dumpr3 ; fffafffe
 
moveq 2,r3
moveq 1,r4
lsl.w r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 4
 
moveq -1,r3
moveq 31,r4
lsl.w r4,r3
test_move_cc 0 1 0 0
dumpr3 ; ffff0000
 
moveq -1,r3
moveq 15,r4
lsl.w r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffff8000
 
move.d 0x5a67f19f,r3
moveq 12,r4
lsl.w r4,r3
test_move_cc 1 0 0 0
dumpr3 ; 5a67f000
 
move.d 0xda67f19f,r3
move.d 31,r4
lsl.b r4,r3
test_move_cc 0 1 0 0
dumpr3 ; da67f100
 
move.d 0xda67f19f,r3
move.d 32,r4
lsl.b r4,r3
test_move_cc 0 1 0 0
dumpr3 ; da67f100
 
move.d 0xda67f19f,r3
move.d 33,r4
lsl.b r4,r3
test_move_cc 0 1 0 0
dumpr3 ; da67f100
 
move.d 0xda67f19f,r3
move.d 66,r4
lsl.b r4,r3
test_move_cc 0 0 0 0
dumpr3 ; da67f17c
 
move.d 0xfff3faff,r3
moveq 0,r4
lsl.b r4,r3
test_move_cc 1 0 0 0
dumpr3 ; fff3faff
 
move.d 0xfff3faff,r3
moveq 1,r4
lsl.b r4,r3
test_move_cc 1 0 0 0
dumpr3 ; fff3fafe
 
moveq 2,r3
moveq 1,r4
lsl.b r4,r3
test_move_cc 0 0 0 0
dumpr3 ; 4
 
moveq -1,r3
moveq 31,r4
lsl.b r4,r3
test_move_cc 0 1 0 0
dumpr3 ; ffffff00
 
moveq -1,r3
moveq 15,r4
lsl.b r4,r3
test_move_cc 0 1 0 0
dumpr3 ; ffffff00
 
moveq -1,r3
moveq 7,r4
lsl.b r4,r3
test_move_cc 1 0 0 0
dumpr3 ; ffffff80
 
move.d 0x5a67f19f,r3
moveq 12,r4
lsl.b r4,r3
test_move_cc 0 1 0 0
dumpr3 ; 5a67f100
 
move.d 0x5a67f19f,r3
moveq 4,r4
lsl.b r4,r3
test_move_cc 1 0 0 0
dumpr3 ; 5a67f1f0
 
quit
/asm/ftagi.ms
0,0 → 1,9
# mach: crisv32
# xerror:
# output: FTAGI isn't implemented\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
start
ftagi [r8]
 
quit
/asm/testutils.inc
0,0 → 1,361
; Copied from fr30 and modified.
; r9, r11-r13 are used as tmps, consider them call clobbered by these macros.
;
; Do not use the macro counter \@ in macros, there's a bug in
; gas 2.9.1 when it is also a line-separator.
;
 
; Don't require the $-prefix on registers.
.syntax no_register_prefix
 
.macro startnostack
.data
.space 64,0 ; Simple stack
stackhi:
failmsg:
.ascii "fail\n"
passmsg:
.ascii "pass\n"
.text
break 11
.global _start
_start:
.endm
 
.macro start
startnostack
move.d stackhi,sp
.endm
 
; Exit with return code
.macro exit rc
move.d \rc,r10
moveq 1,r9 ; == __NR_exit
break 13
break 15
.endm
 
; Pass the test case
.macro pass
moveq 5,r12
move.d passmsg,r11
move.d 1,r10
moveq 4,r9 ; == __NR_write
break 13
exit 0
.endm
 
; Fail the testcase
.macro fail
; moveq 5,r12
; move.d failmsg,r11
; move.d 1,r10
; moveq 4,r1
; break 13
; exit 1
break 15
.endm
 
.macro quit
break 15
.endm
 
.macro dumpr3
break 14
.endm
 
; Load an immediate value into a general register
; TODO: use minimal sized insn
.macro mvi_h_gr val reg
move.d \val,\reg
.endm
 
; Load an immediate value into a dedicated register
.macro mvi_h_dr val reg
move.d \val,r9
move.d r9,\reg
.endm
 
; Load a general register into another general register
.macro mvr_h_gr src targ
move.d \src,\targ
.endm
 
; Store an immediate into a word in memory
.macro mvi_h_mem val addr
mvi_h_gr \val r11
mvr_h_mem r11,\addr
.endm
 
; Store a register into a word in memory
.macro mvr_h_mem reg addr
move.d \addr,$r13
move.d \reg,[$r13]
.endm
 
; Store the current ps on the stack
.macro save_ps
.if ..asm.arch.cris.v32
move ccs,acr ; Push will do a "subq" first.
push acr
.else
push dccr
.endif
.endm
 
; Load a word value from memory
.macro ldmem_h_gr addr reg
move.d \addr,$r13
move.d [$r13],\reg
.endm
 
; Add 2 general registers
.macro add_h_gr reg1 reg2
add.d \reg1,\reg2
.endm
 
; Increment a register by and immediate
.macro inci_h_gr inc reg
mvi_h_gr \inc,r11
add.d r11,\reg
.endm
 
; Test the value of an immediate against a general register
.macro test_h_gr val reg
cmp.d \val,\reg
beq 9f
nop
fail
9:
.endm
 
; compare two general registers
.macro testr_h_gr reg1 reg2
cmp.d \reg1,\reg2
beq 9f
fail
9:
.endm
 
; Test the value of an immediate against a dedicated register
.macro test_h_dr val reg
move \reg,$r12
test_h_gr \val $r12
.endm
 
; Test the value of an general register against a dedicated register
.macro testr_h_dr gr dr
move \dr,$r12
testr_h_gr \gr $r12
.endm
 
; Compare an immediate with word in memory
.macro test_h_mem val addr
ldmem_h_gr \addr $r12
test_h_gr \val $r12
.endm
 
; Compare a general register with word in memory
.macro testr_h_mem reg addr
ldmem_h_gr \addr r12
testr_h_gr \reg r12
.endm
 
; Set the condition codes
; The lower bits of the mask *are* nzvc, so we don't
; have to do anything strange.
.macro set_cc mask
move.w \mask,r13
.if ..asm.arch.cris.v32
move r13,ccs
.else
move r13,ccr
.endif
.endm
 
; Set the stack mode
; .macro set_s_user
; orccr 0x20
; .endm
;
; .macro set_s_system
; andccr 0x1f
; .endm
;
;; Test the stack mode
; .macro test_s_user
; mvr_h_gr ps,r9
; mvi_h_gr 0x20,r11
; and r11,r9
; test_h_gr 0x20,r9
; .endm
;
; .macro test_s_system
; mvr_h_gr ps,r9
; mvi_h_gr 0x20,r11
; and r11,r9
; test_h_gr 0x0,r9
; .endm
 
; Set the interrupt bit
; ??? Do they mean "enable interrupts" or "disable interrupts"?
; Assuming enable here.
.macro set_i val
.if (\val == 1)
ei
.else
di
.endif
.endm
 
; Test the stack mode
; .macro test_i val
; mvr_h_gr ps,r9
; mvi_h_gr 0x10,r11
; and r11,r9
; .if (\val == 1)
; test_h_gr 0x10,r9
; .else
; test_h_gr 0x0,r9
; .endif
; .endm
;
;; Set the ilm
; .macro set_ilm val
; stilm \val
; .endm
;
;; Test the ilm
; .macro test_ilm val
; mvr_h_gr ps,r9
; mvi_h_gr 0x1f0000,r11
; and r11,r9
; mvi_h_gr \val,r12
; mvi_h_gr 0x1f,r11
; and r11,r12
; lsl 15,r12
; lsl 1,r12
; testr_h_gr r9,r12
; .endm
;
; Test the condition codes
.macro test_cc N Z V C
.if \N
bpl 9f
nop
.else
bmi 9f
nop
.endif
.if \Z
bne 9f
nop
.else
beq 9f
nop
.endif
.if \V
bvc 9f
nop
.else
bvs 9f
nop
.endif
.if \C
bcc 9f
nop
.else
bcs 9f
nop
.endif
ba 8f
nop
9:
fail
8:
.endm
 
.macro test_move_cc N Z V C
.if ..asm.arch.cris.v32
; V and C aren't affected on v32, so to re-use the test-cases,
; we fake them cleared. There's a separate test, nonvcv32.ms
; covering this omission.
clearf vc
test_cc \N \Z 0 0
.else
test_cc \N \Z \V \C
.endif
.endm
 
; Set the division bits
; .macro set_dbits val
; mvr_h_gr ps,r12
; mvi_h_gr 0xfffff8ff,r11
; and r11,r12
; mvi_h_gr \val,r9
; mvi_h_gr 3,r11
; and r11,r9
; lsl 9,r9
; or r9,r12
; mvr_h_gr r12,ps
; .endm
;
;; Test the division bits
; .macro test_dbits val
; mvr_h_gr ps,r9
; lsr 9,r9
; mvi_h_gr 3,r11
; and r11,r9
; test_h_gr \val,r9
; .endm
;
; Save the return pointer
.macro save_rp
push srp
.ENDM
 
; restore the return pointer
.macro restore_rp
pop srp
.endm
 
; Ensure branch taken
.macro take_branch opcode
\opcode 9f
nop
fail
9:
.endm
 
.macro take_branch_d opcode val
\opcode 9f
nop
move.d \val,r9
fail
9:
test_h_gr \val,r9
.endm
 
; Ensure branch not taken
.macro no_branch opcode
\opcode 9f
nop
ba 8f
nop
9:
fail
8:
.endm
 
.macro no_branch_d opcode val
\opcode 9f
move.d \val,r9
nop
ba 8f
nop
9:
fail
8:
test_h_gr \val,r9
.endm
 
/asm/movepcb.ms
0,0 → 1,9
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
 
.include "testutils.inc"
startnostack
setf
test.b pc
quit
/asm/bare2.ms
0,0 → 1,9
# mach: crisv32
# output: 0\n0\n4\n42\n
# sim: --cris-naked --target binary --architecture crisv32
# ld: --oformat binary
 
; Check that we can run a naked binary with the same expected
; results as an ELF "executable".
 
.include "bare1.ms"
/asm/addiv32.ms
0,0 → 1,62
# mach: crisv32
# output: 4455aa77\n4455aa77\nee19ccff\nff22\n4455aa77\nff224455\n55aa77ff\n
 
.include "testutils.inc"
.data
x:
.dword 0x55aa77ff
.dword 0xccff2244
.dword 0x88ccee19
 
start
setf cv
moveq -1,r0
move.d x-32768,r5
move.d 32769,r6
addi r6.b,r5,acr
test_cc 0 0 1 1
move.d [acr],r3
dumpr3 ; 4455aa77
 
addu.w 32771,r5
setf znvc
moveq -1,r8
addi r8.w,r5,acr
test_cc 1 1 1 1
move.d [acr],r3
dumpr3 ; 4455aa77
 
moveq 5,r10
clearf znvc
addi r10.b,acr,acr
test_cc 0 0 0 0
move.d [acr],r3
dumpr3 ; ee19ccff
 
subq 1,r5
move.d r5,r8
subq 1,r8
moveq 1,r9
addi r9.d,r8,acr
test_cc 0 0 0 0
movu.w [acr],r3
dumpr3 ; ff22
 
moveq -2,r11
addi r11.w,acr,acr
move.d [acr],r3
dumpr3 ; 4455aa77
 
moveq 5,r9
addi r9.d,acr,acr
subq 18,acr
move.d [acr],r3
dumpr3 ; ff224455
 
move.d -76789888/4,r12
addi r12.d,r5,acr
add.d 76789886,acr
move.d [acr],r3
dumpr3 ; 55aa77ff
 
quit
/asm/option4.ms
0,0 → 1,7
#mach: crisv0 crisv3 crisv8 crisv10 crisv32
#sim: --cris-unknown-syscall=foo
#xerror:
#output: Unknown option `--cris-unknown-syscall=foo'\n
.include "testutils.inc"
start
fail
/asm/raw12.ms
0,0 → 1,24
; Checking read-after-write: swrite-then-nop-nop-read unaffected.
#mach: crisv32
#output: Basic clock cycles, total @: 6\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "testutils.inc"
startnostack
.lcomm x,4
.lcomm y,4
move.d x,$r0
move.d y,$r1
clear.d [$r0]
nop
nop
move [$r1],$srp
break 15
/asm/tmvmrv10.ms
0,0 → 1,50
#mach: crisv10
#output: Basic clock cycles, total @: 45\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
 
; Check that movem to register basically looks ok cycle-wise.
; Nothing deep.
 
.include "testutils.inc"
startnostack
move.d 0f,r5
moveq 0,r8
moveq 0,r9
 
; Adapted from crisv32 movem-to-memory penalty examples many
; revisions ago.
 
movem [r5],r4
test.d [r3] ; 3 cycle penalty on v32 (2 memory source, 1 movem dest).
movem [r5],r4
subq 1,r8
test.d [r3] ; 2 cycle penalty on v32.
movem [r5],r4
subq 1,r1 ; 3 cycle penalty on v32.
movem [r5],r4
add.d r8,r9
subq 1,r1 ; 2 cycle penalty on v32.
movem [r5],r4
add.d r8,r9
subq 1, r9
subq 1, r1 ; 1 cycle penalty on v32.
break 15
 
.data
.p2align 5
0:
.dword 0b
.dword 0b
.dword 0b
.dword 0b
.dword 0b
 
/asm/jsr.ms
0,0 → 1,86
# mach: crisv3 crisv8 crisv10 crisv32
# output: 0\n0\n0\n0\n0\n0\n
 
# Test that jsr Rn and jsr [PC+] work.
 
.include "testutils.inc"
start
x:
move.d 0f,r6
setf nzvc
jsr r6
.if ..asm.arch.cris.v32
nop
.endif
0:
test_move_cc 1 1 1 1
move srp,r3
sub.d 0b,r3
dumpr3
 
move.d 1f,r0
setf nzvc
jsr r0
.if ..asm.arch.cris.v32
moveq 0,r0
.endif
6:
nop
quit
 
2:
test_move_cc 0 0 0 0
move srp,r3
sub.d 3f,r3
dumpr3
jsr 4f
.if ..asm.arch.cris.v32
nop
.endif
7:
nop
quit
 
; Can't use local label 8 or 9, as they're used by test_move_cc.
y:
move srp,r3
sub.d 7b,r3
dumpr3
quit
 
4:
move srp,r3
sub.d 7b,r3
dumpr3
move.d 5f,r3
jump r3
.if ..asm.arch.cris.v32
moveq 0,r3
.endif
quit
 
.space 32770,0
1:
test_move_cc 1 1 1 1
move srp,r3
sub.d 6b,r3
dumpr3
 
clearf cznv
jsr 2b
.if ..asm.arch.cris.v32
nop
.endif
3:
 
quit
 
5:
move srp,r3
sub.d 7b,r3
dumpr3
jump y
.if ..asm.arch.cris.v32
nop
.endif
quit
/asm/io7.ms
0,0 → 1,22
# mach: crisv32
# ld: --section-start=.text=0
# sim: --cris-900000xx
# xerror:
# output: ce11d0c\n
# output: core: 4 byte write to unmapped address 0x90000004 at 0x16\n
# output: program stopped with signal 11.\n
 
; Check that invalid access to the simulator area is recognized.
; "PASS" area.
 
.include "testutils.inc"
start
move.d 0x0ce11d0c,$r3
dumpr3
move.d 0x90000004,$acr
clear.d [$acr]
move.d 0xbadc0de,$r3
dumpr3
0:
ba 0b
nop
/asm/msteppc3.ms
0,0 → 1,8
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\n
# output: program stopped with signal 5.\n
 
.include "testutils.inc"
start
mstep pc,pc
/c/stat4.c
0,0 → 1,28
/* Simulator options:
#notarget: cris*-*-elf
#sim: --sysroot=@exedir@
*/
 
#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
 
int main (int argc, char *argv[])
{
char path[1024] = "/";
struct stat buf;
strcat (path, argv[0]);
if (lstat (".", &buf) != 0
|| !S_ISDIR (buf.st_mode))
abort ();
if (lstat (path, &buf) != 0
|| !S_ISREG (buf.st_mode))
abort ();
printf ("pass\n");
exit (0);
}
 
c/stat4.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/hellodyn2.c =================================================================== --- c/hellodyn2.c (nonexistent) +++ c/hellodyn2.c (revision 816) @@ -0,0 +1,5 @@ +/* +#dynamic: +#sim: --sysroot=@exedir@ --load-vma + */ +#include "hello.c"
c/hellodyn2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/stat8.c =================================================================== --- c/stat8.c (nonexistent) +++ c/stat8.c (revision 816) @@ -0,0 +1,26 @@ +/* For this test, we need to do the lstat syscall directly, or else + glibc gets a SEGV. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include + +int main (void) +{ + int ret; + + /* From Linux, we get EFAULT. The simulator sends us EINVAL. */ + ret = syscall (SYS_lstat64, ".", NULL); + if (ret != -1 || (errno != EINVAL && errno != EFAULT)) + { + perror ("lstat"); + abort (); + } + + printf ("pass\n"); + exit (0); +}
c/stat8.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sig1.c =================================================================== --- c/sig1.c (nonexistent) +++ c/sig1.c (revision 816) @@ -0,0 +1,20 @@ +#include +#include +#include + +void +leave (int n) +{ + exit (0); +} + +int +main (void) +{ + /* Check that the sigaction syscall (for signal) is interpreted, though + possibly ignored. */ + signal (SIGFPE, leave); + + printf ("pass\n"); + exit (0); +}
c/sig1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sig5.c =================================================================== --- c/sig5.c (nonexistent) +++ c/sig5.c (revision 816) @@ -0,0 +1,16 @@ +/* Check that TRT happens for an uncaught non-abort signal, single thread. +#xerror: +#output: Unimplemented signal: 7\n +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include +#include +int main (void) +{ + kill (getpid (), SIGBUS); + printf ("xyzzy\n"); + exit (0); +}
c/sig5.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/openpf1.c =================================================================== --- c/openpf1.c (nonexistent) +++ c/openpf1.c (revision 816) @@ -0,0 +1,38 @@ +/* Check that --sysroot is applied to open(2). +#sim: --sysroot=@exedir@ + + We assume, with EXE being the name of the executable: + - The simulator executes with cwd the same directory where the executable + is located (so argv[0] contains a plain filename without directory + components). + - There's no /EXE on the host file system. */ + +#include +#include +#include +#include +int main (int argc, char *argv[]) +{ + char *fnam = argv[0]; + FILE *f; + if (argv[0][0] != '/') + { + fnam = malloc (strlen (argv[0]) + 2); + if (fnam == NULL) + abort (); + strcpy (fnam, "/"); + strcat (fnam, argv[0]); + } + + f = fopen (fnam, "rb"); + if (f == NULL) + abort (); + close (f); + + /* Cover another execution path. */ + if (fopen ("/nonexistent", "rb") != NULL + || errno != ENOENT) + abort (); + printf ("pass\n"); + return 0; +}
c/openpf1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sig9.c =================================================================== --- c/sig9.c (nonexistent) +++ c/sig9.c (revision 816) @@ -0,0 +1,36 @@ +/* Check that TRT happens at an non-abort ignored signal, more than one thread. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +*/ + +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + int i; + for (i = 0; i < 100; i++) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + int retcode; + void *retval; + signal (SIGALRM, SIG_IGN); + if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) + kill (getpid (), SIGALRM); + retcode = pthread_join (th_a, &retval); + if (retcode != 0 || retval != NULL) + abort (); + printf ("pass\n"); + exit (0); +}
c/sig9.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/ftruncate1.c =================================================================== --- c/ftruncate1.c (nonexistent) +++ c/ftruncate1.c (revision 816) @@ -0,0 +1,52 @@ +/* Check that the ftruncate syscall works trivially. +#notarget: cris*-*-elf +*/ + +#include +#include +#include + +void +perr (const char *s) +{ + perror (s); + exit (1); +} + +int +main (void) +{ + FILE *f; + const char fname[] = "sk1test.dat"; + const char tsttxt1[] + = "This is the first and only line of this file.\n"; + const char tsttxt2[] = "Now there is a second line.\n"; + char buf[sizeof (tsttxt1) + sizeof (tsttxt2) - 1] = ""; + + f = fopen (fname, "w+"); + if (f == NULL + || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1)) + perr ("open or fwrite"); + + if (fflush (f) != 0) + perr ("fflush"); + + if (ftruncate (fileno (f), strlen(tsttxt1) - 20) != 0) + perr ("ftruncate"); + + if (fclose (f) != 0) + perr ("fclose"); + + f = fopen (fname, "r"); + if (f == NULL + || fread (buf, 1, sizeof (buf), f) != strlen (tsttxt1) - 20 + || strncmp (buf, tsttxt1, strlen (tsttxt1) - 20) != 0 + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +}
c/ftruncate1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/mmap2.c =================================================================== --- c/mmap2.c (nonexistent) +++ c/mmap2.c (revision 816) @@ -0,0 +1,48 @@ +/* +#notarget: cris*-*-elf +*/ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + int fd = open (argv[0], O_RDONLY); + struct stat sb; + int size; + void *a; + const char *str = "a string you'll only find in the program"; + + if (fd == -1) + { + perror ("open"); + abort (); + } + + if (fstat (fd, &sb) < 0) + { + perror ("fstat"); + abort (); + } + + size = sb.st_size; + + /* We want to test mmapping a size that isn't exactly a page. */ + if ((size & 8191) == 0) + size--; + + a = mmap (NULL, size, PROT_READ, MAP_SHARED, fd, 0); + + if (memmem (a, size, str, strlen (str) + 1) == NULL) + abort (); + + printf ("pass\n"); + exit (0); +}
c/mmap2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/openpf5.c =================================================================== --- c/openpf5.c (nonexistent) +++ c/openpf5.c (revision 816) @@ -0,0 +1,56 @@ +/* Check that TRT happens when error on too many opened files. +#notarget: cris*-*-elf +#sim: --sysroot=@exedir@ +*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + int i; + int filemax; + +#ifdef OPEN_MAX + filemax = OPEN_MAX; +#else + filemax = sysconf (_SC_OPEN_MAX); +#endif + + char *fn = malloc (strlen (argv[0]) + 2); + if (fn == NULL) + abort (); + strcpy (fn, "/"); + strcat (fn, argv[0]); + + for (i = 0; i < filemax + 1; i++) + { + if (open (fn, O_RDONLY) < 0) + { + /* Shouldn't happen too early. */ + if (i < filemax - 3 - 1) + { + fprintf (stderr, "i: %d\n", i); + abort (); + } + if (errno != EMFILE) + { + perror ("open"); + abort (); + } + goto ok; + } + } + abort (); + +ok: + printf ("pass\n"); + exit (0); +}
c/openpf5.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/kill2.c =================================================================== --- c/kill2.c (nonexistent) +++ c/kill2.c (revision 816) @@ -0,0 +1,16 @@ +/* Basic kill functionality test; suicide. +#xerror: +#output: program stopped with signal 6.\n +*/ + +#include +#include +#include +#include +int +main (void) +{ + kill (getpid (), SIGABRT); + printf ("undead\n"); + exit (1); +}
c/kill2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/freopen2.c =================================================================== --- c/freopen2.c (nonexistent) +++ c/freopen2.c (revision 816) @@ -0,0 +1,40 @@ +/* Tests that stdin can be redirected from a normal file. */ +#include +#include +#include + +int +main (void) +{ + const char* fname = "freopen.dat"; + const char tsttxt[] + = "A random line of text, used to test correct freopen etc.\n"; + FILE* instream; + FILE *old_stderr; + char c1; + + /* Like the freopen call in flex. */ + old_stderr = freopen (fname, "w+", stderr); + if (old_stderr == NULL + || fwrite (tsttxt, 1, strlen (tsttxt), stderr) != strlen (tsttxt) + || fclose (stderr) != 0) + { + printf ("fail\n"); + exit (1); + } + + instream = freopen(fname, "r", stdin); + if (instream == NULL) { + printf("fail\n"); + exit(1); + } + + c1 = getc(instream); + if (c1 != 'A') { + printf("fail\n"); + exit(1); + } + + printf ("pass\n"); + exit(0); +}
c/freopen2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/mmap6.c =================================================================== --- c/mmap6.c (nonexistent) +++ c/mmap6.c (revision 816) @@ -0,0 +1,8 @@ +/* Check that mmapping specifying a previously mmapped address without + MAP_FIXED works; that we just don't get the same address. +#notarget: cris*-*-elf +*/ +#define NO_MUNMAP +#define MMAP_FLAGS2 MAP_PRIVATE +#define MMAP_TEST_BAD (a == b || MMAP_TEST_BAD_ORIG) +#include "mmap5.c"
c/mmap6.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/thread2.c =================================================================== --- c/thread2.c (nonexistent) +++ c/thread2.c (revision 816) @@ -0,0 +1,28 @@ +/* Compiler options: +#cc: additional_flags=-pthread +#notarget: cris*-*-elf + + A sanity check for syscalls resulting from + pthread_getschedparam and pthread_setschedparam. */ + +#include +#include +#include + +int main (void) +{ + struct sched_param param; + int policy; + + if (pthread_getschedparam (pthread_self (), &policy, ¶m) != 0 + || policy != SCHED_OTHER + || param.sched_priority != 0) + abort (); + + if (pthread_setschedparam (pthread_self (), SCHED_OTHER, ¶m) != 0 + || param.sched_priority != 0) + abort (); + + printf ("pass\n"); + exit (0); +}
c/thread2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/syscall1.c =================================================================== --- c/syscall1.c (nonexistent) +++ c/syscall1.c (revision 816) @@ -0,0 +1,22 @@ +/* Test unknown-syscall output. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented syscall: 166 (0x1, 0x2, 0x3, 0x4, 0x5, 0x6)\n +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include +#include + +int main (void) +{ + /* The number 166 is chosen because there's a gap for that number in + the CRIS asm/unistd.h. */ + int err = syscall (166, 1, 2, 3, 4, 5, 6); + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + printf ("xyzzy\n"); + exit (0); +}
c/syscall1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/ex1.c =================================================================== --- c/ex1.c (nonexistent) +++ c/ex1.c (revision 816) @@ -0,0 +1,54 @@ +/* Compiler options: +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#output: Starting process a\naaaaaaaaStarting process b\nababbbbbbbbb + + The output will change depending on the exact syscall sequence per + thread, so will change with glibc versions. Prepare to modify; use + the latest glibc. + + This file is from glibc/linuxthreads, with the difference that the + number is 10, not 10000. */ + +/* Creates two threads, one printing 10000 "a"s, the other printing + 10000 "b"s. + Illustrates: thread creation, thread joining. */ + +#include +#include +#include +#include "pthread.h" + +static void * +process (void *arg) +{ + int i; + fprintf (stderr, "Starting process %s\n", (char *) arg); + for (i = 0; i < 10; i++) + { + write (1, (char *) arg, 1); + } + return NULL; +} + +int +main (void) +{ + int retcode; + pthread_t th_a, th_b; + void *retval; + + retcode = pthread_create (&th_a, NULL, process, (void *) "a"); + if (retcode != 0) + fprintf (stderr, "create a failed %d\n", retcode); + retcode = pthread_create (&th_b, NULL, process, (void *) "b"); + if (retcode != 0) + fprintf (stderr, "create b failed %d\n", retcode); + retcode = pthread_join (th_a, &retval); + if (retcode != 0) + fprintf (stderr, "join a failed %d\n", retcode); + retcode = pthread_join (th_b, &retval); + if (retcode != 0) + fprintf (stderr, "join b failed %d\n", retcode); + return 0; +}
c/ex1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/syscall5.c =================================================================== --- c/syscall5.c (nonexistent) +++ c/syscall5.c (revision 816) @@ -0,0 +1,9 @@ +/* As the included file, but specifying ENOSYS with message. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys +#output: Unimplemented syscall: 166 (0x1, 0x2, 0x3, 0x4, 0x5, 0x6)\n +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "syscall1.c"
c/syscall5.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/writev1.c =================================================================== --- c/writev1.c (nonexistent) +++ c/writev1.c (revision 816) @@ -0,0 +1,25 @@ +/* Trivial test of writev. +#notarget: cris*-*-elf +#output: abcdefghijklmn\npass\n +*/ +#include +#include +#include + +#define X(x) {x, sizeof (x) -1} +struct iovec v[] = { + X("a"), + X("bcd"), + X("efghi"), + X("j"), + X("klmn\n"), +}; + +int main (void) +{ + if (writev (1, v, sizeof v / sizeof (v[0])) != 15) + abort (); + + printf ("pass\n"); + return 0; +}
c/writev1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sysctl2.c =================================================================== --- c/sysctl2.c (nonexistent) +++ c/sysctl2.c (revision 816) @@ -0,0 +1,41 @@ +/* Check error message for invalid sysctl call. +#xerror: +#output: Unimplemented _sysctl syscall *\n +#output: program stopped with signal 4.\n +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +int main (void) +{ + static int sysctl_args[] = { 99, 99 }; + size_t x = 8; + + struct __sysctl_args { + int *name; + int nlen; + void *oldval; + size_t *oldlenp; + void *newval; + size_t newlen; + unsigned long __unused[4]; + } scargs + = + { + sysctl_args, + sizeof (sysctl_args) / sizeof (sysctl_args[0]), + (void *) -1, &x, NULL, 0 + }; + + int err = syscall (SYS__sysctl, &scargs); + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + printf ("xyzzy\n"); + exit (0); +}
c/sysctl2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sigreturn3.c =================================================================== --- c/sigreturn3.c (nonexistent) +++ c/sigreturn3.c (revision 816) @@ -0,0 +1,8 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "sigreturn1.c"
c/sigreturn3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sched3.c =================================================================== --- c/sched3.c (nonexistent) +++ c/sched3.c (revision 816) @@ -0,0 +1,24 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (void) +{ + struct sched_param sb; + sb.sched_priority = 0; + if (sched_setscheduler (getpid (), SCHED_OTHER, &sb) != 0 + || sb.sched_priority != 0) + abort (); + sb.sched_priority = 5; + if (sched_setscheduler (getpid (), SCHED_OTHER, &sb) != -1 + || errno != EINVAL + || sb.sched_priority != 5) + abort (); + printf ("pass\n"); + exit (0); +}
c/sched3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/rtsigprocmask2.c =================================================================== --- c/rtsigprocmask2.c (nonexistent) +++ c/rtsigprocmask2.c (revision 816) @@ -0,0 +1,9 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "rtsigprocmask1.c"
c/rtsigprocmask2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/rtsigsuspend1.c =================================================================== --- c/rtsigsuspend1.c (nonexistent) +++ c/rtsigsuspend1.c (revision 816) @@ -0,0 +1,21 @@ +/* Test that TRT happens for invalid rt_sigsuspend calls. Single-thread. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented rt_sigsuspend syscall arguments (0x1, 0x2)\n +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include +#include +#include + +int main (void) +{ + int err = syscall (SYS_rt_sigsuspend, 1, 2); + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + printf ("xyzzy\n"); + exit (0); +}
c/rtsigsuspend1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/readlink4.c =================================================================== --- c/readlink4.c (nonexistent) +++ c/readlink4.c (revision 816) @@ -0,0 +1,62 @@ +/* Check for corner case: readlink of too-long name. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +void bye (const char *s, int i) +{ + fprintf (stderr, "%s: %d\n", s, i); + fflush (NULL); + abort (); +} + +int main (int argc, char *argv[]) +{ + char *buf; + char buf2[1024]; + int max, i; + + /* We assume this limit is what we see in the simulator as well. */ +#ifdef PATH_MAX + max = PATH_MAX; +#else + max = pathconf (argv[0], _PC_PATH_MAX); +#endif + + max *= 10; + + if (max <= 0) + bye ("path_max", max); + + if ((buf = malloc (max + 1)) == NULL) + bye ("malloc", 0); + + strcat (buf, argv[0]); + + if (rindex (buf, '/') == NULL) + strcat (buf, "./"); + + for (i = rindex (buf, '/') - buf + 1; i < max; i++) + buf[i] = 'a'; + + buf [i] = 0; + + i = readlink (buf, buf2, sizeof (buf2) - 1); + if (i != -1) + bye ("i", i); + + if (errno != ENAMETOOLONG) + { + perror (buf); + bye ("errno", errno); + } + + printf ("pass\n"); + exit (0); +}
c/readlink4.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sched7.c =================================================================== --- c/sched7.c (nonexistent) +++ c/sched7.c (revision 816) @@ -0,0 +1,17 @@ +/* Check corner error case: specifying invalid PID. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (void) +{ + if (sched_getscheduler (99) != -1 + || errno != ESRCH) + abort (); + printf ("pass\n"); + exit (0); +}
c/sched7.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/pipe2.c =================================================================== --- c/pipe2.c (nonexistent) +++ c/pipe2.c (revision 816) @@ -0,0 +1,143 @@ +/* Check that closing a pipe with a nonempty buffer works. +#notarget: cris*-*-elf +#output: got: a\ngot: b\nexit: 0\n +*/ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +int pip[2]; + +int pipemax; + +int +process (void *arg) +{ + char *s = arg; + int lots = pipemax + 256; + char *buf = malloc (lots); + int ret; + + if (buf == NULL) + abort (); + + *buf = *s; + + /* The first write should go straight through. */ + if (write (pip[1], buf, 1) != 1) + abort (); + + *buf = s[1]; + + /* The second write may or may not be successful for the whole + write, but should be successful for at least the pipemax part. + As linux/limits.h clamps PIPE_BUF to 4096, but the page size is + actually 8k, we can get away with that much. There should be no + error, though. Doing this on host shows that for + x86_64-unknown-linux-gnu (2.6.14-1.1656_FC4) pipemax * 10 can be + successfully written, perhaps for similar reasons. */ + ret = write (pip[1], buf, lots); + if (ret < pipemax) + { + fprintf (stderr, "ret: %d, %s, %d\n", ret, strerror (errno), pipemax); + fflush (0); + abort (); + } + + return 0; +} + +int +main (void) +{ + int retcode; + int pid; + int st = 0; + long stack[16384]; + char buf[1]; + + /* We need to turn this off because we don't want (to have to model) a + SIGPIPE resulting from the close. */ + if (signal (SIGPIPE, SIG_IGN) != SIG_DFL) + abort (); + + retcode = pipe (pip); + + if (retcode != 0) + { + fprintf (stderr, "Bad pipe %d\n", retcode); + abort (); + } + +#ifdef PIPE_MAX + pipemax = PIPE_MAX; +#else + pipemax = fpathconf (pip[1], _PC_PIPE_BUF); +#endif + + if (pipemax <= 0) + { + fprintf (stderr, "Bad pipemax %d\n", pipemax); + abort (); + } + + pid = clone (process, (char *) stack + sizeof (stack) - 64, + (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) + | SIGCHLD, "ab"); + if (pid <= 0) + { + fprintf (stderr, "Bad clone %d\n", pid); + abort (); + } + + while ((retcode = read (pip[0], buf, 1)) == 0) + ; + + if (retcode != 1) + { + fprintf (stderr, "Bad read 1: %d\n", retcode); + abort (); + } + + printf ("got: %c\n", buf[0]); + + /* Need to read out something from the second write too before + closing, or the writer can get EPIPE. */ + while ((retcode = read (pip[0], buf, 1)) == 0) + ; + + if (retcode != 1) + { + fprintf (stderr, "Bad read 2: %d\n", retcode); + abort (); + } + + printf ("got: %c\n", buf[0]); + + if (close (pip[0]) != 0) + { + perror ("pip close"); + abort (); + } + + retcode = waitpid (pid, &st, __WALL); + + if (retcode != pid || !WIFEXITED (st)) + { + fprintf (stderr, "Bad wait %d:%d %x\n", pid, retcode, st); + perror ("errno"); + abort (); + } + + printf ("exit: %d\n", WEXITSTATUS (st)); + return 0; +}
c/pipe2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/readlink8.c =================================================================== --- c/readlink8.c (nonexistent) +++ c/readlink8.c (revision 816) @@ -0,0 +1,8 @@ +/* Check that rare readlink calls don't cause the simulator to abort. +#notarget: cris*-*-elf +#sim: --sysroot=@exedir@ +#simenv: env(-u\ PWD\ foo)=bar + FIXME: Need to unset PWD, but right now I won't bother tweaking the + generic parts of the testsuite machinery and instead abuse a flaw. */ +#define SYSROOTED 1 +#include "readlink2.c"
c/readlink8.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/pipe6.c =================================================================== --- c/pipe6.c (nonexistent) +++ c/pipe6.c (revision 816) @@ -0,0 +1,111 @@ +/* Check that writing an inordinate amount of data works (somewhat). +#notarget: cris*-*-elf +#output: got: a\nexit: 0\n + This test-case will *not* work on host (or for real): the first + pipemax+1 bytes will be successfully written. It's just for + exercising a rare execution path. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int pip[2]; + +int pipemax; + +int +process (void *arg) +{ + char *s = arg; + char *buf = calloc (pipemax * 100, 1); + int ret; + + if (buf == NULL) + abort (); + + *buf = *s; + + ret = write (pip[1], buf, pipemax * 100); + if (ret != -1 || errno != EFBIG) + { + perror ("write"); + abort (); + } + + return 0; +} + +int +main (void) +{ + int retcode; + int pid; + int st = 0; + long stack[16384]; + char buf[1]; + + retcode = pipe (pip); + + if (retcode != 0) + { + fprintf (stderr, "Bad pipe %d\n", retcode); + abort (); + } + +#ifdef PIPE_MAX + pipemax = PIPE_MAX; +#else + pipemax = fpathconf (pip[1], _PC_PIPE_BUF); +#endif + + if (pipemax <= 0) + { + fprintf (stderr, "Bad pipemax %d\n", pipemax); + abort (); + } + + pid = clone (process, (char *) stack + sizeof (stack) - 64, + (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) + | SIGCHLD, "ab"); + if (pid <= 0) + { + fprintf (stderr, "Bad clone %d\n", pid); + abort (); + } + + while ((retcode = read (pip[0], buf, 1)) == 0) + ; + + if (retcode != 1) + { + fprintf (stderr, "Bad read 1: %d\n", retcode); + abort (); + } + + printf ("got: %c\n", buf[0]); + + if (close (pip[0]) != 0) + { + perror ("pip close"); + abort (); + } + + retcode = waitpid (pid, &st, __WALL); + + if (retcode != pid || !WIFEXITED (st)) + { + fprintf (stderr, "Bad wait %d:%d %x\n", pid, retcode, st); + perror ("errno"); + abort (); + } + + printf ("exit: %d\n", WEXITSTATUS (st)); + return 0; +}
c/pipe6.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/clone3.c =================================================================== --- c/clone3.c (nonexistent) +++ c/clone3.c (revision 816) @@ -0,0 +1,45 @@ +/* Check that exiting from a parent thread does not kill the child. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int +process (void *arg) +{ + int i; + + for (i = 0; i < 50; i++) + if (sched_yield ()) + abort (); + + printf ("pass\n"); + return 0; +} + +int +main (void) +{ + int pid; + long stack[16384]; + + pid = clone (process, (char *) stack + sizeof (stack) - 64, + (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) + | SIGCHLD, "ab"); + if (pid <= 0) + { + fprintf (stderr, "Bad clone %d\n", pid); + abort (); + } + + exit (0); +}
c/clone3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sig12.c =================================================================== --- c/sig12.c (nonexistent) +++ c/sig12.c (revision 816) @@ -0,0 +1,38 @@ +/* Check that TRT happens for a signal sent to a non-existent process/thread, more than one thread. +#cc: additional_flags=-pthread +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + int i; + for (i = 0; i < 100; i++) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + int retcode; + void *retval; + + if (pthread_create (&th_a, NULL, process, (void *) "a") != 0) + abort (); + if (kill (getpid () - 1, SIGBUS) != -1 + || errno != ESRCH + || pthread_join (th_a, &retval) != 0) + abort (); + printf ("pass\n"); + exit (0); +}
c/sig12.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/badldso2.c =================================================================== --- c/badldso2.c (nonexistent) +++ c/badldso2.c (revision 816) @@ -0,0 +1,8 @@ +/* +#notarget: cris*-*-elf +#dynamic: +#xerror: +#cc: additional_flags=-Wl,-dynamic-linker,/dev/null +#output: *: could not load ELF interpreter `*' for program `*'\n + */ +#include "hello.c"
c/badldso2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/readlink11.c =================================================================== --- c/readlink11.c (nonexistent) +++ c/readlink11.c (revision 816) @@ -0,0 +1,9 @@ +/* As readlink5.c (sic), but specifying silent ENOSYS. +#notarget: cris*-*-elf +#dest: ./readlink11.c.x +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "readlink2.c"
c/readlink11.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/stat1.c =================================================================== --- c/stat1.c (nonexistent) +++ c/stat1.c (revision 816) @@ -0,0 +1,16 @@ +#include +#include +#include +#include +#include + +int main (void) +{ + struct stat buf; + + if (stat (".", &buf) != 0 + || !S_ISDIR (buf.st_mode)) + abort (); + printf ("pass\n"); + exit (0); +}
c/stat1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/stat5.c =================================================================== --- c/stat5.c (nonexistent) +++ c/stat5.c (revision 816) @@ -0,0 +1,20 @@ +/* Check that lstat:ing an nonexistent file works as expected. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +int main (void) +{ + struct stat buf; + + if (lstat ("nonexistent", &buf) == 0 || errno != ENOENT) + abort (); + printf ("pass\n"); + exit (0); +}
c/stat5.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/hellodyn3.c =================================================================== --- c/hellodyn3.c (nonexistent) +++ c/hellodyn3.c (revision 816) @@ -0,0 +1,9 @@ +/* Check that invoking ld.so as a program, invoking the main program, + works. Jump through a few hoops to avoid reading the host + ld.so.cache (having no absolute path specified for the executable + falls back on loading through the same mechanisms as a DSO). +#notarget: *-*-elf +#dynamic: +#sim: --sysroot=@exedir@ @exedir@/lib/ld.so.1 --library-path / + */ +#include "hello.c"
c/hellodyn3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sig2.c =================================================================== --- c/sig2.c (nonexistent) +++ c/sig2.c (revision 816) @@ -0,0 +1,32 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include + +/* Like sig1.c, but using sigaction. */ + +void +leave (int n, siginfo_t *info, void *x) +{ + abort (); +} + +int +main (void) +{ + struct sigaction sa; + sa.sa_sigaction = leave; + sa.sa_flags = SA_RESTART | SA_SIGINFO; + sigemptyset (&sa.sa_mask); + + /* Check that the sigaction syscall (for signal) is interpreted, though + possibly ignored. */ + if (sigaction (SIGFPE, &sa, NULL) != 0) + abort (); + + printf ("pass\n"); + exit (0); +}
c/sig2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/ugetrlimit1.c =================================================================== --- c/ugetrlimit1.c (nonexistent) +++ c/ugetrlimit1.c (revision 816) @@ -0,0 +1,21 @@ +/* Check corner error case: specifying unimplemented resource. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +int main (void) +{ + struct rlimit lim; + + if (getrlimit (RLIMIT_NPROC, &lim) != -1 + || errno != EINVAL) + abort (); + printf ("pass\n"); + exit (0); +}
c/ugetrlimit1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sig6.c =================================================================== --- c/sig6.c (nonexistent) +++ c/sig6.c (revision 816) @@ -0,0 +1,32 @@ +/* Check that TRT happens at an non-abort non-caught signal, more than one thread. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#xerror: +#output: Exiting pid 42 due to signal 7\n +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + while (1) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) + kill (getpid (), SIGBUS); + printf ("xyzzy\n"); + exit (0); +}
c/sig6.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/openpf2.c =================================================================== --- c/openpf2.c (nonexistent) +++ c/openpf2.c (revision 816) @@ -0,0 +1,16 @@ +/* Check that the simulator has chdir:ed to the --sysroot argument +#sim: --sysroot=@srcdir@ + (or that --sysroot is applied to relative file paths). */ + +#include +#include +#include +int main (int argc, char *argv[]) +{ + FILE *f = fopen ("openpf2.c", "rb"); + if (f == NULL) + abort (); + close (f); + printf ("pass\n"); + return 0; +}
c/openpf2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/ftruncate2.c =================================================================== --- c/ftruncate2.c (nonexistent) +++ c/ftruncate2.c (revision 816) @@ -0,0 +1,39 @@ +/* +#notarget: cris*-*-elf +*/ + +/* Check that we get a proper error indication if trying ftruncate on a + fd that is a pipe descriptor. */ + +#include +#include +#include +#include +int main (void) +{ + int pip[2]; + + if (pipe (pip) != 0) + { + perror ("pipe"); + abort (); + } + + if (ftruncate (pip[0], 20) == 0 || errno != EINVAL) + { + perror ("ftruncate 1"); + abort (); + } + + errno = 0; + + if (ftruncate (pip[1], 20) == 0 || errno != EINVAL) + { + perror ("ftruncate 2"); + abort (); + } + + printf ("pass\n"); + + exit (0); +}
c/ftruncate2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/mmap3.c =================================================================== --- c/mmap3.c (nonexistent) +++ c/mmap3.c (revision 816) @@ -0,0 +1,33 @@ +/* +#notarget: cris*-*-elf +*/ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + volatile unsigned char *a; + + /* Check that we can map a non-multiple of a page and still get a full page. */ + a = mmap (NULL, 0x4c, PROT_READ | PROT_WRITE | PROT_EXEC, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (a == NULL || a == (unsigned char *) -1) + abort (); + + a[0] = 0xbe; + a[8191] = 0xef; + memset ((char *) a + 1, 0, 8190); + + if (a[0] != 0xbe || a[8191] != 0xef) + abort (); + + printf ("pass\n"); + exit (0); +}
c/mmap3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/kill3.c =================================================================== --- c/kill3.c (nonexistent) +++ c/kill3.c (revision 816) @@ -0,0 +1,16 @@ +/* Basic kill functionality test; suicide. +#xerror: +#output: program stopped with signal 6.\n +*/ + +#include +#include +#include +#include +int +main (void) +{ + abort (); + printf ("undead\n"); + exit (1); +}
c/kill3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/mmap7.c =================================================================== --- c/mmap7.c (nonexistent) +++ c/mmap7.c (revision 816) @@ -0,0 +1,14 @@ +/* Check that mmapping a page-aligned size, larger than the file, + works. + +#notarget: cris*-*-elf +*/ + +/* Make sure we get an address where the size fits. */ +#define MMAP_SIZE1 ((sb.st_size + 8192) & ~8191) + +/* If this ever fails because the file is a page-multiple, we'll deal + with that then. We want it larger than the file-size anyway. */ +#define MMAP_SIZE2 ((size + 8192) & ~8191) +#define MMAP_FLAGS2 MAP_DENYWRITE | MAP_PRIVATE | MAP_FIXED +#include "mmap5.c"
c/mmap7.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/rename2.c =================================================================== --- c/rename2.c (nonexistent) +++ c/rename2.c (revision 816) @@ -0,0 +1,38 @@ +/* Test some execution paths for error cases. +#cc: additional_flags=-Wl,--section-start=.startup=0x8000 + The linker option is for sake of newlib, where the default program + layout starts at address 0. We need to change the layout so + there's no memory at 0, as all sim error checking is "lazy", + depending on lack of memory mapping. */ + +#include +#include +#include + +void err (const char *s) +{ + perror (s); + abort (); +} + +int main (int argc, char *argv[]) +{ + /* Avoid getting files with random characters due to errors + elsewhere. */ + if (argc != 1 + || (argv[0][0] != '.' && argv[0][0] != '/' && argv[0][0] != 'r')) + abort (); + + if (rename (argv[0], NULL) != -1 + || errno != EFAULT) + err ("rename 1 "); + + errno = 0; + + if (rename (NULL, argv[0]) != -1 + || errno != EFAULT) + err ("rename 2"); + + printf ("pass\n"); + return 0; +}
c/rename2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/thread3.c =================================================================== --- c/thread3.c (nonexistent) +++ c/thread3.c (revision 816) @@ -0,0 +1,46 @@ +/* Compiler options: +#cc: additional_flags=-pthread +#notarget: cris*-*-elf + + To test sched_yield in the presencs of threads. Core from ex1.c. */ + +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + int i; + for (i = 0; i < 10; i++) + { + if (sched_yield () != 0) + abort (); + } + return NULL; +} + +int +main (void) +{ + int retcode; + pthread_t th_a, th_b; + void *retval; + + retcode = pthread_create (&th_a, NULL, process, (void *) "a"); + if (retcode != 0) + abort (); + retcode = pthread_create (&th_b, NULL, process, (void *) "b"); + if (retcode != 0) + abort (); + retcode = pthread_join (th_a, &retval); + if (retcode != 0) + abort (); + retcode = pthread_join (th_b, &retval); + if (retcode != 0) + abort (); + printf ("pass\n"); + return 0; +}
c/thread3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/syscall2.c =================================================================== --- c/syscall2.c (nonexistent) +++ c/syscall2.c (revision 816) @@ -0,0 +1,23 @@ +/* Test unknown-syscall output. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented syscall: 0 (0x3, 0x2, 0x1, 0x4, 0x6, 0x5)\n +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include +#include + +int main (void) +{ + int err; + + /* Check special case of number 0 syscall. */ + err = syscall (0, 3, 2, 1, 4, 6, 5); + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + printf ("xyzzy\n"); + exit (0); +}
c/syscall2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/settls1.c =================================================================== --- c/settls1.c (nonexistent) +++ c/settls1.c (revision 816) @@ -0,0 +1,49 @@ +/* Check that the syscall set_thread_area is supported and does the right thing. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include + +#ifndef SYS_set_thread_area +#define SYS_set_thread_area 243 +#endif + +int main (void) +{ + int ret; + + /* Check the error check that the low 8 bits must be 0. */ + ret = syscall (SYS_set_thread_area, 0xfeeb1ff0); + if (ret != -1 || errno != EINVAL) + { + perror ("tls1"); + abort (); + } + + ret = syscall (SYS_set_thread_area, 0xcafebe00); + if (ret != 0) + { + perror ("tls2"); + abort (); + } + + /* Check that we got the right result. */ +#ifdef __arch_v32 + asm ("move $pid,%0\n\tclear.b %0" : "=rm" (ret)); +#else + asm ("move $brp,%0" : "=rm" (ret)); +#endif + + if (ret != 0xcafebe00) + { + perror ("tls2"); + abort (); + } + + printf ("pass\n"); + exit (0); +}
c/settls1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/syscall6.c =================================================================== --- c/syscall6.c (nonexistent) +++ c/syscall6.c (revision 816) @@ -0,0 +1,9 @@ +/* As the included file, but specifying ENOSYS with message. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys +#output: Unimplemented syscall: 0 (0x3, 0x2, 0x1, 0x4, 0x6, 0x5)\n +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "syscall2.c"
c/syscall6.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/writev2.c =================================================================== --- c/writev2.c (nonexistent) +++ c/writev2.c (revision 816) @@ -0,0 +1,28 @@ +/* Trivial test of failing writev: invalid file descriptor. +#notarget: cris*-*-elf +*/ +#include +#include +#include +#include + +#define X(x) {x, sizeof (x) -1} +struct iovec v[] = { + X("a"), + X("bcd"), + X("efghi"), + X("j"), + X("klmn\n"), +}; + +int main (void) +{ + if (writev (99, v, sizeof v / sizeof (v[0])) != -1 + /* The simulator write gives EINVAL instead of EBADF; let's + cope. */ + || (errno != EBADF && errno != EINVAL)) + abort (); + + printf ("pass\n"); + return 0; +}
c/writev2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sysctl3.c =================================================================== --- c/sysctl3.c (nonexistent) +++ c/sysctl3.c (revision 816) @@ -0,0 +1,8 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "sysctl2.c"
c/sysctl3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sigreturn4.c =================================================================== --- c/sigreturn4.c (nonexistent) +++ c/sigreturn4.c (revision 816) @@ -0,0 +1,9 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "sigreturn2.c"
c/sigreturn4.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/truncate1.c =================================================================== --- c/truncate1.c (nonexistent) +++ c/truncate1.c (revision 816) @@ -0,0 +1,49 @@ +/* Check that the truncate syscall works trivially. +#notarget: cris*-*-elf +*/ + +#include +#include +#include + +#ifndef PREFIX +#define PREFIX +#endif +int +main (void) +{ + FILE *f; + const char fname[] = PREFIX "sk1test.dat"; + const char tsttxt1[] + = "This is the first and only line of this file.\n"; + const char tsttxt2[] = "Now there is a second line.\n"; + char buf[sizeof (tsttxt1) + sizeof (tsttxt2) - 1] = ""; + + f = fopen (fname, "w+"); + if (f == NULL + || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1) + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + if (truncate (fname, strlen(tsttxt1) - 10) != 0) + { + perror ("truncate"); + exit (1); + } + + f = fopen (fname, "r"); + if (f == NULL + || fread (buf, 1, sizeof (buf), f) != strlen (tsttxt1) - 10 + || strncmp (buf, tsttxt1, strlen (tsttxt1) - 10) != 0 + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +}
c/truncate1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/seek1.c =================================================================== --- c/seek1.c (nonexistent) +++ c/seek1.c (revision 816) @@ -0,0 +1,47 @@ +/* Check that basic (ll|f)seek sim functionality works. Also uses basic + file open/write functionality. */ +#include +#include +#include + +int +main (void) +{ + FILE *f; + const char fname[] = "sk1test.dat"; + const char tsttxt[] + = "A random line of text, used to test correct read, write and seek.\n"; + char buf[sizeof tsttxt] = ""; + + f = fopen (fname, "w"); + if (f == NULL + || fwrite (tsttxt, 1, strlen (tsttxt), f) != strlen (tsttxt) + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + /* Using "rb" to make this test similar to the use in genconf.c in + GhostScript. */ + f = fopen (fname, "rb"); + if (f == NULL + || fseek (f, 0L, SEEK_END) != 0 + || ftell (f) != strlen (tsttxt)) + { + printf ("fail\n"); + exit (1); + } + + rewind (f); + if (fread (buf, 1, strlen (tsttxt), f) != strlen (tsttxt) + || strcmp (buf, tsttxt) != 0 + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +}
c/seek1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sched4.c =================================================================== --- c/sched4.c (nonexistent) +++ c/sched4.c (revision 816) @@ -0,0 +1,24 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (void) +{ + struct sched_param sb; + sb.sched_priority = 0; + if (sched_setparam (getpid (), &sb) != 0 + || sb.sched_priority != 0) + abort (); + sb.sched_priority = 5; + if (sched_setparam (getpid (), &sb) == 0 + || errno != EINVAL + || sb.sched_priority != 5) + abort (); + printf ("pass\n"); + exit (0); +}
c/sched4.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/readlink1.c =================================================================== --- c/readlink1.c (nonexistent) +++ c/readlink1.c (revision 816) @@ -0,0 +1,20 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + char buf[1024]; + /* This depends on the test-setup, but it's unlikely that the program + is passed as a symlink, so supposedly safe. */ + if (readlink(argv[0], buf, sizeof (buf)) != -1 || errno != EINVAL) + abort (); + + printf ("pass\n"); + exit (0); +}
c/readlink1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/rtsigsuspend2.c =================================================================== --- c/rtsigsuspend2.c (nonexistent) +++ c/rtsigsuspend2.c (revision 816) @@ -0,0 +1,8 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "rtsigsuspend1.c"
c/rtsigsuspend2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/mapbrk.c =================================================================== --- c/mapbrk.c (nonexistent) +++ c/mapbrk.c (revision 816) @@ -0,0 +1,39 @@ +#include +#include + +/* Basic sanity check that syscalls to implement malloc (brk, mmap2, + munmap) are trivially functional. */ + +int main () +{ + void *p1, *p2, *p3, *p4, *p5, *p6; + + if ((p1 = malloc (8100)) == NULL + || (p2 = malloc (16300)) == NULL + || (p3 = malloc (4000)) == NULL + || (p4 = malloc (500)) == NULL + || (p5 = malloc (1023*1024)) == NULL + || (p6 = malloc (8191*1024)) == NULL) + { + printf ("fail\n"); + exit (1); + } + + free (p1); + free (p2); + free (p3); + free (p4); + free (p5); + free (p6); + + p1 = malloc (64000); + if (p1 == NULL) + { + printf ("fail\n"); + exit (1); + } + free (p1); + + printf ("pass\n"); + exit (0); +}
c/mapbrk.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sched8.c =================================================================== --- c/sched8.c (nonexistent) +++ c/sched8.c (revision 816) @@ -0,0 +1,19 @@ +/* Check corner error case: specifying invalid PID. +#notarget: cris*-*-elf +*/ +#include +#include +#include +#include +#include + +int main (void) +{ + struct sched_param sb; + memset (&sb, -1, sizeof sb); + if (sched_getparam (99, &sb) != -1 + || errno != ESRCH) + abort (); + printf ("pass\n"); + exit (0); +}
c/sched8.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/hellodyn.c =================================================================== --- c/hellodyn.c (nonexistent) +++ c/hellodyn.c (revision 816) @@ -0,0 +1,5 @@ +/* +#dynamic: +#sim: --sysroot=@exedir@ + */ +#include "hello.c"
c/hellodyn.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/readlink5.c =================================================================== --- c/readlink5.c (nonexistent) +++ c/readlink5.c (revision 816) @@ -0,0 +1,8 @@ +/* Check that unsupported readlink calls don't cause the simulator to abort. +#notarget: cris*-*-elf +#dest: ./readlink5.c.x +#xerror: +#output: Unimplemented readlink syscall (*)\n +#output: program stopped with signal 4.\n +*/ +#include "readlink2.c"
c/readlink5.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/time1.c =================================================================== --- c/time1.c (nonexistent) +++ c/time1.c (revision 816) @@ -0,0 +1,46 @@ +/* Basic time functionality test: check that milliseconds are + incremented for each syscall (does not work on host). */ +#include +#include +#include +#include +#include + +void err (const char *s) +{ + perror (s); + abort (); +} + +int +main (void) +{ + struct timeval t_m = {0, 0}; + struct timezone t_z = {0, 0}; + struct timeval t_m1 = {0, 0}; + int i; + + if (gettimeofday (&t_m, &t_z) != 0) + err ("gettimeofday"); + + for (i = 1; i < 10000; i++) + if (gettimeofday (&t_m1, NULL) != 0) + err ("gettimeofday 1"); + else + if (t_m1.tv_sec * 1000000 + t_m1.tv_usec + != (t_m.tv_sec * 1000000 + t_m.tv_usec + i * 1000)) + { + fprintf (stderr, "t0 (%ld, %ld), i %d, t1 (%ld, %ld)\n", + t_m.tv_sec, t_m.tv_usec, i, t_m1.tv_sec, t_m1.tv_usec); + abort (); + } + + if (time (NULL) != t_m1.tv_sec) + { + fprintf (stderr, "time != gettod\n"); + abort (); + } + + printf ("pass\n"); + exit (0); +}
c/time1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/pipe3.c =================================================================== --- c/pipe3.c (nonexistent) +++ c/pipe3.c (revision 816) @@ -0,0 +1,48 @@ +/* Check that TRT happens when error on pipe call. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +int main (void) +{ + int i; + int filemax; + +#ifdef OPEN_MAX + filemax = OPEN_MAX; +#else + filemax = sysconf (_SC_OPEN_MAX); +#endif + + /* Check that TRT happens when error on pipe call. */ + for (i = 0; i < filemax + 1; i++) + { + int pip[2]; + if (pipe (pip) != 0) + { + /* Shouldn't happen too early. */ + if (i < filemax / 2 - 3 - 1) + { + fprintf (stderr, "i: %d\n", i); + abort (); + } + if (errno != EMFILE) + { + perror ("pipe"); + abort (); + } + goto ok; + } + } + abort (); + +ok: + printf ("pass\n"); + exit (0); +}
c/pipe3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/readlink9.c =================================================================== --- c/readlink9.c (nonexistent) +++ c/readlink9.c (revision 816) @@ -0,0 +1,23 @@ +/* Check that odd cases of readlink work. +#notarget: cris*-*-elf +#cc: additional_flags=-DX="@exedir@" +*/ + +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + /* We assume that "sim/testsuite" isn't renamed to anything that + together with "/" is shorter than 7 characters. */ + char buf[7]; + + if (readlink("/proc/42/exe", buf, sizeof (buf)) != sizeof (buf) + || strncmp (buf, X, sizeof (buf)) != 0) + abort (); + + printf ("pass\n"); + exit (0); +}
c/readlink9.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/pipe7.c =================================================================== --- c/pipe7.c (nonexistent) +++ c/pipe7.c (revision 816) @@ -0,0 +1,21 @@ +/* Check for proper pipe semantics at corner cases. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (void) +{ + if (pipe (NULL) != -1 + || errno != EFAULT) + { + perror ("pipe"); + abort (); + } + + printf ("pass\n"); + exit (0); +}
c/pipe7.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/clone4.c =================================================================== --- c/clone4.c (nonexistent) +++ c/clone4.c (revision 816) @@ -0,0 +1,61 @@ +/* Check that TRT happens when we reach the #threads implementation limit. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int +process (void *arg) +{ + int i; + + for (i = 0; i < 500; i++) + if (sched_yield ()) + abort (); + + return 0; +} + +int +main (void) +{ + int pid; + int i; + int stacksize = 16384; + + for (i = 0; i < 1000; i++) + { + char *stack = malloc (stacksize); + if (stack == NULL) + abort (); + + pid = clone (process, (char *) stack + stacksize - 64, + (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) + | SIGCHLD, "ab"); + if (pid <= 0) + { + /* FIXME: Read sysconf instead of magic number. */ + if (i < 60) + { + fprintf (stderr, "Bad clone %d\n", pid); + abort (); + } + + if (errno == EAGAIN) + { + printf ("pass\n"); + exit (0); + } + } + } + + abort (); +}
c/clone4.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sig13.c =================================================================== --- c/sig13.c (nonexistent) +++ c/sig13.c (revision 816) @@ -0,0 +1,8 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "sig7.c"
c/sig13.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/badldso3.c =================================================================== --- c/badldso3.c (nonexistent) +++ c/badldso3.c (revision 816) @@ -0,0 +1,9 @@ +/* +#notarget: cris*-*-elf +#dynamic: +#xerror: +#cc: additional_flags=-Wl,-dynamic-linker,/compilercheck.x +#sim: --sysroot=@exedir@ +#output: *: could not load ELF interpreter `*' for program `*'\n + */ +#include "hello.c"
c/badldso3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/helloaout.c =================================================================== --- c/helloaout.c (nonexistent) +++ c/helloaout.c (revision 816) @@ -0,0 +1,10 @@ +/* Make sure we don't just assume ELF all over. (We have to jump + through hoops to get runnable a.out out of the ELF setup, and + having problems with a.out and discontinous section arrangements + doesn't help. Adjust as needed to get a.out which says "pass". If + necessary, move to the asm subdir. By design, it doesn't work with + CRIS v32.) +#target: cris-*-elf +#cc: ldflags=-Wl,-mcrisaout\ -sim\ -Ttext=0 +*/ +#include "hello.c"
c/helloaout.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/stat2.c =================================================================== --- c/stat2.c (nonexistent) +++ c/stat2.c (revision 816) @@ -0,0 +1,20 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include + +int main (void) +{ + struct stat buf; + + if (lstat (".", &buf) != 0 + || !S_ISDIR (buf.st_mode)) + abort (); + printf ("pass\n"); + exit (0); +}
c/stat2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/getcwd1.c =================================================================== --- c/getcwd1.c (nonexistent) +++ c/getcwd1.c (revision 816) @@ -0,0 +1,18 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + if (getcwd ((void *) -1, 4096) != NULL + || errno != EFAULT) + abort (); + + printf ("pass\n"); + exit (0); +}
c/getcwd1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/exitg1.c =================================================================== --- c/exitg1.c (nonexistent) +++ c/exitg1.c (revision 816) @@ -0,0 +1,20 @@ +/* Check exit_group(2) trivially. Newlib doesn't have it and the + pre-v32 glibc requires updated headers we'd have to check or adjust + for. +#notarget: cris-*-* *-*-elf +#output: exit_group\n +*/ +#include +#include +#include +#include +#ifndef EXITVAL +#define EXITVAL 0 +#endif +int main (int argc, char **argv) +{ + printf ("exit_group\n"); + syscall (SYS_exit_group, EXITVAL); + printf ("failed\n"); + abort (); +}
c/exitg1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sig3.c =================================================================== --- c/sig3.c (nonexistent) +++ c/sig3.c (revision 816) @@ -0,0 +1,13 @@ +/* Check that TRT happens at an abort (3) call, single thread. +#xerror: +#output: program stopped with signal 6.\n +*/ + +#include +#include +int main (void) +{ + abort (); + printf ("xyzzy\n"); + exit (0); +}
c/sig3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sig7.c =================================================================== --- c/sig7.c (nonexistent) +++ c/sig7.c (revision 816) @@ -0,0 +1,27 @@ +/* Check unsupported case of sigaction syscall. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented rt_sigaction syscall (0x8, 0x3df*\n +#output: program stopped with signal 4.\n +*/ +#include +#include +#include +#include + +int +main (void) +{ + struct sigaction sa; + int err; + sa.sa_sigaction = NULL; + sa.sa_flags = SA_RESTART | SA_SIGINFO; + sigemptyset (&sa.sa_mask); + + err = sigaction (SIGFPE, &sa, NULL); + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + + printf ("xyzzy\n"); + exit (0); +}
c/sig7.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/openpf3.c =================================================================== --- c/openpf3.c (nonexistent) +++ c/openpf3.c (revision 816) @@ -0,0 +1,49 @@ +/* Basic file operations (rename, unlink); once without sysroot. We + also test that the simulator has chdir:ed to PREFIX, when defined. */ + +#include +#include +#include +#include +#include +#include + +#ifndef PREFIX +#define PREFIX +#endif + +void err (const char *s) +{ + perror (s); + abort (); +} + +int main (int argc, char *argv[]) +{ + FILE *f; + struct stat buf; + + unlink (PREFIX "testfoo2.tmp"); + + f = fopen ("testfoo1.tmp", "w"); + if (f == NULL) + err ("open"); + fclose (f); + + if (rename (PREFIX "testfoo1.tmp", PREFIX "testfoo2.tmp") != 0) + err ("rename"); + + if (stat (PREFIX "testfoo2.tmp", &buf) != 0 + || !S_ISREG (buf.st_mode)) + err ("stat 1"); + + if (stat ("testfoo2.tmp", &buf) != 0 + || !S_ISREG (buf.st_mode)) + err ("stat 2"); + + if (unlink (PREFIX "testfoo2.tmp") != 0) + err ("unlink"); + + printf ("pass\n"); + return 0; +}
c/openpf3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/mmap4.c =================================================================== --- c/mmap4.c (nonexistent) +++ c/mmap4.c (revision 816) @@ -0,0 +1,5 @@ +/* Just check that MAP_DENYWRITE is "honored" (ignored). +#notarget: cris*-*-elf +*/ +#define MMAP_FLAGS (MAP_PRIVATE|MAP_DENYWRITE) +#include "mmap1.c"
c/mmap4.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/mmap8.c =================================================================== --- c/mmap8.c (nonexistent) +++ c/mmap8.c (revision 816) @@ -0,0 +1,9 @@ +/* Check that mmapping 0 using MAP_FIXED works, both with/without + there being previously mmapped contents. +#notarget: cris*-*-elf +*/ +#define MMAP_FLAGS1 MAP_PRIVATE | MAP_ANONYMOUS | MAP_FIXED +#define NO_MUNMAP +#define MMAP_SIZE2 8192 +#define MMAP_TEST_BAD (a != b || a != 0) +#include "mmap5.c"
c/mmap8.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/fcntl1.c =================================================================== --- c/fcntl1.c (nonexistent) +++ c/fcntl1.c (revision 816) @@ -0,0 +1,19 @@ +/* Check that we get the expected message for unsupported fcntl calls. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented fcntl* +#output: program stopped with signal 4.\n +*/ +#include +#include +#include +#include + +int main (void) +{ + int err = fcntl (1, 42); + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + printf ("xyzzy\n"); + exit (0); +}
c/fcntl1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/thread4.c =================================================================== --- c/thread4.c (nonexistent) +++ c/thread4.c (revision 816) @@ -0,0 +1,50 @@ +/* Compiler options: +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#output: abb ok\n + + Testing a pthread corner case. Output will change with glibc + releases. */ + +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + int i; + + if (pthread_setcancelstate (PTHREAD_CANCEL_ENABLE, NULL) != 0) + abort (); + write (2, "a", 1); + for (i = 0; i < 10; i++) + { + sched_yield (); + pthread_testcancel (); + write (2, "b", 1); + } + return NULL; +} + +int +main (void) +{ + int retcode; + pthread_t th_a; + void *retval; + + retcode = pthread_create (&th_a, NULL, process, NULL); + sched_yield (); + sched_yield (); + sched_yield (); + sched_yield (); + retcode = pthread_cancel (th_a); + retcode = pthread_join (th_a, &retval); + if (retcode != 0) + abort (); + fprintf (stderr, " ok\n"); + return 0; +}
c/thread4.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/syscall3.c =================================================================== --- c/syscall3.c (nonexistent) +++ c/syscall3.c (revision 816) @@ -0,0 +1,9 @@ +/* As the included file, just actually specifying the default. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=stop +#xerror: +#output: Unimplemented syscall: 166 (0x1, 0x2, 0x3, 0x4, 0x5, 0x6)\n +#output: program stopped with signal 4.\n +*/ + +#include "syscall1.c"
c/syscall3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/syscall7.c =================================================================== --- c/syscall7.c (nonexistent) +++ c/syscall7.c (revision 816) @@ -0,0 +1,8 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "syscall1.c"
c/syscall7.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sigreturn1.c =================================================================== --- c/sigreturn1.c (nonexistent) +++ c/sigreturn1.c (revision 816) @@ -0,0 +1,21 @@ +/* Test that TRT happens for spurious sigreturn calls. Single-thread. +#notarget: cris*-*-elf +#xerror: +#output: Invalid sigreturn syscall: no signal handler active (0x1, 0x2, 0x3, 0x4, 0x5, 0x6)\n +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include +#include +#include + +int main (void) +{ + int err = syscall (SYS_sigreturn, 1, 2, 3, 4, 5, 6); + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + printf ("xyzzy\n"); + exit (0); +}
c/sigreturn1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/truncate2.c =================================================================== --- c/truncate2.c (nonexistent) +++ c/truncate2.c (revision 816) @@ -0,0 +1,6 @@ +/* +#sim: --sysroot=@exedir@ +#notarget: cris*-*-elf +*/ +#define PREFIX "/" +#include "truncate1.c"
c/truncate2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sched1.c =================================================================== --- c/sched1.c (nonexistent) +++ c/sched1.c (revision 816) @@ -0,0 +1,15 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include + +int main (void) +{ + if (sched_getscheduler (getpid ()) != SCHED_OTHER) + abort (); + printf ("pass\n"); + exit (0); +}
c/sched1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/seek2.c =================================================================== --- c/seek2.c (nonexistent) +++ c/seek2.c (revision 816) @@ -0,0 +1,4 @@ +/* Simulator options: +#sim: --sysroot=@exedir@/ +*/ +#include "seek1.c"
c/seek2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/readlink2.c =================================================================== --- c/readlink2.c (nonexistent) +++ c/readlink2.c (revision 816) @@ -0,0 +1,80 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + char buf[1024]; + char buf2[1024]; + int err; + + /* This is a special feature handled in the simulator. The "42" + should be formed from getpid () if this was a real program. */ + err = readlink ("/proc/42/exe", buf, sizeof (buf)); + if (err < 0) + { + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + printf ("xyzzy\n"); + exit (0); + } + + /* Don't use an abort in the following; it might cause the printf to + not make it all the way to output and make debugging more + difficult. */ + + /* We assume the program is called with no path, so we might need to + prepend it. */ + if (getcwd (buf2, sizeof (buf2)) != buf2) + { + perror ("getcwd"); + exit (1); + } + + if (argv[0][0] == '/') + { +#ifdef SYSROOTED + if (strchr (argv[0] + 1, '/') != NULL) + { + printf ("%s != %s\n", argv[0], strrchr (argv[0] + 1, '/')); + exit (1); + } +#endif + if (strcmp (argv[0], buf) != 0) + { + printf ("%s != %s\n", buf, argv[0]); + exit (1); + } + } + else if (argv[0][0] != '.') + { + if (buf2[strlen (buf2) - 1] != '/') + strcat (buf2, "/"); + strcat (buf2, argv[0]); + if (strcmp (buf2, buf) != 0) + { + printf ("%s != %s\n", buf, buf2); + exit (1); + } + } + else + { + strcat (buf2, argv[0] + 1); + if (strcmp (buf, buf2) != 0) + { + printf ("%s != %s\n", buf, buf2); + exit (1); + } + } + + printf ("pass\n"); + exit (0); +} + +
c/readlink2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sched5.c =================================================================== --- c/sched5.c (nonexistent) +++ c/sched5.c (revision 816) @@ -0,0 +1,19 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +int main (void) +{ + int Min = sched_get_priority_min (SCHED_OTHER); + int Max = sched_get_priority_max (SCHED_OTHER); + if (Min != 0 || Max != 0) + { + fprintf (stderr, "min: %d, max: %d\n", Min, Max); + abort (); + } + printf ("pass\n"); + exit (0); +}
c/sched5.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/mprotect1.c =================================================================== --- c/mprotect1.c (nonexistent) +++ c/mprotect1.c (revision 816) @@ -0,0 +1,19 @@ +/* Check unimplemented-output for mprotect call. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented mprotect call (0x0, 0x2001, 0x4)\n +#output: program stopped with signal 4.\n + */ +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + int err = mprotect (0, 8193, PROT_EXEC); + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + printf ("xyzzy\n"); + exit (0); +}
c/mprotect1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/readlink6.c =================================================================== --- c/readlink6.c (nonexistent) +++ c/readlink6.c (revision 816) @@ -0,0 +1,5 @@ +/* Check that rare readlink calls don't cause the simulator to abort. +#notarget: cris*-*-elf +#dest: @exedir@/readlink6.c.x +*/ +#include "readlink2.c"
c/readlink6.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sched9.c =================================================================== --- c/sched9.c (nonexistent) +++ c/sched9.c (revision 816) @@ -0,0 +1,24 @@ +/* Check corner error case: specifying invalid scheduling policy. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (void) +{ + if (sched_get_priority_min (-1) != -1 + || errno != EINVAL) + abort (); + + errno = 0; + + if (sched_get_priority_max (-1) != -1 + || errno != EINVAL) + abort (); + + printf ("pass\n"); + exit (0); +}
c/sched9.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/time2.c =================================================================== --- c/time2.c (nonexistent) +++ c/time2.c (revision 816) @@ -0,0 +1,18 @@ +/* CB_SYS_time doesn't implement the Linux time syscall; the return + value isn't written to the argument. */ + +#include +#include +#include + +int +main (void) +{ + time_t x = (time_t) -1; + time_t t = time (&x); + + if (t == (time_t) -1 || t != x) + abort (); + printf ("pass\n"); + exit (0); +}
c/time2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sock1.c =================================================================== --- c/sock1.c (nonexistent) +++ c/sock1.c (revision 816) @@ -0,0 +1,32 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +/* Check that socketcall is suitably stubbed. */ + +int main (void) +{ + int ret = socket (PF_INET, SOCK_STREAM, IPPROTO_TCP); + + if (ret != -1) + { + fprintf (stderr, "sock: %d\n", ret); + abort (); + } + + if (errno != ENOSYS) + { + perror ("unexpected"); + abort (); + } + + printf ("pass\n"); + return 0; +}
c/sock1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/pipe4.c =================================================================== --- c/pipe4.c (nonexistent) +++ c/pipe4.c (revision 816) @@ -0,0 +1,66 @@ +/* Check that TRT happens for pipe corner cases. +#notarget: cris*-*-elf +*/ +#include +#include +#include +#include +#include +#include +#include + +void err (const char *s) +{ + perror (s); + abort (); +} + +int main (void) +{ + int pip[2]; + char c; + int pipemax; + + if (pipe (pip) != 0) + err ("pipe"); + +#ifdef PIPE_MAX + pipemax = PIPE_MAX; +#else + pipemax = fpathconf (pip[1], _PC_PIPE_BUF); +#endif + + if (pipemax <= 0) + { + fprintf (stderr, "Bad pipemax %d\n", pipemax); + abort (); + } + + /* Writing to wrong end of pipe. */ + if (write (pip[0], "argh", 1) != -1 + || errno != EBADF) + err ("write pipe"); + + errno = 0; + + /* Reading from wrong end of pipe. */ + if (read (pip[1], &c, 1) != -1 + || errno != EBADF) + err ("write pipe"); + + errno = 0; + + if (close (pip[0]) != 0) + err ("close"); + + if (signal (SIGPIPE, SIG_IGN) != SIG_DFL) + err ("signal"); + + /* Writing to pipe with closed read end. */ + if (write (pip[1], "argh", 1) != -1 + || errno != EPIPE) + err ("write closed"); + + printf ("pass\n"); + exit (0); +}
c/pipe4.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/mremap.c =================================================================== --- c/mremap.c (nonexistent) +++ c/mremap.c (revision 816) @@ -0,0 +1,31 @@ +#include +#include + +/* Sanity check that system calls for realloc works. Also tests a few + more cases for mmap2 and munmap. */ + +int main () +{ + void *p1, *p2; + + if ((p1 = malloc (8100)) == NULL + || (p1 = realloc (p1, 16300)) == NULL + || (p1 = realloc (p1, 4000)) == NULL + || (p1 = realloc (p1, 500)) == NULL + || (p1 = realloc (p1, 1023*1024)) == NULL + || (p1 = realloc (p1, 8191*1024)) == NULL + || (p1 = realloc (p1, 512*1024)) == NULL + || (p2 = malloc (1023*1024)) == NULL + || (p1 = realloc (p1, 1023*1024)) == NULL + || (p1 = realloc (p1, 8191*1024)) == NULL + || (p1 = realloc (p1, 512*1024)) == NULL) + { + printf ("fail\n"); + exit (1); + } + + free (p1); + free (p2); + printf ("pass\n"); + exit (0); +}
c/mremap.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/clone1.c =================================================================== --- c/clone1.c (nonexistent) +++ c/clone1.c (revision 816) @@ -0,0 +1,90 @@ +/* +#notarget: cris*-*-elf +#output: got: a\nthen: bc\nexit: 0\n +*/ + +/* This is a very limited subset of what ex1.c does; we just check that + thread creation (clone syscall) and pipe writes and reads work. */ + +#include +#include +#include +#include +#include +#include +#include +#include + +int pip[2]; + +int +process (void *arg) +{ + char *s = arg; + if (write (pip[1], s+2, 1) != 1) abort (); + if (write (pip[1], s+1, 1) != 1) abort (); + if (write (pip[1], s, 1) != 1) abort (); + return 0; +} + +int +main (void) +{ + int retcode; + int pid; + int st; + long stack[16384]; + char buf[10] = {0}; + + retcode = pipe (pip); + + if (retcode != 0) + { + fprintf (stderr, "Bad pipe %d\n", retcode); + abort (); + } + + pid = clone (process, (char *) stack + sizeof (stack) - 64, + (CLONE_VM | CLONE_FS | CLONE_FILES | CLONE_SIGHAND) + | SIGCHLD, "cba"); + if (pid <= 0) + { + fprintf (stderr, "Bad clone %d\n", pid); + abort (); + } + + if ((retcode = read (pip[0], buf, 1)) != 1) + { + fprintf (stderr, "Bad read 1: %d\n", retcode); + abort (); + } + printf ("got: %c\n", buf[0]); + retcode = read (pip[0], buf, 2); + if (retcode == 1) + { + retcode = read (pip[0], buf+1, 1); + if (retcode != 1) + { + fprintf (stderr, "Bad read 1.5: %d\n", retcode); + abort (); + } + retcode = 2; + } + if (retcode != 2) + { + fprintf (stderr, "Bad read 2: %d\n", retcode); + abort (); + } + + printf ("then: %s\n", buf); + retcode = wait4 (-1, &st, WNOHANG | __WCLONE, NULL); + + if (retcode != pid || !WIFEXITED (st)) + { + fprintf (stderr, "Bad wait %d %x\n", retcode, st); + abort (); + } + + printf ("exit: %d\n", WEXITSTATUS (st)); + return 0; +}
c/clone1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sig10.c =================================================================== --- c/sig10.c (nonexistent) +++ c/sig10.c (revision 816) @@ -0,0 +1,33 @@ +/* Check that TRT happens when trying to IGN an non-ignorable signal, more than one thread. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#xerror: +#output: Exiting pid 42 due to signal 9\n +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + while (1) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + signal (SIGKILL, SIG_IGN); + if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) + kill (getpid (), SIGKILL); + printf ("xyzzy\n"); + exit (0); +}
c/sig10.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/clone5.c =================================================================== --- c/clone5.c (nonexistent) +++ c/clone5.c (revision 816) @@ -0,0 +1,35 @@ +/* Check that unimplemented clone syscalls get the right treatment. +#notarget: cris*-*-elf +#xerror: +#output: Unimplemented clone syscall * +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include +#include +#include +#include +#include + +int pip[2]; + +int +process (void *arg) +{ + return 0; +} + +int +main (void) +{ + int retcode; + long stack[16384]; + + retcode = clone (process, (char *) stack + sizeof (stack) - 64, 0, "cba"); + if (retcode == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + printf ("xyzzy\n"); + return 0; +}
c/clone5.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/uname1.c =================================================================== --- c/uname1.c (nonexistent) +++ c/uname1.c (revision 816) @@ -0,0 +1,21 @@ +/* Check that the right machine name appears in the uname result. +#notarget: *-*-elf +*/ +#include +#include +#include +int main (void) +{ + struct utsname buf; + if (uname (&buf) != 0 + || strcmp (buf.machine, +#ifdef __arch_v32 + "crisv32" +#else + "cris" +#endif + ) != 0) + abort (); + printf ("pass\n"); + exit (0); +}
c/uname1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/fdopen1.c =================================================================== --- c/fdopen1.c (nonexistent) +++ c/fdopen1.c (revision 816) @@ -0,0 +1,54 @@ +/* Check that the syscalls implementing fdopen work trivially. */ + +#include +#include +#include +#include +#include + +void +perr (const char *s) +{ + perror (s); + exit (1); +} + +int +main (void) +{ + FILE *f; + int fd; + const char fname[] = "sk1test.dat"; + const char tsttxt1[] + = "This is the first and only line of this file.\n"; + char buf[sizeof (tsttxt1)] = ""; + + fd = open (fname, O_WRONLY|O_TRUNC|O_CREAT, S_IRWXU); + if (fd <= 0) + perr ("open-w"); + + f = fdopen (fd, "w"); + if (f == NULL + || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1)) + perr ("fdopen or fwrite"); + + if (fclose (f) != 0) + perr ("fclose"); + + fd = open (fname, O_RDONLY); + if (fd <= 0) + perr ("open-r"); + + f = fdopen (fd, "r"); + if (f == NULL + || fread (buf, 1, sizeof (buf), f) != strlen (tsttxt1) + || strcmp (buf, tsttxt1) != 0 + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +}
c/fdopen1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/stat3.c =================================================================== --- c/stat3.c (nonexistent) +++ c/stat3.c (revision 816) @@ -0,0 +1,26 @@ +/* Simulator options: +#sim: --sysroot=@exedir@ +*/ +#include +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + char path[1024] = "/"; + struct stat buf; + + strcat (path, argv[0]); + if (stat (".", &buf) != 0 + || !S_ISDIR (buf.st_mode)) + abort (); + if (stat (path, &buf) != 0 + || !S_ISREG (buf.st_mode)) + abort (); + printf ("pass\n"); + exit (0); +} +
c/stat3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/exitg2.c =================================================================== --- c/exitg2.c (nonexistent) +++ c/exitg2.c (revision 816) @@ -0,0 +1,7 @@ +/* Check exit_group(2) trivially with non-zero status. +#notarget: cris-*-* *-*-elf +#output: exit_group\n +#xerror: +*/ +#define EXITVAL 1 +#include "exitg1.c"
c/exitg2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/stat7.c =================================================================== --- c/stat7.c (nonexistent) +++ c/stat7.c (revision 816) @@ -0,0 +1,26 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include + +int main (void) +{ + struct stat buf; + + /* From Linux, we get EFAULT. The simulator sends us EINVAL. */ + if (lstat (NULL, &buf) != -1 + || (errno != EINVAL && errno != EFAULT)) + { + perror ("lstat 1"); + abort (); + } + + printf ("pass\n"); + exit (0); +}
c/stat7.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/hello.c =================================================================== --- c/hello.c (nonexistent) +++ c/hello.c (revision 816) @@ -0,0 +1,7 @@ +#include +#include +int main () +{ + printf ("pass\n"); + exit (0); +}
c/hello.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sig4.c =================================================================== --- c/sig4.c (nonexistent) +++ c/sig4.c (revision 816) @@ -0,0 +1,30 @@ +/* Check that TRT happens at an abort (3) call, more than one thread. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#xerror: +#output: Exiting pid 42 due to signal 6\n +#output: program stopped with signal 6.\n +*/ + +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + while (1) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) + abort (); + printf ("xyzzy\n"); + exit (0); +}
c/sig4.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sig8.c =================================================================== --- c/sig8.c (nonexistent) +++ c/sig8.c (revision 816) @@ -0,0 +1,19 @@ +/* Check that TRT happens for an ignored catchable signal, single thread. +#xerror: +#output: Unimplemented signal: 14\n +#output: program stopped with signal 4.\n + + Sure, it'd probably be better to support signals in single-thread too, + but that's on an as-need basis, and I don't have a need for it yet. */ + +#include +#include +#include +#include +int main (void) +{ + signal (SIGALRM, SIG_IGN); + kill (getpid (), SIGALRM); + printf ("xyzzy\n"); + exit (0); +}
c/sig8.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/openpf4.c =================================================================== --- c/openpf4.c (nonexistent) +++ c/openpf4.c (revision 816) @@ -0,0 +1,5 @@ +/* Basic file operations, now *with* sysroot. +#sim: --sysroot=@exedir@ +*/ +#define PREFIX "/" +#include "openpf3.c"
c/openpf4.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/mmap1.c =================================================================== --- c/mmap1.c (nonexistent) +++ c/mmap1.c (revision 816) @@ -0,0 +1,52 @@ +/* +#notarget: cris*-*-elf +*/ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + int fd = open (argv[0], O_RDONLY); + struct stat sb; + int size; + void *a; + const char *str = "a string you'll only find in the program"; + + if (fd == -1) + { + perror ("open"); + abort (); + } + + if (fstat (fd, &sb) < 0) + { + perror ("fstat"); + abort (); + } + + size = sb.st_size; + + /* We want to test mmapping a size that isn't exactly a page. */ + if ((size & 8191) == 0) + size--; + +#ifndef MMAP_FLAGS +#define MMAP_FLAGS MAP_PRIVATE +#endif + + a = mmap (NULL, size, PROT_READ, MMAP_FLAGS, fd, 0); + + if (memmem (a, size, str, strlen (str) + 1) == NULL) + abort (); + + printf ("pass\n"); + exit (0); +}
c/mmap1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/kill1.c =================================================================== --- c/kill1.c (nonexistent) +++ c/kill1.c (revision 816) @@ -0,0 +1,30 @@ +/* Basic kill functionality test; fail killing init. Don't run as root. */ +#include +#include +#include +#include +#include +int +main (void) +{ + if (kill (1, SIGTERM) != -1 + || errno != EPERM) + { + printf ("fail\n"); + exit (1); + } + + errno = 0; + + if (kill (1, SIGABRT) != -1 + || errno != EPERM) + { + printf ("fail\n"); + exit (1); + } + + errno = 0; + + printf ("pass\n"); + exit (0); +}
c/kill1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/mmap5.c =================================================================== --- c/mmap5.c (nonexistent) +++ c/mmap5.c (revision 816) @@ -0,0 +1,91 @@ +/* +#notarget: cris*-*-elf +*/ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + int fd = open (argv[0], O_RDONLY); + struct stat sb; + int size; + void *a; + void *b; + const char *str = "a string you'll only find in the program"; + + if (fd == -1) + { + perror ("open"); + abort (); + } + + if (fstat (fd, &sb) < 0) + { + perror ("fstat"); + abort (); + } + + size = 8192; +#ifdef MMAP_SIZE1 + size = MMAP_SIZE1; +#endif + +#ifndef MMAP_PROT1 +#define MMAP_PROT1 PROT_READ | PROT_WRITE | PROT_EXEC +#endif + +#ifndef MMAP_FLAGS1 +#define MMAP_FLAGS1 MAP_PRIVATE | MAP_ANONYMOUS +#endif + + /* Get a page, any page. */ + b = mmap (NULL, size, MMAP_PROT1, MMAP_FLAGS1, -1, 0); + if (b == MAP_FAILED) + abort (); + + /* Remember it, unmap it. */ +#ifndef NO_MUNMAP + if (munmap (b, size) != 0) + abort (); +#endif + +#ifdef MMAP_ADDR2 + b = MMAP_ADDR2; +#endif + +#ifndef MMAP_PROT2 +#define MMAP_PROT2 PROT_READ | PROT_EXEC +#endif + +#ifndef MMAP_FLAGS2 +#define MMAP_FLAGS2 MAP_DENYWRITE | MAP_FIXED | MAP_PRIVATE +#endif + + size = sb.st_size; +#ifdef MMAP_SIZE2 + size = MMAP_SIZE2; +#endif + +#define MMAP_TEST_BAD_ORIG \ + (a == MAP_FAILED || memmem (a, size, str, strlen (str) + 1) == NULL) +#ifndef MMAP_TEST_BAD +#define MMAP_TEST_BAD MMAP_TEST_BAD_ORIG +#endif + + /* Try mapping the now non-mapped page fixed. */ + a = mmap (b, size, MMAP_PROT2, MMAP_FLAGS2, fd, 0); + + if (MMAP_TEST_BAD) + abort (); + + printf ("pass\n"); + exit (0); +}
c/mmap5.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/freopen1.c =================================================================== --- c/freopen1.c (nonexistent) +++ c/freopen1.c (revision 816) @@ -0,0 +1,49 @@ +/* Check that basic freopen functionality works. */ + +#include +#include +#include + +int +main (void) +{ + FILE *old_stderr; + FILE *f; + const char fname[] = "sk1test.dat"; + const char tsttxt[] + = "A random line of text, used to test correct freopen etc.\n"; + char buf[sizeof tsttxt] = ""; + + /* Like the freopen call in flex. */ + old_stderr = freopen (fname, "w+", stderr); + if (old_stderr == NULL + || fwrite (tsttxt, 1, strlen (tsttxt), stderr) != strlen (tsttxt) + || fclose (stderr) != 0) + { + printf ("fail\n"); + exit (1); + } + + /* Using "rb" to make this test similar to the use in genconf.c in + GhostScript. */ + f = fopen (fname, "rb"); + if (f == NULL + || fseek (f, 0L, SEEK_END) != 0 + || ftell (f) != strlen (tsttxt)) + { + printf ("fail\n"); + exit (1); + } + + rewind (f); + if (fread (buf, 1, strlen (tsttxt), f) != strlen (tsttxt) + || strcmp (buf, tsttxt) != 0 + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +}
c/freopen1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/access1.c =================================================================== --- c/access1.c (nonexistent) +++ c/access1.c (revision 816) @@ -0,0 +1,16 @@ +/* Check access(2) trivially. Newlib doesn't have it. +#notarget: cris*-*-elf +*/ +#include +#include +#include +#include +int main (int argc, char **argv) +{ + if (access (argv[0], R_OK|W_OK|X_OK) == 0 + && access ("/dev/null", R_OK|W_OK) == 0 + && access ("/dev/null", X_OK) == -1 + && errno == EACCES) + printf ("pass\n"); + exit (0); +}
c/access1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/gettod.c =================================================================== --- c/gettod.c (nonexistent) +++ c/gettod.c (revision 816) @@ -0,0 +1,27 @@ +/* Basic time functionality test. */ +#include +#include +#include +#include +int +main (void) +{ + struct timeval t_m = {0, 0}; + time_t t; + + if ((t = time (NULL)) == (time_t) -1 + || gettimeofday (&t_m, NULL) != 0 + || t_m.tv_sec == 0 + + /* We assume there will be no delay between the time and + gettimeofday calls above, but allow a timer-tick to make the + seconds increase by one. */ + || (t != t_m.tv_sec && t+1 != t_m.tv_sec)) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +}
c/gettod.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/append1.c =================================================================== --- c/append1.c (nonexistent) +++ c/append1.c (revision 816) @@ -0,0 +1,51 @@ +/* Check regression of a bug uncovered by the libio tFile test (old + libstdc++, pre-gcc-3.x era), where appending to a file doesn't work. + The default open-flags-mapping does not match Linux/CRIS, so a + specific mapping is necessary. */ + +#include +#include +#include + +int +main (void) +{ + FILE *f; + const char fname[] = "sk1test.dat"; + const char tsttxt1[] + = "This is the first and only line of this file.\n"; + const char tsttxt2[] = "Now there is a second line.\n"; + char buf[sizeof (tsttxt1) + sizeof (tsttxt2) - 1] = ""; + + f = fopen (fname, "w+"); + if (f == NULL + || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1) + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + f = fopen (fname, "a+"); + if (f == NULL + || fwrite (tsttxt2, 1, strlen (tsttxt2), f) != strlen (tsttxt2) + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + f = fopen (fname, "r"); + if (f == NULL + || fread (buf, 1, sizeof (buf), f) != sizeof (buf) - 1 + || strncmp (buf, tsttxt1, strlen (tsttxt1)) != 0 + || strncmp (buf + strlen (tsttxt1), tsttxt2, strlen (tsttxt2)) != 0 + || fclose (f) != 0) + { + printf ("fail\n"); + exit (1); + } + + printf ("pass\n"); + exit (0); +}
c/append1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/fcntl2.c =================================================================== --- c/fcntl2.c (nonexistent) +++ c/fcntl2.c (revision 816) @@ -0,0 +1,8 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "fcntl1.c"
c/fcntl2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/c.exp =================================================================== --- c/c.exp (nonexistent) +++ c/c.exp (revision 816) @@ -0,0 +1,244 @@ +# Copyright (C) 2005, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# Miscellaneous CRIS simulator testcases testing syscall sequences. + +if ![istarget cris*-*-*] { + return +} + +set CFLAGS_FOR_TARGET "-O2" +if [istarget cris-*-*] { + set mach "crisv10" +} { + set mach "crisv32" +} + +# Using target_compile, since it is less noisy, +if { [target_compile $srcdir/$subdir/hello.c compilercheck.x \ + "executable" "" ] == "" } { + set has_cc 1 + + # Now check if we can link a program dynamically, and where + # libc.so is located. If it is, we provide a sym link to the + # directory (which must end in /lib) in [pwd], so /lib/ld.so.1 is + # found (which must reside along libc.so). We don't bother + # replacing the board ldflags like below as we don't care about + # detrimental effects on the executable from the specs and + # -static in the board ldflags, we just add -Bdynamic. + if [regexp "(.*/lib)/libc.so" \ + [target_compile $srcdir/$subdir/hello.c compilercheck.x \ + "executable" \ + "ldflags=-print-file-name=libc.so -Wl,-Bdynamic"] \ + xxx libcsodir] { + file delete lib + verbose -log "Creating link to $libcsodir in [pwd]" + file link lib $libcsodir + } +} { + verbose -log "Can't execute C compiler" + set has_cc 0 +} + +# Like istarget, except take a list of targets as a string. +proc anytarget { targets } { + set targetlist [split $targets] + set argc [llength $targetlist] + for { set i 0 } { $i < $argc } { incr i } { + if [istarget [lindex $targetlist $i]] { + return 1 + } + } + return 0 +} + +foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.c]] { + set orig_ldflags "" + + if ![runtest_file_p $runtests $src] { + continue + } + set testname "[file tail $src]" + + set opt_array [slurp_options $src] + if { $opt_array == -1 } { + unresolved $testname + return + } + + # And again, to simplify specifying tests. + if ![runtest_file_p $runtests $src] { + continue + } + + # Note absence of CC in results, but don't make a big fuss over it. + if { $has_cc == 0 } { + untested $testname + continue + } + + # Clear default options + set opts(cc) "" + set opts(sim) "" + set opts(output) "" + set opts(progoptions) "" + set opts(timeout) "" + set opts(mach) "" + set opts(xerror) "no" + set opts(dest) "$testname.x" + set opts(simenv) "" + set opts(kfail) "" + set opts(xfail) "" + set opts(target) "" + set opts(notarget) "" + set opts(dynamic) "" + + # Clear any machine specific options specified in a previous test case + if [info exists opts(sim,$mach)] { + unset opts(sim,$mach) + } + + foreach i $opt_array { + set opt_name [lindex $i 0] + set opt_machs [lindex $i 1] + set opt_val [lindex $i 2] + if ![info exists opts($opt_name)] { + perror "unknown option $opt_name in file $src" + unresolved $testname + return + } + + # Replace specific substitutions: + # @exedir@ is where the test-program is located. + regsub -all "@exedir@" $opt_val "[pwd]" opt_val + # @srcdir@ is where the source of the test-program is located. + regsub -all "@srcdir@" $opt_val "$srcdir/$subdir" opt_val + + # Multiple of these options concatenate, they don't override. + if { $opt_name == "output" || $opt_name == "progoptions" } { + set opt_val "$opts($opt_name)$opt_val" + } + + # Similar with "xfail", "kfail", "target" and "notarget", but + # arguments are space-separated. + if { $opt_name == "xfail" || $opt_name == "kfail" \ + || $opt_name == "target" || $opt_name == "notarget" } { + if { $opts($opt_name) != "" } { + set opt_val "$opts($opt_name) $opt_val" + } + } + + if { $opt_name == "dynamic" \ + && [info exists board_info([target_info name],ldflags)] } { + # Weed out -static from ldflags, but keep the original in + # $orig_ldflags. + set orig_ldflags $board_info([target_info name],ldflags) + set ldflags " $orig_ldflags " + regsub -all " -static " $ldflags " " ldflags + set board_info([target_info name],ldflags) $ldflags + } + + foreach m $opt_machs { + set opts($opt_name,$m) $opt_val + } + if { "$opt_machs" == "" } { + set opts($opt_name) $opt_val + } + } + + if { $opts(output) == "" } { + if { "$opts(xerror)" == "no" } { + set opts(output) "pass\n" + } else { + set opts(output) "fail\n" + } + } + + if { $opts(target) != "" && ![anytarget $opts(target)] } { + continue + } + + if { $opts(notarget) != "" && [anytarget $opts(notarget)] } { + continue + } + + # If no machine specific options, default to the general version. + if ![info exists opts(sim,$mach)] { + set opts(sim,$mach) $opts(sim) + } + + # Change \n sequences to newline chars. + regsub -all "\\\\n" $opts(output) "\n" opts(output) + + verbose -log "Compiling $src with $opts(cc)" + + set dest "$opts(dest)" + if { [sim_compile $src $dest "executable" "$opts(cc)" ] != "" } { + unresolved $testname + continue + } + + if { $orig_ldflags != "" } { + set board_info([target_info name],ldflags) $orig_ldflags + } + + verbose -log "Simulating $src with $opts(sim,$mach)" + + # Time to setup xfailures and kfailures. + if { "$opts(xfail)" != "" } { + verbose -log "xfail: $opts(xfail)" + # Using eval to make $opts(xfail) appear as individual + # arguments. + eval setup_xfail $opts(xfail) + } + if { "$opts(kfail)" != "" } { + verbose -log "kfail: $opts(kfail)" + eval setup_kfail $opts(kfail) + } + + set result [sim_run $dest "$opts(sim,$mach)" "$opts(progoptions)" \ + "" "$opts(simenv)"] + set status [lindex $result 0] + set output [lindex $result 1] + + if { "$status" == "pass" } { + if { "$opts(xerror)" == "no" } { + if [string match $opts(output) $output] { + pass "$mach $testname" + } else { + verbose -log "output: $output" 3 + verbose -log "pattern: $opts(output)" 3 + fail "$mach $testname (execution)" + } + } else { + verbose -log "`pass' return code when expecting failure" 3 + fail "$mach $testname (execution)" + } + } elseif { "$status" == "fail" } { + if { "$opts(xerror)" == "no" } { + fail "$mach $testname (execution)" + } else { + if [string match $opts(output) $output] { + pass "$mach $testname" + } else { + verbose -log "output: $output" 3 + verbose -log "pattern: $opts(output)" 3 + fail "$mach $testname (execution)" + } + } + } else { + $status "$mach $testname" + } +} Index: c/thread5.c =================================================================== --- c/thread5.c (nonexistent) +++ c/thread5.c (revision 816) @@ -0,0 +1,77 @@ +/* Compiler options: +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#output: abbb ok\n + + Testing a signal handler corner case. */ + +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + write (2, "a", 1); + write (2, "b", 1); + write (2, "b", 1); + write (2, "b", 1); + return NULL; +} + +int ok = 0; +volatile int done = 0; + +void +sigusr1 (int signum) +{ + if (signum != SIGUSR1 || !ok) + abort (); + done = 1; +} + +int +main (void) +{ + int retcode; + pthread_t th_a; + void *retval; + sigset_t sigs; + + if (sigemptyset (&sigs) != 0) + abort (); + + retcode = pthread_create (&th_a, NULL, process, NULL); + if (retcode != 0) + abort (); + + if (signal (SIGUSR1, sigusr1) != SIG_DFL) + abort (); + if (pthread_sigmask (SIG_BLOCK, NULL, &sigs) != 0 + || sigaddset (&sigs, SIGUSR1) != 0 + || pthread_sigmask (SIG_BLOCK, &sigs, NULL) != 0) + abort (); + if (pthread_kill (pthread_self (), SIGUSR1) != 0 + || sched_yield () != 0 + || sched_yield () != 0 + || sched_yield () != 0) + abort (); + + ok = 1; + if (pthread_sigmask (SIG_UNBLOCK, NULL, &sigs) != 0 + || sigaddset (&sigs, SIGUSR1) != 0 + || pthread_sigmask (SIG_UNBLOCK, &sigs, NULL) != 0) + abort (); + + if (!done) + abort (); + + retcode = pthread_join (th_a, &retval); + if (retcode != 0) + abort (); + fprintf (stderr, " ok\n"); + return 0; +}
c/thread5.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/setrlimit1.c =================================================================== --- c/setrlimit1.c (nonexistent) +++ c/setrlimit1.c (revision 816) @@ -0,0 +1,22 @@ +/* Check corner error case: specifying unimplemented resource. +#notarget: cris*-*-elf +*/ +#include +#include +#include +#include +#include +#include +#include + +int main (void) +{ + struct rlimit lim; + memset (&lim, 0, sizeof lim); + + if (setrlimit (RLIMIT_NPROC, &lim) != -1 + || errno != EINVAL) + abort (); + printf ("pass\n"); + exit (0); +}
c/setrlimit1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/syscall4.c =================================================================== --- c/syscall4.c (nonexistent) +++ c/syscall4.c (revision 816) @@ -0,0 +1,9 @@ +/* As the included file, just actually specifying the default. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=stop +#xerror: +#output: Unimplemented syscall: 0 (0x3, 0x2, 0x1, 0x4, 0x6, 0x5)\n +#output: program stopped with signal 4.\n +*/ + +#include "syscall2.c"
c/syscall4.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sjlj.c =================================================================== --- c/sjlj.c (nonexistent) +++ c/sjlj.c (revision 816) @@ -0,0 +1,34 @@ +/* Check that setjmp and longjmp stand a chance to work; that the used machine + primitives work in the simulator. */ + +#include +#include +#include + +extern void f (void); + +int ok = 0; +jmp_buf b; + +int +main () +{ + int ret = setjmp (b); + + if (ret == 42) + ok = 100; + else if (ret == 0) + f (); + + if (ok == 100) + printf ("pass\n"); + else + printf ("fail\n"); + exit (0); +} + +void +f (void) +{ + longjmp (b, 42); +}
c/sjlj.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/syscall8.c =================================================================== --- c/syscall8.c (nonexistent) +++ c/syscall8.c (revision 816) @@ -0,0 +1,8 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "syscall2.c"
c/syscall8.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sysctl1.c =================================================================== --- c/sysctl1.c (nonexistent) +++ c/sysctl1.c (revision 816) @@ -0,0 +1,38 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include + +/* I can't seem to include the right things, so we do it brute force. */ +int main (void) +{ + static int sysctl_args[] = { 1, 4 }; + size_t x = 8; + + struct __sysctl_args { + int *name; + int nlen; + void *oldval; + size_t *oldlenp; + void *newval; + size_t newlen; + unsigned long __unused[4]; + } scargs + = + { + sysctl_args, + sizeof (sysctl_args) / sizeof (sysctl_args[0]), + (void *) -1, &x, NULL, 0 + }; + + if (syscall (SYS__sysctl, &scargs) != -1 + || errno != EFAULT) + abort (); + printf ("pass\n"); + exit (0); +}
c/sysctl1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sigreturn2.c =================================================================== --- c/sigreturn2.c (nonexistent) +++ c/sigreturn2.c (revision 816) @@ -0,0 +1,38 @@ +/* Check that TRT happens for spurious sigreturn calls. Multiple threads. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#xerror: +#output: Invalid sigreturn syscall: no signal handler active (0x1, 0x2, 0x3, 0x4, 0x5, 0x6)\n +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + while (1) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) + { + int err = syscall (SYS_sigreturn, 1, 2, 3, 4, 5, 6); + if (err == -1 && errno == ENOSYS) + printf ("ENOSYS\n"); + } + printf ("xyzzy\n"); + exit (0); +}
c/sigreturn2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sched2.c =================================================================== --- c/sched2.c (nonexistent) +++ c/sched2.c (revision 816) @@ -0,0 +1,19 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (void) +{ + struct sched_param sb; + memset (&sb, -1, sizeof sb); + if (sched_getparam (getpid (), &sb) != 0 + || sb.sched_priority != 0) + abort (); + printf ("pass\n"); + exit (0); +}
c/sched2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/rtsigprocmask1.c =================================================================== --- c/rtsigprocmask1.c (nonexistent) +++ c/rtsigprocmask1.c (revision 816) @@ -0,0 +1,51 @@ +/* Compiler options: +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#xerror: +#output: Unimplemented rt_sigprocmask syscall (0x3, 0x0, 0x3dff*\n +#output: program stopped with signal 4.\n + + Testing a signal handler corner case. */ + +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + while (1) + sched_yield (); + return NULL; +} + +int +main (void) +{ + int retcode; + pthread_t th_a; + void *retval; + sigset_t sigs; + + if (sigemptyset (&sigs) != 0) + abort (); + + retcode = pthread_create (&th_a, NULL, process, NULL); + if (retcode != 0) + abort (); + + /* An invalid parameter 1 should cause this to halt the simulator. */ + retcode + = pthread_sigmask (SIG_BLOCK + SIG_UNBLOCK + SIG_SETMASK, NULL, &sigs); + /* Direct return of the error number; i.e. not using -1 and errno, + is the actual documented behavior. */ + if (retcode == ENOSYS) + printf ("ENOSYS\n"); + + printf ("xyzzy\n"); + return 0; +}
c/rtsigprocmask1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/readlink3.c =================================================================== --- c/readlink3.c (nonexistent) +++ c/readlink3.c (revision 816) @@ -0,0 +1,6 @@ +/* Simulator options: +#notarget: cris*-*-elf +#sim: --sysroot=@exedir@ +*/ +#define SYSROOTED 1 +#include "readlink2.c"
c/readlink3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sched6.c =================================================================== --- c/sched6.c (nonexistent) +++ c/sched6.c (revision 816) @@ -0,0 +1,15 @@ +/* +#notarget: cris*-*-elf +*/ + +#include +#include +#include + +int main (void) +{ + if (sched_yield () != 0) + abort (); + printf ("pass\n"); + exit (0); +}
c/sched6.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/pipe1.c =================================================================== --- c/pipe1.c (nonexistent) +++ c/pipe1.c (revision 816) @@ -0,0 +1,47 @@ +/* Check for proper pipe semantics at corner cases. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int main (void) +{ + int i; + int filemax; + +#ifdef OPEN_MAX + filemax = OPEN_MAX; +#else + filemax = sysconf (_SC_OPEN_MAX); +#endif + + if (filemax < 10) + abort (); + + /* Check that pipes don't leak file descriptors. */ + for (i = 0; i < filemax * 10; i++) + { + int pip[2]; + if (pipe (pip) != 0) + { + perror ("pipe"); + abort (); + } + + if (close (pip[0]) != 0 || close (pip[1]) != 0) + { + perror ("close"); + abort (); + } + } + printf ("pass\n"); + exit (0); +}
c/pipe1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/mprotect2.c =================================================================== --- c/mprotect2.c (nonexistent) +++ c/mprotect2.c (revision 816) @@ -0,0 +1,8 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "mprotect1.c"
c/mprotect2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/readlink7.c =================================================================== --- c/readlink7.c (nonexistent) +++ c/readlink7.c (revision 816) @@ -0,0 +1,6 @@ +/* Check that rare readlink calls don't cause the simulator to abort. +#notarget: cris*-*-elf +#simenv: env(-u\ PWD\ foo)=bar + FIXME: Need to unset PWD, but right now I won't bother tweaking the + generic parts of the testsuite machinery and instead abuse a flaw. */ +#include "readlink2.c"
c/readlink7.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/clone2.c =================================================================== --- c/clone2.c (nonexistent) +++ c/clone2.c (revision 816) @@ -0,0 +1,6 @@ +/* Make sure the thread system trivially works with trace output. +#notarget: cris*-*-elf +#sim: --cris-trace=basic --trace-file=@exedir@/clone2.tmp +#output: got: a\nthen: bc\nexit: 0\n +*/ +#include "clone1.c"
c/clone2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/pipe5.c =================================================================== --- c/pipe5.c (nonexistent) +++ c/pipe5.c (revision 816) @@ -0,0 +1,59 @@ +/* Check that TRT happens for pipe corner cases (for our definition of TRT). +#notarget: cris*-*-elf +#xerror: +#output: Terminating simulation due to writing pipe * from one single thread\n +#output: program stopped with signal 4.\n +*/ +#include +#include +#include +#include +#include +#include +#include + +void err (const char *s) +{ + perror (s); + abort (); +} + +int main (void) +{ + int pip[2]; + int pipemax; + char *buf; + + if (pipe (pip) != 0) + err ("pipe"); + +#ifdef PIPE_MAX + pipemax = PIPE_MAX; +#else + pipemax = fpathconf (pip[1], _PC_PIPE_BUF); +#endif + + if (pipemax <= 0) + { + fprintf (stderr, "Bad pipemax %d\n", pipemax); + abort (); + } + + /* Writing an inordinate amount to the pipe. */ + buf = calloc (100 * pipemax, 1); + if (buf == NULL) + err ("calloc"); + + /* The following doesn't trig on host; writing more than PIPE_MAX to a + pipe with no reader makes the program hang. Neither does it trig + on target: we don't want to emulate the "hanging" (which would + happen with *any* amount written to a pipe with no reader if we'd + support it - but we don't). Better to abort the simulation with a + suitable message. */ + if (write (pip[1], buf, 100 * pipemax) != -1 + || errno != EFBIG) + err ("write mucho"); + + printf ("pass\n"); + exit (0); +}
c/pipe5.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/sig11.c =================================================================== --- c/sig11.c (nonexistent) +++ c/sig11.c (revision 816) @@ -0,0 +1,32 @@ +/* Check that TRT happens when getting a non-standard (realtime) signal, more than one thread. +#notarget: cris*-*-elf +#cc: additional_flags=-pthread +#xerror: +#output: Unimplemented signal: 77\n +#output: program stopped with signal 4.\n +*/ + +#include +#include +#include +#include +#include +#include +#include + +static void * +process (void *arg) +{ + while (1) + sched_yield (); + return NULL; +} + +int main (void) +{ + pthread_t th_a; + if (pthread_create (&th_a, NULL, process, (void *) "a") == 0) + kill (getpid (), 77); + printf ("xyzzy\n"); + exit (0); +}
c/sig11.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/clone6.c =================================================================== --- c/clone6.c (nonexistent) +++ c/clone6.c (revision 816) @@ -0,0 +1,8 @@ +/* As the included file, but specifying silent ENOSYS. +#notarget: cris*-*-elf +#sim: --cris-unknown-syscall=enosys-quiet +#output: ENOSYS\n +#output: xyzzy\n +*/ + +#include "clone5.c"
c/clone6.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/badldso1.c =================================================================== --- c/badldso1.c (nonexistent) +++ c/badldso1.c (revision 816) @@ -0,0 +1,7 @@ +/* +#notarget: cris*-*-elf +#dynamic: +#xerror: +#output: *: could not load ELF interpreter `*' for program `*'\n + */ +#include "hello.c"
c/badldso1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/readlink10.c =================================================================== --- c/readlink10.c (nonexistent) +++ c/readlink10.c (revision 816) @@ -0,0 +1,18 @@ +/* Check that odd cases of readlink work. +#notarget: cris*-*-elf +*/ + +#include +#include +#include +#include + +int main (int argc, char *argv[]) +{ + if (readlink("/proc/42/exe", NULL, 4096) != -1 + || errno != EFAULT) + abort (); + + printf ("pass\n"); + exit (0); +}
c/readlink10.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: c/fdopen2.c =================================================================== --- c/fdopen2.c (nonexistent) +++ c/fdopen2.c (revision 816) @@ -0,0 +1,52 @@ +/* Check that the syscalls implementing fdopen work trivially. +#output: This is the first line of this test.\npass\n +*/ + +#include +#include +#include +#include +#include + +void +perr (const char *s) +{ + perror (s); + exit (1); +} + +int +main (void) +{ + FILE *f; + int fd; + const char fname[] = "sk1test.dat"; + const char tsttxt1[] + = "This is the first line of this test.\n"; + char buf[sizeof (tsttxt1)] = ""; + + /* Write a line to stdout. */ + f = fdopen (1, "w"); + if (f == NULL + || fwrite (tsttxt1, 1, strlen (tsttxt1), f) != strlen (tsttxt1)) + perr ("fdopen or fwrite"); + +#if 0 + /* Unfortunately we can't get < /dev/null to the simulator with + reasonable test-framework surgery. */ + + /* Try to read from stdin. Expect EOF. */ + f = fdopen (0, "r"); + if (f == NULL + || fread (buf, 1, sizeof (buf), f) != 0 + || feof (f) == 0 + || ferror (f) != 0) + { + printf ("fail\n"); + exit (1); + } +#endif + + printf ("pass\n"); + exit (0); +}
c/fdopen2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: hw/rv-n-cris/quit.s =================================================================== --- hw/rv-n-cris/quit.s (nonexistent) +++ hw/rv-n-cris/quit.s (revision 816) @@ -0,0 +1,4 @@ +; Trivial target simulator program that just exits. + .include "testutils.inc" + startnostack + quit
hw/rv-n-cris/quit.s Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: hw/rv-n-cris/rvc.exp =================================================================== --- hw/rv-n-cris/rvc.exp (nonexistent) +++ hw/rv-n-cris/rvc.exp (revision 816) @@ -0,0 +1,240 @@ +# Copyright (C) 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# Miscellaneous CRIS simulator testcases in assembly code, testing +# dv-rv.c and dv-cris.c functions. + +# Check whether dv-rv and dv-cris are present. + +proc sim_has_rv_and_cris {} { + global srcdir + global subdir + global SIMFLAGS + global global_as_options + global global_ld_options + global global_sim_options + + # We need to assemble and link a trivial program and pass that, in + # order to test successful exit. + + # A bit of duplication here for the assembling and linking part; + # what we want to do it to run the simulator without affecting the + # PASS/FAIL counters, and we can use e.g. run_sim_test for that. + + if ![info exists global_as_options] { + set global_as_options "" + } + if ![info exists global_ld_options] { + set global_ld_options "" + } + if ![info exists global_sim_options] { + set global_sim_options "" + } + + set comp_output [target_assemble $srcdir/$subdir/quit.s quit.o \ + "-I$srcdir/$subdir $global_as_options"] + + if ![string match "" $comp_output] { + verbose -log "$comp_output" 3 + fail "rv sim test setup (assembling)" + return 0 + } + + set comp_output [target_link quit.o quit.x "$global_ld_options"] + + if ![string match "" $comp_output] { + verbose -log "$comp_output" 3 + fail "rv sim test setup (linking)" + return 0 + } + + set result \ + [sim_run quit.x \ + "$global_sim_options --hw-device rv --hw-device cris --hw-info" \ + "" "" ""] + set return_code [lindex $result 0] + set output [lindex $result 1] + + if { "$return_code" == "pass" } { + return 1 + } + + return 0 +} + +# Similar to slurp_options, but lines are fixed format "^#r ..." (not +# "^#{ws}*r:{ws}+" to avoid intruding on slurp_options syntax). Only +# trailing whitespace of the "..." is trimmed. Beware that lines +# including parameters may not contain ":". + +proc slurp_rv { file } { + if [catch { set f [open $file r] } x] { + #perror "couldn't open `$file': $x" + perror "$x" + return -1 + } + set rv_array {} + # whitespace expression + set ws {[ ]*} + # whitespace is ignored at the end of a line. + set pat "^#r (.*)$ws\$" + # Allow arbitrary lines until the first option is seen. + set seen_opt 0 + while { [gets $f line] != -1 } { + set line [string trim $line] + # Whitespace here is space-tab. + if [regexp $pat $line xxx cmd] { + # match! + lappend rv_array $cmd + set seen_opt 1 + } else { + if { $seen_opt } { + break + } + } + } + close $f + return $rv_array +} + +# The main test loop. + +if [istarget cris*-*-*] { + global ASFLAGS_FOR_TARGET + set has_rv_and_cris [sim_has_rv_and_cris] + global global_as_options + global global_ld_options + global global_sim_options + + set saved_global_sim_options $global_sim_options + set saved_global_ld_options $global_ld_options + set rvdummy "[file dirname [board_info target sim]]/rvdummy" + + # All machines we test and the corresponding assembler option. + # We'll only ever test v10 and higher here. + + set combos {{"crisv10" "--march=v10 --no-mul-bug-abort"} + {"crisv32" "--march=v32"}} + + # We need to pass different assembler flags for each machine. + # Specifying it here rather than adding a specifier to each and every + # test-file is preferrable. + + foreach combo $combos { + set mach [lindex $combo 0] + set ASFLAGS_FOR_TARGET "[lindex $combo 1]" + + # The .ms suffix is for "miscellaneous .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { + + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + # Whoever runs the test should be alerted that not all + # testcases have been checked; that's why we do the loop + # and don't just return at the top. + if !$has_rv_and_cris { + untested $src + continue + } + + set sim_defaults "--hw-file $srcdir/$subdir/std.dev" + set ld_defaults "--section-start=.text=0" + + # We parse options an extra time besides in run_sim_test, + # to determine if our defaults should be overridden. + + set opt_array [slurp_options $src] + foreach i $opt_array { + set opt_name [lindex $i 0] + set opt_machs [lindex $i 1] + set opt_val [lindex $i 2] + + # Allow concatenating to the default options by + # specifying a mach. + if { $opt_name == "sim" && $opt_machs == "" } { + set sim_defaults "" + } + + if { $opt_name == "ld" && $opt_machs == "" } { + set ld_defaults "" + } + } + + set rvdummy_id -1 + set hostcmds [slurp_rv $src] + + if { $hostcmds != "" } { + # I guess we could ask to have rvdummy executed on a + # remote host, but it looks like too much trouble for + # a feature rarely used. + if [is_remote host] { + untested $src + continue + } + + set src_components [file split $src] + set rvfile "[lindex $src_components \ + [expr [llength $src_components] - 1]].r" + + if [catch { set f [open $rvfile w] } x] { + error "$x" + } { + set contents [join $hostcmds "\n"] + + # Make it possible to use files from the test + # source directory; expected with the @-command. + regsub -all "@srcdir@" $contents "$srcdir/$subdir" contents + + verbose "rv: $contents" 2 + puts $f $contents + close $f + } + + spawn -noecho $rvdummy "$rvfile" + if { $spawn_id < 0 } { + error "Couldn't spawn $rvdummy" + continue + } + set rvdummy_id $spawn_id + } + + # Unfortunately this seems like the only way to pass + # additional sim, ld etc. options to run_sim_test. + set global_sim_options "$saved_global_sim_options $sim_defaults" + set global_ld_options "$saved_global_ld_options $ld_defaults" + run_sim_test $src $mach + set global_sim_options $saved_global_sim_options + set global_ld_options $saved_global_ld_options + + # Stop the rvdummy, if it's still running. We need to + # wait on it anyway to avoid it turning into a zombie. + if { $rvdummy_id != -1 } { + close -i $rvdummy_id + wait -i $rvdummy_id + + # Gleaned from framework.exp, this seems an indicator + # to whether the test had expected outcome. If so, we + # want to remove the rv-file. + if { $exit_status == 0 } { + file delete $rvfile + } + } + } + } +} Index: hw/rv-n-cris/irq1.ms =================================================================== --- hw/rv-n-cris/irq1.ms (nonexistent) +++ hw/rv-n-cris/irq1.ms (revision 816) @@ -0,0 +1,69 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" +#sim(crisv32): --hw-device "/rv/trace? true" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000032\n +#output: /rv: := 0xabcdef01\n +#output: /rv: IRQ 0x4\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543211\n +#output: /rv: REG R 0xd0000030\n +#output: /rv: IRQ 0x0\n +#output: /rv: := 0xeeff4455\n +#output: pass\n + +# Trivial test of interrupts. +# Locations of IRQ notifiers above depend on when the simulator is +# polled; adjustments may be needed (after checking that no poll is +# gone due to a bug!) + +#r W, +#r r,a8832,abcdef01 +#r I,4 +#r r,a8836,76543210 +#r r,a8836,76543211 +#r I,0 +#r r,a8830,eeff4455 + + .lcomm dummy,4 + + .include "testutils.inc" + start + .if ..asm.arch.cris.v32 + move irqvec1,$ebp + .else + move irqvec1,$ibr + .endif + test_h_mem 0xabcdef01 0xd0000032 + nop + nop + test_h_mem 0x76543210 0xd0000036 + ei + test_h_mem 0,dummy +wouldreturnhere: + nop +killme: + fail + +returnhere: + test_h_mem 0x76543211 0xd0000036 + test_h_mem 0xeeff4455 0xd0000030 + pass + +irq0x33: + .if ..asm.arch.cris.v32 + test_h_dr wouldreturnhere,$erp + move returnhere,$erp + rete + rfe + .else + move $dccr,$r0 + test_h_dr wouldreturnhere,$irp + move returnhere,$irp + reti + move $r0,$dccr + .endif + + singlevec irqvec1,0x33,irq0x33 Index: hw/rv-n-cris/irq2.ms =================================================================== --- hw/rv-n-cris/irq2.ms (nonexistent) +++ hw/rv-n-cris/irq2.ms (revision 816) @@ -0,0 +1,44 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" --hw-device "/rv/intmultiple 0xaa" +#sim(crisv32): --hw-device "/rv/trace? true" --hw-device "/rv/intmultiple 0xaa" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000032\n +#output: /rv: := 0xabcdef01\n +#output: /rv: IRQ 0xaa\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: /rv: REG R 0xd0000030\n +#output: /rv: IRQ 0x0\n +#output: /rv: := 0xeeff4455\n +#output: pass\n + +# Primarily to test multiple-int-bits set in dv-rv.c. + +#r W, +#r r,a8832,abcdef01 +#r I,6 +#r r,a8836,76543210 +#r I,0 +#r r,a8830,eeff4455 + + .lcomm dummy,4 + + .include "testutils.inc" + start + test_h_mem 0xabcdef01 0xd0000032 + .if ..asm.arch.cris.v32 + move irqvec1,$ebp + .else + move irqvec1,$ibr + .endif + ei + test_h_mem 0,dummy +killme: + fail + +irq0xea: + test_h_mem 0x76543210 0xd0000036 + test_h_mem 0xeeff4455 0xd0000030 + pass + + singlevec irqvec1,0xea,irq0xea Index: hw/rv-n-cris/irq3.ms =================================================================== --- hw/rv-n-cris/irq3.ms (nonexistent) +++ hw/rv-n-cris/irq3.ms (revision 816) @@ -0,0 +1,46 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" --hw-device "/rv/intmultiple 0xaa" +#sim(crisv32): --hw-device "/rv/trace? true" --hw-device "/rv/intmultiple 0xaa" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000032\n +#output: /rv: := 0xabcdef01\n +#output: /rv: IRQ 0xaa\n +#output: /rv: IRQ 0xaa\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: /rv: REG R 0xd0000030\n +#output: /rv: IRQ 0x0\n +#output: /rv: := 0xeeff4455\n +#output: pass\n + +# Much like irq2.ms, but modified to check same-int-port-value-twice. + +#r W, +#r r,a8832,abcdef01 +#r I,6 +#r I,6 +#r r,a8836,76543210 +#r I,0 +#r r,a8830,eeff4455 + + .lcomm dummy,4 + + .include "testutils.inc" + start + test_h_mem 0xabcdef01 0xd0000032 + .if ..asm.arch.cris.v32 + move irqvec1,$ebp + .else + move irqvec1,$ibr + .endif + ei + test_h_mem 0,dummy +killme: + fail + +irq0xea: + test_h_mem 0x76543210 0xd0000036 + test_h_mem 0xeeff4455 0xd0000030 + pass + + singlevec irqvec1,0xea,irq0xea Index: hw/rv-n-cris/irq4.ms =================================================================== --- hw/rv-n-cris/irq4.ms (nonexistent) +++ hw/rv-n-cris/irq4.ms (revision 816) @@ -0,0 +1,46 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" --hw-device "/cris/multiple-int ignore_previous" +#sim(crisv32): --hw-device "/rv/trace? true" --hw-device "/cris/multiple-int ignore_previous" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000032\n +#output: /rv: := 0xabcdef01\n +#output: /rv: IRQ 0x4\n +#output: /rv: IRQ 0x8\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: /rv: REG R 0xd0000030\n +#output: /rv: IRQ 0x0\n +#output: /rv: := 0xeeff4455\n +#output: pass\n + +# Much like irq3.ms, but modified to test multiple-int ignore_previous. + +#r W, +#r r,a8832,abcdef01 +#r I,4 +#r I,8 +#r r,a8836,76543210 +#r I,0 +#r r,a8830,eeff4455 + + .lcomm dummy,4 + + .include "testutils.inc" + start + test_h_mem 0xabcdef01 0xd0000032 + .if ..asm.arch.cris.v32 + move irqvec1,$ebp + .else + move irqvec1,$ibr + .endif + ei + test_h_mem 0,dummy +killme: + fail + +irq0x34: + test_h_mem 0x76543210 0xd0000036 + test_h_mem 0xeeff4455 0xd0000030 + pass + + singlevec irqvec1,0x34,irq0x34 Index: hw/rv-n-cris/trivial4.r =================================================================== --- hw/rv-n-cris/trivial4.r (nonexistent) +++ hw/rv-n-cris/trivial4.r (revision 816) @@ -0,0 +1,4 @@ +W, +r,a8832,abcdef01 +w,a8836,aabbccdd +r,a8836,76543210 Index: hw/rv-n-cris/irq5.ms =================================================================== --- hw/rv-n-cris/irq5.ms (nonexistent) +++ hw/rv-n-cris/irq5.ms (revision 816) @@ -0,0 +1,46 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" --hw-device "/cris/multiple-int 0xae" +#sim(crisv32): --hw-device "/rv/trace? true" --hw-device "/cris/multiple-int 0xae" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000032\n +#output: /rv: := 0xabcdef01\n +#output: /rv: IRQ 0x4\n +#output: /rv: IRQ 0x8\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: /rv: REG R 0xd0000030\n +#output: /rv: IRQ 0x0\n +#output: /rv: := 0xeeff4455\n +#output: pass\n + +# Much like irq4.ms, but modified to test vector case for multiple-int. + +#r W, +#r r,a8832,abcdef01 +#r I,4 +#r I,8 +#r r,a8836,76543210 +#r I,0 +#r r,a8830,eeff4455 + + .lcomm dummy,4 + + .include "testutils.inc" + start + test_h_mem 0xabcdef01 0xd0000032 + .if ..asm.arch.cris.v32 + move irqvec1,$ebp + .else + move irqvec1,$ibr + .endif + ei + test_h_mem 0,dummy +killme: + fail + +irq0xae: + test_h_mem 0x76543210 0xd0000036 + test_h_mem 0xeeff4455 0xd0000030 + pass + + singlevec irqvec1,0xae,irq0xae Index: hw/rv-n-cris/irq6.ms =================================================================== --- hw/rv-n-cris/irq6.ms (nonexistent) +++ hw/rv-n-cris/irq6.ms (revision 816) @@ -0,0 +1,99 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" +#sim(crisv32): --hw-device "/rv/trace? true" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000032\n +#output: /rv: := 0xabcdef01\n +#output: /rv: IRQ 0x4\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: /rv: REG R 0xd0000030\n +#output: /rv: IRQ 0x0\n +#output: /rv: IRQ 0x8\n +#output: /rv: := 0xeeff4455\n +#output: /rv: REG R 0xd0000034\n +#output: /rv: := 0xdd001122\n +#output: /rv: REG R 0xd0000038\n +#output: /rv: := 0xaaeeff44\n +#output: /rv: REG R 0xd000003c\n +#output: /rv: := 0xff445511\n +#output: pass\n + +# Test two successive ints; that flags are disabled when an interrupt +# is taken, and then automatically (or by register restore) enabled at +# return. + +#r W, +#r r,a8832,abcdef01 +#r I,4 +#r r,a8836,76543210 +#r I,0 +#r I,8 +#r r,a8830,eeff4455 +#r r,a8834,dd001122 +#r r,a8838,aaeeff44 +#r r,a883c,ff445511 + + .lcomm dummy,4 + + .include "testutils.inc" + start + test_h_mem 0xabcdef01 0xd0000032 + moveq -1,$r4 + + .if ..asm.arch.cris.v32 + move irqvec1,$ebp + .else + move irqvec1,$ibr + .endif + + ei + test_h_mem 0,dummy + + ; Here after the first interrupt, or perhaps the second interrupt is + ; taken directly; leave it optional. Anyway, the second interrupt + ; should be taken no later than this branch. + test_h_mem 0,dummy + +killme: + fail + +irq0x33: + .if ..asm.arch.cris.v32 + ; Nothing needed to save flags - "shift" should happen, and back at rfe. + .else + ; The missing sim support for interrupt-excluding instructions is matched + ; by the flaw that sim doesn't service interrupts in straight code. + ; So, we can use a sequence that would work on actual hardware. + move $dccr,$r5 + di + .endif + + test_h_mem 0x76543210 0xd0000036 + test_h_mem 0xeeff4455 0xd0000030 + test_h_mem 0xdd001122 0xd0000034 + moveq -22,$r4 + + .if ..asm.arch.cris.v32 + move irqvec2,$ebp + rete + rfe + .else + move irqvec2,$ibr + reti + move $r5,$dccr + .endif + + pass + +irq0x34: + test_h_mem 0xaaeeff44 0xd0000038 + test_h_mem 0xff445511 0xd000003c + cmpq -22,$r4 + bne killme + nop + pass + + singlevec irqvec1,0x33,irq0x33 + + singlevec irqvec2,0x34,irq0x34 Index: hw/rv-n-cris/mbox1.ms =================================================================== --- hw/rv-n-cris/mbox1.ms (nonexistent) +++ hw/rv-n-cris/mbox1.ms (revision 816) @@ -0,0 +1,88 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" +#sim(crisv32): --hw-device "/rv/trace? true" +#output: /rv: WD\n +#output: /rv: MBOX H 0x1001d..0x10037\n +#output: /rv: 0x10020: 12 23 34 56 79 8a bd de\n +#output: /rv: 0x10028: fb ad ba db ad 56 78 9a\n +#output: /rv: 0x10030: fd e1 23 45 66 54 32 1a\n +#output: /rv: -> 0x1001d..0x10027\n +#output: /rv: 0x10020: aa 55 77 88 32 10 ee cc\n +#output: /rv: MBOX P 0xfffd..0x1001f\n +#output: /rv: 0x10000: aa 55 12 23 34 56 79 8a\n +#output: /rv: 0x10008: bd de fb ad ba db ad 56\n +#output: /rv: 0x10010: 78 9a fd e1 23 45 66 54\n +#output: /rv: 0x10018: 32 1a ac cb be ed db ed\n +#output: /rv: -> 0xfffd..0x10017\n +#output: /rv: 0x10000: 11 22 56 78 ee dd 12 ab\n +#output: /rv: 0x10008: 55 aa ee 00 42 12 27 98\n +#output: /rv: 0x10010: 88 55 22 33 66 77 22 45\n +#output: /rv: REG R 0xd0000038\n +#output: /rv: := 0x76543211\n +#output: pass\n + +# Trivial test of mailbox commands. + +#r W, +#r i,1b000512233456798abddefbadbadbad56789afde123456654321a +#r o,0b0005aa5577883210eecc +#r i,230006aa5512233456798abddefbadbadbad56789afde123456654321aaccbbeeddbed +#r o,1b000511225678eedd12ab55aaee00421227988855223366772245 +#r r,a8838,76543211 + + .include "testutils.inc" + start + move.w 0x1b,$r0 + move.d 0x1001d,$r1 + move.w $r0,[$r1+] + moveq 5,$r0 + move.b $r0,[$r1] + mvi_h_mem 0x56342312 0x10020 + mvi_h_mem 0xdebd8a79 0x10024 + mvi_h_mem 0xdbbaadfb 0x10028 + mvi_h_mem 0x9a7856ad 0x1002c + mvi_h_mem 0x4523e1fd 0x10030 + mvi_h_mem 0x1a325466 0x10034 + + mvi_h_mem 0x1001d 0xc000f000 + + move.d 0x1001d,$r0 + movu.w [$r0+],$r1 + test_h_gr 0xb $r1 + movu.b [$r0],$r1 + test_h_gr 0x5 $r1 + test_h_mem 0x887755aa 0x10020 + test_h_mem 0xccee1032 0x10024 + + move.w 0x23,$r0 + move.d 0xfffd,$r1 + move.w $r0,[$r1+] + moveq 6,$r0 + move.b $r0,[$r1] + mvi_h_mem 0x231255aa 0x10000 + mvi_h_mem 0x8a795634 0x10004 + mvi_h_mem 0xadfbdebd 0x10008 + mvi_h_mem 0x56addbba 0x1000c + mvi_h_mem 0xe1fd9a78 0x10010 + mvi_h_mem 0x54664523 0x10014 + mvi_h_mem 0xcbac1a32 0x10018 + mvi_h_mem 0xeddbedbe 0x1001c + + mvi_h_mem 0xfffd 0xc000f000 + + move.d 0xfffd,$r0 + movu.w [$r0+],$r1 + test_h_gr 0x1b $r1 + movu.b [$r0],$r1 + test_h_gr 0x6 $r1 + test_h_mem 0x78562211 0x10000 + test_h_mem 0xab12ddee 0x10004 + test_h_mem 0x00eeaa55 0x10008 + test_h_mem 0x98271242 0x1000c + test_h_mem 0x33225588 0x10010 + test_h_mem 0x45227766 0x10014 + + test_h_mem 0x76543211 0xd0000038 + pass + + .fill 65536*2+128,1,0 Index: hw/rv-n-cris/poll1.ms =================================================================== --- hw/rv-n-cris/poll1.ms (nonexistent) +++ hw/rv-n-cris/poll1.ms (revision 816) @@ -0,0 +1,22 @@ +#mach: crisv32 +#sim(crisv32): --hw-device "/rv/dummy 0x12" + +# A variant of trivial2.ms to check that the right thing happens when +# we reach the poll function with a dummy device. + + .include "testutils.inc" + start + move.d 0xd0000000,$r0 + move.d [$r0+],$r3 + cmp.d 0x12121212,$r3 + beq ok + nop +bad: + fail +ok: + move.d 0x10000,$r10 +0: + bne 0b + subq 1,$r10 + + pass Index: hw/rv-n-cris/std.dev =================================================================== --- hw/rv-n-cris/std.dev (nonexistent) +++ hw/rv-n-cris/std.dev (revision 816) @@ -0,0 +1,8 @@ +/rv/reg 0xd0000000 64 +/rv/remote-reg 0xa8800 +/rv/intnum 4 2 +/cris/vec-for-int 4 0x33 8 0x34 0xaa 0xea +/rv/mem 0x20000 0x400 +/rv/remote-mem 0xe000 +/rv/mbox 0xc000f000 +/rv > int int /cris Index: hw/rv-n-cris/testutils.inc =================================================================== --- hw/rv-n-cris/testutils.inc (nonexistent) +++ hw/rv-n-cris/testutils.inc (revision 816) @@ -0,0 +1,22 @@ + .include "../../asm/testutils.inc" + +# Define an exception vector table "vecname" with a single +# vector number "n" as "entry", all others "other". +# V32 only needs 1<<10 alignment, earlier versions need 1<<16. + .macro singlevec vecname vecno entry other=killme + .section .text.exvec + .p2align 16 +\vecname: + .if (\vecno) + .rept \vecno + .dword \other + .endr + .endif + .dword \entry + .if (\vecno)-255 + .rept 256-(\vecno)-1 + .dword \other + .endr + .endif + .previous + .endm Index: hw/rv-n-cris/wd1.ms =================================================================== --- hw/rv-n-cris/wd1.ms (nonexistent) +++ hw/rv-n-cris/wd1.ms (revision 816) @@ -0,0 +1,33 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" --hw-device "/rv/watchdog-interval 1" +#sim(crisv32): --hw-device "/rv/trace? true" --hw-device "/rv/watchdog-interval 1" --hw-device "/rv/max-poll-ticks 1000" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: /rv: WD\n +#output: /rv: DMA W 0x20000..0x20003\n +#output: /rv: 0x20000: 01 02 03 04\n +#output: /rv: REG R 0xd0000038\n +#output: /rv: := 0x76543211\n +#output: pass\n + +#r W, +#r r,a8836,76543210 +#r W, +#r s,e000,01020304 +#r r,a8838,76543211 + + .include "testutils.inc" + start + mvi_h_mem 0 0x20000 + test_h_mem 0x76543210 0xd0000036 + + move.d 0x20000,$r1 +0: + test.b [$r1] + beq 0b + nop + test_h_mem 0x76543211 0xd0000038 + pass + + .fill 65536*2+128,1,0 Index: hw/rv-n-cris/trivial1.ms =================================================================== --- hw/rv-n-cris/trivial1.ms (nonexistent) +++ hw/rv-n-cris/trivial1.ms (revision 816) @@ -0,0 +1,17 @@ +#mach: crisv32 +#sim(crisv32): --hw-info +#output: /\n +#output: /rv\n +#output: /rv/reg 0xd0000000 0x40\n +#output: /rv/remote-reg 0xa8800\n +#output: /rv/intnum 0x4 0x2\n +#output: /rv/mem 0x20000 0x400\n +#output: /rv/remote-mem 0xe000\n +#output: /rv/mbox 0xc000f000\n +#output: /rv > int int /cris\n +#output: /cris\n +#output: /cris/vec-for-int 0x4 0x33 0x8 0x34 0xaa 0xea\n + +# Test expected --hw-info output and startup paths of components. + + .include "quit.s" Index: hw/rv-n-cris/trivial2.ms =================================================================== --- hw/rv-n-cris/trivial2.ms (nonexistent) +++ hw/rv-n-cris/trivial2.ms (revision 816) @@ -0,0 +1,21 @@ +#mach: crisv32 +#sim(crisv32): --hw-device "/rv/dummy 0x12" + +# Test dummy settings: set from value. + + .include "testutils.inc" + start + move.d 0xd0000000,$r0 + move.d [$r0+],$r3 + cmp.d 0x12121212,$r3 + beq ok + nop +bad: + fail +ok: + moveq -1,$r3 + move.d $r3,[$r0] + cmp.d [$r0],$r3 + bne bad + nop + pass Index: hw/rv-n-cris/trivial3.ms =================================================================== --- hw/rv-n-cris/trivial3.ms (nonexistent) +++ hw/rv-n-cris/trivial3.ms (revision 816) @@ -0,0 +1,20 @@ +#mach: crisv32 +#sim(crisv32): --hw-device "/rv/dummy /dev/zero" + +# Test dummy settings: set from file. + + .include "testutils.inc" + start + move.d 0xd0000000,$r0 + move.d [$r0+],$r3 + beq ok + nop +bad: + fail +ok: + moveq -1,$r3 + move.d $r3,[$r0] + cmp.d [$r0],$r3 + bne bad + nop + pass Index: hw/rv-n-cris/host1.ms =================================================================== --- hw/rv-n-cris/host1.ms (nonexistent) +++ hw/rv-n-cris/host1.ms (revision 816) @@ -0,0 +1,8 @@ +#mach: crisv32 +#sim(crisv32): --hw-device "/rv/host localhost" + +# Check that we trivially resolve a hostname. + +#r @,@srcdir@/trivial4.r + + .include "trivial4.ms" Index: hw/rv-n-cris/trivial4.ms =================================================================== --- hw/rv-n-cris/trivial4.ms (nonexistent) +++ hw/rv-n-cris/trivial4.ms (revision 816) @@ -0,0 +1,22 @@ +#mach: crisv32 +#r @,@srcdir@/trivial4.r + +# Test read and writes. + + .include "testutils.inc" + start + move.d 0xd0000032,$r0 + move.d [$r0+],$r3 + cmp.d 0xabcdef01,$r3 + beq ok + nop +bad: + fail +ok: + move.d 0xaabbccdd,$r3 + move.d $r3,[$r0] + move.d [$r0],$r3 + cmp.d 0x76543210,$r3 + bne bad + nop + pass Index: hw/rv-n-cris/mem1.ms =================================================================== --- hw/rv-n-cris/mem1.ms (nonexistent) +++ hw/rv-n-cris/mem1.ms (revision 816) @@ -0,0 +1,100 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" +#sim(crisv32): --hw-device "/rv/trace? true" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: /rv: DMA W 0x20020..0x2003f\n +#output: /rv: 0x20020: 12 23 34 56\n +#output: /rv: 0x20024: 79 8a bd de\n +#output: /rv: 0x20028: fb ad ba db\n +#output: /rv: 0x2002c: ad 56 78 9a\n +#output: /rv: 0x20030: fd e1 23 45\n +#output: /rv: 0x20034: 66 54 32 1a\n +#output: /rv: 0x20038: ac cb be ed\n +#output: /rv: 0x2003c: db ed aa da\n +#output: /rv: REG R 0xd0000038\n +#output: /rv: := 0x76543211\n +#output: /rv: DMA R 0x20000..0x2001f\n +#output: /rv: 0x20000: aa 55 12 23\n +#output: /rv: 0x20004: 34 56 79 8a\n +#output: /rv: 0x20008: bd de fb ad\n +#output: /rv: 0x2000c: ba db ad 56\n +#output: /rv: 0x20010: 78 9a fd e1\n +#output: /rv: 0x20014: 23 45 66 54\n +#output: /rv: 0x20018: 32 1a ac cb\n +#output: /rv: 0x2001c: be ed db ed\n +#output: /rv: IRQ 0x8\n +#output: /rv: REG R 0xd0000038\n +#output: /rv: := 0x76543212\n +#output: pass\n + +# Trivial test of DMA. + +# Locations of IRQ notifiers above depend on when the simulator is +# polled; adjustments may be needed (after checking that no poll is +# gone due to a bug!) + +#r W, +#r r,a8836,76543210 +#r s,e020,12233456798abddefbadbadbad56789afde123456654321aaccbbeeddbedaada +#r r,a8838,76543211 +#r l,e000,aa5512233456798abddefbadbadbad56789afde123456654321aaccbbeeddbed +#r I,8 +#r r,a8838,76543212 + + .include "testutils.inc" + start + test_h_mem 0x76543210 0xd0000036 + + move.d 0x2003f,$r1 + move.d 0x10000,$r3 +0: + test.b [$r1] + bne 1f + subq 1,$r3 + bne 0b + nop + +1: + test_h_mem 0x56342312 0x20020 + test_h_mem 0xdebd8a79 0x20024 + test_h_mem 0xdbbaadfb 0x20028 + test_h_mem 0x9a7856ad 0x2002c + test_h_mem 0x4523e1fd 0x20030 + test_h_mem 0x1a325466 0x20034 + test_h_mem 0xedbecbac 0x20038 + test_h_mem 0xdaaaeddb 0x2003c + + move.d 0x20020,$r0 + move.d 0x20000,$r1 + move.w 0x55aa,$r2 + move.w $r2,[r1+] + .rept 8 + move.d [$r0+],$r2 + move.d $r2,[$r1+] + .endr + + test_h_mem 0x76543211 0xd0000038 + + .if ..asm.arch.cris.v32 + move irqvec1,$ebp + .else + move irqvec1,$ibr + .endif + ei + move.d 0x100000,$r9 +0: + subq 1,$r9 + bne 0b + nop +killme: + fail + +irq0x34: + test_h_mem 0x76543212 0xd0000038 + pass + + .fill 65536*2+128,1,0 + + singlevec irqvec1,0x34,irq0x34 Index: hw/rv-n-cris/trivial5.ms =================================================================== --- hw/rv-n-cris/trivial5.ms (nonexistent) +++ hw/rv-n-cris/trivial5.ms (revision 816) @@ -0,0 +1,16 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" +#sim(crisv32): --hw-device "/rv/trace? true" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000032\n +#output: /rv: := 0xabcdef01\n +#output: /rv: REG W 0xd0000036 := 0xaabbccdd\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: pass\n + +# Test trace output for read and write. + +#r @,@srcdir@/trivial4.r + + .include "trivial4.ms" Index: hw/rv-n-cris/mem2.ms =================================================================== --- hw/rv-n-cris/mem2.ms (nonexistent) +++ hw/rv-n-cris/mem2.ms (revision 816) @@ -0,0 +1,104 @@ +#mach: crisv10 crisv32 +#sim(crisv10): --hw-device "/rv/trace? true" +#sim(crisv32): --hw-device "/rv/trace? true" +#output: /rv: WD\n +#output: /rv: REG R 0xd0000036\n +#output: /rv: := 0x76543210\n +#output: /rv: DMA W 0x20020..0x20043\n +#output: /rv: 0x20020: 12 23 34 56\n +#output: /rv: 0x20024: 79 8a bd de\n +#output: /rv: 0x20028: fb ad ba db\n +#output: /rv: 0x2002c: ad 56 78 9a\n +#output: /rv: 0x20030: fd e1 23 45\n +#output: /rv: 0x20034: 66 54 32 1a\n +#output: /rv: 0x20038: ac cb be ed\n +#output: /rv: 0x2003c: db ed aa da\n +#output: /rv: 0x20040: 00 aa bb cc\n +#output: /rv: REG R 0xd0000038\n +#output: /rv: := 0x76543211\n +#output: /rv: DMA R 0x20000..0x20023\n +#output: /rv: 0x20000: aa 55 12 23\n +#output: /rv: 0x20004: 34 56 79 8a\n +#output: /rv: 0x20008: bd de fb ad\n +#output: /rv: 0x2000c: ba db ad 56\n +#output: /rv: 0x20010: 78 9a fd e1\n +#output: /rv: 0x20014: 23 45 66 54\n +#output: /rv: 0x20018: 32 1a ac cb\n +#output: /rv: 0x2001c: be ed db ed\n +#output: /rv: 0x20020: aa da 00 aa\n +#output: /rv: IRQ 0x8\n +#output: /rv: REG R 0xd0000038\n +#output: /rv: := 0x76543212\n +#output: pass\n + +# This is a slight variation of mem1.ms just to trig the "buffer needs +# to be malloced for large request size" for the DMA request. + +# Locations of IRQ notifiers above depend on when the simulator is +# polled; adjustments may be needed (after checking that no poll is +# gone due to a bug!) + +#r W, +#r r,a8836,76543210 +#r s,e020,12233456798abddefbadbadbad56789afde123456654321aaccbbeeddbedaada00aabbcc +#r r,a8838,76543211 +#r l,e000,aa5512233456798abddefbadbadbad56789afde123456654321aaccbbeeddbedaada00aa +#r I,8 +#r r,a8838,76543212 + + .include "testutils.inc" + start + test_h_mem 0x76543210 0xd0000036 + + move.d 0x2003f,$r1 + move.d 0x10000,$r3 +0: + test.b [$r1] + bne 1f + subq 1,$r3 + bne 0b + nop + +1: + test_h_mem 0x56342312 0x20020 + test_h_mem 0xdebd8a79 0x20024 + test_h_mem 0xdbbaadfb 0x20028 + test_h_mem 0x9a7856ad 0x2002c + test_h_mem 0x4523e1fd 0x20030 + test_h_mem 0x1a325466 0x20034 + test_h_mem 0xedbecbac 0x20038 + test_h_mem 0xdaaaeddb 0x2003c + test_h_mem 0xccbbaa00 0x20040 + + move.d 0x20020,$r0 + move.d 0x20000,$r1 + move.w 0x55aa,$r2 + move.w $r2,[r1+] + .rept 9 + move.d [$r0+],$r2 + move.d $r2,[$r1+] + .endr + + test_h_mem 0x76543211 0xd0000038 + + .if ..asm.arch.cris.v32 + move irqvec1,$ebp + .else + move irqvec1,$ibr + .endif + ei + move.d 0x100000,$r9 +0: + subq 1,$r9 + bne 0b + nop +killme: + fail + +irq0x34: + test_h_mem 0x76543212 0xd0000038 + pass + + .fill 65536*2+128,1,0 + + singlevec irqvec1,0x34,irq0x34

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