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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/gnu-src/binutils-2.18.50/gas/testsuite/gas/m32r
    from Rev 38 to Rev 156
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  •

Rev 38 → Rev 156

/signed-relocs.d
0,0 → 1,77
#as: -J
#objdump: -dr
#name: Signed relocs
 
.*: +file format .*
 
Disassembly of section .text:
 
0+0000 <relocs>:
0: d0 c0 87 65 seth r0,#0x8765
4: 80 a0 43 21 add3 r0,r0,#17185
8: d0 c0 87 65 seth r0,#0x8765
c: 80 a0 43 21 add3 r0,r0,#17185
10: d0 c0 12 35 seth r0,#0x1235
14: 80 a0 ff ff add3 r0,r0,#-1
18: d0 c0 12 35 seth r0,#0x1235
1c: 80 a0 ff ff add3 r0,r0,#-1
20: d0 c0 87 65 seth r0,#0x8765
24: 80 e0 43 21 or3 r0,r0,#0x4321
28: d0 c0 87 65 seth r0,#0x8765
2c: 80 e0 43 21 or3 r0,r0,#0x4321
30: d0 c0 12 34 seth r0,#0x1234
34: 80 e0 ff ff or3 r0,r0,#0xffff
38: d0 c0 12 34 seth r0,#0x1234
3c: 80 e0 ff ff or3 r0,r0,#0xffff
40: d0 c0 87 65 seth r0,#0x8765
44: a0 c0 43 20 ld r0,@\(17184,r0\)
48: d0 c0 87 65 seth r0,#0x8765
4c: a0 a0 43 20 ldh r0,@\(17184,r0\)
50: d0 c0 87 65 seth r0,#0x8765
54: a0 b0 43 20 lduh r0,@\(17184,r0\)
58: d0 c0 87 65 seth r0,#0x8765
5c: a0 80 43 20 ldb r0,@\(17184,r0\)
60: d0 c0 87 65 seth r0,#0x8765
64: a0 90 43 20 ldub r0,@\(17184,r0\)
68: d0 c0 12 35 seth r0,#0x1235
6c: a0 c0 ff f0 ld r0,@\(-16,r0\)
70: d0 c0 12 35 seth r0,#0x1235
74: a0 a0 ff f0 ldh r0,@\(-16,r0\)
78: d0 c0 12 35 seth r0,#0x1235
7c: a0 b0 ff f0 lduh r0,@\(-16,r0\)
80: d0 c0 12 35 seth r0,#0x1235
84: a0 80 ff f0 ldb r0,@\(-16,r0\)
88: d0 c0 12 35 seth r0,#0x1235
8c: a0 90 ff f0 ldub r0,@\(-16,r0\)
90: d0 c0 87 65 seth r0,#0x8765
94: a0 c0 43 20 ld r0,@\(17184,r0\)
98: d0 c0 87 65 seth r0,#0x8765
9c: a0 a0 43 20 ldh r0,@\(17184,r0\)
a0: d0 c0 87 65 seth r0,#0x8765
a4: a0 b0 43 20 lduh r0,@\(17184,r0\)
a8: d0 c0 87 65 seth r0,#0x8765
ac: a0 80 43 20 ldb r0,@\(17184,r0\)
b0: d0 c0 87 65 seth r0,#0x8765
b4: a0 90 43 20 ldub r0,@\(17184,r0\)
b8: d0 c0 12 35 seth r0,#0x1235
bc: a0 c0 ff f0 ld r0,@\(-16,r0\)
c0: d0 c0 87 65 seth r0,#0x8765
c4: a0 40 43 20 st r0,@\(17184,r0\)
c8: d0 c0 87 65 seth r0,#0x8765
cc: a0 20 43 20 sth r0,@\(17184,r0\)
d0: d0 c0 87 65 seth r0,#0x8765
d4: a0 00 43 20 stb r0,@\(17184,r0\)
d8: d0 c0 12 35 seth r0,#0x1235
dc: a0 40 ff f0 st r0,@\(-16,r0\)
e0: d0 c0 12 35 seth r0,#0x1235
e4: a0 20 ff f0 sth r0,@\(-16,r0\)
e8: d0 c0 12 35 seth r0,#0x1235
ec: a0 00 ff f0 stb r0,@\(-16,r0\)
f0: d0 c0 87 65 seth r0,#0x8765
f4: a0 40 43 20 st r0,@\(17184,r0\)
f8: d0 c0 87 65 seth r0,#0x8765
fc: a0 20 43 20 sth r0,@\(17184,r0\)
100: d0 c0 87 65 seth r0,#0x8765
104: a0 00 43 20 stb r0,@\(17184,r0\)
108: d0 c0 12 35 seth r0,#0x1235
10c: a0 40 ff f0 st r0,@\(-16,r0\)
/fslotx.s
0,0 → 1,19
# Test the FILL-SLOT attribute.
# The FILL-SLOT attribute ensures the next insn begins on a 32 byte boundary.
# This is needed for example with bl because the subroutine will return
# to a 32 bit boundary.
 
.text
bcl:
bcl bcl
ldi r0,#8
bcl_s:
bcl.s bcl_s
ldi r0,#8
 
bncl:
bncl bncl
ldi r0,#8
bncl_s:
bncl.s bncl_s
ldi r0,#8
/allinsn.d
0,0 → 1,374
#as:
#objdump: -dr
#name: allinsn
 
.*: +file format .*
 
Disassembly of section .text:
 
0+0000 <add>:
0: 0d ad f0 00 add fp,fp \|\| nop
 
0+0004 <add3>:
4: 8d ad 00 00 add3 fp,fp,[#]*0
 
0+0008 <and>:
8: 0d cd f0 00 and fp,fp \|\| nop
 
0+000c <and3>:
c: 8d cd 00 00 and3 fp,fp,[#]*0x0
 
0+0010 <or>:
10: 0d ed f0 00 or fp,fp \|\| nop
 
0+0014 <or3>:
14: 8d ed 00 00 or3 fp,fp,[#]*0x0
 
0+0018 <xor>:
18: 0d dd f0 00 xor fp,fp \|\| nop
 
0+001c <xor3>:
1c: 8d dd 00 00 xor3 fp,fp,[#]*0x0
 
0+0020 <addi>:
20: 4d 00 f0 00 addi fp,[#]*0 \|\| nop
 
0+0024 <addv>:
24: 0d 8d f0 00 addv fp,fp \|\| nop
 
0+0028 <addv3>:
28: 8d 8d 00 00 addv3 fp,fp,[#]*0
 
0+002c <addx>:
2c: 0d 9d f0 00 addx fp,fp \|\| nop
 
0+0030 <bc8>:
30: 7c f4 f0 00 bc 0 <add> \|\| nop
 
0+0034 <bc8_s>:
34: 7c f3 f0 00 bc 0 <add> \|\| nop
 
0+0038 <bc24>:
38: 7c f2 f0 00 bc 0 <add> \|\| nop
 
0+003c <bc24_l>:
3c: fc ff ff f1 bc 0 <add>
 
0+0040 <beq>:
40: bd 0d ff f0 beq fp,fp,0 <add>
 
0+0044 <beqz>:
44: b0 8d ff ef beqz fp,0 <add>
 
0+0048 <bgez>:
48: b0 bd ff ee bgez fp,0 <add>
 
0+004c <bgtz>:
4c: b0 dd ff ed bgtz fp,0 <add>
 
0+0050 <blez>:
50: b0 cd ff ec blez fp,0 <add>
 
0+0054 <bltz>:
54: b0 ad ff eb bltz fp,0 <add>
 
0+0058 <bnez>:
58: b0 9d ff ea bnez fp,0 <add>
 
0+005c <bl8>:
5c: 7e e9 f0 00 bl 0 <add> \|\| nop
 
0+0060 <bl8_s>:
60: 7e e8 f0 00 bl 0 <add> \|\| nop
 
0+0064 <bl24>:
64: 7e e7 f0 00 bl 0 <add> \|\| nop
 
0+0068 <bl24_l>:
68: fe ff ff e6 bl 0 <add>
 
0+006c <bnc8>:
6c: 7d e5 f0 00 bnc 0 <add> \|\| nop
 
0+0070 <bnc8_s>:
70: 7d e4 f0 00 bnc 0 <add> \|\| nop
 
0+0074 <bnc24>:
74: 7d e3 f0 00 bnc 0 <add> \|\| nop
 
0+0078 <bnc24_l>:
78: fd ff ff e2 bnc 0 <add>
 
0+007c <bne>:
7c: bd 1d ff e1 bne fp,fp,0 <add>
 
0+0080 <bra8>:
80: 7f e0 f0 00 bra 0 <add> \|\| nop
 
0+0084 <bra8_s>:
84: 7f df f0 00 bra 0 <add> \|\| nop
 
0+0088 <bra24>:
88: 7f de f0 00 bra 0 <add> \|\| nop
 
0+008c <bra24_l>:
8c: ff ff ff dd bra 0 <add>
 
0+0090 <cmp>:
90: 0d 4d f0 00 cmp fp,fp \|\| nop
 
0+0094 <cmpi>:
94: 80 4d 00 00 cmpi fp,[#]*0
 
0+0098 <cmpu>:
98: 0d 5d f0 00 cmpu fp,fp \|\| nop
 
0+009c <cmpui>:
9c: 80 5d 00 00 cmpui fp,[#]*0
 
0+00a0 <div>:
a0: 9d 0d 00 00 div fp,fp
 
0+00a4 <divu>:
a4: 9d 1d 00 00 divu fp,fp
 
0+00a8 <rem>:
a8: 9d 2d 00 00 rem fp,fp
 
0+00ac <remu>:
ac: 9d 3d 00 00 remu fp,fp
 
0+00b0 <jl>:
b0: 1e cd f0 00 jl fp \|\| nop
 
0+00b4 <jmp>:
b4: 1f cd f0 00 jmp fp \|\| nop
 
0+00b8 <ld>:
b8: 2d cd f0 00 ld fp,@fp \|\| nop
 
0+00bc <ld_2>:
bc: 2d cd f0 00 ld fp,@fp \|\| nop
 
0+00c0 <ld_d>:
c0: ad cd 00 00 ld fp,@\(0,fp\)
 
0+00c4 <ld_d2>:
c4: ad cd 00 00 ld fp,@\(0,fp\)
 
0+00c8 <ldb>:
c8: 2d 8d f0 00 ldb fp,@fp \|\| nop
 
0+00cc <ldb_2>:
cc: 2d 8d f0 00 ldb fp,@fp \|\| nop
 
0+00d0 <ldb_d>:
d0: ad 8d 00 00 ldb fp,@\(0,fp\)
 
0+00d4 <ldb_d2>:
d4: ad 8d 00 00 ldb fp,@\(0,fp\)
 
0+00d8 <ldh>:
d8: 2d ad f0 00 ldh fp,@fp \|\| nop
 
0+00dc <ldh_2>:
dc: 2d ad f0 00 ldh fp,@fp \|\| nop
 
0+00e0 <ldh_d>:
e0: ad ad 00 00 ldh fp,@\(0,fp\)
 
0+00e4 <ldh_d2>:
e4: ad ad 00 00 ldh fp,@\(0,fp\)
 
0+00e8 <ldub>:
e8: 2d 9d f0 00 ldub fp,@fp \|\| nop
 
0+00ec <ldub_2>:
ec: 2d 9d f0 00 ldub fp,@fp \|\| nop
 
0+00f0 <ldub_d>:
f0: ad 9d 00 00 ldub fp,@\(0,fp\)
 
0+00f4 <ldub_d2>:
f4: ad 9d 00 00 ldub fp,@\(0,fp\)
 
0+00f8 <lduh>:
f8: 2d bd f0 00 lduh fp,@fp \|\| nop
 
0+00fc <lduh_2>:
fc: 2d bd f0 00 lduh fp,@fp \|\| nop
 
0+0100 <lduh_d>:
100: ad bd 00 00 lduh fp,@\(0,fp\)
 
0+0104 <lduh_d2>:
104: ad bd 00 00 lduh fp,@\(0,fp\)
 
0+0108 <ld_plus>:
108: 2d ed f0 00 ld fp,@fp\+ \|\| nop
 
0+010c <ld24>:
10c: ed 00 00 00 ld24 fp,[#]*0 <add>
10c: R_M32R_24_RELA .data
 
0+0110 <ldi8>:
110: 6d 00 f0 00 ldi fp,[#]*0 \|\| nop
 
0+0114 <ldi16>:
114: 9d f0 01 00 ldi fp,[#]*256
 
0+0118 <lock>:
118: 2d dd f0 00 lock fp,@fp \|\| nop
 
0+011c <machi>:
11c: 3d 4d f0 00 machi fp,fp \|\| nop
 
0+0120 <maclo>:
120: 3d 5d f0 00 maclo fp,fp \|\| nop
 
0+0124 <macwhi>:
124: 3d 6d f0 00 macwhi fp,fp \|\| nop
 
0+0128 <macwlo>:
128: 3d 7d f0 00 macwlo fp,fp \|\| nop
 
0+012c <mul>:
12c: 1d 6d f0 00 mul fp,fp \|\| nop
 
0+0130 <mulhi>:
130: 3d 0d f0 00 mulhi fp,fp \|\| nop
 
0+0134 <mullo>:
134: 3d 1d f0 00 mullo fp,fp \|\| nop
 
0+0138 <mulwhi>:
138: 3d 2d f0 00 mulwhi fp,fp \|\| nop
 
0+013c <mulwlo>:
13c: 3d 3d f0 00 mulwlo fp,fp \|\| nop
 
0+0140 <mv>:
140: 1d 8d f0 00 mv fp,fp \|\| nop
 
0+0144 <mvfachi>:
144: 5d f0 f0 00 mvfachi fp \|\| nop
 
0+0148 <mvfaclo>:
148: 5d f1 f0 00 mvfaclo fp \|\| nop
 
0+014c <mvfacmi>:
14c: 5d f2 f0 00 mvfacmi fp \|\| nop
 
0+0150 <mvfc>:
150: 1d 90 f0 00 mvfc fp,psw \|\| nop
 
0+0154 <mvtachi>:
154: 5d 70 f0 00 mvtachi fp \|\| nop
 
0+0158 <mvtaclo>:
158: 5d 71 f0 00 mvtaclo fp \|\| nop
 
0+015c <mvtc>:
15c: 10 ad f0 00 mvtc fp,psw \|\| nop
 
0+0160 <neg>:
160: 0d 3d f0 00 neg fp,fp \|\| nop
 
0+0164 <nop>:
164: 70 00 f0 00 nop \|\| nop
 
0+0168 <not>:
168: 0d bd f0 00 not fp,fp \|\| nop
 
0+016c <rac>:
16c: dd c0 00 00 seth fp,[#]*0x0
 
0+0170 <sll>:
170: 1d 4d f0 00 sll fp,fp \|\| nop
 
0+0174 <sll3>:
174: 9d cd 00 00 sll3 fp,fp,[#]*0
 
0+0178 <slli>:
178: 5d 40 f0 00 slli fp,[#]*0x0 \|\| nop
 
0+017c <sra>:
17c: 1d 2d f0 00 sra fp,fp \|\| nop
 
0+0180 <sra3>:
180: 9d ad 00 00 sra3 fp,fp,[#]*0
 
0+0184 <srai>:
184: 5d 20 f0 00 srai fp,[#]*0x0 \|\| nop
 
0+0188 <srl>:
188: 1d 0d f0 00 srl fp,fp \|\| nop
 
0+018c <srl3>:
18c: 9d 8d 00 00 srl3 fp,fp,[#]*0
 
0+0190 <srli>:
190: 5d 00 f0 00 srli fp,[#]*0x0 \|\| nop
 
0+0194 <st>:
194: 2d 4d f0 00 st fp,@fp \|\| nop
 
0+0198 <st_2>:
198: 2d 4d f0 00 st fp,@fp \|\| nop
 
0+019c <st_d>:
19c: ad 4d 00 00 st fp,@\(0,fp\)
 
0+01a0 <st_d2>:
1a0: ad 4d 00 00 st fp,@\(0,fp\)
 
0+01a4 <stb>:
1a4: 2d 0d f0 00 stb fp,@fp \|\| nop
 
0+01a8 <stb_2>:
1a8: 2d 0d f0 00 stb fp,@fp \|\| nop
 
0+01ac <stb_d>:
1ac: ad 0d 00 00 stb fp,@\(0,fp\)
 
0+01b0 <stb_d2>:
1b0: ad 0d 00 00 stb fp,@\(0,fp\)
 
0+01b4 <sth>:
1b4: 2d 2d f0 00 sth fp,@fp \|\| nop
 
0+01b8 <sth_2>:
1b8: 2d 2d f0 00 sth fp,@fp \|\| nop
 
0+01bc <sth_d>:
1bc: ad 2d 00 00 sth fp,@\(0,fp\)
 
0+01c0 <sth_d2>:
1c0: ad 2d 00 00 sth fp,@\(0,fp\)
 
0+01c4 <st_plus>:
1c4: 2d 6d f0 00 st fp,@\+fp \|\| nop
 
0+01c8 <st_minus>:
1c8: 2d 7d f0 00 st fp,@-fp \|\| nop
 
0+01cc <sub>:
1cc: 0d 2d f0 00 sub fp,fp \|\| nop
 
0+01d0 <subv>:
1d0: 0d 0d f0 00 subv fp,fp \|\| nop
 
0+01d4 <subx>:
1d4: 0d 1d f0 00 subx fp,fp \|\| nop
 
0+01d8 <trap>:
1d8: 10 f0 f0 00 trap [#]*0x0 \|\| nop
 
0+01dc <unlock>:
1dc: 2d 5d f0 00 unlock fp,@fp \|\| nop
 
0+01e0 <push>:
1e0: 2d 7f f0 00 push fp \|\| nop
 
0+01e4 <pop>:
1e4: 2d ef f0 00 pop fp \|\| nop
/rela-1.s
0,0 → 1,18
 
.section .text
bl label
bl.l label
bl.s label
bnez r0,label
mv r0,r0
bl.s label
 
.section .text2, "ax"
nop
nop
nop
nop
label:
.end
 
 
/error.exp
0,0 → 1,17
# Test assembler warnings and errors.
 
if [istarget m32r-*-*] {
 
load_lib gas-dg.exp
 
dg-init
 
dg-runtest "$srcdir/$subdir/wrongsize.s" "" ""
dg-runtest "$srcdir/$subdir/interfere.s" "" ""
dg-runtest "$srcdir/$subdir/outofrange.s" "" ""
dg-runtest "$srcdir/$subdir/parallel.s" "" ""
dg-runtest "$srcdir/$subdir/rel32-err.s" "" ""
 
dg-finish
 
}
/interfere.s
0,0 → 1,14
; Test error messages in instances where output operands interfere.
 
; { dg-do assemble { target m32r-*-* } }
; { dg-options -m32rx }
 
interfere:
trap #1 || cmp r3, r4 ; { dg-error "write to the same" }
; { dg-warning "same" "out->in" { target *-*-* } { 7 } }
rte || addx r3, r4 ; { dg-error "write to the same" }
; { dg-warning "same" "out->in" { target *-*-* } { 9 } }
cmp r1, r2 || addx r3, r4 ; { dg-error "write to the same" }
; { dg-warning "same" "out->in" { target *-*-* } { 11 } }
mvtc r0, psw || addx r1, r4 ; { dg-error "write to the same" }
; { dg-warning "same" "out->in" { target *-*-* } { 13 } }
/fslot.s
0,0 → 1,27
# Test the FILL-SLOT attribute.
# The FILL-SLOT attribute ensures the next insn begins on a 32 byte boundary.
# This is needed for example with bl because the subroutine will return
# to a 32 bit boundary.
 
.text
bl:
bl bl
ldi r0,#8
bl_s:
bl.s bl_s
ldi r0,#8
 
bra:
bra bra
ldi r0,#8
bra_s:
bra.s bra_s
ldi r0,#8
 
jl:
jl r0
ldi r0,#8
 
trap:
trap #4
ldi r0,#8
/uppercase.s
0,0 → 1,14
.text
.global foo
foo:
mv R0,R1
mvfc R0,CBR
 
high:
seth r0,#HIGH(high)
shigh:
seth r0,#SHIGH(shigh)
low:
or3 r0,r0,#LOW(low)
sda:
add3 r0,r0,#SDA(sdavar)
/rel32.s
0,0 → 1,12
.text
nop
nop
bar:
.section .text2
.4byte bar - .
label:
nop
nop
.4byte bar - label
.4byte bar - label2
label2:
/parallel-2.s
0,0 → 1,7
.text
test:
add r4,r5
st r4,@(r6)
addi r6,#4
.debugsym .LM568
bc.s test
/parallel.s
0,0 → 1,14
; Test error messages where parallel instructions conflict
 
; { dg-options "-m32rx" }
; { dg-do assemble { target m32r-*-* } }
 
.text
.global parallel
parallel:
mv r1,r0 || mv r2,r1
; { dg-warning "output of 1st instruction" "parallel output overlaps input" { target *-*-* } { 9 } }
mv r1,r0 || mv r0,r2
; { dg-warning "output of 2nd instruction" "parallel output overlaps input" { target *-*-* } { 11 } }
mv r1,r0 || mv r1,r2
; { dg-error "instructions write to the same destination register" "parallel overlapping destinations" { target *-*-* } { 13 } }
/signed-relocs.s
0,0 → 1,80
; check: not case sensitive for special operand modifier
; check: shigh, high, low
.text
relocs:
seth r0, #shigh(0x87654321)
add3 r0, r0, #low(0x87654321)
seth r0, #SHIGH(0x87654321)
add3 r0, r0, #LOW(0x87654321)
seth r0, #shigh(0x1234ffff)
add3 r0, r0, #low(0x1234ffff)
seth r0, #SHIGH(0x1234ffff)
add3 r0, r0, #LOW(0x1234ffff)
 
seth r0, #high(0x87654321)
or3 r0, r0, #low(0x87654321)
seth r0, #HIGH(0x87654321)
or3 r0, r0, #LOW(0x87654321)
seth r0, #high(0x1234ffff)
or3 r0, r0, #low(0x1234ffff)
seth r0, #HIGH(0x1234ffff)
or3 r0, r0, #LOW(0x1234ffff)
 
seth r0, #shigh(0x87654320)
ld r0, @(#low(0x87654320),r0)
seth r0, #shigh(0x87654320)
ldh r0, @(#low(0x87654320),r0)
seth r0, #shigh(0x87654320)
lduh r0, @(#low(0x87654320),r0)
seth r0, #shigh(0x87654320)
ldb r0, @(#low(0x87654320),r0)
seth r0, #shigh(0x87654320)
ldub r0, @(#low(0x87654320),r0)
 
seth r0, #shigh(0x1234fff0)
ld r0, @(#low(0x1234fff0),r0)
seth r0, #shigh(0x1234fff0)
ldh r0, @(#low(0x1234fff0),r0)
seth r0, #shigh(0x1234fff0)
lduh r0, @(#low(0x1234fff0),r0)
seth r0, #shigh(0x1234fff0)
ldb r0, @(#low(0x1234fff0),r0)
seth r0, #shigh(0x1234fff0)
ldub r0, @(#low(0x1234fff0),r0)
 
seth r0, #SHIGH(0x87654320)
ld r0, @(#LOW(0x87654320),r0)
seth r0, #SHIGH(0x87654320)
ldh r0, @(#LOW(0x87654320),r0)
seth r0, #SHIGH(0x87654320)
lduh r0, @(#LOW(0x87654320),r0)
seth r0, #SHIGH(0x87654320)
ldb r0, @(#LOW(0x87654320),r0)
seth r0, #SHIGH(0x87654320)
ldub r0, @(#LOW(0x87654320),r0)
seth r0, #SHIGH(0x1234fff0)
ld r0, @(#LOW(0x1234fff0),r0)
 
seth r0, #shigh(0x87654320)
st r0, @(#low(0x87654320),r0)
seth r0, #shigh(0x87654320)
sth r0, @(#low(0x87654320),r0)
seth r0, #shigh(0x87654320)
stb r0, @(#low(0x87654320),r0)
 
seth r0, #shigh(0x1234fff0)
st r0, @(#low(0x1234fff0),r0)
seth r0, #shigh(0x1234fff0)
sth r0, @(#low(0x1234fff0),r0)
seth r0, #shigh(0x1234fff0)
stb r0, @(#low(0x1234fff0),r0)
 
seth r0, #SHIGH(0x87654320)
st r0, @(#LOW(0x87654320),r0)
seth r0, #SHIGH(0x87654320)
sth r0, @(#LOW(0x87654320),r0)
seth r0, #SHIGH(0x87654320)
stb r0, @(#LOW(0x87654320),r0)
seth r0, #SHIGH(0x1234fff0)
st r0, @(#LOW(0x1234fff0),r0)
 
/high-1.d
0,0 → 1,19
#as:
#objdump: -dr
#name: high-1
 
.*: +file format .*
 
Disassembly of section .text:
 
0* <foo>:
*0: d4 c0 00 00 seth r4,[#]*0x0
[ ]*0: R_M32R_HI16_ULO_RELA .text\+0x10000
*4: 84 e4 00 00 or3 r4,r4,[#]*0x0
[ ]*4: R_M32R_LO16_RELA .text\+0x10000
*8: d4 c0 12 34 seth r4,[#]*0x1234
*c: 84 e4 87 65 or3 r4,r4,[#]*0x8765
*10: d4 c0 12 35 seth r4,[#]*0x1235
*14: 84 e4 87 65 or3 r4,r4,[#]*0x8765
*18: d4 c0 87 65 seth r4,[#]*0x8765
*1c: 84 e4 43 21 or3 r4,r4,[#]*0x4321
/m32r2.exp
0,0 → 1,6
# M32R2 assembler testsuite.
 
if [istarget m32r*-*-*] {
run_dump_test "m32r2"
run_dump_test "parallel-2"
}
/allinsn.s
0,0 → 1,501
.data
foodata: .word 42
.text
footext:
.text
.global add
add:
add fp,fp
.text
.global add3
add3:
add3 fp,fp,#0
.text
.global and
and:
and fp,fp
.text
.global and3
and3:
and3 fp,fp,#0
.text
.global or
or:
or fp,fp
.text
.global or3
or3:
or3 fp,fp,#0
.text
.global xor
xor:
xor fp,fp
.text
.global xor3
xor3:
xor3 fp,fp,#0
.text
.global addi
addi:
addi fp,#0
.text
.global addv
addv:
addv fp,fp
.text
.global addv3
addv3:
addv3 fp,fp,#0
.text
.global addx
addx:
addx fp,fp
.text
.global bc8
bc8:
bc footext
.text
.global bc8_s
bc8_s:
bc.s footext
.text
.global bc24
bc24:
bc footext
.text
.global bc24_l
bc24_l:
bc.l footext
.text
.global beq
beq:
beq fp,fp,footext
.text
.global beqz
beqz:
beqz fp,footext
.text
.global bgez
bgez:
bgez fp,footext
.text
.global bgtz
bgtz:
bgtz fp,footext
.text
.global blez
blez:
blez fp,footext
.text
.global bltz
bltz:
bltz fp,footext
.text
.global bnez
bnez:
bnez fp,footext
.text
.global bl8
bl8:
bl footext
.text
.global bl8_s
bl8_s:
bl.s footext
.text
.global bl24
bl24:
bl footext
.text
.global bl24_l
bl24_l:
bl.l footext
.text
.global bnc8
bnc8:
bnc footext
.text
.global bnc8_s
bnc8_s:
bnc.s footext
.text
.global bnc24
bnc24:
bnc footext
.text
.global bnc24_l
bnc24_l:
bnc.l footext
.text
.global bne
bne:
bne fp,fp,footext
.text
.global bra8
bra8:
bra footext
.text
.global bra8_s
bra8_s:
bra.s footext
.text
.global bra24
bra24:
bra footext
.text
.global bra24_l
bra24_l:
bra.l footext
.text
.global cmp
cmp:
cmp fp,fp
.text
.global cmpi
cmpi:
cmpi fp,#0
.text
.global cmpu
cmpu:
cmpu fp,fp
.text
.global cmpui
cmpui:
cmpui fp,#0
.text
.global div
div:
div fp,fp
.text
.global divu
divu:
divu fp,fp
.text
.global rem
rem:
rem fp,fp
.text
.global remu
remu:
remu fp,fp
.text
.global jl
jl:
jl fp
.text
.global jmp
jmp:
jmp fp
.text
.global ld
ld:
ld fp,@fp
.text
.global ld_2
ld_2:
ld fp,@(fp)
.text
.global ld_d
ld_d:
ld fp,@(0,fp)
.text
.global ld_d2
ld_d2:
ld fp,@(fp,0)
.text
.global ldb
ldb:
ldb fp,@fp
.text
.global ldb_2
ldb_2:
ldb fp,@(fp)
.text
.global ldb_d
ldb_d:
ldb fp,@(0,fp)
.text
.global ldb_d2
ldb_d2:
ldb fp,@(fp,0)
.text
.global ldh
ldh:
ldh fp,@fp
.text
.global ldh_2
ldh_2:
ldh fp,@(fp)
.text
.global ldh_d
ldh_d:
ldh fp,@(0,fp)
.text
.global ldh_d2
ldh_d2:
ldh fp,@(fp,0)
.text
.global ldub
ldub:
ldub fp,@fp
.text
.global ldub_2
ldub_2:
ldub fp,@(fp)
.text
.global ldub_d
ldub_d:
ldub fp,@(0,fp)
.text
.global ldub_d2
ldub_d2:
ldub fp,@(fp,0)
.text
.global lduh
lduh:
lduh fp,@fp
.text
.global lduh_2
lduh_2:
lduh fp,@(fp)
.text
.global lduh_d
lduh_d:
lduh fp,@(0,fp)
.text
.global lduh_d2
lduh_d2:
lduh fp,@(fp,0)
.text
.global ld_plus
ld_plus:
ld fp,@fp+
.text
.global ld24
ld24:
ld24 fp,foodata
.text
.global ldi8
ldi8:
ldi fp,0
.text
.global ldi16
ldi16:
ldi fp,256
.text
.global lock
lock:
lock fp,@fp
.text
.global machi
machi:
machi fp,fp
.text
.global maclo
maclo:
maclo fp,fp
.text
.global macwhi
macwhi:
macwhi fp,fp
.text
.global macwlo
macwlo:
macwlo fp,fp
.text
.global mul
mul:
mul fp,fp
.text
.global mulhi
mulhi:
mulhi fp,fp
.text
.global mullo
mullo:
mullo fp,fp
.text
.global mulwhi
mulwhi:
mulwhi fp,fp
.text
.global mulwlo
mulwlo:
mulwlo fp,fp
.text
.global mv
mv:
mv fp,fp
.text
.global mvfachi
mvfachi:
mvfachi fp
.text
.global mvfaclo
mvfaclo:
mvfaclo fp
.text
.global mvfacmi
mvfacmi:
mvfacmi fp
.text
.global mvfc
mvfc:
mvfc fp,psw
.text
.global mvtachi
mvtachi:
mvtachi fp
.text
.global mvtaclo
mvtaclo:
mvtaclo fp
.text
.global mvtc
mvtc:
mvtc fp,psw
.text
.global neg
neg:
neg fp,fp
.text
.global nop
nop:
nop
.text
.global not
not:
not fp,fp
.text
.global rac
rac:
.text
.global rach
rach:
.text
.global rte
rte:
.text
.global seth
seth:
seth fp,0
.text
.global sll
sll:
sll fp,fp
.text
.global sll3
sll3:
sll3 fp,fp,0
.text
.global slli
slli:
slli fp,0
.text
.global sra
sra:
sra fp,fp
.text
.global sra3
sra3:
sra3 fp,fp,0
.text
.global srai
srai:
srai fp,0
.text
.global srl
srl:
srl fp,fp
.text
.global srl3
srl3:
srl3 fp,fp,0
.text
.global srli
srli:
srli fp,0
.text
.global st
st:
st fp,@fp
.text
.global st_2
st_2:
st fp,@(fp)
.text
.global st_d
st_d:
st fp,@(0,fp)
.text
.global st_d2
st_d2:
st fp,@(fp,0)
.text
.global stb
stb:
stb fp,@fp
.text
.global stb_2
stb_2:
stb fp,@(fp)
.text
.global stb_d
stb_d:
stb fp,@(0,fp)
.text
.global stb_d2
stb_d2:
stb fp,@(fp,0)
.text
.global sth
sth:
sth fp,@fp
.text
.global sth_2
sth_2:
sth fp,@(fp)
.text
.global sth_d
sth_d:
sth fp,@(0,fp)
.text
.global sth_d2
sth_d2:
sth fp,@(fp,0)
.text
.global st_plus
st_plus:
st fp,@+fp
.text
.global st_minus
st_minus:
st fp,@-fp
.text
.global sub
sub:
sub fp,fp
.text
.global subv
subv:
subv fp,fp
.text
.global subx
subx:
subx fp,fp
.text
.global trap
trap:
trap 0
.text
.global unlock
unlock:
unlock fp,@fp
.text
.global push
push:
push fp
.text
.global pop
pop:
pop fp
/pic.exp
0,0 → 1,6
# M32R PIC testcases
 
if [istarget m32r*-*-*] {
run_dump_test "pic"
run_dump_test "pic2"
}
/m32rx.exp
0,0 → 1,7
# M32Rx assembler testsuite.
 
if [istarget m32r*-*-*] {
run_dump_test "m32rx"
run_dump_test "fslotx"
run_dump_test "relax-2"
}
/high-1.s
0,0 → 1,14
; Test high/shigh handling.
 
foo:
seth r4,#high(foo+0x10000)
or3 r4,r4,#low(foo+0x10000)
 
seth r4,#high(0x12348765)
or3 r4,r4,#low(0x12348765)
 
seth r4,#shigh(0x12348765)
or3 r4,r4,#low(0x12348765)
 
seth r4,#shigh(0x87654321)
or3 r4,r4,#low(0x87654321)
/m32r.exp
0,0 → 1,11
# M32R testcases
 
if [istarget m32r*-*-*] {
run_dump_test "high-1"
run_dump_test "relax-1"
run_dump_test "uppercase"
run_dump_test "fslot"
run_dump_test "signed-relocs"
run_dump_test "seth"
run_dump_test "rela-1"
}
/rel32-err.s
0,0 → 1,10
 
; { dg-do assemble { target m32r-*-* } }
 
.text
nop
nop
bar:
.section .text2
.2byte bar - . ; { dg-error "can't export reloc type 11" }
.byte bar - . ; { dg-error "can\'t export reloc type 7" }
/pic2.d
0,0 → 1,58
#objdump: -dr
#name: pic2
 
.*: +file format .*
 
Disassembly of section .text:
 
0+0000 <pic_gotpc>:
0: 7e 01 f0 00 bl 4 <pic_gotpc\+0x4> \|\| nop
4: ec 00 00 00 ld24 r12,0 <pic_gotpc>
4: R_M32R_GOTPC24 _GLOBAL_OFFSET_TABLE_
8: 0c ae f0 00 add r12,lr \|\| nop
 
0+000c <pic_gotpc_slo>:
c: 7e 01 f0 00 bl 10 <pic_gotpc_slo\+0x4> \|\| nop
10: dc c0 00 00 seth r12,[#]0x0
10: R_M32R_GOTPC_HI_SLO _GLOBAL_OFFSET_TABLE_
14: 8c ac 00 00 add3 r12,r12,[#]0
14: R_M32R_GOTPC_LO _GLOBAL_OFFSET_TABLE_\+0x4
18: 0c ae f0 00 add r12,lr \|\| nop
 
0+001c <pic_gotpc_ulo>:
1c: 7e 01 f0 00 bl 20 <pic_gotpc_ulo\+0x4> \|\| nop
20: dc c0 00 00 seth r12,[#]0x0
20: R_M32R_GOTPC_HI_ULO _GLOBAL_OFFSET_TABLE_
24: 8c ec 00 00 or3 r12,r12,[#]0x0
24: R_M32R_GOTPC_LO _GLOBAL_OFFSET_TABLE_\+0x4
28: 0c ae f0 00 add r12,lr \|\| nop
 
0+002c <pic_got>:
2c: e0 00 00 00 ld24 r0,0 <pic_gotpc>
2c: R_M32R_GOTOFF sym
 
0+0030 <pic_got16>:
30: dc c0 00 00 seth r12,[#]0x0
30: R_M32R_GOT16_HI_SLO sym2
34: 8c ac 00 00 add3 r12,r12,[#]0
34: R_M32R_GOT16_LO sym2
38: dc c0 00 00 seth r12,[#]0x0
38: R_M32R_GOTOFF_HI_ULO sym2
3c: 8c ec 00 00 or3 r12,r12,[#]0x0
3c: R_M32R_GOT16_LO sym2
 
0+0040 <pic_plt>:
40: fe 00 00 00 bl 40 <pic_plt>
40: R_M32R_26_PLTREL func
 
0+0044 <gotoff>:
44: e0 00 00 00 ld24 r0,0 <pic_gotpc>
44: R_M32R_GOTOFF .text\+0x44
48: d0 c0 00 00 seth r0,[#]0x0
48: R_M32R_GOTOFF_HI_SLO .text\+0x44
4c: 80 a0 00 00 add3 r0,r0,[#]0
4c: R_M32R_GOTOFF_LO .text\+0x44
50: d0 c0 00 00 seth r0,[#]0x0
50: R_M32R_GOTOFF_HI_ULO .text\+0x44
54: 80 e0 00 00 or3 r0,r0,[#]0x0
54: R_M32R_GOTOFF_LO .text\+0x44
/rel32.exp
0,0 → 1,6
# M32R R_M32R_REL32 testcases
 
if [istarget m32r*-*-*] {
run_dump_test "rel32"
run_dump_test "rel32-pic"
}
/rel32-pic.d
0,0 → 1,13
#as: -KPIC
#objdump: -r
#name: rel32-pic
 
.*: +file format .*
 
RELOCATION RECORDS FOR \[.text2\]:
OFFSET TYPE VALUE
00000000 R_M32R_REL32 .text\+0x00000004
00000008 R_M32R_REL32 .text\+0x00000008
0000000c R_M32R_REL32 .text
 
 
/seth.d
0,0 → 1,8
#objdump: -dr
 
.*: +file format .*
 
Disassembly of section .text:
 
0+000 <.text>:
0: d0 c0 00 00 seth r0,[#]0x0
/m32r2.d
0,0 → 1,92
#as: -m32r2
#objdump: -dr
#name: m32r2
 
.*: +file format .*
 
Disassembly of section .text:
 
0+0000 <setpsw>:
0: 71 c1 71 ff setpsw #0xc1 -> setpsw #0xff
 
0+0004 <clrpsw>:
4: 72 c1 72 ff clrpsw #0xc1 -> clrpsw #0xff
 
0+0008 <bset>:
8: a0 61 00 04 bset #0x0,@\(4,r1\)
c: a1 61 00 04 bset #0x1,@\(4,r1\)
10: a7 61 00 04 bset #0x7,@\(4,r1\)
 
0+0014 <bclr>:
14: a0 71 00 04 bclr #0x0,@\(4,r1\)
18: a1 71 00 04 bclr #0x1,@\(4,r1\)
1c: a7 71 00 04 bclr #0x7,@\(4,r1\)
 
0+0020 <btst>:
20: 00 fd 01 fd btst #0x0,fp -> btst #0x1,fp
24: 07 fd f0 00 btst #0x7,fp \|\| nop
28: 01 fd 90 82 btst #0x1,fp \|\| mv r0,r2
2c: 01 fd 90 82 btst #0x1,fp \|\| mv r0,r2
 
0+0030 <divuh>:
30: 9d 1d 00 10 divuh fp,fp
 
0+0034 <divb>:
34: 9d 0d 00 18 divb fp,fp
 
0+0038 <divub>:
38: 9d 1d 00 18 divub fp,fp
 
0+003c <remh>:
3c: 9d 2d 00 10 remh fp,fp
 
0+0040 <remuh>:
40: 9d 3d 00 10 remuh fp,fp
 
0+0044 <remb>:
44: 9d 2d 00 18 remb fp,fp
 
0+0048 <remub>:
48: 9d 3d 00 18 remub fp,fp
 
0+004c <sll>:
4c: 10 41 92 43 sll r0,r1 \|\| sll r2,r3
50: 12 43 90 61 sll r2,r3 \|\| mul r0,r1
54: 10 41 92 63 sll r0,r1 \|\| mul r2,r3
58: 60 01 92 43 ldi r0,#1 \|\| sll r2,r3
5c: 10 41 e2 01 sll r0,r1 \|\| ldi r2,#1
 
0+0060 <slli>:
60: 50 41 d2 5f slli r0,#0x1 \|\| slli r2,#0x1f
64: 52 5f 90 61 slli r2,#0x1f \|\| mul r0,r1
68: 50 41 92 63 slli r0,#0x1 \|\| mul r2,r3
6c: 60 01 d2 5f ldi r0,#1 \|\| slli r2,#0x1f
70: 50 41 e2 01 slli r0,#0x1 \|\| ldi r2,#1
 
0+0074 <sra>:
74: 10 21 92 23 sra r0,r1 \|\| sra r2,r3
78: 12 23 90 61 sra r2,r3 \|\| mul r0,r1
7c: 10 21 92 63 sra r0,r1 \|\| mul r2,r3
80: 60 01 92 23 ldi r0,#1 \|\| sra r2,r3
84: 10 21 e2 01 sra r0,r1 \|\| ldi r2,#1
 
0+0088 <srai>:
88: 50 21 d2 3f srai r0,#0x1 \|\| srai r2,#0x1f
8c: 52 3f 90 61 srai r2,#0x1f \|\| mul r0,r1
90: 50 21 92 63 srai r0,#0x1 \|\| mul r2,r3
94: 60 01 d2 3f ldi r0,#1 \|\| srai r2,#0x1f
98: 50 21 e2 01 srai r0,#0x1 \|\| ldi r2,#1
 
0+009c <srl>:
9c: 10 01 92 03 srl r0,r1 \|\| srl r2,r3
a0: 12 03 90 61 srl r2,r3 \|\| mul r0,r1
a4: 10 01 92 63 srl r0,r1 \|\| mul r2,r3
a8: 60 01 92 03 ldi r0,#1 \|\| srl r2,r3
ac: 10 01 e2 01 srl r0,r1 \|\| ldi r2,#1
 
0+00b0 <srli>:
b0: 50 01 d2 1f srli r0,#0x1 \|\| srli r2,#0x1f
b4: 52 1f 90 61 srli r2,#0x1f \|\| mul r0,r1
b8: 50 01 92 63 srli r0,#0x1 \|\| mul r2,r3
bc: 60 01 d2 1f ldi r0,#1 \|\| srli r2,#0x1f
c0: 50 01 e2 01 srli r0,#0x1 \|\| ldi r2,#1
/wrongsize.s
0,0 → 1,10
; Test error messages in instances where an insn of a particular size
; is required.
 
; { dg-do assemble { target m32r-*-* } }
 
wrongsize:
cmpi r8,#10 -> ldi r0,#8 ; { dg-error "not a 16 bit instruction" }
ldi r0,#8 -> cmpi r8,#10 ; { dg-error "not a 16 bit instruction" }
cmpi r8,#10 || ldi r0,#8 ; { dg-error "not a 16 bit instruction" }
ldi r0,#8 || cmpi r8,#10 ; { dg-error "not a 16 bit instruction" }
/allinsn.exp
0,0 → 1,5
# M32R assembler testsuite.
 
if [istarget m32r*-*-*] {
run_dump_test "allinsn"
}
/relax-1.d
0,0 → 1,18
#as:
#objdump: -dr
#name: relax-1
 
.*: +file format .*
 
Disassembly of section .text:
 
0* <DoesNotWork>:
*0: 70 00 70 00 * nop -> nop
 
0*4 <Work>:
*4: 70 00 70 00 * nop -> nop
Disassembly of section .branch:
 
0* <branch>:
*0: ff 00 00 00 bra 0 <branch>
[ ]*0: R_M32R_26_PCREL_RELA .text\+0x4
/relax-2.d
0,0 → 1,18
#as: --m32rx
#objdump: -dr
#name: relax-2
 
.*: +file format .*
 
Disassembly of section .text:
 
0+0 <label1>:
0: fd 00 00 83 bnc 20c <label3>
4: 70 00 f0 00 nop \|\| nop
8: 43 03 c2 02 addi r3,[#]3 \|\| addi r2,[#]2
 
0+0c <label2>:
...
 
0+020c <label3>:
20c: 70 00 f0 00 nop \|\| nop
/pic.d
0,0 → 1,47
#as: -K PIC
#objdump: -dr
#name: pic
 
.*: +file format .*
 
Disassembly of section .text:
 
0+0000 <pic_gotpc>:
0: 7e 01 f0 00 bl 4 <pic_gotpc\+0x4> \|\| nop
4: ec 00 00 00 ld24 r12,0 <pic_gotpc>
4: R_M32R_GOTPC24 _GLOBAL_OFFSET_TABLE_
8: 0c ae f0 00 add r12,lr \|\| nop
 
0+000c <pic_gotpc_slo>:
c: 7e 01 f0 00 bl 10 <pic_gotpc_slo\+0x4> \|\| nop
10: dc c0 00 00 seth r12,[#]0x0
10: R_M32R_GOTPC_HI_SLO _GLOBAL_OFFSET_TABLE_
14: 8c ac 00 00 add3 r12,r12,[#]0
14: R_M32R_GOTPC_LO _GLOBAL_OFFSET_TABLE_\+0x4
18: 0c ae f0 00 add r12,lr \|\| nop
 
0+001c <pic_gotpc_ulo>:
1c: 7e 01 f0 00 bl 20 <pic_gotpc_ulo\+0x4> \|\| nop
20: dc c0 00 00 seth r12,[#]0x0
20: R_M32R_GOTPC_HI_ULO _GLOBAL_OFFSET_TABLE_
24: 8c ec 00 00 or3 r12,r12,[#]0x0
24: R_M32R_GOTPC_LO _GLOBAL_OFFSET_TABLE_\+0x4
28: 0c ae f0 00 add r12,lr \|\| nop
 
0+002c <pic_got>:
2c: e0 00 00 00 ld24 r0,0 <pic_gotpc>
2c: R_M32R_GOT24 sym
 
0+0030 <pic_got16>:
30: dc c0 00 00 seth r12,[#]0x0
30: R_M32R_GOT16_HI_SLO sym2
34: 8c ac 00 00 add3 r12,r12,[#]0
34: R_M32R_GOT16_LO sym2\+0x4
38: dc c0 00 00 seth r12,[#]0x0
38: R_M32R_GOT16_HI_ULO sym2
3c: 8c ec 00 00 or3 r12,r12,[#]0x0
3c: R_M32R_GOT16_LO sym2\+0x4
 
0+0040 <pic_plt>:
40: fe 00 00 00 bl 40 <pic_plt>
40: R_M32R_26_PLTREL func
/m32rx.d
0,0 → 1,349
#as: -m32rx --no-warn-explicit-parallel-conflicts --hidden -O
#objdump: -dr
#name: m32rx
 
.*: +file format .*
 
Disassembly of section .text:
 
0+0000 <bcl>:
0: 78 00 f0 00 bcl 0 <bcl> \|\| nop
 
0+0004 <bncl>:
4: 79 ff f0 00 bncl 0 <bcl> \|\| nop
 
0+0008 <cmpz>:
8: 00 7d f0 00 cmpz fp \|\| nop
 
0+000c <cmpeq>:
c: 0d 6d f0 00 cmpeq fp,fp \|\| nop
 
0+0010 <maclh1>:
10: 5d cd f0 00 maclh1 fp,fp \|\| nop
 
0+0014 <msblo>:
14: 5d dd f0 00 msblo fp,fp \|\| nop
 
0+0018 <mulwu1>:
18: 5d ad f0 00 mulwu1 fp,fp \|\| nop
 
0+001c <macwu1>:
1c: 5d bd f0 00 macwu1 fp,fp \|\| nop
 
0+0020 <sadd>:
20: 50 e4 f0 00 sadd \|\| nop
 
0+0024 <satb>:
24: 8d 6d 03 00 satb fp,fp
 
0+0028 <mulhi>:
28: 3d 8d f0 00 mulhi fp,fp,a1 \|\| nop
 
0+002c <mullo>:
2c: 3d 1d f0 00 mullo fp,fp \|\| nop
 
0+0030 <divh>:
30: 9d 0d 00 10 divh fp,fp
 
0+0034 <machi>:
34: 3d cd f0 00 machi fp,fp,a1 \|\| nop
 
0+0038 <maclo>:
38: 3d 5d f0 00 maclo fp,fp \|\| nop
 
0+003c <mvfachi>:
3c: 5d f4 f0 00 mvfachi fp,a1 \|\| nop
 
0+0040 <mvfacmi>:
40: 5d f6 f0 00 mvfacmi fp,a1 \|\| nop
 
0+0044 <mvfaclo>:
44: 5d f5 f0 00 mvfaclo fp,a1 \|\| nop
 
0+0048 <mvtachi>:
48: 5d 74 f0 00 mvtachi fp,a1 \|\| nop
 
0+004c <mvtaclo>:
4c: 5d 71 f0 00 mvtaclo fp \|\| nop
 
0+0050 <rac>:
50: 54 90 f0 00 rac a1 \|\| nop
 
0+0054 <rac_ds>:
54: 54 90 f0 00 rac a1 \|\| nop
 
0+0058 <rac_dsi>:
58: 50 94 f0 00 rac a0,a1 \|\| nop
 
0+005c <rach>:
5c: 54 80 f0 00 rach a1 \|\| nop
 
0+0060 <rach_ds>:
60: 50 84 f0 00 rach a0,a1 \|\| nop
 
0+0064 <rach_dsi>:
64: 54 81 f0 00 rach a1,a0,#0x2 \|\| nop
 
0+0068 <bc__add>:
68: 7c 00 8d ad bc 68 <bc__add> \|\| add fp,fp
68: R_M32R_10_PCREL_RELA bcl
6c: 7c 00 0d ad bc 6c <bc__add\+0x4> -> add fp,fp
6c: R_M32R_10_PCREL_RELA bcl
 
0+0070 <bcl__addi>:
70: 78 00 cd 4d bcl 70 <bcl__addi> \|\| addi fp,#77
70: R_M32R_10_PCREL_RELA bcl
74: 78 00 cd 4d bcl 74 <bcl__addi\+0x4> \|\| addi fp,#77
74: R_M32R_10_PCREL_RELA bcl
 
0+0078 <bl__addv>:
78: 7e 00 8d 8d bl 78 <bl__addv> \|\| addv fp,fp
78: R_M32R_10_PCREL_RELA bcl
7c: 7e 00 8d 8d bl 7c <bl__addv\+0x4> \|\| addv fp,fp
7c: R_M32R_10_PCREL_RELA bcl
 
0+0080 <bnc__addx>:
80: 7d 00 8d 9d bnc 80 <bnc__addx> \|\| addx fp,fp
80: R_M32R_10_PCREL_RELA bcl
84: 7d 00 0d 9d bnc 84 <bnc__addx\+0x4> -> addx fp,fp
84: R_M32R_10_PCREL_RELA bcl
 
0+0088 <bncl__and>:
88: 79 00 8d cd bncl 88 <bncl__and> \|\| and fp,fp
88: R_M32R_10_PCREL_RELA bcl
8c: 79 00 8d cd bncl 8c <bncl__and\+0x4> \|\| and fp,fp
8c: R_M32R_10_PCREL_RELA bcl
 
0+0090 <bra__cmp>:
90: 7f 00 8d 4d bra 90 <bra__cmp> \|\| cmp fp,fp
90: R_M32R_10_PCREL_RELA bcl
94: 7f 00 8d 4d bra 94 <bra__cmp\+0x4> \|\| cmp fp,fp
94: R_M32R_10_PCREL_RELA bcl
 
0+0098 <jl__cmpeq>:
98: 1e cd 8d 6d jl fp \|\| cmpeq fp,fp
9c: 1e cd 8d 6d jl fp \|\| cmpeq fp,fp
 
0+00a0 <jmp__cmpu>:
a0: 1f cd 8d 5d jmp fp \|\| cmpu fp,fp
a4: 1f cd 8d 5d jmp fp \|\| cmpu fp,fp
 
0+00a8 <ld__cmpz>:
a8: 2d cd 80 71 ld fp,@fp \|\| cmpz r1
ac: 2d cd 80 71 ld fp,@fp \|\| cmpz r1
 
0+00b0 <ld__ldi>:
b0: 2d e1 e2 4d ld fp,@r1\+ \|\| ldi r2,#77
b4: 2d e1 e2 4d ld fp,@r1\+ \|\| ldi r2,#77
 
0+00b8 <ldb__mv>:
b8: 2d 8d 92 8d ldb fp,@fp \|\| mv r2,fp
bc: 2d 8d 12 8d ldb fp,@fp -> mv r2,fp
 
0+00c0 <ldh__neg>:
c0: 2d ad 82 3d ldh fp,@fp \|\| neg r2,fp
c4: 2d ad 02 3d ldh fp,@fp -> neg r2,fp
 
0+00c8 <ldub__nop>:
c8: 2d 9d f0 00 ldub fp,@fp \|\| nop
cc: 2d 9d f0 00 ldub fp,@fp \|\| nop
 
0+00d0 <lduh__not>:
d0: 2d bd 82 bd lduh fp,@fp \|\| not r2,fp
d4: 2d bd 02 bd lduh fp,@fp -> not r2,fp
 
0+00d8 <lock__or>:
d8: 2d dd 82 ed lock fp,@fp \|\| or r2,fp
dc: 2d dd 02 ed lock fp,@fp -> or r2,fp
 
0+00e0 <mvfc__sub>:
e0: 1d 91 82 2d mvfc fp,cbr \|\| sub r2,fp
e4: 1d 91 02 2d mvfc fp,cbr -> sub r2,fp
 
0+00e8 <mvtc__subv>:
e8: 12 ad 82 0d mvtc fp,spi \|\| subv r2,fp
ec: 12 ad 82 0d mvtc fp,spi \|\| subv r2,fp
 
0+00f0 <rte__subx>:
f0: 10 d6 82 2d rte \|\| sub r2,fp
f4: 10 d6 02 1d rte -> subx r2,fp
 
0+00f8 <sll__xor>:
f8: 1d 41 82 dd sll fp,r1 \|\| xor r2,fp
fc: 1d 41 02 dd sll fp,r1 -> xor r2,fp
 
0+0100 <slli__machi>:
100: 5d 56 b2 4d slli fp,#0x16 \|\| machi r2,fp
104: 5d 56 32 4d slli fp,#0x16 -> machi r2,fp
 
0+0108 <sra__maclh1>:
108: 1d 2d d2 cd sra fp,fp \|\| maclh1 r2,fp
10c: 1d 2d 52 cd sra fp,fp -> maclh1 r2,fp
 
0+0110 <srai__maclo>:
110: 5d 36 b2 5d srai fp,#0x16 \|\| maclo r2,fp
114: 5d 36 32 5d srai fp,#0x16 -> maclo r2,fp
 
0+0118 <srl__macwhi>:
118: 1d 0d b2 6d srl fp,fp \|\| macwhi r2,fp
11c: 1d 0d 32 6d srl fp,fp -> macwhi r2,fp
 
0+0120 <srli__macwlo>:
120: 5d 16 b2 7d srli fp,#0x16 \|\| macwlo r2,fp
124: 5d 16 32 7d srli fp,#0x16 -> macwlo r2,fp
 
0+0128 <st__macwu1>:
128: 2d 4d d2 bd st fp,@fp \|\| macwu1 r2,fp
12c: 2d 4d d2 bd st fp,@fp \|\| macwu1 r2,fp
 
0+0130 <st__msblo>:
130: 2d 6d d2 dd st fp,@\+fp \|\| msblo r2,fp
134: 2d 6d 52 dd st fp,@\+fp -> msblo r2,fp
 
0+0138 <st__mul>:
138: 2d 7d 92 6d st fp,@-fp \|\| mul r2,fp
13c: 2d 7d 12 6d st fp,@-fp -> mul r2,fp
 
0+0140 <stb__mulhi>:
140: 2d 0d b2 0d stb fp,@fp \|\| mulhi r2,fp
144: 2d 0d b2 0d stb fp,@fp \|\| mulhi r2,fp
 
0+0148 <sth__mullo>:
148: 2d 2d b2 1d sth fp,@fp \|\| mullo r2,fp
14c: 2d 2d b2 1d sth fp,@fp \|\| mullo r2,fp
 
0+0150 <trap__mulwhi>:
150: 10 f2 b2 2d trap #0x2 \|\| mulwhi r2,fp
154: 10 f2 f0 00 trap #0x2 \|\| nop
158: 32 2d f0 00 mulwhi r2,fp \|\| nop
 
0+015c <unlock__mulwlo>:
15c: 2d 5d b2 3d unlock fp,@fp \|\| mulwlo r2,fp
160: 2d 5d b2 3d unlock fp,@fp \|\| mulwlo r2,fp
 
0+0164 <add__mulwu1>:
164: 0d ad d2 ad add fp,fp \|\| mulwu1 r2,fp
168: 0d ad 52 ad add fp,fp -> mulwu1 r2,fp
 
0+016c <addi__mvfachi>:
16c: 4d 4d d2 f0 addi fp,#77 \|\| mvfachi r2
170: 4d 4d d2 f0 addi fp,#77 \|\| mvfachi r2
 
0+0174 <addv__mvfaclo>:
174: 0d 8d d2 f5 addv fp,fp \|\| mvfaclo r2,a1
178: 0d 8d d2 f5 addv fp,fp \|\| mvfaclo r2,a1
 
0+017c <addx__mvfacmi>:
17c: 0d 9d d2 f2 addx fp,fp \|\| mvfacmi r2
180: 0d 9d d2 f2 addx fp,fp \|\| mvfacmi r2
 
0+0184 <and__mvtachi>:
184: 0d cd d2 70 and fp,fp \|\| mvtachi r2
188: 0d cd d2 70 and fp,fp \|\| mvtachi r2
 
0+018c <cmp__mvtaclo>:
18c: 0d 4d d2 71 cmp fp,fp \|\| mvtaclo r2
190: 0d 4d d2 71 cmp fp,fp \|\| mvtaclo r2
 
0+0194 <cmpeq__rac>:
194: 0d 6d d4 90 cmpeq fp,fp \|\| rac a1
198: 0d 6d d4 90 cmpeq fp,fp \|\| rac a1
 
0+019c <cmpu__rach>:
19c: 0d 5d d0 84 cmpu fp,fp \|\| rach a0,a1
1a0: 0d 5d d4 84 cmpu fp,fp \|\| rach a1,a1
 
0+01a4 <cmpz__sadd>:
1a4: 00 7d d0 e4 cmpz fp \|\| sadd
1a8: 00 7d d0 e4 cmpz fp \|\| sadd
 
0+01ac <sc>:
1ac: 74 01 d0 e4 sc \|\| sadd
 
0+01b0 <snc>:
1b0: 75 01 d0 e4 snc \|\| sadd
 
0+01b4 <jc>:
1b4: 1c cd f0 00 jc fp \|\| nop
 
0+01b8 <jnc>:
1b8: 1d cd f0 00 jnc fp \|\| nop
 
0+01bc <pcmpbz>:
1bc: 03 7d f0 00 pcmpbz fp \|\| nop
 
0+01c0 <sat>:
1c0: 8d 6d 00 00 sat fp,fp
 
0+01c4 <sath>:
1c4: 8d 6d 02 00 sath fp,fp
 
0+01c8 <jc__pcmpbz>:
1c8: 1c cd 83 7d jc fp \|\| pcmpbz fp
1cc: 1c cd 03 7d jc fp -> pcmpbz fp
 
0+01d0 <jnc__ldi>:
1d0: 1d cd ed 4d jnc fp \|\| ldi fp,#77
1d4: 1d cd 6d 4d jnc fp -> ldi fp,#77
 
0+01d8 <sc__mv>:
1d8: 74 01 9d 82 sc \|\| mv fp,r2
1dc: 74 01 9d 82 sc \|\| mv fp,r2
 
0+01e0 <snc__neg>:
1e0: 75 01 8d 32 snc \|\| neg fp,r2
1e4: 75 01 8d 32 snc \|\| neg fp,r2
 
0+01e8 <nop__sadd>:
1e8: 70 00 d0 e4 nop \|\| sadd
 
0+01ec <sadd__nop>:
1ec: 70 00 d0 e4 nop \|\| sadd
 
0+01f0 <sadd__nop_reverse>:
1f0: 70 00 d0 e4 nop \|\| sadd
 
0+01f4 <add__not>:
1f4: 00 a1 83 b5 add r0,r1 \|\| not r3,r5
 
0+01f8 <add__not_dest_clash>:
1f8: 03 a4 03 b5 add r3,r4 -> not r3,r5
 
0+01fc <add__not__src_clash>:
1fc: 03 a4 05 b3 add r3,r4 -> not r5,r3
 
0+0200 <add__not__no_clash>:
200: 03 a4 84 b5 add r3,r4 \|\| not r4,r5
 
0+0204 <mul__sra>:
204: 13 24 91 62 sra r3,r4 \|\| mul r1,r2
 
0+0208 <mul__sra__reverse_src_clash>:
208: 13 24 91 63 sra r3,r4 \|\| mul r1,r3
 
0+020c <bc__add_>:
20c: 7c 04 01 a2 bc 21c <label> -> add r1,r2
 
0+0210 <add__bc>:
210: 7c 03 83 a4 bc 21c <label> \|\| add r3,r4
 
0+0214 <bc__add__forced_parallel>:
214: 7c 02 85 a6 bc 21c <label> \|\| add r5,r6
 
0+0218 <add__bc__forced_parallel>:
218: 7c 01 87 a8 bc 21c <label> \|\| add r7,r8
 
0+021c <label>:
21c: 70 00 f0 00 nop \|\| nop
 
0+0220 <mulwhi>:
220: 3d 2d 3d ad mulwhi fp,fp -> mulwhi fp,fp,a1
 
0+0224 <mulwlo>:
224: 3d 3d 3d bd mulwlo fp,fp -> mulwlo fp,fp,a1
 
0+0228 <macwhi>:
228: 3d 6d 3d ed macwhi fp,fp -> macwhi fp,fp,a1
 
0+022c <macwlo>:
22c: 3d 7d 3d fd macwlo fp,fp -> macwlo fp,fp,a1
/pic2.s
0,0 → 1,55
.section .text
# R_M32R_GOTPC24
pic_gotpc:
bl.s .+4
ld24 r12,#_GLOBAL_OFFSET_TABLE_
add r12,lr
 
# R_M32R_GOTPC_HI_ULO
# R_M32R_GOTPC_HI_SLO
# R_M32R_GOTPC_LO
pic_gotpc_slo:
bl.s .+4
seth r12,#shigh(_GLOBAL_OFFSET_TABLE_)
add3 r12,r12,#low(_GLOBAL_OFFSET_TABLE_+4)
add r12,lr
 
pic_gotpc_ulo:
bl.s .+4
seth r12,#high(_GLOBAL_OFFSET_TABLE_)
or3 r12,r12,#low(_GLOBAL_OFFSET_TABLE_+4)
add r12,lr
 
# R_M32R_GOT24
pic_got:
.global sym
ld24 r0,#sym@GOTOFF
 
# R_M32R_GOT16_HI_ULO
# R_M32R_GOT16_HI_SLO
# R_M32R_GOT16_LO
pic_got16:
.global sym2
seth r12,#shigh(sym2@GOT)
add3 r12,r12,#low(sym2@GOT)
seth r12,#high(sym2@GOTOFF)
or3 r12,r12,#low(sym2@GOT)
 
# R_M32R_26_PLTREL
pic_plt:
.global func
bl func@PLT
 
# R_M32R_GOTOFF
gotoff:
ld24 r0,#gotoff@GOTOFF
 
# R_M32R_GOTOFF_HI_ULO
# R_M32R_GOTOFF_HI_SLO
# R_M32R_GOTOFF_LO
seth r0,#shigh(gotoff@GOTOFF)
add3 r0,r0,#low(gotoff@GOTOFF)
seth r0,#high(gotoff@GOTOFF)
or3 r0,r0,#low(gotoff@GOTOFF)
 
.end
/fslotx.d
0,0 → 1,23
#as: -m32rx
#objdump: -dr
#name: fslotx
 
.*: +file format .*
 
Disassembly of section .text:
 
0+0 <bcl>:
*0: 78 00 f0 00 bcl 0 <bcl> \|\| nop
*4: 60 08 f0 00 ldi r0,[#]*8 \|\| nop
 
0+8 <bcl_s>:
*8: 78 00 f0 00 bcl 8 <bcl_s> \|\| nop
*c: 60 08 f0 00 ldi r0,[#]*8 \|\| nop
 
0+10 <bncl>:
10: 79 00 f0 00 bncl 10 <bncl> \|\| nop
14: 60 08 f0 00 ldi r0,[#]*8 \|\| nop
 
0+18 <bncl_s>:
18: 79 00 f0 00 bncl 18 <bncl_s> \|\| nop
1c: 60 08 f0 00 ldi r0,[#]*8 \|\| nop
/rel32-pic.s
0,0 → 1,12
.text
nop
nop
bar:
.section .text2
.4byte bar - .
label:
nop
nop
.4byte bar - label
.4byte bar - label2
label2:
/rela-1.d
0,0 → 1,24
#as:
#objdump: -dr
#name: rela-1
 
.*: +file format .*
 
Disassembly of section .text:
 
0+0000 <.text>:
0: fe 00 00 00 bl 0 <.text>
0: R_M32R_26_PCREL_RELA .text2\+0x8
4: fe 00 00 00 bl 4 <.text\+0x4>
4: R_M32R_26_PCREL_RELA .text2\+0x8
8: 7e 00 f0 00 bl 8 <.text\+0x8> \|\| nop
8: R_M32R_10_PCREL_RELA .text2\+0x8
c: b0 90 00 00 bnez r0,c <.text\+0xc>
c: R_M32R_18_PCREL_RELA .text2\+0x8
10: 10 80 7e 00 mv r0,r0 -> bl 10 <.text\+0x10>
12: R_M32R_10_PCREL_RELA .text2\+0x8
Disassembly of section .text2:
 
0+0000 <label-0x8>:
0: 70 00 70 00 nop -> nop
4: 70 00 70 00 nop -> nop
/seth.s
0,0 → 1,3
.text
seth r0, #shigh(0xffff8000)
.end
/m32r2.s
0,0 → 1,126
# Test new instructions
.text
.global setpsw
setpsw:
setpsw 0xc1
setpsw 0xff
 
.text
.global clrpsw
clrpsw:
clrpsw 0xc1
clrpsw 0xff
 
.text
.global bset
bset:
bset #0,@(4,r1)
bset #1,@(4,r1)
bset #7,@(4,r1)
 
.text
.global bclr
bclr:
bclr #0,@(4,r1)
bclr #1,@(4,r1)
bclr #7,@(4,r1)
 
.text
.global btst
btst:
btst #0,fp
btst #1,fp
btst #7,fp
btst #1,fp || mv r0,r2
mv r0,r2 || btst #1,fp
 
.text
.global divuh
divuh:
divuh fp,fp
 
.text
.global divb
divb:
divb fp,fp
.text
.global divub
divub:
divub fp,fp
.text
.global remh
remh:
remh fp,fp
.text
.global remuh
remuh:
remuh fp,fp
.text
.global remb
remb:
remb fp,fp
.text
.global remub
remub:
remub fp,fp
.text
.global sll
sll:
sll r0,r1 || sll r2,r3
mul r0,r1 || sll r2,r3
sll r0,r1 || mul r2,r3
ldi r0,#1 || sll r2,r3
sll r0,r1 || ldi r2,#1
 
.text
.global slli
slli:
slli r0,#1 || slli r2,#31
mul r0,r1 || slli r2,#31
slli r0,#1 || mul r2,r3
ldi r0,#1 || slli r2,#31
slli r0,#1 || ldi r2,#1
 
.text
.global sra
sra:
sra r0,r1 || sra r2,r3
mul r0,r1 || sra r2,r3
sra r0,r1 || mul r2,r3
ldi r0,#1 || sra r2,r3
sra r0,r1 || ldi r2,#1
 
.text
.global srai
srai:
srai r0,#1 || srai r2,#31
mul r0,r1 || srai r2,#31
srai r0,#1 || mul r2,r3
ldi r0,#1 || srai r2,#31
srai r0,#1 || ldi r2,#1
 
.text
.global sra
srl:
srl r0,r1 || srl r2,r3
mul r0,r1 || srl r2,r3
srl r0,r1 || mul r2,r3
ldi r0,#1 || srl r2,r3
srl r0,r1 || ldi r2,#1
 
.text
.global srai
srli:
srli r0,#1 || srli r2,#31
mul r0,r1 || srli r2,#31
srli r0,#1 || mul r2,r3
ldi r0,#1 || srli r2,#31
srli r0,#1 || ldi r2,#1
 
/fslot.d
0,0 → 1,31
#as:
#objdump: -dr
#name: fslot
 
.*: +file format .*
 
Disassembly of section .text:
 
0+0 <bl>:
*0: 7e 00 f0 00 bl 0 <bl> \|\| nop
*4: 60 08 f0 00 ldi r0,[#]*8 \|\| nop
 
0+8 <bl_s>:
*8: 7e 00 f0 00 bl 8 <bl_s> \|\| nop
*c: 60 08 f0 00 ldi r0,[#]*8 \|\| nop
 
0+10 <bra>:
*10: 7f 00 f0 00 bra 10 <bra> \|\| nop
*14: 60 08 f0 00 ldi r0,[#]*8 \|\| nop
 
0+18 <bra_s>:
*18: 7f 00 f0 00 bra 18 <bra_s> \|\| nop
*1c: 60 08 f0 00 ldi r0,[#]*8 \|\| nop
 
0+20 <jl>:
*20: 1e c0 f0 00 jl r0 \|\| nop
*24: 60 08 f0 00 ldi r0,[#]*8 \|\| nop
 
0+28 <trap>:
*28: 10 f4 f0 00 trap [#]*0x4 \|\| nop
*2c: 60 08 f0 00 ldi r0,[#]*8 \|\| nop
/uppercase.d
0,0 → 1,26
#as:
#objdump: -dr
#name: uppercase
 
.*: +file format .*
 
Disassembly of section .text:
 
0+0000 <foo>:
0: 10 81 10 91 * mv r0,r1 -> mvfc r0,cbr
 
0+0004 <high>:
4: d0 c0 00 00 seth r0,#0x0
[ ]*4: R_M32R_HI16_ULO_RELA [.]text\+0x4
 
0+0008 <shigh>:
8: d0 c0 00 00 seth r0,#0x0
[ ]*8: R_M32R_HI16_SLO_RELA [.]text\+0x8
 
0+000c <low>:
c: 80 e0 00 00 or3 r0,r0,#0x0
[ ]*c: R_M32R_LO16_RELA [.]text\+0xc
 
0+0010 <sda>:
10: 80 a0 00 00 add3 r0,r0,#0
[ ]*10: R_M32R_SDA16_RELA sdavar
/rel32.d
0,0 → 1,13
#as:
#objdump: -r
#name: rel32
 
.*: +file format .*
 
RELOCATION RECORDS FOR \[.text2\]:
OFFSET TYPE VALUE
00000000 R_M32R_REL32 .text\+0x00000004
00000008 R_M32R_REL32 .text\+0x00000008
0000000c R_M32R_REL32 .text
 
 
/relax-1.s
0,0 → 1,17
; Test relaxation into non-zero offset to different segment.
 
.section .branch, "ax",@progbits
.balign 4
branch:
bra Work
 
 
.section .text
.balign 4
DoesNotWork:
nop
nop
 
Work:
nop
nop
/outofrange.s
0,0 → 1,145
; Test error messages where branches are out of range.
 
; { dg-do assemble { target m32r-*-* } }
 
.text
.global foo
foo:
bl.s label
; { dg-error "out of range" "out of range bl.s" { target *-*-* } { 8 } }
bnc.s label
; { dg-error "out of range" "out of range bnc.s" { target *-*-* } { 10 } }
bra.s label
; { dg-error "out of range" "out of range bra.s" { target *-*-* } { 12 } }
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
ld24 r0,#0
label:
jmp r14
/relax-2.s
0,0 → 1,11
; Test whether parallel insns get inappropriately moved during relaxation.
 
.text
label1:
bnc label3
nop
addi r3, #3 || addi r2, #2
label2:
.space 512
label3:
nop
/m32rx.s
0,0 → 1,590
# Test new instructions
branchpoint:
.text
.global bcl
bcl:
bcl branchpoint
 
.text
.global bncl
bncl:
bncl branchpoint
 
.text
.global cmpz
cmpz:
cmpz fp
 
.text
.global cmpeq
cmpeq:
cmpeq fp, fp
 
.text
.global maclh1
maclh1:
maclh1 fp, fp
.text
.global macsl0
msblo:
msblo fp, fp
.text
.global mulwu1
mulwu1:
mulwu1 fp, fp
.text
.global macwu1
macwu1:
macwu1 fp, fp
.text
.global sadd
sadd:
sadd
.text
.global satb
satb:
satb fp, fp
 
.text
.global mulhi
mulhi:
mulhi fp, fp, a1
.text
.global mullo
mullo:
mullo fp, fp, a0
.text
.global divh
divh:
divh fp, fp
.text
.global machi
machi:
machi fp, fp, a1
.text
.global maclo
maclo:
maclo fp, fp, a0
.text
.global mvfachi
mvfachi:
mvfachi fp, a1
.text
.global mvfacmi
mvfacmi:
mvfacmi fp, a1
.text
.global mvfaclo
mvfaclo:
mvfaclo fp, a1
.text
.global mvtachi
mvtachi:
mvtachi fp, a1
.text
.global mvtaclo
mvtaclo:
mvtaclo fp, a0
.text
.global rac
rac:
rac a1
.text
.global rac_ds
rac_ds:
rac a1, a0
.text
.global rac_dsi
rac_dsi:
rac a0, a1, #1
.text
.global rach
rach:
rach a1
.text
.global rach_ds
rach_ds:
rach a0, a1
.text
.global rach_dsi
rach_dsi:
rach a1, a0, #2
# Test explicitly parallel and implicitly parallel instructions
# Including apparent instruction sequence reordering.
.text
.global bc__add
bc__add:
bc bcl || add fp, fp
# Use bc.s here as bc is relaxable and thus a nop will be emitted.
bc.s bcl
add fp, fp
 
.text
.global bcl__addi
bcl__addi:
bcl bcl || addi fp, #77
addi fp, #77
# Use bcl.s here as bcl is relaxable and thus the parallelization won't happen.
bcl.s bcl
 
.text
.global bl__addv
bl__addv:
bl bcl || addv fp, fp
addv fp, fp
# Use bl.s here as bl is relaxable and thus the parallelization won't happen.
bl.s bcl
.text
.global bnc__addx
bnc__addx:
bnc bcl || addx fp, fp
# Use bnc.s here as bnc is relaxable and thus the parallelization attempt won't
# happen. Things still won't be parallelized, but we want this test to try.
bnc.s bcl
addx fp, fp
 
.text
.global bncl__and
bncl__and:
bncl bcl || and fp, fp
and fp, fp
bncl.s bcl
 
.text
.global bra__cmp
bra__cmp:
bra bcl || cmp fp, fp
cmp fp, fp
# Use bra.s here as bra is relaxable and thus the parallelization won't happen.
bra.s bcl
.text
.global jl__cmpeq
jl__cmpeq:
jl fp || cmpeq fp, fp
cmpeq fp, fp
jl fp
.text
.global jmp__cmpu
jmp__cmpu:
jmp fp || cmpu fp, fp
cmpu fp, fp
jmp fp
.text
.global ld__cmpz
ld__cmpz:
ld fp, @fp || cmpz r1
cmpz r1
ld fp, @fp
.text
.global ld__ldi
ld__ldi:
ld fp, @r1+ || ldi r2, #77
ld fp, @r1+
ldi r2, #77
.text
.global ldb__mv
ldb__mv:
ldb fp, @fp || mv r2, fp
ldb fp, @fp
mv r2, fp
 
.text
.global ldh__neg
ldh__neg:
ldh fp, @fp || neg r2, fp
ldh fp, @fp
neg r2, fp
 
.text
.global ldub__nop
ldub__nop:
ldub fp, @fp || nop
ldub fp, @fp
nop
 
.text
.global lduh__not
lduh__not:
lduh fp, @fp || not r2, fp
lduh fp, @fp
not r2, fp
 
.text
.global lock__or
lock__or:
lock fp, @fp || or r2, fp
lock fp, @fp
or r2, fp
 
.text
.global mvfc__sub
mvfc__sub:
mvfc fp, cr1 || sub r2, fp
mvfc fp, cr1
sub r2, fp
 
.text
.global mvtc__subv
mvtc__subv:
mvtc fp, cr2 || subv r2, fp
mvtc fp, cr2
subv r2, fp
 
.text
.global rte__subx
rte__subx:
rte || sub r2, fp
rte
subx r2, fp
 
.text
.global sll__xor
sll__xor:
sll fp, r1 || xor r2, fp
sll fp, r1
xor r2, fp
 
.text
.global slli__machi
slli__machi:
slli fp, #22 || machi r2, fp
slli fp, #22
machi r2, fp
 
.text
.global sra__maclh1
sra__maclh1:
sra fp, fp || maclh1 r2, fp
sra fp, fp
maclh1 r2, fp
 
.text
.global srai__maclo
srai__maclo:
srai fp, #22 || maclo r2, fp
srai fp, #22
maclo r2, fp
 
.text
.global srl__macwhi
srl__macwhi:
srl fp, fp || macwhi r2, fp
srl fp, fp
macwhi r2, fp
 
.text
.global srli__macwlo
srli__macwlo:
srli fp, #22 || macwlo r2, fp
srli fp, #22
macwlo r2, fp
.text
.global st__macwu1
st__macwu1:
st fp, @fp || macwu1 r2, fp
st fp, @fp
macwu1 r2, fp
 
.text
.global st__msblo
st__msblo:
st fp, @+fp || msblo r2, fp
st fp, @+fp
msblo r2, fp
 
.text
.global st__mul
st__mul:
st fp, @-fp || mul r2, fp
st fp, @-fp
mul r2, fp
 
.text
.global stb__mulhi
stb__mulhi:
stb fp, @fp || mulhi r2, fp
stb fp, @fp
mulhi r2, fp
.text
.global sth__mullo
sth__mullo:
sth fp, @fp || mullo r2, fp
sth fp, @fp
mullo r2, fp
 
.text
.global trap__mulwhi
trap__mulwhi:
trap #2 || mulwhi r2, fp
trap #2
mulwhi r2, fp
 
.text
.global unlock__mulwlo
unlock__mulwlo:
unlock fp, @fp || mulwlo r2, fp
unlock fp, @fp
mulwlo r2, fp
 
.text
.global add__mulwu1
add__mulwu1:
add fp, fp || mulwu1 r2, fp
add fp, fp
mulwu1 r2, fp
 
.text
.global addi__mvfachi
addi__mvfachi:
addi fp, #77 || mvfachi r2, a0
addi fp, #77
mvfachi r2, a0
 
.text
.global addv__mvfaclo
addv__mvfaclo:
addv fp, fp || mvfaclo r2, a1
addv fp, fp
mvfaclo r2, a1
 
.text
.global addx__mvfacmi
addx__mvfacmi:
addx fp, fp || mvfacmi r2, a0
addx fp, fp
mvfacmi r2, a0
 
.text
.global and__mvtachi
and__mvtachi:
and fp, fp || mvtachi r2, a0
and fp, fp
mvtachi r2, a0
.text
.global cmp__mvtaclo
cmp__mvtaclo:
cmp fp, fp || mvtaclo r2, a0
cmp fp, fp
mvtaclo r2, a0
 
.text
.global cmpeq__rac
cmpeq__rac:
cmpeq fp, fp || rac a1
cmpeq fp, fp
rac a1
 
.text
.global cmpu__rach
cmpu__rach:
cmpu fp, fp || rach a0, a1
cmpu fp, fp
rach a1, a1, #1
 
.text
.global cmpz__sadd
cmpz__sadd:
cmpz fp || sadd
cmpz fp
sadd
 
 
# Test private instructions
.text
.global sc
sc:
sc
sadd
.text
.global snc
snc:
snc
sadd
.text
.global jc
jc:
jc fp
.text
.global jnc
jnc:
jnc fp
.text
.global pcmpbz
pcmpbz:
pcmpbz fp
.text
.global sat
sat:
sat fp, fp
.text
.global sath
sath:
sath fp, fp
 
 
# Test parallel versions of the private instructions
.text
.global jc__pcmpbz
jc__pcmpbz:
jc fp || pcmpbz fp
jc fp
pcmpbz fp
.text
.global jnc__ldi
jnc__ldi:
jnc fp || ldi fp, #77
jnc fp
ldi fp, #77
.text
.global sc__mv
sc__mv:
sc || mv fp, r2
sc
mv fp, r2
 
.text
.global snc__neg
snc__neg:
snc || neg fp, r2
snc
neg fp, r2
# Test automatic and explicit parallelisation of instructions
.text
.global nop__sadd
nop__sadd:
nop
sadd
 
.text
.global sadd__nop
sadd__nop:
sadd
nop
 
.text
.global sadd__nop_reverse
sadd__nop_reverse:
sadd || nop
 
.text
.global add__not
add__not:
add r0, r1
not r3, r5
 
.text
.global add__not__dest_clash
add__not_dest_clash:
add r3, r4
not r3, r5
 
.text
.global add__not__src_clash
add__not__src_clash:
add r3, r4
not r5, r3
 
.text
.global add__not__no_clash
add__not__no_clash:
add r3, r4
not r4, r5
 
.text
.global mul__sra
mul__sra:
mul r1, r2
sra r3, r4
.text
.global mul__sra__reverse_src_clash
mul__sra__reverse_src_clash:
mul r1, r3
sra r3, r4
.text
.global bc__add_
bc__add_:
bc.s label
add r1, r2
 
.text
.global add__bc
add__bc:
add r3, r4
bc.s label
 
.text
.global bc__add__forced_parallel
bc__add__forced_parallel:
bc label || add r5, r6
 
.text
.global add__bc__forced_parallel
add__bc__forced_parallel:
add r7, r8 || bc label
label:
nop
 
; Additional testcases.
; These insns were added to the chip later.
 
.text
mulwhi:
mulwhi fp, fp, a0
mulwhi fp, fp, a1
mulwlo:
mulwlo fp, fp, a0
mulwlo fp, fp, a1
 
macwhi:
macwhi fp, fp, a0
macwhi fp, fp, a1
 
macwlo:
macwlo fp, fp, a0
macwlo fp, fp, a1
/pic.s
0,0 → 1,43
.section .text
# R_M32R_GOTPC24
pic_gotpc:
bl.s .+4
ld24 r12,#_GLOBAL_OFFSET_TABLE_
add r12,lr
 
# R_M32R_GOTPC_HI_ULO
# R_M32R_GOTPC_HI_SLO
# R_M32R_GOTPC_LO
pic_gotpc_slo:
bl.s .+4
seth r12,#shigh(_GLOBAL_OFFSET_TABLE_)
add3 r12,r12,#low(_GLOBAL_OFFSET_TABLE_+4)
add r12,lr
 
pic_gotpc_ulo:
bl.s .+4
seth r12,#high(_GLOBAL_OFFSET_TABLE_)
or3 r12,r12,#low(_GLOBAL_OFFSET_TABLE_+4)
add r12,lr
 
# R_M32R_GOT24
pic_got:
.global sym
ld24 r0,#sym
 
# R_M32R_GOT16_HI_ULO
# R_M32R_GOT16_HI_SLO
# R_M32R_GOT16_LO
pic_got16:
.global sym2
seth r12,#shigh(sym2)
add3 r12,r12,#low(sym2+4)
seth r12,#high(sym2)
or3 r12,r12,#low(sym2+4)
 
# R_M32R_26_PLTREL
pic_plt:
.global func
bl func
 
.end
/parallel-2.d
0,0 → 1,10
#as: -m32r2 -O
#objdump: -dr
 
.*: +file format .*
 
Disassembly of section .text:
 
0+0000 <test>:
0: 04 a5 24 46 add r4,r5 -> st r4,@r6
4: 7c ff c6 04 bc 0 <test> \|\| addi r6,[#]4

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