URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/gnu-src/binutils-2.18.50/gas/testsuite/gas/msp430
- from Rev 38 to Rev 156
- ↔ Reverse comparison
Rev 38 → Rev 156
/msp430.exp
0,0 → 1,7
# |
# msp430 tests |
# |
|
if [expr [istarget "msp430-*-*"]] then { |
run_dump_test "opcode" |
} |
/opcode.s
0,0 → 1,57
.arch msp430x123 |
.text |
.p2align 1,0 |
|
.global foo |
foo: |
and #1, r11 |
inv r10 |
xor #0x00ff, r11 |
bis #8, r12 |
bit #0x10, r13 |
bic #0xa0, r14 |
cmp #0, r15 |
sub #1, r10 |
subc #0, r11 |
add #1, r12 |
addc #2, r13 |
push r14 |
pop r15 |
sxt r10 |
rra r11 |
swpb r12 |
rrc r13 |
ret |
|
.p2align 1,0 |
.global main |
.type main,@function |
main: |
mov #(__stack-0), r1 |
call #foo |
mov &a, r14 |
mov r14, r15 |
rla r15 |
subc r15, r15 |
inv r15 |
call #__floatsisf |
mov r14, &c |
mov r15, &c+2 |
mov &b, r14 |
mov r14, r15 |
rla r15 |
subc r15, r15 |
inv r15 |
call #__floatsisf |
mov r14, &d |
mov r15, &d+2 |
mov #llo(240), r15 |
br #__stop_progExec__ |
.comm a,2,2 |
.comm b,2,2 |
.comm c,4,2 |
.comm d,4,2 |
|
;; This next instruction triggered a bug which |
;; was fixed by a patch to msp430-dis.c on Jan 2, 2004 |
add &0x200, &0x172 |
/opcode.d
0,0 → 1,45
#objdump: -d --prefix-addresses --show-raw-insn |
#name: MSP430 basic instructions |
|
.*: +file format .*msp.* |
|
Disassembly of section .text: |
0+000 <[^>]*> 1b f3 and #1, r11 ;r3 As==01 |
0+002 <[^>]*> 3a e3 inv r10 ; |
0+004 <[^>]*> 3b e0 ff 00 xor #255, r11 ;#0x00ff |
0+008 <[^>]*> 3c d2 bis #8, r12 ;r2 As==11 |
0+00a <[^>]*> 3d b0 10 00 bit #16, r13 ;#0x0010 |
0+00e <[^>]*> 3e c0 a0 00 bic #160, r14 ;#0x00a0 |
0+012 <[^>]*> 0f 93 cmp #0, r15 ;r3 As==00 |
0+014 <[^>]*> 1a 83 dec r10 ; |
0+016 <[^>]*> 0b 73 sbc r11 ; |
0+018 <[^>]*> 1c 53 inc r12 ; |
0+01a <[^>]*> 2d 63 addc #2, r13 ;r3 As==10 |
0+01c <[^>]*> 0e 12 push r14 ; |
0+01e <[^>]*> 3f 41 pop r15 ; |
0+020 <[^>]*> 8a 11 sxt r10 ; |
0+022 <[^>]*> 0b 11 rra r11 ; |
0+024 <[^>]*> 8c 10 swpb r12 ; |
0+026 <[^>]*> 0d 10 rrc r13 ; |
0+028 <[^>]*> 30 41 ret |
0+02a <[^>]*> 31 40 00 00 mov #0, r1 ;#0x0000 |
0+02e <[^>]*> b0 12 00 00 call #0 ;#0x0000 |
0+032 <[^>]*> 1e 42 00 00 mov &0x0000,r14 ;0x0000 |
0+036 <[^>]*> 0f 4e mov r14, r15 ; |
0+038 <[^>]*> 0f 5f rla r15 ; |
0+03a <[^>]*> 0f 7f subc r15, r15 ; |
0+03c <[^>]*> 3f e3 inv r15 ; |
0+03e <[^>]*> b0 12 00 00 call #0 ;#0x0000 |
0+042 <[^>]*> 82 4e 00 00 mov r14, &0x0000 ; |
0+046 <[^>]*> 82 4f 00 00 mov r15, &0x0000 ; |
0+04a <[^>]*> 1e 42 00 00 mov &0x0000,r14 ;0x0000 |
0+04e <[^>]*> 0f 4e mov r14, r15 ; |
0+050 <[^>]*> 0f 5f rla r15 ; |
0+052 <[^>]*> 0f 7f subc r15, r15 ; |
0+054 <[^>]*> 3f e3 inv r15 ; |
0+056 <[^>]*> b0 12 00 00 call #0 ;#0x0000 |
0+05a <[^>]*> 82 4e 00 00 mov r14, &0x0000 ; |
0+05e <[^>]*> 82 4f 00 00 mov r15, &0x0000 ; |
0+062 <[^>]*> 3f 40 f0 00 mov #240, r15 ;#0x00f0 |
0+066 <[^>]*> 30 40 00 00 br #0x0000 ; |
0+06a <[^>]*> 92 52 00 02 72 01 add &0x0200,&0x0172 ;0x0200 |