OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/gnu-src/binutils-2.18.50/ld/testsuite/ld-arm
    from Rev 38 to Rev 156
    ↔ Reverse comparison
  •

Rev 38 → Rev 156

/vfp11-fix-none.s
0,0 → 1,7
.arm
.text
.globl _start
_start:
.word 0xee474a20
.word 0xed927a00
bx lr
/tls-app.r
0,0 → 1,10
 
.*: file format elf32-.*arm
 
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
[0-9a-f]+ R_ARM_TLS_DTPMOD32 app_gd
[0-9a-f]+ R_ARM_TLS_DTPOFF32 app_gd
[0-9a-f]+ R_ARM_TLS_DTPMOD32 lib_gd
[0-9a-f]+ R_ARM_TLS_DTPOFF32 lib_gd
[0-9a-f]+ R_ARM_TLS_TPOFF32 app_ie
/tls-app.s
0,0 → 1,34
.text
.globl foo
.type foo, %function
foo:
nop
.L2:
nop
mov pc, lr
 
.Lpool:
.word lib_gd(tlsgd) + (. - .L2 - 8)
.word app_gd(tlsgd) + (. - .L2 - 8)
.word app_ld(tlsldm) + (. - .L2 - 8)
.word app_ld(tlsldo)
.word app_ie(gottpoff) + (. - .L2 - 8)
.word app_le(tpoff)
 
.section .tdata,"awT"
.global app_gd
app_gd:
.space 4
 
.global app_ld
app_ld:
.space 4
 
.section .tbss,"awT",%nobits
.global app_ie
app_ie:
.space 4
 
.global app_le
app_le:
.space 4
/symbian-seg1.d
0,0 → 1,8
#source: symbian-seg1.s
#ld: -Ttext 0x10000 -Tdata 0x400000
#objdump: -dR
#...
+10000: 00400000 .word 0x00400000
+10000: R_ARM_RELATIVE .data
+10004: 00010008 .word 0x00010008
+10004: R_ARM_RELATIVE .text
/armv4-bx.d
0,0 → 1,19
 
.*: .*file format elf32-(big|little)arm
 
Disassembly of section \.text:
 
00008000 <_start>:
8000: ea000001 b 800c \<__bx_r14\>
8004: ea000003 b 8018 \<__bx_r0\>
8008: 0a000002 beq 8018 \<__bx_r0\>
 
0000800c <__bx_r14>:
800c: e31e0001 tst lr, #1 ; 0x1
8010: 01a0f00e moveq pc, lr
8014: e12fff1e bx lr
 
00008018 <__bx_r0>:
8018: e3100001 tst r0, #1 ; 0x1
801c: 01a0f000 moveq pc, r0
8020: e12fff10 bx r0
/arm-lib.r
0,0 → 1,8
 
tmpdir/arm-lib.so: file format elf32-(little|big)arm
 
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
.* R_ARM_JUMP_SLOT app_func2
 
 
/use-thumb-lib.sym
0,0 → 1,4
#...
.. ..: 00000000 2 FUNC GLOBAL DEFAULT UND lib_func2
#pass
 
/arm-lib.s
0,0 → 1,24
.text
 
.globl lib_func1
.type lib_func1, %function
lib_func1:
mov ip, sp
stmdb sp!, {r11, ip, lr, pc}
bl app_func2
ldmia sp, {r11, sp, lr}
bx lr
.size lib_func1, . - lib_func1
 
.globl lib_func2
.type lib_func2, %function
lib_func2:
bx lr
.size lib_func2, . - lib_func2
 
.data
.globl data_obj
.type data_obj, %object
data_obj:
.long 0
.size data_obj, . - data_obj
/callweak.s
0,0 → 1,16
.syntax unified
.weak bar
.section .far, "ax", %progbits
.global _start
.type _start, %function
_start:
bl bar
bleq bar
.thumb
.type foo, %function
.thumb_func
foo:
bl bar
movs r0, #0
bl bar
bx lr
/group-relocs-alu-bad.s
0,0 → 1,20
@ Test intended to fail for ALU group relocations.
@
@ Beware when editing this file: it is carefully crafted so that
@ a specific PC-relative offset arises.
 
@ We will place .text at 0x8000.
 
.text
.globl _start
 
_start:
add r0, r0, #:pc_g0:(bar)
 
@ We will place the section foo at 0x9004.
 
.section foo
 
bar:
mov r0, #0
 
/arm-target1-rel.d
0,0 → 1,7
 
.*: file format .*
 
Contents of section .text:
8000 (04000000|00000004) .*
# Ignore .ARM.attributes section
#...
/group-relocs-ldrs-bad.d
0,0 → 1,4
#name: LDRS group relocations failure test
#source: group-relocs-ldrs-bad.s
#ld: -Ttext 0x8000 --section-start foo=0x8000100
#error: Overflow whilst splitting 0x8000100 for group relocation
/preempt-app.s
0,0 → 1,27
@ Preempt an ARM shared library function with a Thumb function
@ in the application.
.text
.p2align 4
.globl _start
_start:
mov ip, sp
stmdb sp!, {r11, ip, lr, pc}
bl lib_func1
ldmia sp, {r11, sp, lr}
bx lr
 
.p2align 4
.globl app_func2
.type app_func2,%function
app_func2:
bx lr
 
.p2align 4
.globl lib_func1
.type lib_func1,%function
.thumb_func
lib_func1:
bx lr
 
.data
.long data_obj
/mixed-lib.d
0,0 → 1,38
 
tmpdir/mixed-lib.so: file format elf32-(little|big)arm
architecture: arm, flags 0x00000150:
HAS_SYMS, DYNAMIC, D_PAGED
start address 0x.*
 
Disassembly of section .plt:
 
.* <.plt>:
.*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
.*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func1-0x1c>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
Disassembly of section .text:
 
.* <lib_func1>:
.*: e1a0c00d mov ip, sp
.*: e92dd800 push {fp, ip, lr, pc}
.*: ebfffff. bl .* <lib_func1-0x..?>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
.*: e1a00000 nop \(mov r0,r0\)
.*: e1a00000 nop \(mov r0,r0\)
.*: e1a00000 nop \(mov r0,r0\)
 
.* <lib_func2>:
.*: 4770 bx lr
.*: 46c0 nop \(mov r8, r8\)
.*: 46c0 nop \(mov r8, r8\)
.*: 46c0 nop \(mov r8, r8\)
.*: 46c0 nop \(mov r8, r8\)
.*: 46c0 nop \(mov r8, r8\)
.*: 46c0 nop \(mov r8, r8\)
.*: 46c0 nop \(mov r8, r8\)
/gc-unwind.s
0,0 → 1,38
@ Test -gc-sections and unwinding tables. .data.eh should be pulled in
@ via the EH tables, .data.foo should not.
.text
.global _start
.fnstart
_start:
bx lr
.personality my_pr
.handlerdata
.word 0
.fnend
 
.section .data.foo
my_foo:
.word 0x11111111
 
.section .text.foo
.fnstart
foo:
bx lr
.personality my_pr
.handlerdata
.word my_foo
.fnend
 
.section .data.eh
my_eh:
.word 0x22222222
 
.section .text.eh
.fnstart
my_pr:
bx lr
.personality my_pr
.handlerdata
.word my_eh
.fnend
 
/thumb2-bl.s
0,0 → 1,23
@ Test to ensure that a Thumb-2 BL works with an offset that is
@ not permissable for Thumb-1.
 
.arch armv7
.global _start
.syntax unified
 
@ We will place the section .text at 0x1000.
 
.text
.thumb_func
 
_start:
bl bar
 
@ We will place the section .foo at 0x1001000.
 
.section .foo, "xa"
.thumb_func
 
bar:
bx lr
 
/vxworks1-lib.dd
0,0 → 1,41
 
.*: file format .*
 
Disassembly of section \.plt:
 
00080800 <_PROCEDURE_LINKAGE_TABLE_>:
80800: e59fc000 ldr ip, \[pc, #0\] ; 80808 <.*>
80804: e79cf009 ldr pc, \[ip, r9\]
80808: 0000000c .word 0x0000000c
8080c: e59fc000 ldr ip, \[pc, #0\] ; 80814 <.*>
80810: e599f008 ldr pc, \[r9, #8\]
80814: 00000000 .word 0x00000000
80818: e59fc000 ldr ip, \[pc, #0\] ; 80820 <.*>
8081c: e79cf009 ldr pc, \[ip, r9\]
80820: 00000010 .word 0x00000010
80824: e59fc000 ldr ip, \[pc, #0\] ; 8082c <.*>
80828: e599f008 ldr pc, \[r9, #8\]
8082c: 0000000c .word 0x0000000c
Disassembly of section \.text:
 
00080c00 <foo>:
80c00: e92dc200 push {r9, lr, pc}
80c04: e59f9024 ldr r9, \[pc, #36\] ; 80c30 <.*>
80c08: e5999000 ldr r9, \[r9\]
80c0c: e5999000 ldr r9, \[r9\]
80c10: e59f001c ldr r0, \[pc, #28\] ; 80c34 <.*>
80c14: e7991000 ldr r1, \[r9, r0\]
80c18: e2811001 add r1, r1, #1 ; 0x1
80c1c: e7891000 str r1, \[r9, r0\]
80c20: eb000004 bl 80c38 <slocal>
80c24: ebfffefb bl 80818 <.*>
80c28: ebfffef4 bl 80800 <.*>
80c2c: e8bd8200 pop {r9, pc}
80c30: 00000000 .word 0x00000000
80c34: 00000014 .word 0x00000014
 
00080c38 <slocal>:
80c38: e1a0f00e mov pc, lr
 
00080c3c <sglobal>:
80c3c: e1a0f00e mov pc, lr
/symbian-seg1.s
0,0 → 1,13
.text
.globl _start
_start:
.word datavar
.word rodatavar
 
.section ".rodata", "a"
rodatavar:
.word 0
 
.section ".data", "aw"
datavar:
.word 0
/thumb-entry.d
0,0 → 1,3
#...
Entry point address: 0x8001
#...
/armv4-bx.s
0,0 → 1,8
.text
.arch armv4
.global _start
.type _start, %function
_start:
bx lr
bx r0
bxeq r0
/preempt-app.sym
0,0 → 1,16
 
Symbol table for image:
Num Buc: Value Size Type Bind Vis Ndx Name
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _edata
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_start__
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _end
.. ..: ........ 4 OBJECT GLOBAL DEFAULT 10 data_obj
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_end__
.. ..: .......1 20 FUNC GLOBAL DEFAULT 6 lib_func1
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __exidx_start
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT 9 __data_start
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __end__
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_start
.. ..: .......0 0 FUNC GLOBAL DEFAULT 6 app_func2
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _bss_end__
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __exidx_end
/vfp11-fix-scalar.d
0,0 → 1,15
 
.*: .*file format elf32-(big|little)arm
 
Disassembly of section \.text:
 
00008000 <_start>:
8000: 0a000001 beq 800c <__vfp11_veneer_0>
 
00008004 <__vfp11_veneer_0_r>:
8004: ed927a00 flds s14, \[r2\]
8008: e12fff1e bx lr
 
0000800c <__vfp11_veneer_0>:
800c: 0e474a20 fmacseq s9, s14, s1
8010: eafffffb b 8004 <__vfp11_veneer_0_r>
/emit-relocs1-vxworks.d
0,0 → 1,12
#source: emit-relocs1.s
#ld: -Ttext 0x10000 --defsym target=0xc000 -e0 --emit-relocs
#objdump: -dr
#...
+10000: e1a00000 nop .*
+10004: e1a00000 nop .*
+10008: e1a00000 nop .*
+1000c: e1a00000 nop .*
+10010: eaffeffa b c000 <target>
+10010: R_ARM_PC24 target\+0xf+8
+10014: eaffeffd b c010 <target\+0x10>
+10014: R_ARM_PC24 target\+0x8
/group-relocs-ldrs-bad.s
0,0 → 1,17
@ Test intended to fail for LDRS group relocations.
 
@ We will place .text at 0x8000.
 
.text
.globl _start
 
_start:
add r0, r0, #:sb_g0_nc:(bar)
ldrd r2, [r0, #:sb_g1:(bar)]
 
@ We will place the section foo at 0x8000100.
 
.section foo
 
bar:
mov r0, #0
/attr-merge-2a.s
0,0 → 1,10
.cpu arm7tdmi
.fpu softvfp
.eabi_attribute 20, 1
.eabi_attribute 21, 1
.eabi_attribute 23, 3
.eabi_attribute 24, 1
.eabi_attribute 25, 1
.eabi_attribute 26, 1
.eabi_attribute 30, 6
.file "attr-merge-2a.s"
/arm-target1-abs.d
0,0 → 1,7
 
.*: file format.*
 
Contents of section .text:
8000 (04800000|00008004) .*
# Ignore .ARM.attributes section
#...
/arm-call1.s
0,0 → 1,30
# Test R_ARM_CALL and R_ARM_JUMP24 relocations and interworking
.text
.arch armv5t
.global _start
_start:
bl arm
bl t1
bl t2
bl t5
blx t1
blx t2
b t1
b t2
blne t1
blne t2
blne arm
blx arm
blx thumblocal
.thumb
thumblocal:
bx lr
.global t3
.thumb_func
t3:
bx lr
.global t4
.thumb_func
t4:
bx lr
nop
/mixed-lib.r
0,0 → 1,8
 
tmpdir/mixed-lib.so: file format elf32-(little|big)arm
 
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
.* R_ARM_JUMP_SLOT app_func2
 
 
/arm-movwt.d
0,0 → 1,39
 
.*: file format.*
 
Disassembly of section .text:
 
00008000 <[^>]*>:
8000: e3000000 movw r0, #0 ; 0x0
8004: e3411234 movt r1, #4660 ; 0x1234
8008: e3082000 movw r2, #32768 ; 0x8000
800c: e3413233 movt r3, #4659 ; 0x1233
8010: e3004011 movw r4, #17 ; 0x11
8014: e3415234 movt r5, #4660 ; 0x1234
8018: e3086011 movw r6, #32785 ; 0x8011
801c: e3417233 movt r7, #4659 ; 0x1233
 
00008020 <[^>]*>:
8020: f240 0700 movw r7, #0 ; 0x0
8024: f2c1 2634 movt r6, #4660 ; 0x1234
8028: f248 0500 movw r5, #32768 ; 0x8000
802c: f2c1 2433 movt r4, #4659 ; 0x1233
8030: f240 0311 movw r3, #17 ; 0x11
8034: f2c1 2234 movt r2, #4660 ; 0x1234
8038: f248 0111 movw r1, #32785 ; 0x8011
803c: f2c1 2033 movt r0, #4659 ; 0x1233
 
Disassembly of section .far:
 
12340000 <[^>]*>:
12340000: e3080000 movw r0, #32768 ; 0x8000
12340004: e34e0dcc movt r0, #60876 ; 0xedcc
12340008: e3080021 movw r0, #32801 ; 0x8021
1234000c: e34e0dcc movt r0, #60876 ; 0xedcc
 
12340010 <[^>]*>:
12340010: f248 0000 movw r0, #32768 ; 0x8000
12340014: f6ce 50cc movt r0, #60876 ; 0xedcc
12340018: f248 0021 movw r0, #32801 ; 0x8021
1234001c: f6ce 50cc movt r0, #60876 ; 0xedcc
 
/mixed-lib.s
0,0 → 1,28
.text
 
.p2align 4
.globl lib_func1
.type lib_func1, %function
lib_func1:
mov ip, sp
stmdb sp!, {r11, ip, lr, pc}
bl app_func2
ldmia sp, {r11, sp, lr}
bx lr
.size lib_func1, . - lib_func1
 
.p2align 4
.globl lib_func2
.type lib_func2, %function
.thumb_func
.code 16
lib_func2:
bx lr
.size lib_func2, . - lib_func2
 
.data
.globl data_obj
.type data_obj, %object
data_obj:
.long 0
.size data_obj, . - data_obj
/vxworks1-lib.td
0,0 → 1,3
#...
0x0+16 \(TEXTREL\) +0x0
#pass
/thumb-entry.s
0,0 → 1,8
.text
.arch armv4t
.thumb
.global _start
.thumb_func
_start:
bx lr
/arm-app.d
0,0 → 1,35
 
tmpdir/arm-app: file format elf32-(little|big)arm
architecture: arm, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x.*
 
Disassembly of section .plt:
 
.* <.plt>:
.*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
.*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x10>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
Disassembly of section .text:
 
.* <_start>:
.*: e1a0c00d mov ip, sp
.*: e92dd800 push {fp, ip, lr, pc}
.*: eb000001 bl .* <app_func>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
 
.* <app_func>:
.*: e1a0c00d mov ip, sp
.*: e92dd800 push {fp, ip, lr, pc}
.*: ebfffff4 bl .* <_start-0xc>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
 
.* <app_func2>:
.*: e12fff1e bx lr
/attr-merge-2.attr
0,0 → 1,12
Attribute Section: aeabi
File Attributes
Tag_CPU_name: "ARM7TDMI"
Tag_CPU_arch: v4T
Tag_ABI_PCS_wchar_t: 4
Tag_ABI_FP_denormal: Needed
Tag_ABI_FP_exceptions: Needed
Tag_ABI_FP_number_model: IEEE 754
Tag_ABI_align8_needed: Yes
Tag_ABI_align8_preserved: Yes, except leaf SP
Tag_ABI_enum_size: small
Tag_ABI_optimization_goals: Aggressive Debug
/mixed-lib.sym
0,0 → 1,17
 
Symbol table for image:
Num Buc: Value Size Type Bind Vis Ndx Name
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _edata
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_start__
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _end
.. ..: ........ 4 OBJECT GLOBAL DEFAULT 9 data_obj
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_end__
.. ..: .......0 20 FUNC GLOBAL DEFAULT 6 lib_func1
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __exidx_start
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT 9 __data_start
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __end__
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_start
.. ..: 00000000 0 NOTYPE GLOBAL DEFAULT UND app_func2
.. ..: .......1 2 FUNC GLOBAL DEFAULT 6 lib_func2
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _bss_end__
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __exidx_end
/arm-lib.ld
0,0 → 1,187
/* Script for --shared -z combreloc: shared library, combine & sort relocs */
OUTPUT_ARCH(arm)
ENTRY(_start)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = 0 + SIZEOF_HEADERS;
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.rel.dyn :
{
*(.rel.init)
*(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
*(.rel.fini)
*(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
*(.rel.data.rel.ro*)
*(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
*(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
*(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
*(.rel.ctors)
*(.rel.dtors)
*(.rel.got)
*(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
}
.rela.dyn :
{
*(.rela.init)
*(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
*(.rela.fini)
*(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
*(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
*(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
*(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
*(.rela.ctors)
*(.rela.dtors)
*(.rela.got)
*(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
}
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init :
{
KEEP (*(.init))
} =0
.plt : { *(.plt) }
.text :
{
*(.text .stub .text.* .gnu.linkonce.t.*)
KEEP (*(.text.*personality*))
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.glue_7t) *(.glue_7)
} =0
.fini :
{
KEEP (*(.fini))
} =0
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
.rodata1 : { *(.rodata1) }
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) }
__exidx_start = .;
.ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
__exidx_end = .;
.eh_frame_hdr : { *(.eh_frame_hdr) }
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
.gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. */
. = ALIGN (0x8000) - ((0x8000 - .) & (0x8000 - 1)); . = DATA_SEGMENT_ALIGN (0x8000, 0x1000);
/* Exception handling */
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
.gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
/* Thread Local Storage sections */
.tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
/* Ensure the __preinit_array_start label is properly aligned. We
could instead move the label definition inside the section, but
the linker would then create the section even if it turns out to
be empty, which isn't pretty. */
. = ALIGN(32 / 8);
.preinit_array : { KEEP (*(.preinit_array)) }
.init_array : { KEEP (*(.init_array)) }
.fini_array : { KEEP (*(.fini_array)) }
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin*.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
}
.dtors :
{
KEEP (*crtbegin*.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
}
.jcr : { KEEP (*(.jcr)) }
.data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) }
.dynamic : { *(.dynamic) }
.got : { *(.got.plt) *(.got) }
.data :
{
__data_start = . ;
*(.data .data.* .gnu.linkonce.d.*)
KEEP (*(.gnu.linkonce.d.*personality*))
SORT(CONSTRUCTORS)
}
.data1 : { *(.data1) }
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
__bss_start__ = .;
.bss :
{
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(32 / 8);
}
. = ALIGN(32 / 8);
_end = .;
_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
PROVIDE (end = .);
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
/DISCARD/ : { *(.note.GNU-stack) }
}
 
 
/vfp11-fix-scalar.s
0,0 → 1,7
.arm
.text
.globl _start
_start:
fmacseq s9, s14, s1
flds s14, [r2]
bx lr
/arm-target1.s
0,0 → 1,6
# Test the R_ARM_TARGET1 relocation
.text
.global _start
_start:
.word foo(target1)
foo:
/emit-relocs1.d
0,0 → 1,12
#source: emit-relocs1.s
#ld: -Ttext 0x10000 --defsym target=0xc000 -e0 --emit-relocs
#objdump: -dr
#...
+10000: e1a00000 nop .*
+10004: e1a00000 nop .*
+10008: e1a00000 nop .*
+1000c: e1a00000 nop .*
+10010: eaffeffa b c000 <target>
+10010: R_ARM_(JUMP|PC)24 target
+10014: eaffeffd b c010 <target\+0x10>
+10014: R_ARM_(JUMP|PC)24 target
/vxworks1.dd
0,0 → 1,37
 
.*: file format .*
 
Disassembly of section \.plt:
 
00080800 <_PROCEDURE_LINKAGE_TABLE_>:
80800: e52dc008 str ip, \[sp, #-8\]!
80804: e59fc000 ldr ip, \[pc, #0\] ; 8080c <.*>
80808: e59cf008 ldr pc, \[ip, #8\]
8080c: 00081400 .word 0x00081400
8080c: R_ARM_ABS32 _GLOBAL_OFFSET_TABLE_
80810: e59fc000 ldr ip, \[pc, #0\] ; 80818 <.*>
80814: e59cf000 ldr pc, \[ip\]
80818: 0008140c .word 0x0008140c
80818: R_ARM_ABS32 _GLOBAL_OFFSET_TABLE_\+0xc
8081c: e59fc000 ldr ip, \[pc, #0\] ; 80824 <.*>
80820: eafffff6 b 80800 <.*>
80824: 00000000 .word 0x00000000
80828: e59fc000 ldr ip, \[pc, #0\] ; 80830 <.*>
8082c: e59cf000 ldr pc, \[ip\]
80830: 00081410 .word 0x00081410
80830: R_ARM_ABS32 _GLOBAL_OFFSET_TABLE_\+0x10
80834: e59fc000 ldr ip, \[pc, #0\] ; 8083c <.*>
80838: eafffff0 b 80800 <.*>
8083c: 0000000c .word 0x0000000c
Disassembly of section \.text:
 
00080c00 <_start>:
80c00: ebffff08 bl 80828 <.*>
80c00: R_ARM_PC24 \.plt\+0x20
80c04: eb000000 bl 80c0c <sexternal>
80c04: R_ARM_PC24 sexternal\+0xfffffff8
80c08: eaffff00 b 80810 <.*>
80c08: R_ARM_PC24 \.plt\+0x8
 
00080c0c <sexternal>:
80c0c: e1a0f00e mov pc, lr
/arm-movwt.s
0,0 → 1,44
.text
.arch armv6t2
.syntax unified
.global _start
.type _start, %function
_start:
base1:
arm1:
movw r0, #:lower16:arm2
movt r1, #:upper16:arm2
movw r2, #:lower16:(arm2 - arm1)
movt r3, #:upper16:(arm2 - arm1)
movw r4, #:lower16:thumb2
movt r5, #:upper16:thumb2
movw r6, #:lower16:(thumb2 - arm1)
movt r7, #:upper16:(thumb2 - arm1)
.thumb
.type thumb1, %function
.thumb_func
thumb1:
movw r7, #:lower16:arm2
movt r6, #:upper16:arm2
movw r5, #:lower16:(arm2 - arm1)
movt r4, #:upper16:(arm2 - arm1)
movw r3, #:lower16:thumb2
movt r2, #:upper16:thumb2
movw r1, #:lower16:(thumb2 - arm1)
movt r0, #:upper16:(thumb2 - arm1)
 
.section .far, "ax", %progbits
.arm
arm2:
movw r0, #:lower16:(arm1 - arm2)
movt r0, #:upper16:(arm1 - arm2)
movw r0, #:lower16:(thumb1 - arm2)
movt r0, #:upper16:(thumb1 - arm2)
.thumb
.type thumb2, %function
.thumb_func
thumb2:
movw r0, #:lower16:(arm1 - arm2)
movt r0, #:upper16:(arm1 - arm2)
movw r0, #:lower16:(thumb1 - arm2)
movt r0, #:upper16:(thumb1 - arm2)
/arm-app.r
0,0 → 1,9
 
tmpdir/arm-app.*: file format elf32-(little|big)arm
 
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
.* R_ARM_COPY data_obj
.* R_ARM_JUMP_SLOT lib_func1
 
 
/arm-app.s
0,0 → 1,23
.text
.globl _start
_start:
mov ip, sp
stmdb sp!, {r11, ip, lr, pc}
bl app_func
ldmia sp, {r11, sp, lr}
bx lr
 
.globl app_func
app_func:
mov ip, sp
stmdb sp!, {r11, ip, lr, pc}
bl lib_func1
ldmia sp, {r11, sp, lr}
bx lr
 
.globl app_func2
app_func2:
bx lr
 
.data
.long data_obj
/thumb2-bl-as-thumb1-bad.d
0,0 → 1,4
#name: Thumb-2-as-Thumb-1 BL failure test
#source: thumb2-bl-as-thumb1-bad.s
#ld: -Ttext 0x1000 --section-start .foo=0x401004
#error: .*\(.text\+0x0\): relocation truncated to fit: R_ARM_THM_CALL against `bar'
/vxworks1.ld
0,0 → 1,30
SECTIONS
{
. = 0x80000;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
 
. = ALIGN (0x400);
.rela.dyn : { *(.rela.dyn) }
.rela.plt : { *(.rela.plt) }
 
. = ALIGN (0x400);
.plt : { *(.plt) }
 
. = ALIGN (0x400);
.text : { *(.text) }
 
. = ALIGN (0x1000);
.dynamic : { *(.dynamic) }
 
. = ALIGN (0x400);
.got : { *(.got.plt) *(.got) }
 
. = ALIGN (0x400);
.data : { *(.data) }
 
. = ALIGN (0x400);
.bss : { *(.bss) *(.dynbss) }
}
/arm-static-app.d
0,0 → 1,24
 
tmpdir/arm-static-app: file format elf32-(little|big)arm
architecture: arm, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x.*
 
Disassembly of section .text:
 
.* <_start>:
.*: e1a0c00d mov ip, sp
.*: e92dd800 push {fp, ip, lr, pc}
.*: eb000001 bl .* <app_func>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
 
.* <app_func>:
.*: e1a0c00d mov ip, sp
.*: e92dd800 push {fp, ip, lr, pc}
.*: eb000001 bl .* <app_func2>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
 
.* <app_func2>:
.*: e12fff1e bx lr
/arm-dyn.ld
0,0 → 1,194
/* Script for -z combreloc: combine and sort reloc sections */
OUTPUT_ARCH(arm)
ENTRY(_start)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
PROVIDE (__executable_start = 0x8000); . = 0x8000;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.rel.dyn :
{
*(.rel.init)
*(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
*(.rel.fini)
*(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
*(.rel.data.rel.ro*)
*(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
*(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
*(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
*(.rel.ctors)
*(.rel.dtors)
*(.rel.got)
*(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
}
.rela.dyn :
{
*(.rela.init)
*(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
*(.rela.fini)
*(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
*(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
*(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
*(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
*(.rela.ctors)
*(.rela.dtors)
*(.rela.got)
*(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
}
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init :
{
KEEP (*(.init))
} =0
.plt : { *(.plt) }
.text :
{
*(.text .stub .text.* .gnu.linkonce.t.*)
KEEP (*(.text.*personality*))
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.glue_7t) *(.glue_7)
} =0
.fini :
{
KEEP (*(.fini))
} =0
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
.rodata1 : { *(.rodata1) }
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) }
__exidx_start = .;
.ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
__exidx_end = .;
.eh_frame_hdr : { *(.eh_frame_hdr) }
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
.gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. */
. = ALIGN (0x8000) - ((0x8000 - .) & (0x8000 - 1)); . = DATA_SEGMENT_ALIGN (0x8000, 0x1000);
/* Exception handling */
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
.gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
/* Thread Local Storage sections */
.tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
/* Ensure the __preinit_array_start label is properly aligned. We
could instead move the label definition inside the section, but
the linker would then create the section even if it turns out to
be empty, which isn't pretty. */
. = ALIGN(32 / 8);
PROVIDE (__preinit_array_start = .);
.preinit_array : { KEEP (*(.preinit_array)) }
PROVIDE (__preinit_array_end = .);
PROVIDE (__init_array_start = .);
.init_array : { KEEP (*(.init_array)) }
PROVIDE (__init_array_end = .);
PROVIDE (__fini_array_start = .);
.fini_array : { KEEP (*(.fini_array)) }
PROVIDE (__fini_array_end = .);
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin*.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
}
.dtors :
{
KEEP (*crtbegin*.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
}
.jcr : { KEEP (*(.jcr)) }
.data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) }
.dynamic : { *(.dynamic) }
.got : { *(.got.plt) *(.got) }
.data :
{
__data_start = . ;
*(.data .data.* .gnu.linkonce.d.*)
KEEP (*(.gnu.linkonce.d.*personality*))
SORT(CONSTRUCTORS)
}
.data1 : { *(.data1) }
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
__bss_start__ = .;
.bss :
{
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(32 / 8);
}
. = ALIGN(32 / 8);
_end = .;
_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
PROVIDE (end = .);
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
/DISCARD/ : { *(.note.GNU-stack) }
}
 
 
/emit-relocs1.s
0,0 → 1,6
nop
nop
nop
nop
b target
b target+16
/vxworks2.s
0,0 → 1,5
.globl _start
.type _start, %function
_start:
mov pc, lr
.end _start
/mixed-app.d
0,0 → 1,58
 
tmpdir/mixed-app: file format elf32-(little|big)arm
architecture: arm, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x.*
 
Disassembly of section .plt:
 
.* <.plt>:
.*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
.*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x2c>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.*: 4778 bx pc
.*: 46c0 nop \(mov r8, r8\)
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
Disassembly of section .text:
 
.* <_start>:
.*: e1a0c00d mov ip, sp
.*: e92dd800 push {fp, ip, lr, pc}
.*: eb000004 bl .* <app_func>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
.*: e1a00000 nop \(mov r0,r0\)
.*: e1a00000 nop \(mov r0,r0\)
.*: e1a00000 nop \(mov r0,r0\)
 
.* <app_func>:
.*: e1a0c00d mov ip, sp
.*: e92dd800 push {fp, ip, lr, pc}
.*: ebffff.. bl .*
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
.*: e1a00000 nop \(mov r0,r0\)
.*: e1a00000 nop \(mov r0,r0\)
.*: e1a00000 nop \(mov r0,r0\)
 
.* <app_func2>:
.*: e12fff1e bx lr
.*: e1a00000 nop \(mov r0,r0\)
.*: e1a00000 nop \(mov r0,r0\)
.*: e1a00000 nop \(mov r0,r0\)
 
.* <app_tfunc>:
.*: b500 push {lr}
.*: f7ff ffc. bl .* <_start-0x..>
.*: bd00 pop {pc}
.*: 4770 bx lr
.*: 46c0 nop \(mov r8, r8\)
.*: 46c0 nop \(mov r8, r8\)
.*: 46c0 nop \(mov r8, r8\)
/group-relocs-ldr-bad.d
0,0 → 1,4
#name: LDR group relocations failure test
#source: group-relocs-ldr-bad.s
#ld: -Ttext 0x8000 --section-start foo=0x8001000
#error: .*Overflow whilst splitting 0x8001000 for group relocation.*
/jump19.d
0,0 → 1,12
 
.*jump19: file format elf32-(big|little)arm
 
Disassembly of section .text:
 
00008000 <_start>:
8000: 4280 cmp r0, r0
8002: f010 8000 beq.w 18006 <bar>
...
 
00018006 <bar>:
18006: 4770 bx lr
/arm-be8.d
0,0 → 1,8
 
.*: file format.*
 
Contents of section .text:
8000 0000a0e3 1eff2fe1 c0467047 fff7fcff .*
8010 12345678 .*
# Ignore .ARM.attributes section
#...
/arm.ld
0,0 → 1,21
/* Script for ld testsuite */
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
/* Read-only sections, merged into text segment: */
PROVIDE (__executable_start = 0x8000); . = 0x8000;
.text :
{
*(.before)
*(.text)
*(.after)
*(.glue_7)
*(.v4_bx)
} =0
. = 0x9000;
.got : { *(.got) *(.got.plt)}
. = 0x12340000;
.far : { *(.far) }
.ARM.attribues 0 : { *(.ARM.atttributes) }
}
/use-thumb-lib.s
0,0 → 1,25
.cpu arm10tdmi
.fpu softvfp
.eabi_attribute 18, 4
.eabi_attribute 20, 1
.eabi_attribute 21, 1
.eabi_attribute 23, 3
.eabi_attribute 24, 1
.eabi_attribute 25, 1
.eabi_attribute 26, 2
.eabi_attribute 30, 6
.file "use_thumb_lib.c"
.text
.align 2
.global foo
.type foo, %function
foo:
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 1, uses_anonymous_args = 0
mov ip, sp
stmfd sp!, {fp, ip, lr, pc}
sub fp, ip, #4
bl lib_func2
ldmfd sp, {fp, sp, pc}
.size foo, .-foo
.ident "GCC: (GNU) 4.1.0 (CodeSourcery ARM 2006q1-7)"
/arm-elf.exp
0,0 → 1,221
# Expect script for various ARM ELF tests.
# Copyright 2002, 2003, 2004, 2007 Free Software Foundation, Inc.
#
# This file is part of the GNU Binutils.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
# MA 02110-1301, USA.
#
 
if {[istarget "arm-*-vxworks"]} {
set armvxworkstests {
{"VxWorks shared library test 1" "-shared -Tvxworks1.ld"
"" {vxworks1-lib.s}
{{readelf --relocs vxworks1-lib.rd} {objdump -dr vxworks1-lib.dd}
{readelf --symbols vxworks1-lib.nd} {readelf -d vxworks1-lib.td}}
"libvxworks1.so"}
{"VxWorks executable test 1 (dynamic)" \
"tmpdir/libvxworks1.so -Tvxworks1.ld -q --force-dynamic"
"" {vxworks1.s}
{{readelf --relocs vxworks1.rd} {objdump -dr vxworks1.dd}}
"vxworks1"}
{"VxWorks executable test 2 (dynamic)" \
"-Tvxworks1.ld -q --force-dynamic"
"" {vxworks2.s}
{{readelf --segments vxworks2.sd}}
"vxworks2"}
{"VxWorks executable test 2 (static)"
"-Tvxworks1.ld"
"" {vxworks2.s}
{{readelf --segments vxworks2-static.sd}}
"vxworks2"}
}
run_ld_link_tests $armvxworkstests
run_dump_test "vxworks1-static"
run_dump_test "emit-relocs1-vxworks"
}
 
if { [istarget "arm*-*-symbianelf*"] } {
run_dump_test "symbian-seg1"
}
 
# Exclude non-ARM-ELF targets.
 
if { ![is_elf_format] || ![istarget "arm*-*-*"] } {
return
}
 
# List contains test-items with 3 items followed by 2 lists:
# 0:name 1:ld options 2:assembler options
# 3:filenames of assembler files 4: action and options. 5: name of output file
 
# Actions:
# objdump: Apply objdump options on result. Compare with regex (last arg).
# nm: Apply nm options on result. Compare with regex (last arg).
# readelf: Apply readelf options on result. Compare with regex (last arg).
 
set armelftests {
{"Group relocations" "-Ttext 0x8000 --section-start zero=0x0 --section-start alpha=0xeef0 --section-start beta=0xffeef0" "" {group-relocs.s}
{{objdump -Dr group-relocs.d}}
"group-relocs"}
{"Thumb-1 BL" "-Ttext 0x1000 --section-start .foo=0x401000" "" {thumb1-bl.s}
{{objdump -dr thumb1-bl.d}}
"thumb1-bl"}
{"Simple non-PIC shared library" "-shared" "" {arm-lib.s}
{{objdump -fdw arm-lib.d} {objdump -Rw arm-lib.r}}
"arm-lib.so"}
{"Simple PIC shared library" "-shared" "" {arm-lib-plt32.s}
{{objdump -fdw arm-lib-plt32.d} {objdump -Rw arm-lib-plt32.r}}
"arm-lib-plt32.so"}
{"Simple dynamic application" "tmpdir/arm-lib.so" "" {arm-app.s}
{{objdump -fdw arm-app.d} {objdump -Rw arm-app.r}}
"arm-app"}
{"Simple static application" "" "" {arm-static-app.s}
{{objdump -fdw arm-static-app.d} {objdump -rw arm-static-app.r}}
"arm-static-app"}
{"Non-pcrel function reference" "tmpdir/arm-lib.so" "" {arm-app-abs32.s}
{{objdump -fdw arm-app-abs32.d} {objdump -Rw arm-app-abs32.r}}
"arm-app-abs32"}
{"Thumb shared library with ARM entry points" "-shared -T arm-lib.ld" "-mthumb-interwork"
{mixed-lib.s}
{{objdump -fdw armthumb-lib.d} {readelf -Ds armthumb-lib.sym}}
"armthumb-lib.so"}
{"Mixed ARM/Thumb shared library" "-shared -T arm-lib.ld -use-blx" ""
{mixed-lib.s}
{{objdump -fdw mixed-lib.d} {objdump -Rw mixed-lib.r}
{readelf -Ds mixed-lib.sym}}
"mixed-lib.so"}
{"Mixed ARM/Thumb dynamic application" "tmpdir/mixed-lib.so -T arm-dyn.ld" ""
{mixed-app.s}
{{objdump -fdw mixed-app.d} {objdump -Rw mixed-app.r}
{readelf -Ds mixed-app.sym}}
"mixed-app"}
{"Mixed ARM/Thumb arch5 dynamic application" "tmpdir/mixed-lib.so -T arm-dyn.ld --use-blx" ""
{mixed-app.s}
{{objdump -fdw mixed-app-v5.d} {objdump -Rw mixed-app.r}
{readelf -Ds mixed-app.sym}}
"mixed-app-v5"}
{"target1-abs" "-static --target1-abs -T arm.ld" "" {arm-target1.s}
{{objdump -s arm-target1-abs.d}}
"arm-target1-abs"}
{"target1-rel" "-static --target1-rel -T arm.ld" "" {arm-target1.s}
{{objdump -s arm-target1-rel.d}}
"arm-target1-rel"}
{"target2-rel" "-static --target2=rel -T arm.ld" "" {arm-target2.s}
{{objdump -s arm-target2-rel.d}}
"arm-target2-rel"}
{"target2-abs" "-static --target2=abs -T arm.ld" "" {arm-target2.s}
{{objdump -s arm-target2-abs.d}}
"arm-target2-abs"}
{"target2-got-rel" "-static --target2=got-rel -T arm.ld" "" {arm-target2.s}
{{objdump -s arm-target2-got-rel.d}}
"arm-target2-got-rel"}
{"arm-rel31" "-static -T arm.ld" "" {arm-rel31.s}
{{objdump -s arm-rel31.d}}
"arm-rel31"}
{"arm-call" "-static -T arm.ld" "-meabi=4" {arm-call1.s arm-call2.s}
{{objdump -d arm-call.d}}
"arm-call"}
{"TLS shared library" "-shared -T arm-lib.ld" "" {tls-lib.s}
{{objdump -fdw tls-lib.d} {objdump -Rw tls-lib.r}}
"tls-lib.so"}
{"TLS dynamic application" "-T arm-dyn.ld tmpdir/tls-lib.so" "" {tls-app.s}
{{objdump -fdw tls-app.d} {objdump -Rw tls-app.r}}
"tls-app"}
{"Thumb entry point" "-T arm.ld" "" {thumb-entry.s}
{{readelf -h thumb-entry.d}}
"thumb-entry"}
{"thumb-rel32" "-static -T arm.ld" "" {thumb-rel32.s}
{{objdump -s thumb-rel32.d}}
"thumb-rel32"}
{"MOVW/MOVT" "-static -T arm.ld" "" {arm-movwt.s}
{{objdump -dw arm-movwt.d}}
"arm-movwt"}
{"BE8 Mapping Symbols" "-static -T arm.ld -EB --be8" "-EB" {arm-be8.s}
{{objdump -s arm-be8.d}}
"arm-be8"}
{"Using Thumb lib by another lib" "-shared tmpdir/mixed-lib.so" "" {use-thumb-lib.s}
{{readelf -Ds use-thumb-lib.sym}}
"use-thumb-lib.so"}
{"VFP11 denorm erratum fix, scalar operation"
"-EL --vfp11-denorm-fix=scalar -Ttext=0x8000" "-EL -mfpu=vfpxd" {vfp11-fix-scalar.s}
{{objdump -dr vfp11-fix-scalar.d}}
"vfp11-fix-scalar"}
{"VFP11 denorm erratum fix, vector operation"
"-EB --vfp11-denorm-fix=vector -Ttext=0x8000" "-EB -mfpu=vfpxd" {vfp11-fix-vector.s}
{{objdump -dr vfp11-fix-vector.d}}
"vfp11-fix-vector"}
{"VFP11 denorm erratum fix, embedded code-like data"
"-EL --vfp11-denorm-fix=scalar -Ttext=0x8000" "-EL -mfpu=vfpxd" {vfp11-fix-none.s}
{{objdump -dr vfp11-fix-none.d}}
"vfp11-fix-none"}
{"Unwinding and -gc-sections" "-gc-sections" "" {gc-unwind.s}
{{objdump -sj.data gc-unwind.d}}
"gc-unwind"}
{"arm-pic-veneer" "-static -T arm.ld --pic-veneer" "" {arm-pic-veneer.s}
{{objdump -d arm-pic-veneer.d}}
"arm-pic-veneer"}
{"Preempt Thumb symbol" "tmpdir/mixed-lib.so -T arm-dyn.ld --use-blx" ""
{preempt-app.s}
{{readelf -Ds preempt-app.sym}}
"preempt-app"}
{"jump19" "-static -T arm.ld" "" {jump19.s}
{{objdump -dr jump19.d}}
"jump19"}
{"callweak" "-static -T arm.ld" "" {callweak.s}
{{objdump -dr callweak.d}}
"callweak"}
{"ARMv4 interworking" "-static -T arm.ld --fix-v4bx-interworking" "--fix-v4bx -meabi=4" {armv4-bx.s}
{{objdump -d armv4-bx.d}}
"armv4-bx"}
{"MOVW/MOVT and merged sections" "-T arm.ld" "" {movw-merge.s}
{{objdump -dw movw-merge.d}}
"movw-merge"}
{"MOVW/MOVT against shared libraries" "tmpdir/arm-lib.so" "" {arm-app-movw.s}
{{objdump -Rw arm-app.r}}
"arm-app-movw"}
}
 
run_ld_link_tests $armelftests
run_dump_test "group-relocs-alu-bad"
run_dump_test "group-relocs-ldr-bad"
run_dump_test "group-relocs-ldrs-bad"
run_dump_test "group-relocs-ldc-bad"
run_dump_test "thumb2-bl-as-thumb1-bad"
run_dump_test "thumb2-bl-bad"
run_dump_test "emit-relocs1"
 
# Exclude non-ARM-EABI targets.
 
if { ![istarget "arm*-*-*eabi"] } {
return
}
 
set armeabitests {
{"EABI attribute merging" "-r" "" {attr-merge.s attr-merge.s}
{{readelf -A attr-merge.attr}}
"attr-merge"}
{"EABI attribute merging 2" "-r" "" {attr-merge-2a.s attr-merge-2b.s}
{{readelf -A attr-merge-2.attr}}
"attr-merge-2"}
{"Thumb-2 BL" "-Ttext 0x1000 --section-start .foo=0x1001000" "" {thumb2-bl.s}
{{objdump -dr thumb2-bl.d}}
"thumb2-bl"}
{"Thumb-2 Interworked branch" "-T arm.ld" "" {thumb2-b-interwork.s}
{{objdump -dr thumb2-b-interwork.d}}
"thumb2-b-interwork"}
}
 
run_ld_link_tests $armeabitests
/thumb2-bl-as-thumb1-bad.s
0,0 → 1,22
@ Test to ensure that a Thumb-1 BL with a Thumb-2-only offset fails.
 
.arch armv5t
.global _start
.syntax unified
 
@ We will place the section .text at 0x1000.
 
.text
.thumb_func
 
_start:
bl bar
 
@ We will place the section .foo at 0x401004.
 
.section .foo, "xa"
.thumb_func
 
bar:
bx lr
 
/attr-merge.attr
0,0 → 1,12
Attribute Section: aeabi
File Attributes
Tag_CPU_name: "ARM7TDMI"
Tag_CPU_arch: v4T
Tag_ABI_PCS_wchar_t: 4
Tag_ABI_FP_denormal: Needed
Tag_ABI_FP_exceptions: Needed
Tag_ABI_FP_number_model: IEEE 754
Tag_ABI_align8_needed: Yes
Tag_ABI_align8_preserved: Yes, except leaf SP
Tag_ABI_enum_size: small
Tag_ABI_optimization_goals: Aggressive Debug
/arm-static-app.r
0,0 → 1,3
 
tmpdir/arm-static-app: file format elf32-(little|big)arm
 
/arm-static-app.s
0,0 → 1,20
.text
.globl _start
_start:
mov ip, sp
stmdb sp!, {r11, ip, lr, pc}
bl app_func
ldmia sp, {r11, sp, lr}
bx lr
 
.globl app_func
app_func:
mov ip, sp
stmdb sp!, {r11, ip, lr, pc}
bl app_func2
ldmia sp, {r11, sp, lr}
bx lr
 
.globl app_func2
app_func2:
bx lr
/mixed-app.r
0,0 → 1,10
 
tmpdir/mixed-app.*: file format elf32-(little|big)arm
 
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
.* R_ARM_COPY data_obj
.* R_ARM_JUMP_SLOT lib_func2
.* R_ARM_JUMP_SLOT lib_func1
 
 
/arm-app-movw.s
0,0 → 1,11
.text
.globl _start
_start:
movw r0, #:lower16:data_obj
movt r0, #:upper16:data_obj
movw r0, #:lower16:lib_func1
movt r0, #:upper16:lib_func1
 
.globl app_func2
app_func2:
bx lr
/arm-rel31.d
0,0 → 1,7
 
.*: file format.*
 
Contents of section .text:
8000 (10000000 fcffff7f 08000080 f4ffffff|00000010 7ffffffc 80000008 fffffff4) .*
# Ignore .ARM.attributes section
#...
/group-relocs-ldr-bad.s
0,0 → 1,18
@ Test intended to fail for LDR group relocations.
 
@ We will place .text at 0x8000.
 
.text
.globl _start
 
_start:
add r0, r0, #:sb_g0_nc:(bar)
ldr r1, [r0, #:sb_g1:(bar)]
 
@ We will place the section foo at 0x8001000.
 
.section foo
 
bar:
mov r0, #0
 
/mixed-app.s
0,0 → 1,39
.text
.p2align 4
.globl _start
_start:
mov ip, sp
stmdb sp!, {r11, ip, lr, pc}
bl app_func
ldmia sp, {r11, sp, lr}
bx lr
 
.p2align 4
.globl app_func
.type app_func,%function
app_func:
mov ip, sp
stmdb sp!, {r11, ip, lr, pc}
bl lib_func1
ldmia sp, {r11, sp, lr}
bx lr
 
.p2align 4
.globl app_func2
.type app_func2,%function
app_func2:
bx lr
 
.p2align 4
.globl app_tfunc
.type app_tfunc,%function
.thumb_func
.code 16
app_tfunc:
push {lr}
bl lib_func2
pop {pc}
bx lr
 
.data
.long data_obj
/jump19.s
0,0 → 1,12
@ Test the Thumb-2 JUMP19 relocation.
 
.syntax unified
.thumb
.global _start
_start:
cmp r0, r0
beq.w bar
.space 65536
.weak bar
bar:
bx lr
/thumb-rel32.d
0,0 → 1,7
 
.*: file format.*
 
Contents of section .text:
8000 (00000011 fffffffd 00ffffff f8000000|11000000 fdffffff 00f8ffff ff000000) .*
# Ignore .ARM.attributes section
#...
/arm-target2-rel.d
0,0 → 1,7
 
.*: file format.*
 
Contents of section .text:
8000 (04000000|00000004) .*
# Ignore .ARM.attributes section
#...
/tls-lib.d
0,0 → 1,15
 
.*: file format elf32-.*arm
architecture: arm, flags 0x00000150:
HAS_SYMS, DYNAMIC, D_PAGED
start address 0x.*
 
Disassembly of section .text:
 
.* <foo>:
.*: e1a00000 nop \(mov r0,r0\)
.*: e1a00000 nop \(mov r0,r0\)
.*: e1a0f00e mov pc, lr
.*: 00008098 .word 0x00008098
.*: 0000808c .word 0x0000808c
.*: 00000004 .word 0x00000004
/armthumb-lib.sym
0,0 → 1,17
 
Symbol table for image:
Num Buc: Value Size Type Bind Vis Ndx Name
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _edata
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_start__
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _end
.. ..: ........ 4 OBJECT GLOBAL DEFAULT 9 data_obj
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_end__
.. ..: .......0 20 FUNC GLOBAL DEFAULT 6 lib_func1
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __exidx_start
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT 9 __data_start
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __end__
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_start
.. ..: 00000000 0 NOTYPE GLOBAL DEFAULT UND app_func2
.. ..: .......0 2 FUNC GLOBAL DEFAULT 6 lib_func2
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _bss_end__
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __exidx_end
/mixed-app.sym
0,0 → 1,17
 
Symbol table for image:
Num Buc: Value Size Type Bind Vis Ndx Name
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _edata
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_start__
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _end
.. ..: ........ 4 OBJECT GLOBAL DEFAULT 12 data_obj
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_end__
.. ..: 0*[^0]*.* 20 FUNC GLOBAL DEFAULT UND lib_func1
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __exidx_start
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT 11 __data_start
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __end__
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __bss_start
.. ..: .......0 0 FUNC GLOBAL DEFAULT 8 app_func2
.. ..: 0*[^0]*.* 2 FUNC GLOBAL DEFAULT UND lib_func2
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS _bss_end__
.. ..: ........ 0 NOTYPE GLOBAL DEFAULT ABS __exidx_end
/arm-be8.s
0,0 → 1,14
.arch armv6
.text
arm:
mov r0, #0
$m:
bx lr
.thumb
.thumb_func
thumb:
nop
bx lr
bl thumb
data:
.word 0x12345678
/thumb2-bl-bad.d
0,0 → 1,4
#name: Thumb-2 BL failure test
#source: thumb2-bl-bad.s
#ld: -Ttext 0x1000 --section-start .foo=0x1001004
#error: .*\(.text\+0x0\): relocation truncated to fit: R_ARM_THM_CALL against `bar'
/group-relocs.d
0,0 → 1,69
 
tmpdir/group-relocs: file format elf32-(little|big)arm
 
Disassembly of section .text:
 
00008000 <_start>:
8000: e28f00bc add r0, pc, #188 ; 0xbc
8004: e28f0c6e add r0, pc, #28160 ; 0x6e00
8008: e28000ec add r0, r0, #236 ; 0xec
800c: e28f08ff add r0, pc, #16711680 ; 0xff0000
8010: e2800c6e add r0, r0, #28160 ; 0x6e00
8014: e28000e4 add r0, r0, #228 ; 0xe4
8018: e2800000 add r0, r0, #0 ; 0x0
801c: e28f0cee add r0, pc, #60928 ; 0xee00
8020: e28000f0 add r0, r0, #240 ; 0xf0
8024: e28008ff add r0, r0, #16711680 ; 0xff0000
8028: e2800cee add r0, r0, #60928 ; 0xee00
802c: e28000f0 add r0, r0, #240 ; 0xf0
8030: e2800c6e add r0, r0, #28160 ; 0x6e00
8034: e59010c0 ldr r1, \[r0, #192\]
8038: e28008ff add r0, r0, #16711680 ; 0xff0000
803c: e2800c6e add r0, r0, #28160 ; 0x6e00
8040: e59010b8 ldr r1, \[r0, #184\]
8044: e5901000 ldr r1, \[r0\]
8048: e2800cee add r0, r0, #60928 ; 0xee00
804c: e59010f0 ldr r1, \[r0, #240\]
8050: e28008ff add r0, r0, #16711680 ; 0xff0000
8054: e2800cee add r0, r0, #60928 ; 0xee00
8058: e59010f0 ldr r1, \[r0, #240\]
805c: e1c026d0 ldrd r2, \[r0, #96\]
8060: e2800c6e add r0, r0, #28160 ; 0x6e00
8064: e1c029d0 ldrd r2, \[r0, #144\]
8068: e28008ff add r0, r0, #16711680 ; 0xff0000
806c: e2800c6e add r0, r0, #28160 ; 0x6e00
8070: e1c028d8 ldrd r2, \[r0, #136\]
8074: e1c020d0 ldrd r2, \[r0\]
8078: e2800cee add r0, r0, #60928 ; 0xee00
807c: e1c02fd0 ldrd r2, \[r0, #240\]
8080: e28008ff add r0, r0, #16711680 ; 0xff0000
8084: e2800cee add r0, r0, #60928 ; 0xee00
8088: e1c02fd0 ldrd r2, \[r0, #240\]
808c: ed90000c ldc 0, cr0, \[r0, #48\]
8090: e2800c6e add r0, r0, #28160 ; 0x6e00
8094: ed900018 ldc 0, cr0, \[r0, #96\]
8098: e28008ff add r0, r0, #16711680 ; 0xff0000
809c: e2800c6e add r0, r0, #28160 ; 0x6e00
80a0: ed900016 ldc 0, cr0, \[r0, #88\]
80a4: ed900000 ldc 0, cr0, \[r0\]
80a8: e2800cee add r0, r0, #60928 ; 0xee00
80ac: ed90003c ldc 0, cr0, \[r0, #240\]
80b0: e28008ff add r0, r0, #16711680 ; 0xff0000
80b4: e2800cee add r0, r0, #60928 ; 0xee00
80b8: ed90003c ldc 0, cr0, \[r0, #240\]
 
000080bc <one_group_needed_alu_pc>:
80bc: e3a00000 mov r0, #0 ; 0x0
Disassembly of section zero:
 
00000000 <one_group_needed_alu_sb>:
0: e3a00000 mov r0, #0 ; 0x0
Disassembly of section alpha:
 
0000eef0 <two_groups_needed_alu_pc>:
eef0: e3a00000 mov r0, #0 ; 0x0
Disassembly of section beta:
 
00ffeef0 <three_groups_needed_alu_pc>:
ffeef0: e3a00000 mov r0, #0 ; 0x0
#...
/vfp11-fix-vector.d
0,0 → 1,16
 
.*: .*file format elf32-(big|little)arm
 
Disassembly of section \.text:
 
00008000 <_start>:
8000: 0a000002 beq 8010 <__vfp11_veneer_0>
 
00008004 <__vfp11_veneer_0_r>:
8004: e1a02003 mov r2, r3
8008: ed927a00 flds s14, \[r2\]
800c: e12fff1e bx lr
 
00008010 <__vfp11_veneer_0>:
8010: 0e474a20 fmacseq s9, s14, s1
8014: eafffffa b 8004 <__vfp11_veneer_0_r>
/arm-rel31.s
0,0 → 1,11
# Test the R_ARM_REL31 relocation
.section .before
.global _start
_start:
.text
.rel31 0, foo
.rel31 0, _start
.rel31 1, foo
.rel31 1, _start
.section .after
foo:
/thumb-rel32.s
0,0 → 1,18
.text
.arch armv4t
.global _start
.type _start, %function
.thumb_func
_start:
.word bar - .
.word _start - .
.byte 0
.4byte (_start - .) + 1
.byte 0, 0, 0
.section .after, "ax", %progbits
.global bar
.type bar, %function
.thumb_func
bar:
.word 0
.ident "GCC: (GNU) 4.1.0 (CodeSourcery ARM)"
/tls-lib.r
0,0 → 1,10
 
.*: file format elf32-.*arm
 
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
.* R_ARM_TLS_DTPMOD32 \*ABS\*
.* R_ARM_TLS_DTPMOD32 lib_gd
.* R_ARM_TLS_DTPOFF32 lib_gd
 
 
/arm-lib-plt32.d
0,0 → 1,28
 
tmpdir/arm-lib-plt32.so: file format elf32-(little|big)arm
architecture: arm, flags 0x00000150:
HAS_SYMS, DYNAMIC, D_PAGED
start address 0x.*
 
Disassembly of section .plt:
 
.* <.plt>:
.*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
.*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func1-0x10>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
Disassembly of section .text:
 
.* <lib_func1>:
.*: e1a0c00d mov ip, sp
.*: e92dd800 push {fp, ip, lr, pc}
.*: ebfffff9 bl .* <lib_func1-0xc>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
 
.* <lib_func2>:
.*: e12fff1e bx lr
/movw-merge.d
0,0 → 1,13
 
.*: file format.*
 
Disassembly of section .text:
 
00008000 <[^>]*>:
8000: e3080013 movw r0, #32787 ; 0x8013
8004: e3400000 movt r0, #0 ; 0x0
 
00008008 <[^>]*>:
8008: f248 0013 movw r0, #32787 ; 0x8013
800c: f2c0 0000 movt r0, #0 ; 0x0
 
/tls-lib.s
0,0 → 1,22
.text
.globl foo
.type foo, %function
foo:
nop
.L2:
nop
mov pc, lr
 
.Lpool:
.word lib_gd(tlsgd) + (. - .L2 - 8)
.word lib_ld(tlsldm) + (. - .L2 - 8)
.word lib_ld(tlsldo)
 
.section .tdata,"awT"
.global lib_gd
lib_gd:
.space 4
 
.global lib_ld
lib_ld:
.space 4
/attr-merge.s
0,0 → 1,11
.cpu arm7tdmi
.fpu softvfp
.eabi_attribute 20, 1
.eabi_attribute 21, 1
.eabi_attribute 23, 3
.eabi_attribute 24, 1
.eabi_attribute 25, 1
.eabi_attribute 26, 1
.eabi_attribute 30, 6
.eabi_attribute 18, 4
.file "attr-merge.s"
/vxworks1-lib.nd
0,0 → 1,9
#...
Symbol table '\.dynsym' .*:
#...
.*: 00081400 * 0 * OBJECT * GLOBAL * DEFAULT * [0-9]+ _GLOBAL_OFFSET_TABLE_
#...
Symbol table '\.symtab' .*:
#...
.*: 00081400 * 0 * OBJECT * GLOBAL * DEFAULT * [0-9]+ _GLOBAL_OFFSET_TABLE_
#pass
/attr-merge-2b.s
0,0 → 1,11
.cpu arm7tdmi
.fpu softvfp
.eabi_attribute 20, 1
.eabi_attribute 21, 1
.eabi_attribute 23, 3
.eabi_attribute 24, 1
.eabi_attribute 25, 1
.eabi_attribute 26, 1
.eabi_attribute 30, 6
.eabi_attribute 18, 4
.file "attr-merge-2b.s"
/vxworks1-lib.s
0,0 → 1,36
.text
.globl foo
.type foo, %function
foo:
stmfd sp!, {r9, lr, pc}
ldr r9, 1f
ldr r9, [r9]
ldr r9, [r9, #__GOTT_INDEX__]
ldr r0, 1f + 4
ldr r1, [r9, r0]
add r1, r1, #1
str r1, [r9, r0]
bl slocal(PLT)
bl sglobal(PLT)
bl sexternal(PLT)
ldmfd sp!, {r9, pc}
1:
.word __GOTT_BASE__
.word x(got)
.size foo, .-foo
 
.type slocal, %function
slocal:
mov pc,lr
.size slocal, .-slocal
 
.globl sglobal
.type sglobal, %function
sglobal:
mov pc,lr
.size sglobal, .-sglobal
 
.data
.4byte slocal
 
.comm x,4,4
/arm-target2-abs.d
0,0 → 1,7
 
.*: file format.*
 
Contents of section .text:
8000 (04800000|00008004) .*
# Ignore .ARM.attributes section
#...
/arm-call2.s
0,0 → 1,24
.text
.arch armv5t
.global arm
.global t1
.global t2
.global t5
arm:
bx lr
.thumb
.thumb_func
t1:
bx lr
.thumb_func
t2:
bl t3
bl t4
.thumb_func
t5:
bl local_thumb
nop
local_thumb:
blx t3
bl _start
blx _start
/vxworks1-static.d
0,0 → 1,4
#name: VxWorks executable test 1 (static)
#source: vxworks1.s
#ld: tmpdir/libvxworks1.so -Tvxworks1.ld
#error: Dynamic sections created in non-dynamic link
/vxworks1-lib.rd
0,0 → 1,12
 
Relocation section '\.rela\.plt' at offset .* contains 2 entries:
Offset Info Type Sym\.Value Sym\. Name \+ Addend
0008140c .*16 R_ARM_JUMP_SLOT 00000000 sexternal \+ 0
00081410 .*16 R_ARM_JUMP_SLOT 00080c3c sglobal \+ 0
 
Relocation section '\.rela\.dyn' at offset .* contains 4 entries:
Offset Info Type Sym\.Value Sym\. Name \+ Addend
00081800 00000017 R_ARM_RELATIVE * 00080c38
00080c0c .*06 R_ARM_ABS12 00000000 __GOTT_INDEX__ \+ 0
00080c30 .*02 R_ARM_ABS32 00000000 __GOTT_BASE__ \+ 0
00081414 .*15 R_ARM_GLOB_DAT 00081c00 x \+ 0
/thumb1-bl.d
0,0 → 1,11
 
.*thumb1-bl: file format elf32-.*arm
 
Disassembly of section .text:
 
00001000 <_start>:
1000: f3ff fffe bl 401000 <bar>
Disassembly of section .foo:
 
00401000 <bar>:
401000: 4770 bx lr
/thumb2-bl-bad.s
0,0 → 1,22
@ Test to ensure that a Thumb-2 BL with an oversize offset fails.
 
.arch armv7
.global _start
.syntax unified
 
@ We will place the section .text at 0x1000.
 
.text
.thumb_func
 
_start:
bl bar
 
@ We will place the section .foo at 0x1001004.
 
.section .foo, "xa"
.thumb_func
 
bar:
bx lr
 
/group-relocs.s
0,0 → 1,156
@ Tests for group relocations.
@
@ Beware when editing this file: it is carefully crafted so that
@ specific PC- and SB-relative offsets arise.
@
@ Note that the gas tests have already checked that group relocations are
@ handled in the same way for local and external symbols.
 
@ We will place .text at 0x8000.
 
.text
.globl _start
 
_start:
@ ALU, PC-relative
 
@ Instructions start at .text + 0x0
add r0, r15, #:pc_g0:(one_group_needed_alu_pc)
 
@ Instructions start at .text + 0x4
add r0, r15, #:pc_g0_nc:(two_groups_needed_alu_pc)
add r0, r0, #:pc_g1:(two_groups_needed_alu_pc + 4)
 
@ Instructions start at .text + 0xc
add r0, r15, #:pc_g0_nc:(three_groups_needed_alu_pc)
add r0, r0, #:pc_g1_nc:(three_groups_needed_alu_pc + 4)
add r0, r0, #:pc_g2:(three_groups_needed_alu_pc + 8)
 
@ ALU, SB-relative
 
add r0, r0, #:sb_g0:(one_group_needed_alu_sb)
 
add r0, r15, #:sb_g0_nc:(two_groups_needed_alu_sb)
add r0, r0, #:sb_g1:(two_groups_needed_alu_sb)
 
add r0, r0, #:sb_g0_nc:(three_groups_needed_alu_sb)
add r0, r0, #:sb_g1_nc:(three_groups_needed_alu_sb)
add r0, r0, #:sb_g2:(three_groups_needed_alu_sb)
 
@ LDR, PC-relative
 
@ Instructions start at .text + 0x30
add r0, r0, #:pc_g0_nc:(two_groups_needed_ldr_pc)
ldr r1, [r0, #:pc_g1:(two_groups_needed_ldr_pc + 4)]
 
@ Instructions start at .text + 0x38
add r0, r0, #:pc_g0_nc:(three_groups_needed_ldr_pc)
add r0, r0, #:pc_g1_nc:(three_groups_needed_ldr_pc + 4)
ldr r1, [r0, #:pc_g2:(three_groups_needed_ldr_pc + 8)]
 
@ LDR, SB-relative
 
ldr r1, [r0, #:sb_g0:(one_group_needed_ldr_sb)]
 
add r0, r0, #:sb_g0_nc:(two_groups_needed_ldr_sb)
ldr r1, [r0, #:sb_g1:(two_groups_needed_ldr_sb)]
 
add r0, r0, #:sb_g0_nc:(three_groups_needed_ldr_sb)
add r0, r0, #:sb_g1_nc:(three_groups_needed_ldr_sb)
ldr r1, [r0, #:sb_g2:(three_groups_needed_ldr_sb)]
 
@ LDRS, PC-relative
 
@ Instructions start at .text + 0x5c
ldrd r2, [r0, #:pc_g0:(one_group_needed_ldrs_pc)]
 
@ Instructions start at .text + 0x60
add r0, r0, #:pc_g0_nc:(two_groups_needed_ldrs_pc)
ldrd r2, [r0, #:pc_g1:(two_groups_needed_ldrs_pc + 4)]
 
@ Instructions start at .text + 0x68
add r0, r0, #:pc_g0_nc:(three_groups_needed_ldrs_pc)
add r0, r0, #:pc_g1_nc:(three_groups_needed_ldrs_pc + 4)
ldrd r2, [r0, #:pc_g2:(three_groups_needed_ldrs_pc + 8)]
 
@ LDRS, SB-relative
 
ldrd r2, [r0, #:sb_g0:(one_group_needed_ldrs_sb)]
 
add r0, r0, #:sb_g0_nc:(two_groups_needed_ldrs_sb)
ldrd r2, [r0, #:sb_g1:(two_groups_needed_ldrs_sb)]
 
add r0, r0, #:sb_g0_nc:(three_groups_needed_ldrs_sb)
add r0, r0, #:sb_g1_nc:(three_groups_needed_ldrs_sb)
ldrd r2, [r0, #:sb_g2:(three_groups_needed_ldrs_sb)]
 
@ LDC, PC-relative
 
@ Instructions start at .text + 0x8c
ldc 0, c0, [r0, #:pc_g0:(one_group_needed_ldc_pc)]
 
@ Instructions start at .text + 0x90
add r0, r0, #:pc_g0_nc:(two_groups_needed_ldc_pc)
ldc 0, c0, [r0, #:pc_g1:(two_groups_needed_ldc_pc + 4)]
 
@ Instructions start at .text + 0x98
add r0, r0, #:pc_g0_nc:(three_groups_needed_ldc_pc)
add r0, r0, #:pc_g1_nc:(three_groups_needed_ldc_pc + 4)
ldc 0, c0, [r0, #:pc_g2:(three_groups_needed_ldc_pc + 8)]
 
@ LDC, SB-relative
 
ldc 0, c0, [r0, #:sb_g0:(one_group_needed_ldc_sb)]
 
add r0, r0, #:sb_g0_nc:(two_groups_needed_ldc_sb)
ldc 0, c0, [r0, #:sb_g1:(two_groups_needed_ldc_sb)]
 
add r0, r0, #:sb_g0_nc:(three_groups_needed_ldc_sb)
add r0, r0, #:sb_g1_nc:(three_groups_needed_ldc_sb)
ldc 0, c0, [r0, #:sb_g2:(three_groups_needed_ldc_sb)]
 
@ This point in the file is .text + 0xbc.
 
one_group_needed_alu_pc:
one_group_needed_ldrs_pc:
one_group_needed_ldc_pc:
mov r0, #0
 
@ We will place the section zero at 0x0.
 
.section zero
 
one_group_needed_alu_sb:
one_group_needed_ldr_sb:
one_group_needed_ldrs_sb:
one_group_needed_ldc_sb:
mov r0, #0
 
@ We will place the section alpha at 0xeef0.
 
.section alpha
 
two_groups_needed_alu_sb:
two_groups_needed_ldr_sb:
two_groups_needed_ldrs_sb:
two_groups_needed_ldc_sb:
two_groups_needed_alu_pc:
two_groups_needed_ldr_pc:
two_groups_needed_ldrs_pc:
two_groups_needed_ldc_pc:
mov r0, #0
 
@ We will place the section beta at 0xffeef0.
 
.section beta
 
three_groups_needed_alu_sb:
three_groups_needed_ldr_sb:
three_groups_needed_ldrs_sb:
three_groups_needed_ldc_sb:
three_groups_needed_alu_pc:
three_groups_needed_ldr_pc:
three_groups_needed_ldrs_pc:
three_groups_needed_ldc_pc:
mov r0, #0
 
/vfp11-fix-vector.s
0,0 → 1,8
.arm
.text
.globl _start
_start:
fmacseq s9, s14, s1
mov r2,r3
flds s14, [r2]
bx lr
/thumb2-b-interwork.d
0,0 → 1,19
 
.*thumb2-b-interwork: file format elf32-.*arm
 
Disassembly of section .text:
 
00008000 <_start>:
8000: f000 b802 b.w 8008 <__bar_from_thumb>
 
00008004 <bar>:
8004: e12fff1e bx lr
Disassembly of section .glue_7t:
 
00008008 <__bar_from_thumb>:
8008: 4778 bx pc
800a: 46c0 nop \(mov r8, r8\)
 
0000800c <__bar_change_to_arm>:
800c: eafffffc b 8004 <bar>
 
/arm-lib-plt32.r
0,0 → 1,8
 
tmpdir/arm-lib-plt32.so: file format elf32-(little|big)arm
 
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
.* R_ARM_JUMP_SLOT app_func2
 
 
/arm-target2.s
0,0 → 1,6
# Test the R_ARM_TARGET2 relocation
.text
.global _start
_start:
.word foo(target2)
foo:
/arm-lib-plt32.s
0,0 → 1,17
.text
 
.globl lib_func1
.type lib_func1, %function
lib_func1:
mov ip, sp
stmdb sp!, {r11, ip, lr, pc}
bl app_func2(PLT)
ldmia sp, {r11, sp, lr}
bx lr
.size lib_func1, . - lib_func1
 
.globl lib_func2
.type lib_func2, %function
lib_func2:
bx lr
.size lib_func2, . - lib_func2
/movw-merge.s
0,0 → 1,20
.arch armv7-a
.syntax unified
.text
.global _start
.type _start, %function
_start:
movw r0, #:lower16:.LC0
movt r0, #:upper16:.LC0
.thumb
.global tfunc
.type tfunc, %function
tfunc:
movw r0, #:lower16:.LC0
movt r0, #:upper16:.LC0
 
.section .rodata.str1.4,"aMS",%progbits,1
.align 2
.ascii "pad"
.LC0:
.ascii "inner: cont \000"
/group-relocs-ldc-bad.d
0,0 → 1,4
#name: LDC group relocations failure test
#source: group-relocs-ldc-bad.s
#ld: -Ttext 0x8000 --section-start foo=0x118400
#error: Overflow whilst splitting 0x110400 for group relocation
/arm-app-abs32.d
0,0 → 1,29
 
tmpdir/arm-app-abs32: file format elf32-(little|big)arm
architecture: arm, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address .*
 
Disassembly of section .plt:
 
.* <.plt>:
.*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
.*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x10>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .* .*
.*: e28fc6.* add ip, pc, #.* ; .*
.*: e28cca.* add ip, ip, #.* ; .*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
Disassembly of section .text:
 
.* <_start>:
.*: e1a0c00d mov ip, sp
.*: e92dd800 push {fp, ip, lr, pc}
.*: e59f0004 ldr r0, \[pc, #4\] ; .* <_start\+0x14>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
.*: .* .*
 
.* <app_func2>:
.*: e12fff1e bx lr
/arm-pic-veneer.d
0,0 → 1,17
 
.*: file format.*
 
Disassembly of section .text:
 
00008000 <_start>:
8000: ea000000 b 8008 <__foo_from_arm>
 
00008004 <foo>:
8004: 46c0 nop \(mov r8, r8\)
8006: 4770 bx lr
 
00008008 <__foo_from_arm>:
8008: e59fc004 ldr ip, \[pc, #4\] ; 8014 <__foo_from_arm\+0xc>
800c: e08cc00f add ip, ip, pc
8010: e12fff1c bx ip
8014: fffffff1 .word 0xfffffff1
/thumb1-bl.s
0,0 → 1,22
@ Test to ensure that a Thumb-1 BL works.
 
.arch armv5t
.global _start
.syntax unified
 
@ We will place the section .text at 0x1000.
 
.text
.thumb_func
 
_start:
bl bar
 
@ We will place the section .foo at 0x401000.
 
.section .foo, "xa"
.thumb_func
 
bar:
bx lr
 
/mixed-app-v5.d
0,0 → 1,56
 
tmpdir/mixed-app-v5: file format elf32-(little|big)arm
architecture: arm, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x.*
 
Disassembly of section .plt:
 
.* <.plt>:
.*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
.*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x1c>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
Disassembly of section .text:
 
.* <_start>:
.*: e1a0c00d mov ip, sp
.*: e92dd800 push {fp, ip, lr, pc}
.*: eb000004 bl .* <app_func>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
.*: e1a00000 nop \(mov r0,r0\)
.*: e1a00000 nop \(mov r0,r0\)
.*: e1a00000 nop \(mov r0,r0\)
 
.* <app_func>:
.*: e1a0c00d mov ip, sp
.*: e92dd800 push {fp, ip, lr, pc}
.*: ebfffff. bl .*
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
.*: e1a00000 nop \(mov r0,r0\)
.*: e1a00000 nop \(mov r0,r0\)
.*: e1a00000 nop \(mov r0,r0\)
 
.* <app_func2>:
.*: e12fff1e bx lr
.*: e1a00000 nop \(mov r0,r0\)
.*: e1a00000 nop \(mov r0,r0\)
.*: e1a00000 nop \(mov r0,r0\)
 
.* <app_tfunc>:
.*: b500 push {lr}
.*: f7ff efc. blx .* <_start-0x..>
.*: bd00 pop {pc}
.*: 4770 bx lr
.*: 46c0 nop \(mov r8, r8\)
.*: 46c0 nop \(mov r8, r8\)
.*: 46c0 nop \(mov r8, r8\)
/vxworks2-static.sd
0,0 → 1,9
#...
Elf file type is EXEC \(Executable file\)
Entry point 0x80000
#...
Program Headers:
Type .*
LOAD .* 0x00080000 0x00080000 .* R E 0x1000
 
#...
/vfp11-fix-none.d
0,0 → 1,9
 
.*: .*file format elf32-(big|little)arm
 
Disassembly of section \.text:
 
00008000 <_start>:
8000: ee474a20 \.word 0xee474a20
8004: ed927a00 \.word 0xed927a00
8008: e12fff1e bx lr
/tls-app.d
0,0 → 1,18
 
.*: file format elf32-.*arm
architecture: arm, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x00008204
 
Disassembly of section .text:
 
00008204 <foo>:
8204: e1a00000 nop \(mov r0,r0\)
8208: e1a00000 nop \(mov r0,r0\)
820c: e1a0f00e mov pc, lr
8210: 000080bc .word 0x000080bc
8214: 000080b4 .word 0x000080b4
8218: 000080ac .word 0x000080ac
821c: 00000004 .word 0x00000004
8220: 000080c4 .word 0x000080c4
8224: 00000014 .word 0x00000014
/thumb2-b-interwork.s
0,0 → 1,20
@ Test to ensure that a Thumb-2 B.W can branch to an ARM funtion.
 
.arch armv7-a
.global _start
.syntax unified
.text
.thumb_func
 
_start:
b.w bar
 
@ Put this in a separate section to force the assembler to generate a reloc
 
.arm
.section .after, "xa"
.global bar
.type bar, %function
bar:
bx lr
 
/callweak.d
0,0 → 1,17
 
.*: file format.*
 
Disassembly of section .far:
 
12340000 <[^>]*>:
12340000: eaffffff b 12340004 <[^>]*>
12340004: 0affffff beq 12340008 <[^>]*>
 
12340008 <[^>]*>:
12340008: e000 b.n 1234000c <[^>]*>
1234000a: bf00 nop
1234000c: 2000 movs r0, #0
1234000e: e000 b.n 12340012 <[^>]*>
12340010: bf00 nop
12340012: 4770 bx lr
 
/armthumb-lib.d
0,0 → 1,44
 
tmpdir/armthumb-lib.so: file format elf32-(little|big)arm
architecture: arm, flags 0x00000150:
HAS_SYMS, DYNAMIC, D_PAGED
start address 0x.*
 
Disassembly of section .plt:
 
.* <.plt>:
.*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
.*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func1-0x1c>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
Disassembly of section .text:
 
.* <lib_func1>:
.*: e1a0c00d mov ip, sp
.*: e92dd800 push {fp, ip, lr, pc}
.*: ebfffff. bl .* <lib_func1-0x..?>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
.*: e1a00000 nop \(mov r0,r0\)
.*: e1a00000 nop \(mov r0,r0\)
.*: e1a00000 nop \(mov r0,r0\)
 
.* <__real_lib_func2>:
.*: 4770 bx lr
.*: 46c0 nop \(mov r8, r8\)
.*: 46c0 nop \(mov r8, r8\)
.*: 46c0 nop \(mov r8, r8\)
.*: 46c0 nop \(mov r8, r8\)
.*: 46c0 nop \(mov r8, r8\)
.*: 46c0 nop \(mov r8, r8\)
.*: 46c0 nop \(mov r8, r8\)
 
.* <lib_func2>:
.*: e59fc004 ldr ip, \[pc, #4\] ; .* <lib_func2\+0xc>
.*: e08cc00f add ip, ip, pc
.*: e12fff1c bx ip
.*: ffffffe5 .*
/arm-app-abs32.r
0,0 → 1,8
 
tmpdir/arm-app-abs32: file format elf32-(little|big)arm
 
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
.* R_ARM_JUMP_SLOT lib_func1
 
 
/arm-lib.d
0,0 → 1,28
 
tmpdir/arm-lib.so: file format elf32-(little|big)arm
architecture: arm, flags 0x00000150:
HAS_SYMS, DYNAMIC, D_PAGED
start address 0x.*
 
Disassembly of section .plt:
 
.* <.plt>:
.*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
.*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func1-0x10>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.*: e28fc6.* add ip, pc, #.* ; 0x.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!
Disassembly of section .text:
 
.* <lib_func1>:
.*: e1a0c00d mov ip, sp
.*: e92dd800 push {fp, ip, lr, pc}
.*: ebfffff9 bl .* <lib_func1-0xc>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
 
.* <lib_func2>:
.*: e12fff1e bx lr
/vxworks1.s
0,0 → 1,14
.text
.globl _start
.type _start, %function
_start:
bl foo
bl sexternal
b sglobal
.size _start, .-_start
 
.globl sexternal
.type sexternal, %function
sexternal:
mov pc, lr
.size sexternal, .-sexternal
/group-relocs-ldc-bad.s
0,0 → 1,19
@ Test intended to fail for LDC group relocations.
 
@ We will place .text at 0x8000.
 
.text
.globl _start
 
_start:
add r0, r0, #:pc_g0_nc:(bar)
ldc 0, c0, [r0, #:pc_g1:(bar + 4)]
 
@ We will place the section foo at 0x118400.
@ (The relocations above would be OK if it were at 0x118200, for example.)
 
.section foo
 
bar:
mov r0, #0
 
/group-relocs-alu-bad.d
0,0 → 1,4
#name: ALU group relocations failure test
#source: group-relocs-alu-bad.s
#ld: -Ttext 0x8000 --section-start foo=0x9010
#error: Overflow whilst splitting 0x1010 for group relocation
/arm-app-abs32.s
0,0 → 1,16
.text
.globl _start
_start:
mov ip, sp
stmdb sp!, {r11, ip, lr, pc}
ldr a1, .Lval
ldmia sp, {r11, sp, lr}
bx lr
 
.Lval:
.long lib_func1
 
.globl app_func2
app_func2:
bx lr
 
/vxworks1.rd
0,0 → 1,19
 
Relocation section '\.rela\.plt' at offset .* contains 2 entries:
Offset Info Type Sym\.Value Sym\. Name \+ Addend
0008140c .*16 R_ARM_JUMP_SLOT 00080810 sglobal \+ 0
00081410 .*16 R_ARM_JUMP_SLOT 00080828 foo \+ 0
 
Relocation section '\.rela\.text' at offset .* contains 3 entries:
Offset Info Type Sym.Value Sym. Name \+ Addend
00080c00 .*01 R_ARM_PC24 00080800 \.plt \+ 20
00080c04 .*01 R_ARM_PC24 00080c0c sexternal \+ fffffff8
00080c08 .*01 R_ARM_PC24 00080800 \.plt \+ 8
 
Relocation section '\.rela\.plt\.unloaded' at offset .* contains 5 entries:
Offset Info Type Sym\.Value Sym\. Name \+ Addend
0008080c .*02 R_ARM_ABS32 00081400 _GLOBAL_OFFSET_TABLE_ \+ 0
00080818 .*02 R_ARM_ABS32 00081400 _GLOBAL_OFFSET_TABLE_ \+ c
0008140c .*02 R_ARM_ABS32 00080800 _PROCEDURE_LINKAGE_TAB.* \+ 0
00080830 .*02 R_ARM_ABS32 00081400 _GLOBAL_OFFSET_TABLE_ \+ 10
00081410 .*02 R_ARM_ABS32 00080800 _PROCEDURE_LINKAGE_TAB.* \+ 0
/arm-call.d
0,0 → 1,56
 
.*: file format.*
 
Disassembly of section .text:
 
00008000 <_start>:
8000: eb00000d bl 803c <arm>
8004: fa00000d blx 8040 <t1>
8008: fb00000c blx 8042 <t2>
800c: fb00000d blx 804a <t5>
8010: fa00000a blx 8040 <t1>
8014: fb000009 blx 8042 <t2>
8018: ea00000f b 805c <__t1_from_arm>
801c: ea000010 b 8064 <__t2_from_arm>
8020: 1b00000d blne 805c <__t1_from_arm>
8024: 1b00000e blne 8064 <__t2_from_arm>
8028: 1b000003 blne 803c <arm>
802c: eb000002 bl 803c <arm>
8030: faffffff blx 8034 <thumblocal>
 
00008034 <thumblocal>:
8034: 4770 bx lr
 
00008036 <t3>:
8036: 4770 bx lr
 
00008038 <t4>:
8038: 4770 bx lr
803a: 46c0 nop \(mov r8, r8\)
 
0000803c <arm>:
803c: e12fff1e bx lr
 
00008040 <t1>:
8040: 4770 bx lr
 
00008042 <t2>:
8042: f7ff fff8 bl 8036 <t3>
8046: f7ff fff7 bl 8038 <t4>
 
0000804a <t5>:
804a: f000 f801 bl 8050 <local_thumb>
804e: 46c0 nop \(mov r8, r8\)
 
00008050 <local_thumb>:
8050: f7ff fff1 bl 8036 <t3>
8054: f7ff efd4 blx 8000 <_start>
8058: f7ff efd2 blx 8000 <_start>
 
0000805c <__t1_from_arm>:
805c: e51ff004 ldr pc, \[pc, #-4\] ; 8060 <__t1_from_arm\+0x4>
8060: 00008041 .word 0x00008041
 
00008064 <__t2_from_arm>:
8064: e51ff004 ldr pc, \[pc, #-4\] ; 8068 <__t2_from_arm\+0x4>
8068: 00008043 .word 0x00008043
/vxworks2.sd
0,0 → 1,13
#...
Elf file type is EXEC \(Executable file\)
Entry point 0x80400
#...
Program Headers:
Type .*
PHDR .*
#...
LOAD .* 0x00080000 0x00080000 .* R E 0x1000
LOAD .* 0x00081000 0x00081000 .* RW 0x1000
DYNAMIC .*
 
#...
/arm-pic-veneer.s
0,0 → 1,14
.text
.arm
.global _start
.type _start, %function
_start:
b foo
 
.thumb
.global foo
.type foo, %function
foo:
nop
bx lr
 
/gc-unwind.d
0,0 → 1,5
 
.*: file format.*
 
Contents of section .data:
[^ ]* 22222222 .*
/arm-target2-got-rel.d
0,0 → 1,9
 
.*: file format.*
 
Contents of section .text:
8000 (00100000|00001000) .*
Contents of section .got:
9000 (04800000|00008004) .*
# Ignore .ARM.attributes section
#...
/thumb2-bl.d
0,0 → 1,11
 
.*thumb2-bl: file format elf32-.*arm
 
Disassembly of section .text:
 
00001000 <_start>:
1000: f3ff d7fe bl 1001000 <bar>
Disassembly of section .foo:
 
01001000 <bar>:
1001000: 4770 bx lr

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