OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/gnu-src/binutils-2.18.50/ld/testsuite/ld-spu
    from Rev 38 to Rev 156
    ↔ Reverse comparison
  •

Rev 38 → Rev 156

/embed.rd
0,0 → 1,16
 
Relocation section '\.rela\.rodata\.speelf' at .* contains 3 entries:
Offset Info Type Sym\. Value Symbol's Name \+ Addend
00000184 00000601 R_PPC_ADDR32 00000000 main \+ 0
000001a4 00000901 R_PPC_ADDR32 00000000 foo \+ 0
000001b4 00000701 R_PPC_ADDR32 00000000 blah \+ 0
 
Relocation section '\.rela\.data' at .* contains 2 entries:
Offset Info Type Sym\. Value Symbol's Name \+ Addend
00000004 00000201 R_PPC_ADDR32 00000000 \.rodata\.speelf \+ 0
00000008 00000401 R_PPC_ADDR32 00000000 \.data\.spetoe \+ 0
 
Relocation section '\.rela\.data\.spetoe' at .* contains 2 entries:
Offset Info Type Sym\. Value Symbol's Name \+ Addend
00000004 00000201 R_PPC_ADDR32 00000000 \.rodata\.speelf \+ 0
00000014 00000a01 R_PPC_ADDR32 00000000 bar \+ 0
/ovl.s
0,0 → 1,82
.text
.p2align 2
.globl _start
_start:
ai sp,sp,-32
xor lr,lr,lr
stqd lr,0(sp)
stqd lr,16(sp)
brsl lr,f1_a1
brsl lr,f2_a1
brsl lr,f1_a2
ila 9,f2_a2
bisl lr,9
ai sp,sp,32
br _start
 
.type f0,@function
f0:
bi lr
.size f0,.-f0
 
.section .ov_a1,"ax",@progbits
.p2align 2
.global f1_a1
.type f1_a1,@function
f1_a1:
br f3_a1
.size f1_a1,.-f1_a1
 
.global f2_a1
.type f2_a1,@function
f2_a1:
ila 3,f4_a1
bi lr
.size f2_a1,.-f2_a1
 
.global f3_a1
.type f3_a1,@function
f3_a1:
bi lr
.size f3_a1,.-f3_a1
 
.global f4_a1
.type f4_a1,@function
f4_a1:
bi lr
.size f4_a1,.-f4_a1
 
 
.section .ov_a2,"ax",@progbits
.p2align 2
.global f1_a2
.type f1_a2,@function
f1_a2:
stqd lr,16(sp)
stqd sp,-32(sp)
ai sp,sp,-32
brsl lr,f0
brsl lr,f1_a1
brsl lr,f3_a2
lqd lr,48(sp)
ai sp,sp,32
bi lr
.size f1_a2,.-f1_a2
 
.global f2_a2
.type f2_a2,@function
f2_a2:
ilhu 3,f4_a2@h
iohl 3,f4_a2@l
bi lr
.size f2_a2,.-f2_a2
 
.type f3_a2,@function
f3_a2:
bi lr
.size f3_a2,.-f3_a2
 
.type f4_a2,@function
f4_a2:
br f3_a2
.size f4_a2,.-f4_a2
/ovl.d
0,0 → 1,182
#source: ovl.s
#ld: -N -T ovl1.lnk -T ovl.lnk --emit-relocs
#objdump: -D -r
 
.*elf32-spu
 
Disassembly of section \.text:
 
00000100 <_start>:
.* ai \$1,\$1,-32
.* xor \$0,\$0,\$0
.* stqd \$0,0\(\$1\)
.* stqd \$0,16\(\$1\)
.* brsl \$0,.* <00000000\.ovl_call\.f1_a1>.*
.*SPU_REL16 f1_a1
.* brsl \$0,.* <00000000\.ovl_call\.f2_a1>.*
.*SPU_REL16 f2_a1
.* brsl \$0,.* <00000000\.ovl_call\.f1_a2>.*
.*SPU_REL16 f1_a2
#.* ila \$9,328 # 148
.* ila \$9,352 # 160
.*SPU_ADDR18 f2_a2
.* bisl \$0,\$9
.* ai \$1,\$1,32 # 20
.* br 100 <_start> # 100
.*SPU_REL16 _start
 
0000012c <f0>:
.* bi \$0
 
#00000130 <00000000\.ovl_call\.f1_a1>:
#.* brsl \$75,.* <__ovly_load>.*
#.*00 04 04 00.*
#
#00000138 <00000000\.ovl_call\.f2_a1>:
#.* brsl \$75,.* <__ovly_load>.*
#.*00 04 04 04.*
#
#00000140 <00000000\.ovl_call\.f1_a2>:
#.* brsl \$75,.* <__ovly_load>.*
#.*00 08 04 00.*
#
#00000148 <00000000\.ovl_call\.f2_a2>:
#.* brsl \$75,.* <__ovly_load>.*
#.*00 08 04 24.*
#
#00000150 <00000000\.ovl_call\.f4_a1>:
#.* brsl \$75,.* <__ovly_load>.*
#.*00 04 04 10.*
#
#00000158 <00000000.ovl_call.14:8>:
#.* brsl \$75,.* <__ovly_load>.*
#.*00 08 04 34.*
 
00000130 <00000000\.ovl_call\.f1_a1>:
.* ila \$78,1
.* lnop
.* ila \$79,1024 # 400
.* br .* <__ovly_load>.*
 
00000140 <00000000\.ovl_call\.f2_a1>:
.* ila \$78,1
.* lnop
.* ila \$79,1028 # 404
.* br .* <__ovly_load>.*
 
00000150 <00000000.ovl_call.f1_a2>:
.* ila \$78,2
.* lnop
.* ila \$79,1024 # 400
.* br .* <__ovly_load>.*
 
00000160 <00000000\.ovl_call\.f2_a2>:
.* ila \$78,2
.* lnop
.* ila \$79,1060 # 424
.* br .* <__ovly_load>.*
 
00000170 <00000000\.ovl_call\.f4_a1>:
.* ila \$78,1
.* lnop
.* ila \$79,1040 # 410
.* br .* <__ovly_load>.*
 
00000180 <00000000.ovl_call.14:8>:
.* ila \$78,2
.* lnop
.* ila \$79,1076 # 434
.* br .* <__ovly_load>.*
 
#...
[0-9a-f]+ <__ovly_return>:
#...
[0-9a-f]+ <__ovly_load>:
#...
[0-9a-f]+ <_ovly_debug_event>:
#...
Disassembly of section \.ov_a1:
 
00000400 <f1_a1>:
.* br .* <f3_a1>.*
.*SPU_REL16 f3_a1
 
00000404 <f2_a1>:
#.* ila \$3,336 # 150
.* ila \$3,368 # 170
.*SPU_ADDR18 f4_a1
.* bi \$0
 
0000040c <f3_a1>:
.* bi \$0
 
00000410 <f4_a1>:
.* bi \$0
\.\.\.
Disassembly of section \.ov_a2:
 
00000400 <f1_a2>:
.* stqd \$0,16\(\$1\)
.* stqd \$1,-32\(\$1\)
.* ai \$1,\$1,-32
.* brsl \$0,12c <f0> # 12c
.*SPU_REL16 f0
.* brsl \$0,130 <00000000\.ovl_call\.f1_a1> # 130
.*SPU_REL16 f1_a1
.* brsl \$0,430 <f3_a2> # 430
.*SPU_REL16 f3_a2
.* lqd \$0,48\(\$1\) # 30
.* ai \$1,\$1,32 # 20
.* bi \$0
 
00000424 <f2_a2>:
.* ilhu \$3,0
.*SPU_ADDR16_HI f4_a2
#.* iohl \$3,344 # 158
.* iohl \$3,384 # 180
.*SPU_ADDR16_LO f4_a2
.* bi \$0
 
00000430 <f3_a2>:
.* bi \$0
 
00000434 <f4_a2>:
.* br .* <f3_a2>.*
.*SPU_REL16 f3_a2
\.\.\.
Disassembly of section .data:
 
00000440 <_ovly_table-0x10>:
440: 00 00 00 00 .*
444: 00 00 00 01 .*
\.\.\.
00000450 <_ovly_table>:
450: 00 00 04 00 .*
454: 00 00 00 20 .*
# 458: 00 00 03 40 .*
458: 00 00 03 70 .*
45c: 00 00 00 01 .*
460: 00 00 04 00 .*
464: 00 00 00 40 .*
# 468: 00 00 03 60 .*
468: 00 00 03 90 .*
46c: 00 00 00 01 .*
 
00000470 <_ovly_buf_table>:
470: 00 00 00 00 .*
 
Disassembly of section \.toe:
 
00000480 <_EAR_>:
\.\.\.
Disassembly of section \.note\.spu_name:
 
.* <\.note\.spu_name>:
.*: 00 00 00 08 .*
.*: 00 00 00 0c .*
.*: 00 00 00 01 .*
.*: 53 50 55 4e .*
.*: 41 4d 45 00 .*
.*: 74 6d 70 64 .*
.*: 69 72 2f 64 .*
.*: 75 6d 70 00 .*
/spu.exp
0,0 → 1,94
# Expect script for ld-spu tests
# Copyright (C) 2006, 2007 Free Software Foundation
#
# This file is part of the GNU Binutils.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
# MA 02110-1301, USA.
#
 
if { ![istarget "spu-*-*"] } {
return
}
 
proc embed_test { } {
global subdir srcdir
global AS ASFLAGS LD LDFLAGS READELF READELFFLAGS
 
set cmd "$AS $ASFLAGS -o tmpdir/ear.o $srcdir/$subdir/ear.s"
send_log "$cmd\n"
set cmdret [catch "exec $cmd" comp_output]
set comp_output [prune_warnings $comp_output]
if { $cmdret != 0 || $comp_output != ""} then {
send_log "$comp_output\n"
verbose "$comp_output" 3
fail "ear assembly"
return
}
 
set cmd "$LD $LDFLAGS -o tmpdir/ear tmpdir/ear.o"
send_log "$cmd\n"
set cmdret [catch "exec $cmd" comp_output]
set comp_output [prune_warnings $comp_output]
if { $cmdret != 0 || $comp_output != ""} then {
send_log "$comp_output\n"
verbose "$comp_output" 3
fail "ear link"
return
}
 
set cmd "sh $srcdir/../../binutils/embedspu.sh -m32 ear tmpdir/ear tmpdir/embed.o"
send_log "$cmd\n"
set cmdret [catch "exec $cmd" comp_output]
set comp_output [prune_warnings $comp_output]
if { $cmdret != 0 || $comp_output != ""} then {
send_log "$comp_output\n"
verbose "$comp_output" 3
if { [regexp "unknown pseudo-op: `.reloc'" $comp_output] } {
untested "ear embedspu"
return
}
fail "ear embedspu"
return
}
 
set cmd "$READELF $READELFFLAGS -r --wide tmpdir/embed.o > tmpdir/embed.out"
send_log "$cmd\n"
set cmdret [catch "exec $cmd" comp_output]
set comp_output [prune_warnings $comp_output]
if { $cmdret != 0 || $comp_output != ""} then {
send_log "$comp_output\n"
verbose "$comp_output" 3
fail "ear embed readelf"
return
}
 
if { [regexp_diff "tmpdir/embed.out" $srcdir/$subdir/embed.rd] } then {
fail "ear embed output"
return
}
 
pass "ear embed"
}
 
set rd_test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
foreach sputest $rd_test_list {
verbose [file rootname $sputest]
run_dump_test [file rootname $sputest]
}
 
if { [isbuild "powerpc*-*-linux*"] } {
embed_test
}
/ovl.lnk
0,0 → 1,7
SECTIONS
{
. = SIZEOF_HEADERS;
.text : { *(.text) *(.stub) }
.data : { *(.data) *(.ovtab) }
.bss : { *(.bss) }
}
/ovl2.s
0,0 → 1,52
.text
.p2align 2
.global _start
_start:
brsl lr,f1_a1
brsl lr,setjmp
br _start
 
.type setjmp,@function
.global setjmp
setjmp:
bi lr
.size setjmp,.-setjmp
 
.type longjmp,@function
longjmp:
bi lr
.size longjmp,.-longjmp
 
.word .L1
 
.section .ov_a1,"ax",@progbits
.p2align 2
.global f1_a1
.type f1_a1,@function
f1_a1:
bi lr
.size f1_a1,.-f1_a1
 
.L1:
.word .L1, .L2, .L3
.L2:
 
.section .ov_a2,"ax",@progbits
.p2align 2
.type f1_a2,@function
f1_a2:
br longjmp
.size f1_a2,.-f1_a2
 
.L3:
.word .L2, .L4
.L4:
 
.section .nonalloc,"",@progbits
.word .L1,.L2,.L3,.L4
 
_SPUEAR_f1_a2 = f1_a2
.global _SPUEAR_f1_a2
 
_SPUEAR_version=3
.global _SPUEAR_version
/ovl1.lnk
0,0 → 1,9
SECTIONS
{
OVERLAY 0x400 :
{
.ov_a1 { *(.ov_a1) }
.ov_a2 { *(.ov_a2) }
}
}
INSERT AFTER .text;
/ovl2.d
0,0 → 1,145
#source: ovl2.s
#ld: -N -T ovl2.lnk -T ovl.lnk --emit-relocs
#objdump: -D -r
 
.*elf32-spu
 
Disassembly of section \.text:
 
00000100 <_start>:
.* brsl \$0,.* <00000000\.ovl_call\.f1_a1>.*
.*SPU_REL16 f1_a1
.* brsl \$0,.* <00000000\.ovl_call\.setjmp>.*
.*SPU_REL16 setjmp
.* br 100 <_start> # 100
.*SPU_REL16 _start
 
0000010c <setjmp>:
.* bi \$0
 
00000110 <longjmp>:
.* bi \$0
.*00 00 01 40.*
.*SPU_ADDR32 \.ov_a1\+0x14
\.\.\.
 
#00000118 <00000000\.ovl_call.f1_a1>:
#.* brsl \$75,.* <__ovly_load>.*
#.*00 04 04 00.*
#
#00000120 <00000000\.ovl_call.setjmp>:
#.* brsl \$75,.* <__ovly_load>.*
#.*00 00 01 0c.*
#
#00000128 <_SPUEAR_f1_a2>:
#.* brsl \$75,.* <__ovly_load>.*
#.*00 08 04 00.*
 
00000120 <00000000\.ovl_call.f1_a1>:
.* ila \$78,1
.* lnop
.* ila \$79,1040 # 410
.* br .* <__ovly_load>.*
 
00000130 <00000000\.ovl_call.setjmp>:
.* ila \$78,0
.* lnop
.* ila \$79,268 # 10c
.* br .* <__ovly_load>.*
 
00000140 <00000000\.ovl_call\.13:5>:
.* ila \$78,1
.* lnop
.* ila \$79,1044 # 414
.* br .* <__ovly_load>.*
 
00000150 <_SPUEAR_f1_a2>:
.* ila \$78,2
.* lnop
.* ila \$79,1040 # 410
.* br .* <__ovly_load>.*
 
#...
Disassembly of section \.ov_a1:
 
00000400 <00000001\.ovl_call\.14:6>:
.* ila \$78,2
.* lnop
.* ila \$79,1044 # 414
.* br .* <__ovly_load>.*
 
00000410 <f1_a1>:
.* bi \$0
.*00 00 04 14.*
.*SPU_ADDR32 \.ov_a1\+0x14
.*00 00 04 20.*
.*SPU_ADDR32 \.ov_a1\+0x20
.*00 00 04 00.*
.*SPU_ADDR32 \.ov_a2\+0x14
 
Disassembly of section \.ov_a2:
 
00000400 <00000002\.ovl_call\.13:5>:
.* ila \$78,1
.* lnop
.* ila \$79,1056 # 420
.* br .* <__ovly_load>.*
 
00000410 <f1_a2>:
.* br .* <longjmp>.*
.*SPU_REL16 longjmp
.*00 00 04 00.*
.*SPU_ADDR32 \.ov_a1\+0x20
.*00 00 04 1c.*
.*SPU_ADDR32 \.ov_a2\+0x1c
.*00 00 00 00.*
 
Disassembly of section \.data:
 
00000420 <_ovly_table-0x10>:
.*00 00 00 00 .*
.*00 00 00 01 .*
\.\.\.
00000430 <_ovly_table>:
.*00 00 04 00 .*
.*00 00 00 20 .*
#.*00 00 03 10 .*
.*00 00 03 40 .*
.*00 00 00 01 .*
.*00 00 04 00 .*
.*00 00 00 20 .*
#.*00 00 03 20 .*
.*00 00 03 60 .*
.*00 00 00 01 .*
 
00000450 <_ovly_buf_table>:
.*00 00 00 00 .*
 
Disassembly of section \.toe:
 
00000460 <_EAR_>:
\.\.\.
 
Disassembly of section .nonalloc:
 
00000000 <.nonalloc>:
.*00 00 04 14.*
.*SPU_ADDR32 \.ov_a1\+0x14
.*00 00 04 20.*
.*SPU_ADDR32 \.ov_a1\+0x20
.*00 00 04 14.*
.*SPU_ADDR32 \.ov_a2\+0x14
.*00 00 04 1c.*
.*SPU_ADDR32 \.ov_a2\+0x1c
 
Disassembly of section \.note\.spu_name:
 
.* <\.note\.spu_name>:
.*: 00 00 00 08 .*
.*: 00 00 00 0c .*
.*: 00 00 00 01 .*
.*: 53 50 55 4e .*
.*: 41 4d 45 00 .*
.*: 74 6d 70 64 .*
.*: 69 72 2f 64 .*
.*: 75 6d 70 00 .*
/ovl2.lnk
0,0 → 1,10
SECTIONS
{
OVERLAY 0x400 :
{
.ov_a1 { *(.ov_a1) }
.ov_a2 { *(.ov_a2) }
.empty { empty.o?(.text) }
}
}
INSERT BEFORE .data;
/ear.s
0,0 → 1,25
.text
.global _start
_start:
br _start
 
#test old-style toe _EAR_ syms
.section .toe,"a",@nobits
_EAR_:
.space 16
_EAR_bar:
.space 16
 
#test new-style _EAR_ syms
.data
_EAR_main:
.space 16
 
#new ones don't need to be 16 bytes apart
.space 16
_EAR_foo:
.space 16
 
.section .data.blah,"aw",@progbits
_EAR_blah:
.space 16
/ear.d
0,0 → 1,30
#as:
#objdump: -Dr
#name: ear
 
.*: +file format .*
 
Disassembly of section \.text:
 
0+00 <_start>:
0: 32 00 00 00 br 0
0: SPU_REL16 _start
 
Disassembly of section \.data:
 
0+00 <_EAR_main>:
\.\.\.
 
0+20 <_EAR_foo>:
\.\.\.
Disassembly of section \.toe:
 
0+00 <_EAR_>:
\.\.\.
 
0+10 <_EAR_bar>:
\.\.\.
Disassembly of section \.data\.blah:
 
0+00 <_EAR_blah>:
\.\.\.

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