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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/gnu-src/gdb-6.8/include/opcode
    from Rev 157 to Rev 225
    ↔ Reverse comparison
  •

Rev 157 → Rev 225

/i386.h
1,6 → 1,6
/* opcode/i386.h -- Intel 80386 opcode macros
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
Free Software Foundation, Inc.
 
This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
35,6 → 35,9
 
The affected opcode map is dceX, dcfX, deeX, defX. */
 
#ifndef OPCODE_I386_H
#define OPCODE_I386_H
 
#ifndef SYSV386_COMPAT
/* Set non-zero for broken, compatible instructions. Set to zero for
non-broken opcodes at your peril. gcc generates SystemV/386
56,6 → 59,11
/* The opcode for the fwait instruction, which disassembler treats as a
prefix when it can. */
#define FWAIT_OPCODE 0x9b
 
/* Instruction prefixes.
NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as
part of the opcode. Other prefixes may still appear between them
and the 0x0f part of the opcode. */
#define ADDR_PREFIX_OPCODE 0x67
#define DATA_PREFIX_OPCODE 0x66
#define LOCK_PREFIX_OPCODE 0xf0
72,8 → 80,14
#define NOP_OPCODE (char) 0x90
 
/* register numbers */
#define EAX_REG_NUM 0
#define ECX_REG_NUM 1
#define EDX_REG_NUM 2
#define EBX_REG_NUM 3
#define ESP_REG_NUM 4
#define EBP_REG_NUM 5
#define ESP_REG_NUM 4
#define ESI_REG_NUM 6
#define EDI_REG_NUM 7
 
/* modrm_byte.regmem for twobyte escape */
#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
87,9 → 101,22
#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
 
/* Extract fields from the mod/rm byte. */
#define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3)
#define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7)
#define MODRM_RM_FIELD(modrm) (((modrm) >> 0) & 7)
 
/* Extract fields from the sib byte. */
#define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3)
#define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7)
#define SIB_BASE_FIELD(sib) (((sib) >> 0) & 7)
 
/* x86-64 extension prefix. */
#define REX_OPCODE 0x40
 
/* Non-zero if OPCODE is the rex prefix. */
#define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE)
 
/* Indicates 64 bit operand size. */
#define REX_W 8
/* High extension to reg field of modrm byte. */
100,7 → 127,7
#define REX_B 1
 
/* max operands per insn */
#define MAX_OPERANDS 4
#define MAX_OPERANDS 5
 
/* max immediates per insn (lcall, ljmp, insertq, extrq) */
#define MAX_IMMEDIATE_OPERANDS 2
109,7 → 136,9
#define MAX_MEMORY_OPERANDS 2
 
/* max size of insn mnemonics. */
#define MAX_MNEM_SIZE 16
#define MAX_MNEM_SIZE 20
 
/* max size of register name in insn mnemonics. */
#define MAX_REG_NAME_SIZE 8
 
#endif /* OPCODE_I386_H */
/h8300.h
1,6 → 1,6
/* Opcode table for the H8/300
Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2001, 2002,
2003, 2004
2003, 2004, 2005, 2008, 2009
Free Software Foundation, Inc.
Written by Steve Chamberlain <sac@cygnus.com>.
1519,6 → 1519,7
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP16DST, E}}, {{PREFIX_0100, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{RS32, DISP32DST, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}},
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}},
{O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB16D, E}}, {{PREFIX_0101, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW16D, E}}, {{PREFIX_0102, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},
{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL16D, E}}, {{PREFIX_0103, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}},
1564,62 → 1565,62
MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS32SRC, FROM_ABS32, ABS32LIST),
 
#define DO_MOVA1(TYPE, OP0, OP1) \
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, DISP16LIST, E}}}, \
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, DISP16LIST, E}}}, \
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, DISP16LIST, E}}}, \
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, DISP16LIST, E}}}, \
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, DISP16LIST, E}}}, \
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, DISP16LIST, E}}}, \
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
\
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, DISP32LIST, E}}}, \
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, DISP32LIST, E}}}, \
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, DISP32LIST, E}}}, \
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, DISP32LIST, E}}}, \
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, DISP32LIST, E}}}, \
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, DISP32LIST, E}}}
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}
 
#define DO_MOVA2(TYPE, OP0, OP1, OP2) \
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, OP2, DISP16LIST, E}}}, \
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, OP2, DISP16LIST, E}}}, \
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, OP2, DISP16LIST, E}}}, \
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, OP2, DISP16LIST, E}}}, \
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, OP2, DISP16LIST, E}}}, \
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, OP2, DISP16LIST, E}}}, \
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
\
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, OP2, DISP32LIST, E}}}, \
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, OP2, DISP32LIST, E}}}, \
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, OP2, DISP32LIST, E}}}, \
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, OP2, DISP32LIST, E}}}, \
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, OP2, DISP32LIST, E}}}, \
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, OP2, DISP32LIST, E}}}
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}
 
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, E}}, {{0x7, 0xA, 0x8, B31 | DISPREG, DISP16LIST, E}}},
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, E}}, {{0x7, 0xA, 0x9, B31 | DISPREG, DISP16LIST, E}}},
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xA, B31 | DISPREG, DISP16LIST, E}}},
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xB, B31 | DISPREG, DISP16LIST, E}}},
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xC, B31 | DISPREG, DISP16LIST, E}}},
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xD, B31 | DISPREG, DISP16LIST, E}}},
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, E}}, {{0x7, 0xA, 0x8, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, E}}, {{0x7, 0xA, 0x9, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xA, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xB, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xC, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xD, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
 
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, E}}, {{0x7, 0xA, 0x8, B30 | DISPREG, DISP32LIST, E}}},
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, E}}, {{0x7, 0xA, 0x9, B30 | DISPREG, DISP32LIST, E}}},
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xA, B30 | DISPREG, DISP32LIST, E}}},
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xB, B30 | DISPREG, DISP32LIST, E}}},
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xC, B30 | DISPREG, DISP32LIST, E}}},
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xD, B30 | DISPREG, DISP32LIST, E}}},
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, E}}, {{0x7, 0xA, 0x8, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, E}}, {{0x7, 0xA, 0x9, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xA, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xB, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xC, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xD, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
 
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B31 | R3_32, DISP16LIST, E}}},
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B31 | R3_32, DISP16LIST, E}}},
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B31 | R3_32, DISP16LIST, E}}},
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B31 | R3_32, DISP16LIST, E}}},
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B31 | R3_32, DISP16LIST, E}}},
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B31 | R3_32, DISP16LIST, E}}},
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
 
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B30 | R3_32, DISP32LIST, E}}},
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B30 | R3_32, DISP32LIST, E}}},
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B30 | R3_32, DISP32LIST, E}}},
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B30 | R3_32, DISP32LIST, E}}},
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B30 | R3_32, DISP32LIST, E}}},
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B30 | R3_32, DISP32LIST, E}}},
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
 
DO_MOVA1 (RDIND, 0x0, B30 | RDIND),
DO_MOVA1 (RDPOSTINC, 0x8, B30 | RDPOSTINC),
1627,16 → 1628,16
DO_MOVA1 (RDPREINC, 0x9, B30 | RDPREINC),
DO_MOVA1 (RDPREDEC, 0xB, B30 | RDPREDEC),
DO_MOVA1 (DISP2DST, B30 | B20 | DISP2DST, B30 | DSTDISPREG),
DO_MOVA2 (DISP16DST, 0xC, B30 | DSTDISPREG, DSTDISP16LIST),
DO_MOVA2 (DISP32DST, 0xC, B31 | DSTDISPREG, DSTDISP32LIST),
DO_MOVA2 (INDEXB16D, 0xD, B30 | DSTDISPREG, DSTDISP16LIST),
DO_MOVA2 (INDEXW16D, 0xE, B30 | DSTDISPREG, DSTDISP16LIST),
DO_MOVA2 (INDEXL16D, 0xF, B30 | DSTDISPREG, DSTDISP16LIST),
DO_MOVA2 (INDEXB32D, 0xD, B31 | DSTDISPREG, DSTDISP32LIST),
DO_MOVA2 (INDEXW32D, 0xE, B31 | DSTDISPREG, DSTDISP32LIST),
DO_MOVA2 (INDEXL32D, 0xF, B31 | DSTDISPREG, DSTDISP32LIST),
DO_MOVA2 (ABS16DST, 0x4, 0x0, DSTABS16LIST),
DO_MOVA2 (ABS32DST, 0x4, 0x8, DSTABS32LIST),
DO_MOVA2 (DISP16DST, 0xC, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
DO_MOVA2 (DISP32DST, 0xC, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
DO_MOVA2 (INDEXB16D, 0xD, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
DO_MOVA2 (INDEXW16D, 0xE, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
DO_MOVA2 (INDEXL16D, 0xF, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
DO_MOVA2 (INDEXB32D, 0xD, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
DO_MOVA2 (INDEXW32D, 0xE, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
DO_MOVA2 (INDEXL32D, 0xF, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
DO_MOVA2 (ABS16DST, 0x4, 0x0, MEMRELAX | DSTABS16LIST),
DO_MOVA2 (ABS32DST, 0x4, 0x8, MEMRELAX | DSTABS32LIST),
 
{O (O_MOV, SB), AV_H8, 10, "movfpe", {{ABS16SRC, RD8, E}}, {{0x6, 0xA, 0x4, RD8, ABS16SRC, DATA3, E}}},
{O (O_MOV, SB), AV_H8, 10, "movtpe", {{RS8, ABS16DST, E}}, {{0x6, 0xA, 0xC, RS8, ABS16DST, DATA3, E}}},
/score-datadep.h
1,6 → 1,7
/* score-datadep.h -- Score Instructions data dependency table
Copyright 2006 Free Software Foundation, Inc.
Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
Contributed by:
Brain.lin (brain.lin@sunplusct.com)
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
 
8,7 → 9,7
 
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
the Free Software Foundation; either version 3, or (at your option)
any later version.
 
GAS is distributed in the hope that it will be useful,
28,20 → 29,7
 
enum insn_type_for_dependency
{
D_pce,
D_cond_br,
D_cond_mv,
D_cached,
D_cachei,
D_ldst,
D_ldcombine,
D_mtcr,
D_mfcr,
D_mfsr,
D_mftlb,
D_mtptlb,
D_mtrtlb,
D_stlb,
D_all_insn
};
 
58,225 → 46,20
enum insn_type_for_dependency cur_insn_type;
char cur_reg[6];
int bubblenum_7;
int bubblenum_5;
int bubblenum_3;
int warn_or_error; /* warning - 0; error - 1 */
};
 
static const struct insn_to_dependency insn_to_dependency_table[] =
{
/* pce instruction. */
{"pce", D_pce},
/* conditional branch instruction. */
{"bcs", D_cond_br},
{"bcc", D_cond_br},
{"bgtu", D_cond_br},
{"bleu", D_cond_br},
{"beq", D_cond_br},
{"bne", D_cond_br},
{"bgt", D_cond_br},
{"ble", D_cond_br},
{"bge", D_cond_br},
{"blt", D_cond_br},
{"bmi", D_cond_br},
{"bpl", D_cond_br},
{"bvs", D_cond_br},
{"bvc", D_cond_br},
{"bcsl", D_cond_br},
{"bccl", D_cond_br},
{"bgtul", D_cond_br},
{"bleul", D_cond_br},
{"beql", D_cond_br},
{"bnel", D_cond_br},
{"bgtl", D_cond_br},
{"blel", D_cond_br},
{"bgel", D_cond_br},
{"bltl", D_cond_br},
{"bmil", D_cond_br},
{"bpll", D_cond_br},
{"bvsl", D_cond_br},
{"bvcl", D_cond_br},
{"bcs!", D_cond_br},
{"bcc!", D_cond_br},
{"bgtu!", D_cond_br},
{"bleu!", D_cond_br},
{"beq!", D_cond_br},
{"bne!", D_cond_br},
{"bgt!", D_cond_br},
{"ble!", D_cond_br},
{"bge!", D_cond_br},
{"blt!", D_cond_br},
{"bmi!", D_cond_br},
{"bpl!", D_cond_br},
{"bvs!", D_cond_br},
{"bvc!", D_cond_br},
{"brcs", D_cond_br},
{"brcc", D_cond_br},
{"brgtu", D_cond_br},
{"brleu", D_cond_br},
{"breq", D_cond_br},
{"brne", D_cond_br},
{"brgt", D_cond_br},
{"brle", D_cond_br},
{"brge", D_cond_br},
{"brlt", D_cond_br},
{"brmi", D_cond_br},
{"brpl", D_cond_br},
{"brvs", D_cond_br},
{"brvc", D_cond_br},
{"brcsl", D_cond_br},
{"brccl", D_cond_br},
{"brgtul", D_cond_br},
{"brleul", D_cond_br},
{"breql", D_cond_br},
{"brnel", D_cond_br},
{"brgtl", D_cond_br},
{"brlel", D_cond_br},
{"brgel", D_cond_br},
{"brltl", D_cond_br},
{"brmil", D_cond_br},
{"brpll", D_cond_br},
{"brvsl", D_cond_br},
{"brvcl", D_cond_br},
{"brcs!", D_cond_br},
{"brcc!", D_cond_br},
{"brgtu!", D_cond_br},
{"brleu!", D_cond_br},
{"breq!", D_cond_br},
{"brne!", D_cond_br},
{"brgt!", D_cond_br},
{"brle!", D_cond_br},
{"brge!", D_cond_br},
{"brlt!", D_cond_br},
{"brmi!", D_cond_br},
{"brpl!", D_cond_br},
{"brvs!", D_cond_br},
{"brvc!", D_cond_br},
{"brcsl!", D_cond_br},
{"brccl!", D_cond_br},
{"brgtul!", D_cond_br},
{"brleul!", D_cond_br},
{"breql!", D_cond_br},
{"brnel!", D_cond_br},
{"brgtl!", D_cond_br},
{"brlel!", D_cond_br},
{"brgel!", D_cond_br},
{"brltl!", D_cond_br},
{"brmil!", D_cond_br},
{"brpll!", D_cond_br},
{"brvsl!", D_cond_br},
{"brvcl!", D_cond_br},
/* conditional move instruction. */
{"mvcs", D_cond_mv},
{"mvcc", D_cond_mv},
{"mvgtu", D_cond_mv},
{"mvleu", D_cond_mv},
{"mveq", D_cond_mv},
{"mvne", D_cond_mv},
{"mvgt", D_cond_mv},
{"mvle", D_cond_mv},
{"mvge", D_cond_mv},
{"mvlt", D_cond_mv},
{"mvmi", D_cond_mv},
{"mvpl", D_cond_mv},
{"mvvs", D_cond_mv},
{"mvvc", D_cond_mv},
/* move spectial instruction. */
{"mtcr", D_mtcr},
{"mftlb", D_mftlb},
{"mtptlb", D_mtptlb},
{"mtrtlb", D_mtrtlb},
{"stlb", D_stlb},
{"mfcr", D_mfcr},
{"mfsr", D_mfsr},
/* cache instruction. */
{"cache 8", D_cached},
{"cache 9", D_cached},
{"cache 10", D_cached},
{"cache 11", D_cached},
{"cache 12", D_cached},
{"cache 13", D_cached},
{"cache 14", D_cached},
{"cache 24", D_cached},
{"cache 26", D_cached},
{"cache 27", D_cached},
{"cache 29", D_cached},
{"cache 30", D_cached},
{"cache 31", D_cached},
{"cache 0", D_cachei},
{"cache 1", D_cachei},
{"cache 2", D_cachei},
{"cache 3", D_cachei},
{"cache 4", D_cachei},
{"cache 16", D_cachei},
{"cache 17", D_cachei},
/* load/store instruction. */
{"lb", D_ldst},
{"lbu", D_ldst},
{"lbu!", D_ldst},
{"lbup!", D_ldst},
{"lh", D_ldst},
{"lhu", D_ldst},
{"lh!", D_ldst},
{"lhp!", D_ldst},
{"lw", D_ldst},
{"lw!", D_ldst},
{"lwp!", D_ldst},
{"sb", D_ldst},
{"sb!", D_ldst},
{"sbp!", D_ldst},
{"sh", D_ldst},
{"sh!", D_ldst},
{"shp!", D_ldst},
{"sw", D_ldst},
{"sw!", D_ldst},
{"swp!", D_ldst},
{"alw", D_ldst},
{"asw", D_ldst},
{"push!", D_ldst},
{"pushhi!", D_ldst},
{"pop!", D_ldst},
{"pophi!", D_ldst},
{"ldc1", D_ldst},
{"ldc2", D_ldst},
{"ldc3", D_ldst},
{"stc1", D_ldst},
{"stc2", D_ldst},
{"stc3", D_ldst},
{"scb", D_ldst},
{"scw", D_ldst},
{"sce", D_ldst},
/* load combine instruction. */
{"lcb", D_ldcombine},
{"lcw", D_ldcombine},
{"lce", D_ldcombine},
};
 
static const struct data_dependency data_dependency_table[] =
{
/* Condition register. */
{D_mtcr, "cr1", D_pce, "", 2, 1, 1},
{D_mtcr, "cr1", D_cond_br, "", 1, 0, 1},
{D_mtcr, "cr1", D_cond_mv, "", 1, 0, 1},
/* Status regiser. */
{D_mtcr, "cr0", D_all_insn, "", 5, 4, 0},
/* CCR regiser. */
{D_mtcr, "cr4", D_all_insn, "", 6, 5, 0},
/* EntryHi/EntryLo register. */
{D_mftlb, "", D_mtptlb, "", 1, 1, 1},
{D_mftlb, "", D_mtrtlb, "", 1, 1, 1},
{D_mftlb, "", D_stlb, "", 1, 1,1},
{D_mftlb, "", D_mfcr, "cr11", 1, 1, 1},
{D_mftlb, "", D_mfcr, "cr12", 1, 1, 1},
/* Index register. */
{D_stlb, "", D_mtptlb, "", 1, 1, 1},
{D_stlb, "", D_mftlb, "", 1, 1, 1},
{D_stlb, "", D_mfcr, "cr8", 2, 2, 1},
/* Cache. */
{D_cached, "", D_ldst, "", 1, 1, 0},
{D_cached, "", D_ldcombine, "", 1, 1, 0},
{D_cachei, "", D_all_insn, "", 5, 4, 0},
/* Load combine. */
{D_ldcombine, "", D_mfsr, "sr1", 3, 3, 1},
{D_mtcr, "cr0", D_all_insn, "", 5, 1, 0},
};
 
#endif
/bfin.h
939,7 → 939,7
 
/* PseudoDbg_assert
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 1 | 1 | 1 | 1 | 0 | - | - | - | - | - |.dbgop.....|.regtest...|
| 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
|.expected......................................................|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
*/
951,6 → 951,8
int mask_expected;
int bits_regtest;
int mask_regtest;
int bits_grp;
int mask_grp;
int bits_dbgop;
int mask_dbgop;
int bits_dontcare;
964,10 → 966,12
#define PseudoDbg_Assert_expected_mask 0xffff
#define PseudoDbg_Assert_regtest_bits 16
#define PseudoDbg_Assert_regtest_mask 0x7
#define PseudoDbg_Assert_dbgop_bits 19
#define PseudoDbg_Assert_dbgop_mask 0x7
#define PseudoDbg_Assert_dontcare_bits 22
#define PseudoDbg_Assert_dontcare_mask 0x1f
#define PseudoDbg_Assert_grp_bits 19
#define PseudoDbg_Assert_grp_mask 0x7
#define PseudoDbg_Assert_dbgop_bits 22
#define PseudoDbg_Assert_dbgop_mask 0x3
#define PseudoDbg_Assert_dontcare_bits 24
#define PseudoDbg_Assert_dontcare_mask 0x7
#define PseudoDbg_Assert_code_bits 27
#define PseudoDbg_Assert_code_mask 0x1f
 
976,6 → 980,7
PseudoDbg_Assert_opcode, \
PseudoDbg_Assert_expected_bits, PseudoDbg_Assert_expected_mask, \
PseudoDbg_Assert_regtest_bits, PseudoDbg_Assert_regtest_mask, \
PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask, \
PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, \
PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask, \
PseudoDbg_Assert_code_bits, PseudoDbg_Assert_code_mask \
/arm.h
44,6 → 44,9
#define ARM_EXT_V7A 0x00100000 /* Arm V7A. */
#define ARM_EXT_V7R 0x00200000 /* Arm V7R. */
#define ARM_EXT_V7M 0x00400000 /* Arm V7M. */
#define ARM_EXT_V6M 0x00800000 /* ARM V6M. */
#define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */
#define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */
 
/* Co-processor space extensions. */
#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
61,6 → 64,8
#define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */
#define FPU_VFP_EXT_V3 0x01000000 /* VFPv3 insns. */
#define FPU_NEON_EXT_V1 0x00800000 /* Neon (SIMD) insns. */
#define FPU_VFP_EXT_D32 0x00400000 /* Registers D16-D31. */
#define FPU_NEON_FP16 0x00200000 /* Half-precision extensions. */
 
/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
87,17 → 92,22
#define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K)
#define ARM_AEXT_V6Z (ARM_AEXT_V6 | ARM_EXT_V6Z)
#define ARM_AEXT_V6ZK (ARM_AEXT_V6 | ARM_EXT_V6K | ARM_EXT_V6Z)
#define ARM_AEXT_V6T2 (ARM_AEXT_V6 | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM)
#define ARM_AEXT_V6T2 (ARM_AEXT_V6 \
| ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR)
#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K)
#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_V6Z)
#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_V6Z)
#define ARM_AEXT_V7_ARM (ARM_AEXT_V6ZKT2 | ARM_EXT_V7)
#define ARM_AEXT_V7_ARM (ARM_AEXT_V6ZKT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A)
#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
#define ARM_AEXT_NOTM \
(ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM)
#define ARM_AEXT_V6M \
((ARM_AEXT_V6K | ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) \
& ~(ARM_AEXT_NOTM))
#define ARM_AEXT_V7M \
((ARM_AEXT_V7_ARM | ARM_EXT_V7M | ARM_EXT_DIV) & ~(ARM_AEXT_NOTM))
((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \
& ~(ARM_AEXT_NOTM))
#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M)
 
/* Processors with specific extensions in the co-processor space. */
110,9 → 120,10
#define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE)
#define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1)
#define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2)
#define FPU_VFP_V3 (FPU_VFP_V2 | FPU_VFP_EXT_V3)
#define FPU_VFP_V3D16 (FPU_VFP_V2 | FPU_VFP_EXT_V3)
#define FPU_VFP_V3 (FPU_VFP_V3D16 | FPU_VFP_EXT_D32)
#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \
| FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1)
| FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32)
#define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2)
 
/* Deprecated */
124,10 → 135,13
#define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD)
#define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1)
#define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2)
#define FPU_ARCH_VFP_V3D16 ARM_FEATURE (0, FPU_VFP_V3D16)
#define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3)
#define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1)
#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \
ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1)
#define FPU_ARCH_NEON_FP16 \
ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_NEON_FP16)
#define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD)
 
#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE)
158,6 → 172,7
#define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0)
#define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0)
#define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0)
#define ARM_ARCH_V6M ARM_FEATURE (ARM_AEXT_V6M, 0)
#define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0)
#define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0)
#define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0)
/tic54x.h
1,5 → 1,5
/* tic54x.h -- Header file for TI TMS320C54X opcode table
Copyright 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1999, 2000, 2001, 2005, 2009 Free Software Foundation, Inc.
Written by Timothy Wall (twall@cygnus.com)
 
This file is part of GDB, GAS, and the GNU binutils.
147,17 → 147,17
const char* parname;
enum optype paroperand_types[MAX_OPERANDS];
 
} template;
} insn_template;
 
extern const template tic54x_unknown_opcode;
extern const template tic54x_optab[];
extern const template tic54x_paroptab[];
extern const insn_template tic54x_unknown_opcode;
extern const insn_template tic54x_optab[];
extern const insn_template tic54x_paroptab[];
extern const symbol mmregs[], regs[];
extern const symbol condition_codes[], cc2_codes[], status_bits[];
extern const symbol cc3_codes[];
extern const char *misc_symbols[];
struct disassemble_info;
extern const template* tic54x_get_insn (struct disassemble_info *,
extern const insn_template* tic54x_get_insn (struct disassemble_info *,
bfd_vma, unsigned short, int *);
 
#endif /* _opcode_tic54x_h_ */
/ppc.h
1,6 → 1,6
/* ppc.h -- Header file for PowerPC opcode table
Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
2007 Free Software Foundation, Inc.
2007, 2008, 2009 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
 
This file is part of GDB, GAS, and the GNU binutils.
22,6 → 22,10
#ifndef PPC_H
#define PPC_H
 
#include "bfd_stdint.h"
 
typedef uint64_t ppc_cpu_t;
 
/* The opcode table is an array of struct powerpc_opcode. */
 
struct powerpc_opcode
42,8 → 46,13
/* One bit flags for the opcode. These are used to indicate which
specific processors support the instructions. The defined values
are listed below. */
unsigned long flags;
ppc_cpu_t flags;
 
/* One bit flags for the opcode. These are used to indicate which
specific processors no longer support the instructions. The defined
values are listed below. */
ppc_cpu_t deprecated;
 
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
107,8 → 116,8
/* Opcode is only supported by Power4 architecture. */
#define PPC_OPCODE_POWER4 0x4000
 
/* Opcode isn't supported by Power4 architecture. */
#define PPC_OPCODE_NOPOWER4 0x8000
/* Opcode is only supported by Power7 architecture. */
#define PPC_OPCODE_POWER7 0x8000
 
/* Opcode is only supported by POWERPC Classic architecture. */
#define PPC_OPCODE_CLASSIC 0x10000
149,6 → 158,21
/* Opcode is supported by CPUs with paired singles support. */
#define PPC_OPCODE_PPCPS 0x10000000
 
/* Opcode is supported by Power E500MC */
#define PPC_OPCODE_E500MC 0x20000000
 
/* Opcode is supported by PowerPC 405 processor. */
#define PPC_OPCODE_405 0x40000000
 
/* Opcode is supported by Vector-Scalar (VSX) Unit */
#define PPC_OPCODE_VSX 0x80000000
 
/* Opcode is supported by A2. */
#define PPC_OPCODE_A2 0x100000000ULL
 
/* Opcode is supported by PowerPC 476 processor. */
#define PPC_OPCODE_476 0x200000000ULL
 
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
180,7 → 204,7
operand value is legal, *ERRMSG will be unchanged (most operands
can accept any value). */
unsigned long (*insert)
(unsigned long instruction, long op, int dialect, const char **errmsg);
(unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
 
/* Extraction function. This is used by the disassembler. To
extract this operand type from an instruction, check this field.
198,7 → 222,7
non-zero if this operand type can not actually be extracted from
this operand (i.e., the instruction does not match). If the
operand is valid, *INVALID will not be changed. */
long (*extract) (unsigned long instruction, int dialect, int *invalid);
long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
 
/* One bit syntax flags. */
unsigned long flags;
299,6 → 323,15
 
/* Valid range of operand is 0..n rather than 0..n-1. */
#define PPC_OPERAND_PLUS1 (0x10000)
 
/* Xilinx APU and FSL related operands */
#define PPC_OPERAND_FSL (0x20000)
#define PPC_OPERAND_FCR (0x40000)
#define PPC_OPERAND_UDI (0x80000)
 
/* This operand names a vector-scalar unit register. The disassembler
prints these with a leading 'vs'. */
#define PPC_OPERAND_VSR (0x100000)
/* The POWER and PowerPC assemblers use a few macros. We keep them
with the operands table for simplicity. The macro table is an
315,7 → 348,7
/* One bit flags for the opcode. These are used to indicate which
specific processors support the instructions. The values are the
same as those for the struct powerpc_opcode flags field. */
unsigned long flags;
ppc_cpu_t flags;
 
/* A format string to turn the macro into a normal instruction.
Each %N in the string is replaced with operand number N (zero
326,4 → 359,6
extern const struct powerpc_macro powerpc_macros[];
extern const int powerpc_num_macros;
 
extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, const char *);
 
#endif /* PPC_H */
/or32.h
28,7 → 28,7
#define NUM_SIGNED (1)
 
#define MAX_GPRS 32
#define PAGE_SIZE 4096
#define PAGE_SIZE 8192
#undef __HALF_WORD_INSN__
 
#define OPERAND_DELIM (',')
37,6 → 37,18
#define OR32_W_FLAG (2)
#define OR32_R_FLAG (4)
 
#if defined(HAS_EXECUTION)
# if SIMPLE_EXECUTION
# include "simpl32_defs.h"
# elif DYNAMIC_EXECUTION
# include "dyn32_defs.h"
# else
extern void l_none (void);
# endif
#else
extern void l_none (void);
#endif
 
struct or32_letter
{
char letter;
44,6 → 56,23
/* int reloc; relocation per letter ?? */
};
 
enum insn_type {
it_unknown,
it_exception,
it_arith,
it_shift,
it_compare,
it_branch,
it_jump,
it_load,
it_store,
it_movimm,
it_move,
it_extend,
it_nop,
it_mac,
it_float };
 
/* Main instruction specification array. */
struct or32_opcode
{
67,8 → 96,21
/* Opcode and operand encoding. */
char *encoding;
void (*exec) (void);
 
#ifdef HAS_EXECUTION
# if COMPLEX_EXECUTION
char *function_name;
# elif SIMPLE_EXECUTION
void (*exec)(struct iqueue_entry *);
# else /* DYNAMIC_EXECUTION */
void (*exec)(struct op_queue *opq, int param_t[3], orreg_t param[3], int);
# endif
#else /* HAS_EXECUTION */
void (*exec)(void);
#endif
 
unsigned int flags;
enum insn_type func_unit;
};
 
#define OPTYPE_LAST (0x80000000)
88,61 → 130,19
unsigned long data;
} **op_start;
 
#ifdef HAS_EXECUTION
extern void l_invalid (void);
extern void l_sfne (void);
extern void l_bf (void);
extern void l_add (void);
extern void l_sw (void);
extern void l_sb (void);
extern void l_sh (void);
extern void l_lwz (void);
extern void l_lbs (void);
extern void l_lbz (void);
extern void l_lhs (void);
extern void l_lhz (void);
extern void l_movhi (void);
extern void l_and (void);
extern void l_or (void);
extern void l_xor (void);
extern void l_sub (void);
extern void l_mul (void);
extern void l_div (void);
extern void l_divu (void);
extern void l_sll (void);
extern void l_sra (void);
extern void l_srl (void);
extern void l_j (void);
extern void l_jal (void);
extern void l_jalr (void);
extern void l_jr (void);
extern void l_rfe (void);
extern void l_nop (void);
extern void l_bnf (void);
extern void l_sfeq (void);
extern void l_sfgts (void);
extern void l_sfges (void);
extern void l_sflts (void);
extern void l_sfles (void);
extern void l_sfgtu (void);
extern void l_sfgeu (void);
extern void l_sfltu (void);
extern void l_sfleu (void);
extern void l_mtspr (void);
extern void l_mfspr (void);
extern void l_sys (void);
extern void l_trap (void); /* CZ 21/06/01. */
extern void l_macrc (void);
extern void l_mac (void);
extern void l_msb (void);
extern void l_invalid (void);
extern void l_cust1 (void);
extern void l_cust2 (void);
extern void l_cust3 (void);
extern void l_cust4 (void);
#endif
extern void l_none (void);
/* Leaf flag used in automata building */
#define LEAF_FLAG (0x80000000)
 
struct temp_insn_struct
{
unsigned long insn;
unsigned long insn_mask;
int in_pass;
};
 
extern unsigned long *automata;
extern struct temp_insn_struct *ti;
 
extern const struct or32_letter or32_letters[];
 
extern const struct or32_opcode or32_opcodes[];
177,4 → 177,17
Return the size of the instruction. */
int disassemble_insn (unsigned long);
 
/* Extract instruction */
extern unsigned long insn_extract(char,char*);
/* Disassemble one instruction from insn index.
Return the size of the instruction. */
int disassemble_index (unsigned long,int);
 
/* FOR INTERNAL USE ONLY */
/* Automatically does zero- or sign- extension and also finds correct
sign bit position if sign extension is correct extension. Which extension
is proper is figured out from letter description. */
unsigned long extend_imm(unsigned long,char);
 
#endif
/avr.h
32,7 → 32,6
#define AVR_ISA_MOVW 0x1000 /* device has MOVW */
 
#define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM)
#define AVR_ISA_PWMx (AVR_ISA_M8 | AVR_ISA_BRK)
#define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM)
/* For the attiny26 which is missing LPM Rd,Z+. */
#define AVR_ISA_2xxe (AVR_ISA_2xxx | AVR_ISA_LPMX)
39,14 → 38,11
#define AVR_ISA_RF401 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX)
#define AVR_ISA_TINY2 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX | \
AVR_ISA_SPM | AVR_ISA_BRK)
#define AVR_ISA_M8 (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_MOVW | \
AVR_ISA_LPMX | AVR_ISA_SPM)
#define AVR_ISA_M603 (AVR_ISA_2xxx | AVR_ISA_MEGA)
#define AVR_ISA_M103 (AVR_ISA_M603 | AVR_ISA_ELPM)
#define AVR_ISA_USB162 (AVR_ISA_M603 | AVR_ISA_MOVW | \
#define AVR_ISA_M8 (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_MOVW | \
AVR_ISA_LPMX | AVR_ISA_SPM)
#define AVR_ISA_AVR3 (AVR_ISA_M603 | AVR_ISA_MOVW | \
AVR_ISA_LPMX | AVR_ISA_SPM | AVR_ISA_ELPM)
#define AVR_ISA_PWMx (AVR_ISA_M8 | AVR_ISA_BRK)
#define AVR_ISA_M161 (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | \
AVR_ISA_LPMX | AVR_ISA_SPM)
#define AVR_ISA_94K (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | AVR_ISA_LPMX)
53,7 → 49,22
#define AVR_ISA_M323 (AVR_ISA_M161 | AVR_ISA_BRK)
#define AVR_ISA_M128 (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX)
 
#define AVR_ISA_ALL 0xFFFF
#define AVR_ISA_AVR1 AVR_ISA_TINY1
#define AVR_ISA_AVR2 AVR_ISA_2xxx
#define AVR_ISA_AVR25 AVR_ISA_TINY2
#define AVR_ISA_AVR3 AVR_ISA_M603
#define AVR_ISA_AVR31 AVR_ISA_M103
#define AVR_ISA_AVR35 (AVR_ISA_AVR3 | AVR_ISA_MOVW | \
AVR_ISA_LPMX | AVR_ISA_SPM | AVR_ISA_BRK)
#define AVR_ISA_AVR3_ALL (AVR_ISA_AVR3 | AVR_ISA_AVR31 | AVR_ISA_AVR35)
#define AVR_ISA_AVR4 AVR_ISA_PWMx
#define AVR_ISA_AVR5 AVR_ISA_M323
#define AVR_ISA_AVR51 AVR_ISA_M128
#define AVR_ISA_AVR6 (AVR_ISA_1200 | AVR_ISA_LPM | AVR_ISA_LPMX | \
AVR_ISA_SRAM | AVR_ISA_MEGA | AVR_ISA_MUL | \
AVR_ISA_ELPM | AVR_ISA_ELPMX | AVR_ISA_SPM | \
AVR_ISA_SPM | AVR_ISA_BRK | AVR_ISA_EIND | \
AVR_ISA_MOVW)
 
#define REGISTER_P(x) ((x) == 'r' \
|| (x) == 'd' \
/s390.h
37,7 → 37,8
S390_OPCODE_Z900,
S390_OPCODE_Z990,
S390_OPCODE_Z9_109,
S390_OPCODE_Z9_EC
S390_OPCODE_Z9_EC,
S390_OPCODE_Z10
};
 
/* The opcode table is an array of struct s390_opcode. */
/ChangeLog
1,3 → 1,174
2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
 
* ppc.h (PPC_OPCODE_476): Define.
 
2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
 
* ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 
2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
 
* ppc.h (ppc_cpu_t): Typedef to uint64_t.
 
2009-09-21 Ben Elliston <bje@au.ibm.com>
 
* ppc.h (PPC_OPCODE_PPCA2): New.
 
2009-09-05 Martin Thuresson <martin@mtme.org>
 
* ia64.h (struct ia64_operand): Renamed member class to op_class.
 
2009-08-29 Martin Thuresson <martin@mtme.org>
 
* tic30.h (template): Rename type template to
insn_template. Updated code to use new name.
* tic54x.h (template): Rename type template to
insn_template.
 
2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
 
* hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 
2009-06-11 Anthony Green <green@moxielogic.com>
 
* moxie.h (MOXIE_F3_PCREL): Define.
(moxie_form3_opc_info): Grow.
 
2009-06-06 Anthony Green <green@moxielogic.com>
 
* moxie.h (MOXIE_F1_M): Define.
 
2009-04-15 Anthony Green <green@moxielogic.com>
 
* moxie.h: Created.
 
2009-04-06 DJ Delorie <dj@redhat.com>
 
* h8300.h: Add relaxation attributes to MOVA opcodes.
 
2009-03-10 Alan Modra <amodra@bigpond.net.au>
 
* ppc.h (ppc_parse_cpu): Declare.
 
2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
 
* score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
and _IMM11 for mbitclr and mbitset.
* score-datadep.h: Update dependency information.
 
2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
 
* ppc.h (PPC_OPCODE_POWER7): New.
 
2009-02-06 Doug Evans <dje@google.com>
 
* i386.h: Add comment regarding sse* insns and prefixes.
 
2009-02-03 Sandip Matte <sandip@rmicorp.com>
 
* mips.h (INSN_XLR): Define.
(INSN_CHIP_MASK): Update.
(CPU_XLR): Define.
(OPCODE_IS_MEMBER): Update.
(M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 
2009-01-28 Doug Evans <dje@google.com>
 
* opcode/i386.h: Add multiple inclusion protection.
(EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
(EDI_REG_NUM): New macros.
(MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
(SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
(REX_PREFIX_P): New macro.
 
2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
 
* ppc.h (struct powerpc_opcode): New field "deprecated".
(PPC_OPCODE_NOPOWER4): Delete.
 
2008-11-28 Joshua Kinard <kumba@gentoo.org>
 
* mips.h: Define CPU_R14000, CPU_R16000.
(OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 
2008-11-18 Catherine Moore <clm@codesourcery.com>
 
* arm.h (FPU_NEON_FP16): New.
(FPU_ARCH_NEON_FP16): New.
 
2008-11-06 Chao-ying Fu <fu@mips.com>
 
* mips.h: Doucument '1' for 5-bit sync type.
 
2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
 
* ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
IA64_RS_CR.
 
2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
 
* ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 
2008-07-30 Michael J. Eager <eager@eagercon.com>
 
* ppc.h (PPC_OPCODE_405): Define.
(PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 
2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
 
* ppc.h (ppc_cpu_t): New typedef.
(struct powerpc_opcode <flags>): Use it.
(struct powerpc_operand <insert, extract>): Likewise.
(struct powerpc_macro <flags>): Likewise.
 
2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
 
* mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
Update comment before MIPS16 field descriptors to mention MIPS16.
(OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
BBIT.
(OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
New bit masks and shift counts for cins and exts.
 
* mips.h: Document new field descriptors +Q.
(OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 
2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
 
* mips.h (INSN_MACRO): Move it up to the the pinfo macros.
(INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 
2008-04-14 Edmar Wienskoski <edmar@freescale.com>
 
* ppc.h: (PPC_OPCODE_E500MC): New.
 
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
 
* i386.h (MAX_OPERANDS): Set to 5.
(MAX_MNEM_SIZE): Changed to 20.
 
2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
 
* avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 
2008-03-09 Paul Brook <paul@codesourcery.com>
 
* arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 
2008-03-04 Paul Brook <paul@codesourcery.com>
 
* arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
(ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
(ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 
2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
Nick Clifton <nickc@redhat.com>
 
PR 3134
* h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
with a 32-bit displacement but without the top bit of the 4th byte
set.
 
2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 
* cr16.h (cr16_num_optab): Declared.
15,6 → 186,15
(CPU_OCTEON): New macro.
(OPCODE_IS_MEMBER): Handle Octeon instructions.
 
2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
 
* avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 
2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
 
* avr.h (AVR_ISA_USB162): Add new opcode set.
(AVR_ISA_AVR3): Likewise.
 
2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
 
* mips.h (INSN_LOONGSON_2E): New.
338,6 → 518,10
before corresponding pa11 opcodes. Add strict pa10 register-immediate
entries for "fdc".
 
2005-09-30 Catherine Moore <clm@cm00re.com>
 
* bfin.h: New file.
 
2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
 
* hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
/ia64.h
171,9 → 171,10
IA64_RS_BR,
IA64_RS_CFM,
IA64_RS_CPUID,
IA64_RS_CR_IIB,
IA64_RS_CR_IRR,
IA64_RS_CR_LRR,
IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */
IA64_RS_CR, /* 3-7,10-15,18,28-63,75-79,82-127 */
IA64_RS_DBR,
IA64_RS_FR,
IA64_RS_FRb,
326,7 → 327,7
 
struct ia64_operand
{
enum ia64_operand_class class;
enum ia64_operand_class op_class;
 
/* Set VALUE as the operand bits for the operand of type SELF in the
instruction pointed to by CODE. If an error occurs, *CODE is not
/mips.h
1,6 → 1,6
/* mips.h. Mips opcode list for GDB, the GNU debugger.
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
2003, 2004, 2005, 2008
2003, 2004, 2005, 2008, 2009
Free Software Foundation, Inc.
Contributed by Ralph Campbell and OSF
Commented and modified by Ian Lance Taylor, Cygnus Support
215,6 → 215,16
#define OP_SH_UDI4 6
#define OP_MASK_UDI4 0xfffff
 
/* Octeon */
#define OP_SH_BBITIND 16
#define OP_MASK_BBITIND 0x1f
#define OP_SH_CINSPOS 6
#define OP_MASK_CINSPOS 0x1f
#define OP_SH_CINSLM1 11
#define OP_MASK_CINSLM1 0x1f
#define OP_SH_SEQI 6
#define OP_MASK_SEQI 0x3ff
 
/* This structure holds information for a particular instruction. */
 
struct mips_opcode
252,6 → 262,7
 
Each of these characters corresponds to a mask field defined above.
 
"1" 5 bit sync type (OP_*_SHAMT)
"<" 5 bit shift amount (OP_*_SHAMT)
">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
"a" 26 bit target address (OP_*_TARGET)
370,6 → 381,20
"+3" UDI immediate bits 6-20
"+4" UDI immediate bits 6-25
 
Octeon:
"+x" Bit index field of bbit. Enforces: 0 <= index < 32.
"+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64,
otherwise skips to next candidate.
"+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
"+P" Position field of cins/exts aliasing cins32/exts32. Matches if
32 <= pos < 64, otherwise skips to next candidate.
"+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512.
"+s" Length-minus-one field of cins/exts. Enforces: 0 <= lenm1 < 32.
"+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing
cint32/exts32. Enforces non-negative value and that
pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous
position field is "+p" or "+P".
 
Other:
"()" parens surrounding optional value
"," separates operands
377,7 → 402,7
"+" Start of extension sequence.
 
Characters used so far, for quick reference when adding more:
"234567890"
"1234567890"
"%[]<>(),+:'@!$*&"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
"abcdefghijklopqrstuvwxz"
385,8 → 410,8
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
"1234"
"ABCDEFGHIT"
"t"
"ABCDEFGHIPQSTX"
"pstx"
*/
 
/* These are the bits which may be set in the pinfo field of an
456,6 → 481,9
#define INSN_MULT 0x40000000
/* Instruction synchronize shared memory. */
#define INSN_SYNC 0x80000000
/* Instruction is actually a macro. It should be ignored by the
disassembler, and requires special treatment by the assembler. */
#define INSN_MACRO 0xffffffff
 
/* These are the bits which may be set in the pinfo2 field of an
instruction. */
466,11 → 494,15
#define INSN2_READ_MDMX_ACC 0x00000002
/* Instruction writes MDMX accumulator. */
#define INSN2_WRITE_MDMX_ACC 0x00000004
/* Macro uses single-precision floating-point instructions. This should
only be set for macros. For instructions, FP_S in pinfo carries the
same information. */
#define INSN2_M_FP_S 0x00000008
/* Macro uses double-precision floating-point instructions. This should
only be set for macros. For instructions, FP_D in pinfo carries the
same information. */
#define INSN2_M_FP_D 0x00000010
 
/* Instruction is actually a macro. It should be ignored by the
disassembler, and requires special treatment by the assembler. */
#define INSN_MACRO 0xffffffff
 
/* Masks used to mark instructions to indicate which MIPS ISA level
they were introduced in. INSN_ISA_MASK masks an enumeration that
specifies the base ISA level(s). The remainder of a 32-bit
511,7 → 543,7
{ 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
 
/* Masks used for Chip specific instructions. */
#define INSN_CHIP_MASK 0xc3ff0800
#define INSN_CHIP_MASK 0xc3ff0820
 
/* Cavium Networks Octeon instructions. */
#define INSN_OCTEON 0x00000800
560,6 → 592,8
#define INSN_LOONGSON_2E 0x40000000
/* ST Microelectronics Loongson 2F. */
#define INSN_LOONGSON_2F 0x80000000
/* RMI Xlr instruction */
#define INSN_XLR 0x00000020
 
/* MIPS ISA defines, use instead of hardcoding ISA level. */
 
600,6 → 634,8
#define CPU_RM9000 9000
#define CPU_R10000 10000
#define CPU_R12000 12000
#define CPU_R14000 14000
#define CPU_R16000 16000
#define CPU_MIPS16 16
#define CPU_MIPS32 32
#define CPU_MIPS32R2 33
610,6 → 646,7
#define CPU_LOONGSON_2E 3001
#define CPU_LOONGSON_2F 3002
#define CPU_OCTEON 6501
#define CPU_XLR 887682 /* decimal 'XLR' */
 
/* Test for membership in an ISA including chip specific ISAs. INSN
is pointer to an element of the opcode table; ISA is the specified
629,7 → 666,8
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
|| (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
|| ((cpu == CPU_R10000 || cpu == CPU_R12000) \
|| ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000 \
|| cpu == CPU_R16000) \
&& ((insn)->membership & INSN_10000) != 0) \
|| (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
|| (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
642,6 → 680,7
&& ((insn)->membership & INSN_LOONGSON_2F) != 0) \
|| (cpu == CPU_OCTEON \
&& ((insn)->membership & INSN_OCTEON) != 0) \
|| (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
|| 0) /* Please keep this term for easier source merging. */
 
/* This is a list of macro expanded instructions.
774,6 → 813,11
M_LWR_A,
M_LWR_AB,
M_LWU_AB,
M_MSGSND,
M_MSGLD,
M_MSGLD_T,
M_MSGWAIT,
M_MSGWAIT_T,
M_MOVE,
M_MUL,
M_MUL_I,
955,11 → 999,10
#define MIPS16OP_MASK_IMM6 0x3f
#define MIPS16OP_SH_IMM6 5
 
/* These are the characters which may appears in the args field of an
instruction. They appear in the order in which the fields appear
when the instruction is used. Commas and parentheses in the args
string are ignored when assembling, and written into the output
when disassembling.
/* These are the characters which may appears in the args field of a MIPS16
instruction. They appear in the order in which the fields appear when the
instruction is used. Commas and parentheses in the args string are ignored
when assembling, and written into the output when disassembling.
 
"y" 3 bit register (MIPS16OP_*_RY)
"x" 3 bit register (MIPS16OP_*_RX)
/tic30.h
1,5 → 1,5
/* tic30.h -- Header file for TI TMS320C30 opcode table
Copyright 1998 Free Software Foundation, Inc.
Copyright 1998, 2005, 2009 Free Software Foundation, Inc.
Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
 
This file is part of GDB, GAS, and the GNU binutils.
241,9 → 241,9
#define Imm_SInt 2
#define Imm_UInt 3
}
template;
insn_template;
 
static const template tic30_optab[] = {
static const insn_template tic30_optab[] = {
{ "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "absi" ,2,0x00800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "addc" ,2,0x01000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
604,7 → 604,7
{ "" ,0,0x00000000,0, { 0, 0, 0 }, 0 }
};
 
static const template *const tic30_optab_end =
static const insn_template *const tic30_optab_end =
tic30_optab + sizeof(tic30_optab)/sizeof(tic30_optab[0]);
 
typedef struct {
/score-inst.h
1,6 → 1,7
/* score-inst.h -- Score Instructions Table
Copyright 2006 Free Software Foundation, Inc.
Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
Contributed by:
Brain.lin (brain.lin@sunplusct.com)
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
 
8,7 → 9,7
 
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
the Free Software Foundation; either version 3, or (at your option)
any later version.
 
GAS is distributed in the hope that it will be useful,
96,6 → 97,8
Rd_Rs_I14,
I15,
Rd_I16,
Rd_I30,
Rd_I32,
Rd_rvalueRs_SI10,
Rd_lvalueRs_SI10,
Rd_rvalueRs_preSI12,
105,6 → 108,8
Rd_Rs_SI14,
Rd_rvalueRs_SI15,
Rd_lvalueRs_SI15,
Rd_SI5,
Rd_SI6,
Rd_SI16,
PC_DISP8div2,
PC_DISP11div2,
139,6 → 144,8
Insn_GP,
Insn_PIC,
Insn_internal,
Insn_BCMP,
Ra_I9_I5,
};
 
enum score_data_type
178,6 → 185,13
_SIMM16_pic = 42, /* Index in score_df_range. */
_IMM16_LO16_pic = 43,
_IMM16_pic = 44,
 
_SIMM5 = 45,
_SIMM6 = 46,
_IMM32 = 47,
_SIMM32 = 48,
_IMM11 = 49,
_IMM5_MULTI_LOAD = 50,
};
 
#define REG_TMP 1
206,302 → 220,17
#define OP16_SH_DISP8 (OP_IMM_TYPE | 0)
#define OP16_SH_DISP11 (OP_IMM_TYPE | 1)
 
struct datafield_range
{
int data_type;
int bits;
int range[2];
};
 
struct datafield_range score_df_range[] =
{
{_IMM4, 4, {0, (1 << 4) - 1}}, /* ( 0 ~ 15 ) */
{_IMM5, 5, {0, (1 << 5) - 1}}, /* ( 0 ~ 31 ) */
{_IMM8, 8, {0, (1 << 8) - 1}}, /* ( 0 ~ 255 ) */
{_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 16383) */
{_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */
{_IMM16, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */
{_SIMM10, 10, {-(1 << 9), (1 << 9) - 1}}, /* ( -512 ~ 511 ) */
{_SIMM12, 12, {-(1 << 11), (1 << 11) - 1}}, /* ( -2048 ~ 2047 ) */
{_SIMM14, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8192 ~ 8191 ) */
{_SIMM15, 15, {-(1 << 14), (1 << 14) - 1}}, /* (-16384 ~ 16383) */
{_SIMM16, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
{_SIMM14_NEG, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8191 ~ 8192 ) */
{_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* (-65535 ~ 0 ) */
{_SIMM16_NEG, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
{_IMM20, 20, {0, (1 << 20) - 1}},
{_IMM25, 25, {0, (1 << 25) - 1}},
{_DISP8div2, 8, {-(1 << 8), (1 << 8) - 1}}, /* ( -256 ~ 255 ) */
{_DISP11div2, 11, {0, 0}},
{_DISP19div2, 19, {-(1 << 19), (1 << 19) - 1}}, /* (-524288 ~ 524287) */
{_DISP24div2, 24, {0, 0}},
{_VALUE, 32, {0, ((unsigned int)1 << 31) - 1}},
{_VALUE_HI16, 16, {0, (1 << 16) - 1}},
{_VALUE_LO16, 16, {0, (1 << 16) - 1}},
{_VALUE_LDST_LO16, 16, {0, (1 << 16) - 1}},
{_SIMM16_LA, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
{_IMM5_RSHIFT_1, 5, {0, (1 << 6) - 1}}, /* ( 0 ~ 63 ) */
{_IMM5_RSHIFT_2, 5, {0, (1 << 7) - 1}}, /* ( 0 ~ 127 ) */
{_SIMM16_LA_POS, 16, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */
{_IMM5_RANGE_8_31, 5, {8, 31}}, /* But for cop0 the valid data : (8 ~ 31). */
{_IMM10_RSHIFT_2, 10, {-(1 << 11), (1 << 11) - 1}}, /* For ldc#, stc#. */
{_SIMM10, 10, {0, (1 << 10) - 1}}, /* ( -1024 ~ 1023 ) */
{_SIMM12, 12, {0, (1 << 12) - 1}}, /* ( -2048 ~ 2047 ) */
{_SIMM14, 14, {0, (1 << 14) - 1}}, /* ( -8192 ~ 8191 ) */
{_SIMM15, 15, {0, (1 << 15) - 1}}, /* (-16384 ~ 16383) */
{_SIMM16, 16, {0, (1 << 16) - 1}}, /* (-65536 ~ 65536) */
{_SIMM14_NEG, 14, {0, (1 << 16) - 1}}, /* ( -8191 ~ 8192 ) */
{_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
{_SIMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
{_IMM20, 20, {0, (1 << 20) - 1}}, /* (-32768 ~ 32767) */
{_IMM25, 25, {0, (1 << 25) - 1}}, /* (-32768 ~ 32767) */
{_GP_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 65535) */
{_GP_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 65535) */
{_SIMM16_pic, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
{_IMM16_LO16_pic, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
{_IMM16_pic, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */
};
 
struct shift_bitmask
{
int opd_type;
int opd_num;
struct datafield_range *df_range;
int sh[4];
long fieldbits[4];
};
 
struct shift_bitmask score_sh_bits_map[] =
{
{
Rd_I4, 2, &score_df_range[_IMM4],
{OP16_SH_REGD, OP16_SH_I45, 0, 0},
{0xf, 0xf, 0, 0},
},
{
Rd_I5, 2, &score_df_range[_IMM5],
{OP16_SH_REGD, OP16_SH_I45, 0, 0},
{0xf, 0x1f, 0, 0},
},
{
Rd_rvalueBP_I5, 2, &score_df_range[_IMM5],
{OP16_SH_REGD, OP16_SH_I45, 0, 0},
{0xf, 0x1f, 0, 0},
},
{
Rd_lvalueBP_I5, 2, &score_df_range[_IMM5],
{OP16_SH_REGD, OP16_SH_I45, 0, 0},
{0xf, 0x1f, 0, 0},
},
{
Rd_Rs_I5, 3, &score_df_range[_IMM5],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I5, 0},
{0x1f, 0x1f, 0x1f, 0},
},
{
x_Rs_I5, 2, &score_df_range[_IMM5],
{OP_SH_REGS1, OP_SH_I5, 0, 0},
{0x1f, 0x1f, 0, 0},
},
{
x_I5_x, 1, &score_df_range[_IMM5],
{OP_SH_TRAPI5, 0, 0, 0},
{0x1f, 0, 0, 0},
},
{
Rd_I8, 2, &score_df_range[_IMM8],
{OP16_SH_REGD, OP16_SH_I8, 0, 0},
{0xf, 0xff, 0, 0},
},
{
Rd_Rs_I14, 3, &score_df_range[_IMM14],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
{0x1f, 0x1f, 0x3fff, 0},
},
{
I15, 1, &score_df_range[_IMM15],
{OP_SH_I15, 0, 0, 0},
{0x7fff, 0, 0, 0},
},
{
Rd_I16, 2, &score_df_range[_IMM16],
{OP_SH_REGD, OP_SH_I, 0, 0},
{0x1f, 0xffff, 0, 0},
},
{
Rd_rvalueRs_SI10, 3, &score_df_range[_SIMM10],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
{0x1f, 0x1f, 0x3ff, 0},
},
{
Rd_lvalueRs_SI10, 3, &score_df_range[_SIMM10],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
{0x1f, 0x1f, 0x3ff, 0},
},
{
Rd_rvalueRs_preSI12, 3, &score_df_range[_SIMM12],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
{0xf, 0xf, 0xfff, 0},
},
{
Rd_rvalueRs_postSI12, 3, &score_df_range[_SIMM12],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
{0xf, 0xf, 0xfff, 0},
},
{
Rd_lvalueRs_preSI12, 3, &score_df_range[_SIMM12],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
{0xf, 0xf, 0xfff, 0},
},
{
Rd_lvalueRs_postSI12, 3, &score_df_range[_SIMM12],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
{0xf, 0xf, 0xfff, 0},
},
{
Rd_Rs_SI14, 3, &score_df_range[_SIMM14],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
{0x1f, 0x1f, 0x3fff, 0},
},
{
Rd_rvalueRs_SI15, 3, &score_df_range[_SIMM15],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
{0x1f, 0x1f, 0x7fff, 0},
},
{
Rd_lvalueRs_SI15, 3, &score_df_range[_SIMM15],
{OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
{0x1f, 0x1f, 0x7fff, 0},
},
{
Rd_SI16, 2, &score_df_range[_SIMM16],
{OP_SH_REGD, OP_SH_I, 0, 0},
{0x1f, 0xffff, 0, 0},
},
{
PC_DISP8div2, 1, &score_df_range[_DISP8div2],
{OP16_SH_DISP8, 0, 0, 0},
{0xff, 0, 0, 0},
},
{
PC_DISP11div2, 1, &score_df_range[_DISP11div2],
{OP16_SH_DISP11, 0, 0, 0},
{0x7ff, 0, 0, 0},
},
{
PC_DISP19div2, 2, &score_df_range[_DISP19div2],
{OP_SH_DISP19_p1, OP_SH_DISP19_p2, 0, 0},
{0x3ff, 0x1ff, 0, 0},
},
{
PC_DISP24div2, 1, &score_df_range[_DISP24div2],
{OP_SH_DISP24, 0, 0, 0},
{0xffffff, 0, 0, 0},
},
{
Rd_Rs_Rs, 3, NULL,
{OP_SH_REGD, OP_SH_REGS1, OP_SH_REGS2, 0},
{0x1f, 0x1f, 0x1f, 0}
},
{
Rd_Rs_x, 2, NULL,
{OP_SH_REGD, OP_SH_REGS1, 0, 0},
{0x1f, 0x1f, 0, 0},
},
{
Rd_x_Rs, 2, NULL,
{OP_SH_REGD, OP_SH_REGS2, 0, 0},
{0x1f, 0x1f, 0, 0},
},
{
Rd_x_x, 1, NULL,
{OP_SH_REGD, 0, 0, 0},
{0x1f, 0, 0, 0},
},
{
x_Rs_Rs, 2, NULL,
{OP_SH_REGS1, OP_SH_REGS2, 0, 0},
{0x1f, 0x1f, 0, 0},
},
{
x_Rs_x, 1, NULL,
{OP_SH_REGS1, 0, 0, 0},
{0x1f, 0, 0, 0},
},
{
Rd_Rs, 2, NULL,
{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
{0xf, 0xf, 0, 0},
},
{
Rd_HighRs, 2, NULL,
{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
{0xf, 0xf, 0x1f, 0},
},
{
Rd_rvalueRs, 2, NULL,
{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
{0xf, 0xf, 0, 0},
},
{
Rd_lvalueRs, 2, NULL,
{OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
{0xf, 0xf, 0, 0}
},
{
Rd_lvalue32Rs, 2, NULL,
{OP_SH_REGD, OP_SH_REGS1, 0, 0},
{0x1f, 0x1f, 0, 0},
},
{
Rd_rvalue32Rs, 2, NULL,
{OP_SH_REGD, OP_SH_REGS1, 0, 0},
{0x1f, 0x1f, 0, 0},
},
{
x_Rs, 1, NULL,
{OP16_SH_REGS1, 0, 0, 0},
{0xf, 0, 0, 0},
},
{
NO_OPD, 0, NULL,
{0, 0, 0, 0},
{0, 0, 0, 0},
},
{
NO16_OPD, 0, NULL,
{0, 0, 0, 0},
{0, 0, 0, 0},
},
};
 
struct asm_opcode
{
/* Instruction name. */
const char *template;
 
/* Instruction Opcode. */
unsigned long value;
 
/* Instruction bit mask. */
unsigned long bitmask;
 
/* Relax instruction opcode. 0x8000 imply no relaxation. */
unsigned long relax_value;
 
/* Instruction type. */
enum score_insn_type type;
 
/* Function to call to parse args. */
void (*parms) (char *);
};
 
enum insn_class
{
INSN_CLASS_16,
INSN_CLASS_32,
INSN_CLASS_48,
INSN_CLASS_PCE,
INSN_CLASS_SYN
};
 
/* s3_s7: Globals for both tc-score.c and elf32-score.c. */
extern int score3;
extern int score7;
 
#endif
/hppa.h
1,6 → 1,6
/* Table of opcodes for the PA-RISC.
Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,
2001, 2002, 2003, 2004, 2005
2001, 2002, 2003, 2004, 2005, 2006, 2009
Free Software Foundation, Inc.
 
Contributed by the Center for Software Science at the
597,6 → 597,7
{ "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT},
{ "bb", 0xc4004000, 0xfc006000, "?bnx,Q,w", pa10, FLAG_STRICT},
{ "bb", 0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT},
{ "bb", 0xc4004000, 0xfc006000, "?bnx,Q,w", pa10, 0},
{ "bvb", 0xc0004000, 0xffe04000, "?bnx,w", pa10, 0},
{ "clrbts", 0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT},
{ "popbts", 0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT},

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