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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

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Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/gnu-stable/binutils-2.20.1/gas/testsuite/gas/arc
    from Rev 816 to Rev 818
    ↔ Reverse comparison
  •

Rev 816 → Rev 818

/sshift.d
0,0 → 1,44
#objdump: -dr
#name: @OC@
 
# Test the @OC@ insn.
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
00000000 1800@I3+80@00 @OC@ r0,r1
00000004 1b6e@I3+00@00 @OC@ fp,sp
00000008 181f@I3+80@00 @OC@ r0,0
0000000c 183f@I3+81@ff @OC@ r1,-1
00000010 1fe1@I3+00@00 @OC@ 0,r2
00000014 1fe1@I3+81@ff @OC@ -1,r3
00000018 189f@I3+80@ff @OC@ r4,255
0000001c 1fe2@I3+80@ff @OC@ 255,r5
00000020 18df@I3+81@00 @OC@ r6,-256
00000024 1fe3@I3+81@00 @OC@ -256,r7
00000028 191f@I3+00@00 @OC@ r8,256
00000030 193f@I3+00@00 @OC@ r9,-257
00000038 1fc5@I3+00@00 @OC@ 511,r10
00000040 197f@I3+00@00 @OC@ r11,1111638594
00000048 1fc6@I3+00@00 @OC@ 305419896,r12
00000050 1fff@I3+00@ff @OC@ 255,256
00000058 1fdf@I3+80@ff @OC@ 256,255
00000060 181f@I3+00@00 @OC@ r0,0
RELOC: 00000064 R_ARC_32 foo
00000068 1945@I3+80@01 @OC@.eq r10,r11
0000006c 1986@I3+80@02 @OC@.ne r12,r13
00000070 19df@I3+00@0b @OC@.lt r14,0
00000078 19ff@I3+00@09 @OC@.gt r15,512
00000080 1800@I3+81@00 @OC@.f r0,r1
00000084 185e@I3+80@01 @OC@.f r2,1
00000088 1fa2@I3+00@00 @OC@.f 0,r4
0000008c 18bf@I3+01@00 @OC@.f r5,512
00000094 1fc3@I3+01@00 @OC@.f 512,r6
0000009c 1fdf@I3+01@00 @OC@.f 512,512
000000a4 1800@I3+81@01 @OC@.eq.f r0,r1
000000a8 183f@I3+01@02 @OC@.ne.f r1,0
000000b0 1fc1@I3+01@0b @OC@.lt.f 0,r2
000000b8 1fc1@I3+01@09 @OC@.gt.f 1,r2
000000c0 181f@I3+01@0c @OC@.le.f r0,512
000000c8 1fc1@I3+01@0a @OC@.ge.f 512,r2
000000d0 1fdf@I3+01@04 @OC@.n.f 512,512
/swi.d
0,0 → 1,11
#as: -EL -marc8
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <main>:
0: 00 84 00 40 40008400 add r0,r1,r2
4: 02 fe ff 1f 1ffffe02 swi
8: 00 0a 62 50 50620a00 sub r3,r4,r5
/extw.s
0,0 → 1,38
# extw test
 
extw r0,r1
extw fp,sp
 
extw r0,0
extw r1,-1
extw 0,r2
extw -1,r3
extw r4,255
extw 255,r5
extw r6,-256
extw -256,r7
 
extw r8,256
extw r9,-257
extw r11,0x42424242
 
extw 255,256
 
extw r0,foo
 
extw.eq r10,r11
extw.ne r12,r13
extw.lt r14,0
extw.gt r15,512
 
extw.f r0,r1
extw.f r2,1
extw.f 0,r4
extw.f r5,512
extw.f 512,512
 
extw.eq.f r0,r1
extw.ne.f r1,0
extw.lt.f 0,r2
extw.le.f r0,512
extw.n.f 512,512
/add.s
0,0 → 1,68
# add test
 
add r0,r1,r2
add r26,fp,sp
add ilink1,ilink2,blink
add r56,r59,lp_count
 
add r0,r1,0
add r0,0,r2
add 0,r1,r2
add r0,r1,-1
add r0,-1,r2
add -1,r1,r2
add r0,r1,255
add r0,255,r2
add 255,r1,r2
add r0,r1,-256
add r0,-256,r2
add -256,r1,r2
 
add r0,r1,256
add r0,-257,r2
 
add r0,255,256
add r0,256,255
 
add r0,r1,foo
 
add.al r0,r1,r2
add.ra r3,r4,r5
add.eq r6,r7,r8
add.z r9,r10,r11
add.ne r12,r13,r14
add.nz r15,r16,r17
add.pl r18,r19,r20
add.p r21,r22,r23
add.mi r24,r25,r26
add.n r27,r28,r29
add.cs r30,r31,r32
add.c r33,r34,r35
add.lo r36,r37,r38
add.cc r39,r40,r41
add.nc r42,r43,r44
add.hs r45,r46,r47
add.vs r48,r49,r50
add.v r56,r52,r53
add.vc r56,r55,r56
add.nv r56,r58,r59
add.gt r60,r60,r0
add.ge r0,r0,0
add.lt r1,1,r1
add.hi r3,3,r3
add.ls 4,4,r4
add.pnz 5,r5,5
 
add.f r0,r1,r2
add.f r0,r1,1
add.f r0,1,r2
add.f 0,r1,r2
add.f r0,r1,512
add.f r0,512,r2
 
add.eq.f r0,r1,r2
add.ne.f r0,r1,0
add.lt.f r0,0,r2
add.gt.f 0,r1,r2
add.le.f r0,r1,512
add.ge.f r0,512,r2
/sbc.d
0,0 → 1,85
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 84 00 58 58008400 sbc r0,r1,r2
4: 00 b8 4d 5b 5b4db800 sbc gp,fp,sp
8: 00 3e af 5b 5baf3e00 sbc ilink1,ilink2,blink
c: 00 f8 1d 5f 5f1df800 sbc r56,r59,lp_count
10: 00 fe 00 58 5800fe00 sbc r0,r1,0
14: 00 84 1f 58 581f8400 sbc r0,0,r2
18: 00 84 e0 5f 5fe08400 sbc 0,r1,r2
1c: ff ff 00 58 5800ffff sbc r0,r1,-1
20: ff 85 1f 58 581f85ff sbc r0,-1,r2
24: 00 84 e0 5f 5fe08400 sbc 0,r1,r2
28: ff fe 00 58 5800feff sbc r0,r1,255
2c: ff 84 1f 58 581f84ff sbc r0,255,r2
30: 00 84 e0 5f 5fe08400 sbc 0,r1,r2
34: 00 ff 00 58 5800ff00 sbc r0,r1,-256
38: 00 85 1f 58 581f8500 sbc r0,-256,r2
3c: 00 84 e0 5f 5fe08400 sbc 0,r1,r2
40: 00 fc 00 58 5800fc00 sbc r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 58 581f0400 sbc r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 58 581ffcff sbc r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 58 581f7eff sbc r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 58 5800fc00 sbc r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 58 58008400 sbc r0,r1,r2
6c: 00 0a 62 58 58620a00 sbc r3,r4,r5
70: 01 90 c3 58 58c39001 sbc.z r6,r7,r8
74: 01 16 25 59 59251601 sbc.z r9,r10,r11
78: 02 9c 86 59 59869c02 sbc.nz r12,r13,r14
7c: 02 22 e8 59 59e82202 sbc.nz r15,r16,r17
80: 03 a8 49 5a 5a49a803 sbc.p r18,r19,r20
84: 03 2e ab 5a 5aab2e03 sbc.p r21,r22,r23
88: 04 b4 0c 5b 5b0cb404 sbc.n r24,r25,gp
8c: 04 3a 6e 5b 5b6e3a04 sbc.n fp,sp,ilink1
90: 05 c0 cf 5b 5bcfc005 sbc.c ilink2,blink,r32
94: 05 46 31 5c 5c314605 sbc.c r33,r34,r35
98: 05 cc 92 5c 5c92cc05 sbc.c r36,r37,r38
9c: 06 52 f4 5c 5cf45206 sbc.nc r39,r40,r41
a0: 06 d8 55 5d 5d55d806 sbc.nc r42,r43,r44
a4: 06 5e b7 5d 5db75e06 sbc.nc r45,r46,r47
a8: 07 e4 18 5e 5e18e407 sbc.v r48,r49,r50
ac: 07 6a 1a 5f 5f1a6a07 sbc.v r56,r52,r53
b0: 08 f0 1b 5f 5f1bf008 sbc.nv r56,r55,r56
b4: 08 76 1d 5f 5f1d7608 sbc.nv r56,r58,r59
b8: 09 00 9e 5f 5f9e0009 sbc.gt lp_count,lp_count,r0
bc: 0a 7c 00 58 58007c0a sbc.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 58 583f020b sbc.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 58 587f060d sbc.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 5f 5fdf080e sbc.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 5f 5fc2fc0f sbc.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 58 58008500 sbc.f r0,r1,r2
e8: 01 fa 00 58 5800fa01 sbc.f r0,r1,1
ec: 01 84 1e 58 581e8401 sbc.f r0,1,r2
f0: 00 85 e0 5f 5fe08500 sbc.f 0,r1,r2
f4: 00 fd 00 58 5800fd00 sbc.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 58 581f0500 sbc.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 58 58008501 sbc.z.f r0,r1,r2
108: 02 fd 00 58 5800fd02 sbc.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 58 581f050b sbc.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 5f 5fc08509 sbc.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 58 5800fd0c sbc.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 58 581f050a sbc.ge.f r0,0x200,r2
12c: 00 02 00 00
/sub.s
0,0 → 1,68
# sub test
 
sub r0,r1,r2
sub r26,fp,sp
sub ilink1,ilink2,blink
sub r56,r59,lp_count
 
sub r0,r1,0
sub r0,0,r2
sub 0,r1,r2
sub r0,r1,-1
sub r0,-1,r2
sub -1,r1,r2
sub r0,r1,255
sub r0,255,r2
sub 255,r1,r2
sub r0,r1,-256
sub r0,-256,r2
sub -256,r1,r2
 
sub r0,r1,256
sub r0,-257,r2
 
sub r0,255,256
sub r0,256,255
 
sub r0,r1,foo
 
sub.al r0,r1,r2
sub.ra r3,r4,r5
sub.eq r6,r7,r8
sub.z r9,r10,r11
sub.ne r12,r13,r14
sub.nz r15,r16,r17
sub.pl r18,r19,r20
sub.p r21,r22,r23
sub.mi r24,r25,r26
sub.n r27,r28,r29
sub.cs r30,r31,r32
sub.c r33,r34,r35
sub.lo r36,r37,r38
sub.cc r39,r40,r41
sub.nc r42,r43,r44
sub.hs r45,r46,r47
sub.vs r48,r49,r50
sub.v r56,r52,r53
sub.vc r56,r55,r56
sub.nv r56,r58,r59
sub.gt r60,r60,r0
sub.ge r0,r0,0
sub.lt r1,1,r1
sub.hi r3,3,r3
sub.ls 4,4,r4
sub.pnz 5,r5,5
 
sub.f r0,r1,r2
sub.f r0,r1,1
sub.f r0,1,r2
sub.f 0,r1,r2
sub.f r0,r1,512
sub.f r0,512,r2
 
sub.eq.f r0,r1,r2
sub.ne.f r0,r1,0
sub.lt.f r0,0,r2
sub.gt.f 0,r1,r2
sub.le.f r0,r1,512
sub.ge.f r0,512,r2
/sleep.d
0,0 → 1,11
#as: -EL -marc7
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <main>:
0: 00 84 00 40 40008400 add r0,r1,r2
4: 01 fe ff 1f 1ffffe01 sleep
8: 00 0a 62 50 50620a00 sub r3,r4,r5
/brk.d
0,0 → 1,11
#as: -EL -marc7
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <main>:
0: 00 84 00 40 40008400 add r0,r1,r2
4: 00 fe ff 1f 1ffffe00 brk
8: 00 0a 62 50 50620a00 sub r3,r4,r5
/sshift.s
0,0 → 1,52
# Single shift @OC@ test
 
# reg,reg
@OC@ r0,r1
@OC@ fp,sp
 
# shimm values
@OC@ r0,0
@OC@ r1,-1
@OC@ 0,r2
@OC@ -1,r3
@OC@ r4,255
@OC@ 255,r5
@OC@ r6,-256
@OC@ -256,r7
 
# limm values
@OC@ r8,256
@OC@ r9,-257
@OC@ 511,r10
@OC@ r11,0x42424242
@OC@ 0x12345678,r12
 
# shimm and limm
@OC@ 255,256
@OC@ 256,255
 
# symbols
@OC@ r0,foo
 
# conditional execution
@OC@.eq r10,r11
@OC@.ne r12,r13
@OC@.lt r14,0
@OC@.gt r15,512
 
# flag setting
@OC@.f r0,r1
@OC@.f r2,1
@OC@.f 0,r4
@OC@.f r5,512
@OC@.f 512,r6
@OC@.f 512,512
 
# conditional execution + flag setting
@OC@.eq.f r0,r1
@OC@.ne.f r1,0
@OC@.lt.f 0,r2
@OC@.gt.f 1,r2
@OC@.le.f r0,512
@OC@.ge.f 512,r2
@OC@.n.f 512,512
/swi.s
0,0 → 1,6
# swi test
 
main:
add r0,r1,r2
swi
sub r3,r4,r5
/rrc.d
0,0 → 1,51
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 88 00 18 18008800 rrc r0,r1
4: 00 08 6e 1b 1b6e0800 rrc fp,sp
8: 00 88 1f 18 181f8800 rrc r0,0
c: ff 89 3f 18 183f89ff rrc r1,-1
10: 00 08 e1 1f 1fe10800 rrc 0,r2
14: 00 88 e1 1f 1fe18800 rrc 0,r3
18: ff 88 9f 18 189f88ff rrc r4,255
1c: 00 88 e2 1f 1fe28800 rrc 0,r5
20: 00 89 df 18 18df8900 rrc r6,-256
24: 00 88 e3 1f 1fe38800 rrc 0,r7
28: 00 08 1f 19 191f0800 rrc r8,0x100
2c: 00 01 00 00
30: 00 08 3f 19 193f0800 rrc r9,0xffff_feff
34: ff fe ff ff
38: 00 08 7f 19 197f0800 rrc r11,0x4242_4242
3c: 42 42 42 42
40: 00 08 ff 1f 1fff0800 rrc 0,0x100
44: 00 01 00 00
48: 00 08 1f 18 181f0800 rrc r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 88 45 19 19458801 rrc.z r10,r11
54: 02 88 86 19 19868802 rrc.nz r12,r13
58: 0b 08 df 19 19df080b rrc.lt r14,0
5c: 00 00 00 00
60: 09 08 ff 19 19ff0809 rrc.gt r15,0x200
64: 00 02 00 00
68: 00 89 00 18 18008900 rrc.f r0,r1
6c: 01 88 5e 18 185e8801 rrc.f r2,1
70: 00 09 e2 1f 1fe20900 rrc.f 0,r4
74: 00 09 bf 18 18bf0900 rrc.f r5,0x200
78: 00 02 00 00
7c: 00 09 df 1f 1fdf0900 rrc.f 0,0x200
80: 00 02 00 00
84: 01 89 00 18 18008901 rrc.z.f r0,r1
88: 02 09 3f 18 183f0902 rrc.nz.f r1,0
8c: 00 00 00 00
90: 0b 09 c1 1f 1fc1090b rrc.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 09 1f 18 181f090c rrc.le.f r0,0x200
9c: 00 02 00 00
a0: 04 09 df 1f 1fdf0904 rrc.n.f 0,0x200
a4: 00 02 00 00
/sbc.s
0,0 → 1,68
# sbc test
 
sbc r0,r1,r2
sbc r26,fp,sp
sbc ilink1,ilink2,blink
sbc r56,r59,lp_count
 
sbc r0,r1,0
sbc r0,0,r2
sbc 0,r1,r2
sbc r0,r1,-1
sbc r0,-1,r2
sbc -1,r1,r2
sbc r0,r1,255
sbc r0,255,r2
sbc 255,r1,r2
sbc r0,r1,-256
sbc r0,-256,r2
sbc -256,r1,r2
 
sbc r0,r1,256
sbc r0,-257,r2
 
sbc r0,255,256
sbc r0,256,255
 
sbc r0,r1,foo
 
sbc.al r0,r1,r2
sbc.ra r3,r4,r5
sbc.eq r6,r7,r8
sbc.z r9,r10,r11
sbc.ne r12,r13,r14
sbc.nz r15,r16,r17
sbc.pl r18,r19,r20
sbc.p r21,r22,r23
sbc.mi r24,r25,r26
sbc.n r27,r28,r29
sbc.cs r30,r31,r32
sbc.c r33,r34,r35
sbc.lo r36,r37,r38
sbc.cc r39,r40,r41
sbc.nc r42,r43,r44
sbc.hs r45,r46,r47
sbc.vs r48,r49,r50
sbc.v r56,r52,r53
sbc.vc r56,r55,r56
sbc.nv r56,r58,r59
sbc.gt r60,r60,r0
sbc.ge r0,r0,0
sbc.lt r1,1,r1
sbc.hi r3,3,r3
sbc.ls 4,4,r4
sbc.pnz 5,r5,5
 
sbc.f r0,r1,r2
sbc.f r0,r1,1
sbc.f r0,1,r2
sbc.f 0,r1,r2
sbc.f r0,r1,512
sbc.f r0,512,r2
 
sbc.eq.f r0,r1,r2
sbc.ne.f r0,r1,0
sbc.lt.f r0,0,r2
sbc.gt.f 0,r1,r2
sbc.le.f r0,r1,512
sbc.ge.f r0,512,r2
/sleep.s
0,0 → 1,6
# sleep test
 
main:
add r0,r1,r2
sleep
sub r3,r4,r5
/math.d
0,0 → 1,78
#objdump: -dr
#name: @OC@
 
# Test the @OC@ insn.
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
00000000 @IC+0@008400 @OC@ r0,r1,r2
00000004 @IC+3@4db800 @OC@ r26,fp,sp
00000008 @IC+3@af3e00 @OC@ ilink1,ilink2,blink
0000000c @IC+7@5df800 @OC@ r58,r59,lp_count
00000010 @IC+0@00fe00 @OC@ r0,r1,0
00000014 @IC+0@1f8400 @OC@ r0,0,r2
00000018 @IC+7@e08400 @OC@ 0,r1,r2
0000001c @IC+0@00ffff @OC@ r0,r1,-1
00000020 @IC+0@1f85ff @OC@ r0,-1,r2
00000024 @IC+7@e085ff @OC@ -1,r1,r2
00000028 @IC+0@00feff @OC@ r0,r1,255
0000002c @IC+0@1f84ff @OC@ r0,255,r2
00000030 @IC+7@e084ff @OC@ 255,r1,r2
00000034 @IC+0@00ff00 @OC@ r0,r1,-256
00000038 @IC+0@1f8500 @OC@ r0,-256,r2
0000003c @IC+7@e08500 @OC@ -256,r1,r2
00000040 @IC+0@00fc00 @OC@ r0,r1,256
00000048 @IC+0@1f0400 @OC@ r0,-257,r2
00000050 @IC+7@c08400 @OC@ 511,r1,r2
00000058 @IC+0@1f0400 @OC@ r0,1111638594,r2
00000060 @IC+7@c0fc00 @OC@ 305419896,r1,305419896
00000068 @IC+0@1ffcff @OC@ r0,255,256
00000070 @IC+0@1f7eff @OC@ r0,256,255
00000078 @IC+7@e0fcff @OC@ 255,r1,256
00000080 @IC+7@ff04ff @OC@ 255,256,r2
00000088 @IC+7@c0feff @OC@ 256,r1,255
00000090 @IC+7@df84ff @OC@ 256,255,r2
00000098 @IC+0@00fc00 @OC@ r0,r1,0
RELOC: 0000009c R_ARC_32 foo
000000a0 @IC+0@008400 @OC@ r0,r1,r2
000000a4 @IC+0@620a00 @OC@ r3,r4,r5
000000a8 @IC+0@c39001 @OC@.eq r6,r7,r8
000000ac @IC+1@251601 @OC@.eq r9,r10,r11
000000b0 @IC+1@869c02 @OC@.ne r12,r13,r14
000000b4 @IC+1@e82202 @OC@.ne r15,r16,r17
000000b8 @IC+2@49a803 @OC@.p r18,r19,r20
000000bc @IC+2@ab2e03 @OC@.p r21,r22,r23
000000c0 @IC+3@0cb404 @OC@.n r24,r25,r26
000000c4 @IC+3@6e3a04 @OC@.n fp,sp,ilink1
000000c8 @IC+3@cfc005 @OC@.c ilink2,blink,r32
000000cc @IC+4@314605 @OC@.c r33,r34,r35
000000d0 @IC+4@92cc05 @OC@.c r36,r37,r38
000000d4 @IC+4@f45206 @OC@.nc r39,r40,r41
000000d8 @IC+5@55d806 @OC@.nc r42,r43,r44
000000dc @IC+5@b75e06 @OC@.nc r45,r46,r47
000000e0 @IC+6@18e407 @OC@.v r48,r49,r50
000000e4 @IC+6@7a6a07 @OC@.v r51,r52,r53
000000e8 @IC+6@dbf008 @OC@.nv r54,r55,r56
000000ec @IC+7@3d7608 @OC@.nv r57,r58,r59
000000f0 @IC+7@9e0009 @OC@.gt lp_count,lp_count,r0
000000f4 @IC+0@007c0a @OC@.ge r0,r0,0
000000fc @IC+0@3f020b @OC@.lt r1,1,r1
00000104 @IC+7@c0840c @OC@.le 2,r1,r2
0000010c @IC+0@7f060d @OC@.hi r3,3,r3
00000114 @IC+7@df080e @OC@.ls 4,4,r4
0000011c @IC+7@c2fc0f @OC@.pnz 5,r5,5
00000124 @IC+0@008500 @OC@.f r0,r1,r2
00000128 @IC+0@00fa01 @OC@.f r0,r1,1
0000012c @IC+0@1e8401 @OC@.f r0,1,r2
00000130 @IC+7@a08400 @OC@.f 0,r1,r2
00000134 @IC+0@00fd00 @OC@.f r0,r1,512
0000013c @IC+0@1f0500 @OC@.f r0,512,r2
00000144 @IC+7@c08500 @OC@.f 512,r1,r2
0000014c @IC+0@008501 @OC@.eq.f r0,r1,r2
00000150 @IC+0@00fd02 @OC@.ne.f r0,r1,0
00000158 @IC+0@1f050b @OC@.lt.f r0,0,r2
00000160 @IC+7@c08509 @OC@.gt.f 0,r1,r2
00000168 @IC+0@00fd0c @OC@.le.f r0,r1,512
00000170 @IC+0@1f050a @OC@.ge.f r0,512,r2
00000178 @IC+7@c08504 @OC@.n.f 512,r1,r2
/brk.s
0,0 → 1,7
# brk test
 
main:
 
add r0,r1,r2
brk
sub r3,r4,r5
/bic.d
0,0 → 1,85
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 84 00 70 70008400 bic r0,r1,r2
4: 00 b8 4d 73 734db800 bic gp,fp,sp
8: 00 3e af 73 73af3e00 bic ilink1,ilink2,blink
c: 00 f8 1d 77 771df800 bic r56,r59,lp_count
10: 00 fe 00 70 7000fe00 bic r0,r1,0
14: 00 84 1f 70 701f8400 bic r0,0,r2
18: 00 84 e0 77 77e08400 bic 0,r1,r2
1c: ff ff 00 70 7000ffff bic r0,r1,-1
20: ff 85 1f 70 701f85ff bic r0,-1,r2
24: 00 84 e0 77 77e08400 bic 0,r1,r2
28: ff fe 00 70 7000feff bic r0,r1,255
2c: ff 84 1f 70 701f84ff bic r0,255,r2
30: 00 84 e0 77 77e08400 bic 0,r1,r2
34: 00 ff 00 70 7000ff00 bic r0,r1,-256
38: 00 85 1f 70 701f8500 bic r0,-256,r2
3c: 00 84 e0 77 77e08400 bic 0,r1,r2
40: 00 fc 00 70 7000fc00 bic r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 70 701f0400 bic r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 70 701ffcff bic r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 70 701f7eff bic r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 70 7000fc00 bic r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 70 70008400 bic r0,r1,r2
6c: 00 0a 62 70 70620a00 bic r3,r4,r5
70: 01 90 c3 70 70c39001 bic.z r6,r7,r8
74: 01 16 25 71 71251601 bic.z r9,r10,r11
78: 02 9c 86 71 71869c02 bic.nz r12,r13,r14
7c: 02 22 e8 71 71e82202 bic.nz r15,r16,r17
80: 03 a8 49 72 7249a803 bic.p r18,r19,r20
84: 03 2e ab 72 72ab2e03 bic.p r21,r22,r23
88: 04 b4 0c 73 730cb404 bic.n r24,r25,gp
8c: 04 3a 6e 73 736e3a04 bic.n fp,sp,ilink1
90: 05 c0 cf 73 73cfc005 bic.c ilink2,blink,r32
94: 05 46 31 74 74314605 bic.c r33,r34,r35
98: 05 cc 92 74 7492cc05 bic.c r36,r37,r38
9c: 06 52 f4 74 74f45206 bic.nc r39,r40,r41
a0: 06 d8 55 75 7555d806 bic.nc r42,r43,r44
a4: 06 5e b7 75 75b75e06 bic.nc r45,r46,r47
a8: 07 e4 18 76 7618e407 bic.v r48,r49,r50
ac: 07 6a 1a 77 771a6a07 bic.v r56,r52,r53
b0: 08 f0 1b 77 771bf008 bic.nv r56,r55,r56
b4: 08 76 1d 77 771d7608 bic.nv r56,r58,r59
b8: 09 00 9e 77 779e0009 bic.gt lp_count,lp_count,r0
bc: 0a 7c 00 70 70007c0a bic.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 70 703f020b bic.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 70 707f060d bic.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 77 77df080e bic.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 77 77c2fc0f bic.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 70 70008500 bic.f r0,r1,r2
e8: 01 fa 00 70 7000fa01 bic.f r0,r1,1
ec: 01 84 1e 70 701e8401 bic.f r0,1,r2
f0: 00 85 e0 77 77e08500 bic.f 0,r1,r2
f4: 00 fd 00 70 7000fd00 bic.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 70 701f0500 bic.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 70 70008501 bic.z.f r0,r1,r2
108: 02 fd 00 70 7000fd02 bic.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 70 701f050b bic.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 77 77c08509 bic.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 70 7000fd0c bic.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 70 701f050a bic.ge.f r0,0x200,r2
12c: 00 02 00 00
/ld.d
0,0 → 1,16
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 84 00 00 00008400 ld r0,\[r1,r2\]
4: 02 84 00 00 00008402 ldb r0,\[r1,r2\]
8: 08 88 21 00 00218808 ld.a r1,\[r3,r4\]
c: 05 06 21 00 00210605 ldw.x r1,\[r2,r3\]
10: 0d 88 41 00 0041880d ldw.x.a r2,\[r3,r4\]
14: 00 80 1f 08 081f8000 ld r0,\[0\]
18: 1e 80 00 08 0800801e ld r0,\[r1,30\]
1c: ec 01 21 08 082101ec ld r1,\[r2,-20\]
/extensions.d
0,0 → 1,12
#as: -EL -marc8
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <condcodeTest>:
0: 12 02 00 40 40000212 add.isbusy r0,r0,r1
4: 00 02 60 45 45600200 add rwscreg,r0,r1
8: 00 d8 00 40 4000d800 add r0,r1,roscreg
c: 00 02 a0 45 45a00200 add woscreg,r0,r1
/extb.d
0,0 → 1,51
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 8e 00 18 18008e00 extb r0,r1
4: 00 0e 6e 1b 1b6e0e00 extb fp,sp
8: 00 8e 1f 18 181f8e00 extb r0,0
c: ff 8f 3f 18 183f8fff extb r1,-1
10: 00 0e e1 1f 1fe10e00 extb 0,r2
14: 00 8e e1 1f 1fe18e00 extb 0,r3
18: ff 8e 9f 18 189f8eff extb r4,255
1c: 00 8e e2 1f 1fe28e00 extb 0,r5
20: 00 8f df 18 18df8f00 extb r6,-256
24: 00 8e e3 1f 1fe38e00 extb 0,r7
28: 00 0e 1f 19 191f0e00 extb r8,0x100
2c: 00 01 00 00
30: 00 0e 3f 19 193f0e00 extb r9,0xffff_feff
34: ff fe ff ff
38: 00 0e 7f 19 197f0e00 extb r11,0x4242_4242
3c: 42 42 42 42
40: 00 0e ff 1f 1fff0e00 extb 0,0x100
44: 00 01 00 00
48: 00 0e 1f 18 181f0e00 extb r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 8e 45 19 19458e01 extb.z r10,r11
54: 02 8e 86 19 19868e02 extb.nz r12,r13
58: 0b 0e df 19 19df0e0b extb.lt r14,0
5c: 00 00 00 00
60: 09 0e ff 19 19ff0e09 extb.gt r15,0x200
64: 00 02 00 00
68: 00 8f 00 18 18008f00 extb.f r0,r1
6c: 01 8e 5e 18 185e8e01 extb.f r2,1
70: 00 0f e2 1f 1fe20f00 extb.f 0,r4
74: 00 0f bf 18 18bf0f00 extb.f r5,0x200
78: 00 02 00 00
7c: 00 0f df 1f 1fdf0f00 extb.f 0,0x200
80: 00 02 00 00
84: 01 8f 00 18 18008f01 extb.z.f r0,r1
88: 02 0f 3f 18 183f0f02 extb.nz.f r1,0
8c: 00 00 00 00
90: 0b 0f c1 1f 1fc10f0b extb.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 0f 1f 18 181f0f0c extb.le.f r0,0x200
9c: 00 02 00 00
a0: 04 0f df 1f 1fdf0f04 extb.n.f 0,0x200
a4: 00 02 00 00
/rrc.s
0,0 → 1,38
# rrc test
 
rrc r0,r1
rrc fp,sp
 
rrc r0,0
rrc r1,-1
rrc 0,r2
rrc -1,r3
rrc r4,255
rrc 255,r5
rrc r6,-256
rrc -256,r7
 
rrc r8,256
rrc r9,-257
rrc r11,0x42424242
 
rrc 255,256
 
rrc r0,foo
 
rrc.eq r10,r11
rrc.ne r12,r13
rrc.lt r14,0
rrc.gt r15,512
 
rrc.f r0,r1
rrc.f r2,1
rrc.f 0,r4
rrc.f r5,512
rrc.f 512,512
 
rrc.eq.f r0,r1
rrc.ne.f r1,0
rrc.lt.f 0,r2
rrc.le.f r0,512
rrc.n.f 512,512
/math.s
0,0 → 1,89
# @OC@ test
 
# Stay away from operands with duplicate arguments (eg: add r0,r1,r1).
# They will be disassembled as they're macro counterparts (eg: asl r0,r1).
 
# reg,reg,reg
@OC@ r0,r1,r2
@OC@ r26,fp,sp
@OC@ ilink1,ilink2,blink
@OC@ r58,r59,lp_count
 
# shimm values
@OC@ r0,r1,0
@OC@ r0,0,r2
@OC@ 0,r1,r2
@OC@ r0,r1,-1
@OC@ r0,-1,r2
@OC@ -1,r1,r2
@OC@ r0,r1,255
@OC@ r0,255,r2
@OC@ 255,r1,r2
@OC@ r0,r1,-256
@OC@ r0,-256,r2
@OC@ -256,r1,r2
 
# limm values
@OC@ r0,r1,256
@OC@ r0,-257,r2
@OC@ 511,r1,r2
@OC@ r0,0x42424242,r2
@OC@ 0x12345678,r1,0x12345678
 
# shimm and limm
@OC@ r0,255,256
@OC@ r0,256,255
@OC@ 255,r1,256
@OC@ 255,256,r2
@OC@ 256,r1,255
@OC@ 256,255,r2
 
# symbols
@OC@ r0,r1,foo
 
# conditional execution
@OC@.al r0,r1,r2
@OC@.ra r3,r4,r5
@OC@.eq r6,r7,r8
@OC@.z r9,r10,r11
@OC@.ne r12,r13,r14
@OC@.nz r15,r16,r17
@OC@.pl r18,r19,r20
@OC@.p r21,r22,r23
@OC@.mi r24,r25,r26
@OC@.n r27,r28,r29
@OC@.cs r30,r31,r32
@OC@.c r33,r34,r35
@OC@.lo r36,r37,r38
@OC@.cc r39,r40,r41
@OC@.nc r42,r43,r44
@OC@.hs r45,r46,r47
@OC@.vs r48,r49,r50
@OC@.v r51,r52,r53
@OC@.vc r54,r55,r56
@OC@.nv r57,r58,r59
@OC@.gt r60,r60,r0
@OC@.ge r0,r0,0
@OC@.lt r1,1,r1
@OC@.le 2,r1,r2
@OC@.hi r3,3,r3
@OC@.ls 4,4,r4
@OC@.pnz 5,r5,5
 
# flag setting
@OC@.f r0,r1,r2
@OC@.f r0,r1,1
@OC@.f r0,1,r2
@OC@.f 0,r1,r2
@OC@.f r0,r1,512
@OC@.f r0,512,r2
@OC@.f 512,r1,r2
 
# conditional execution + flag setting
@OC@.eq.f r0,r1,r2
@OC@.ne.f r0,r1,0
@OC@.lt.f r0,0,r2
@OC@.gt.f 0,r1,r2
@OC@.le.f r0,r1,512
@OC@.ge.f r0,512,r2
@OC@.n.f 512,r1,r2
/lp.d
0,0 → 1,76
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <text_label>:
0: 80 ff ff 37 37ffff80 lp 0 <text_label>
 
4: 00 ff ff 37 37ffff00 lp 0 <text_label>
 
8: 80 fe ff 37 37fffe80 lp 0 <text_label>
 
c: 01 fe ff 37 37fffe01 lpz 0 <text_label>
 
10: 81 fd ff 37 37fffd81 lpz 0 <text_label>
 
14: 02 fd ff 37 37fffd02 lpnz 0 <text_label>
 
18: 82 fc ff 37 37fffc82 lpnz 0 <text_label>
 
1c: 03 fc ff 37 37fffc03 lpp 0 <text_label>
 
20: 83 fb ff 37 37fffb83 lpp 0 <text_label>
 
24: 04 fb ff 37 37fffb04 lpn 0 <text_label>
 
28: 84 fa ff 37 37fffa84 lpn 0 <text_label>
 
2c: 05 fa ff 37 37fffa05 lpc 0 <text_label>
 
30: 85 f9 ff 37 37fff985 lpc 0 <text_label>
 
34: 05 f9 ff 37 37fff905 lpc 0 <text_label>
 
38: 86 f8 ff 37 37fff886 lpnc 0 <text_label>
 
3c: 06 f8 ff 37 37fff806 lpnc 0 <text_label>
 
40: 86 f7 ff 37 37fff786 lpnc 0 <text_label>
 
44: 07 f7 ff 37 37fff707 lpv 0 <text_label>
 
48: 87 f6 ff 37 37fff687 lpv 0 <text_label>
 
4c: 08 f6 ff 37 37fff608 lpnv 0 <text_label>
 
50: 88 f5 ff 37 37fff588 lpnv 0 <text_label>
 
54: 09 f5 ff 37 37fff509 lpgt 0 <text_label>
 
58: 8a f4 ff 37 37fff48a lpge 0 <text_label>
 
5c: 0b f4 ff 37 37fff40b lplt 0 <text_label>
 
60: 8c f3 ff 37 37fff38c lple 0 <text_label>
 
64: 0d f3 ff 37 37fff30d lphi 0 <text_label>
 
68: 8e f2 ff 37 37fff28e lpls 0 <text_label>
 
6c: 0f f2 ff 37 37fff20f lppnz 0 <text_label>
 
70: a0 f1 ff 37 37fff1a0 lp.d 0 <text_label>
 
74: 00 f1 ff 37 37fff100 lp 0 <text_label>
 
78: c0 f0 ff 37 37fff0c0 lp.jd 0 <text_label>
 
7c: 21 f0 ff 37 37fff021 lpz.d 0 <text_label>
 
80: 82 ef ff 37 37ffef82 lpnz 0 <text_label>
 
84: 46 ef ff 37 37ffef46 lpnc.jd 0 <text_label>
 
/bic.s
0,0 → 1,68
# bic test
 
bic r0,r1,r2
bic r26,fp,sp
bic ilink1,ilink2,blink
bic r56,r59,lp_count
 
bic r0,r1,0
bic r0,0,r2
bic 0,r1,r2
bic r0,r1,-1
bic r0,-1,r2
bic -1,r1,r2
bic r0,r1,255
bic r0,255,r2
bic 255,r1,r2
bic r0,r1,-256
bic r0,-256,r2
bic -256,r1,r2
 
bic r0,r1,256
bic r0,-257,r2
 
bic r0,255,256
bic r0,256,255
 
bic r0,r1,foo
 
bic.al r0,r1,r2
bic.ra r3,r4,r5
bic.eq r6,r7,r8
bic.z r9,r10,r11
bic.ne r12,r13,r14
bic.nz r15,r16,r17
bic.pl r18,r19,r20
bic.p r21,r22,r23
bic.mi r24,r25,r26
bic.n r27,r28,r29
bic.cs r30,r31,r32
bic.c r33,r34,r35
bic.lo r36,r37,r38
bic.cc r39,r40,r41
bic.nc r42,r43,r44
bic.hs r45,r46,r47
bic.vs r48,r49,r50
bic.v r56,r52,r53
bic.vc r56,r55,r56
bic.nv r56,r58,r59
bic.gt r60,r60,r0
bic.ge r0,r0,0
bic.lt r1,1,r1
bic.hi r3,3,r3
bic.ls 4,4,r4
bic.pnz 5,r5,5
 
bic.f r0,r1,r2
bic.f r0,r1,1
bic.f r0,1,r2
bic.f 0,r1,r2
bic.f r0,r1,512
bic.f r0,512,r2
 
bic.eq.f r0,r1,r2
bic.ne.f r0,r1,0
bic.lt.f r0,0,r2
bic.gt.f 0,r1,r2
bic.le.f r0,r1,512
bic.ge.f r0,512,r2
/ld.s
0,0 → 1,10
# ld test
ld r0,[r1,r2]
ldb r0,[r1,r2]
ld.a r1,[r3,r4]
ldw.x r1,[r2,r3]
ldw.x.a r2,[r3,r4]
ld r0,[0]
ld r0,[r1,30]
ld r1,[r2,-20]
/arc.exp
0,0 → 1,46
# ARC base instruction set (to arc8)
if [istarget arc*-*-*] then {
run_dump_test ld
run_dump_test ld2
run_dump_test st
 
# Specially encoded/single operand instructions
run_dump_test flag
run_dump_test brk
run_dump_test sleep
run_dump_test swi
run_dump_test asr
run_dump_test lsr
run_dump_test ror
run_dump_test rrc
run_dump_test sexb
run_dump_test sexw
run_dump_test extb
run_dump_test extw
 
run_dump_test b
run_dump_test bl
run_dump_test lp
run_dump_test j
run_dump_test jl
run_dump_test add
run_dump_test asl
# FIXME: ??? `lsl' gets dumped as `asl'
# run_dump_test lsl
run_dump_test adc
run_dump_test rlc
run_dump_test sub
run_dump_test sbc
run_dump_test and
run_dump_test mov
run_dump_test or
run_dump_test bic
run_dump_test xor
run_dump_test nop
run_dump_test extensions
}
 
# ARC library extensions
if [istarget arc*-*-*] then {
# *TODO*
}
/extensions.s
0,0 → 1,10
.extCondCode isbusy, 0x12
.extCoreRegister rwscreg,43,r|w,can_shortcut
.extCoreRegister roscreg,44,r,can_shortcut
.extCoreRegister woscreg,45,w,can_shortcut
.section .text
condcodeTest:
add.isbusy r0,r0,r1
add rwscreg,r0,r1
add r0,r1,roscreg
add woscreg,r0,r1
/asl.d
0,0 → 1,68
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 82 00 40 40008200 asl r0,r1
4: 00 38 6e 43 436e3800 asl fp,sp
8: 00 fe 1f 40 401ffe00 asl r0,0
c: ff ff 3f 40 403fffff asl r1,-1
10: 00 04 e1 47 47e10400 asl 0,r2
14: 00 86 e1 47 47e18600 asl 0,r3
18: ff fe 9f 40 409ffeff asl r4,255
1c: 00 8a e2 47 47e28a00 asl 0,r5
20: 00 ff df 40 40dfff00 asl r6,-256
24: 00 8e e3 47 47e38e00 asl 0,r7
28: 00 7c 1f 41 411f7c00 asl r8,0x100
2c: 00 01 00 00
30: 00 7c 3f 41 413f7c00 asl r9,0xffff_feff
34: ff fe ff ff
38: 00 7c 7f 41 417f7c00 asl r11,0x4242_4242
3c: 42 42 42 42
40: 00 7c ff 47 47ff7c00 asl 0,0x100
44: 00 01 00 00
48: 00 7c 1f 40 401f7c00 asl r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 00 82 00 40 40008200 asl r0,r1
54: 00 08 62 40 40620800 asl r3,r4
58: 01 8e c3 40 40c38e01 asl.z r6,r7
5c: 01 14 25 41 41251401 asl.z r9,r10
60: 02 9a 86 41 41869a02 asl.nz r12,r13
64: 02 20 e8 41 41e82002 asl.nz r15,r16
68: 03 a6 49 42 4249a603 asl.p r18,r19
6c: 03 2c ab 42 42ab2c03 asl.p r21,r22
70: 04 b2 0c 43 430cb204 asl.n r24,r25
74: 04 38 6e 43 436e3804 asl.n fp,sp
78: 05 be cf 43 43cfbe05 asl.c ilink2,blink
7c: 05 44 31 44 44314405 asl.c r33,r34
80: 05 ca 92 44 4492ca05 asl.c r36,r37
84: 06 50 f4 44 44f45006 asl.nc r39,r40
88: 06 d6 55 45 4555d606 asl.nc r42,r43
8c: 06 5c b7 45 45b75c06 asl.nc r45,r46
90: 07 e2 18 46 4618e207 asl.v r48,r49
94: 07 64 39 46 46396407 asl.v r49,r50
98: 08 ee 3b 46 463bee08 asl.nv r49,r55
9c: 08 74 3d 46 463d7408 asl.nv r49,r58
a0: 09 78 9e 47 479e7809 asl.gt lp_count,lp_count
a4: 0a 7c 1f 40 401f7c0a asl.ge r0,0
a8: 00 00 00 00
ac: 0c 7c df 47 47df7c0c asl.le 0,2
b0: 02 00 00 00
b4: 0d 86 61 40 4061860d asl.hi r3,r3
b8: 0e 08 82 40 4082080e asl.ls r4,r4
bc: 0f 8a a2 40 40a28a0f asl.pnz r5,r5
c0: 00 83 00 40 40008300 asl.f r0,r1
c4: 01 fa 5e 40 405efa01 asl.f r2,1
c8: 00 87 e1 47 47e18700 asl.f 0,r3
cc: 00 09 e2 47 47e20900 asl.f 0,r4
d0: 00 7d bf 40 40bf7d00 asl.f r5,0x200
d4: 00 02 00 00
d8: 00 7d df 47 47df7d00 asl.f 0,0x200
dc: 00 02 00 00
e0: 01 83 00 40 40008301 asl.z.f r0,r1
e4: 02 7d 3f 40 403f7d02 asl.nz.f r1,0
e8: 00 00 00 00
/b.d
0,0 → 1,76
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <text_label>:
0: 80 ff ff 27 27ffff80 b 0 <text_label>
 
4: 00 ff ff 27 27ffff00 b 0 <text_label>
 
8: 80 fe ff 27 27fffe80 b 0 <text_label>
 
c: 01 fe ff 27 27fffe01 bz 0 <text_label>
 
10: 81 fd ff 27 27fffd81 bz 0 <text_label>
 
14: 02 fd ff 27 27fffd02 bnz 0 <text_label>
 
18: 82 fc ff 27 27fffc82 bnz 0 <text_label>
 
1c: 03 fc ff 27 27fffc03 bp 0 <text_label>
 
20: 83 fb ff 27 27fffb83 bp 0 <text_label>
 
24: 04 fb ff 27 27fffb04 bn 0 <text_label>
 
28: 84 fa ff 27 27fffa84 bn 0 <text_label>
 
2c: 05 fa ff 27 27fffa05 bc 0 <text_label>
 
30: 85 f9 ff 27 27fff985 bc 0 <text_label>
 
34: 05 f9 ff 27 27fff905 bc 0 <text_label>
 
38: 86 f8 ff 27 27fff886 bnc 0 <text_label>
 
3c: 06 f8 ff 27 27fff806 bnc 0 <text_label>
 
40: 86 f7 ff 27 27fff786 bnc 0 <text_label>
 
44: 07 f7 ff 27 27fff707 bv 0 <text_label>
 
48: 87 f6 ff 27 27fff687 bv 0 <text_label>
 
4c: 08 f6 ff 27 27fff608 bnv 0 <text_label>
 
50: 88 f5 ff 27 27fff588 bnv 0 <text_label>
 
54: 09 f5 ff 27 27fff509 bgt 0 <text_label>
 
58: 8a f4 ff 27 27fff48a bge 0 <text_label>
 
5c: 0b f4 ff 27 27fff40b blt 0 <text_label>
 
60: 8c f3 ff 27 27fff38c ble 0 <text_label>
 
64: 0d f3 ff 27 27fff30d bhi 0 <text_label>
 
68: 8e f2 ff 27 27fff28e bls 0 <text_label>
 
6c: 0f f2 ff 27 27fff20f bpnz 0 <text_label>
 
70: a0 f1 ff 27 27fff1a0 b.d 0 <text_label>
 
74: 00 f1 ff 27 27fff100 b 0 <text_label>
 
78: c0 f0 ff 27 27fff0c0 b.jd 0 <text_label>
 
7c: 21 f0 ff 27 27fff021 bz.d 0 <text_label>
 
80: 82 ef ff 27 27ffef82 bnz 0 <text_label>
 
84: 46 ef ff 27 27ffef46 bnc.jd 0 <text_label>
 
/extb.s
0,0 → 1,38
# extb test
 
extb r0,r1
extb fp,sp
 
extb r0,0
extb r1,-1
extb 0,r2
extb -1,r3
extb r4,255
extb 255,r5
extb r6,-256
extb -256,r7
 
extb r8,256
extb r9,-257
extb r11,0x42424242
 
extb 255,256
 
extb r0,foo
 
extb.eq r10,r11
extb.ne r12,r13
extb.lt r14,0
extb.gt r15,512
 
extb.f r0,r1
extb.f r2,1
extb.f 0,r4
extb.f r5,512
extb.f 512,512
 
extb.eq.f r0,r1
extb.ne.f r1,0
extb.lt.f 0,r2
extb.le.f r0,512
extb.n.f 512,512
/asr.d
0,0 → 1,51
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 82 00 18 18008200 asr r0,r1
4: 00 02 6e 1b 1b6e0200 asr fp,sp
8: 00 82 1f 18 181f8200 asr r0,0
c: ff 83 3f 18 183f83ff asr r1,-1
10: 00 02 e1 1f 1fe10200 asr 0,r2
14: 00 82 e1 1f 1fe18200 asr 0,r3
18: ff 82 9f 18 189f82ff asr r4,255
1c: 00 82 e2 1f 1fe28200 asr 0,r5
20: 00 83 df 18 18df8300 asr r6,-256
24: 00 82 e3 1f 1fe38200 asr 0,r7
28: 00 02 1f 19 191f0200 asr r8,0x100
2c: 00 01 00 00
30: 00 02 3f 19 193f0200 asr r9,0xffff_feff
34: ff fe ff ff
38: 00 02 7f 19 197f0200 asr r11,0x4242_4242
3c: 42 42 42 42
40: 00 02 ff 1f 1fff0200 asr 0,0x100
44: 00 01 00 00
48: 00 02 1f 18 181f0200 asr r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 82 45 19 19458201 asr.z r10,r11
54: 02 82 86 19 19868202 asr.nz r12,r13
58: 0b 02 df 19 19df020b asr.lt r14,0
5c: 00 00 00 00
60: 09 02 ff 19 19ff0209 asr.gt r15,0x200
64: 00 02 00 00
68: 00 83 00 18 18008300 asr.f r0,r1
6c: 01 82 5e 18 185e8201 asr.f r2,1
70: 00 03 e2 1f 1fe20300 asr.f 0,r4
74: 00 03 bf 18 18bf0300 asr.f r5,0x200
78: 00 02 00 00
7c: 00 03 df 1f 1fdf0300 asr.f 0,0x200
80: 00 02 00 00
84: 01 83 00 18 18008301 asr.z.f r0,r1
88: 02 03 3f 18 183f0302 asr.nz.f r1,0
8c: 00 00 00 00
90: 0b 03 c1 1f 1fc1030b asr.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 03 1f 18 181f030c asr.le.f r0,0x200
9c: 00 02 00 00
a0: 04 03 df 1f 1fdf0304 asr.n.f 0,0x200
a4: 00 02 00 00
/sexw.d
0,0 → 1,51
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 8c 00 18 18008c00 sexw r0,r1
4: 00 0c 6e 1b 1b6e0c00 sexw fp,sp
8: 00 8c 1f 18 181f8c00 sexw r0,0
c: ff 8d 3f 18 183f8dff sexw r1,-1
10: 00 0c e1 1f 1fe10c00 sexw 0,r2
14: 00 8c e1 1f 1fe18c00 sexw 0,r3
18: ff 8c 9f 18 189f8cff sexw r4,255
1c: 00 8c e2 1f 1fe28c00 sexw 0,r5
20: 00 8d df 18 18df8d00 sexw r6,-256
24: 00 8c e3 1f 1fe38c00 sexw 0,r7
28: 00 0c 1f 19 191f0c00 sexw r8,0x100
2c: 00 01 00 00
30: 00 0c 3f 19 193f0c00 sexw r9,0xffff_feff
34: ff fe ff ff
38: 00 0c 7f 19 197f0c00 sexw r11,0x4242_4242
3c: 42 42 42 42
40: 00 0c ff 1f 1fff0c00 sexw 0,0x100
44: 00 01 00 00
48: 00 0c 1f 18 181f0c00 sexw r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 8c 45 19 19458c01 sexw.z r10,r11
54: 02 8c 86 19 19868c02 sexw.nz r12,r13
58: 0b 0c df 19 19df0c0b sexw.lt r14,0
5c: 00 00 00 00
60: 09 0c ff 19 19ff0c09 sexw.gt r15,0x200
64: 00 02 00 00
68: 00 8d 00 18 18008d00 sexw.f r0,r1
6c: 01 8c 5e 18 185e8c01 sexw.f r2,1
70: 00 0d e2 1f 1fe20d00 sexw.f 0,r4
74: 00 0d bf 18 18bf0d00 sexw.f r5,0x200
78: 00 02 00 00
7c: 00 0d df 1f 1fdf0d00 sexw.f 0,0x200
80: 00 02 00 00
84: 01 8d 00 18 18008d01 sexw.z.f r0,r1
88: 02 0d 3f 18 183f0d02 sexw.nz.f r1,0
8c: 00 00 00 00
90: 0b 0d c1 1f 1fc10d0b sexw.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 0d 1f 18 181f0d0c sexw.le.f r0,0x200
9c: 00 02 00 00
a0: 04 0d df 1f 1fdf0d04 sexw.n.f 0,0x200
a4: 00 02 00 00
/warn.s
0,0 → 1,16
; Test ARC specific assembler warnings
;
; { dg-do assemble { target arc-*-* } }
 
b.d foo
mov r0,256 ; { dg-warning "8 byte instruction in delay slot" "8 byte instruction in delay slot" }
 
j.d foo ; { dg-warning "8 byte jump instruction with delay slot" "8 byte jump instruction with delay slot" }
mov r0,r1
 
foo:
.extCoreRegister roscreg,45,r,can_shortcut
.extCoreRegister woscreg,46,w,can_shortcut
.section .text
add r0,woscreg,r1 ; { dg-warning "Error: attempt to read writeonly register" }
add roscreg,r1,r2 ; { dg-warning "Error: attempt to set readonly register" }
/adc.d
0,0 → 1,85
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 84 00 48 48008400 adc r0,r1,r2
4: 00 b8 4d 4b 4b4db800 adc gp,fp,sp
8: 00 3e af 4b 4baf3e00 adc ilink1,ilink2,blink
c: 00 f8 1d 4f 4f1df800 adc r56,r59,lp_count
10: 00 fe 00 48 4800fe00 adc r0,r1,0
14: 00 84 1f 48 481f8400 adc r0,0,r2
18: 00 84 e0 4f 4fe08400 adc 0,r1,r2
1c: ff ff 00 48 4800ffff adc r0,r1,-1
20: ff 85 1f 48 481f85ff adc r0,-1,r2
24: 00 84 e0 4f 4fe08400 adc 0,r1,r2
28: ff fe 00 48 4800feff adc r0,r1,255
2c: ff 84 1f 48 481f84ff adc r0,255,r2
30: 00 84 e0 4f 4fe08400 adc 0,r1,r2
34: 00 ff 00 48 4800ff00 adc r0,r1,-256
38: 00 85 1f 48 481f8500 adc r0,-256,r2
3c: 00 84 e0 4f 4fe08400 adc 0,r1,r2
40: 00 fc 00 48 4800fc00 adc r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 48 481f0400 adc r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 48 481ffcff adc r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 48 481f7eff adc r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 48 4800fc00 adc r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 48 48008400 adc r0,r1,r2
6c: 00 0a 62 48 48620a00 adc r3,r4,r5
70: 01 90 c3 48 48c39001 adc.z r6,r7,r8
74: 01 16 25 49 49251601 adc.z r9,r10,r11
78: 02 9c 86 49 49869c02 adc.nz r12,r13,r14
7c: 02 22 e8 49 49e82202 adc.nz r15,r16,r17
80: 03 a8 49 4a 4a49a803 adc.p r18,r19,r20
84: 03 2e ab 4a 4aab2e03 adc.p r21,r22,r23
88: 04 b4 0c 4b 4b0cb404 adc.n r24,r25,gp
8c: 04 3a 6e 4b 4b6e3a04 adc.n fp,sp,ilink1
90: 05 c0 cf 4b 4bcfc005 adc.c ilink2,blink,r32
94: 05 46 31 4c 4c314605 adc.c r33,r34,r35
98: 05 cc 92 4c 4c92cc05 adc.c r36,r37,r38
9c: 06 52 f4 4c 4cf45206 adc.nc r39,r40,r41
a0: 06 d8 55 4d 4d55d806 adc.nc r42,r43,r44
a4: 06 5e b7 4d 4db75e06 adc.nc r45,r46,r47
a8: 07 e4 18 4e 4e18e407 adc.v r48,r49,r50
ac: 07 6a 1a 4f 4f1a6a07 adc.v r56,r52,r53
b0: 08 f0 1b 4f 4f1bf008 adc.nv r56,r55,r56
b4: 08 76 1d 4f 4f1d7608 adc.nv r56,r58,r59
b8: 09 00 9e 4f 4f9e0009 adc.gt lp_count,lp_count,r0
bc: 0a 7c 00 48 48007c0a adc.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 48 483f020b adc.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 48 487f060d adc.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 4f 4fdf080e adc.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 4f 4fc2fc0f adc.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 48 48008500 adc.f r0,r1,r2
e8: 01 fa 00 48 4800fa01 adc.f r0,r1,1
ec: 01 84 1e 48 481e8401 adc.f r0,1,r2
f0: 00 85 e0 4f 4fe08500 adc.f 0,r1,r2
f4: 00 fd 00 48 4800fd00 adc.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 48 481f0500 adc.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 48 48008501 adc.z.f r0,r1,r2
108: 02 fd 00 48 4800fd02 adc.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 48 481f050b adc.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 4f 4fc08509 adc.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 48 4800fd0c adc.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 48 481f050a adc.ge.f r0,0x200,r2
12c: 00 02 00 00
/alias.d
0,0 → 1,68
#objdump: -dr
#name: @OC@
 
# Test the @OC@ insn.
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
00000000 @IC+0@008200 @OC@ r0,r1
00000004 @IC+3@6e3800 @OC@ fp,sp
00000008 @IC+0@1ffe00 @OC@ r0,0
0000000c @IC+0@3fffff @OC@ r1,-1
00000010 @IC+7@e10400 @OC@ 0,r2
00000014 @IC+7@e187ff @OC@ -1,r3
00000018 @IC+0@9ffeff @OC@ r4,255
0000001c @IC+7@e28aff @OC@ 255,r5
00000020 @IC+0@dfff00 @OC@ r6,-256
00000024 @IC+7@e38f00 @OC@ -256,r7
00000028 @IC+1@1f7c00 @OC@ r8,256
00000030 @IC+1@3f7c00 @OC@ r9,-257
00000038 @IC+7@c51400 @OC@ 511,r10
00000040 @IC+1@7f7c00 @OC@ r11,1111638594
00000048 @IC+7@c61800 @OC@ 305419896,r12
00000050 @IC+7@ff7cff @OC@ 255,256
00000058 @IC+7@dffeff @OC@ 256,255
00000060 @IC+0@1f7c00 @OC@ r0,0
RELOC: 00000064 R_ARC_32 foo
00000068 @IC+0@008200 @OC@ r0,r1
0000006c @IC+0@620800 @OC@ r3,r4
00000070 @IC+0@c38e01 @OC@.eq r6,r7
00000074 @IC+1@251401 @OC@.eq r9,r10
00000078 @IC+1@869a02 @OC@.ne r12,r13
0000007c @IC+1@e82002 @OC@.ne r15,r16
00000080 @IC+2@49a603 @OC@.p r18,r19
00000084 @IC+2@ab2c03 @OC@.p r21,r22
00000088 @IC+3@0cb204 @OC@.n r24,r25
0000008c @IC+3@6e3804 @OC@.n fp,sp
00000090 @IC+3@cfbe05 @OC@.c ilink2,blink
00000094 @IC+4@314405 @OC@.c r33,r34
00000098 @IC+4@92ca05 @OC@.c r36,r37
0000009c @IC+4@f45006 @OC@.nc r39,r40
000000a0 @IC+5@55d606 @OC@.nc r42,r43
000000a4 @IC+5@b75c06 @OC@.nc r45,r46
000000a8 @IC+6@18e207 @OC@.v r48,r49
000000ac @IC+6@7a6807 @OC@.v r51,r52
000000b0 @IC+6@dbee08 @OC@.nv r54,r55
000000b4 @IC+7@3d7408 @OC@.nv r57,r58
000000b8 @IC+7@9e7809 @OC@.gt lp_count,lp_count
000000bc @IC+0@1f7c0a @OC@.ge r0,0
000000c4 @IC+7@c0820b @OC@.lt 1,r1
000000cc @IC+7@df7c0c @OC@.le 2,2
000000d4 @IC+0@61860d @OC@.hi r3,r3
000000d8 @IC+0@82080e @OC@.ls r4,r4
000000dc @IC+0@a28a0f @OC@.pnz r5,r5
000000e0 @IC+0@008300 @OC@.f r0,r1
000000e4 @IC+0@5efa01 @OC@.f r2,1
000000e8 @IC+7@a18601 @OC@.f 1,r3
000000ec @IC+7@a20800 @OC@.f 0,r4
000000f0 @IC+0@bf7d00 @OC@.f r5,512
000000f8 @IC+7@c30d00 @OC@.f 512,r6
00000100 @IC+7@df7d00 @OC@.f 512,512
00000108 @IC+0@008301 @OC@.eq.f r0,r1
0000010c @IC+0@3f7d02 @OC@.ne.f r1,0
00000114 @IC+7@c1050b @OC@.lt.f 0,r2
0000011c @IC+7@c10509 @OC@.gt.f 1,r2
00000124 @IC+0@1f7d0c @OC@.le.f r0,512
0000012c @IC+7@c1050a @OC@.ge.f 512,r2
00000134 @IC+7@df7d04 @OC@.n.f 512,512
/j.d
0,0 → 1,127
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <text_label>:
0: 00 00 1f 38 381f0000 j 0 <text_label>
 
4: 00 00 00 00
4: R_ARC_B26 .text
8: 00 00 1f 38 381f0000 j 0 <text_label>
 
c: 00 00 00 00
c: R_ARC_B26 .text
10: 00 00 1f 38 381f0000 j 0 <text_label>
 
14: 00 00 00 00
14: R_ARC_B26 .text
18: 01 00 1f 38 381f0001 jz 0 <text_label>
 
1c: 00 00 00 00
1c: R_ARC_B26 .text
20: 01 00 1f 38 381f0001 jz 0 <text_label>
 
24: 00 00 00 00
24: R_ARC_B26 .text
28: 02 00 1f 38 381f0002 jnz 0 <text_label>
 
2c: 00 00 00 00
2c: R_ARC_B26 .text
30: 02 00 1f 38 381f0002 jnz 0 <text_label>
 
34: 00 00 00 00
34: R_ARC_B26 .text
38: 03 00 1f 38 381f0003 jp 0 <text_label>
 
3c: 00 00 00 00
3c: R_ARC_B26 .text
40: 03 00 1f 38 381f0003 jp 0 <text_label>
 
44: 00 00 00 00
44: R_ARC_B26 .text
48: 04 00 1f 38 381f0004 jn 0 <text_label>
 
4c: 00 00 00 00
4c: R_ARC_B26 .text
50: 04 00 1f 38 381f0004 jn 0 <text_label>
 
54: 00 00 00 00
54: R_ARC_B26 .text
58: 05 00 1f 38 381f0005 jc 0 <text_label>
 
5c: 00 00 00 00
5c: R_ARC_B26 .text
60: 05 00 1f 38 381f0005 jc 0 <text_label>
 
64: 00 00 00 00
64: R_ARC_B26 .text
68: 05 00 1f 38 381f0005 jc 0 <text_label>
 
6c: 00 00 00 00
6c: R_ARC_B26 .text
70: 06 00 1f 38 381f0006 jnc 0 <text_label>
 
74: 00 00 00 00
74: R_ARC_B26 .text
78: 06 00 1f 38 381f0006 jnc 0 <text_label>
 
7c: 00 00 00 00
7c: R_ARC_B26 .text
80: 06 00 1f 38 381f0006 jnc 0 <text_label>
 
84: 00 00 00 00
84: R_ARC_B26 .text
88: 07 00 1f 38 381f0007 jv 0 <text_label>
 
8c: 00 00 00 00
8c: R_ARC_B26 .text
90: 07 00 1f 38 381f0007 jv 0 <text_label>
 
94: 00 00 00 00
94: R_ARC_B26 .text
98: 08 00 1f 38 381f0008 jnv 0 <text_label>
 
9c: 00 00 00 00
9c: R_ARC_B26 .text
a0: 08 00 1f 38 381f0008 jnv 0 <text_label>
 
a4: 00 00 00 00
a4: R_ARC_B26 .text
a8: 09 00 1f 38 381f0009 jgt 0 <text_label>
 
ac: 00 00 00 00
ac: R_ARC_B26 .text
b0: 0a 00 1f 38 381f000a jge 0 <text_label>
 
b4: 00 00 00 00
b4: R_ARC_B26 .text
b8: 0b 00 1f 38 381f000b jlt 0 <text_label>
 
bc: 00 00 00 00
bc: R_ARC_B26 .text
c0: 0c 00 1f 38 381f000c jle 0 <text_label>
 
c4: 00 00 00 00
c4: R_ARC_B26 .text
c8: 0d 00 1f 38 381f000d jhi 0 <text_label>
 
cc: 00 00 00 00
cc: R_ARC_B26 .text
d0: 0e 00 1f 38 381f000e jls 0 <text_label>
 
d4: 00 00 00 00
d4: R_ARC_B26 .text
d8: 0f 00 1f 38 381f000f jpnz 0 <text_label>
 
dc: 00 00 00 00
dc: R_ARC_B26 .text
e0: 00 00 1f 38 381f0000 j 0 <text_label>
 
e4: 00 00 00 00
e4: R_ARC_B26 external_text_label
e8: 00 00 1f 38 381f0000 j 0 <text_label>
 
ec: 00 00 00 00
/insn3.d
0,0 → 1,44
#objdump: -dr
#name: @OC@
 
# Test the @OC@ insn.
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
00000000 1800@I3+80@00 @OC@ r0,r1
00000004 1b6e@I3+00@00 @OC@ fp,sp
00000008 181f@I3+80@00 @OC@ r0,0
0000000c 183f@I3+81@ff @OC@ r1,-1
00000010 1fe1@I3+00@00 @OC@ 0,r2
00000014 1fe1@I3+81@ff @OC@ -1,r3
00000018 189f@I3+80@ff @OC@ r4,255
0000001c 1fe2@I3+80@ff @OC@ 255,r5
00000020 18df@I3+81@00 @OC@ r6,-256
00000024 1fe3@I3+81@00 @OC@ -256,r7
00000028 191f@I3+00@00 @OC@ r8,256
00000030 193f@I3+00@00 @OC@ r9,-257
00000038 1fc5@I3+00@00 @OC@ 511,r10
00000040 197f@I3+00@00 @OC@ r11,1111638594
00000048 1fc6@I3+00@00 @OC@ 305419896,r12
00000050 1fff@I3+00@ff @OC@ 255,256
00000058 1fdf@I3+80@ff @OC@ 256,255
00000060 181f@I3+00@00 @OC@ r0,0
RELOC: 00000064 R_ARC_32 foo
00000068 1945@I3+80@01 @OC@.eq r10,r11
0000006c 1986@I3+80@02 @OC@.ne r12,r13
00000070 19df@I3+00@0b @OC@.lt r14,0
00000078 19ff@I3+00@09 @OC@.gt r15,512
00000080 1800@I3+81@00 @OC@.f r0,r1
00000084 185e@I3+80@01 @OC@.f r2,1
00000088 1fa2@I3+00@00 @OC@.f 0,r4
0000008c 18bf@I3+01@00 @OC@.f r5,512
00000094 1fc3@I3+01@00 @OC@.f 512,r6
0000009c 1fdf@I3+01@00 @OC@.f 512,512
000000a4 1800@I3+81@01 @OC@.eq.f r0,r1
000000a8 183f@I3+01@02 @OC@.ne.f r1,0
000000b0 1fc1@I3+01@0b @OC@.lt.f 0,r2
000000b8 1fc1@I3+01@09 @OC@.gt.f 1,r2
000000c0 181f@I3+01@0c @OC@.le.f r0,512
000000c8 1fc1@I3+01@0a @OC@.ge.f 512,r2
000000d0 1fdf@I3+01@04 @OC@.n.f 512,512
/lp.s
0,0 → 1,40
# lp test
text_label:
 
lp text_label
lpal text_label
lpra text_label
lpeq text_label
lpz text_label
lpne text_label
lpnz text_label
lppl text_label
lpp text_label
lpmi text_label
lpn text_label
lpcs text_label
lpc text_label
lplo text_label
lpcc text_label
lpnc text_label
lphs text_label
lpvs text_label
lpv text_label
lpvc text_label
lpnv text_label
lpgt text_label
lpge text_label
lplt text_label
lple text_label
lphi text_label
lpls text_label
lppnz text_label
 
lp.d text_label
lp.nd text_label
lp.jd text_label
 
lpeq.d text_label
lpne.nd text_label
lpcc.jd text_label
/nop.d
0,0 → 1,9
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: ff ff ff 7f 7fffffff nop
/branch.d
0,0 → 1,45
#objdump: -dr
#name: @OC@
 
# Test the @OC@ insn.
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
00000000 <text_label> @IC+7@ffff80 @OC@ 00000000 <text_label>
00000004 <text_label\+4> @IC+7@ffff00 @OC@ 00000000 <text_label>
00000008 <text_label\+8> @IC+7@fffe80 @OC@ 00000000 <text_label>
0000000c <text_label\+c> @IC+7@fffe01 @OC@eq 00000000 <text_label>
00000010 <text_label\+10> @IC+7@fffd81 @OC@eq 00000000 <text_label>
00000014 <text_label\+14> @IC+7@fffd02 @OC@ne 00000000 <text_label>
00000018 <text_label\+18> @IC+7@fffc82 @OC@ne 00000000 <text_label>
0000001c <text_label\+1c> @IC+7@fffc03 @OC@p 00000000 <text_label>
00000020 <text_label\+20> @IC+7@fffb83 @OC@p 00000000 <text_label>
00000024 <text_label\+24> @IC+7@fffb04 @OC@n 00000000 <text_label>
00000028 <text_label\+28> @IC+7@fffa84 @OC@n 00000000 <text_label>
0000002c <text_label\+2c> @IC+7@fffa05 @OC@c 00000000 <text_label>
00000030 <text_label\+30> @IC+7@fff985 @OC@c 00000000 <text_label>
00000034 <text_label\+34> @IC+7@fff905 @OC@c 00000000 <text_label>
00000038 <text_label\+38> @IC+7@fff886 @OC@nc 00000000 <text_label>
0000003c <text_label\+3c> @IC+7@fff806 @OC@nc 00000000 <text_label>
00000040 <text_label\+40> @IC+7@fff786 @OC@nc 00000000 <text_label>
00000044 <text_label\+44> @IC+7@fff707 @OC@v 00000000 <text_label>
00000048 <text_label\+48> @IC+7@fff687 @OC@v 00000000 <text_label>
0000004c <text_label\+4c> @IC+7@fff608 @OC@nv 00000000 <text_label>
00000050 <text_label\+50> @IC+7@fff588 @OC@nv 00000000 <text_label>
00000054 <text_label\+54> @IC+7@fff509 @OC@gt 00000000 <text_label>
00000058 <text_label\+58> @IC+7@fff48a @OC@ge 00000000 <text_label>
0000005c <text_label\+5c> @IC+7@fff40b @OC@lt 00000000 <text_label>
00000060 <text_label\+60> @IC+7@fff38c @OC@le 00000000 <text_label>
00000064 <text_label\+64> @IC+7@fff30d @OC@hi 00000000 <text_label>
00000068 <text_label\+68> @IC+7@fff28e @OC@ls 00000000 <text_label>
0000006c <text_label\+6c> @IC+7@fff20f @OC@pnz 00000000 <text_label>
00000070 <text_label\+70> @IC+7@ffff80 @OC@ 00000070 <text_label\+70>
RELOC: 00000070 R_ARC_B22_PCREL external_text_label
00000074 <text_label\+74> @IC+0@000000 @OC@ 00000078 <text_label\+78>
00000078 <text_label\+78> @IC+7@fff0a0 @OC@.d 00000000 <text_label>
0000007c <text_label\+7c> @IC+7@fff000 @OC@ 00000000 <text_label>
00000080 <text_label\+80> @IC+7@ffefc0 @OC@.jd 00000000 <text_label>
00000084 <text_label\+84> @IC+7@ffef21 @OC@eq.d 00000000 <text_label>
00000088 <text_label\+88> @IC+7@ffee82 @OC@ne 00000000 <text_label>
0000008c <text_label\+8c> @IC+7@ffee46 @OC@nc.jd 00000000 <text_label>
/asl.s
0,0 → 1,58
# asl test
 
asl r0,r1
asl fp,sp
 
asl r0,0
asl r1,-1
asl 0,r2
asl -1,r3
asl r4,255
asl 255,r5
asl r6,-256
asl -256,r7
 
asl r8,256
asl r9,-257
asl r11,0x42424242
 
asl 255,256
 
asl r0,foo
 
asl.al r0,r1
asl.ra r3,r4
asl.eq r6,r7
asl.z r9,r10
asl.ne r12,r13
asl.nz r15,r16
asl.pl r18,r19
asl.p r21,r22
asl.mi r24,r25
asl.n r27,r28
asl.cs r30,r31
asl.c r33,r34
asl.lo r36,r37
asl.cc r39,r40
asl.nc r42,r43
asl.hs r45,r46
asl.vs r48,r49
asl.v r49,r50
asl.vc r49,r55
asl.nv r49,r58
asl.gt r60,r60
asl.ge r0,0
asl.le 2,2
asl.hi r3,r3
asl.ls r4,r4
asl.pnz r5,r5
 
asl.f r0,r1
asl.f r2,1
asl.f 1,r3
asl.f 0,r4
asl.f r5,512
asl.f 512,512
 
asl.eq.f r0,r1
asl.ne.f r1,0
/b.s
0,0 → 1,40
# b test
text_label:
 
b text_label
bal text_label
bra text_label
beq text_label
bz text_label
bne text_label
bnz text_label
bpl text_label
bp text_label
bmi text_label
bn text_label
bcs text_label
bc text_label
blo text_label
bcc text_label
bnc text_label
bhs text_label
bvs text_label
bv text_label
bvc text_label
bnv text_label
bgt text_label
bge text_label
blt text_label
ble text_label
bhi text_label
bls text_label
bpnz text_label
 
b.d text_label
b.nd text_label
b.jd text_label
 
beq.d text_label
bne.nd text_label
bcc.jd text_label
/lsr.d
0,0 → 1,51
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 84 00 18 18008400 lsr r0,r1
4: 00 04 6e 1b 1b6e0400 lsr fp,sp
8: 00 84 1f 18 181f8400 lsr r0,0
c: ff 85 3f 18 183f85ff lsr r1,-1
10: 00 04 e1 1f 1fe10400 lsr 0,r2
14: 00 84 e1 1f 1fe18400 lsr 0,r3
18: ff 84 9f 18 189f84ff lsr r4,255
1c: 00 84 e2 1f 1fe28400 lsr 0,r5
20: 00 85 df 18 18df8500 lsr r6,-256
24: 00 84 e3 1f 1fe38400 lsr 0,r7
28: 00 04 1f 19 191f0400 lsr r8,0x100
2c: 00 01 00 00
30: 00 04 3f 19 193f0400 lsr r9,0xffff_feff
34: ff fe ff ff
38: 00 04 7f 19 197f0400 lsr r11,0x4242_4242
3c: 42 42 42 42
40: 00 04 ff 1f 1fff0400 lsr 0,0x100
44: 00 01 00 00
48: 00 04 1f 18 181f0400 lsr r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 84 45 19 19458401 lsr.z r10,r11
54: 02 84 86 19 19868402 lsr.nz r12,r13
58: 0b 04 df 19 19df040b lsr.lt r14,0
5c: 00 00 00 00
60: 09 04 ff 19 19ff0409 lsr.gt r15,0x200
64: 00 02 00 00
68: 00 85 00 18 18008500 lsr.f r0,r1
6c: 01 84 5e 18 185e8401 lsr.f r2,1
70: 00 05 e2 1f 1fe20500 lsr.f 0,r4
74: 00 05 bf 18 18bf0500 lsr.f r5,0x200
78: 00 02 00 00
7c: 00 05 df 1f 1fdf0500 lsr.f 0,0x200
80: 00 02 00 00
84: 01 85 00 18 18008501 lsr.z.f r0,r1
88: 02 05 3f 18 183f0502 lsr.nz.f r1,0
8c: 00 00 00 00
90: 0b 05 c1 1f 1fc1050b lsr.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 05 1f 18 181f050c lsr.le.f r0,0x200
9c: 00 02 00 00
a0: 04 05 df 1f 1fdf0504 lsr.n.f 0,0x200
a4: 00 02 00 00
/mov.d
0,0 → 1,68
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 82 00 60 60008200 mov r0,r1
4: 00 38 6e 63 636e3800 mov fp,sp
8: 00 fe 1f 60 601ffe00 mov r0,0
c: ff ff 3f 60 603fffff mov r1,-1
10: 00 04 e1 67 67e10400 mov 0,r2
14: 00 86 e1 67 67e18600 mov 0,r3
18: ff fe 9f 60 609ffeff mov r4,255
1c: 00 8a e2 67 67e28a00 mov 0,r5
20: 00 ff df 60 60dfff00 mov r6,-256
24: 00 8e e3 67 67e38e00 mov 0,r7
28: 00 7c 1f 61 611f7c00 mov r8,0x100
2c: 00 01 00 00
30: 00 7c 3f 61 613f7c00 mov r9,0xffff_feff
34: ff fe ff ff
38: 00 7c 7f 61 617f7c00 mov r11,0x4242_4242
3c: 42 42 42 42
40: 00 7c ff 67 67ff7c00 mov 0,0x100
44: 00 01 00 00
48: 00 7c 1f 60 601f7c00 mov r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 00 82 00 60 60008200 mov r0,r1
54: 00 08 62 60 60620800 mov r3,r4
58: 01 8e c3 60 60c38e01 mov.z r6,r7
5c: 01 14 25 61 61251401 mov.z r9,r10
60: 02 9a 86 61 61869a02 mov.nz r12,r13
64: 02 20 e8 61 61e82002 mov.nz r15,r16
68: 03 a6 49 62 6249a603 mov.p r18,r19
6c: 03 2c ab 62 62ab2c03 mov.p r21,r22
70: 04 b2 0c 63 630cb204 mov.n r24,r25
74: 04 38 6e 63 636e3804 mov.n fp,sp
78: 05 be cf 63 63cfbe05 mov.c ilink2,blink
7c: 05 44 31 64 64314405 mov.c r33,r34
80: 05 ca 92 64 6492ca05 mov.c r36,r37
84: 06 50 f4 64 64f45006 mov.nc r39,r40
88: 06 d6 55 65 6555d606 mov.nc r42,r43
8c: 06 5c b7 65 65b75c06 mov.nc r45,r46
90: 07 e2 18 66 6618e207 mov.v r48,r49
94: 07 64 39 66 66396407 mov.v r49,r50
98: 08 ee 3b 66 663bee08 mov.nv r49,r55
9c: 08 74 3d 66 663d7408 mov.nv r49,r58
a0: 09 78 9e 67 679e7809 mov.gt lp_count,lp_count
a4: 0a 7c 1f 60 601f7c0a mov.ge r0,0
a8: 00 00 00 00
ac: 0c 7c df 67 67df7c0c mov.le 0,2
b0: 02 00 00 00
b4: 0d 86 61 60 6061860d mov.hi r3,r3
b8: 0e 08 82 60 6082080e mov.ls r4,r4
bc: 0f 8a a2 60 60a28a0f mov.pnz r5,r5
c0: 00 83 00 60 60008300 mov.f r0,r1
c4: 01 fa 5e 60 605efa01 mov.f r2,1
c8: 00 87 e1 67 67e18700 mov.f 0,r3
cc: 00 09 e2 67 67e20900 mov.f 0,r4
d0: 00 7d bf 60 60bf7d00 mov.f r5,0x200
d4: 00 02 00 00
d8: 00 7d df 67 67df7d00 mov.f 0,0x200
dc: 00 02 00 00
e0: 01 83 00 60 60008301 mov.z.f r0,r1
e4: 02 7d 3f 60 603f7d02 mov.nz.f r1,0
e8: 00 00 00 00
/and.d
0,0 → 1,85
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 84 00 60 60008400 and r0,r1,r2
4: 00 b8 4d 63 634db800 and gp,fp,sp
8: 00 3e af 63 63af3e00 and ilink1,ilink2,blink
c: 00 f8 1d 67 671df800 and r56,r59,lp_count
10: 00 fe 00 60 6000fe00 and r0,r1,0
14: 00 84 1f 60 601f8400 and r0,0,r2
18: 00 84 e0 67 67e08400 and 0,r1,r2
1c: ff ff 00 60 6000ffff and r0,r1,-1
20: ff 85 1f 60 601f85ff and r0,-1,r2
24: 00 84 e0 67 67e08400 and 0,r1,r2
28: ff fe 00 60 6000feff and r0,r1,255
2c: ff 84 1f 60 601f84ff and r0,255,r2
30: 00 84 e0 67 67e08400 and 0,r1,r2
34: 00 ff 00 60 6000ff00 and r0,r1,-256
38: 00 85 1f 60 601f8500 and r0,-256,r2
3c: 00 84 e0 67 67e08400 and 0,r1,r2
40: 00 fc 00 60 6000fc00 and r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 60 601f0400 and r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 60 601ffcff and r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 60 601f7eff and r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 60 6000fc00 and r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 60 60008400 and r0,r1,r2
6c: 00 0a 62 60 60620a00 and r3,r4,r5
70: 01 90 c3 60 60c39001 and.z r6,r7,r8
74: 01 16 25 61 61251601 and.z r9,r10,r11
78: 02 9c 86 61 61869c02 and.nz r12,r13,r14
7c: 02 22 e8 61 61e82202 and.nz r15,r16,r17
80: 03 a8 49 62 6249a803 and.p r18,r19,r20
84: 03 2e ab 62 62ab2e03 and.p r21,r22,r23
88: 04 b4 0c 63 630cb404 and.n r24,r25,gp
8c: 04 3a 6e 63 636e3a04 and.n fp,sp,ilink1
90: 05 c0 cf 63 63cfc005 and.c ilink2,blink,r32
94: 05 46 31 64 64314605 and.c r33,r34,r35
98: 05 cc 92 64 6492cc05 and.c r36,r37,r38
9c: 06 52 f4 64 64f45206 and.nc r39,r40,r41
a0: 06 d8 55 65 6555d806 and.nc r42,r43,r44
a4: 06 5e b7 65 65b75e06 and.nc r45,r46,r47
a8: 07 e4 18 66 6618e407 and.v r48,r49,r50
ac: 07 6a 1a 67 671a6a07 and.v r56,r52,r53
b0: 08 f0 1b 67 671bf008 and.nv r56,r55,r56
b4: 08 76 1d 67 671d7608 and.nv r56,r58,r59
b8: 09 00 9e 67 679e0009 and.gt lp_count,lp_count,r0
bc: 0a 7c 00 60 60007c0a and.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 60 603f020b and.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 60 607f060d and.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 67 67df080e and.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 67 67c2fc0f and.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 60 60008500 and.f r0,r1,r2
e8: 01 fa 00 60 6000fa01 and.f r0,r1,1
ec: 01 84 1e 60 601e8401 and.f r0,1,r2
f0: 00 85 e0 67 67e08500 and.f 0,r1,r2
f4: 00 fd 00 60 6000fd00 and.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 60 601f0500 and.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 60 60008501 and.z.f r0,r1,r2
108: 02 fd 00 60 6000fd02 and.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 60 601f050b and.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 67 67c08509 and.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 60 6000fd0c and.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 60 601f050a and.ge.f r0,0x200,r2
12c: 00 02 00 00
/ror.d
0,0 → 1,51
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 86 00 18 18008600 ror r0,r1
4: 00 06 6e 1b 1b6e0600 ror fp,sp
8: 00 86 1f 18 181f8600 ror r0,0
c: ff 87 3f 18 183f87ff ror r1,-1
10: 00 06 e1 1f 1fe10600 ror 0,r2
14: 00 86 e1 1f 1fe18600 ror 0,r3
18: ff 86 9f 18 189f86ff ror r4,255
1c: 00 86 e2 1f 1fe28600 ror 0,r5
20: 00 87 df 18 18df8700 ror r6,-256
24: 00 86 e3 1f 1fe38600 ror 0,r7
28: 00 06 1f 19 191f0600 ror r8,0x100
2c: 00 01 00 00
30: 00 06 3f 19 193f0600 ror r9,0xffff_feff
34: ff fe ff ff
38: 00 06 7f 19 197f0600 ror r11,0x4242_4242
3c: 42 42 42 42
40: 00 06 ff 1f 1fff0600 ror 0,0x100
44: 00 01 00 00
48: 00 06 1f 18 181f0600 ror r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 86 45 19 19458601 ror.z r10,r11
54: 02 86 86 19 19868602 ror.nz r12,r13
58: 0b 06 df 19 19df060b ror.lt r14,0
5c: 00 00 00 00
60: 09 06 ff 19 19ff0609 ror.gt r15,0x200
64: 00 02 00 00
68: 00 87 00 18 18008700 ror.f r0,r1
6c: 01 86 5e 18 185e8601 ror.f r2,1
70: 00 07 e2 1f 1fe20700 ror.f 0,r4
74: 00 07 bf 18 18bf0700 ror.f r5,0x200
78: 00 02 00 00
7c: 00 07 df 1f 1fdf0700 ror.f 0,0x200
80: 00 02 00 00
84: 01 87 00 18 18008701 ror.z.f r0,r1
88: 02 07 3f 18 183f0702 ror.nz.f r1,0
8c: 00 00 00 00
90: 0b 07 c1 1f 1fc1070b ror.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 07 1f 18 181f070c ror.le.f r0,0x200
9c: 00 02 00 00
a0: 04 07 df 1f 1fdf0704 ror.n.f 0,0x200
a4: 00 02 00 00
/asr.s
0,0 → 1,38
# asr test
 
asr r0,r1
asr fp,sp
 
asr r0,0
asr r1,-1
asr 0,r2
asr -1,r3
asr r4,255
asr 255,r5
asr r6,-256
asr -256,r7
 
asr r8,256
asr r9,-257
asr r11,0x42424242
 
asr 255,256
 
asr r0,foo
 
asr.eq r10,r11
asr.ne r12,r13
asr.lt r14,0
asr.gt r15,512
 
asr.f r0,r1
asr.f r2,1
asr.f 0,r4
asr.f r5,512
asr.f 512,512
 
asr.eq.f r0,r1
asr.ne.f r1,0
asr.lt.f 0,r2
asr.le.f r0,512
asr.n.f 512,512
/sexw.s
0,0 → 1,38
# sexw test
 
sexw r0,r1
sexw fp,sp
 
sexw r0,0
sexw r1,-1
sexw 0,r2
sexw -1,r3
sexw r4,255
sexw 255,r5
sexw r6,-256
sexw -256,r7
 
sexw r8,256
sexw r9,-257
sexw r11,0x42424242
 
sexw 255,256
 
sexw r0,foo
 
sexw.eq r10,r11
sexw.ne r12,r13
sexw.lt r14,0
sexw.gt r15,512
 
sexw.f r0,r1
sexw.f r2,1
sexw.f 0,r4
sexw.f r5,512
sexw.f 512,512
 
sexw.eq.f r0,r1
sexw.ne.f r1,0
sexw.lt.f 0,r2
sexw.le.f r0,512
sexw.n.f 512,512
/adc.s
0,0 → 1,68
# adc test
 
adc r0,r1,r2
adc r26,fp,sp
adc ilink1,ilink2,blink
adc r56,r59,lp_count
 
adc r0,r1,0
adc r0,0,r2
adc 0,r1,r2
adc r0,r1,-1
adc r0,-1,r2
adc -1,r1,r2
adc r0,r1,255
adc r0,255,r2
adc 255,r1,r2
adc r0,r1,-256
adc r0,-256,r2
adc -256,r1,r2
 
adc r0,r1,256
adc r0,-257,r2
 
adc r0,255,256
adc r0,256,255
 
adc r0,r1,foo
 
adc.al r0,r1,r2
adc.ra r3,r4,r5
adc.eq r6,r7,r8
adc.z r9,r10,r11
adc.ne r12,r13,r14
adc.nz r15,r16,r17
adc.pl r18,r19,r20
adc.p r21,r22,r23
adc.mi r24,r25,r26
adc.n r27,r28,r29
adc.cs r30,r31,r32
adc.c r33,r34,r35
adc.lo r36,r37,r38
adc.cc r39,r40,r41
adc.nc r42,r43,r44
adc.hs r45,r46,r47
adc.vs r48,r49,r50
adc.v r56,r52,r53
adc.vc r56,r55,r56
adc.nv r56,r58,r59
adc.gt r60,r60,r0
adc.ge r0,r0,0
adc.lt r1,1,r1
adc.hi r3,3,r3
adc.ls 4,4,r4
adc.pnz 5,r5,5
 
adc.f r0,r1,r2
adc.f r0,r1,1
adc.f r0,1,r2
adc.f 0,r1,r2
adc.f r0,r1,512
adc.f r0,512,r2
 
adc.eq.f r0,r1,r2
adc.ne.f r0,r1,0
adc.lt.f r0,0,r2
adc.gt.f 0,r1,r2
adc.le.f r0,r1,512
adc.ge.f r0,512,r2
/xor.d
0,0 → 1,85
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 84 00 78 78008400 xor r0,r1,r2
4: 00 b8 4d 7b 7b4db800 xor gp,fp,sp
8: 00 3e af 7b 7baf3e00 xor ilink1,ilink2,blink
c: 00 f8 1d 7f 7f1df800 xor r56,r59,lp_count
10: 00 fe 00 78 7800fe00 xor r0,r1,0
14: 00 84 1f 78 781f8400 xor r0,0,r2
18: 00 84 e0 7f 7fe08400 xor 0,r1,r2
1c: ff ff 00 78 7800ffff xor r0,r1,-1
20: ff 85 1f 78 781f85ff xor r0,-1,r2
24: 00 84 e0 7f 7fe08400 xor 0,r1,r2
28: ff fe 00 78 7800feff xor r0,r1,255
2c: ff 84 1f 78 781f84ff xor r0,255,r2
30: 00 84 e0 7f 7fe08400 xor 0,r1,r2
34: 00 ff 00 78 7800ff00 xor r0,r1,-256
38: 00 85 1f 78 781f8500 xor r0,-256,r2
3c: 00 84 e0 7f 7fe08400 xor 0,r1,r2
40: 00 fc 00 78 7800fc00 xor r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 78 781f0400 xor r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 78 781ffcff xor r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 78 781f7eff xor r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 78 7800fc00 xor r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 78 78008400 xor r0,r1,r2
6c: 00 0a 62 78 78620a00 xor r3,r4,r5
70: 01 90 c3 78 78c39001 xor.z r6,r7,r8
74: 01 16 25 79 79251601 xor.z r9,r10,r11
78: 02 9c 86 79 79869c02 xor.nz r12,r13,r14
7c: 02 22 e8 79 79e82202 xor.nz r15,r16,r17
80: 03 a8 49 7a 7a49a803 xor.p r18,r19,r20
84: 03 2e ab 7a 7aab2e03 xor.p r21,r22,r23
88: 04 b4 0c 7b 7b0cb404 xor.n r24,r25,gp
8c: 04 3a 6e 7b 7b6e3a04 xor.n fp,sp,ilink1
90: 05 c0 cf 7b 7bcfc005 xor.c ilink2,blink,r32
94: 05 46 31 7c 7c314605 xor.c r33,r34,r35
98: 05 cc 92 7c 7c92cc05 xor.c r36,r37,r38
9c: 06 52 f4 7c 7cf45206 xor.nc r39,r40,r41
a0: 06 d8 55 7d 7d55d806 xor.nc r42,r43,r44
a4: 06 5e b7 7d 7db75e06 xor.nc r45,r46,r47
a8: 07 e4 18 7e 7e18e407 xor.v r48,r49,r50
ac: 07 6a 1a 7f 7f1a6a07 xor.v r56,r52,r53
b0: 08 f0 1b 7f 7f1bf008 xor.nv r56,r55,r56
b4: 08 76 1d 7f 7f1d7608 xor.nv r56,r58,r59
b8: 09 00 9e 7f 7f9e0009 xor.gt lp_count,lp_count,r0
bc: 0a 7c 00 78 78007c0a xor.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 78 783f020b xor.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 78 787f060d xor.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 7f 7fdf080e xor.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 7f 7fc2fc0f xor.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 78 78008500 xor.f r0,r1,r2
e8: 01 fa 00 78 7800fa01 xor.f r0,r1,1
ec: 01 84 1e 78 781e8401 xor.f r0,1,r2
f0: 00 85 e0 7f 7fe08500 xor.f 0,r1,r2
f4: 00 fd 00 78 7800fd00 xor.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 78 781f0500 xor.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 78 78008501 xor.z.f r0,r1,r2
108: 02 fd 00 78 7800fd02 xor.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 78 781f050b xor.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 7f 7fc08509 xor.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 78 7800fd0c xor.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 78 781f050a xor.ge.f r0,0x200,r2
12c: 00 02 00 00
/alias.s
0,0 → 1,76
# @OC@ test
 
# reg,reg
@OC@ r0,r1
@OC@ fp,sp
 
# shimm values
@OC@ r0,0
@OC@ r1,-1
@OC@ 0,r2
@OC@ -1,r3
@OC@ r4,255
@OC@ 255,r5
@OC@ r6,-256
@OC@ -256,r7
 
# limm values
@OC@ r8,256
@OC@ r9,-257
@OC@ 511,r10
@OC@ r11,0x42424242
@OC@ 0x12345678,r12
 
# shimm and limm
@OC@ 255,256
@OC@ 256,255
 
# symbols
@OC@ r0,foo
 
# conditional execution
@OC@.al r0,r1
@OC@.ra r3,r4
@OC@.eq r6,r7
@OC@.z r9,r10
@OC@.ne r12,r13
@OC@.nz r15,r16
@OC@.pl r18,r19
@OC@.p r21,r22
@OC@.mi r24,r25
@OC@.n r27,r28
@OC@.cs r30,r31
@OC@.c r33,r34
@OC@.lo r36,r37
@OC@.cc r39,r40
@OC@.nc r42,r43
@OC@.hs r45,r46
@OC@.vs r48,r49
@OC@.v r51,r52
@OC@.vc r54,r55
@OC@.nv r57,r58
@OC@.gt r60,r60
@OC@.ge r0,0
@OC@.lt 1,r1
@OC@.le 2,2
@OC@.hi r3,r3
@OC@.ls r4,r4
@OC@.pnz r5,r5
 
# flag setting
@OC@.f r0,r1
@OC@.f r2,1
@OC@.f 1,r3
@OC@.f 0,r4
@OC@.f r5,512
@OC@.f 512,r6
@OC@.f 512,512
 
# conditional execution + flag setting
@OC@.eq.f r0,r1
@OC@.ne.f r1,0
@OC@.lt.f 0,r2
@OC@.gt.f 1,r2
@OC@.le.f r0,512
@OC@.ge.f 512,r2
@OC@.n.f 512,512
/j.s
0,0 → 1,36
# j test
text_label:
 
j text_label
jal text_label
jra text_label
jeq text_label
jz text_label
jne text_label
jnz text_label
jpl text_label
jp text_label
jmi text_label
jn text_label
jcs text_label
jc text_label
jlo text_label
jcc text_label
jnc text_label
jhs text_label
jvs text_label
jv text_label
jvc text_label
jnv text_label
jgt text_label
jge text_label
jlt text_label
jle text_label
jhi text_label
jls text_label
jpnz text_label
 
j external_text_label
 
j 0
/flag.d
0,0 → 1,38
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 00 a0 1f 1fa00000 flag r0
4: 01 80 bf 1f 1fbf8001 flag 1
8: 02 80 bf 1f 1fbf8002 flag 2
c: 04 80 bf 1f 1fbf8004 flag 4
10: 08 80 bf 1f 1fbf8008 flag 8
14: 10 80 bf 1f 1fbf8010 flag 16
18: 20 80 bf 1f 1fbf8020 flag 32
1c: 40 80 bf 1f 1fbf8040 flag 64
20: 80 80 bf 1f 1fbf8080 flag 128
24: 00 00 bf 1f 1fbf0000 flag 0x8000_0001
28: 01 00 00 80
2c: 0b 00 a0 1f 1fa0000b flag.lt r0
30: 09 00 bf 1f 1fbf0009 flag.gt 1
34: 01 00 00 00
38: 09 00 bf 1f 1fbf0009 flag.gt 2
3c: 02 00 00 00
40: 09 00 bf 1f 1fbf0009 flag.gt 4
44: 04 00 00 00
48: 09 00 bf 1f 1fbf0009 flag.gt 8
4c: 08 00 00 00
50: 09 00 bf 1f 1fbf0009 flag.gt 16
54: 10 00 00 00
58: 09 00 bf 1f 1fbf0009 flag.gt 32
5c: 20 00 00 00
60: 09 00 bf 1f 1fbf0009 flag.gt 64
64: 40 00 00 00
68: 09 00 bf 1f 1fbf0009 flag.gt 128
6c: 80 00 00 00
70: 0a 00 bf 1f 1fbf000a flag.ge 0x8000_0001
74: 01 00 00 80
/insn3.s
0,0 → 1,52
# Insn 3 @OC@ test
 
# reg,reg
@OC@ r0,r1
@OC@ fp,sp
 
# shimm values
@OC@ r0,0
@OC@ r1,-1
@OC@ 0,r2
@OC@ -1,r3
@OC@ r4,255
@OC@ 255,r5
@OC@ r6,-256
@OC@ -256,r7
 
# limm values
@OC@ r8,256
@OC@ r9,-257
@OC@ 511,r10
@OC@ r11,0x42424242
@OC@ 0x12345678,r12
 
# shimm and limm
@OC@ 255,256
@OC@ 256,255
 
# symbols
@OC@ r0,foo
 
# conditional execution
@OC@.eq r10,r11
@OC@.ne r12,r13
@OC@.lt r14,0
@OC@.gt r15,512
 
# flag setting
@OC@.f r0,r1
@OC@.f r2,1
@OC@.f 0,r4
@OC@.f r5,512
@OC@.f 512,r6
@OC@.f 512,512
 
# conditional execution + flag setting
@OC@.eq.f r0,r1
@OC@.ne.f r1,0
@OC@.lt.f 0,r2
@OC@.gt.f 1,r2
@OC@.le.f r0,512
@OC@.ge.f 512,r2
@OC@.n.f 512,512
/nop.s
0,0 → 1,3
# nop test
 
nop
/branch.s
0,0 → 1,47
# @OC@ test
text_label:
 
# Condition tests
@OC@ text_label
@OC@al text_label
@OC@ra text_label
@OC@eq text_label
@OC@z text_label
@OC@ne text_label
@OC@nz text_label
@OC@pl text_label
@OC@p text_label
@OC@mi text_label
@OC@n text_label
@OC@cs text_label
@OC@c text_label
@OC@lo text_label
@OC@cc text_label
@OC@nc text_label
@OC@hs text_label
@OC@vs text_label
@OC@v text_label
@OC@vc text_label
@OC@nv text_label
@OC@gt text_label
@OC@ge text_label
@OC@lt text_label
@OC@le text_label
@OC@hi text_label
@OC@ls text_label
@OC@pnz text_label
 
@OC@ external_text_label
 
@OC@ 0
 
# Delay slots
@OC@.d text_label
@OC@.nd text_label
@OC@.jd text_label
 
# Condition tests and delay slots
@OC@eq.d text_label
@OC@ne.nd text_label
@OC@cc.jd text_label
/lsr.s
0,0 → 1,38
# lsr test
 
lsr r0,r1
lsr fp,sp
 
lsr r0,0
lsr r1,-1
lsr 0,r2
lsr -1,r3
lsr r4,255
lsr 255,r5
lsr r6,-256
lsr -256,r7
 
lsr r8,256
lsr r9,-257
lsr r11,0x42424242
 
lsr 255,256
 
lsr r0,foo
 
lsr.eq r10,r11
lsr.ne r12,r13
lsr.lt r14,0
lsr.gt r15,512
 
lsr.f r0,r1
lsr.f r2,1
lsr.f 0,r4
lsr.f r5,512
lsr.f 512,512
 
lsr.eq.f r0,r1
lsr.ne.f r1,0
lsr.lt.f 0,r2
lsr.le.f r0,512
lsr.n.f 512,512
/warn.exp
0,0 → 1,8
# Test assembler warnings.
 
if [istarget arc*-*-*] {
load_lib gas-dg.exp
dg-init
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/warn*.s]] "" ""
dg-finish
}
/mov.s
0,0 → 1,58
# mov test
 
mov r0,r1
mov fp,sp
 
mov r0,0
mov r1,-1
mov 0,r2
mov -1,r3
mov r4,255
mov 255,r5
mov r6,-256
mov -256,r7
 
mov r8,256
mov r9,-257
mov r11,0x42424242
 
mov 255,256
 
mov r0,foo
 
mov.al r0,r1
mov.ra r3,r4
mov.eq r6,r7
mov.z r9,r10
mov.ne r12,r13
mov.nz r15,r16
mov.pl r18,r19
mov.p r21,r22
mov.mi r24,r25
mov.n r27,r28
mov.cs r30,r31
mov.c r33,r34
mov.lo r36,r37
mov.cc r39,r40
mov.nc r42,r43
mov.hs r45,r46
mov.vs r48,r49
mov.v r49,r50
mov.vc r49,r55
mov.nv r49,r58
mov.gt r60,r60
mov.ge r0,0
mov.le 2,2
mov.hi r3,r3
mov.ls r4,r4
mov.pnz r5,r5
 
mov.f r0,r1
mov.f r2,1
mov.f 1,r3
mov.f 0,r4
mov.f r5,512
mov.f 512,512
 
mov.eq.f r0,r1
mov.ne.f r1,0
/or.d
0,0 → 1,85
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 84 00 68 68008400 or r0,r1,r2
4: 00 b8 4d 6b 6b4db800 or gp,fp,sp
8: 00 3e af 6b 6baf3e00 or ilink1,ilink2,blink
c: 00 f8 1d 6f 6f1df800 or r56,r59,lp_count
10: 00 fe 00 68 6800fe00 or r0,r1,0
14: 00 84 1f 68 681f8400 or r0,0,r2
18: 00 84 e0 6f 6fe08400 or 0,r1,r2
1c: ff ff 00 68 6800ffff or r0,r1,-1
20: ff 85 1f 68 681f85ff or r0,-1,r2
24: 00 84 e0 6f 6fe08400 or 0,r1,r2
28: ff fe 00 68 6800feff or r0,r1,255
2c: ff 84 1f 68 681f84ff or r0,255,r2
30: 00 84 e0 6f 6fe08400 or 0,r1,r2
34: 00 ff 00 68 6800ff00 or r0,r1,-256
38: 00 85 1f 68 681f8500 or r0,-256,r2
3c: 00 84 e0 6f 6fe08400 or 0,r1,r2
40: 00 fc 00 68 6800fc00 or r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 68 681f0400 or r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 68 681ffcff or r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 68 681f7eff or r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 68 6800fc00 or r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 68 68008400 or r0,r1,r2
6c: 00 0a 62 68 68620a00 or r3,r4,r5
70: 01 90 c3 68 68c39001 or.z r6,r7,r8
74: 01 16 25 69 69251601 or.z r9,r10,r11
78: 02 9c 86 69 69869c02 or.nz r12,r13,r14
7c: 02 22 e8 69 69e82202 or.nz r15,r16,r17
80: 03 a8 49 6a 6a49a803 or.p r18,r19,r20
84: 03 2e ab 6a 6aab2e03 or.p r21,r22,r23
88: 04 b4 0c 6b 6b0cb404 or.n r24,r25,gp
8c: 04 3a 6e 6b 6b6e3a04 or.n fp,sp,ilink1
90: 05 c0 cf 6b 6bcfc005 or.c ilink2,blink,r32
94: 05 46 31 6c 6c314605 or.c r33,r34,r35
98: 05 cc 92 6c 6c92cc05 or.c r36,r37,r38
9c: 06 52 f4 6c 6cf45206 or.nc r39,r40,r41
a0: 06 d8 55 6d 6d55d806 or.nc r42,r43,r44
a4: 06 5e b7 6d 6db75e06 or.nc r45,r46,r47
a8: 07 e4 18 6e 6e18e407 or.v r48,r49,r50
ac: 07 6a 1a 6f 6f1a6a07 or.v r56,r52,r53
b0: 08 f0 1b 6f 6f1bf008 or.nv r56,r55,r56
b4: 08 76 1d 6f 6f1d7608 or.nv r56,r58,r59
b8: 09 00 9e 6f 6f9e0009 or.gt lp_count,lp_count,r0
bc: 0a 7c 00 68 68007c0a or.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 68 683f020b or.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 68 687f060d or.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 6f 6fdf080e or.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 6f 6fc2fc0f or.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 68 68008500 or.f r0,r1,r2
e8: 01 fa 00 68 6800fa01 or.f r0,r1,1
ec: 01 84 1e 68 681e8401 or.f r0,1,r2
f0: 00 85 e0 6f 6fe08500 or.f 0,r1,r2
f4: 00 fd 00 68 6800fd00 or.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 68 681f0500 or.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 68 68008501 or.z.f r0,r1,r2
108: 02 fd 00 68 6800fd02 or.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 68 681f050b or.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 6f 6fc08509 or.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 68 6800fd0c or.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 68 681f050a or.ge.f r0,0x200,r2
12c: 00 02 00 00
/rlc.d
0,0 → 1,68
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 82 00 48 48008200 rlc r0,r1
4: 00 38 6e 4b 4b6e3800 rlc fp,sp
8: 00 fe 1f 48 481ffe00 rlc r0,0
c: ff ff 3f 48 483fffff rlc r1,-1
10: 00 04 e1 4f 4fe10400 rlc 0,r2
14: 00 86 e1 4f 4fe18600 rlc 0,r3
18: ff fe 9f 48 489ffeff rlc r4,255
1c: 00 8a e2 4f 4fe28a00 rlc 0,r5
20: 00 ff df 48 48dfff00 rlc r6,-256
24: 00 8e e3 4f 4fe38e00 rlc 0,r7
28: 00 7c 1f 49 491f7c00 rlc r8,0x100
2c: 00 01 00 00
30: 00 7c 3f 49 493f7c00 rlc r9,0xffff_feff
34: ff fe ff ff
38: 00 7c 7f 49 497f7c00 rlc r11,0x4242_4242
3c: 42 42 42 42
40: 00 7c ff 4f 4fff7c00 rlc 0,0x100
44: 00 01 00 00
48: 00 7c 1f 48 481f7c00 rlc r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 00 82 00 48 48008200 rlc r0,r1
54: 00 08 62 48 48620800 rlc r3,r4
58: 01 8e c3 48 48c38e01 rlc.z r6,r7
5c: 01 14 25 49 49251401 rlc.z r9,r10
60: 02 9a 86 49 49869a02 rlc.nz r12,r13
64: 02 20 e8 49 49e82002 rlc.nz r15,r16
68: 03 a6 49 4a 4a49a603 rlc.p r18,r19
6c: 03 2c ab 4a 4aab2c03 rlc.p r21,r22
70: 04 b2 0c 4b 4b0cb204 rlc.n r24,r25
74: 04 38 6e 4b 4b6e3804 rlc.n fp,sp
78: 05 be cf 4b 4bcfbe05 rlc.c ilink2,blink
7c: 05 44 31 4c 4c314405 rlc.c r33,r34
80: 05 ca 92 4c 4c92ca05 rlc.c r36,r37
84: 06 50 f4 4c 4cf45006 rlc.nc r39,r40
88: 06 d6 55 4d 4d55d606 rlc.nc r42,r43
8c: 06 5c b7 4d 4db75c06 rlc.nc r45,r46
90: 07 e2 18 4e 4e18e207 rlc.v r48,r49
94: 07 64 39 4e 4e396407 rlc.v r49,r50
98: 08 ee 3b 4e 4e3bee08 rlc.nv r49,r55
9c: 08 74 3d 4e 4e3d7408 rlc.nv r49,r58
a0: 09 78 9e 4f 4f9e7809 rlc.gt lp_count,lp_count
a4: 0a 7c 1f 48 481f7c0a rlc.ge r0,0
a8: 00 00 00 00
ac: 0c 7c df 4f 4fdf7c0c rlc.le 0,2
b0: 02 00 00 00
b4: 0d 86 61 48 4861860d rlc.hi r3,r3
b8: 0e 08 82 48 4882080e rlc.ls r4,r4
bc: 0f 8a a2 48 48a28a0f rlc.pnz r5,r5
c0: 00 83 00 48 48008300 rlc.f r0,r1
c4: 01 fa 5e 48 485efa01 rlc.f r2,1
c8: 00 87 e1 4f 4fe18700 rlc.f 0,r3
cc: 00 09 e2 4f 4fe20900 rlc.f 0,r4
d0: 00 7d bf 48 48bf7d00 rlc.f r5,0x200
d4: 00 02 00 00
d8: 00 7d df 4f 4fdf7d00 rlc.f 0,0x200
dc: 00 02 00 00
e0: 01 83 00 48 48008301 rlc.z.f r0,r1
e4: 02 7d 3f 48 483f7d02 rlc.nz.f r1,0
e8: 00 00 00 00
/and.s
0,0 → 1,68
# and test
 
and r0,r1,r2
and r26,fp,sp
and ilink1,ilink2,blink
and r56,r59,lp_count
 
and r0,r1,0
and r0,0,r2
and 0,r1,r2
and r0,r1,-1
and r0,-1,r2
and -1,r1,r2
and r0,r1,255
and r0,255,r2
and 255,r1,r2
and r0,r1,-256
and r0,-256,r2
and -256,r1,r2
 
and r0,r1,256
and r0,-257,r2
 
and r0,255,256
and r0,256,255
 
and r0,r1,foo
 
and.al r0,r1,r2
and.ra r3,r4,r5
and.eq r6,r7,r8
and.z r9,r10,r11
and.ne r12,r13,r14
and.nz r15,r16,r17
and.pl r18,r19,r20
and.p r21,r22,r23
and.mi r24,r25,r26
and.n r27,r28,r29
and.cs r30,r31,r32
and.c r33,r34,r35
and.lo r36,r37,r38
and.cc r39,r40,r41
and.nc r42,r43,r44
and.hs r45,r46,r47
and.vs r48,r49,r50
and.v r56,r52,r53
and.vc r56,r55,r56
and.nv r56,r58,r59
and.gt r60,r60,r0
and.ge r0,r0,0
and.lt r1,1,r1
and.hi r3,3,r3
and.ls 4,4,r4
and.pnz 5,r5,5
 
and.f r0,r1,r2
and.f r0,r1,1
and.f r0,1,r2
and.f 0,r1,r2
and.f r0,r1,512
and.f r0,512,r2
 
and.eq.f r0,r1,r2
and.ne.f r0,r1,0
and.lt.f r0,0,r2
and.gt.f 0,r1,r2
and.le.f r0,r1,512
and.ge.f r0,512,r2
/ld2.d
0,0 → 1,21
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 80 00 08 08008000 ld r0,\[r1\]
4: 01 00 a3 08 08a30001 ld r5,\[r6,1\]
8: 00 00 7f 0a 0a7f0000 ld r19,\[0\]
c: 00 00 00 00
c: R_ARC_32 foo
10: 0a 10 81 08 0881100a ld.a r4,\[r2,10\]
14: 00 00 3f 08 083f0000 ld r1,\[0x384\]
18: 84 03 00 00
1c: 0f 84 41 08 0841840f ldb r2,\[r3,15\]
20: fe 09 62 08 086209fe ldw r3,\[r4,-2\]
24: 00 20 21 08 08212000 lr r1,\[r2\]
28: 14 a0 3f 08 083fa014 lr r1,\[0x14\]
2c: 00 a0 1f 08 081fa000 lr r0,\[status\]
/ror.s
0,0 → 1,38
# ror test
 
ror r0,r1
ror fp,sp
 
ror r0,0
ror r1,-1
ror 0,r2
ror -1,r3
ror r4,255
ror 255,r5
ror r6,-256
ror -256,r7
 
ror r8,256
ror r9,-257
ror r11,0x42424242
 
ror 255,256
 
ror r0,foo
 
ror.eq r10,r11
ror.ne r12,r13
ror.lt r14,0
ror.gt r15,512
 
ror.f r0,r1
ror.f r2,1
ror.f 0,r4
ror.f r5,512
ror.f 512,512
 
ror.eq.f r0,r1
ror.ne.f r1,0
ror.lt.f 0,r2
ror.le.f r0,512
ror.n.f 512,512
/st.d
0,0 → 1,42
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 02 01 10 10010200 st r1,\[r2\]
4: 0e 02 01 10 1001020e st r1,\[r2,14\]
8: 00 02 41 10 10410200 stb r1,\[r2\]
c: 0e 82 01 11 1101820e st.a r1,\[r3,14\]
10: 02 02 81 11 11810202 stw.a r1,\[r2,2\]
14: 00 02 1f 10 101f0200 st r1,\[0x384\]
18: 84 03 00 00
1c: 00 7e 41 10 10417e00 stb 0,\[r2\]
20: f8 7f 01 10 10017ff8 st -8,\[r2,-8\]
24: 50 7e 1f 10 101f7e50 st 80,\[0x2ee\]
28: 9e 02 00 00
2c: 00 04 1f 10 101f0400 st r2,\[0\]
30: 00 00 00 00
30: R_ARC_32 foo
34: 02 02 01 14 14010202 st.di r1,\[r2,2\]
38: 03 02 01 15 15010203 st.a.di r1,\[r2,3\]
3c: 04 02 81 15 15810204 stw.a.di r1,\[r2,4\]
40: 04 7c 06 10 10067c04 st 80,\[r12,4\]
44: 50 00 00 00
44: R_ARC_32 .text
48: 04 7c 06 10 10067c04 st 20,\[r12,4\]
4c: 14 00 00 00
4c: R_ARC_B26 .text
50: 00 02 01 12 12010200 sr r1,\[r2\]
54: 0e 82 1f 12 121f820e sr r1,\[0xe\]
58: 00 fc 00 12 1200fc00 sr 0x3e8,\[r1\]
5c: e8 03 00 00
60: 64 7e 01 12 12017e64 sr 100,\[r2\]
64: 00 02 1f 12 121f0200 sr r1,\[0x2710\]
68: 10 27 00 00
6c: 64 7e 1f 12 121f7e64 sr 100,\[0x2710\]
70: 10 27 00 00
74: 64 fc 1f 12 121ffc64 sr 0x2710,\[0x64\]
78: 10 27 00 00
/xor.s
0,0 → 1,68
# xor test
 
xor r0,r1,r2
xor r26,fp,sp
xor ilink1,ilink2,blink
xor r56,r59,lp_count
 
xor r0,r1,0
xor r0,0,r2
xor 0,r1,r2
xor r0,r1,-1
xor r0,-1,r2
xor -1,r1,r2
xor r0,r1,255
xor r0,255,r2
xor 255,r1,r2
xor r0,r1,-256
xor r0,-256,r2
xor -256,r1,r2
 
xor r0,r1,256
xor r0,-257,r2
 
xor r0,255,256
xor r0,256,255
 
xor r0,r1,foo
 
xor.al r0,r1,r2
xor.ra r3,r4,r5
xor.eq r6,r7,r8
xor.z r9,r10,r11
xor.ne r12,r13,r14
xor.nz r15,r16,r17
xor.pl r18,r19,r20
xor.p r21,r22,r23
xor.mi r24,r25,r26
xor.n r27,r28,r29
xor.cs r30,r31,r32
xor.c r33,r34,r35
xor.lo r36,r37,r38
xor.cc r39,r40,r41
xor.nc r42,r43,r44
xor.hs r45,r46,r47
xor.vs r48,r49,r50
xor.v r56,r52,r53
xor.vc r56,r55,r56
xor.nv r56,r58,r59
xor.gt r60,r60,r0
xor.ge r0,r0,0
xor.lt r1,1,r1
xor.hi r3,3,r3
xor.ls 4,4,r4
xor.pnz 5,r5,5
 
xor.f r0,r1,r2
xor.f r0,r1,1
xor.f r0,1,r2
xor.f 0,r1,r2
xor.f r0,r1,512
xor.f r0,512,r2
 
xor.eq.f r0,r1,r2
xor.ne.f r0,r1,0
xor.lt.f r0,0,r2
xor.gt.f 0,r1,r2
xor.le.f r0,r1,512
xor.ge.f r0,512,r2
/flag.s
0,0 → 1,27
# flag test
 
flag r0
 
flag 1
flag 2
flag 4
flag 8
flag 16
flag 32
flag 64
flag 128
 
flag 0x80000001
 
flag.lt r0
 
flag.gt 1
flag.gt 2
flag.gt 4
flag.gt 8
flag.gt 16
flag.gt 32
flag.gt 64
flag.gt 128
 
flag.ge 0x80000001
/bl.d
0,0 → 1,76
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <text_label>:
0: 80 ff ff 2f 2fffff80 bl 0 <text_label>
 
4: 00 ff ff 2f 2fffff00 bl 0 <text_label>
 
8: 80 fe ff 2f 2ffffe80 bl 0 <text_label>
 
c: 01 fe ff 2f 2ffffe01 blz 0 <text_label>
 
10: 81 fd ff 2f 2ffffd81 blz 0 <text_label>
 
14: 02 fd ff 2f 2ffffd02 blnz 0 <text_label>
 
18: 82 fc ff 2f 2ffffc82 blnz 0 <text_label>
 
1c: 03 fc ff 2f 2ffffc03 blp 0 <text_label>
 
20: 83 fb ff 2f 2ffffb83 blp 0 <text_label>
 
24: 04 fb ff 2f 2ffffb04 bln 0 <text_label>
 
28: 84 fa ff 2f 2ffffa84 bln 0 <text_label>
 
2c: 05 fa ff 2f 2ffffa05 blc 0 <text_label>
 
30: 85 f9 ff 2f 2ffff985 blc 0 <text_label>
 
34: 05 f9 ff 2f 2ffff905 blc 0 <text_label>
 
38: 86 f8 ff 2f 2ffff886 blnc 0 <text_label>
 
3c: 06 f8 ff 2f 2ffff806 blnc 0 <text_label>
 
40: 86 f7 ff 2f 2ffff786 blnc 0 <text_label>
 
44: 07 f7 ff 2f 2ffff707 blv 0 <text_label>
 
48: 87 f6 ff 2f 2ffff687 blv 0 <text_label>
 
4c: 08 f6 ff 2f 2ffff608 blnv 0 <text_label>
 
50: 88 f5 ff 2f 2ffff588 blnv 0 <text_label>
 
54: 09 f5 ff 2f 2ffff509 blgt 0 <text_label>
 
58: 8a f4 ff 2f 2ffff48a blge 0 <text_label>
 
5c: 0b f4 ff 2f 2ffff40b bllt 0 <text_label>
 
60: 8c f3 ff 2f 2ffff38c blle 0 <text_label>
 
64: 0d f3 ff 2f 2ffff30d blhi 0 <text_label>
 
68: 8e f2 ff 2f 2ffff28e blls 0 <text_label>
 
6c: 0f f2 ff 2f 2ffff20f blpnz 0 <text_label>
 
70: a0 f1 ff 2f 2ffff1a0 bl.d 0 <text_label>
 
74: 00 f1 ff 2f 2ffff100 bl 0 <text_label>
 
78: c0 f0 ff 2f 2ffff0c0 bl.jd 0 <text_label>
 
7c: 21 f0 ff 2f 2ffff021 blz.d 0 <text_label>
 
80: 82 ef ff 2f 2fffef82 blnz 0 <text_label>
 
84: 46 ef ff 2f 2fffef46 blnc.jd 0 <text_label>
 
/rlc.s
0,0 → 1,58
# rlc test
 
rlc r0,r1
rlc fp,sp
 
rlc r0,0
rlc r1,-1
rlc 0,r2
rlc -1,r3
rlc r4,255
rlc 255,r5
rlc r6,-256
rlc -256,r7
 
rlc r8,256
rlc r9,-257
rlc r11,0x42424242
 
rlc 255,256
 
rlc r0,foo
 
rlc.al r0,r1
rlc.ra r3,r4
rlc.eq r6,r7
rlc.z r9,r10
rlc.ne r12,r13
rlc.nz r15,r16
rlc.pl r18,r19
rlc.p r21,r22
rlc.mi r24,r25
rlc.n r27,r28
rlc.cs r30,r31
rlc.c r33,r34
rlc.lo r36,r37
rlc.cc r39,r40
rlc.nc r42,r43
rlc.hs r45,r46
rlc.vs r48,r49
rlc.v r49,r50
rlc.vc r49,r55
rlc.nv r49,r58
rlc.gt r60,r60
rlc.ge r0,0
rlc.le 2,2
rlc.hi r3,r3
rlc.ls r4,r4
rlc.pnz r5,r5
 
rlc.f r0,r1
rlc.f r2,1
rlc.f 1,r3
rlc.f 0,r4
rlc.f r5,512
rlc.f 512,512
 
rlc.eq.f r0,r1
rlc.ne.f r1,0
/or.s
0,0 → 1,68
# or test
 
or r0,r1,r2
or r26,fp,sp
or ilink1,ilink2,blink
or r56,r59,lp_count
 
or r0,r1,0
or r0,0,r2
or 0,r1,r2
or r0,r1,-1
or r0,-1,r2
or -1,r1,r2
or r0,r1,255
or r0,255,r2
or 255,r1,r2
or r0,r1,-256
or r0,-256,r2
or -256,r1,r2
 
or r0,r1,256
or r0,-257,r2
 
or r0,255,256
or r0,256,255
 
or r0,r1,foo
 
or.al r0,r1,r2
or.ra r3,r4,r5
or.eq r6,r7,r8
or.z r9,r10,r11
or.ne r12,r13,r14
or.nz r15,r16,r17
or.pl r18,r19,r20
or.p r21,r22,r23
or.mi r24,r25,r26
or.n r27,r28,r29
or.cs r30,r31,r32
or.c r33,r34,r35
or.lo r36,r37,r38
or.cc r39,r40,r41
or.nc r42,r43,r44
or.hs r45,r46,r47
or.vs r48,r49,r50
or.v r56,r52,r53
or.vc r56,r55,r56
or.nv r56,r58,r59
or.gt r60,r60,r0
or.ge r0,r0,0
or.lt r1,1,r1
or.hi r3,3,r3
or.ls 4,4,r4
or.pnz 5,r5,5
 
or.f r0,r1,r2
or.f r0,r1,1
or.f r0,1,r2
or.f 0,r1,r2
or.f r0,r1,512
or.f r0,512,r2
 
or.eq.f r0,r1,r2
or.ne.f r0,r1,0
or.lt.f r0,0,r2
or.gt.f 0,r1,r2
or.le.f r0,r1,512
or.ge.f r0,512,r2
/ld2.s
0,0 → 1,13
# ld/lr test
 
ld r0,[r1]
ld r5,[r6,1]
ld r19,[foo]
ld.a r4,[r2,10]
ld r1,[900]
ldb r2,[r3,15]
ldw r3,[r4,-2]
lr r1,[r2]
lr r1,[20]
lr r0,[status]
/sexb.d
0,0 → 1,51
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 8a 00 18 18008a00 sexb r0,r1
4: 00 0a 6e 1b 1b6e0a00 sexb fp,sp
8: 00 8a 1f 18 181f8a00 sexb r0,0
c: ff 8b 3f 18 183f8bff sexb r1,-1
10: 00 0a e1 1f 1fe10a00 sexb 0,r2
14: 00 8a e1 1f 1fe18a00 sexb 0,r3
18: ff 8a 9f 18 189f8aff sexb r4,255
1c: 00 8a e2 1f 1fe28a00 sexb 0,r5
20: 00 8b df 18 18df8b00 sexb r6,-256
24: 00 8a e3 1f 1fe38a00 sexb 0,r7
28: 00 0a 1f 19 191f0a00 sexb r8,0x100
2c: 00 01 00 00
30: 00 0a 3f 19 193f0a00 sexb r9,0xffff_feff
34: ff fe ff ff
38: 00 0a 7f 19 197f0a00 sexb r11,0x4242_4242
3c: 42 42 42 42
40: 00 0a ff 1f 1fff0a00 sexb 0,0x100
44: 00 01 00 00
48: 00 0a 1f 18 181f0a00 sexb r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 8a 45 19 19458a01 sexb.z r10,r11
54: 02 8a 86 19 19868a02 sexb.nz r12,r13
58: 0b 0a df 19 19df0a0b sexb.lt r14,0
5c: 00 00 00 00
60: 09 0a ff 19 19ff0a09 sexb.gt r15,0x200
64: 00 02 00 00
68: 00 8b 00 18 18008b00 sexb.f r0,r1
6c: 01 8a 5e 18 185e8a01 sexb.f r2,1
70: 00 0b e2 1f 1fe20b00 sexb.f 0,r4
74: 00 0b bf 18 18bf0b00 sexb.f r5,0x200
78: 00 02 00 00
7c: 00 0b df 1f 1fdf0b00 sexb.f 0,0x200
80: 00 02 00 00
84: 01 8b 00 18 18008b01 sexb.z.f r0,r1
88: 02 0b 3f 18 183f0b02 sexb.nz.f r1,0
8c: 00 00 00 00
90: 0b 0b c1 1f 1fc10b0b sexb.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 0b 1f 18 181f0b0c sexb.le.f r0,0x200
9c: 00 02 00 00
a0: 04 0b df 1f 1fdf0b04 sexb.n.f 0,0x200
a4: 00 02 00 00
/jl.d
0,0 → 1,25
#as: -EL -marc6
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <text_label>:
0: 40 02 1f 38 381f0240 jl 0 <text_label>
 
4: 00 00 00 00
4: R_ARC_B26 .text
8: 40 03 1f 38 381f0340 jl.f 0 <text_label>
 
c: 00 00 00 00
c: R_ARC_B26 .text
10: 02 82 00 38 38008202 jlnz \[r1\]
14: 40 02 1f 38 381f0240 jl 0 <text_label>
 
18: 00 00 00 00
18: R_ARC_B26 .text
1c: 40 03 1f 38 381f0340 jl.f 0 <text_label>
 
20: 00 00 00 00
20: R_ARC_B26 .text
/st.s
0,0 → 1,27
# st test
 
st r1,[r2]
st r1,[r2,14]
stb r1,[r2]
st.a r1,[r3,14]
stw.a r1,[r2,2]
st r1,[900]
stb 0,[r2]
st -8,[r2,-8]
st 80,[750]
st r2,[foo]
st.di r1,[r2,2]
st.a.di r1,[r2,3]
stw.a.di r1,[r2,4]
 
st .L1,[r12,4]
st .L1@h30,[r12,4]
.L1:
 
sr r1,[r2]
sr r1,[14]
sr 1000, [r1]
sr 100, [r2]
sr r1,[10000]
sr 100,[10000]
sr 10000,[100]
/bl.s
0,0 → 1,40
# bl test
text_label:
 
bl text_label
blal text_label
blra text_label
bleq text_label
blz text_label
blne text_label
blnz text_label
blpl text_label
blp text_label
blmi text_label
bln text_label
blcs text_label
blc text_label
bllo text_label
blcc text_label
blnc text_label
blhs text_label
blvs text_label
blv text_label
blvc text_label
blnv text_label
blgt text_label
blge text_label
bllt text_label
blle text_label
blhi text_label
blls text_label
blpnz text_label
 
bl.d text_label
bl.nd text_label
bl.jd text_label
 
bleq.d text_label
blne.nd text_label
blcc.jd text_label
/sexb.s
0,0 → 1,38
# sexb test
 
sexb r0,r1
sexb fp,sp
 
sexb r0,0
sexb r1,-1
sexb 0,r2
sexb -1,r3
sexb r4,255
sexb 255,r5
sexb r6,-256
sexb -256,r7
 
sexb r8,256
sexb r9,-257
sexb r11,0x42424242
 
sexb 255,256
 
sexb r0,foo
 
sexb.eq r10,r11
sexb.ne r12,r13
sexb.lt r14,0
sexb.gt r15,512
 
sexb.f r0,r1
sexb.f r2,1
sexb.f 0,r4
sexb.f r5,512
sexb.f 512,512
 
sexb.eq.f r0,r1
sexb.ne.f r1,0
sexb.lt.f 0,r2
sexb.le.f r0,512
sexb.n.f 512,512
/jl.s
0,0 → 1,9
# jl test
 
text_label:
 
jl text_label
jl.f text_label
jlnz.nd [r1]
jlal text_label
jlal.f text_label
/extw.d
0,0 → 1,51
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 90 00 18 18009000 extw r0,r1
4: 00 10 6e 1b 1b6e1000 extw fp,sp
8: 00 90 1f 18 181f9000 extw r0,0
c: ff 91 3f 18 183f91ff extw r1,-1
10: 00 10 e1 1f 1fe11000 extw 0,r2
14: 00 90 e1 1f 1fe19000 extw 0,r3
18: ff 90 9f 18 189f90ff extw r4,255
1c: 00 90 e2 1f 1fe29000 extw 0,r5
20: 00 91 df 18 18df9100 extw r6,-256
24: 00 90 e3 1f 1fe39000 extw 0,r7
28: 00 10 1f 19 191f1000 extw r8,0x100
2c: 00 01 00 00
30: 00 10 3f 19 193f1000 extw r9,0xffff_feff
34: ff fe ff ff
38: 00 10 7f 19 197f1000 extw r11,0x4242_4242
3c: 42 42 42 42
40: 00 10 ff 1f 1fff1000 extw 0,0x100
44: 00 01 00 00
48: 00 10 1f 18 181f1000 extw r0,0
4c: 00 00 00 00
4c: R_ARC_32 foo
50: 01 90 45 19 19459001 extw.z r10,r11
54: 02 90 86 19 19869002 extw.nz r12,r13
58: 0b 10 df 19 19df100b extw.lt r14,0
5c: 00 00 00 00
60: 09 10 ff 19 19ff1009 extw.gt r15,0x200
64: 00 02 00 00
68: 00 91 00 18 18009100 extw.f r0,r1
6c: 01 90 5e 18 185e9001 extw.f r2,1
70: 00 11 e2 1f 1fe21100 extw.f 0,r4
74: 00 11 bf 18 18bf1100 extw.f r5,0x200
78: 00 02 00 00
7c: 00 11 df 1f 1fdf1100 extw.f 0,0x200
80: 00 02 00 00
84: 01 91 00 18 18009101 extw.z.f r0,r1
88: 02 11 3f 18 183f1102 extw.nz.f r1,0
8c: 00 00 00 00
90: 0b 11 c1 1f 1fc1110b extw.lt.f 0,r2
94: 00 00 00 00 00000000
98: 0c 11 1f 18 181f110c extw.le.f r0,0x200
9c: 00 02 00 00
a0: 04 11 df 1f 1fdf1104 extw.n.f 0,0x200
a4: 00 02 00 00
/add.d
0,0 → 1,85
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 84 00 40 40008400 add r0,r1,r2
4: 00 b8 4d 43 434db800 add gp,fp,sp
8: 00 3e af 43 43af3e00 add ilink1,ilink2,blink
c: 00 f8 1d 47 471df800 add r56,r59,lp_count
10: 00 fe 00 40 4000fe00 add r0,r1,0
14: 00 84 1f 40 401f8400 add r0,0,r2
18: 00 84 e0 47 47e08400 add 0,r1,r2
1c: ff ff 00 40 4000ffff add r0,r1,-1
20: ff 85 1f 40 401f85ff add r0,-1,r2
24: 00 84 e0 47 47e08400 add 0,r1,r2
28: ff fe 00 40 4000feff add r0,r1,255
2c: ff 84 1f 40 401f84ff add r0,255,r2
30: 00 84 e0 47 47e08400 add 0,r1,r2
34: 00 ff 00 40 4000ff00 add r0,r1,-256
38: 00 85 1f 40 401f8500 add r0,-256,r2
3c: 00 84 e0 47 47e08400 add 0,r1,r2
40: 00 fc 00 40 4000fc00 add r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 40 401f0400 add r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 40 401ffcff add r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 40 401f7eff add r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 40 4000fc00 add r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 40 40008400 add r0,r1,r2
6c: 00 0a 62 40 40620a00 add r3,r4,r5
70: 01 90 c3 40 40c39001 add.z r6,r7,r8
74: 01 16 25 41 41251601 add.z r9,r10,r11
78: 02 9c 86 41 41869c02 add.nz r12,r13,r14
7c: 02 22 e8 41 41e82202 add.nz r15,r16,r17
80: 03 a8 49 42 4249a803 add.p r18,r19,r20
84: 03 2e ab 42 42ab2e03 add.p r21,r22,r23
88: 04 b4 0c 43 430cb404 add.n r24,r25,gp
8c: 04 3a 6e 43 436e3a04 add.n fp,sp,ilink1
90: 05 c0 cf 43 43cfc005 add.c ilink2,blink,r32
94: 05 46 31 44 44314605 add.c r33,r34,r35
98: 05 cc 92 44 4492cc05 add.c r36,r37,r38
9c: 06 52 f4 44 44f45206 add.nc r39,r40,r41
a0: 06 d8 55 45 4555d806 add.nc r42,r43,r44
a4: 06 5e b7 45 45b75e06 add.nc r45,r46,r47
a8: 07 e4 18 46 4618e407 add.v r48,r49,r50
ac: 07 6a 1a 47 471a6a07 add.v r56,r52,r53
b0: 08 f0 1b 47 471bf008 add.nv r56,r55,r56
b4: 08 76 1d 47 471d7608 add.nv r56,r58,r59
b8: 09 00 9e 47 479e0009 add.gt lp_count,lp_count,r0
bc: 0a 7c 00 40 40007c0a add.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 40 403f020b add.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 40 407f060d add.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 47 47df080e add.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 47 47c2fc0f add.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 40 40008500 add.f r0,r1,r2
e8: 01 fa 00 40 4000fa01 add.f r0,r1,1
ec: 01 84 1e 40 401e8401 add.f r0,1,r2
f0: 00 85 e0 47 47e08500 add.f 0,r1,r2
f4: 00 fd 00 40 4000fd00 add.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 40 401f0500 add.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 40 40008501 add.z.f r0,r1,r2
108: 02 fd 00 40 4000fd02 add.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 40 401f050b add.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 47 47c08509 add.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 40 4000fd0c add.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 40 401f050a add.ge.f r0,0x200,r2
12c: 00 02 00 00
/sub.d
0,0 → 1,85
#as: -EL
#objdump: -dr -EL
 
.*: +file format elf32-.*arc
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 84 00 50 50008400 sub r0,r1,r2
4: 00 b8 4d 53 534db800 sub gp,fp,sp
8: 00 3e af 53 53af3e00 sub ilink1,ilink2,blink
c: 00 f8 1d 57 571df800 sub r56,r59,lp_count
10: 00 fe 00 50 5000fe00 sub r0,r1,0
14: 00 84 1f 50 501f8400 sub r0,0,r2
18: 00 84 e0 57 57e08400 sub 0,r1,r2
1c: ff ff 00 50 5000ffff sub r0,r1,-1
20: ff 85 1f 50 501f85ff sub r0,-1,r2
24: 00 84 e0 57 57e08400 sub 0,r1,r2
28: ff fe 00 50 5000feff sub r0,r1,255
2c: ff 84 1f 50 501f84ff sub r0,255,r2
30: 00 84 e0 57 57e08400 sub 0,r1,r2
34: 00 ff 00 50 5000ff00 sub r0,r1,-256
38: 00 85 1f 50 501f8500 sub r0,-256,r2
3c: 00 84 e0 57 57e08400 sub 0,r1,r2
40: 00 fc 00 50 5000fc00 sub r0,r1,0x100
44: 00 01 00 00
48: 00 04 1f 50 501f0400 sub r0,0xffff_feff,r2
4c: ff fe ff ff
50: ff fc 1f 50 501ffcff sub r0,255,0x100
54: 00 01 00 00
58: ff 7e 1f 50 501f7eff sub r0,0x100,255
5c: 00 01 00 00
60: 00 fc 00 50 5000fc00 sub r0,r1,0
64: 00 00 00 00
64: R_ARC_32 foo
68: 00 84 00 50 50008400 sub r0,r1,r2
6c: 00 0a 62 50 50620a00 sub r3,r4,r5
70: 01 90 c3 50 50c39001 sub.z r6,r7,r8
74: 01 16 25 51 51251601 sub.z r9,r10,r11
78: 02 9c 86 51 51869c02 sub.nz r12,r13,r14
7c: 02 22 e8 51 51e82202 sub.nz r15,r16,r17
80: 03 a8 49 52 5249a803 sub.p r18,r19,r20
84: 03 2e ab 52 52ab2e03 sub.p r21,r22,r23
88: 04 b4 0c 53 530cb404 sub.n r24,r25,gp
8c: 04 3a 6e 53 536e3a04 sub.n fp,sp,ilink1
90: 05 c0 cf 53 53cfc005 sub.c ilink2,blink,r32
94: 05 46 31 54 54314605 sub.c r33,r34,r35
98: 05 cc 92 54 5492cc05 sub.c r36,r37,r38
9c: 06 52 f4 54 54f45206 sub.nc r39,r40,r41
a0: 06 d8 55 55 5555d806 sub.nc r42,r43,r44
a4: 06 5e b7 55 55b75e06 sub.nc r45,r46,r47
a8: 07 e4 18 56 5618e407 sub.v r48,r49,r50
ac: 07 6a 1a 57 571a6a07 sub.v r56,r52,r53
b0: 08 f0 1b 57 571bf008 sub.nv r56,r55,r56
b4: 08 76 1d 57 571d7608 sub.nv r56,r58,r59
b8: 09 00 9e 57 579e0009 sub.gt lp_count,lp_count,r0
bc: 0a 7c 00 50 50007c0a sub.ge r0,r0,0
c0: 00 00 00 00
c4: 0b 02 3f 50 503f020b sub.lt r1,1,r1
c8: 01 00 00 00
cc: 0d 06 7f 50 507f060d sub.hi r3,3,r3
d0: 03 00 00 00
d4: 0e 08 df 57 57df080e sub.ls 0,4,r4
d8: 04 00 00 00
dc: 0f fc c2 57 57c2fc0f sub.pnz 0,r5,5
e0: 05 00 00 00
e4: 00 85 00 50 50008500 sub.f r0,r1,r2
e8: 01 fa 00 50 5000fa01 sub.f r0,r1,1
ec: 01 84 1e 50 501e8401 sub.f r0,1,r2
f0: 00 85 e0 57 57e08500 sub.f 0,r1,r2
f4: 00 fd 00 50 5000fd00 sub.f r0,r1,0x200
f8: 00 02 00 00
fc: 00 05 1f 50 501f0500 sub.f r0,0x200,r2
100: 00 02 00 00
104: 01 85 00 50 50008501 sub.z.f r0,r1,r2
108: 02 fd 00 50 5000fd02 sub.nz.f r0,r1,0
10c: 00 00 00 00
110: 0b 05 1f 50 501f050b sub.lt.f r0,0,r2
114: 00 00 00 00
118: 09 85 c0 57 57c08509 sub.gt.f 0,r1,r2
11c: 00 00 00 00 00000000
120: 0c fd 00 50 5000fd0c sub.le.f r0,r1,0x200
124: 00 02 00 00
128: 0a 05 1f 50 501f050a sub.ge.f r0,0x200,r2
12c: 00 02 00 00

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