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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/gnu-stable/binutils-2.20.1/gas/testsuite/gas/dlx
    from Rev 816 to Rev 818
    ↔ Reverse comparison
  •

Rev 816 → Rev 818

/branch.d
0,0 → 1,43
#as:
#objdump: -dr
#name: branch
 
.*: +file format .*
 
Disassembly of section .text:
 
00000000 <L1>:
0: 10 80 00 38 beqz r4,0x0000003c
4: 00 00 00 00 nop
8: 14 a0 ff f4 bnez r5,0x00000000
 
0000000c <L2>:
c: 20 04 00 44 addi r4,r0,0x0044
e: R_DLX_RELOC_16 .text
10: 08 00 00 30 j 0x00000044
14: 00 00 00 00 nop
18: 0c 00 00 20 jal 0x0000003c
1c: 00 00 00 00 nop
20: 50 00 00 18 break 0x0000003c
24: 00 00 00 00 nop
28: 47 ff ff d4 trap 0x00000000
2c: 00 00 00 00 nop
30: 4a 20 00 00 jr r17
34: 00 00 00 00 nop
38: 4e 20 00 00 jalr r17
 
0000003c <L4>:
3c: 8c 42 00 88 lw r2,0x0088\[r2\]
40: 40 00 00 00 rfe 0x00000044
 
00000044 <L5>:
44: 8c 02 00 00 lw r2,0x0000\[r0\]
46: R_DLX_RELOC_16 .text
48: 0b ff ff b4 j 0x00000000
4c: 00 00 00 00 nop
50: 4b e0 00 00 jr r31
54: 00 00 00 00 nop
58: 4b e0 00 00 jr r31
5c: 00 00 00 00 nop
60: 48 20 00 00 jr r1
64: 00 00 00 00 nop
/load.s
0,0 → 1,19
.text
lb %3,%hi(L)
lb %3,%hi(L - 7f + ((4f - 5f)<<4))(r2)
2: lb %3,%hi(1f)
1: lbu %3,%hi((4f - 5f) + 8 - ((5f - 4f)<<4))(r2)
7:
L:
lh r3,%hi(5f)[r5]
5: lhu v1,('8' - '0')(t7)
lw r1,32767($2)
lw r1,2b
.word 0x1000
.long 0x2000
4:
.asciz "this is a test"
.align 4
ldstbu %3,%hi((4b - 5b) + 8 - ((5b - 4b)<<4))(r2)
ldsthu %3,%hi((4b - 5b) + 8 - ((5b - 4b)<<4))(r2)
ldstw %3,%hi((4b - 5b) + 8 - ((5b - 4b)<<4))(r2)
/load.d
0,0 → 1,33
#as:
#objdump: -dr
#name: load
 
.*: +file format .*
 
Disassembly of section .text:
 
00000000 <L-0x10>:
0: 80 03 00 00 lb r3,0x0000\[r0\]
2: R_DLX_RELOC_16_HI .text
4: 80 43 00 00 lb r3,0x0000\[r2\]
8: 80 03 00 00 lb r3,0x0000\[r0\]
a: R_DLX_RELOC_16_HI .text
c: 90 43 00 00 lbu r3,0x0000\[r2\]
 
00000010 <L>:
10: 84 a3 00 00 lh r3,0x0000\[r5\]
12: R_DLX_RELOC_16_HI .text
14: 95 e3 00 08 lhu r3,0x0008\[r15\]
18: 8c 41 7f ff lw r1,0x7fff\[r2\]
1c: 8c 01 00 08 lw r1,0x0008\[r0\]
1e: R_DLX_RELOC_16 .text
20: 00 00 10 00 nop
24: 00 00 20 00 nop
28: 74 68 69 73 sgei r8,r3,0x6973
2c: 20 69 73 20 addi r9,r3,0x7320
30: 61 20 74 65 seqi r0,r9,0x7465
34: 73 74 00 00 slei r20,r27,0x0000
...
40: 98 43 00 00 ldstbu r3,0x0000\[r2\]
44: 9c 43 00 00 ldsthu r3,0x0000\[r2\]
48: b0 43 00 00 ldstw r3,0x0000\[r2\]
/rtype.s
0,0 → 1,33
.text
1: add $3,$1,$2
add %3,%1,%2
addu r3,r1,r2
sub r4,r2,r3
subu r4,r2,r3
mult a1,a2,a3
multu t4,t2,t3
div t7,t5,t6
divu s0,s1,s2
and s3,s4,s5
or s6,s7,zero
xor t7,t8,t9
sll k0,k1,zero
sra gp,sp,fp
srl t7,t5,ra
 
seq at,v0,v1
sne a0,ra,zero
slt t0,t1,t2
sgt $7,%5,r6
sle r7,$5,%6
sge r7,$5,%6
 
seq at,v0,v1
sne a0,ra,zero
slt t0,t1,t2
sgt $7,%5,r6
sle r7,$5,%6
sge r7,$5,%6
 
mvts $10,r5
mvfs r10,$5
/rtype.d
0,0 → 1,38
#as:
#objdump: -dr
#name: rtype
 
.*: +file format .*
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 22 18 20 add r3,r1,r2
4: 00 22 18 20 add r3,r1,r2
8: 00 22 18 21 addu r3,r1,r2
c: 00 43 20 22 sub r4,r2,r3
10: 00 43 20 23 subu r4,r2,r3
14: 00 c7 28 05 mult r5,r6,r7
18: 01 4b 60 06 multu r12,r10,r11
1c: 01 ae 78 07 div r15,r13,r14
20: 02 32 80 08 divu r16,r17,r18
24: 02 95 98 24 and r19,r20,r21
28: 02 e0 b0 25 or r22,r23,r0
2c: 03 19 78 26 xor r15,r24,r25
30: 03 60 d0 04 sll r26,r27,r0
34: 03 be e0 07 div r28,r29,r30
38: 01 bf 78 06 multu r15,r13,r31
3c: 00 43 08 28 seq r1,r2,r3
40: 03 e0 20 29 sne r4,r31,r0
44: 01 2a 40 2a slt r8,r9,r10
48: 00 a6 38 2b sgt r7,r5,r6
4c: 00 a6 38 2c sle r7,r5,r6
50: 00 a6 38 2d sge r7,r5,r6
54: 00 43 08 28 seq r1,r2,r3
58: 03 e0 20 29 sne r4,r31,r0
5c: 01 2a 40 2a slt r8,r9,r10
60: 00 a6 38 2b sgt r7,r5,r6
64: 00 a6 38 2c sle r7,r5,r6
68: 00 a6 38 2d sge r7,r5,r6
6c: 00 a0 50 30 mvts r10,r5
70: 00 a0 50 31 mvfs r10,r5
/alltests.exp
0,0 → 1,11
# DLX assembler testsuite.
 
if [istarget dlx*-*-*] {
run_dump_test "branch"
run_dump_test "itype"
run_dump_test "lhi"
run_dump_test "load"
run_dump_test "lohi"
run_dump_test "rtype"
run_dump_test "store"
}
/itype.s
0,0 → 1,30
.text
2: addi $3,$1,32767
addui r3,r1,-5
subi r4,r2,0x30
subui r4,r2,%hi(2b)
andi a1,a2,2b
ori t4,t2,'x'
xori t7,t5,%lo(2b)
1: slli s0,s1,1b
srai s3,s4,15
srli s6,s7,0xffff
 
seqi t7,t8,0x7fff
snei t7,t8,0x7fff
slti t7,t8,0x7fff
sgti k0,k1,0
slei gp,sp,-23767
sgei t7,t5,'0'
 
sequi t7,t8,0x7fff
sneui t7,t8,0x7fff
sltui t7,t8,0x7fff
sgtui k0,k1,0
sleui gp,sp,-3
sgeui t7,t5,'0'
 
mov at,-32765
mov t0,t1
movu at,%hi(1b)
movu t0,t1
/itype.d
0,0 → 1,40
#as:
#objdump: -dr
#name: itype
 
.*: +file format .*
 
Disassembly of section .text:
 
00000000 <.text>:
0: 20 23 7f ff addi r3,r1,0x7fff
4: 24 23 ff fb addui r3,r1,0xfffb
8: 28 44 00 30 subi r4,r2,0x0030
c: 2c 44 00 00 subui r4,r2,0x0000
e: R_DLX_RELOC_16_HI .text
10: 30 c5 00 00 andi r5,r6,0x0000
12: R_DLX_RELOC_16 .text
14: 35 4c 00 78 ori r12,r10,0x0078
18: 39 af 00 00 xori r15,r13,0x0000
1a: R_DLX_RELOC_16_LO .text
1c: da 30 00 1c slli r16,r17,0x001c
1e: R_DLX_RELOC_16 .text
20: e2 93 00 0f srai r19,r20,0x000f
24: de f6 ff ff srli r22,r23,0xffff
28: 63 0f 7f ff seqi r15,r24,0x7fff
2c: 67 0f 7f ff snei r15,r24,0x7fff
30: 6b 0f 7f ff slti r15,r24,0x7fff
34: 6f 7a 00 00 sgti r26,r27,0x0000
38: 73 bc a3 29 slei r28,r29,0xa329
3c: 75 af 00 30 sgei r15,r13,0x0030
40: c3 0f 7f ff sequi r15,r24,0x7fff
44: c7 0f 7f ff sneui r15,r24,0x7fff
48: cb 0f 7f ff sltui r15,r24,0x7fff
4c: cf 7a 00 00 sgtui r26,r27,0x0000
50: d3 bc ff fd sleui r28,r29,0xfffd
54: d5 af 00 30 sgeui r15,r13,0x0030
58: 20 01 80 03 addi r1,r0,0x8003
5c: 21 28 00 00 addi r8,r9,0x0000
60: 24 01 00 00 addui r1,r0,0x0000
62: R_DLX_RELOC_16_HI .text
64: 25 28 00 00 addui r8,r9,0x0000
/lohi.s
0,0 → 1,9
.text
.align 2
nop
.L1:
lhi r1,%hi(.L1 + 200000)
ori r1,r0,%lo(.L1 + 200000)
lhi r1,%hi(.L1 + 200000000)
ori r1,r0,%lo(.L1 + 200000000)
.end
/lhi.s
0,0 → 1,10
.text
2: lhi $3,32767
lui r3,%hi(2b)
sethi r4,%lo(2b)
lui r4, 2b - 5
sethi r4,('9' - '0') + ('3' - '0')
mov r4,%hi(. - 2b)
mov r4,%hi(.)
ori r4,r4,%lo(. - 4)
mov r4,r3
/lohi.d
0,0 → 1,18
#as:
#objdump: -dr
#name: lohi
 
.*: +file format .*
 
Disassembly of section .text:
 
00000000 <.text>:
0: 00 00 00 00 nop
4: 3c 01 00 03 lhi r1,0x0003
6: R_DLX_RELOC_16_HI .text
8: 34 01 0d 44 ori r1,r0,0x0d44
a: R_DLX_RELOC_16_LO .text
c: 3c 01 0b eb lhi r1,0x0beb
e: R_DLX_RELOC_16_HI .text
10: 34 01 c2 04 ori r1,r0,0xc204
12: R_DLX_RELOC_16_LO .text
/store.s
0,0 → 1,9
.text
2: sw L1(r0),%3
sw %hi(L1)(r0),%3
1: sh (1b - 2b) + 8 - ((5f - 4f)<<4)[r2],r3
4: sb 4b+'0',$3
4: sb L1+'0'-L1,$3
5: sw %hi((L1 - 2b) + 8 + ((5b - 4b)<<4))(r2),%3
nop
L1: nop
/branch.s
0,0 → 1,31
.text
L1:
1: beqz r4, L4
nop
bnez r5, 1b
L2:
mov r4, L5
j L5
nop
jal L4
nop
break L4
nop
trap 1b
nop
jr s1
nop
jalr s1
L4:
lw r2, 8+((L5 - L4)<<4)(r2)
rfe
L5:
lw r2, L1
call 1b
nop
return
nop
ret
nop
retr at
nop
/lhi.d
0,0 → 1,23
#as:
#objdump: -dr
#name: lhi
 
.*: +file format .*
 
Disassembly of section .text:
 
00000000 <.text>:
0: 3c 03 7f ff lhi r3,0x7fff
4: 3c 03 00 00 lhi r3,0x0000
6: R_DLX_RELOC_16_HI .text
8: 3c 04 00 00 lhi r4,0x0000
a: R_DLX_RELOC_16_LO .text
c: 3c 04 ff fb lhi r4,0xfffb
e: R_DLX_RELOC_16 .text
10: 3c 04 00 0c lhi r4,0x000c
14: 20 04 00 00 addi r4,r0,0x0000
18: 20 04 00 00 addi r4,r0,0x0000
1a: R_DLX_RELOC_16_HI .text
1c: 34 84 00 18 ori r4,r4,0x0018
1e: R_DLX_RELOC_16_LO .text
20: 20 64 00 00 addi r4,r3,0x0000
/store.d
0,0 → 1,22
#as:
#objdump: -dr
#name: store
 
.*: +file format .*
 
Disassembly of section .text:
 
00000000 <L1-0x1c>:
0: ac 03 00 1c sw 0x001c\[r0\],r3
2: R_DLX_RELOC_16 .text
4: ac 03 00 00 sw 0x0000\[r0\],r3
6: R_DLX_RELOC_16_HI .text
8: a4 43 ff 90 sh 0xff90\[r2\],r3
c: a0 03 00 3c sb 0x003c\[r0\],r3
e: R_DLX_RELOC_16 .text
10: a0 03 00 30 sb 0x0030\[r0\],r3
14: ac 43 00 00 sw 0x0000\[r2\],r3
18: 00 00 00 00 nop
 
0000001c <L1>:
1c: 00 00 00 00 nop

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