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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

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  • This comparison shows the changes necessary to convert path
    /openrisc/trunk/or1200/rtl/verilog
    from Rev 186 to Rev 187
    Reverse comparison

Rev 186 → Rev 187

/or1200_sprs.v
320,8 → 320,7
(epcr & {32{epcr_sel}}) |
(eear & {32{eear_sel}}) |
`ifdef OR1200_FPU_IMPLEMENTED
({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} &
{32{read_spr & fpcsr_sel}}) |
({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} & {32{fpcsr_sel}}) |
`endif
({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
 

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