URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/or1200/rtl/verilog
- from Rev 259 to Rev 260
- ↔ Reverse comparison
Rev 259 → Rev 260
/or1200_fpu.v
282,8 → 282,6
// Instantiate FPU modules |
// |
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`ifdef OR1200_FPU_ARITH_FPU100 |
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// FPU 100 VHDL core from OpenCores.org: http://opencores.org/project,fpu100 |
// Used only for add,sub,mul,div |
or1200_fpu_arith fpu_arith |
306,8 → 304,6
.snan_o(snan) |
); |
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`endif // `ifdef OR1200_FPU_ARITH_FPU100 |
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// Logic for detection of signaling NaN on input |
// signaling NaN: exponent is 8hff, [22] is zero, rest of fract is non-zero |
// quiet NaN: exponent is 8hff, [22] is 1 |