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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/or1200/rtl/verilog
    from Rev 352 to Rev 353
    ↔ Reverse comparison
  •

Rev 352 → Rev 353

/or1200_sprs.v
99,9 → 99,9
input ex_spr_read; // l.mfspr in EX
input ex_spr_write; // l.mtspr in EX
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
input [width-1:0] epcr; // EPCR0
input [width-1:0] eear; // EEAR0
input [`OR1200_SR_WIDTH-1:0] esr; // ESR0
input [width-1:0] epcr /* verilator public */; // EPCR0
input [width-1:0] eear /* verilator public */; // EEAR0
input [`OR1200_SR_WIDTH-1:0] esr /* verilator public */; // ESR0
input except_started; // Exception was started
output [width-1:0] to_wbmux; // For l.mfspr
output epcr_we; // EPCR0 write enable
110,7 → 110,7
output pc_we; // PC write enable
output sr_we; // Write enable SR
output [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR
output [`OR1200_SR_WIDTH-1:0] sr; // SR
output [`OR1200_SR_WIDTH-1:0] sr /* verilator public */; // SR
input [31:0] spr_dat_cfgr; // Data from CFGR
input [31:0] spr_dat_rf; // Data from RF
input [31:0] spr_dat_npc; // Data from NPC
358,6 → 358,34
always @(sr_reg or sr_reg_bit_eph_muxed)
sr = {sr_reg[`OR1200_SR_WIDTH-1:`OR1200_SR_WIDTH-2], sr_reg_bit_eph_muxed, sr_reg[`OR1200_SR_WIDTH-4:0]};
 
`ifdef verilator
// Function to access various sprs (for Verilator). Have to hide this from
// simulator, since functions with no inputs are not allowed in IEEE
// 1364-2001.
 
function [31:0] get_sr;
// verilator public
get_sr = sr;
endfunction // get_sr
 
function [31:0] get_epcr;
// verilator public
get_epcr = epcr;
endfunction // get_epcr
 
function [31:0] get_eear;
// verilator public
get_eear = eear;
endfunction // get_eear
 
function [31:0] get_esr;
// verilator public
get_esr = esr;
endfunction // get_esr
 
`endif
 
//
// MTSPR/MFSPR interface
//
/or1200_ctrl.v
79,8 → 79,8
input clk;
input rst;
input id_freeze;
input ex_freeze;
input wb_freeze;
input ex_freeze /* verilator public */;
input wb_freeze /* verilator public */;
output if_flushpipe;
output id_flushpipe;
output ex_flushpipe;
90,7 → 90,7
input abort_mvspr ;
input [31:0] if_insn;
output [31:0] id_insn;
output [31:0] ex_insn;
output [31:0] ex_insn /* verilator public */;
output [`OR1200_BRANCHOP_WIDTH-1:0] ex_branch_op;
output [`OR1200_BRANCHOP_WIDTH-1:0] id_branch_op;
input ex_branch_taken;
155,9 → 155,9
wire ex_macrc_op;
`endif
reg [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
reg [31:0] id_insn;
reg [31:0] ex_insn;
reg [31:0] wb_insn;
reg [31:0] id_insn /* verilator public */;
reg [31:0] ex_insn /* verilator public */;
reg [31:0] wb_insn /* verilator public */;
reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
reg [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
373,6 → 373,35
//
assign rfe = (id_branch_op == `OR1200_BRANCHOP_RFE) | (ex_branch_op == `OR1200_BRANCHOP_RFE);
 
`ifdef verilator
// Function to access wb_insn (for Verilator). Have to hide this from
// simulator, since functions with no inputs are not allowed in IEEE
// 1364-2001.
function [31:0] get_wb_insn;
// verilator public
get_wb_insn = wb_insn;
endfunction // get_wb_insn
 
// Function to access id_insn (for Verilator). Have to hide this from
// simulator, since functions with no inputs are not allowed in IEEE
// 1364-2001.
function [31:0] get_id_insn;
// verilator public
get_id_insn = id_insn;
endfunction // get_id_insn
 
// Function to access ex_insn (for Verilator). Have to hide this from
// simulator, since functions with no inputs are not allowed in IEEE
// 1364-2001.
function [31:0] get_ex_insn;
// verilator public
get_ex_insn = ex_insn;
endfunction // get_ex_insn
`endif
 
//
// Generation of sel_a
//
861,15 → 890,15
 
// l.maci
`OR1200_OR32_MACI:
id_mac_op <= `OR1200_MACOP_MAC;
id_mac_op = `OR1200_MACOP_MAC;
 
// l.mac, l.msb
`OR1200_OR32_MACMSB:
id_mac_op <= id_insn[2:0];
id_mac_op = id_insn[2:0];
 
// Illegal and OR1200 unsupported instructions
default:
id_mac_op <= `OR1200_MACOP_NOP;
id_mac_op = `OR1200_MACOP_NOP;
 
endcase
end
1068,39 → 1097,39
 
// l.lwz
`OR1200_OR32_LWZ:
id_lsu_op <= `OR1200_LSUOP_LWZ;
id_lsu_op = `OR1200_LSUOP_LWZ;
 
// l.lbz
`OR1200_OR32_LBZ:
id_lsu_op <= `OR1200_LSUOP_LBZ;
id_lsu_op = `OR1200_LSUOP_LBZ;
 
// l.lbs
`OR1200_OR32_LBS:
id_lsu_op <= `OR1200_LSUOP_LBS;
id_lsu_op = `OR1200_LSUOP_LBS;
 
// l.lhz
`OR1200_OR32_LHZ:
id_lsu_op <= `OR1200_LSUOP_LHZ;
id_lsu_op = `OR1200_LSUOP_LHZ;
 
// l.lhs
`OR1200_OR32_LHS:
id_lsu_op <= `OR1200_LSUOP_LHS;
id_lsu_op = `OR1200_LSUOP_LHS;
 
// l.sw
`OR1200_OR32_SW:
id_lsu_op <= `OR1200_LSUOP_SW;
id_lsu_op = `OR1200_LSUOP_SW;
 
// l.sb
`OR1200_OR32_SB:
id_lsu_op <= `OR1200_LSUOP_SB;
id_lsu_op = `OR1200_LSUOP_SB;
 
// l.sh
`OR1200_OR32_SH:
id_lsu_op <= `OR1200_LSUOP_SH;
id_lsu_op = `OR1200_LSUOP_SH;
 
// Non load/store instructions
default:
id_lsu_op <= `OR1200_LSUOP_NOP;
id_lsu_op = `OR1200_LSUOP_NOP;
 
endcase
end
/or1200_except.v
151,12 → 151,12
//
// Internal regs and wires
//
reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
reg [31:0] id_pc;
reg [`OR1200_EXCEPT_WIDTH-1:0] except_type /* verilator public */;
reg [31:0] id_pc /* verilator public */;
reg id_pc_val;
reg [31:0] ex_pc;
reg [31:0] ex_pc /* verilator public */;
reg ex_pc_val;
reg [31:0] wb_pc;
reg [31:0] wb_pc /* verilator public */;
reg [31:0] dl_pc;
reg [31:0] epcr;
reg [31:0] eear;
166,10 → 166,11
reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
reg extend_flush;
reg extend_flush_last;
reg ex_dslot;
reg ex_dslot /* verilator public */;
reg delayed1_ex_dslot;
reg delayed2_ex_dslot;
wire except_started;
wire except_flushpipe /* verilator public */;
reg [2:0] delayed_iee;
reg [2:0] delayed_tee;
wire int_pending;
293,6 → 294,41
end
end
 
`ifdef verilator
// Function to access wb_pc (for Verilator). Have to hide this from
// simulator, since functions with no inputs are not allowed in IEEE
// 1364-2001.
function [31:0] get_wb_pc;
// verilator public
get_wb_pc = wb_pc;
endfunction // get_wb_pc
 
// Function to access id_pc (for Verilator). Have to hide this from
// simulator, since functions with no inputs are not allowed in IEEE
// 1364-2001.
function [31:0] get_id_pc;
// verilator public
get_id_pc = id_pc;
endfunction // get_id_pc
 
// Function to access ex_pc (for Verilator). Have to hide this from
// simulator, since functions with no inputs are not allowed in IEEE
// 1364-2001.
function [31:0] get_ex_pc;
// verilator public
get_ex_pc = ex_pc;
endfunction // get_ex_pc
// Function to access except_type[3:0] (for Verilator). Have to hide this from
// simulator, since functions with no inputs are not allowed in IEEE
// 1364-2001.
function [3:0] get_except_type;
// verilator public
get_except_type = except_type;
endfunction // get_except_type
`endif
//
// PC and Exception flags pipelines
//

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