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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/or1200/rtl
- from Rev 364 to Rev 401
- ↔ Reverse comparison
Rev 364 → Rev 401
/verilog/or1200_defines.v
345,6 → 345,11
`define OR1200_IMPL_ALU_COMP2 |
|
// |
// Implement Find First/Last '1' |
// |
`define OR1200_IMPL_ALU_FFL1 |
|
// |
// Implement multiplier |
// |
// By default multiplier is implemented |
466,7 → 471,15
`define OR1200_ALUOP_MTSR 4'd14 |
`define OR1200_ALUOP_MFSR 4'd15 |
`define OR1200_ALUOP_CMOV 4'd14 |
`define OR1200_ALUOP_FF1 4'd15 |
`define OR1200_ALUOP_FFL1 4'd15 |
|
|
// ALU instructions second opcode field (previously multicycle field in |
// machine word) |
`define OR1200_ALUOP2_POS 9:8 |
`define OR1200_ALUOP2_WIDTH 2 |
|
|
// |
// MACOPs |
// |
625,9 → 638,6
// SHROT_OP position in machine word |
`define OR1200_SHROTOP_POS 7:6 |
|
// ALU instructions multicycle field in machine word |
`define OR1200_ALUMCYC_POS 9:8 |
|
// |
// Instruction opcode groups (basic) |
// |
/verilog/or1200_alu.v
53,7 → 53,7
|
module or1200_alu( |
a, b, mult_mac_result, macrc_op, |
alu_op, shrot_op, comp_op, |
alu_op, alu_op2, shrot_op, comp_op, |
cust5_op, cust5_limm, |
result, flagforw, flag_we, |
cyforw, cy_we, carry, flag |
69,6 → 69,7
input [width-1:0] mult_mac_result; |
input macrc_op; |
input [`OR1200_ALUOP_WIDTH-1:0] alu_op; |
input [`OR1200_ALUOP2_WIDTH-1:0] alu_op2; |
input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op; |
input [`OR1200_COMPOP_WIDTH-1:0] comp_op; |
input [4:0] cust5_op; |
142,7 → 143,8
// |
// Central part of the ALU |
// |
always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result or flag or result_cust5 or carry |
always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op |
or shifted_rotated or mult_mac_result or flag or result_cust5 or carry |
`ifdef OR1200_IMPL_ADDC |
or result_csum |
`endif |
152,9 → 154,22
`else |
casez (alu_op) // synopsys full_case parallel_case |
`endif |
`OR1200_ALUOP_FF1: begin |
`ifdef OR1200_IMPL_ALU_FFL1 |
`OR1200_ALUOP_FFL1: begin |
`ifdef OR1200_CASE_DEFAULT |
casez (alu_op2) // synopsys parallel_case |
`else |
casez (alu_op2) // synopsys full_case parallel_case |
`endif |
0: begin // FF1 |
result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0; |
end |
end |
default: begin // FL1 |
result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ; |
end |
endcase // casez (alu_op2) |
end // case: `OR1200_ALUOP_FFL1 |
`endif |
`OR1200_ALUOP_CUST5 : begin |
result = result_cust5; |
end |
/verilog/or1200_cpu.v
221,6 → 221,7
wire [dw-1:2] id_branch_addrtarget; |
wire [dw-1:2] ex_branch_addrtarget; |
wire [`OR1200_ALUOP_WIDTH-1:0] alu_op; |
wire [`OR1200_ALUOP2_WIDTH-1:0] alu_op2; |
wire [`OR1200_SHROTOP_WIDTH-1:0] shrot_op; |
wire [`OR1200_COMPOP_WIDTH-1:0] comp_op; |
wire [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op; |
484,6 → 485,7
.rf_rda(rf_rda), |
.rf_rdb(rf_rdb), |
.alu_op(alu_op), |
.alu_op2(alu_op2), |
.mac_op(mac_op), |
.shrot_op(shrot_op), |
.comp_op(comp_op), |
582,6 → 584,7
.mult_mac_result(mult_mac_result), |
.macrc_op(ex_macrc_op), |
.alu_op(alu_op), |
.alu_op2(alu_op2), |
.shrot_op(shrot_op), |
.comp_op(comp_op), |
.cust5_op(cust5_op), |
/verilog/or1200_ctrl.v
62,8 → 62,8
wb_flushpipe, |
id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr, |
id_branch_op, ex_branch_op, ex_branch_taken, pc_we, |
rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op, |
rf_addrw, rfwb_op, fpu_op, |
rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, alu_op2, mac_op, shrot_op, |
comp_op, rf_addrw, rfwb_op, fpu_op, |
wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a, |
sel_b, id_lsu_op, |
cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt, |
100,6 → 100,7
output rf_rda; |
output rf_rdb; |
output [`OR1200_ALUOP_WIDTH-1:0] alu_op; |
output [`OR1200_ALUOP2_WIDTH-1:0] alu_op2; |
output [`OR1200_MACOP_WIDTH-1:0] mac_op; |
output [`OR1200_SHROTOP_WIDTH-1:0] shrot_op; |
output [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op; |
144,6 → 145,7
reg [`OR1200_BRANCHOP_WIDTH-1:0] id_branch_op; |
reg [`OR1200_BRANCHOP_WIDTH-1:0] ex_branch_op; |
reg [`OR1200_ALUOP_WIDTH-1:0] alu_op; |
reg [`OR1200_ALUOP2_WIDTH-1:0] alu_op2; |
wire if_maci_op; |
`ifdef OR1200_MAC_IMPLEMENTED |
reg [`OR1200_MACOP_WIDTH-1:0] ex_mac_op; |
750,6 → 752,11
| (id_insn[3:0] == `OR1200_ALUOP_ADDC) |
`endif |
|
`ifdef OR1200_IMPL_ALU_FFL1 |
`else |
| (id_insn[3:0] == `OR1200_ALUOP_FFL1) |
`endif |
|
`ifdef OR1200_IMPL_ALU_ROTATE |
`else |
| ((id_insn[3:0] == `OR1200_ALUOP_SHROT) & |
844,7 → 851,22
end |
end |
|
|
// |
// Decode of alu_op2 (field of bits 9:8) |
// |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
alu_op2 <= 0; |
else if (!ex_freeze & id_freeze | ex_flushpipe) |
alu_op2 <= 0; |
else if (!ex_freeze) begin |
alu_op2 <= id_insn[`OR1200_ALUOP2_POS]; |
end |
end |
|
|
// |
// Decode of spr_read, spr_write |
// |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |