URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/or1ksim/cache
- from Rev 538 to Rev 556
- ↔ Reverse comparison
Rev 538 → Rev 556
/dcache-model.c
39,8 → 39,8
#include "abstract.h" |
#include "stats.h" |
#include "misc.h" |
#include "pcu.h" |
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/* Data cache */ |
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struct dc_set |
185,6 → 185,10
dc[set].way[minway].lru = config.dc.ustates - 1; |
runtime.sim.mem_cycles += config.dc.load_missdelay; |
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if (config.pcu.enabled) |
pcu_count_event(SPR_PCMR_DCM); |
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tmp = |
dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2]; |
if (width == 4) |
304,6 → 308,10
dc[set].way[i].lru--; |
dc[set].way[minway].lru = config.dc.ustates - 1; |
runtime.sim.mem_cycles += config.dc.store_missdelay; |
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if (config.pcu.enabled) |
pcu_count_event(SPR_PCMR_DCM); |
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} |
} |
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/icache-model.c
45,8 → 45,8
#include "misc.h" |
#include "stats.h" |
#include "sim-cmd.h" |
#include "pcu.h" |
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#define MAX_IC_SETS 1024 |
#define MAX_IC_WAYS 32 |
#define MIN_IC_BLOCK_SIZE 16 |
175,6 → 175,11
} |
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runtime.sim.mem_cycles += ic->missdelay; |
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if (config.pcu.enabled) |
pcu_count_event(SPR_PCMR_ICM); |
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return *(uint32_t *) & ic->mem[way | (reload_addr & ic->block_offset_mask)]; |
} |
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