URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/or1ksim/cpu/or32
- from Rev 107 to Rev 112
- ↔ Reverse comparison
Rev 107 → Rev 112
/insnset.c
35,18 → 35,43
temp3 = (orreg_t)PARAM1; |
temp1 = temp2 + temp3; |
SET_PARAM0(temp1); |
SET_OV_FLAG_FN (temp1); |
if (ARITH_SET_FLAG) { |
if(!temp1) |
cpu_state.sprs[SPR_SR] |= SPR_SR_F; |
else |
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; |
} |
|
/* Set overflow if two negative values gave a positive sum, or if two |
positive values gave a negative sum. Otherwise clear it */ |
if ((((long int) temp2 < 0) && |
((long int) temp3 < 0) && |
((long int) temp1 >= 0)) || |
(((long int) temp2 >= 0) && |
((long int) temp3 >= 0) && |
((long int) temp1 < 0))) |
{ |
cpu_state.sprs[SPR_SR] |= SPR_SR_OV; |
} |
else |
{ |
cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV; |
} |
|
/* Set the carry flag if (as unsigned values) the result is smaller than |
either operand (if it smaller than one, it will be smaller than both, so |
we need only test one). */ |
if ((uorreg_t) temp1 < (uorreg_t) temp2) |
cpu_state.sprs[SPR_SR] |= SPR_SR_CY; |
{ |
cpu_state.sprs[SPR_SR] |= SPR_SR_CY; |
} |
else |
cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY; |
{ |
cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY; |
} |
|
/* Trigger a range exception if the overflow flag is set and the SR[OVE] bit |
is set. */ |
if (((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) == SPR_SR_OVE) && |
((cpu_state.sprs[SPR_SR] & SPR_SR_OV) == SPR_SR_OV)) |
{ |
except_handle (EXCEPT_RANGE, cpu_state.pc); |
} |
|
temp4 = temp1; |
if (temp4 == temp1) |
or1k_mstats.byteadd++; |
213,7 → 238,7
if (temp3) |
temp1 = temp2 / temp3; |
else { |
mtspr (SPR_SR, SPR_SR_CY | mfspr (SPR_SR)); /* Div by zero sets carry */ |
cpu_state.sprs[SPR_SR] |= SPR_SR_CY; /* Div by zero sets carry */ |
except_handle (EXCEPT_RANGE, cpu_state.pc); |
return; |
} |
228,7 → 253,7
if (temp3) |
temp1 = temp2 / temp3; |
else { |
mtspr (SPR_SR, SPR_SR_CY | mfspr (SPR_SR)); /* Div by zero sets carry */ |
cpu_state.sprs[SPR_SR] |= SPR_SR_CY; /* Div by zero sets carry */ |
except_handle(EXCEPT_RANGE, cpu_state.pc); |
return; |
} |