URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/or1ksim/cpu
- from Rev 121 to Rev 122
- ↔ Reverse comparison
Rev 121 → Rev 122
/or32/or32.c
350,8 → 350,8
EF (l_srl), 0, it_shift}, |
{"l.srai", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 10LL LLLL", |
EF (l_sra), 0, it_shift}, |
{"l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL", EFI, |
0, it_shift}, |
{"l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL", |
EF (l_ror), 0, it_shift}, |
|
{"l.sfeqi", "rA,I", "10 0xF 00000 AAAAA IIII IIII IIII IIII", |
EF (l_sfeq), OR32_W_FLAG, it_compare}, |
473,8 → 473,8
EF (l_srl), 0, it_shift}, |
{"l.sra", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0x8", |
EF (l_sra), 0, it_shift}, |
{"l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8", EFI, |
0, it_shift}, |
{"l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8", |
EF (l_ror), 0, it_shift}, |
{"l.div", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x9", |
EF (l_div), 0, it_arith}, |
{"l.divu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xA", |
/or32/insnset.c
417,6 → 417,12
SET_PARAM0(temp1); |
/* runtime.sim.cycles += 2; */ |
} |
INSTRUCTION (l_ror) { |
uorreg_t temp1; |
temp1 = PARAM1 >> (PARAM2 & 0x1f); |
temp1 |= PARAM1 << (32 - (PARAM2 & 0x1f)); |
SET_PARAM0(temp1); |
} |
INSTRUCTION (l_bf) { |
if (config.bpb.enabled) { |
int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0; |