URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/or1ksim/peripheral
- from Rev 346 to Rev 385
- ↔ Reverse comparison
Rev 346 → Rev 385
/mc.c
354,23 → 354,41
{ |
struct mc *mc = dat; |
|
if (val.int_val > 0xf) |
if (val.int_val > MC_POC_VALID) |
{ |
fprintf (stderr, "Warning: memory controller PoC > 4 bits: truncated\n"); |
fprintf (stderr, "Warning: memory controller PoC > 0x%lx: truncated\n", |
MC_POC_VALID); |
} |
|
mc->poc = val.int_val & 0xf; |
mc->poc = val.int_val & MC_POC_VALID; |
|
} /* mc_poc() */ |
|
|
/*---------------------------------------------------------------------------*/ |
/*!Set the index of this memory controller. |
|
This identifies which chip enable value will select this memory |
controller. Truncate if the value is too large with a warning. |
|
@param[in] val The value to use |
@param[in] dat The config data structure */ |
/*---------------------------------------------------------------------------*/ |
static void |
mc_index (union param_val val, void *dat) |
{ |
struct mc *mc = dat; |
mc->index = val.int_val; |
|
if (val.int_val > MC_CE_VALID) |
{ |
fprintf (stderr, "Warning: memory controller index > 0x%x: truncated.\n", |
MC_CE_VALID); |
} |
|
mc->index = val.int_val & MC_CE_VALID; |
} |
|
|
/*---------------------------------------------------------------------------*/ |
/*!Initialize a new memory controller configuration |
|
/mc-defines.h
61,6 → 61,7
#define MC_CSC_MEMTYPE_ASYNC 2 |
#define MC_CSC_MEMTYPE_SYNC 3 |
|
#define MC_CE_VALID (N_CE - 1) |
#define MC_CSR_VALID 0xFF000703LU |
#define MC_POC_VALID 0x0000000FLU |
#define MC_BA_MASK_VALID 0x000003FFLU |