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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/or1ksim/peripheral
    from Rev 418 to Rev 428
    ↔ Reverse comparison
  •

Rev 418 → Rev 428

/Makefile.in
1,4 → 1,4
# Makefile.in generated by automake 1.11.1 from Makefile.am.
# Makefile.in generated by automake 1.11 from Makefile.am.
# @configure_input@
 
# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
400,7 → 400,7
# (which will cause the Makefiles to be regenerated when you run `make');
# (2) otherwise, pass the desired values on the `make' command line.
$(RECURSIVE_TARGETS):
@fail= failcom='exit 1'; \
@failcom='exit 1'; \
for f in x $$MAKEFLAGS; do \
case $$f in \
*=* | --[!k]*);; \
425,7 → 425,7
fi; test -z "$$fail"
 
$(RECURSIVE_CLEAN_TARGETS):
@fail= failcom='exit 1'; \
@failcom='exit 1'; \
for f in x $$MAKEFLAGS; do \
case $$f in \
*=* | --[!k]*);; \
/channels/Makefile.in
1,4 → 1,4
# Makefile.in generated by automake 1.11.1 from Makefile.am.
# Makefile.in generated by automake 1.11 from Makefile.am.
# @configure_input@
 
# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
/eth.c
81,6 → 81,9
/* VAPI ID */
unsigned long base_vapi_id;
 
/* Ethernet PHY address */
unsigned long phy_addr;
 
/* RX and TX file names and handles */
char *rxfile, *txfile;
int txfd;
169,6 → 172,7
static void eth_skip_rx_file (struct eth_device *, off_t);
static void eth_rx_next_packet (struct eth_device *);
static void eth_write_tx_bd_num (struct eth_device *, unsigned long value);
static void eth_miim_trans (void *dat);
/* ========================================================================= */
/* TX LOGIC */
/*---------------------------------------------------------------------------*/
710,7 → 714,9
}
 
/* Set registers to default values */
/* Zero all registers */
memset (&(eth->regs), 0, sizeof (eth->regs));
/* Set those with non-zero reset defaults */
eth->regs.moder = 0x0000A000;
eth->regs.ipgt = 0x00000012;
eth->regs.ipgr1 = 0x0000000C;
731,6 → 737,7
vapi_install_multi_handler (eth->base_vapi_id, ETH_NUM_VAPI_IDS,
eth_vapi_read, dat);
}
}
}
 
811,6 → 818,7
case ETH_MIITX_DATA:
return eth->regs.miitx_data;
case ETH_MIIRX_DATA:
/*printf("or1ksim: read MIIM RX: 0x%x\n",(int)eth->regs.miirx_data);*/
return eth->regs.miirx_data;
case ETH_MIISTATUS:
return eth->regs.miistatus;
903,6 → 911,8
return;
case ETH_MIICOMMAND:
eth->regs.miicommand = value;
/* Perform MIIM transaction, if required */
eth_miim_trans(dat);
return;
case ETH_MIIADDRESS:
eth->regs.miiaddress = value;
911,11 → 921,16
eth->regs.miitx_data = value;
return;
case ETH_MIIRX_DATA:
/* Register is R/O
eth->regs.miirx_data = value;
*/
return;
case ETH_MIISTATUS:
/* Register is R/O
eth->regs.miistatus = value;
*/
return;
 
case ETH_MAC_ADDR0:
eth->mac_address[0] = value & 0xFF;
eth->mac_address[1] = (value >> 8) & 0xFF;
1233,7 → 1248,147
eth->base_vapi_id = val.int_val;
}
 
 
static void
eth_phy_addr (union param_val val,
void *dat)
{
struct eth_device *eth = dat;
eth->phy_addr = val.int_val & ETH_MIIADDR_FIAD_MASK;
}
 
 
/*---------------------------------------------------------------------------*/
/*!Emulate MIIM transaction to ethernet PHY
 
@param[in] dat The config data structure */
/*---------------------------------------------------------------------------*/
static void
eth_miim_trans (void *dat)
{
struct eth_device *eth = dat;
switch (eth->regs.miicommand)
{
case ((1 << ETH_MIICOMM_WCDATA_OFFSET)):
/* Perhaps something to emulate here later, but for now do nothing */
break;
case ((1 << ETH_MIICOMM_RSTAT_OFFSET)):
 
printf("or1ksim: eth_miim_trans: phy %d\n",(int)
((eth->regs.miiaddress >> ETH_MIIADDR_FIAD_OFFSET)&
ETH_MIIADDR_FIAD_MASK));
printf("or1ksim: eth_miim_trans: reg %d\n",(int)
((eth->regs.miiaddress >> ETH_MIIADDR_RGAD_OFFSET)&
ETH_MIIADDR_RGAD_MASK));
 
/*First check if it's the correct PHY to address */
if (((eth->regs.miiaddress >> ETH_MIIADDR_FIAD_OFFSET)&
ETH_MIIADDR_FIAD_MASK) == eth->phy_addr)
{
/* Correct PHY - now switch based on the register address in the PHY*/
switch ((eth->regs.miiaddress >> ETH_MIIADDR_RGAD_OFFSET)&
ETH_MIIADDR_RGAD_MASK)
{
case MII_BMCR:
eth->regs.miirx_data = BMCR_FULLDPLX;
break;
case MII_BMSR:
eth->regs.miirx_data = BMSR_LSTATUS | BMSR_ANEGCOMPLETE |
BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL;
break;
case MII_PHYSID1:
eth->regs.miirx_data = 0x22; /* Micrel PHYID */
break;
case MII_PHYSID2:
eth->regs.miirx_data = 0x1613; /* Micrel PHYID */
break;
case MII_ADVERTISE:
eth->regs.miirx_data = 0;
break;
case MII_LPA:
eth->regs.miirx_data = LPA_DUPLEX | LPA_100;
break;
case MII_EXPANSION:
eth->regs.miirx_data = 0;
break;
case MII_CTRL1000:
eth->regs.miirx_data = 0;
break;
case MII_STAT1000:
eth->regs.miirx_data = 0;
break;
case MII_ESTATUS:
eth->regs.miirx_data = 0;
break;
case MII_DCOUNTER:
eth->regs.miirx_data = 0;
break;
case MII_FCSCOUNTER:
eth->regs.miirx_data = 0;
break;
case MII_NWAYTEST:
eth->regs.miirx_data = 0;
break;
case MII_RERRCOUNTER:
eth->regs.miirx_data = 0;
break;
case MII_SREVISION:
eth->regs.miirx_data = 0;
break;
case MII_RESV1:
eth->regs.miirx_data = 0;
break;
case MII_LBRERROR:
eth->regs.miirx_data = 0;
break;
case MII_PHYADDR:
eth->regs.miirx_data = eth->phy_addr;
break;
case MII_RESV2:
eth->regs.miirx_data = 0;
break;
case MII_TPISTATUS:
eth->regs.miirx_data = 0;
break;
case MII_NCONFIG:
eth->regs.miirx_data = 0;
break;
default:
eth->regs.miirx_data = 0xffff;
break;
}
}
else
eth->regs.miirx_data = 0xffff; /* PHY doesn't exist, read all 1's */
break;
 
case ((1 << ETH_MIICOMM_SCANS_OFFSET)):
/* From MAC's datasheet:
A host initiates the Scan Status Operation by asserting the SCANSTAT
signal. The MIIM performs a continuous read operation of the PHY
Status register. The PHY is selected by the FIAD[4:0] signals. The
link status LinkFail signal is asserted/deasserted by the MIIM module
and reflects the link status bit of the PHY Status register. The
signal NVALID is used for qualifying the validity of the LinkFail
signals and the status data PRSD[15:0]. These signals are invalid
until the first scan status operation ends. During the scan status
operation, the BUSY signal is asserted until the last read is
performed (the scan status operation is stopped).
 
So for now - do nothing, leave link status indicator as permanently
with link.
*/
 
break;
default:
break;
}
 
}
 
/*---------------------------------------------------------------------------*/
/*!Initialize a new Ethernet configuration
 
ALL parameters are set explicitly to default values. */
1262,6 → 1417,7
new->txfile = strdup ("eth_tx");
new->sockif = strdup ("or1ksim_eth");
new->base_vapi_id = 0;
new->phy_addr = 0;
 
return new;
}
1317,6 → 1473,7
reg_config_param (sec, "txfile", PARAMT_STR, eth_txfile);
reg_config_param (sec, "sockif", PARAMT_STR, eth_sockif);
reg_config_param (sec, "vapi_id", PARAMT_INT, eth_vapi_id);
reg_config_param (sec, "phy_addr", PARAMT_INT, eth_phy_addr);
 
} /* reg_ethernet_sec() */
 
/eth.h
128,10 → 128,9
#define ETH_CMODER_PASSALL_OFFSET 0
 
/* Field definitions for MIIMODER */
#define ETH_MIIMODER_MRST_OFFSET 9
#define ETH_MIIMODER_NOPRE_OFFSET 8
#define ETH_MIIMODER_CLKDIV_OFFSET 0
#define ETH_MIIMODER_CLKDIV_WIDTH 8
#define ETH_MIIMODER_CLKDIV_MASK 0xff
 
/* Field definitions for MIICOMMAND */
#define ETH_MIICOMM_WCDATA_OFFSET 2
140,9 → 139,9
 
/* Field definitions for MIIADDRESS */
#define ETH_MIIADDR_RGAD_OFFSET 8
#define ETH_MIIADDR_RGAD_WIDTH 5
#define ETH_MIIADDR_RGAD_MASK 0x1f
#define ETH_MIIADDR_FIAD_OFFSET 0
#define ETH_MIIADDR_FIAD_WIDTH 5
#define ETH_MIIADDR_FIAD_MASK 0x1f
 
/* Field definitions for MIISTATUS */
#define ETH_MIISTAT_NVALID_OFFSET 1
274,4 → 273,136
/* Prototypes for external use */
extern void reg_ethernet_sec ();
 
 
/* Defines taken from linux-2.6.36/include/linux/mii.h for PHY register IF */
 
#define MII_BMCR 0x00 /* Basic mode control register */
#define MII_BMSR 0x01 /* Basic mode status register */
#define MII_PHYSID1 0x02 /* PHYS ID 1 */
#define MII_PHYSID2 0x03 /* PHYS ID 2 */
#define MII_ADVERTISE 0x04 /* Advertisement control reg */
#define MII_LPA 0x05 /* Link partner ability reg */
#define MII_EXPANSION 0x06 /* Expansion register */
#define MII_CTRL1000 0x09 /* 1000BASE-T control */
#define MII_STAT1000 0x0a /* 1000BASE-T status */
#define MII_ESTATUS 0x0f /* Extended Status */
#define MII_DCOUNTER 0x12 /* Disconnect counter */
#define MII_FCSCOUNTER 0x13 /* False carrier counter */
#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
#define MII_RERRCOUNTER 0x15 /* Receive error counter */
#define MII_SREVISION 0x16 /* Silicon revision */
#define MII_RESV1 0x17 /* Reserved... */
#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
#define MII_PHYADDR 0x19 /* PHY address */
#define MII_RESV2 0x1a /* Reserved... */
#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
#define MII_NCONFIG 0x1c /* Network interface config */
 
/* Basic mode control register. */
#define BMCR_RESV 0x003f /* Unused... */
#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
#define BMCR_CTST 0x0080 /* Collision test */
#define BMCR_FULLDPLX 0x0100 /* Full duplex */
#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
#define BMCR_RESET 0x8000 /* Reset the DP83840 */
 
/* Basic mode status register. */
#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
#define BMSR_JCD 0x0002 /* Jabber detected */
#define BMSR_LSTATUS 0x0004 /* Link status */
#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
#define BMSR_RFAULT 0x0010 /* Remote fault detected */
#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
#define BMSR_RESV 0x00c0 /* Unused... */
#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
 
/* Advertisement control register. */
#define ADVERTISE_SLCT 0x001f /* Selector bits */
#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
#define ADVERTISE_RESV 0x1000 /* Unused... */
#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
 
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
ADVERTISE_CSMA)
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
ADVERTISE_100HALF | ADVERTISE_100FULL)
 
/* Link partner ability register. */
#define LPA_SLCT 0x001f /* Same as advertise selector */
#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
#define LPA_PAUSE_CAP 0x0400 /* Can pause */
#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
#define LPA_RESV 0x1000 /* Unused... */
#define LPA_RFAULT 0x2000 /* Link partner faulted */
#define LPA_LPACK 0x4000 /* Link partner acked us */
#define LPA_NPAGE 0x8000 /* Next page bit */
 
#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
 
/* Expansion register for auto-negotiation. */
#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
#define EXPANSION_RESV 0xffe0 /* Unused... */
 
#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
 
/* N-way test register. */
#define NWAYTEST_RESV1 0x00ff /* Unused... */
#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
#define NWAYTEST_RESV2 0xfe00 /* Unused... */
 
/* 1000BASE-T Control register */
#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
 
/* 1000BASE-T Status register */
#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
 
/* Flow control flags */
#define FLOW_CTRL_TX 0x01
#define FLOW_CTRL_RX 0x02
 
 
 
#endif /* ETH__H */

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