URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/or1ksim/testsuite/or1ksim.tests
- from Rev 538 to Rev 556
- ↔ Reverse comparison
Rev 538 → Rev 556
/Makefile.in
245,7 → 245,8
mul.exp \ |
mycompress.exp \ |
testfloat.exp \ |
tick.exp |
tick.exp \ |
pcu.exp |
|
all: all-am |
|
/pcu.cfg
0,0 → 1,128
/* pcu.cfg -- Or1ksim configuration script file when using perf. counters unit |
|
Copyright (C) 2001, Marko Mlinar <markom@opencores.org> |
Copyright (C) 2010 Embecosm Limited |
|
Contributor Marko Mlinar <markom@opencores.org> |
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
Contributor Julius Baxter <julius@opencores.org> |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify it |
under the terms of the GNU General Public License as published by the Free |
Software Foundation; either version 3 of the License, or (at your option) |
any later version. |
|
This program is distributed in the hope that it will be useful, but WITHOUT |
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
more details. |
|
You should have received a copy of the GNU General Public License along |
with this program. If not, see <http: www.gnu.org/licenses/>. */ |
|
section memory |
/*random_seed = 12345 |
type = random*/ |
pattern = 0x00 |
type = unknown /* Fastest */ |
|
name = "RAM" |
ce = 1 |
mc = 0 |
baseaddr = 0x00000000 |
size = 0x00200000 |
delayr = 1 |
delayw = 1 |
end |
|
section immu |
enabled = 1 |
nsets = 64 |
nways = 1 |
ustates = 2 |
pagesize = 8192 |
end |
|
section dmmu |
enabled = 1 |
nsets = 64 |
nways = 1 |
ustates = 2 |
pagesize = 8192 |
end |
|
section ic |
enabled = 1 |
nsets = 256 |
nways = 1 |
ustates = 2 |
blocksize = 16 |
end |
|
section dc |
enabled = 1 |
nsets = 256 |
nways = 1 |
ustates = 2 |
blocksize = 16 |
end |
|
section cpu |
ver = 0x12 |
rev = 0x0001 |
/* upr = */ |
superscalar = 0 |
hazards = 0 |
dependstats = 0 |
hardfloat = 1 |
end |
|
section pcu |
enabled = 1 |
end |
|
section debug |
/* enabled = 1 |
rsp_enabled = 1 |
rsp_port = 51000 */ |
end |
|
section sim |
debug = 0 |
profile = 0 |
prof_fn = "sim.profile" |
|
exe_log = 0 |
exe_log_type = software |
exe_log_fn = "executed.log" |
end |
|
section dma |
baseaddr = 0xB8000000 |
irq = 4 |
end |
|
section ethernet |
enabled = 0 |
baseaddr = 0x92000000 |
irq = 4 |
rtx_type = "file" |
end |
|
section VAPI |
enabled = 0 |
server_port = 9998 |
end |
|
section fb |
enabled = 1 |
baseaddr = 0x97000000 |
refresh_rate = 10000 |
filename = "primary" |
end |
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section kbd |
enabled = 0 |
end |
/pcu.exp
0,0 → 1,83
# pcu.exp - performance counters unit |
|
# Contributor Julius Baxter <julius@opencores.org> |
|
# This file is part of OpenRISC 1000 Architectural Simulator. |
|
# This program is free software; you can redistribute it and/or modify it |
# under the terms of the GNU General Public License as published by the Free |
# Software Foundation; either version 3 of the License, or (at your option) |
# any later version. |
|
# This program is distributed in the hope that it will be useful, but WITHOUT |
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
# more details. |
|
# You should have received a copy of the GNU General Public License along |
# with this program. If not, see <http:#www.gnu.org/licenses/>. */ |
|
# ----------------------------------------------------------------------------- |
# This code is commented throughout for use with Doxygen. |
# ----------------------------------------------------------------------------- |
|
|
# Run the l.ext test |
run_or1ksim "pcu" \ |
[list "report(0x00000046);" \ |
"report(0x00000000);" \ |
"report(0x00000001);" \ |
"report(0x00000002);" \ |
"report(0x00000003);" \ |
"report(0x00000004);" \ |
"report(0x00000005);" \ |
"report(0x00000006);" \ |
"report(0x00000007);" \ |
"report(0x0000004a);" \ |
"report(0x00000000);" \ |
"report(0x00000001);" \ |
"report(0x00000002);" \ |
"report(0x00000003);" \ |
"report(0x00000004);" \ |
"report(0x00000005);" \ |
"report(0x00000006);" \ |
"report(0x00000007);" \ |
"report(0x00002006);" \ |
"report(0x00000000);" \ |
"report(0x00000001);" \ |
"report(0x00000002);" \ |
"report(0x00000003);" \ |
"report(0x00000004);" \ |
"report(0x00000005);" \ |
"report(0x00000006);" \ |
"report(0x00000007);" \ |
"report(0x00001006);" \ |
"report(0x00000000);" \ |
"report(0x00000001);" \ |
"report(0x00000002);" \ |
"report(0x00000003);" \ |
"report(0x00000004);" \ |
"report(0x00000005);" \ |
"report(0x00000006);" \ |
"report(0x00000007);" \ |
"report(0x00000106);" \ |
"report(0x00000000);" \ |
"report(0x00000001);" \ |
"report(0x00000002);" \ |
"report(0x00000003);" \ |
"report(0x00000004);" \ |
"report(0x00000005);" \ |
"report(0x00000006);" \ |
"report(0x00000007);" \ |
"report(0x00000086);" \ |
"report(0x00000000);" \ |
"report(0x00000001);" \ |
"report(0x00000002);" \ |
"report(0x00000003);" \ |
"report(0x00000004);" \ |
"report(0x00000005);" \ |
"report(0x00000006);" \ |
"report(0x00000007);" \ |
"!report(0xdeaddead);" \ |
"!exit(0)"] \ |
"pcu.cfg" "pcu/pcu" |
/mmu.exp
23,7 → 23,11
# This code is commented throughout for use with Doxygen. |
# ----------------------------------------------------------------------------- |
|
# Allow up to 30 seconds to run this |
set old_timeout $timeout |
set timeout 30 |
|
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# Run the MMU test |
run_or1ksim "mmu" \ |
[list "DTLB translation tests OK" \ |
/Makefile.am
61,4 → 61,5
mul.exp \ |
mycompress.exp \ |
testfloat.exp \ |
tick.exp |
tick.exp \ |
pcu.exp |