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- This comparison shows the changes necessary to convert path
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/except
- from Rev 784 to Rev 787
- ↔ Reverse comparison
Rev 784 → Rev 787
/except.S
58,6 → 58,11
reset_vector: |
l.nop |
l.nop |
|
// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero, |
// and indeed it is not when simulating the or1200 Verilog core. |
l.andi r0,r0,0x0 |
|
l.addi r4,r0,0x0 |
l.addi r5,r0,0x0 |
l.addi r6,r0,0x0 |