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  • This comparison shows the changes necessary to convert path
    /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext
    from Rev 784 to Rev 787
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Rev 784 → Rev 787

/ext.S
121,6 → 121,10
 
.section .text
start_test:
// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
// and indeed it is not when simulating the or1200 Verilog core.
l.andi r0,r0,0x0
/* Test l.extbs */
CHECK_HIGH3_CLEAR(l.extbs, 0x7f)
CHECK_HIGH3_CLEAR(l.extbs, 0x53)

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