URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/support
- from Rev 483 to Rev 538
- ↔ Reverse comparison
Rev 483 → Rev 538
/Makefile.in
1,4 → 1,4
# Makefile.in generated by automake 1.11.1 from Makefile.am. |
# Makefile.in generated by automake 1.11 from Makefile.am. |
# @configure_input@ |
|
# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
/spr-defs.h
1,4 → 1,4
/* ipc.h. Microkernel IPC header for Or1ksim |
/* spr-defs.h - Special purpose registers definitions file |
|
Copyright (C) 2000 Damjan Lampret |
Copyright (C) 2008, 2010 Embecosm Limited |
100,6 → 100,7
|
/* Data MMU group */ |
#define SPR_DMMUCR (SPRGROUP_DMMU + 0) |
#define SPR_DTLBEIR (SPRGROUP_DMMU + 2) |
#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) |
#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) |
#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) |
107,6 → 108,7
|
/* Instruction MMU group */ |
#define SPR_IMMUCR (SPRGROUP_IMMU + 0) |
#define SPR_ITLBEIR (SPRGROUP_IMMU + 2) |
#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) |
#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100) |
#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100) |
153,6 → 155,7
|
/* PIC group */ |
#define SPR_PICMR (SPRGROUP_PIC + 0) |
#define SPR_PICPR (SPRGROUP_PIC + 1) |
#define SPR_PICSR (SPRGROUP_PIC + 2) |
|
/* Tick Timer group */ |
280,7 → 283,7
#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ |
#define SPR_DTLBMR_CID 0x0000003c /* Context ID */ |
#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */ |
#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */ |
#define SPR_DTLBMR_VPN 0xffffe000 /* Virtual Page Number */ |
|
/* |
* Bit definitions for the Data TLB Translate Register |
296,7 → 299,7
#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */ |
#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */ |
#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */ |
#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */ |
#define SPR_DTLBTR_PPN 0xffffe000 /* Physical Page Number */ |
|
/* |
* Bit definitions for the Instruction TLB Match Register |
306,7 → 309,7
#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ |
#define SPR_ITLBMR_CID 0x0000003c /* Context ID */ |
#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */ |
#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */ |
#define SPR_ITLBMR_VPN 0xffffe000 /* Virtual Page Number */ |
|
/* |
* Bit definitions for the Instruction TLB Translate Register |
320,7 → 323,7
#define SPR_ITLBTR_D 0x00000020 /* Dirty */ |
#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */ |
#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */ |
#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */ |
#define SPR_ITLBTR_PPN 0xffffe000 /* Physical Page Number */ |
|
/* |
* Bit definitions for Data Cache Control register |
568,6 → 571,12
#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */ |
|
/* |
* Bit definitions for PICPR |
* |
*/ |
#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */ |
|
/* |
* Bit definitions for PICSR |
* |
*/ |
577,8 → 586,8
* Bit definitions for Tick Timer Control Register |
* |
*/ |
#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */ |
#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD |
#define SPR_TTCR_CNT 0xffffffff /* Count, time period */ |
#define SPR_TTMR_TP 0x0fffffff /* Time period */ |
#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */ |
#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */ |
#define SPR_TTMR_DI 0x00000000 /* Disabled */ |