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- This comparison shows the changes necessary to convert path
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos
- from Rev 784 to Rev 787
- ↔ Reverse comparison
Rev 784 → Rev 787
/except-or32.S
200,6 → 200,10
.org 0x100 |
reset_vector: |
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// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero, |
// and indeed it is not when simulating the or1200 Verilog core. |
l.andi r0,r0,0x0 |
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l.movhi r3,hi(MC_BASE_ADDR) |
l.ori r3,r3,lo(MC_BASE_ADDR) |
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