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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/or1ksim/testsuite/test-code-or1k
    from Rev 784 to Rev 787
    ↔ Reverse comparison
  •

Rev 784 → Rev 787

/configure
1,6 → 1,6
#! /bin/sh
# Guess values for system-dependent variables and create Makefiles.
# Generated by GNU Autoconf 2.68 for or1ksim-testsuite 2012-03-21.
# Generated by GNU Autoconf 2.68 for or1ksim-testsuite 2012-03-23.
#
# Report bugs to <openrisc@opencores.org>.
#
570,8 → 570,8
# Identity of this package.
PACKAGE_NAME='or1ksim-testsuite'
PACKAGE_TARNAME='or1ksim-testsuite'
PACKAGE_VERSION='2012-03-21'
PACKAGE_STRING='or1ksim-testsuite 2012-03-21'
PACKAGE_VERSION='2012-03-23'
PACKAGE_STRING='or1ksim-testsuite 2012-03-23'
PACKAGE_BUGREPORT='openrisc@opencores.org'
PACKAGE_URL=''
 
1300,7 → 1300,7
# Omit some internal or obsolete options to make the list less imposing.
# This message is too long to be a string in the A/UX 3.1 sh.
cat <<_ACEOF
\`configure' configures or1ksim-testsuite 2012-03-21 to adapt to many kinds of systems.
\`configure' configures or1ksim-testsuite 2012-03-23 to adapt to many kinds of systems.
 
Usage: $0 [OPTION]... [VAR=VALUE]...
 
1371,7 → 1371,7
 
if test -n "$ac_init_help"; then
case $ac_init_help in
short | recursive ) echo "Configuration of or1ksim-testsuite 2012-03-21:";;
short | recursive ) echo "Configuration of or1ksim-testsuite 2012-03-23:";;
esac
cat <<\_ACEOF
 
1480,7 → 1480,7
test -n "$ac_init_help" && exit $ac_status
if $ac_init_version; then
cat <<\_ACEOF
or1ksim-testsuite configure 2012-03-21
or1ksim-testsuite configure 2012-03-23
generated by GNU Autoconf 2.68
 
Copyright (C) 2010 Free Software Foundation, Inc.
1903,7 → 1903,7
This file contains any messages produced by compilers while
running configure, to aid debugging if configure makes a mistake.
 
It was created by or1ksim-testsuite $as_me 2012-03-21, which was
It was created by or1ksim-testsuite $as_me 2012-03-23, which was
generated by GNU Autoconf 2.68. Invocation command line was
 
$ $0 $@
11104,7 → 11104,7
 
# Define the identity of the package.
PACKAGE='or1ksim-testsuite'
VERSION='2012-03-21'
VERSION='2012-03-23'
 
 
cat >>confdefs.h <<_ACEOF
12556,7 → 12556,7
# report actual input values of CONFIG_FILES etc. instead of their
# values after options handling.
ac_log="
This file was extended by or1ksim-testsuite $as_me 2012-03-21, which was
This file was extended by or1ksim-testsuite $as_me 2012-03-23, which was
generated by GNU Autoconf 2.68. Invocation command line was
 
CONFIG_FILES = $CONFIG_FILES
12622,7 → 12622,7
cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
ac_cs_version="\\
or1ksim-testsuite config.status 2012-03-21
or1ksim-testsuite config.status 2012-03-23
configured by $0, generated by GNU Autoconf 2.68,
with options \\"\$ac_cs_config\\"
 
/mc-common/except-mc.S
55,6 → 55,11
reset_vector:
l.nop
l.nop
// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
// and indeed it is not when simulating the or1200 Verilog core.
l.andi r0,r0,0x0
l.addi r4,r0,0x0
l.addi r5,r0,0x0
l.addi r6,r0,0x0
/except/except.S
58,6 → 58,11
reset_vector:
l.nop
l.nop
// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
// and indeed it is not when simulating the or1200 Verilog core.
l.andi r0,r0,0x0
l.addi r4,r0,0x0
l.addi r5,r0,0x0
l.addi r6,r0,0x0
/ext/ext.S
121,6 → 121,10
 
.section .text
start_test:
// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
// and indeed it is not when simulating the or1200 Verilog core.
l.andi r0,r0,0x0
/* Test l.extbs */
CHECK_HIGH3_CLEAR(l.extbs, 0x7f)
CHECK_HIGH3_CLEAR(l.extbs, 0x53)
/cache/cache-asm.S
49,6 → 49,10
 
.org 0x100
reset_vector:
// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
// and indeed it is not when simulating the or1200 Verilog core.
l.andi r0,r0,0x0
l.addi r2,r0,0x0
l.addi r3,r0,0x0
l.addi r4,r0,0x0
/configure.ac
23,7 → 23,7
# Configure script for the OpenRISC 1000 simulator test suite OR1K code
# directory. This uses a different tool chain, so has its own configuration
# script. Process this file with autoconf to produce a configure script.
AC_INIT([or1ksim-testsuite], [2012-03-21], [openrisc@opencores.org])
AC_INIT([or1ksim-testsuite], [2012-03-23], [openrisc@opencores.org])
AC_CONFIG_MACRO_DIR([m4])
 
AC_PROG_LIBTOOL
/fp/fp.S
353,6 → 353,10
 
.org 0x100
_reset:
// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
// and indeed it is not when simulating the or1200 Verilog core.
l.andi r0,r0,0x0
l.movhi r1,hi(_stack) /* Set up the stack */
l.ori r1,r1,lo(_stack)
/inst-set-test/inst-set-test.S
72,6 → 72,10
.org 0x100
.global _reset
_reset:
// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
// and indeed it is not when simulating the or1200 Verilog core.
l.andi r0,r0,0x0
l.movhi r1,hi(_stack) /* Set up the stack */
l.ori r1,r1,lo(_stack)
 
/ChangeLog
1,8 → 1,20
2012-03-23 Jeremy Bennett <jeremy.bennett@embecosm.com>
 
Patch from R Diez <rdiezmail-openrisc@yahoo.de>
 
* cache/cache-asm.S, cfg/cfg.S, except-test/except-test-s.S,
* except/except.S, ext/ext.S, flag/flag.S, fp/fp.S,
* inst-set-test/inst-set-test.S, int-test/int-test.S,
* mc-common/except-mc.S, uos/except-or32.S: Clear R0 on
start-up. There is no guarantee that R0 is hardwired to zero, and
indeed it is not when simulating the or1200 Verilog core.
* configure: Regenerated.
* configure.ac: Updated version.
 
2012-03-21 Jeremy Bennett <jeremy.bennett@embecosm.com>
 
* configure: Regenerated.
* configure.ac: Updated version. Added AM_SILENT_RULES for nicer
builds.
* configure.ac: Updated version.
 
2011-08-15 Jeremy Bennett <jeremy.bennett@embecosm.com>
 
/cfg/cfg.S
30,6 → 30,10
.section .except,"ax"
.org 0x100
_reset:
// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
// and indeed it is not when simulating the or1200 Verilog core.
l.andi r0,r0,0x0
l.addi r1,r0,0x7f00
l.movhi r2,hi(_main)
l.ori r2,r2,lo(_main)
/except-test/except-test-s.S
77,6 → 77,11
reset_vector:
l.nop
l.nop
 
// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
// and indeed it is not when simulating the or1200 Verilog core.
l.andi r0,r0,0x0
l.addi r2,r0,0x0
l.addi r3,r0,0x0
l.addi r4,r0,0x0
/uos/except-or32.S
200,6 → 200,10
.org 0x100
reset_vector:
 
// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
// and indeed it is not when simulating the or1200 Verilog core.
l.andi r0,r0,0x0
 
l.movhi r3,hi(MC_BASE_ADDR)
l.ori r3,r3,lo(MC_BASE_ADDR)
/int-test/int-test.S
58,6 → 58,10
.org 0x100
 
_reset_vector:
// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
// and indeed it is not when simulating the or1200 Verilog core.
l.andi r0,r0,0x0
l.addi r2,r0,0x0
l.addi r3,r0,0x0
l.addi r4,r0,0x0
/flag/flag.S
36,6 → 36,11
.org 0x100
_reset:
l.nop
// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
// and indeed it is not when simulating the or1200 Verilog core.
l.andi r0,r0,0x0
l.movhi r10,0x8000
l.addi r11,r0,-1
l.addi r12,r0,2

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