URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/or1ksim/testsuite
- from Rev 122 to Rev 123
- ↔ Reverse comparison
Rev 122 → Rev 123
/test-code-or1k/inst-set-test/Makefile.in
61,7 → 61,7
check_PROGRAMS = is-add-test$(EXEEXT) is-div-test$(EXEEXT) \ |
is-find-test$(EXEEXT) is-jump-test$(EXEEXT) \ |
is-lws-test$(EXEEXT) is-mac-test$(EXEEXT) is-mul-test$(EXEEXT) \ |
is-ror-test$(EXEEXT) $(am__EXEEXT_1) |
is-ror-test$(EXEEXT) is-spr-test$(EXEEXT) $(am__EXEEXT_1) |
subdir = inst-set-test |
DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in |
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 |
134,6 → 134,12
is_ror_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ |
$(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ |
$(is_ror_test_LDFLAGS) $(LDFLAGS) -o $@ |
am_is_spr_test_OBJECTS = is-spr-test.$(OBJEXT) |
is_spr_test_OBJECTS = $(am_is_spr_test_OBJECTS) |
is_spr_test_DEPENDENCIES = inst-set-test.lo |
is_spr_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ |
$(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ |
$(is_spr_test_LDFLAGS) $(LDFLAGS) -o $@ |
DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir) |
depcomp = $(SHELL) $(top_srcdir)/../../depcomp |
am__depfiles_maybe = depfiles |
156,13 → 162,14
$(is_add_test_SOURCES) $(is_div_test_SOURCES) \ |
$(is_find_test_SOURCES) $(is_jump_test_SOURCES) \ |
$(is_lws_test_SOURCES) $(is_mac_test_SOURCES) \ |
$(is_mul_test_SOURCES) $(is_ror_test_SOURCES) |
$(is_mul_test_SOURCES) $(is_ror_test_SOURCES) \ |
$(is_spr_test_SOURCES) |
DIST_SOURCES = $(libinst_set_test_la_SOURCES) \ |
$(inst_set_test_old_SOURCES) $(is_add_test_SOURCES) \ |
$(is_div_test_SOURCES) $(is_find_test_SOURCES) \ |
$(is_jump_test_SOURCES) $(is_lws_test_SOURCES) \ |
$(is_mac_test_SOURCES) $(is_mul_test_SOURCES) \ |
$(is_ror_test_SOURCES) |
$(is_ror_test_SOURCES) $(is_spr_test_SOURCES) |
ETAGS = etags |
CTAGS = ctags |
DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) |
333,7 → 340,12
|
is_ror_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld |
is_ror_test_LDADD = inst-set-test.lo |
is_spr_test_SOURCES = inst-set-test.h \ |
is-spr-test.S |
|
is_spr_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld |
is_spr_test_LDADD = inst-set-test.lo |
|
# The old test which builds with warnings and runs with errors |
inst_set_test_old_SOURCES = inst-set-test-old.c |
inst_set_test_old_LDFLAGS = -T$(srcdir)/../default.ld |
421,6 → 433,9
is-ror-test$(EXEEXT): $(is_ror_test_OBJECTS) $(is_ror_test_DEPENDENCIES) |
@rm -f is-ror-test$(EXEEXT) |
$(is_ror_test_LINK) $(is_ror_test_OBJECTS) $(is_ror_test_LDADD) $(LIBS) |
is-spr-test$(EXEEXT): $(is_spr_test_OBJECTS) $(is_spr_test_DEPENDENCIES) |
@rm -f is-spr-test$(EXEEXT) |
$(is_spr_test_LINK) $(is_spr_test_OBJECTS) $(is_spr_test_LDADD) $(LIBS) |
|
mostlyclean-compile: |
-rm -f *.$(OBJEXT) |
438,6 → 453,7
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-mac-test.Po@am__quote@ |
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-mul-test.Po@am__quote@ |
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-ror-test.Po@am__quote@ |
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-spr-test.Po@am__quote@ |
|
.S.o: |
@am__fastdepCCAS_TRUE@ $(CPPASCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $< |
/test-code-or1k/inst-set-test/Makefile.am
49,6 → 49,7
is-mac-test \ |
is-mul-test \ |
is-ror-test \ |
is-spr-test \ |
$(INST_SET_TEST_OLD) |
|
# The new instruction set tests. |
92,6 → 93,11
is_ror_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld |
is_ror_test_LDADD = inst-set-test.lo |
|
is_spr_test_SOURCES = inst-set-test.h \ |
is-spr-test.S |
is_spr_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld |
is_spr_test_LDADD = inst-set-test.lo |
|
# The old test which builds with warnings and runs with errors |
inst_set_test_old_SOURCES = inst-set-test-old.c |
|
/test-code-or1k/inst-set-test/is-spr-test.S
0,0 → 1,212
/* is-spr-test.S. l.mfspr and l.mtspr instruction test of Or1ksim |
* |
* Copyright (C) 1999-2006 OpenCores |
* Copyright (C) 2010 Embecosm Limited |
* |
* Contributors various OpenCores participants |
* Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
* |
* This file is part of OpenRISC 1000 Architectural Simulator. |
* |
* This program is free software; you can redistribute it and/or modify it |
* under the terms of the GNU General Public License as published by the Free |
* Software Foundation; either version 3 of the License, or (at your option) |
* any later version. |
* |
* This program is distributed in the hope that it will be useful, but WITHOUT |
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
* more details. |
* |
* You should have received a copy of the GNU General Public License along |
* with this program. If not, see <http: www.gnu.org/licenses/>. |
*/ |
|
/* ---------------------------------------------------------------------------- |
* Coding conventions are described in inst-set-test.S |
* ------------------------------------------------------------------------- */ |
|
/* ---------------------------------------------------------------------------- |
* Test coverage |
* |
* The l.mfspr and l.mtspr should OR the immdediate operand with the register |
* to determine the SPR address, not add it (Bug 1779). |
* |
* Having fixed the problem, this is (in good software engineering style), a |
* regresison test to go with the fix. |
* |
* This is not a comprehensive test of either instruction (yet). |
* |
* Of course what is really needed is a comprehensive instruction test... |
* ------------------------------------------------------------------------- */ |
|
|
#include "inst-set-test.h" |
|
/* ---------------------------------------------------------------------------- |
* A macro to carry out a test of l.mfspr |
* |
* MACLO is used as the SPR, since it can be read and cleared using l.macrc |
* and can be set using l.maci. op1 and op2 should be chosen to address this |
* register. |
* |
* The value placed in the register is entirely arbitrary - we use 0xdeadbeef. |
* |
* Arguments |
* op1: First l.mfspr operand value |
* op2: Second l.mfspr operand value |
* ------------------------------------------------------------------------- */ |
#define TEST_MFSPR(op1, op2) \ |
l.macrc r2 ;\ |
LOAD_CONST (r2,0xdeadbeef) ;\ |
l.maci r2,1 ;\ |
;\ |
l.mfspr r3,r0,SPR_SR ;\ |
LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ |
l.and r3,r3,r2 /* Clear flags */ ;\ |
l.mtspr r0,r3,SPR_SR ;\ |
;\ |
LOAD_CONST (r5,op1) /* First operand in register */ ;\ |
l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ |
50: l.mfspr r4,r5,op2 ;\ |
l.mfspr r2,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ |
PUSH (r2) /* Save EPCR for later */ ;\ |
PUSH (r4) /* Save result for later */ ;\ |
;\ |
PUTS (" l.mfspr 0x") ;\ |
PUTH (op1) ;\ |
PUTS (" | 0x") ;\ |
PUTHH (op2) ;\ |
PUTS (": ") ;\ |
POP (r4) ;\ |
CHECK_RES1 (r4, 0xdeadbeef) ;\ |
;\ |
LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\ |
l.and r2,r2,r4 ;\ |
l.sfeq r2,r4 ;\ |
l.bnf 51f ;\ |
;\ |
PUTS (" - exception triggered: TRUE\n") ;\ |
l.j 52f ;\ |
l.nop ;\ |
;\ |
51: PUTS (" - exception triggered: FALSE\n") ;\ |
52: |
|
|
/* ---------------------------------------------------------------------------- |
* A macro to carry out a test of l.mtspr |
* |
* MACLO is used as the SPR, since it can be read and cleared using l.macrc. |
* op1 and op2 should be chosen to address this register. |
* |
* The value placed in the register is entirely arbitrary - we use 0xdeadbeef. |
* |
* Arguments |
* op1: First l.mfspr operand value |
* op2: Second l.mfspr operand value |
* ------------------------------------------------------------------------- */ |
#define TEST_MTSPR(op1, op2) \ |
l.macrc r2 ;\ |
;\ |
l.mfspr r3,r0,SPR_SR ;\ |
LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ |
l.and r3,r3,r2 /* Clear flags */ ;\ |
l.mtspr r0,r3,SPR_SR ;\ |
;\ |
LOAD_CONST (r5,op1) /* First operand in register */ ;\ |
LOAD_CONST (r4,0xdeadbeef) /* First operand in register */ ;\ |
l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ |
50: l.mtspr r5,r4,op2 ;\ |
l.mfspr r2,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ |
PUSH (r2) /* Save EPCR for later */ ;\ |
l.macrc r4 ;\ |
PUSH (r4) /* Save result for later */ ;\ |
;\ |
PUTS (" l.mtspr 0x") ;\ |
PUTH (op1) ;\ |
PUTS (" | 0x") ;\ |
PUTHH (op2) ;\ |
PUTS (": ") ;\ |
POP (r4) ;\ |
CHECK_RES1 (r4, 0xdeadbeef) ;\ |
;\ |
LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\ |
l.and r2,r2,r4 ;\ |
l.sfeq r2,r4 ;\ |
l.bnf 51f ;\ |
;\ |
PUTS (" - exception triggered: TRUE\n") ;\ |
l.j 52f ;\ |
l.nop ;\ |
;\ |
51: PUTS (" - exception triggered: FALSE\n") ;\ |
52: |
|
|
/* ---------------------------------------------------------------------------- |
* Start of code |
* ------------------------------------------------------------------------- */ |
.section .text |
.global _start |
_start: |
|
/* ---------------------------------------------------------------------------- |
* Test of move from SPR, l.mfspr |
* |
* MACLO (0x2801) is always used as the test register. |
* ------------------------------------------------------------------------- */ |
_mfspr: |
LOAD_STR (r3, "l.mfspr\n") |
l.jal _puts |
l.nop |
|
/* Move a test value using zero in the register */ |
TEST_MFSPR (0x00000000, 0x2801) |
|
/* Move a test value using zero as the constant */ |
TEST_MFSPR (0x00002801, 0x0000) |
|
/* Move a test value using non-zero in both register and constant. |
Some of these values will not give the correct result if OR rather |
than ADD is used to determine the SPR address */ |
TEST_MFSPR (0x00002801, 0x2801) |
TEST_MFSPR (0x00000801, 0x2000) |
TEST_MFSPR (0x00002000, 0x0801) |
TEST_MFSPR (0x00002801, 0x0001) |
TEST_MFSPR (0x00000800, 0x2801) |
|
/* ---------------------------------------------------------------------------- |
* Test of move to SPR, l.mtspr |
* |
* MACLO (0x2801) is always used as the test register. |
* ------------------------------------------------------------------------- */ |
_mtspr: |
LOAD_STR (r3, "l.mtspr\n") |
l.jal _puts |
l.nop |
|
/* Move a test value using zero in the register */ |
TEST_MTSPR (0x00000000, 0x2801) |
|
/* Move a test value using zero as the constant */ |
TEST_MTSPR (0x00002801, 0x0000) |
|
/* Move a test value using non-zero in both register and constant. |
Some of these values will not give the correct result if OR rather |
than ADD is used to determine the SPR address */ |
TEST_MTSPR (0x00002801, 0x2801) |
TEST_MTSPR (0x00000801, 0x2000) |
TEST_MTSPR (0x00002000, 0x0801) |
TEST_MTSPR (0x00002801, 0x0001) |
TEST_MTSPR (0x00000800, 0x2801) |
|
/* ---------------------------------------------------------------------------- |
* All done |
* ------------------------------------------------------------------------- */ |
_exit: |
LOAD_STR (r3, "Test completed\n") |
l.jal _puts |
l.nop |
|
TEST_EXIT |
test-code-or1k/inst-set-test/is-spr-test.S
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: test-code-or1k/ChangeLog
===================================================================
--- test-code-or1k/ChangeLog (revision 122)
+++ test-code-or1k/ChangeLog (revision 123)
@@ -1,3 +1,8 @@
+2010-06-15 Jeremy Bennett
+ * inst-set-test/is-spr-test.S: Created.
+ * inst-set-test/Makefile.am: Updated for new tests
+ * inst-set-test/Makefile.in: Regenerated.
+
2010-06-14 Jeremy Bennett
* inst-set-test/inst-set-test.S : Just output
identification string.
Index: or1ksim.tests/inst-set-test.exp
===================================================================
--- or1ksim.tests/inst-set-test.exp (revision 122)
+++ or1ksim.tests/inst-set-test.exp (revision 123)
@@ -909,3 +909,40 @@
"!report(0xdeaddead);" \
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-ror-test"
+
+# Run the l.mfspr and l.mtspr test
+run_or1ksim "spr-test" \
+ [list "!l.mfspr" \
+ " l.mfspr 0x00000000 | 0x2801: OK" \
+ " - exception triggered: FALSE" \
+ " l.mfspr 0x00002801 | 0x0000: OK" \
+ " - exception triggered: FALSE" \
+ " l.mfspr 0x00002801 | 0x2801: OK" \
+ " - exception triggered: FALSE" \
+ " l.mfspr 0x00000801 | 0x2000: OK" \
+ " - exception triggered: FALSE" \
+ " l.mfspr 0x00002000 | 0x0801: OK" \
+ " - exception triggered: FALSE" \
+ " l.mfspr 0x00002801 | 0x0001: OK" \
+ " - exception triggered: FALSE" \
+ " l.mfspr 0x00000800 | 0x2801: OK" \
+ " - exception triggered: FALSE" \
+ "!l.mtspr" \
+ " l.mtspr 0x00000000 | 0x2801: OK" \
+ " - exception triggered: FALSE" \
+ " l.mtspr 0x00002801 | 0x0000: OK" \
+ " - exception triggered: FALSE" \
+ " l.mtspr 0x00002801 | 0x2801: OK" \
+ " - exception triggered: FALSE" \
+ " l.mtspr 0x00000801 | 0x2000: OK" \
+ " - exception triggered: FALSE" \
+ " l.mtspr 0x00002000 | 0x0801: OK" \
+ " - exception triggered: FALSE" \
+ " l.mtspr 0x00002801 | 0x0001: OK" \
+ " - exception triggered: FALSE" \
+ " l.mtspr 0x00000800 | 0x2801: OK" \
+ " - exception triggered: FALSE" \
+ "!Test completed" \
+ "!report(0xdeaddead);" \
+ "!exit(0)"] \
+ "inst-set-test.cfg" "inst-set-test/is-spr-test"
Index: ChangeLog
===================================================================
--- ChangeLog (revision 122)
+++ ChangeLog (revision 123)
@@ -1,3 +1,7 @@
+2010-06-15 Jeremy Bennett
+ * or1ksim.tests/inst-set-test.exp: Added tests for l.mfspr and
+ l.mtspr instructions.
+
2010-06-14 Jeremy Bennett
* or1ksim.tests/inst-set-test.exp: Modified output from RANGE
exception. Added tests for jump and rotate right instructions.
Index: README
===================================================================
--- README (revision 122)
+++ README (revision 123)
@@ -12,8 +12,8 @@
Tests are provided for the standalone simulator (or1ksim) and for the library
(libsim.a).
-At the time of writing a total of 1,829 tests compile, run and pass. That
-figure is broken down into 1,565 tests of the standalone simulator and 264
+At the time of writing a total of 1,857 tests compile, run and pass. That
+figure is broken down into 1,593 tests of the standalone simulator and 264
tests of the library
Configuration and make files are provided for further test programs. These
@@ -46,7 +46,7 @@
Working tests
=============
-A total of 1,565 tests of standalone Or1ksim:
+A total of 1,593 tests of standalone Or1ksim:
basic: 8 tests of a wide range of instructions and registers.
cache: 5 tests of the Or1ksim cache modeling
@@ -74,6 +74,7 @@
is-mac-test: 189 tests of the MAC instructions (Bugs 1773, 1777).
is-mul-test: 186 tests of the l.mul* instructions (Bug 1774).
is-ror-test: 36 tests of the l.ror and l.rori instructions (Bug 1778).
+ is-spr-test: 28 tests of the l.mfspr and l.mtspr instructions (Bug 1779).
mem-test: 16 tests of simple memory access.
mmu: 110 tests of the MMU.
mul: 5 tests of the multiply functionality.