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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

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  • This comparison shows the changes necessary to convert path
    /openrisc/trunk/or1ksim/testsuite
    from Rev 123 to Rev 124
    Reverse comparison

Rev 123 → Rev 124

/test-code-or1k/inst-set-test/is-sub-test.S
0,0 → 1,241
/* is-sub-test.S. l.sub instruction test of Or1ksim
*
* Copyright (C) 1999-2006 OpenCores
* Copyright (C) 2010 Embecosm Limited
*
* Contributors various OpenCores participants
* Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
*
* This file is part of OpenRISC 1000 Architectural Simulator.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 3 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program. If not, see <http: www.gnu.org/licenses/>.
*/
 
/* ----------------------------------------------------------------------------
* Coding conventions are described in inst-set-test.S
* ------------------------------------------------------------------------- */
 
/* ----------------------------------------------------------------------------
* Test coverage
*
* The l.sub instruction should set the carry and overflow flags.
*
* Problems in this area were reported in Bugs 1782, 1783 and 1784. Having
* fixed the problem, this is (in good software engineering style), a
* regression test to go with the fix.
*
* This is not a comprehensive test of any instruction (yet).
*
* Of course what is really needed is a comprehensive instruction test...
* ------------------------------------------------------------------------- */
 
 
#include "inst-set-test.h"
 
/* ----------------------------------------------------------------------------
* A macro to carry out a test of subtraction in registers
*
*
* Arguments
* set_flags: Flags to set in the SR
* clr_flags: Flags to clear in the SR
* op1: First operand value
* op2: Second operand value
* res: Expected result
* cy: Expected carry flag
* ov: Expected overflow flag
* ------------------------------------------------------------------------- */
#define TEST_SUB(set_flags, clr_flags, op1, op2, res, cy, ov) \
l.mfspr r3,r0,SPR_SR ;\
LOAD_CONST (r2, set_flags) /* Set flags */ ;\
l.or r3,r3,r2 ;\
LOAD_CONST (r2, ~clr_flags) /* Clear flags */ ;\
l.and r3,r3,r2 ;\
l.mtspr r0,r3,SPR_SR ;\
;\
LOAD_CONST (r5,op1) /* Load numbers to subtract */ ;\
LOAD_CONST (r6,op2) ;\
l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\
50: l.sub r4,r5,r6 ;\
l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\
l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\
PUSH (r5) /* Save EPCR for later */ ;\
PUSH (r2) ;\
PUSH (r4) /* Save result for later */ ;\
;\
PUTS (" 0x") ;\
PUTH (op1) ;\
PUTS (" - 0x") ;\
PUTH (op2) ;\
PUTS (" = 0x") ;\
PUTH (res) ;\
PUTS (": ") ;\
POP (r4) ;\
CHECK_RES1 (r4, res) ;\
;\
POP(r2) /* Retrieve SR */ ;\
PUSH(r2) ;\
LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
CHECK_FLAG ("- carry flag set: ", cy) ;\
;\
POP(r2) /* Retrieve SR */ ;\
LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
CHECK_FLAG ("- overflow flag set: ", ov) ;\
;\
POP (r2) /* Retrieve EPCR */ ;\
LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
l.bnf 53f ;\
;\
PUTS (" - exception triggered: TRUE\n") ;\
l.j 54f ;\
l.nop ;\
;\
53: PUTS (" - exception triggered: FALSE\n") ;\
54:
 
 
/* ----------------------------------------------------------------------------
* Start of code
* ------------------------------------------------------------------------- */
.section .text
.global _start
_start:
l.mfspr r3,r0,SPR_SR
LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */
l.and r3,r3,r2
l.mtspr r0,r3,SPR_SR
LOAD_STR (r3, " ** OVE flag cleared **\n")
l.jal _puts
l.nop
 
/* ----------------------------------------------------------------------------
* Test of subtract signed, l.sub
* ------------------------------------------------------------------------- */
_sub:
LOAD_STR (r3, "l.sub\n")
l.jal _puts
l.nop
 
/* Subtract two small positive numbers. Sets the carry, but never the
overflow if the result is negative. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x00000003, 0x00000002, 0x00000001,
FALSE, FALSE)
 
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x00000001, 0x00000002, 0xffffffff,
TRUE, FALSE)
 
/* Check carry in is ignored. */
TEST_SUB (SPR_SR_CY, SPR_SR_OV,
0x00000003, 0x00000002, 0x00000001,
FALSE, FALSE)
 
/* Subtract two small negative numbers. Sets the carry flag if the
result is negative, but never the overflow flag. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0xfffffffd, 0xfffffffe, 0xffffffff,
TRUE, FALSE)
 
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0xffffffff, 0xfffffffe, 0x00000001,
FALSE, FALSE)
 
/* Subtract two quite large positive numbers. Should set neither the
overflow nor the carry flag. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x7fffffff, 0x3fffffff, 0x40000000,
FALSE, FALSE)
 
/* Subtract two quite large negative numbers. Should set neither the
overflow nor the carry flag. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x40000000, 0x40000000, 0x00000000,
FALSE, FALSE)
 
/* Subtract two large positive numbers with a negative result. Should
set the carry, but not the overflow flag. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x3fffffff, 0x40000000, 0xffffffff,
TRUE, FALSE)
 
/* Subtract two large negative numbers with a positive result. Should
set niether the carry nor the overflow flag. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x40000000, 0x3fffffff, 0x00000001,
FALSE, FALSE)
 
/* Subtract a large positive from a large negative number. Should set
overflow but not the carry flag. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x80000000, 0x7fffffff, 0x00000001,
FALSE, TRUE)
 
/* Subtract a large negative from a large positive number. Should set
both the overflow and carry flags. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x7fffffff, 0x80000000, 0xffffffff,
TRUE, TRUE)
 
/* Check that range exceptions are triggered */
l.mfspr r3,r0,SPR_SR
LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */
l.or r3,r3,r2
l.mtspr r0,r3,SPR_SR
LOAD_STR (r3, " ** OVE flag set **\n")
l.jal _puts
l.nop
 
/* Check that an overflow alone causes a RANGE Exception. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x80000000, 0x7fffffff, 0x00000001,
FALSE, TRUE)
 
/* Check that a carry alone does not cause a RANGE Exception. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x3fffffff, 0x40000000, 0xffffffff,
TRUE, FALSE)
 
/* Check that carry and overflow together cause an exception. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x7fffffff, 0x80000000, 0xffffffff,
TRUE, TRUE)
 
/* Finished checking range exceptions */
l.mfspr r3,r0,SPR_SR
LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */
l.and r3,r3,r2
l.mtspr r0,r3,SPR_SR
LOAD_STR (r3, " ** OVE flag cleared **\n")
l.jal _puts
l.nop
 
/* ----------------------------------------------------------------------------
* All done
* ------------------------------------------------------------------------- */
_exit:
LOAD_STR (r3, "Test completed\n")
l.jal _puts
l.nop
 
TEST_EXIT
test-code-or1k/inst-set-test/is-sub-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: test-code-or1k/inst-set-test/Makefile.in =================================================================== --- test-code-or1k/inst-set-test/Makefile.in (revision 123) +++ test-code-or1k/inst-set-test/Makefile.in (revision 124) @@ -58,10 +58,13 @@ POST_UNINSTALL = : build_triplet = @build@ host_triplet = @host@ -check_PROGRAMS = is-add-test$(EXEEXT) is-div-test$(EXEEXT) \ - is-find-test$(EXEEXT) is-jump-test$(EXEEXT) \ - is-lws-test$(EXEEXT) is-mac-test$(EXEEXT) is-mul-test$(EXEEXT) \ - is-ror-test$(EXEEXT) is-spr-test$(EXEEXT) $(am__EXEEXT_1) +check_PROGRAMS = is-add-test$(EXEEXT) is-and-test$(EXEEXT) \ + is-div-test$(EXEEXT) is-find-test$(EXEEXT) \ + is-jump-test$(EXEEXT) is-lws-test$(EXEEXT) \ + is-mac-test$(EXEEXT) is-mul-test$(EXEEXT) is-or-test$(EXEEXT) \ + is-ror-test$(EXEEXT) is-shift-test$(EXEEXT) \ + is-spr-test$(EXEEXT) is-sub-test$(EXEEXT) is-xor-test$(EXEEXT) \ + $(am__EXEEXT_1) subdir = inst-set-test DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 @@ -92,6 +95,12 @@ is_add_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ $(is_add_test_LDFLAGS) $(LDFLAGS) -o $@ +am_is_and_test_OBJECTS = is-and-test.$(OBJEXT) +is_and_test_OBJECTS = $(am_is_and_test_OBJECTS) +is_and_test_DEPENDENCIES = inst-set-test.lo +is_and_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(is_and_test_LDFLAGS) $(LDFLAGS) -o $@ am_is_div_test_OBJECTS = is-div-test.$(OBJEXT) is_div_test_OBJECTS = $(am_is_div_test_OBJECTS) is_div_test_DEPENDENCIES = inst-set-test.lo @@ -128,6 +137,12 @@ is_mul_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ $(is_mul_test_LDFLAGS) $(LDFLAGS) -o $@ +am_is_or_test_OBJECTS = is-or-test.$(OBJEXT) +is_or_test_OBJECTS = $(am_is_or_test_OBJECTS) +is_or_test_DEPENDENCIES = inst-set-test.lo +is_or_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(is_or_test_LDFLAGS) $(LDFLAGS) -o $@ am_is_ror_test_OBJECTS = is-ror-test.$(OBJEXT) is_ror_test_OBJECTS = $(am_is_ror_test_OBJECTS) is_ror_test_DEPENDENCIES = inst-set-test.lo @@ -134,6 +149,12 @@ is_ror_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ $(is_ror_test_LDFLAGS) $(LDFLAGS) -o $@ +am_is_shift_test_OBJECTS = is-shift-test.$(OBJEXT) +is_shift_test_OBJECTS = $(am_is_shift_test_OBJECTS) +is_shift_test_DEPENDENCIES = inst-set-test.lo +is_shift_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(is_shift_test_LDFLAGS) $(LDFLAGS) -o $@ am_is_spr_test_OBJECTS = is-spr-test.$(OBJEXT) is_spr_test_OBJECTS = $(am_is_spr_test_OBJECTS) is_spr_test_DEPENDENCIES = inst-set-test.lo @@ -140,6 +161,18 @@ is_spr_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ $(is_spr_test_LDFLAGS) $(LDFLAGS) -o $@ +am_is_sub_test_OBJECTS = is-sub-test.$(OBJEXT) +is_sub_test_OBJECTS = $(am_is_sub_test_OBJECTS) +is_sub_test_DEPENDENCIES = inst-set-test.lo +is_sub_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(is_sub_test_LDFLAGS) $(LDFLAGS) -o $@ +am_is_xor_test_OBJECTS = is-xor-test.$(OBJEXT) +is_xor_test_OBJECTS = $(am_is_xor_test_OBJECTS) +is_xor_test_DEPENDENCIES = inst-set-test.lo +is_xor_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(is_xor_test_LDFLAGS) $(LDFLAGS) -o $@ DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir) depcomp = $(SHELL) $(top_srcdir)/../../depcomp am__depfiles_maybe = depfiles @@ -159,17 +192,22 @@ --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \ $(LDFLAGS) -o $@ SOURCES = $(libinst_set_test_la_SOURCES) $(inst_set_test_old_SOURCES) \ - $(is_add_test_SOURCES) $(is_div_test_SOURCES) \ - $(is_find_test_SOURCES) $(is_jump_test_SOURCES) \ - $(is_lws_test_SOURCES) $(is_mac_test_SOURCES) \ - $(is_mul_test_SOURCES) $(is_ror_test_SOURCES) \ - $(is_spr_test_SOURCES) -DIST_SOURCES = $(libinst_set_test_la_SOURCES) \ - $(inst_set_test_old_SOURCES) $(is_add_test_SOURCES) \ + $(is_add_test_SOURCES) $(is_and_test_SOURCES) \ $(is_div_test_SOURCES) $(is_find_test_SOURCES) \ $(is_jump_test_SOURCES) $(is_lws_test_SOURCES) \ $(is_mac_test_SOURCES) $(is_mul_test_SOURCES) \ - $(is_ror_test_SOURCES) $(is_spr_test_SOURCES) + $(is_or_test_SOURCES) $(is_ror_test_SOURCES) \ + $(is_shift_test_SOURCES) $(is_spr_test_SOURCES) \ + $(is_sub_test_SOURCES) $(is_xor_test_SOURCES) +DIST_SOURCES = $(libinst_set_test_la_SOURCES) \ + $(inst_set_test_old_SOURCES) $(is_add_test_SOURCES) \ + $(is_and_test_SOURCES) $(is_div_test_SOURCES) \ + $(is_find_test_SOURCES) $(is_jump_test_SOURCES) \ + $(is_lws_test_SOURCES) $(is_mac_test_SOURCES) \ + $(is_mul_test_SOURCES) $(is_or_test_SOURCES) \ + $(is_ror_test_SOURCES) $(is_shift_test_SOURCES) \ + $(is_spr_test_SOURCES) $(is_sub_test_SOURCES) \ + $(is_xor_test_SOURCES) ETAGS = etags CTAGS = ctags DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) @@ -301,51 +339,76 @@ # The new instruction set tests. is_add_test_SOURCES = inst-set-test.h \ - is-add-test.S + is-add-test.S is_add_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld is_add_test_LDADD = inst-set-test.lo +is_and_test_SOURCES = inst-set-test.h \ + is-and-test.S + +is_and_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_and_test_LDADD = inst-set-test.lo is_div_test_SOURCES = inst-set-test.h \ - is-div-test.S + is-div-test.S is_div_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld is_div_test_LDADD = inst-set-test.lo is_find_test_SOURCES = inst-set-test.h \ - is-find-test.S + is-find-test.S is_find_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld is_find_test_LDADD = inst-set-test.lo is_jump_test_SOURCES = inst-set-test.h \ - is-jump-test.S + is-jump-test.S is_jump_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld is_jump_test_LDADD = inst-set-test.lo is_lws_test_SOURCES = inst-set-test.h \ - is-lws-test.S + is-lws-test.S is_lws_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld is_lws_test_LDADD = inst-set-test.lo is_mac_test_SOURCES = inst-set-test.h \ - is-mac-test.S + is-mac-test.S is_mac_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld is_mac_test_LDADD = inst-set-test.lo is_mul_test_SOURCES = inst-set-test.h \ - is-mul-test.S + is-mul-test.S is_mul_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld is_mul_test_LDADD = inst-set-test.lo +is_or_test_SOURCES = inst-set-test.h \ + is-or-test.S + +is_or_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_or_test_LDADD = inst-set-test.lo is_ror_test_SOURCES = inst-set-test.h \ - is-ror-test.S + is-ror-test.S is_ror_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld is_ror_test_LDADD = inst-set-test.lo +is_shift_test_SOURCES = inst-set-test.h \ + is-shift-test.S + +is_shift_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_shift_test_LDADD = inst-set-test.lo is_spr_test_SOURCES = inst-set-test.h \ - is-spr-test.S + is-spr-test.S is_spr_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld is_spr_test_LDADD = inst-set-test.lo +is_sub_test_SOURCES = inst-set-test.h \ + is-sub-test.S +is_sub_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_sub_test_LDADD = inst-set-test.lo +is_xor_test_SOURCES = inst-set-test.h \ + is-xor-test.S + +is_xor_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_xor_test_LDADD = inst-set-test.lo + # The old test which builds with warnings and runs with errors inst_set_test_old_SOURCES = inst-set-test-old.c inst_set_test_old_LDFLAGS = -T$(srcdir)/../default.ld @@ -412,6 +475,9 @@ is-add-test$(EXEEXT): $(is_add_test_OBJECTS) $(is_add_test_DEPENDENCIES) @rm -f is-add-test$(EXEEXT) $(is_add_test_LINK) $(is_add_test_OBJECTS) $(is_add_test_LDADD) $(LIBS) +is-and-test$(EXEEXT): $(is_and_test_OBJECTS) $(is_and_test_DEPENDENCIES) + @rm -f is-and-test$(EXEEXT) + $(is_and_test_LINK) $(is_and_test_OBJECTS) $(is_and_test_LDADD) $(LIBS) is-div-test$(EXEEXT): $(is_div_test_OBJECTS) $(is_div_test_DEPENDENCIES) @rm -f is-div-test$(EXEEXT) $(is_div_test_LINK) $(is_div_test_OBJECTS) $(is_div_test_LDADD) $(LIBS) @@ -430,12 +496,24 @@ is-mul-test$(EXEEXT): $(is_mul_test_OBJECTS) $(is_mul_test_DEPENDENCIES) @rm -f is-mul-test$(EXEEXT) $(is_mul_test_LINK) $(is_mul_test_OBJECTS) $(is_mul_test_LDADD) $(LIBS) +is-or-test$(EXEEXT): $(is_or_test_OBJECTS) $(is_or_test_DEPENDENCIES) + @rm -f is-or-test$(EXEEXT) + $(is_or_test_LINK) $(is_or_test_OBJECTS) $(is_or_test_LDADD) $(LIBS) is-ror-test$(EXEEXT): $(is_ror_test_OBJECTS) $(is_ror_test_DEPENDENCIES) @rm -f is-ror-test$(EXEEXT) $(is_ror_test_LINK) $(is_ror_test_OBJECTS) $(is_ror_test_LDADD) $(LIBS) +is-shift-test$(EXEEXT): $(is_shift_test_OBJECTS) $(is_shift_test_DEPENDENCIES) + @rm -f is-shift-test$(EXEEXT) + $(is_shift_test_LINK) $(is_shift_test_OBJECTS) $(is_shift_test_LDADD) $(LIBS) is-spr-test$(EXEEXT): $(is_spr_test_OBJECTS) $(is_spr_test_DEPENDENCIES) @rm -f is-spr-test$(EXEEXT) $(is_spr_test_LINK) $(is_spr_test_OBJECTS) $(is_spr_test_LDADD) $(LIBS) +is-sub-test$(EXEEXT): $(is_sub_test_OBJECTS) $(is_sub_test_DEPENDENCIES) + @rm -f is-sub-test$(EXEEXT) + $(is_sub_test_LINK) $(is_sub_test_OBJECTS) $(is_sub_test_LDADD) $(LIBS) +is-xor-test$(EXEEXT): $(is_xor_test_OBJECTS) $(is_xor_test_DEPENDENCIES) + @rm -f is-xor-test$(EXEEXT) + $(is_xor_test_LINK) $(is_xor_test_OBJECTS) $(is_xor_test_LDADD) $(LIBS) mostlyclean-compile: -rm -f *.$(OBJEXT) @@ -446,6 +524,7 @@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/inst-set-test-old.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/inst-set-test.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-add-test.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-and-test.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-div-test.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-find-test.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-jump-test.Po@am__quote@ @@ -452,8 +531,12 @@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-lws-test.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-mac-test.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-mul-test.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-or-test.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-ror-test.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-shift-test.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-spr-test.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-sub-test.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-xor-test.Po@am__quote@ .S.o: @am__fastdepCCAS_TRUE@ $(CPPASCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
/test-code-or1k/inst-set-test/is-and-test.S
0,0 → 1,237
/* is-and-test.S. l.and and l.andi instruction test of Or1ksim
*
* Copyright (C) 1999-2006 OpenCores
* Copyright (C) 2010 Embecosm Limited
*
* Contributors various OpenCores participants
* Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
*
* This file is part of OpenRISC 1000 Architectural Simulator.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 3 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program. If not, see <http: www.gnu.org/licenses/>.
*/
 
/* ----------------------------------------------------------------------------
* Coding conventions are described in inst-set-test.S
* ------------------------------------------------------------------------- */
 
/* ----------------------------------------------------------------------------
* Test coverage
*
* The l.and and l.andi instructions should never set the carry and overflow
* flags.
*
* Problems in this area were reported in Bugs 1782, 1783 and 1784. Having
* fixed the problem, this is (in good software engineering style), a
* regression test to go with the fix.
*
* This is not a comprehensive test of any instruction (yet).
*
* Of course what is really needed is a comprehensive instruction test...
* ------------------------------------------------------------------------- */
 
 
#include "inst-set-test.h"
 
/* ----------------------------------------------------------------------------
* A macro to carry out a test of bitwise AND in registers
*
* This opcode should never set the flags. Result is compared with the native
* computed value.
*
* Arguments
* op1: First operand value
* op2: Second operand value
* ------------------------------------------------------------------------- */
#define TEST_AND(op1, op2) \
l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\
LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\
l.and r3,r3,r2 ;\
l.mtspr r0,r3,SPR_SR ;\
;\
LOAD_CONST (r5,op1) /* Load operands */ ;\
LOAD_CONST (r6,op2) ;\
l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\
50: l.and r4,r5,r6 ;\
l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\
l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\
PUSH (r5) /* Save EPCR for later */ ;\
PUSH (r2) /* Save SR for later */ ;\
PUSH (r4) /* Save result for later */ ;\
;\
PUTS (" 0x") ;\
PUTH (op1) ;\
PUTS (" & 0x") ;\
PUTH (op2) ;\
PUTS (" = 0x") ;\
PUTH (op1 & op2) ;\
PUTS (": ") ;\
POP (r4) ;\
CHECK_RES1 (r4, op1 & op2) ;\
;\
POP(r2) /* Retrieve SR */ ;\
PUSH(r2) ;\
LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
CHECK_FLAG ("- carry flag set: ", FALSE) ;\
;\
POP(r2) /* Retrieve SR */ ;\
LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
CHECK_FLAG ("- overflow flag set: ", FALSE) ;\
;\
POP (r2) /* Retrieve EPCR */ ;\
LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
l.bnf 51f ;\
;\
PUTS (" - exception triggered: TRUE\n") ;\
l.j 52f ;\
l.nop ;\
;\
51: PUTS (" - exception triggered: FALSE\n") ;\
52:
 
 
/* ----------------------------------------------------------------------------
* A macro to carry out a test of bitwise AND with an immediate operand
*
* This opcode should never set the flags. Result is compared with the native
* computed value.
*
* Arguments
* op1: First operand value
* op2: Second operand value
* ------------------------------------------------------------------------- */
#define TEST_ANDI(op1, op2) \
l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\
LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\
l.and r3,r3,r2 ;\
l.mtspr r0,r3,SPR_SR ;\
;\
LOAD_CONST (r5,op1) /* Load operands */ ;\
l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\
53: l.andi r4,r5,op2 ;\
l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\
l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\
PUSH (r5) /* Save EPCR for later */ ;\
PUSH (r2) /* Save SR for later */ ;\
PUSH (r4) /* Save result for later */ ;\
;\
PUTS (" 0x") ;\
PUTH (op1) ;\
PUTS (" & 0x") ;\
PUTHH (op2) ;\
PUTS (" = 0x") ;\
PUTH (op1 & op2) ;\
PUTS (": ") ;\
POP (r4) ;\
CHECK_RES1 (r4, op1 & op2) ;\
;\
POP(r2) /* Retrieve SR */ ;\
PUSH(r2) ;\
LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
CHECK_FLAG ("- carry flag set: ", FALSE) ;\
;\
POP(r2) /* Retrieve SR */ ;\
LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
CHECK_FLAG ("- overflow flag set: ", FALSE) ;\
;\
POP (r2) /* Retrieve EPCR */ ;\
LOAD_CONST (r4, 53b) /* The opcode of interest */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
l.bnf 54f ;\
;\
PUTS (" - exception triggered: TRUE\n") ;\
l.j 55f ;\
l.nop ;\
;\
54: PUTS (" - exception triggered: FALSE\n") ;\
55:
 
 
/* ----------------------------------------------------------------------------
* Start of code
* ------------------------------------------------------------------------- */
.section .text
.global _start
_start:
/* Always set OVE. We should never trigger an exception, even if this
bit is set. */
l.mfspr r3,r0,SPR_SR
LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */
l.or r3,r3,r2
l.mtspr r0,r3,SPR_SR
LOAD_STR (r3, " ** OVE flag set **\n")
l.jal _puts
l.nop
 
/* ----------------------------------------------------------------------------
* Test of and, l.and
* ------------------------------------------------------------------------- */
_and:
LOAD_STR (r3, "l.and\n")
l.jal _puts
l.nop
 
/* Test a range of operands */
TEST_AND (0x00000000, 0x00000000)
TEST_AND (0xffffffff, 0xffffffff)
TEST_AND (0xaaaaaaaa, 0x00000000)
TEST_AND (0xaaaaaaaa, 0xaaaaaaaa)
TEST_AND (0x55555555, 0x00000000)
TEST_AND (0x55555555, 0x55555555)
TEST_AND (0xaaaaaaaa, 0x55555555)
TEST_AND (0x4c70f07c, 0xb38f0f83)
TEST_AND (0x4c70f07c, 0xc4c70f07)
TEST_AND (0xb38f0f83, 0x38f0f83b)
 
/* ----------------------------------------------------------------------------
* Test of and with immediate half word, l.andi
* ------------------------------------------------------------------------- */
_andi:
LOAD_STR (r3, "l.andi\n")
l.jal _puts
l.nop
 
/* Test a range of operands */
TEST_ANDI (0x00000000, 0x0000)
TEST_ANDI (0xffffffff, 0xffff)
TEST_ANDI (0xaaaaaaaa, 0x0000)
TEST_ANDI (0xaaaaaaaa, 0xaaaa)
TEST_ANDI (0x55555555, 0x0000)
TEST_ANDI (0x55555555, 0x5555)
TEST_ANDI (0xaaaaaaaa, 0x5555)
TEST_ANDI (0x4c70f07c, 0x0f83)
TEST_ANDI (0x4c70f07c, 0x0f07)
TEST_ANDI (0xb38f0f83, 0xf83b)
 
/* ----------------------------------------------------------------------------
* All done
* ------------------------------------------------------------------------- */
_exit:
LOAD_STR (r3, "Test completed\n")
l.jal _puts
l.nop
 
TEST_EXIT
test-code-or1k/inst-set-test/is-and-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: test-code-or1k/inst-set-test/is-xor-test.S =================================================================== --- test-code-or1k/inst-set-test/is-xor-test.S (nonexistent) +++ test-code-or1k/inst-set-test/is-xor-test.S (revision 124) @@ -0,0 +1,256 @@ +/* is-xor-test.S. l.xor and l.xori instruction test of Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * Test coverage + * + * The l.xor and l.xori instructions should never set the carry and overflow + * flags. + * + * Problems in this area were reported in Bugs 1782, 1783 and 1784. Having + * fixed the problem, this is (in good software engineering style), a + * regression test to go with the fix. + * + * This is not a comprehensive test of any instruction (yet). + * + * Of course what is really needed is a comprehensive instruction test... + * ------------------------------------------------------------------------- */ + + +#include "inst-set-test.h" + +/* A macro to sign extend a 16-bit value */ +#define SE(v) (v | ((v & 0x8000) << 1) | \ + ((v & 0x8000) << 2) | \ + ((v & 0x8000) << 3) | \ + ((v & 0x8000) << 4) | \ + ((v & 0x8000) << 5) | \ + ((v & 0x8000) << 6) | \ + ((v & 0x8000) << 7) | \ + ((v & 0x8000) << 8) | \ + ((v & 0x8000) << 9) | \ + ((v & 0x8000) << 10) | \ + ((v & 0x8000) << 11) | \ + ((v & 0x8000) << 12) | \ + ((v & 0x8000) << 13) | \ + ((v & 0x8000) << 14) | \ + ((v & 0x8000) << 15) | \ + ((v & 0x8000) << 16) ) + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of bitwise XOR in registers + * + * This opcode should never set the flags. Result is compared with the native + * computed value. + * + * Arguments + * op1: First operand value + * op2: Second operand value + * ------------------------------------------------------------------------- */ +#define TEST_XOR(op1, op2) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + LOAD_CONST (r6,op2) ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +50: l.xor r4,r5,r6 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" ^ 0x") ;\ + PUTH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (op1 ^ op2) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, op1 ^ op2) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 51f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 52f ;\ + l.nop ;\ + ;\ +51: PUTS (" - exception triggered: FALSE\n") ;\ +52: + + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of bitwise XOR with an immediate operand + * + * This opcode should never set the flags. Result is compared with the native + * computed value. Note that the OR1K architecture specfies that the immediate + * operand is sign-extended, not zero-extended. + * + * Arguments + * op1: First operand value + * op2: Second operand value + * ------------------------------------------------------------------------- */ +#define TEST_XORI(op1, op2) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +53: l.xori r4,r5,op2 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" ^ 0x") ;\ + PUTHH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (op1 ^ SE (op2)) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, op1 ^ SE (op2)) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 53b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 54f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 55f ;\ + l.nop ;\ + ;\ +54: PUTS (" - exception triggered: FALSE\n") ;\ +55: + + +/* ---------------------------------------------------------------------------- + * Start of code + * ------------------------------------------------------------------------- */ + .section .text + .global _start +_start: + /* Always set OVE. We should never trigger an exception, even if this + bit is set. */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */ + l.or r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag set **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * Test of xor, l.xor + * ------------------------------------------------------------------------- */ +_xor: + LOAD_STR (r3, "l.xor\n") + l.jal _puts + l.nop + + /* Test a range of operands */ + TEST_XOR (0x00000000, 0x00000000) + TEST_XOR (0xffffffff, 0xffffffff) + TEST_XOR (0xaaaaaaaa, 0x00000000) + TEST_XOR (0xaaaaaaaa, 0xaaaaaaaa) + TEST_XOR (0x55555555, 0x00000000) + TEST_XOR (0x55555555, 0x55555555) + TEST_XOR (0xaaaaaaaa, 0x55555555) + TEST_XOR (0x4c70f07c, 0xb38f0f83) + TEST_XOR (0x4c70f07c, 0xc4c70f07) + TEST_XOR (0xb38f0f83, 0x38f0f83b) + +/* ---------------------------------------------------------------------------- + * Test of xor with immediate half word, l.xori + * ------------------------------------------------------------------------- */ +_xori: + LOAD_STR (r3, "l.xori\n") + l.jal _puts + l.nop + + /* Test a range of operands */ + TEST_XORI (0x00000000, 0x0000) + TEST_XORI (0xffffffff, 0xffff) + TEST_XORI (0xaaaaaaaa, 0x0000) + TEST_XORI (0xaaaaaaaa, 0xaaaa) + TEST_XORI (0x55555555, 0x0000) + TEST_XORI (0x55555555, 0x5555) + TEST_XORI (0xaaaaaaaa, 0x5555) + TEST_XORI (0x4c70f07c, 0x0f83) + TEST_XORI (0x4c70f07c, 0x0f07) + TEST_XORI (0xb38f0f83, 0xf83b) + +/* ---------------------------------------------------------------------------- + * All done + * ------------------------------------------------------------------------- */ +_exit: + LOAD_STR (r3, "Test completed\n") + l.jal _puts + l.nop + + TEST_EXIT
test-code-or1k/inst-set-test/is-xor-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: test-code-or1k/inst-set-test/is-shift-test.S =================================================================== --- test-code-or1k/inst-set-test/is-shift-test.S (nonexistent) +++ test-code-or1k/inst-set-test/is-shift-test.S (revision 124) @@ -0,0 +1,378 @@ +/* is-shift-test.S. shift instructions test of Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * Test coverage + * + * The shift instructions should never set the carry and overflow flags. + * + * Problems in this area were reported in Bugs 1782, 1783 and 1784. Having + * fixed the problem, this is (in good software engineering style), a + * regression test to go with the fix. + * + * This is not a comprehensive test of any instruction (yet). + * + * Of course what is really needed is a comprehensive instruction test... + * ------------------------------------------------------------------------- */ + + +#include "inst-set-test.h" + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of shift in registers + * + * This opcode should never set the flags. + * + * Arguments + * opc: The operand + * op1: First operand value + * op2: Second operand value + * res: The expected result + * ------------------------------------------------------------------------- */ +#define TEST_SHIFT(opc, op1, op2, res) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + LOAD_CONST (r6,op2) ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +50: opc r4,r5,r6 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" shifted by 0x") ;\ + PUTH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (res) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, res) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 51f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 52f ;\ + l.nop ;\ + ;\ +51: PUTS (" - exception triggered: FALSE\n") ;\ +52: + + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of shift with an immediate operand + * + * This opcode should never set the flags. + * + * Arguments + * opc: The operand + * op1: First operand value + * op2: Second operand value + * res: The expected result + * ------------------------------------------------------------------------- */ +#define TEST_SHIFTI(opc, op1, op2, res) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +53: opc r4,r5,op2 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" shifted by 0x") ;\ + PUTHH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (res) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, res) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 53b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 54f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 55f ;\ + l.nop ;\ + ;\ +54: PUTS (" - exception triggered: FALSE\n") ;\ +55: + + +/* ---------------------------------------------------------------------------- + * Start of code + * ------------------------------------------------------------------------- */ + .section .text + .global _start +_start: + /* Always set OVE. We should never trigger an exception, even if this + bit is set. */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */ + l.or r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag set **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * Test of shift left logical, l.sll + * ------------------------------------------------------------------------- */ +_sll: + LOAD_STR (r3, "l.sll\n") + l.jal _puts + l.nop + + /* Shift left by zero. */ + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00000000, 0xb38f0f83) + + /* Shift left by amounts in the 1-31 range */ + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00000001, 0x671e1f06) + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00000004, 0x38f0f830) + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00000010, 0x0f830000) + TEST_SHIFT (l.sll, 0xb38f0f83, 0x0000001f, 0x80000000) + + /* Shift left by larger amounts - should be masked. */ + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00000021, 0x671e1f06) + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00002224, 0x38f0f830) + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00f789f0, 0x0f830000) + TEST_SHIFT (l.sll, 0xb38f0f83, 0xffffffff, 0x80000000) + +/* ---------------------------------------------------------------------------- + * Test of shift left logical with immediate, l.slli + * ------------------------------------------------------------------------- */ +_slli: + LOAD_STR (r3, "l.slli\n") + l.jal _puts + l.nop + + /* Shift left by zero. */ + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0000, 0xb38f0f83) + + /* Shift left by amounts in the 1-31 range */ + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0001, 0x671e1f06) + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0004, 0x38f0f830) + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0010, 0x0f830000) + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x001f, 0x80000000) + + /* Shift left by larger amounts - should be masked. */ + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0021, 0x671e1f06) + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0024, 0x38f0f830) + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0030, 0x0f830000) + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x003f, 0x80000000) + +/* ---------------------------------------------------------------------------- + * Test of shift right arithmetic, l.sra + * ------------------------------------------------------------------------- */ +_sra: + LOAD_STR (r3, "l.sra\n") + l.jal _puts + l.nop + + /* Shift right by zero. */ + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00000000, 0xb38f0f83) + + /* Shift right by amounts in the 1-31 range */ + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00000001, 0xd9c787c1) + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00000004, 0xfb38f0f8) + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00000010, 0xffffb38f) + TEST_SHIFT (l.sra, 0xb38f0f83, 0x0000001f, 0xffffffff) + + TEST_SHIFT (l.sra, 0x4c70f07c, 0x00000001, 0x2638783e) + TEST_SHIFT (l.sra, 0x4c70f07c, 0x00000004, 0x04c70f07) + TEST_SHIFT (l.sra, 0x4c70f07c, 0x00000010, 0x00004c70) + TEST_SHIFT (l.sra, 0x4c70f07c, 0x0000001f, 0x00000000) + + /* Shift right by larger amounts - should be masked. */ + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00000021, 0xd9c787c1) + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00002224, 0xfb38f0f8) + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00f789f0, 0xffffb38f) + TEST_SHIFT (l.sra, 0xb38f0f83, 0xffffffff, 0xffffffff) + + TEST_SHIFT (l.sra, 0x4c70f07c, 0x00000021, 0x2638783e) + TEST_SHIFT (l.sra, 0x4c70f07c, 0x00002224, 0x04c70f07) + TEST_SHIFT (l.sra, 0x4c70f07c, 0x00f789f0, 0x00004c70) + TEST_SHIFT (l.sra, 0x4c70f07c, 0xffffffff, 0x00000000) + + +/* ---------------------------------------------------------------------------- + * Test of shift right arithmetic with immediate, l.srai + * ------------------------------------------------------------------------- */ +_srai: + LOAD_STR (r3, "l.srai\n") + l.jal _puts + l.nop + + /* Shift right by zero. */ + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0000, 0xb38f0f83) + + /* Shift right by amounts in the 1-31 range */ + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0001, 0xd9c787c1) + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0004, 0xfb38f0f8) + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0010, 0xffffb38f) + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x001f, 0xffffffff) + + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x0001, 0x2638783e) + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x0004, 0x04c70f07) + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x0010, 0x00004c70) + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x001f, 0x00000000) + + /* Shift right by larger amounts - should be masked. */ + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0021, 0xd9c787c1) + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0024, 0xfb38f0f8) + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0030, 0xffffb38f) + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x003f, 0xffffffff) + + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x0021, 0x2638783e) + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x0024, 0x04c70f07) + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x0030, 0x00004c70) + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x003f, 0x00000000) + +/* ---------------------------------------------------------------------------- + * Test of shift right logical, l.srl + * ------------------------------------------------------------------------- */ +_srl: + LOAD_STR (r3, "l.srl\n") + l.jal _puts + l.nop + + /* Shift right by zero. */ + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00000000, 0xb38f0f83) + + /* Shift right by amounts in the 1-31 range */ + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00000001, 0x59c787c1) + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00000004, 0x0b38f0f8) + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00000010, 0x0000b38f) + TEST_SHIFT (l.srl, 0xb38f0f83, 0x0000001f, 0x00000001) + + TEST_SHIFT (l.srl, 0x4c70f07c, 0x00000001, 0x2638783e) + TEST_SHIFT (l.srl, 0x4c70f07c, 0x00000004, 0x04c70f07) + TEST_SHIFT (l.srl, 0x4c70f07c, 0x00000010, 0x00004c70) + TEST_SHIFT (l.srl, 0x4c70f07c, 0x0000001f, 0x00000000) + + /* Shift right by larger amounts - should be masked. */ + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00000021, 0x59c787c1) + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00002224, 0x0b38f0f8) + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00f789f0, 0x0000b38f) + TEST_SHIFT (l.srl, 0xb38f0f83, 0xffffffff, 0x00000001) + + TEST_SHIFT (l.srl, 0x4c70f07c, 0x00000021, 0x2638783e) + TEST_SHIFT (l.srl, 0x4c70f07c, 0x00002224, 0x04c70f07) + TEST_SHIFT (l.srl, 0x4c70f07c, 0x00f789f0, 0x00004c70) + TEST_SHIFT (l.srl, 0x4c70f07c, 0xffffffff, 0x00000000) + + +/* ---------------------------------------------------------------------------- + * Test of shift right logical with immediate, l.srli + * ------------------------------------------------------------------------- */ +_srli: + LOAD_STR (r3, "l.srli\n") + l.jal _puts + l.nop + + /* Shift right by zero. */ + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0000, 0xb38f0f83) + + /* Shift right by amounts in the 1-31 range */ + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0001, 0x59c787c1) + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0004, 0x0b38f0f8) + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0010, 0x0000b38f) + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x001f, 0x00000001) + + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x0001, 0x2638783e) + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x0004, 0x04c70f07) + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x0010, 0x00004c70) + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x001f, 0x00000000) + + /* Shift right by larger amounts - should be masked. */ + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0021, 0x59c787c1) + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0024, 0x0b38f0f8) + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0030, 0x0000b38f) + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x003f, 0x00000001) + + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x0021, 0x2638783e) + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x0024, 0x04c70f07) + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x0030, 0x00004c70) + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x003f, 0x00000000) + +/* ---------------------------------------------------------------------------- + * All done + * ------------------------------------------------------------------------- */ +_exit: + LOAD_STR (r3, "Test completed\n") + l.jal _puts + l.nop + + TEST_EXIT
test-code-or1k/inst-set-test/is-shift-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: test-code-or1k/inst-set-test/is-or-test.S =================================================================== --- test-code-or1k/inst-set-test/is-or-test.S (nonexistent) +++ test-code-or1k/inst-set-test/is-or-test.S (revision 124) @@ -0,0 +1,237 @@ +/* is-or-test.S. l.or and l.ori instruction test of Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * Test coverage + * + * The l.or and l.ori instructions should never set the carry and overflow + * flags. + * + * Problems in this area were reported in Bugs 1782, 1783 and 1784. Having + * fixed the problem, this is (in good software engineering style), a + * regression test to go with the fix. + * + * This is not a comprehensive test of any instruction (yet). + * + * Of course what is really needed is a comprehensive instruction test... + * ------------------------------------------------------------------------- */ + + +#include "inst-set-test.h" + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of bitwise OR in registers + * + * This opcode should never set the flags. Result is compared with the native + * computed value. + * + * Arguments + * op1: First operand value + * op2: Second operand value + * ------------------------------------------------------------------------- */ +#define TEST_OR(op1, op2) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + LOAD_CONST (r6,op2) ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +50: l.or r4,r5,r6 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" | 0x") ;\ + PUTH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (op1 | op2) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, op1 | op2) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 51f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 52f ;\ + l.nop ;\ + ;\ +51: PUTS (" - exception triggered: FALSE\n") ;\ +52: + + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of bitwise OR with an immediate operand + * + * This opcode should never set the flags. Result is compared with the native + * computed value. + * + * Arguments + * op1: First operand value + * op2: Second operand value + * ------------------------------------------------------------------------- */ +#define TEST_ORI(op1, op2) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +53: l.ori r4,r5,op2 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" | 0x") ;\ + PUTHH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (op1 | op2) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, op1 | op2) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 53b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 54f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 55f ;\ + l.nop ;\ + ;\ +54: PUTS (" - exception triggered: FALSE\n") ;\ +55: + + +/* ---------------------------------------------------------------------------- + * Start of code + * ------------------------------------------------------------------------- */ + .section .text + .global _start +_start: + /* Always set OVE. We should never trigger an exception, even if this + bit is set. */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */ + l.or r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag set **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * Test of or, l.or + * ------------------------------------------------------------------------- */ +_or: + LOAD_STR (r3, "l.or\n") + l.jal _puts + l.nop + + /* Test a range of operands */ + TEST_OR (0x00000000, 0x00000000) + TEST_OR (0xffffffff, 0xffffffff) + TEST_OR (0xaaaaaaaa, 0x00000000) + TEST_OR (0xaaaaaaaa, 0xaaaaaaaa) + TEST_OR (0x55555555, 0x00000000) + TEST_OR (0x55555555, 0x55555555) + TEST_OR (0xaaaaaaaa, 0x55555555) + TEST_OR (0x4c70f07c, 0xb38f0f83) + TEST_OR (0x4c70f07c, 0xc4c70f07) + TEST_OR (0xb38f0f83, 0x38f0f83b) + +/* ---------------------------------------------------------------------------- + * Test of or with immediate half word, l.ori + * ------------------------------------------------------------------------- */ +_ori: + LOAD_STR (r3, "l.ori\n") + l.jal _puts + l.nop + + /* Test a range of operands */ + TEST_ORI (0x00000000, 0x0000) + TEST_ORI (0xffffffff, 0xffff) + TEST_ORI (0xaaaaaaaa, 0x0000) + TEST_ORI (0xaaaaaaaa, 0xaaaa) + TEST_ORI (0x55555555, 0x0000) + TEST_ORI (0x55555555, 0x5555) + TEST_ORI (0xaaaaaaaa, 0x5555) + TEST_ORI (0x4c70f07c, 0x0f83) + TEST_ORI (0x4c70f07c, 0x0f07) + TEST_ORI (0xb38f0f83, 0xf83b) + +/* ---------------------------------------------------------------------------- + * All done + * ------------------------------------------------------------------------- */ +_exit: + LOAD_STR (r3, "Test completed\n") + l.jal _puts + l.nop + + TEST_EXIT
test-code-or1k/inst-set-test/is-or-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: test-code-or1k/inst-set-test/Makefile.am =================================================================== --- test-code-or1k/inst-set-test/Makefile.am (revision 123) +++ test-code-or1k/inst-set-test/Makefile.am (revision 124) @@ -42,6 +42,7 @@ # The test programs check_PROGRAMS = is-add-test \ + is-and-test \ is-div-test \ is-find-test \ is-jump-test \ @@ -48,56 +49,85 @@ is-lws-test \ is-mac-test \ is-mul-test \ + is-or-test \ is-ror-test \ + is-shift-test \ is-spr-test \ + is-sub-test \ + is-xor-test \ $(INST_SET_TEST_OLD) # The new instruction set tests. -is_add_test_SOURCES = inst-set-test.h \ - is-add-test.S -is_add_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld -is_add_test_LDADD = inst-set-test.lo +is_add_test_SOURCES = inst-set-test.h \ + is-add-test.S +is_add_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_add_test_LDADD = inst-set-test.lo -is_div_test_SOURCES = inst-set-test.h \ - is-div-test.S -is_div_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld -is_div_test_LDADD = inst-set-test.lo +is_and_test_SOURCES = inst-set-test.h \ + is-and-test.S +is_and_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_and_test_LDADD = inst-set-test.lo -is_find_test_SOURCES = inst-set-test.h \ - is-find-test.S -is_find_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld -is_find_test_LDADD = inst-set-test.lo +is_div_test_SOURCES = inst-set-test.h \ + is-div-test.S +is_div_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_div_test_LDADD = inst-set-test.lo -is_jump_test_SOURCES = inst-set-test.h \ - is-jump-test.S -is_jump_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld -is_jump_test_LDADD = inst-set-test.lo +is_find_test_SOURCES = inst-set-test.h \ + is-find-test.S +is_find_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_find_test_LDADD = inst-set-test.lo -is_lws_test_SOURCES = inst-set-test.h \ - is-lws-test.S -is_lws_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld -is_lws_test_LDADD = inst-set-test.lo +is_jump_test_SOURCES = inst-set-test.h \ + is-jump-test.S +is_jump_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_jump_test_LDADD = inst-set-test.lo -is_mac_test_SOURCES = inst-set-test.h \ - is-mac-test.S -is_mac_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld -is_mac_test_LDADD = inst-set-test.lo +is_lws_test_SOURCES = inst-set-test.h \ + is-lws-test.S +is_lws_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_lws_test_LDADD = inst-set-test.lo -is_mul_test_SOURCES = inst-set-test.h \ - is-mul-test.S -is_mul_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld -is_mul_test_LDADD = inst-set-test.lo +is_mac_test_SOURCES = inst-set-test.h \ + is-mac-test.S +is_mac_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_mac_test_LDADD = inst-set-test.lo -is_ror_test_SOURCES = inst-set-test.h \ - is-ror-test.S -is_ror_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld -is_ror_test_LDADD = inst-set-test.lo +is_mul_test_SOURCES = inst-set-test.h \ + is-mul-test.S +is_mul_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_mul_test_LDADD = inst-set-test.lo -is_spr_test_SOURCES = inst-set-test.h \ - is-spr-test.S -is_spr_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld -is_spr_test_LDADD = inst-set-test.lo +is_or_test_SOURCES = inst-set-test.h \ + is-or-test.S +is_or_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_or_test_LDADD = inst-set-test.lo +is_ror_test_SOURCES = inst-set-test.h \ + is-ror-test.S +is_ror_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_ror_test_LDADD = inst-set-test.lo + +is_shift_test_SOURCES = inst-set-test.h \ + is-shift-test.S +is_shift_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_shift_test_LDADD = inst-set-test.lo + +is_spr_test_SOURCES = inst-set-test.h \ + is-spr-test.S +is_spr_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_spr_test_LDADD = inst-set-test.lo + +is_sub_test_SOURCES = inst-set-test.h \ + is-sub-test.S +is_sub_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_sub_test_LDADD = inst-set-test.lo + +is_xor_test_SOURCES = inst-set-test.h \ + is-xor-test.S +is_xor_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_xor_test_LDADD = inst-set-test.lo + # The old test which builds with warnings and runs with errors inst_set_test_old_SOURCES = inst-set-test-old.c
/test-code-or1k/ChangeLog
1,5 → 1,10
2010-06-15 Jeremy Bennett <jeremy.bennett@embecosm.com>
* inst-set-test/is-and-test.S: Created.
* inst-set-test/is-or-test.S: Created.
* inst-set-test/is-shift-test.S: Created.
* inst-set-test/is-spr-test.S: Created.
* inst-set-test/is-sub-test.S: Created.
* inst-set-test/is-xor-test.S: Created.
* inst-set-test/Makefile.am: Updated for new tests
* inst-set-test/Makefile.in: Regenerated.
 
/or1ksim.tests/inst-set-test.exp
254,6 → 254,96
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-add-test"
 
# Run the l.and, and l.andi tests
run_or1ksim "and-test" \
[list "! ** OVE flag set **" \
"!l.and" \
" 0x00000000 & 0x00000000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xffffffff & 0xffffffff = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa & 0x00000000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa & 0xaaaaaaaa = 0xaaaaaaaa: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 & 0x00000000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 & 0x55555555 = 0x55555555: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa & 0x55555555 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c & 0xb38f0f83 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c & 0xc4c70f07 = 0x44400004: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 & 0x38f0f83b = 0x30800803: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!l.andi" \
" 0x00000000 & 0x0000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xffffffff & 0xffff = 0x0000ffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa & 0x0000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa & 0xaaaa = 0x0000aaaa: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 & 0x0000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 & 0x5555 = 0x00005555: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa & 0x5555 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c & 0x0f83 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c & 0x0f07 = 0x00000004: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 & 0xf83b = 0x00000803: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!Test completed" \
"!report(0xdeaddead);" \
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-and-test"
 
# Run the l.div and l.divu test
run_or1ksim "div-test" \
[list "!l.div" \
865,6 → 955,96
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-mul-test"
 
# Run the l.or, and l.ori tests
run_or1ksim "or-test" \
[list "! ** OVE flag set **" \
"!l.or" \
" 0x00000000 | 0x00000000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xffffffff | 0xffffffff = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa | 0x00000000 = 0xaaaaaaaa: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa | 0xaaaaaaaa = 0xaaaaaaaa: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 | 0x00000000 = 0x55555555: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 | 0x55555555 = 0x55555555: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa | 0x55555555 = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c | 0xb38f0f83 = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c | 0xc4c70f07 = 0xccf7ff7f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 | 0x38f0f83b = 0xbbffffbb: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!l.ori" \
" 0x00000000 | 0x0000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xffffffff | 0xffff = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa | 0x0000 = 0xaaaaaaaa: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa | 0xaaaa = 0xaaaaaaaa: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 | 0x0000 = 0x55555555: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 | 0x5555 = 0x55555555: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa | 0x5555 = 0xaaaaffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c | 0x0f83 = 0x4c70ffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c | 0x0f07 = 0x4c70ff7f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 | 0xf83b = 0xb38fffbb: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!Test completed" \
"!report(0xdeaddead);" \
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-or-test"
 
# Run the l.ror test
run_or1ksim "ror-test" \
[list "!l.ror" \
946,3 → 1126,520
"!report(0xdeaddead);" \
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-spr-test"
 
# Run the shift tests
run_or1ksim "shift-test" \
[list "! ** OVE flag set **" \
"!l.sll" \
" 0xb38f0f83 shifted by 0x00000000 = 0xb38f0f83: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000001 = 0x671e1f06: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000004 = 0x38f0f830: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000010 = 0x0f830000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0000001f = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000021 = 0x671e1f06: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00002224 = 0x38f0f830: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00f789f0 = 0x0f830000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0xffffffff = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!l.slli" \
" 0xb38f0f83 shifted by 0x0000 = 0xb38f0f83: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0001 = 0x671e1f06: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0004 = 0x38f0f830: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0010 = 0x0f830000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x001f = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0021 = 0x671e1f06: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0024 = 0x38f0f830: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0030 = 0x0f830000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x003f = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!l.sra" \
" 0xb38f0f83 shifted by 0x00000000 = 0xb38f0f83: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000001 = 0xd9c787c1: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000004 = 0xfb38f0f8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000010 = 0xffffb38f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0000001f = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00000001 = 0x2638783e: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00000004 = 0x04c70f07: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00000010 = 0x00004c70: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0000001f = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000021 = 0xd9c787c1: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00002224 = 0xfb38f0f8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00f789f0 = 0xffffb38f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0xffffffff = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00000021 = 0x2638783e: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00002224 = 0x04c70f07: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00f789f0 = 0x00004c70: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0xffffffff = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!l.srai" \
" 0xb38f0f83 shifted by 0x0000 = 0xb38f0f83: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0001 = 0xd9c787c1: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0004 = 0xfb38f0f8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0010 = 0xffffb38f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x001f = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0001 = 0x2638783e: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0004 = 0x04c70f07: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0010 = 0x00004c70: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x001f = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0021 = 0xd9c787c1: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0024 = 0xfb38f0f8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0030 = 0xffffb38f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x003f = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0021 = 0x2638783e: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0024 = 0x04c70f07: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0030 = 0x00004c70: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x003f = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!l.srl" \
" 0xb38f0f83 shifted by 0x00000000 = 0xb38f0f83: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000001 = 0x59c787c1: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000004 = 0x0b38f0f8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000010 = 0x0000b38f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0000001f = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00000001 = 0x2638783e: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00000004 = 0x04c70f07: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00000010 = 0x00004c70: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0000001f = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000021 = 0x59c787c1: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00002224 = 0x0b38f0f8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00f789f0 = 0x0000b38f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0xffffffff = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00000021 = 0x2638783e: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00002224 = 0x04c70f07: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00f789f0 = 0x00004c70: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0xffffffff = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!l.srli" \
" 0xb38f0f83 shifted by 0x0000 = 0xb38f0f83: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0001 = 0x59c787c1: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0004 = 0x0b38f0f8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0010 = 0x0000b38f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x001f = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0001 = 0x2638783e: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0004 = 0x04c70f07: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0010 = 0x00004c70: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x001f = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0021 = 0x59c787c1: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0024 = 0x0b38f0f8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0030 = 0x0000b38f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x003f = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0021 = 0x2638783e: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0024 = 0x04c70f07: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0030 = 0x00004c70: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x003f = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!Test completed" \
"!report(0xdeaddead);" \
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-shift-test"
 
# Run the l.sub test
run_or1ksim "sub-test" \
[list "! ** OVE flag cleared **" \
"!l.sub" \
" 0x00000003 - 0x00000002 = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x00000001 - 0x00000002 = 0xffffffff: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x00000003 - 0x00000002 = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xfffffffd - 0xfffffffe = 0xffffffff: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xffffffff - 0xfffffffe = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x7fffffff - 0x3fffffff = 0x40000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x40000000 - 0x40000000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x3fffffff - 0x40000000 = 0xffffffff: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x40000000 - 0x3fffffff = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x80000000 - 0x7fffffff = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" - exception triggered: FALSE" \
" 0x7fffffff - 0x80000000 = 0xffffffff: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: TRUE" \
" - exception triggered: FALSE" \
"! ** OVE flag set **" \
" RANGE exception" \
" 0x80000000 - 0x7fffffff = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" - exception triggered: TRUE" \
" 0x3fffffff - 0x40000000 = 0xffffffff: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" RANGE exception" \
" 0x7fffffff - 0x80000000 = 0xffffffff: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: TRUE" \
" - exception triggered: TRUE" \
"! ** OVE flag cleared **" \
"!Test completed" \
"!report(0xdeaddead);" \
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-sub-test"
 
# Run the l.xor test
run_or1ksim "xor-test" \
[list "! ** OVE flag set **" \
"!l.xor" \
" 0x00000000 ^ 0x00000000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xffffffff ^ 0xffffffff = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa ^ 0x00000000 = 0xaaaaaaaa: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa ^ 0xaaaaaaaa = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 ^ 0x00000000 = 0x55555555: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 ^ 0x55555555 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa ^ 0x55555555 = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c ^ 0xb38f0f83 = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c ^ 0xc4c70f07 = 0x88b7ff7b: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 ^ 0x38f0f83b = 0x8b7ff7b8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!l.xori" \
" 0x00000000 ^ 0x0000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xffffffff ^ 0xffff = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa ^ 0x0000 = 0xaaaaaaaa: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa ^ 0xaaaa = 0x55550000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 ^ 0x0000 = 0x55555555: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 ^ 0x5555 = 0x55550000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa ^ 0x5555 = 0xaaaaffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c ^ 0x0f83 = 0x4c70ffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c ^ 0x0f07 = 0x4c70ff7b: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 ^ 0xf83b = 0x4c70f7b8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!Test completed" \
"!report(0xdeaddead);" \
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-xor-test"
/ChangeLog
1,6 → 1,6
2010-06-15 Jeremy Bennett <jeremy.bennett@embecosm.com>
* or1ksim.tests/inst-set-test.exp: Added tests for l.mfspr and
l.mtspr instructions.
l.mtspr, l.sub, logical and shift instructions.
 
2010-06-14 Jeremy Bennett <jeremy.bennett@embecosm.com>
* or1ksim.tests/inst-set-test.exp: Modified output from RANGE
/README
12,8 → 12,8
Tests are provided for the standalone simulator (or1ksim) and for the library
(libsim.a).
 
At the time of writing a total of 1,857 tests compile, run and pass. That
figure is broken down into 1,593 tests of the standalone simulator and 264
At the time of writing a total of 2,499 tests compile, run and pass. That
figure is broken down into 2,235 tests of the standalone simulator and 264
tests of the library
 
Configuration and make files are provided for further test programs. These
46,7 → 46,7
Working tests
=============
 
A total of 1,593 tests of standalone Or1ksim:
A total of 2,235 tests of standalone Or1ksim:
 
basic: 8 tests of a wide range of instructions and registers.
cache: 5 tests of the Or1ksim cache modeling
67,6 → 67,7
local-global: 1 test of C local and global variables.
inst-set-test: A collection of tests of individual instructions
is-add-test 213 tests of the l.add* instructions (Bugs 1771, 1776)
is-and-test 80 tests of the l.and* instructions (Bugs 1782-1784)
is-div-test: 101 tests of the l.div and l.divu instructions (Bug 1770).
is-find-test: 14 tests of the l.ff1 and l.fl1 instructions (Bug 1772).
is-jump-test: 27 tests of the jump instructions (Bug 1775).
73,8 → 74,12
is-lws-test: 13 tests of the l.lws instruction (Bug 1767).
is-mac-test: 189 tests of the MAC instructions (Bugs 1773, 1777).
is-mul-test: 186 tests of the l.mul* instructions (Bug 1774).
is-or-test 80 tests of the l.or* instructions (Bugs 1782-1784)
is-ror-test: 36 tests of the l.ror and l.rori instructions (Bug 1778).
is-shift-test: 344 tests of the shift instructions (Bug 1782-1784).
is-spr-test: 28 tests of the l.mfspr and l.mtspr instructions (Bug 1779).
is-sub-test 58 tests of the l.sub instruction (Bugs 1782-1784)
is-xor-test 80 tests of the l.xor* instructions (Bugs 1782-1784)
mem-test: 16 tests of simple memory access.
mmu: 110 tests of the MMU.
mul: 5 tests of the multiply functionality.

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